CHIPSET(0x15DD, RAVEN)
CHIPSET(0x15D8, RAVEN)
+CHIPSET(0x1636, RENOIR)
+
CHIPSET(0x738C, ARCTURUS)
CHIPSET(0x7388, ARCTURUS)
CHIPSET(0x738E, ARCTURUS)
#define AMDGPU_RAVEN_RANGE 0x01, 0x81
#define AMDGPU_RAVEN2_RANGE 0x81, 0xFF
+#define AMDGPU_RENOIR_RANGE 0x01, 0x91
#define AMDGPU_ARCTURUS_RANGE 0x32, 0xFF
#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
#define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2)
+#define ASICREV_IS_RENOIR(r) ASICREV_IS(r, RENOIR)
#define ASICREV_IS_ARCTURUS(r) ASICREV_IS(r, ARCTURUS)
m_settings.applyAliasFix = 1;
}
+ if (ASICREV_IS_RENOIR(uChipRevision))
+ {
+ m_settings.isRaven = 1;
+ }
+
m_settings.isDcn1 = m_settings.isRaven;
m_settings.metaBaseAlignFix = 1;
if (info->drm_minor >= 31 &&
(info->family == CHIP_RAVEN ||
- info->family == CHIP_RAVEN2)) {
+ info->family == CHIP_RAVEN2 ||
+ info->family == CHIP_RENOIR)) {
if (info->num_render_backends == 1)
info->use_display_dcc_unaligned = true;
else
case CHIP_VEGA20:
return "gfx906";
case CHIP_RAVEN2:
+ case CHIP_RENOIR:
return HAVE_LLVM >= 0x0800 ? "gfx909" : "gfx902";
case CHIP_ARCTURUS:
return "gfx908";
CHIP_VEGA20,
CHIP_RAVEN,
CHIP_RAVEN2,
+ CHIP_RENOIR,
CHIP_ARCTURUS,
CHIP_NAVI10,
CHIP_NAVI12,
sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
sscreen->info.family == CHIP_RAVEN;
sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2 ||
+ sscreen->info.family == CHIP_RENOIR ||
sscreen->info.chip_class >= GFX10;
sscreen->use_ngg = sscreen->info.chip_class >= GFX10;
sscreen->use_ngg_streamout = sscreen->info.chip_class >= GFX10;
(sscreen->info.family == CHIP_STONEY ||
sscreen->info.family == CHIP_VEGA12 ||
sscreen->info.family == CHIP_RAVEN ||
- sscreen->info.family == CHIP_RAVEN2);
+ sscreen->info.family == CHIP_RAVEN2 ||
+ sscreen->info.family == CHIP_RENOIR);
}
sscreen->dcc_msaa_allowed =
break;
case CHIP_RAVEN:
case CHIP_RAVEN2:
+ case CHIP_RENOIR:
case CHIP_NAVI10:
case CHIP_NAVI12:
pc_lines = 1024;