code-comments

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 652f5987a56db16cce1e331d7dc6ccd608617957..bd770a94863e68501943e01a406483b43e01a7f6 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -672,7 +672,8 @@ class NonProductionCore(ControlBase):
         # the detection of what shall be written to is based
         # on *issue*.  it is delayed by 1 cycle so that instructions
         # "addi 5,5,0x2" do not cause combinatorial loops due to
-        # fake-dependency on *themselves*
+        # fake-dependency on *themselves*.  this will totally fail
+        # spectacularly when doing multi-issue
         print ("write vector (for regread)", regfile, wvset)
         wviaddr_en = Signal(len(wvset), name="wv_issue_addr_en_"+name)
         issue_active = Signal(name="iactive_"+name)