hmmm sync-delay wport write and wen

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index aa63d6d949e04aee954ad8bae1fe3ddf0c6696cb..c1bbf7438664f65adb570f006b5fb085700c09d3 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -163,7 +163,7 @@ class NonProductionCore(Elaboratable):
                 # only if one FU actually requests (and is granted) the port
                 # will the write-enable be activated
                 with m.If(wrpick.en_o):
-                    comb += wport.wen.eq(write)
+                    sync += wport.wen.eq(write)
 
                 # connect up the FU req/go signals and the reg-read to the FU
                 # these are arbitrated by Data.ok signals
@@ -187,7 +187,7 @@ class NonProductionCore(Elaboratable):
                     wsigs.append(dest)
 
                 # here is where we create the Write Broadcast Bus. simple, eh?
-                comb += wport.data_i.eq(ortreereduce(wsigs, "data"))
+                sync += wport.data_i.eq(ortreereduce(wsigs, "data"))
 
         return m