return SelectableInt(exts(value.value, value.bits) & ((1 << 64)-1), 64)
+def EXTS128(value):
+ """ extends sign bit out from current MSB to 128 bits
+ """
+ assert isinstance(value, SelectableInt)
+ return SelectableInt(exts(value.value, value.bits) & ((1 << 128)-1), 128)
+
+
# signed version of MUL
def MULS(a, b):
if isinstance(b, int):
from soc.decoder.isa.caller import inject, instruction_info
from soc.decoder.helpers import (EXTS, EXTS64, EXTZ64, ROTL64, ROTL32, MASK,
ne, eq, gt, ge, lt, le, ltu, gtu, length,
- trunc_divs, trunc_rems, MULS, DIVS, MODS)
+ trunc_divs, trunc_rems, MULS, DIVS, MODS,
+ EXTS128)
from soc.decoder.selectable_int import SelectableInt
from soc.decoder.selectable_int import selectconcat as concat
from soc.decoder.orderedset import OrderedSet
class DivTestCases(TestAccumulatorBase):
+ def case_divdeu_regression(self):
+ lst = ["divdeu 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1
+ initial_regs[2] = 0x2
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divde_regression3(self):
+ lst = ["divde 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x8000000000000000
+ initial_regs[2] = 0xFFFFFFFFFFFFFFFF
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divwe_regression2(self):
+ lst = ["divwe 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x80000000
+ initial_regs[2] = 0xFFFFFFFF
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divde_regression2(self):
+ lst = ["divde 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1
+ initial_regs[2] = 0xfffffffffffffffe
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
def case_divde_regression(self):
lst = ["divde 3, 1, 2"]
initial_regs = [0] * 32