clear sel on loadstore

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index ffd6fec4f77096958c7c5792f2f99ff7fb2dc225..db05c3008946f585e380b725f2068276b136f6e0 100644 (file)
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -85,6 +85,7 @@ class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
                 m.d.sync += [
                     self.dbus.cyc.eq(0),
                     self.dbus.stb.eq(0),
+                    self.dbus.sel.eq(0),
                     self.m_ld_data_o.eq(self.dbus.dat_r)
                 ]
         with m.Elif((self.x_ld_i | self.x_st_i) &