# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
-# Authors: Steve Reinhardt
+# Authors: Nathan Binkert
+import imp
import os
import sys
-import zipfile
from os.path import basename
from os.path import join as joinpath
+from os.path import exists
+from os.path import isdir
+from os.path import isfile
import SCons
# Children need to see the environment
Export('env')
+def sort_list(_list):
+ """return a sorted copy of '_list'"""
+ if isinstance(_list, list):
+ _list = _list[:]
+ else:
+ _list = list(_list)
+ _list.sort()
+ return _list
+
+class PySourceFile(object):
+ def __init__(self, package, source):
+ filename = str(source)
+ pyname = basename(filename)
+ assert pyname.endswith('.py')
+ name = pyname[:-3]
+ path = package.split('.')
+ modpath = path
+ if name != '__init__':
+ modpath += [name]
+ modpath = '.'.join(modpath)
+
+ arcpath = package.split('.') + [ pyname + 'c' ]
+ arcname = joinpath(*arcpath)
+
+ self.source = source
+ self.pyname = pyname
+ self.srcpath = source.srcnode().abspath
+ self.package = package
+ self.modpath = modpath
+ self.arcname = arcname
+ self.filename = filename
+ self.compiled = File(filename + 'c')
+
########################################################################
-# Code for adding source files
+# Code for adding source files of various types
#
-sources = []
+cc_sources = []
def Source(source):
- if isinstance(source, SCons.Node.FS.File):
- sources.append(source)
- else:
- sources.append(File(source))
+ '''Add a C/C++ source file to the build'''
+ if not isinstance(source, SCons.Node.FS.File):
+ source = File(source)
-# Children should have access
-Export('Source')
+ cc_sources.append(source)
-########################################################################
-# Code for adding python objects
-#
py_sources = []
-py_source_packages = {}
def PySource(package, source):
+ '''Add a python source file to the named package'''
if not isinstance(source, SCons.Node.FS.File):
source = File(source)
- py_source_packages[source] = package
+
+ source = PySourceFile(package, source)
py_sources.append(source)
-sim_objects = []
+sim_objects_fixed = False
+sim_object_modfiles = set()
def SimObject(source):
+ '''Add a SimObject python file as a python source object and add
+ it to a list of sim object modules'''
+
+ if sim_objects_fixed:
+ raise AttributeError, "Too late to call SimObject now."
+
if not isinstance(source, SCons.Node.FS.File):
source = File(source)
+
PySource('m5.objects', source)
- modname = basename(str(source))
- sim_objects.append(modname)
+ modfile = basename(str(source))
+ assert modfile.endswith('.py')
+ modname = modfile[:-3]
+ sim_object_modfiles.add(modname)
swig_sources = []
-swig_source_packages = {}
def SwigSource(package, source):
+ '''Add a swig file to build'''
if not isinstance(source, SCons.Node.FS.File):
source = File(source)
- swig_source_packages[source] = package
- swig_sources.append(source)
+ val = source,package
+ swig_sources.append(val)
# Children should have access
+Export('Source')
Export('PySource')
Export('SimObject')
Export('SwigSource')
env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())])
########################################################################
+#
# Walk the tree and execute all SConscripts
#
scripts = []
if root == srcdir:
# we don't want to recurse back into this SConscript
continue
-
+
if 'SConscript' in files:
# strip off the srcdir part since scons will try to find the
# script in the build directory
########################################################################
#
-# Deal with python/swig, object code. Collect .py files and
-# generating a zip archive that is appended to the m5 binary.
+# Prevent any SimObjects from being added after this point, they
+# should all have been added in the SConscripts above
#
+sim_objects_fixed = True
-# Generate Python file that contains a dict specifying the current
-# build_env flags.
-def MakeDefinesPyFile(target, source, env):
- f = file(str(target[0]), 'w')
- print >>f, "m5_build_env = ", source[0]
- f.close()
+########################################################################
+#
+# Manually turn python/generate.py into a python module and import it
+#
+generate_file = File('python/generate.py')
+generate_module = imp.new_module('generate')
+sys.modules['generate'] = generate_module
+exec file(generate_file.srcnode().abspath, 'r') in generate_module.__dict__
+########################################################################
+#
+# build a generate
+#
+from generate import Generate
optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions])
-env.Command('python/m5/defines.py', Value(optionDict), MakeDefinesPyFile)
-PySource('m5', 'python/m5/defines.py')
+generate = Generate(py_sources, sim_object_modfiles, optionDict)
+m5 = generate.m5
+
+########################################################################
+#
+# calculate extra dependencies
+#
+module_depends = ["m5", "m5.SimObject", "m5.params"]
+module_depends = [ File(generate.py_modules[dep]) for dep in module_depends ]
+file_depends = [ generate_file ]
+depends = module_depends + file_depends
-def MakeInfoPyFile(target, source, env):
- f = file(str(target[0]), 'w')
- for src in source:
- data = ''.join(file(src.srcnode().abspath, 'r').xreadlines())
- print >>f, "%s = %s" % (src, repr(data))
- f.close()
+########################################################################
+#
+# Commands for the basic automatically generated python files
+#
+
+# Generate a file with all of the compile options in it
+env.Command('python/m5/defines.py', Value(optionDict),
+ generate.makeDefinesPyFile)
+PySource('m5', 'python/m5/defines.py')
+# Generate a file that wraps the basic top level files
env.Command('python/m5/info.py',
[ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ],
- MakeInfoPyFile)
+ generate.makeInfoPyFile)
PySource('m5', 'python/m5/info.py')
-def MakeObjectsInitFile(target, source, env):
- f = file(str(target[0]), 'w')
- print >>f, 'from m5.SimObject import *'
- for src_path in source:
- src_file = basename(src_path.get_contents())
- assert(src_file.endswith('.py'))
- src_module = src_file[:-3]
- print >>f, 'from %s import *' % src_module
- f.close()
-
+# Generate an __init__.py file for the objects package
env.Command('python/m5/objects/__init__.py',
- [ Value(o) for o in sim_objects],
- MakeObjectsInitFile)
+ [ Value(o) for o in sort_list(sim_object_modfiles) ],
+ generate.makeObjectsInitFile)
PySource('m5.objects', 'python/m5/objects/__init__.py')
+########################################################################
+#
+# Create all of the SimObject param headers and enum headers
+#
+
+# Generate all of the SimObject param struct header files
+params_hh_files = []
+for name,simobj in generate.sim_objects.iteritems():
+ extra_deps = [ File(generate.py_modules[simobj.__module__]) ]
+
+ hh_file = File('params/%s.hh' % name)
+ params_hh_files.append(hh_file)
+ env.Command(hh_file, Value(name), generate.createSimObjectParam)
+ env.Depends(hh_file, depends + extra_deps)
+
+# Generate any parameter header files needed
+for name,param in generate.params.iteritems():
+ if isinstance(param, m5.params.VectorParamDesc):
+ ext = 'vptype'
+ else:
+ ext = 'ptype'
+
+ i_file = File('params/%s_%s.i' % (name, ext))
+ env.Command(i_file, Value(name), generate.createSwigParam)
+ env.Depends(i_file, depends)
+
+# Generate all enum header files
+for name,enum in generate.enums.iteritems():
+ extra_deps = [ File(generate.py_modules[enum.__module__]) ]
+
+ cc_file = File('enums/%s.cc' % name)
+ env.Command(cc_file, Value(name), generate.createEnumStrings)
+ env.Depends(cc_file, depends + extra_deps)
+ Source(cc_file)
+
+ hh_file = File('enums/%s.hh' % name)
+ env.Command(hh_file, Value(name), generate.createEnumParam)
+ env.Depends(hh_file, depends + extra_deps)
+
+# Build the big monolithic swigged params module (wraps all SimObject
+# param structs and enum structs)
+params_file = File('params/params.i')
+names = sort_list(generate.sim_objects.keys())
+env.Command(params_file, [ Value(v) for v in names ],
+ generate.buildParams)
+env.Depends(params_file, params_hh_files + depends)
+SwigSource('m5.objects', params_file)
+
+# Build all swig modules
swig_modules = []
-for source in swig_sources:
- source.rfile() # Hack to cause the symlink to the .i file to be created
- package = swig_source_packages[source]
+for source,package in swig_sources:
filename = str(source)
- module = basename(filename)
+ assert filename.endswith('.i')
- assert(module.endswith('.i'))
- module = module[:-2]
- cc_file = 'swig/%s_wrap.cc' % module
- py_file = 'm5/internal/%s.py' % module
+ base = '.'.join(filename.split('.')[:-1])
+ module = basename(base)
+ cc_file = base + '_wrap.cc'
+ py_file = base + '.py'
env.Command([cc_file, py_file], source,
'$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} '
'-o ${TARGETS[0]} $SOURCES')
env.Depends(py_file, source)
env.Depends(cc_file, source)
-
+
swig_modules.append(Value(module))
Source(cc_file)
PySource(package, py_file)
-def MakeSwigInit(target, source, env):
- f = file(str(target[0]), 'w')
- print >>f, 'extern "C" {'
- for module in source:
- print >>f, ' void init_%s();' % module.get_contents()
- print >>f, '}'
- print >>f, 'void init_swig() {'
- for module in source:
- print >>f, ' init_%s();' % module.get_contents()
- print >>f, '}'
- f.close()
-env.Command('python/swig/init.cc', swig_modules, MakeSwigInit)
-
-def CompilePyFile(target, source, env):
- import py_compile
- py_compile.compile(str(source[0]), str(target[0]))
+# Generate the main swig init file
+env.Command('swig/init.cc', swig_modules, generate.makeSwigInit)
+Source('swig/init.cc')
+# Build the zip file
py_compiled = []
-py_arcname = {}
py_zip_depends = []
for source in py_sources:
- filename = str(source)
- package = py_source_packages[source]
- arc_path = package.split('.') + [ basename(filename) + 'c' ]
- zip_path = [ 'zip' ] + arc_path
- arcname = joinpath(*arc_path)
- zipname = joinpath(*zip_path)
- f = File(zipname)
-
- env.Command(f, source, CompilePyFile)
- py_compiled.append(f)
- py_arcname[f] = arcname
+ env.Command(source.compiled, source.source, generate.compilePyFile)
+ py_compiled.append(source.compiled)
# make the zipfile depend on the archive name so that the archive
# is rebuilt if the name changes
- py_zip_depends.append(Value(arcname))
-
-# Action function to build the zip archive. Uses the PyZipFile module
-# included in the standard Python library.
-def buildPyZip(target, source, env):
- zf = zipfile.ZipFile(str(target[0]), 'w')
- for s in source:
- arcname = py_arcname[s]
- zipname = str(s)
- zf.write(zipname, arcname)
- zf.close()
+ py_zip_depends.append(Value(source.arcname))
# Add the zip file target to the environment.
-env.Command('m5py.zip', py_compiled, buildPyZip)
-env.Depends('m5py.zip', py_zip_depends)
+m5zip = File('m5py.zip')
+env.Command(m5zip, py_compiled, generate.buildPyZip)
+env.Depends(m5zip, py_zip_depends)
########################################################################
#
newEnv.Append(**kwargs)
exe = 'm5.' + label # final executable
bin = exe + '.bin' # executable w/o appended Python zip archive
- newEnv.Program(bin, make_objs(sources, newEnv))
+ newEnv.Program(bin, make_objs(cc_sources, newEnv))
if strip:
stripped_bin = bin + '.stripped'
if sys.platform == 'sunos5':
ccflags['prof'] = '-fast -g -pg'
else:
print 'Unknown compiler, please fix compiler options'
- Exit(1)
+ Exit(1)
makeEnv('debug', '.do',
CCFLAGS = Split(ccflags['debug']),
class AlphaDTB(AlphaTLB):
type = 'AlphaDTB'
+ cxx_namespace = 'AlphaISA'
+ cxx_class = 'DTB'
+
size = 64
class AlphaITB(AlphaTLB):
type = 'AlphaITB'
+ cxx_namespace = 'AlphaISA'
+ cxx_class = 'ITB'
+
size = 48
*
*/
-#include "arch/alpha/system.hh"
#include "arch/alpha/freebsd/system.hh"
+#include "arch/alpha/system.hh"
+#include "arch/isa_traits.hh"
+#include "arch/vtophys.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
-#include "arch/isa_traits.hh"
-#include "sim/builder.hh"
#include "sim/byteswap.hh"
-#include "arch/vtophys.hh"
#define TIMER_FREQUENCY 1193180
((FreebsdAlphaSystem *)tc->getSystemPtr())->doCalibrateClocks(tc);
}
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
-
- Param<Tick> boot_cpu_frequency;
- SimObjectParam<PhysicalMemory *> physmem;
- SimpleEnumParam<System::MemoryMode> mem_mode;
-
- Param<string> kernel;
- Param<string> console;
- Param<string> pal;
-
- Param<string> boot_osflags;
- Param<string> readfile;
- Param<string> symbolfile;
- Param<unsigned int> init_param;
-
- Param<uint64_t> system_type;
- Param<uint64_t> system_rev;
-
-END_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
-
- INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
- INIT_PARAM(physmem, "phsyical memory"),
- INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
- System::MemoryModeStrings),
- INIT_PARAM(kernel, "file that contains the kernel code"),
- INIT_PARAM(console, "file that contains the console code"),
- INIT_PARAM(pal, "file that contains palcode"),
- INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
- "a"),
- INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
- INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
- INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
- INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
- INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
-
-END_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
-
-CREATE_SIM_OBJECT(FreebsdAlphaSystem)
+FreebsdAlphaSystem *
+FreebsdAlphaSystemParams::create()
{
- AlphaSystem::Params *p = new AlphaSystem::Params;
- p->name = getInstanceName();
- p->boot_cpu_frequency = boot_cpu_frequency;
- p->physmem = physmem;
- p->mem_mode = mem_mode;
- p->kernel_path = kernel;
- p->console_path = console;
- p->palcode = pal;
- p->boot_osflags = boot_osflags;
- p->init_param = init_param;
- p->readfile = readfile;
- p->symbolfile = symbolfile;
- p->system_type = system_type;
- p->system_rev = system_rev;
- return new FreebsdAlphaSystem(p);
+ return new FreebsdAlphaSystem(this);
}
-
-REGISTER_SIM_OBJECT("FreebsdAlphaSystem", FreebsdAlphaSystem)
-
* Authors: Ben Nash
*/
-#ifndef __KERN_FREEBSD_FREEBSD_SYSTEM_HH__
-#define __KERN_FREEBSD_FREEBSD_SYSTEM_HH__
+#ifndef __ARCH_ALPHA_FREEBSD_SYSTEM_HH__
+#define __ARCH_ALPHA_FREEBSD_SYSTEM_HH__
+#include "arch/alpha/system.hh"
#include "kern/system_events.hh"
+#include "params/FreebsdAlphaSystem.hh"
+#include "sim/system.hh"
class FreebsdAlphaSystem : public AlphaSystem
{
SkipCalibrateClocksEvent *skipCalibrateClocks;
public:
+ typedef FreebsdAlphaSystemParams Params;
FreebsdAlphaSystem(Params *p);
~FreebsdAlphaSystem();
+
void doCalibrateClocks(ThreadContext *tc);
};
-#endif // __KERN_FREEBSD_FREEBSD_SYSTEM_HH__
+#endif // __ARCH_ALPHA_FREEBSD_SYSTEM_HH__
#include "kern/linux/events.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
-#include "sim/builder.hh"
#include "sim/byteswap.hh"
using namespace std;
ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart());
}
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
-
- Param<Tick> boot_cpu_frequency;
- SimObjectParam<PhysicalMemory *> physmem;
- SimpleEnumParam<System::MemoryMode> mem_mode;
-
- Param<string> kernel;
- Param<string> console;
- Param<string> pal;
-
- Param<string> boot_osflags;
- Param<string> readfile;
- Param<string> symbolfile;
- Param<unsigned int> init_param;
-
- Param<uint64_t> system_type;
- Param<uint64_t> system_rev;
-
-END_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
-
- INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
- INIT_PARAM(physmem, "phsyical memory"),
- INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
- System::MemoryModeStrings),
- INIT_PARAM(kernel, "file that contains the kernel code"),
- INIT_PARAM(console, "file that contains the console code"),
- INIT_PARAM(pal, "file that contains palcode"),
- INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
- "a"),
- INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
- INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
- INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
- INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
- INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
-
-END_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
-
-CREATE_SIM_OBJECT(LinuxAlphaSystem)
+LinuxAlphaSystem *
+LinuxAlphaSystemParams::create()
{
- AlphaSystem::Params *p = new AlphaSystem::Params;
- p->name = getInstanceName();
- p->boot_cpu_frequency = boot_cpu_frequency;
- p->physmem = physmem;
- p->mem_mode = mem_mode;
- p->kernel_path = kernel;
- p->console_path = console;
- p->palcode = pal;
- p->boot_osflags = boot_osflags;
- p->init_param = init_param;
- p->readfile = readfile;
- p->symbolfile = symbolfile;
- p->system_type = system_type;
- p->system_rev = system_rev;
- return new LinuxAlphaSystem(p);
+ return new LinuxAlphaSystem(this);
}
-
-REGISTER_SIM_OBJECT("LinuxAlphaSystem", LinuxAlphaSystem)
-
#include "arch/alpha/idle_event.hh"
#include "arch/alpha/system.hh"
#include "kern/linux/events.hh"
+#include "params/LinuxAlphaSystem.hh"
using namespace AlphaISA;
using namespace Linux;
IdleStartEvent *idleStartEvent;
public:
+ typedef LinuxAlphaSystemParams Params;
LinuxAlphaSystem(Params *p);
~LinuxAlphaSystem();
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "mem/physical.hh"
+#include "params/AlphaSystem.hh"
#include "sim/byteswap.hh"
-#include "sim/builder.hh"
using namespace LittleEndianGuest;
* Load the pal, and console code into memory
*/
// Load Console Code
- console = createObjectFile(params()->console_path);
+ console = createObjectFile(params()->console);
if (console == NULL)
- fatal("Could not load console file %s", params()->console_path);
+ fatal("Could not load console file %s", params()->console);
// Load pal file
- pal = createObjectFile(params()->palcode);
+ pal = createObjectFile(params()->pal);
if (pal == NULL)
- fatal("Could not load PALcode file %s", params()->palcode);
+ fatal("Could not load PALcode file %s", params()->pal);
// Load program sections into memory
palSymtab->unserialize("pal_symtab", cp, section);
}
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
-
- Param<Tick> boot_cpu_frequency;
- SimObjectParam<PhysicalMemory *> physmem;
- SimpleEnumParam<System::MemoryMode> mem_mode;
-
- Param<std::string> kernel;
- Param<std::string> console;
- Param<std::string> pal;
-
- Param<std::string> boot_osflags;
- Param<std::string> readfile;
- Param<std::string> symbolfile;
- Param<unsigned int> init_param;
-
- Param<uint64_t> system_type;
- Param<uint64_t> system_rev;
-
-END_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
-
- INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
- INIT_PARAM(physmem, "phsyical memory"),
- INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
- System::MemoryModeStrings),
- INIT_PARAM(kernel, "file that contains the kernel code"),
- INIT_PARAM(console, "file that contains the console code"),
- INIT_PARAM(pal, "file that contains palcode"),
- INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
- "a"),
- INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
- INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
- INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
- INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
- INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
-
-END_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
-
-CREATE_SIM_OBJECT(AlphaSystem)
+AlphaSystem *
+AlphaSystemParams::create()
{
- AlphaSystem::Params *p = new AlphaSystem::Params;
- p->name = getInstanceName();
- p->boot_cpu_frequency = boot_cpu_frequency;
- p->physmem = physmem;
- p->mem_mode = mem_mode;
- p->kernel_path = kernel;
- p->console_path = console;
- p->palcode = pal;
- p->boot_osflags = boot_osflags;
- p->init_param = init_param;
- p->readfile = readfile;
- p->symbolfile = symbolfile;
- p->system_type = system_type;
- p->system_rev = system_rev;
- return new AlphaSystem(p);
+ return new AlphaSystem(this);
}
-
-REGISTER_SIM_OBJECT("AlphaSystem", AlphaSystem)
-
-
#include <string>
#include <vector>
-#include "sim/system.hh"
#include "base/loader/symtab.hh"
#include "cpu/pc_event.hh"
#include "kern/system_events.hh"
+#include "params/AlphaSystem.hh"
#include "sim/sim_object.hh"
+#include "sim/system.hh"
class AlphaSystem : public System
{
public:
- struct Params : public System::Params
- {
- std::string console_path;
- std::string palcode;
- uint64_t system_type;
- uint64_t system_rev;
- };
-
+ typedef AlphaSystemParams Params;
AlphaSystem(Params *p);
-
~AlphaSystem();
/**
#include "base/trace.hh"
#include "config/alpha_tlaser.hh"
#include "cpu/thread_context.hh"
-#include "sim/builder.hh"
+#include "params/AlphaDTB.hh"
+#include "params/AlphaITB.hh"
using namespace std;
using namespace EV5;
/* end namespace AlphaISA */ }
-DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB)
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
-
- Param<int> size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(ITB)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
-
- INIT_PARAM_DFLT(size, "TLB size", 48)
-
-END_INIT_SIM_OBJECT_PARAMS(ITB)
-
-
-CREATE_SIM_OBJECT(ITB)
+AlphaISA::ITB *
+AlphaITBParams::create()
{
- return new ITB(getInstanceName(), size);
+ return new AlphaISA::ITB(name, size);
}
-REGISTER_SIM_OBJECT("AlphaITB", ITB)
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
-
- Param<int> size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DTB)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
-
- INIT_PARAM_DFLT(size, "TLB size", 64)
-
-END_INIT_SIM_OBJECT_PARAMS(DTB)
-
-
-CREATE_SIM_OBJECT(DTB)
+AlphaISA::DTB *
+AlphaDTBParams::create()
{
- return new DTB(getInstanceName(), size);
+ return new AlphaISA::DTB(name, size);
}
-
-REGISTER_SIM_OBJECT("AlphaDTB", DTB)
#include "kern/system_events.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
-#include "sim/builder.hh"
using namespace std;
#endif
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
-
- Param<Tick> boot_cpu_frequency;
- SimObjectParam<PhysicalMemory *> physmem;
- SimpleEnumParam<System::MemoryMode> mem_mode;
-
- Param<string> kernel;
- Param<string> console;
- Param<string> pal;
-
- Param<string> boot_osflags;
- Param<string> readfile;
- Param<string> symbolfile;
- Param<unsigned int> init_param;
-
- Param<uint64_t> system_type;
- Param<uint64_t> system_rev;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
-
- INIT_PARAM(boot_cpu_frequency, "frequency of the boot cpu"),
- INIT_PARAM(physmem, "phsyical memory"),
- INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
- System::MemoryModeStrings),
- INIT_PARAM(kernel, "file that contains the kernel code"),
- INIT_PARAM(console, "file that contains the console code"),
- INIT_PARAM(pal, "file that contains palcode"),
- INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
- "a"),
- INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
- INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
- INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
- INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 12),
- INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 2<<1)
-
-END_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
-
-CREATE_SIM_OBJECT(Tru64AlphaSystem)
+Tru64AlphaSystem *
+Tru64AlphaSystemParams::create()
{
- AlphaSystem::Params *p = new AlphaSystem::Params;
- p->name = getInstanceName();
- p->boot_cpu_frequency = boot_cpu_frequency;
- p->physmem = physmem;
- p->mem_mode = mem_mode;
- p->kernel_path = kernel;
- p->console_path = console;
- p->palcode = pal;
- p->boot_osflags = boot_osflags;
- p->init_param = init_param;
- p->readfile = readfile;
- p->symbolfile = symbolfile;
- p->system_type = system_type;
- p->system_rev = system_rev;
-
- return new Tru64AlphaSystem(p);
+ return new Tru64AlphaSystem(this);
}
-
-REGISTER_SIM_OBJECT("Tru64AlphaSystem", Tru64AlphaSystem)
#include "arch/alpha/system.hh"
#include "arch/isa_traits.hh"
+#include "params/Tru64AlphaSystem.hh"
#include "sim/system.hh"
class ThreadContext;
DumpMbufEvent *dumpMbufEvent;
public:
+ typedef Tru64AlphaSystemParams Params;
Tru64AlphaSystem(Params *p);
~Tru64AlphaSystem();
class SparcDTB(SparcTLB):
type = 'SparcDTB'
+ cxx_namespace = 'SparcISA'
+ cxx_class = 'DTB'
+
size = 64
class SparcITB(SparcTLB):
type = 'SparcITB'
+ cxx_namespace = 'SparcISA'
+ cxx_class = 'ITB'
+
size = 64
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "mem/physical.hh"
+#include "params/SparcSystem.hh"
#include "sim/byteswap.hh"
-#include "sim/builder.hh"
using namespace BigEndianGuest;
partitionDescSymtab->unserialize("partition_desc_symtab", cp, section);
}
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
-
- SimObjectParam<PhysicalMemory *> physmem;
- SimObjectParam<PhysicalMemory *> rom;
- SimObjectParam<PhysicalMemory *> nvram;
- SimObjectParam<PhysicalMemory *> hypervisor_desc;
- SimObjectParam<PhysicalMemory *> partition_desc;
- SimpleEnumParam<System::MemoryMode> mem_mode;
-
- Param<Addr> reset_addr;
- Param<Addr> hypervisor_addr;
- Param<Addr> openboot_addr;
- Param<Addr> nvram_addr;
- Param<Addr> hypervisor_desc_addr;
- Param<Addr> partition_desc_addr;
-
- Param<std::string> kernel;
- Param<std::string> reset_bin;
- Param<std::string> hypervisor_bin;
- Param<std::string> openboot_bin;
- Param<std::string> nvram_bin;
- Param<std::string> hypervisor_desc_bin;
- Param<std::string> partition_desc_bin;
-
- Param<Tick> boot_cpu_frequency;
- Param<std::string> boot_osflags;
- Param<std::string> readfile;
- Param<unsigned int> init_param;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem)
-
- INIT_PARAM(physmem, "phsyical memory"),
- INIT_PARAM(rom, "ROM for boot code"),
- INIT_PARAM(nvram, "Non-volatile RAM for the nvram"),
- INIT_PARAM(hypervisor_desc, "ROM for the hypervisor description"),
- INIT_PARAM(partition_desc, "ROM for the partition description"),
- INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
- System::MemoryModeStrings),
-
- INIT_PARAM(reset_addr, "Address that reset should be loaded at"),
- INIT_PARAM(hypervisor_addr, "Address that hypervisor should be loaded at"),
- INIT_PARAM(openboot_addr, "Address that openboot should be loaded at"),
- INIT_PARAM(nvram_addr, "Address that nvram should be loaded at"),
- INIT_PARAM(hypervisor_desc_addr,
- "Address that hypervisor description should be loaded at"),
- INIT_PARAM(partition_desc_addr,
- "Address that partition description should be loaded at"),
-
- INIT_PARAM(kernel, "file that contains the kernel code"),
- INIT_PARAM(reset_bin, "file that contains the reset code"),
- INIT_PARAM(hypervisor_bin, "file that contains the hypervisor code"),
- INIT_PARAM(openboot_bin, "file that contains the openboot code"),
- INIT_PARAM(nvram_bin, "file that contains the nvram image"),
- INIT_PARAM(hypervisor_desc_bin,
- "file that contains the hypervisor description image"),
- INIT_PARAM(partition_desc_bin,
- "file that contains the partition description image"),
- INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
- INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
- "a"),
- INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
- INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0)
-
-END_INIT_SIM_OBJECT_PARAMS(SparcSystem)
-
-CREATE_SIM_OBJECT(SparcSystem)
+SparcSystem *
+SparcSystemParams::create()
{
- SparcSystem::Params *p = new SparcSystem::Params;
- p->name = getInstanceName();
- p->boot_cpu_frequency = boot_cpu_frequency;
- p->physmem = physmem;
- p->rom = rom;
- p->nvram = nvram;
- p->hypervisor_desc = hypervisor_desc;
- p->partition_desc = partition_desc;
- p->mem_mode = mem_mode;
- p->kernel_path = kernel;
- p->reset_addr = reset_addr;
- p->hypervisor_addr = hypervisor_addr;
- p->openboot_addr = openboot_addr;
- p->nvram_addr = nvram_addr;
- p->hypervisor_desc_addr = hypervisor_desc_addr;
- p->partition_desc_addr = partition_desc_addr;
- p->reset_bin = reset_bin;
- p->hypervisor_bin = hypervisor_bin;
- p->openboot_bin = openboot_bin;
- p->nvram_bin = nvram_bin;
- p->hypervisor_desc_bin = hypervisor_desc_bin;
- p->partition_desc_bin = partition_desc_bin;
- p->boot_osflags = boot_osflags;
- p->init_param = init_param;
- p->readfile = readfile;
- return new SparcSystem(p);
+ return new SparcSystem(this);
}
-
-REGISTER_SIM_OBJECT("SparcSystem", SparcSystem)
-
-
#include "base/loader/symtab.hh"
#include "cpu/pc_event.hh"
#include "kern/system_events.hh"
+#include "params/SparcSystem.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
class SparcSystem : public System
{
public:
- struct Params : public System::Params
- {
- PhysicalMemory *rom;
- PhysicalMemory *nvram;
- PhysicalMemory *hypervisor_desc;
- PhysicalMemory *partition_desc;
- Addr reset_addr;
- Addr hypervisor_addr;
- Addr openboot_addr;
- Addr nvram_addr;
- Addr hypervisor_desc_addr;
- Addr partition_desc_addr;
- std::string reset_bin;
- std::string hypervisor_bin;
- std::string openboot_bin;
- std::string nvram_bin;
- std::string hypervisor_desc_bin;
- std::string partition_desc_bin;
- std::string boot_osflags;
- };
-
+ typedef SparcSystemParams Params;
SparcSystem(Params *p);
-
~SparcSystem();
/**
#include "cpu/base.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
-#include "sim/builder.hh"
+#include "params/SparcDTB.hh"
+#include "params/SparcITB.hh"
#include "sim/system.hh"
/* @todo remove some of the magic constants. -- ali
/* end namespace SparcISA */ }
-using namespace SparcISA;
-
-DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
-
- Param<int> size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(ITB)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
-
- INIT_PARAM_DFLT(size, "TLB size", 48)
-
-END_INIT_SIM_OBJECT_PARAMS(ITB)
-
-
-CREATE_SIM_OBJECT(ITB)
+SparcISA::ITB *
+SparcITBParams::create()
{
- return new ITB(getInstanceName(), size);
+ return new SparcISA::ITB(name, size);
}
-REGISTER_SIM_OBJECT("SparcITB", ITB)
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
-
- Param<int> size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DTB)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
-
- INIT_PARAM_DFLT(size, "TLB size", 64)
-
-END_INIT_SIM_OBJECT_PARAMS(DTB)
-
-
-CREATE_SIM_OBJECT(DTB)
+SparcISA::DTB *
+SparcDTBParams::create()
{
- return new DTB(getInstanceName(), size);
+ return new SparcISA::DTB(name, size);
}
-
-REGISTER_SIM_OBJECT("SparcDTB", DTB)
if env['USE_CHECKER']:
temp_cpu_list.append('CheckerCPU')
-# Generate header.
+# Generate header.
def gen_cpu_exec_signatures(target, source, env):
f = open(str(target[0]), 'w')
print >> f, '''
Source('cpuevent.cc')
Source('exetrace.cc')
Source('func_unit.cc')
-Source('op_class.cc')
Source('pc_event.cc')
Source('quiesce_event.cc')
Source('static_inst.cc')
#include "cpu/thread_context.hh"
#include "cpu/profile.hh"
#include "sim/sim_exit.hh"
-#include "sim/param.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh"
#include "sim/system.hh"
functionEntryTick = curTick;
}
}
-
-
-DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
-#include "sim/param.hh"
+#include "enums/OpClass.hh"
#include "sim/system.hh"
#if FULL_SYSTEM
outs << " : ";
if (IsOn(ExecOpClass)) {
- outs << opClassStrings[staticInst->opClass()] << " : ";
+ outs << Enums::OpClassStrings[staticInst->opClass()] << " : ";
}
if (IsOn(ExecResult) && data_status != DataInvalid) {
#include "base/misc.hh"
#include "cpu/func_unit.hh"
-#include "sim/builder.hh"
+#include "params/OpDesc.hh"
+#include "params/FUDesc.hh"
using namespace std;
//
// The operation-class description object
//
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
-
- SimpleEnumParam<OpClass> opClass;
- Param<unsigned> opLat;
- Param<unsigned> issueLat;
-
-END_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(OpDesc)
-
- INIT_ENUM_PARAM(opClass, "type of operation", opClassStrings),
- INIT_PARAM(opLat, "cycles until result is available"),
- INIT_PARAM(issueLat, "cycles until another can be issued")
-
-END_INIT_SIM_OBJECT_PARAMS(OpDesc)
-
-
-CREATE_SIM_OBJECT(OpDesc)
+OpDesc *
+OpDescParams::create()
{
- return new OpDesc(getInstanceName(), opClass, opLat, issueLat);
+ return new OpDesc(name, opClass, opLat, issueLat);
}
-REGISTER_SIM_OBJECT("OpDesc", OpDesc)
-
-
//
// The FuDesc object
//
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
-
- SimObjectVectorParam<OpDesc *> opList;
- Param<unsigned> count;
-
-END_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(FUDesc)
-
- INIT_PARAM(opList, "list of operation classes for this FU type"),
- INIT_PARAM(count, "number of these FU's available")
-
-END_INIT_SIM_OBJECT_PARAMS(FUDesc)
-
-
-CREATE_SIM_OBJECT(FUDesc)
+FUDesc *
+FUDescParams::create()
{
- return new FUDesc(getInstanceName(), opList, count);
+ return new FUDesc(name, opList, count);
}
-
-REGISTER_SIM_OBJECT("FUDesc", FUDesc)
-
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "cpu/intr_control.hh"
-#include "sim/builder.hh"
+#include "params/IntrControl.hh"
#include "sim/sim_object.hh"
using namespace std;
temp->clear_interrupt(int_num, index);
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
-
- SimObjectParam<System *> sys;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
-
- INIT_PARAM(sys, "the system we are part of")
-
-END_INIT_SIM_OBJECT_PARAMS(IntrControl)
-
-CREATE_SIM_OBJECT(IntrControl)
+IntrControl *
+IntrControlParams::create()
{
- return new IntrControl(getInstanceName(), sys);
+ return new IntrControl(name, sys);
}
-
-REGISTER_SIM_OBJECT("IntrControl", IntrControl)
#include "mem/packet.hh"
//#include "mem/physical.hh"
#include "mem/request.hh"
-#include "sim/builder.hh"
+#include "params/MemTest.hh"
#include "sim/sim_events.hh"
#include "sim/stats.hh"
}
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
-
-// SimObjectParam<BaseCache *> cache;
-// SimObjectParam<PhysicalMemory *> main_mem;
-// SimObjectParam<PhysicalMemory *> check_mem;
- Param<unsigned> memory_size;
- Param<unsigned> percent_reads;
- Param<unsigned> percent_functional;
- Param<unsigned> percent_uncacheable;
- Param<unsigned> progress_interval;
- Param<unsigned> percent_source_unaligned;
- Param<unsigned> percent_dest_unaligned;
- Param<Addr> trace_addr;
- Param<Counter> max_loads;
- Param<bool> atomic;
-
-END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
-
-// INIT_PARAM(cache, "L1 cache"),
-// INIT_PARAM(main_mem, "hierarchical memory"),
-// INIT_PARAM(check_mem, "check memory"),
- INIT_PARAM(memory_size, "memory size"),
- INIT_PARAM(percent_reads, "target read percentage"),
- INIT_PARAM(percent_functional, "percentage of access that are functional"),
- INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
- INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
- INIT_PARAM(percent_source_unaligned,
- "percent of copy source address that are unaligned"),
- INIT_PARAM(percent_dest_unaligned,
- "percent of copy dest address that are unaligned"),
- INIT_PARAM(trace_addr, "address to trace"),
- INIT_PARAM(max_loads, "terminate when we have reached this load count"),
- INIT_PARAM(atomic, "Is the tester testing atomic mode (or timing)")
-
-END_INIT_SIM_OBJECT_PARAMS(MemTest)
-
-
-CREATE_SIM_OBJECT(MemTest)
+MemTest *
+MemTestParams::create()
{
- return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
- /*check_mem,*/ memory_size, percent_reads, percent_functional,
+ return new MemTest(name,
+#if 0
+ cache->getInterface(), main_mem, check_mem,
+#endif
+ memory_size, percent_reads, percent_functional,
percent_uncacheable, progress_interval,
percent_source_unaligned, percent_dest_unaligned,
trace_addr, max_loads, atomic);
}
-
-REGISTER_SIM_OBJECT("MemTest", MemTest)
#include <string>
+#include "config/use_checker.hh"
#include "cpu/base.hh"
#include "cpu/o3/alpha/cpu.hh"
#include "cpu/o3/alpha/impl.hh"
#include "cpu/o3/alpha/params.hh"
#include "cpu/o3/fu_pool.hh"
-#include "sim/builder.hh"
+#include "params/DerivO3CPU.hh"
class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
{
{ }
};
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
- Param<int> clock;
- Param<int> phase;
- Param<int> numThreads;
-Param<int> cpu_id;
-Param<int> activity;
-
-#if FULL_SYSTEM
-SimObjectParam<System *> system;
-SimObjectParam<AlphaISA::ITB *> itb;
-SimObjectParam<AlphaISA::DTB *> dtb;
-Param<Tick> profile;
-
-Param<bool> do_quiesce;
-Param<bool> do_checkpoint_insts;
-Param<bool> do_statistics_insts;
-#else
-SimObjectVectorParam<Process *> workload;
-#endif // FULL_SYSTEM
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-Param<Tick> progress_interval;
-
-Param<unsigned> cachePorts;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> dispatchWidth;
-Param<unsigned> issueWidth;
-Param<unsigned> wbWidth;
-Param<unsigned> wbDepth;
-SimObjectParam<FUPool *> fuPool;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-Param<Tick> trapLatency;
-
-Param<unsigned> backComSize;
-Param<unsigned> forwardComSize;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string> smtFetchPolicy;
-Param<std::string> smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string> smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string> smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string> smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM_DFLT(phase, "clock phase", 0),
- INIT_PARAM(numThreads, "number of HW thread contexts"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM_DFLT(activity, "Initial activity count", 0),
-
-#if FULL_SYSTEM
- INIT_PARAM(system, "System object"),
- INIT_PARAM(itb, "Instruction translation buffer"),
- INIT_PARAM(dtb, "Data translation buffer"),
- INIT_PARAM(profile, ""),
-
- INIT_PARAM(do_quiesce, ""),
- INIT_PARAM(do_checkpoint_insts, ""),
- INIT_PARAM(do_statistics_insts, ""),
-#else
- INIT_PARAM(workload, "Processes to run"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
- INIT_PARAM_DFLT(max_insts_any_thread,
- "Terminate when any thread reaches this inst count",
- 0),
- INIT_PARAM_DFLT(max_insts_all_threads,
- "Terminate when all threads have reached"
- "this inst count",
- 0),
- INIT_PARAM_DFLT(max_loads_any_thread,
- "Terminate when any thread reaches this load count",
- 0),
- INIT_PARAM_DFLT(max_loads_all_threads,
- "Terminate when all threads have reached this load"
- "count",
- 0),
- INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
-
- INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-
- INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
- INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
- INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
- "delay"),
- INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
- INIT_PARAM(fetchWidth, "Fetch width"),
- INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
- INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
- "delay"),
- INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
- INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
- INIT_PARAM(decodeWidth, "Decode width"),
-
- INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
- "delay"),
- INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
- INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
- INIT_PARAM(renameWidth, "Rename width"),
-
- INIT_PARAM(commitToIEWDelay, "Commit to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(renameToIEWDelay, "Rename to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
- "to the IEW stage)"),
- INIT_PARAM(dispatchWidth, "Dispatch width"),
- INIT_PARAM(issueWidth, "Issue width"),
- INIT_PARAM(wbWidth, "Writeback width"),
- INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
- INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
-
- INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
- "delay"),
- INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
- INIT_PARAM(commitWidth, "Commit width"),
- INIT_PARAM(squashWidth, "Squash width"),
- INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
-
- INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
- INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
-
- INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
- INIT_PARAM(localPredictorSize, "Size of local predictor"),
- INIT_PARAM(localCtrBits, "Bits per counter"),
- INIT_PARAM(localHistoryTableSize, "Size of local history table"),
- INIT_PARAM(localHistoryBits, "Bits for the local history"),
- INIT_PARAM(globalPredictorSize, "Size of global predictor"),
- INIT_PARAM(globalCtrBits, "Bits per counter"),
- INIT_PARAM(globalHistoryBits, "Bits of history"),
- INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
- INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
- INIT_PARAM(BTBEntries, "Number of BTB entries"),
- INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
- INIT_PARAM(RASSize, "RAS size"),
-
- INIT_PARAM(LQEntries, "Number of load queue entries"),
- INIT_PARAM(SQEntries, "Number of store queue entries"),
- INIT_PARAM(LFSTSize, "Last fetched store table size"),
- INIT_PARAM(SSITSize, "Store set ID table size"),
-
- INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
- INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
- "registers"),
- INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
- INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
- INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
- INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
- INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
- INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
- INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
- INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
- INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-CREATE_SIM_OBJECT(DerivO3CPU)
+DerivO3CPU *
+DerivO3CPUParams::create()
{
DerivO3CPU *cpu;
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
int actual_num_threads =
- (numThreads.isValid() && numThreads >= workload.size()) ?
- numThreads : workload.size();
+ (numThreads >= workload.size()) ? numThreads : workload.size();
if (workload.size() == 0) {
fatal("Must specify at least one workload!");
params->clock = clock;
params->phase = phase;
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = actual_num_threads;
params->cpu_id = cpu_id;
params->activity = activity;
params->workload = workload;
#endif // FULL_SYSTEM
+#if USE_CHECKER
params->checker = checker;
+#endif
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
return cpu;
}
-
-REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
-
#include "cpu/inst_seq.hh"
#include "cpu/o3/alpha/dyn_inst.hh"
#include "cpu/o3/alpha/impl.hh"
-#include "sim/builder.hh"
+#include "params/O3Checker.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
//
// CheckerCPU Simulation Object
//
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
-
- Param<Counter> max_insts_any_thread;
- Param<Counter> max_insts_all_threads;
- Param<Counter> max_loads_any_thread;
- Param<Counter> max_loads_all_threads;
- Param<Tick> progress_interval;
-
-#if FULL_SYSTEM
- SimObjectParam<TheISA::ITB *> itb;
- SimObjectParam<TheISA::DTB *> dtb;
- SimObjectParam<System *> system;
- Param<int> cpu_id;
- Param<Tick> profile;
-#else
- SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
- Param<int> clock;
-
- Param<bool> defer_registration;
- Param<bool> exitOnError;
- Param<bool> updateOnError;
- Param<bool> warnOnlyOnLoadError;
- Param<bool> function_trace;
- Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
-
- INIT_PARAM(max_insts_any_thread,
- "terminate when any thread reaches this inst count"),
- INIT_PARAM(max_insts_all_threads,
- "terminate when all threads have reached this inst count"),
- INIT_PARAM(max_loads_any_thread,
- "terminate when any thread reaches this load count"),
- INIT_PARAM(max_loads_all_threads,
- "terminate when all threads have reached this load count"),
- INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
-
-#if FULL_SYSTEM
- INIT_PARAM(itb, "Instruction TLB"),
- INIT_PARAM(dtb, "Data TLB"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM(profile, ""),
-#else
- INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM(clock, "clock speed"),
-
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
- INIT_PARAM(exitOnError, "exit on error"),
- INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
- INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load "
- "result errors", false),
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(O3Checker)
-
-
-CREATE_SIM_OBJECT(O3Checker)
+O3Checker *
+O3CheckerParams::create()
{
O3Checker::Params *params = new O3Checker::Params();
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = 0;
params->max_insts_all_threads = 0;
O3Checker *cpu = new O3Checker(params);
return cpu;
}
-
-REGISTER_SIM_OBJECT("O3Checker", O3Checker)
#include "config/full_system.hh"
#include "config/use_checker.hh"
-#if FULL_SYSTEM
-#include "cpu/quiesce_event.hh"
-#include "sim/system.hh"
-#else
-#include "sim/process.hh"
-#endif
-
#include "cpu/activity.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "cpu/o3/isa_specific.hh"
#include "cpu/o3/cpu.hh"
-
+#include "enums/MemoryMode.hh"
#include "sim/core.hh"
#include "sim/stat_control.hh"
+#if FULL_SYSTEM
+#include "cpu/quiesce_event.hh"
+#include "sim/system.hh"
+#else
+#include "sim/process.hh"
+#endif
+
#if USE_CHECKER
#include "cpu/checker/cpu.hh"
#endif
return;
#if FULL_SYSTEM
- assert(system->getMemoryMode() == System::Timing);
+ assert(system->getMemoryMode() == Enums::timing);
#endif
if (!tickEvent.scheduled())
#include "cpu/o3/fu_pool.hh"
#include "cpu/func_unit.hh"
-#include "sim/builder.hh"
+#include "params/FUPool.hh"
using namespace std;
//
// The FuPool object
//
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUPool)
-
- SimObjectVectorParam<FUDesc *> FUList;
-
-END_DECLARE_SIM_OBJECT_PARAMS(FUPool)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(FUPool)
-
- INIT_PARAM(FUList, "list of FU's for this pool")
-
-END_INIT_SIM_OBJECT_PARAMS(FUPool)
-
-
-CREATE_SIM_OBJECT(FUPool)
+FUPool *
+FUPoolParams::create()
{
- return new FUPool(getInstanceName(), FUList);
+ return new FUPool(name, FUList);
}
-
-REGISTER_SIM_OBJECT("FUPool", FUPool)
-
#include <limits>
#include <vector>
-#include "sim/core.hh"
-
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
+#include "enums/OpClass.hh"
+#include "sim/core.hh"
template <class Impl>
InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
}
*/
statIssuedInstType
- .init(numThreads,Num_OpClasses)
+ .init(numThreads,Enums::Num_OpClass)
.name(name() + ".ISSUE:FU_type")
.desc("Type of FU issued")
.flags(total | pdf | dist)
;
- statIssuedInstType.ysubnames(opClassStrings);
+ statIssuedInstType.ysubnames(Enums::OpClassStrings);
//
// How long did instructions for a particular FU type wait prior to issue
.flags(pdf | dist)
;
for (int i=0; i < Num_OpClasses; ++i) {
- statFuBusy.subname(i, opClassStrings[i]);
+ statFuBusy.subname(i, Enums::OpClassStrings[i]);
}
fuBusy
#include <string>
+#include "config/use_checker.hh"
#include "cpu/base.hh"
#include "cpu/o3/mips/cpu.hh"
#include "cpu/o3/mips/impl.hh"
#include "cpu/o3/mips/params.hh"
#include "cpu/o3/fu_pool.hh"
-#include "sim/builder.hh"
+#include "params/DerivO3CPU.hh"
class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
{
{ }
};
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-Param<int> clock;
-Param<int> phase;
-Param<int> numThreads;
-Param<int> cpu_id;
-Param<int> activity;
-
-SimObjectVectorParam<Process *> workload;
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-
-Param<unsigned> cachePorts;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> dispatchWidth;
-Param<unsigned> issueWidth;
-Param<unsigned> wbWidth;
-Param<unsigned> wbDepth;
-SimObjectParam<FUPool *> fuPool;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-Param<Tick> trapLatency;
-
-Param<unsigned> backComSize;
-Param<unsigned> forwardComSize;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string> smtFetchPolicy;
-Param<std::string> smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string> smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string> smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string> smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM_DFLT(phase, "clock phase", 0),
- INIT_PARAM(numThreads, "number of HW thread contexts"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM_DFLT(activity, "Initial activity count", 0),
-
- INIT_PARAM(workload, "Processes to run"),
-
- INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
- INIT_PARAM_DFLT(max_insts_any_thread,
- "Terminate when any thread reaches this inst count",
- 0),
- INIT_PARAM_DFLT(max_insts_all_threads,
- "Terminate when all threads have reached"
- "this inst count",
- 0),
- INIT_PARAM_DFLT(max_loads_any_thread,
- "Terminate when any thread reaches this load count",
- 0),
- INIT_PARAM_DFLT(max_loads_all_threads,
- "Terminate when all threads have reached this load"
- "count",
- 0),
-
- INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-
- INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
- INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
- INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
- "delay"),
- INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
- INIT_PARAM(fetchWidth, "Fetch width"),
- INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
- INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
- "delay"),
- INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
- INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
- INIT_PARAM(decodeWidth, "Decode width"),
-
- INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
- "delay"),
- INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
- INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
- INIT_PARAM(renameWidth, "Rename width"),
-
- INIT_PARAM(commitToIEWDelay, "Commit to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(renameToIEWDelay, "Rename to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
- "to the IEW stage)"),
- INIT_PARAM(dispatchWidth, "Dispatch width"),
- INIT_PARAM(issueWidth, "Issue width"),
- INIT_PARAM(wbWidth, "Writeback width"),
- INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
- INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
-
- INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
- "delay"),
- INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
- INIT_PARAM(commitWidth, "Commit width"),
- INIT_PARAM(squashWidth, "Squash width"),
- INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
-
- INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
- INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
-
- INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
- INIT_PARAM(localPredictorSize, "Size of local predictor"),
- INIT_PARAM(localCtrBits, "Bits per counter"),
- INIT_PARAM(localHistoryTableSize, "Size of local history table"),
- INIT_PARAM(localHistoryBits, "Bits for the local history"),
- INIT_PARAM(globalPredictorSize, "Size of global predictor"),
- INIT_PARAM(globalCtrBits, "Bits per counter"),
- INIT_PARAM(globalHistoryBits, "Bits of history"),
- INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
- INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
- INIT_PARAM(BTBEntries, "Number of BTB entries"),
- INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
- INIT_PARAM(RASSize, "RAS size"),
-
- INIT_PARAM(LQEntries, "Number of load queue entries"),
- INIT_PARAM(SQEntries, "Number of store queue entries"),
- INIT_PARAM(LFSTSize, "Last fetched store table size"),
- INIT_PARAM(SSITSize, "Store set ID table size"),
-
- INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
- INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
- "registers"),
- INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
- INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
- INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
- INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
- INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
- INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
- INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
- INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
- INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-CREATE_SIM_OBJECT(DerivO3CPU)
+DerivO3CPU *
+DerivO3CPUParams::create()
{
DerivO3CPU *cpu;
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
int actual_num_threads =
- (numThreads.isValid() && numThreads >= workload.size()) ?
- numThreads : workload.size();
+ (numThreads >= workload.size()) ? numThreads : workload.size();
if (workload.size() == 0) {
fatal("Must specify at least one workload!");
params->clock = clock;
params->phase = phase;
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = actual_num_threads;
params->cpu_id = cpu_id;
params->activity = activity;
params->workload = workload;
+#if USE_CHECKER
params->checker = checker;
+#endif
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
return cpu;
}
-
-REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
-
#include <string>
+#include "config/full_system.hh"
+#include "config/use_checker.hh"
#include "cpu/base.hh"
#include "cpu/o3/sparc/cpu.hh"
#include "cpu/o3/sparc/impl.hh"
#include "cpu/o3/sparc/params.hh"
#include "cpu/o3/fu_pool.hh"
-#include "sim/builder.hh"
+#include "params/DerivO3CPU.hh"
class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
{
{ }
};
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
- Param<int> clock;
- Param<int> phase;
- Param<int> numThreads;
- Param<int> cpu_id;
- Param<int> activity;
-
-#if FULL_SYSTEM
- SimObjectParam<System *> system;
- SimObjectParam<SparcISA::ITB *> itb;
- SimObjectParam<SparcISA::DTB *> dtb;
- Param<Tick> profile;
-
- Param<bool> do_quiesce;
- Param<bool> do_checkpoint_insts;
- Param<bool> do_statistics_insts;
-#else
- SimObjectVectorParam<Process *> workload;
-#endif // FULL_SYSTEM
-
- SimObjectParam<BaseCPU *> checker;
-
- Param<Counter> max_insts_any_thread;
- Param<Counter> max_insts_all_threads;
- Param<Counter> max_loads_any_thread;
- Param<Counter> max_loads_all_threads;
- Param<Tick> progress_interval;
-
- Param<unsigned> cachePorts;
-
- Param<unsigned> decodeToFetchDelay;
- Param<unsigned> renameToFetchDelay;
- Param<unsigned> iewToFetchDelay;
- Param<unsigned> commitToFetchDelay;
- Param<unsigned> fetchWidth;
-
- Param<unsigned> renameToDecodeDelay;
- Param<unsigned> iewToDecodeDelay;
- Param<unsigned> commitToDecodeDelay;
- Param<unsigned> fetchToDecodeDelay;
- Param<unsigned> decodeWidth;
-
- Param<unsigned> iewToRenameDelay;
- Param<unsigned> commitToRenameDelay;
- Param<unsigned> decodeToRenameDelay;
- Param<unsigned> renameWidth;
-
- Param<unsigned> commitToIEWDelay;
- Param<unsigned> renameToIEWDelay;
- Param<unsigned> issueToExecuteDelay;
- Param<unsigned> dispatchWidth;
- Param<unsigned> issueWidth;
- Param<unsigned> wbWidth;
- Param<unsigned> wbDepth;
- SimObjectParam<FUPool *> fuPool;
-
- Param<unsigned> iewToCommitDelay;
- Param<unsigned> renameToROBDelay;
- Param<unsigned> commitWidth;
- Param<unsigned> squashWidth;
- Param<Tick> trapLatency;
-
- Param<unsigned> backComSize;
- Param<unsigned> forwardComSize;
-
- Param<std::string> predType;
- Param<unsigned> localPredictorSize;
- Param<unsigned> localCtrBits;
- Param<unsigned> localHistoryTableSize;
- Param<unsigned> localHistoryBits;
- Param<unsigned> globalPredictorSize;
- Param<unsigned> globalCtrBits;
- Param<unsigned> globalHistoryBits;
- Param<unsigned> choicePredictorSize;
- Param<unsigned> choiceCtrBits;
-
- Param<unsigned> BTBEntries;
- Param<unsigned> BTBTagSize;
-
- Param<unsigned> RASSize;
-
- Param<unsigned> LQEntries;
- Param<unsigned> SQEntries;
- Param<unsigned> LFSTSize;
- Param<unsigned> SSITSize;
-
- Param<unsigned> numPhysIntRegs;
- Param<unsigned> numPhysFloatRegs;
- Param<unsigned> numIQEntries;
- Param<unsigned> numROBEntries;
-
- Param<unsigned> smtNumFetchingThreads;
- Param<std::string> smtFetchPolicy;
- Param<std::string> smtLSQPolicy;
- Param<unsigned> smtLSQThreshold;
- Param<std::string> smtIQPolicy;
- Param<unsigned> smtIQThreshold;
- Param<std::string> smtROBPolicy;
- Param<unsigned> smtROBThreshold;
- Param<std::string> smtCommitPolicy;
-
- Param<unsigned> instShiftAmt;
-
- Param<bool> defer_registration;
-
- Param<bool> function_trace;
- Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM_DFLT(phase, "clock phase", 0),
- INIT_PARAM(numThreads, "number of HW thread contexts"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM_DFLT(activity, "Initial activity count", 0),
-
-#if FULL_SYSTEM
- INIT_PARAM(system, "System object"),
- INIT_PARAM(itb, "Instruction translation buffer"),
- INIT_PARAM(dtb, "Data translation buffer"),
- INIT_PARAM(profile, ""),
-
- INIT_PARAM(do_quiesce, ""),
- INIT_PARAM(do_checkpoint_insts, ""),
- INIT_PARAM(do_statistics_insts, ""),
-#else
- INIT_PARAM(workload, "Processes to run"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
- INIT_PARAM_DFLT(max_insts_any_thread,
- "Terminate when any thread reaches this inst count",
- 0),
- INIT_PARAM_DFLT(max_insts_all_threads,
- "Terminate when all threads have reached"
- "this inst count",
- 0),
- INIT_PARAM_DFLT(max_loads_any_thread,
- "Terminate when any thread reaches this load count",
- 0),
- INIT_PARAM_DFLT(max_loads_all_threads,
- "Terminate when all threads have reached this load"
- "count",
- 0),
- INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
-
- INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-
- INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
- INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
- INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
- "delay"),
- INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
- INIT_PARAM(fetchWidth, "Fetch width"),
- INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
- INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
- "delay"),
- INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
- INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
- INIT_PARAM(decodeWidth, "Decode width"),
-
- INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
- "delay"),
- INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
- INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
- INIT_PARAM(renameWidth, "Rename width"),
-
- INIT_PARAM(commitToIEWDelay, "Commit to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(renameToIEWDelay, "Rename to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
- "to the IEW stage)"),
- INIT_PARAM(dispatchWidth, "Dispatch width"),
- INIT_PARAM(issueWidth, "Issue width"),
- INIT_PARAM(wbWidth, "Writeback width"),
- INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
- INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
-
- INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
- "delay"),
- INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
- INIT_PARAM(commitWidth, "Commit width"),
- INIT_PARAM(squashWidth, "Squash width"),
- INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
-
- INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
- INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
-
- INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
- INIT_PARAM(localPredictorSize, "Size of local predictor"),
- INIT_PARAM(localCtrBits, "Bits per counter"),
- INIT_PARAM(localHistoryTableSize, "Size of local history table"),
- INIT_PARAM(localHistoryBits, "Bits for the local history"),
- INIT_PARAM(globalPredictorSize, "Size of global predictor"),
- INIT_PARAM(globalCtrBits, "Bits per counter"),
- INIT_PARAM(globalHistoryBits, "Bits of history"),
- INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
- INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
- INIT_PARAM(BTBEntries, "Number of BTB entries"),
- INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
- INIT_PARAM(RASSize, "RAS size"),
-
- INIT_PARAM(LQEntries, "Number of load queue entries"),
- INIT_PARAM(SQEntries, "Number of store queue entries"),
- INIT_PARAM(LFSTSize, "Last fetched store table size"),
- INIT_PARAM(SSITSize, "Store set ID table size"),
-
- INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
- INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
- "registers"),
- INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
- INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
- INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
- INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
- INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
- INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
- INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
- INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
- INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-CREATE_SIM_OBJECT(DerivO3CPU)
+DerivO3CPU *
+DerivO3CPUParams::create()
{
DerivO3CPU *cpu;
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
int actual_num_threads =
- (numThreads.isValid() && numThreads >= workload.size()) ?
- numThreads : workload.size();
+ (numThreads >= workload.size()) ? numThreads : workload.size();
if (workload.size() == 0) {
fatal("Must specify at least one workload!");
params->clock = clock;
params->phase = phase;
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = actual_num_threads;
params->cpu_id = cpu_id;
params->activity = activity;
params->workload = workload;
#endif // FULL_SYSTEM
+#if USE_CHECKER
params->checker = checker;
+#endif
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
return cpu;
}
-
-REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
-
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- */
-
-#include "cpu/op_class.hh"
-
-/** OpClass enum -> description string */
-const char *
-opClassStrings[Num_OpClasses] =
-{
- "No_OpClass",
- "IntAlu",
- "IntMult",
- "IntDiv",
- "FloatAdd",
- "FloatCmp",
- "FloatCvt",
- "FloatMult",
- "FloatDiv",
- "FloatSqrt",
- "MemRead",
- "MemWrite",
- "IprAccess",
- "InstPrefetch"
-};
-
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Steve Reinhardt
- * Nathan Binkert
+ * Authors: Nathan Binkert
*/
#ifndef __CPU__OP_CLASS_HH__
#define __CPU__OP_CLASS_HH__
-/**
- * @file
- * Definition of operation classes.
- */
+#include "enums/OpClass.hh"
-/**
- * Instruction operation classes. These classes are used for
- * assigning instructions to functional units.
+/*
+ * Do a bunch of wonky stuff to maintain backward compatability so I
+ * don't have to change code in a zillion places.
*/
-enum OpClass {
- No_OpClass = 0, ///< Instruction does not use a functional unit
- IntAluOp, ///< Integer ALU operaton (add/sub/logical)
- IntMultOp, ///< Integer multiply
- IntDivOp, ///< Integer divide
- FloatAddOp, ///< Floating point add/subtract
- FloatCmpOp, ///< Floating point comparison
- FloatCvtOp, ///< Floating point<->integer conversion
- FloatMultOp, ///< Floating point multiply
- FloatDivOp, ///< Floating point divide
- FloatSqrtOp, ///< Floating point square root
- MemReadOp, ///< Memory read port
- MemWriteOp, ///< Memory write port
- IprAccessOp, ///< Internal Processor Register read/write port
- InstPrefetchOp, ///< Instruction prefetch port (on I-cache)
- Num_OpClasses ///< Total number of operation classes
-};
+using Enums::OpClass;
+using Enums::No_OpClass;
+using Enums::Num_OpClass;
-/**
- * Array mapping OpClass enum values to strings. Defined in op_class.cc.
- */
-extern const char *opClassStrings[Num_OpClasses];
+const OpClass IntAluOp = Enums::IntAlu;
+const OpClass IntMultOp = Enums::IntMult;
+const OpClass IntDivOp = Enums::IntDiv;
+const OpClass FloatAddOp = Enums::FloatAdd;
+const OpClass FloatCmpOp = Enums::FloatCmp;
+const OpClass FloatCvtOp = Enums::FloatCvt;
+const OpClass FloatMultOp = Enums::FloatMult;
+const OpClass FloatDivOp = Enums::FloatDiv;
+const OpClass FloatSqrtOp = Enums::FloatSqrt;
+const OpClass MemReadOp = Enums::MemRead;
+const OpClass MemWriteOp = Enums::MemWrite;
+const OpClass IprAccessOp = Enums::IprAccess;
+const OpClass InstPrefetchOp = Enums::InstPrefetch;
+const OpClass Num_OpClasses = Num_OpClass;
#endif // __CPU__OP_CLASS_HH__
#include "cpu/inst_seq.hh"
#include "cpu/ozone/dyn_inst.hh"
#include "cpu/ozone/ozone_impl.hh"
-#include "sim/builder.hh"
+#include "params/OzoneChecker.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
//
// CheckerCPU Simulation Object
//
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
-
- Param<Counter> max_insts_any_thread;
- Param<Counter> max_insts_all_threads;
- Param<Counter> max_loads_any_thread;
- Param<Counter> max_loads_all_threads;
- Param<Tick> progress_interval;
-
-#if FULL_SYSTEM
- SimObjectParam<TheISA::ITB *> itb;
- SimObjectParam<TheISA::DTB *> dtb;
- SimObjectParam<System *> system;
- Param<int> cpu_id;
- Param<Tick> profile;
-#else
- SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
- Param<int> clock;
-
- Param<bool> defer_registration;
- Param<bool> exitOnError;
- Param<bool> updateOnError;
- Param<bool> warnOnlyOnLoadError;
- Param<bool> function_trace;
- Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
-
- INIT_PARAM(max_insts_any_thread,
- "terminate when any thread reaches this inst count"),
- INIT_PARAM(max_insts_all_threads,
- "terminate when all threads have reached this inst count"),
- INIT_PARAM(max_loads_any_thread,
- "terminate when any thread reaches this load count"),
- INIT_PARAM(max_loads_all_threads,
- "terminate when all threads have reached this load count"),
- INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
-
-#if FULL_SYSTEM
- INIT_PARAM(itb, "Instruction TLB"),
- INIT_PARAM(dtb, "Data TLB"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM(profile, ""),
-#else
- INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM(clock, "clock speed"),
-
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
- INIT_PARAM(exitOnError, "exit on error"),
- INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
- INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load "
- "result errors", false),
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
-
-
-CREATE_SIM_OBJECT(OzoneChecker)
+OzoneChecker *
+OzoneCheckerParams::create()
{
OzoneChecker::Params *params = new OzoneChecker::Params();
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = 0;
params->max_insts_all_threads = 0;
OzoneChecker *cpu = new OzoneChecker(params);
return cpu;
}
-
-REGISTER_SIM_OBJECT("OzoneChecker", OzoneChecker)
#include "cpu/ozone/cpu.hh"
#include "cpu/ozone/ozone_impl.hh"
#include "cpu/ozone/simple_params.hh"
-#include "sim/builder.hh"
+#include "params/DerivOzoneCPU.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
//
// OzoneCPU Simulation Object
//
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
- Param<int> clock;
- Param<int> numThreads;
-
-#if FULL_SYSTEM
-SimObjectParam<System *> system;
-Param<int> cpu_id;
-SimObjectParam<TheISA::ITB *> itb;
-SimObjectParam<TheISA::DTB *> dtb;
-Param<Tick> profile;
-
-Param<bool> do_quiesce;
-Param<bool> do_checkpoint_insts;
-Param<bool> do_statistics_insts;
-#else
-SimObjectVectorParam<Process *> workload;
-//SimObjectParam<PageTable *> page_table;
-#endif // FULL_SYSTEM
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-Param<Tick> progress_interval;
-
-//SimObjectParam<BaseCache *> icache;
-//SimObjectParam<BaseCache *> dcache;
-
-Param<unsigned> cachePorts;
-Param<unsigned> width;
-Param<unsigned> frontEndLatency;
-Param<unsigned> frontEndWidth;
-Param<unsigned> backEndLatency;
-Param<unsigned> backEndWidth;
-Param<unsigned> backEndSquashLatency;
-Param<unsigned> maxInstBufferSize;
-Param<unsigned> numPhysicalRegs;
-Param<unsigned> maxOutstandingMemOps;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> issueWidth;
-Param<unsigned> executeWidth;
-Param<unsigned> executeIntWidth;
-Param<unsigned> executeFloatWidth;
-Param<unsigned> executeBranchWidth;
-Param<unsigned> executeMemoryWidth;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<bool> lsqLimits;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<bool> decoupledFrontEnd;
-Param<int> dispatchWidth;
-Param<int> wbWidth;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string> smtFetchPolicy;
-Param<std::string> smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string> smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string> smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string> smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM(numThreads, "number of HW thread contexts"),
-
-#if FULL_SYSTEM
- INIT_PARAM(system, "System object"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM(itb, "Instruction translation buffer"),
- INIT_PARAM(dtb, "Data translation buffer"),
- INIT_PARAM(profile, ""),
- INIT_PARAM(do_quiesce, ""),
- INIT_PARAM(do_checkpoint_insts, ""),
- INIT_PARAM(do_statistics_insts, ""),
-#else
- INIT_PARAM(workload, "Processes to run"),
-// INIT_PARAM(page_table, "Page table"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
- INIT_PARAM_DFLT(max_insts_any_thread,
- "Terminate when any thread reaches this inst count",
- 0),
- INIT_PARAM_DFLT(max_insts_all_threads,
- "Terminate when all threads have reached"
- "this inst count",
- 0),
- INIT_PARAM_DFLT(max_loads_any_thread,
- "Terminate when any thread reaches this load count",
- 0),
- INIT_PARAM_DFLT(max_loads_all_threads,
- "Terminate when all threads have reached this load"
- "count",
- 0),
- INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
-
-// INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
-// INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
-
- INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
- INIT_PARAM_DFLT(width, "Width", 1),
- INIT_PARAM_DFLT(frontEndLatency, "Front end latency", 1),
- INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
- INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
- INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
- INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
- INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
- INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
- INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4),
-
- INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
- INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
- INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
- "delay"),
- INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
- INIT_PARAM(fetchWidth, "Fetch width"),
- INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
- INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
- "delay"),
- INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
- INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
- INIT_PARAM(decodeWidth, "Decode width"),
-
- INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
- "delay"),
- INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
- INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
- INIT_PARAM(renameWidth, "Rename width"),
-
- INIT_PARAM(commitToIEWDelay, "Commit to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(renameToIEWDelay, "Rename to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
- "to the IEW stage)"),
- INIT_PARAM(issueWidth, "Issue width"),
- INIT_PARAM(executeWidth, "Execute width"),
- INIT_PARAM(executeIntWidth, "Integer execute width"),
- INIT_PARAM(executeFloatWidth, "Floating point execute width"),
- INIT_PARAM(executeBranchWidth, "Branch execute width"),
- INIT_PARAM(executeMemoryWidth, "Memory execute width"),
-
- INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
- "delay"),
- INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
- INIT_PARAM(commitWidth, "Commit width"),
- INIT_PARAM(squashWidth, "Squash width"),
-
- INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
- INIT_PARAM(localPredictorSize, "Size of local predictor"),
- INIT_PARAM(localCtrBits, "Bits per counter"),
- INIT_PARAM(localHistoryTableSize, "Size of local history table"),
- INIT_PARAM(localHistoryBits, "Bits for the local history"),
- INIT_PARAM(globalPredictorSize, "Size of global predictor"),
- INIT_PARAM(globalCtrBits, "Bits per counter"),
- INIT_PARAM(globalHistoryBits, "Bits of history"),
- INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
- INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
- INIT_PARAM(BTBEntries, "Number of BTB entries"),
- INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
- INIT_PARAM(RASSize, "RAS size"),
-
- INIT_PARAM(LQEntries, "Number of load queue entries"),
- INIT_PARAM(SQEntries, "Number of store queue entries"),
- INIT_PARAM_DFLT(lsqLimits, "LSQ size limits dispatch", true),
- INIT_PARAM(LFSTSize, "Last fetched store table size"),
- INIT_PARAM(SSITSize, "Store set ID table size"),
-
- INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
- INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
- "registers"),
- INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
- INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
- INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
- INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
- INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
-
- INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
- INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
- INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
- INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
- INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
- INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
- INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
-CREATE_SIM_OBJECT(DerivOzoneCPU)
+DerivOzoneCPU *
+DerivOzoneCPUParams::create()
{
DerivOzoneCPU *cpu;
params->clock = clock;
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = actual_num_threads;
#if FULL_SYSTEM
return cpu;
}
-
-REGISTER_SIM_OBJECT("DerivOzoneCPU", DerivOzoneCPU)
#include "cpu/ozone/simple_impl.hh"
#include "cpu/ozone/simple_params.hh"
#include "mem/cache/base_cache.hh"
-#include "sim/builder.hh"
+#include "sim/SimpleOzoneCPU.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
//
// OzoneCPU Simulation Object
//
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
- Param<int> clock;
- Param<int> numThreads;
-
-#if FULL_SYSTEM
-SimObjectParam<System *> system;
-Param<int> cpu_id;
-SimObjectParam<TheISA::ITB *> itb;
-SimObjectParam<TheISA::DTB *> dtb;
-#else
-SimObjectVectorParam<Process *> workload;
-//SimObjectParam<PageTable *> page_table;
-#endif // FULL_SYSTEM
-
-SimObjectParam<FunctionalMemory *> mem;
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-
-SimObjectParam<BaseCache *> icache;
-SimObjectParam<BaseCache *> dcache;
-
-Param<unsigned> cachePorts;
-Param<unsigned> width;
-Param<unsigned> frontEndWidth;
-Param<unsigned> backEndWidth;
-Param<unsigned> backEndSquashLatency;
-Param<unsigned> backEndLatency;
-Param<unsigned> maxInstBufferSize;
-Param<unsigned> numPhysicalRegs;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> issueWidth;
-Param<unsigned> executeWidth;
-Param<unsigned> executeIntWidth;
-Param<unsigned> executeFloatWidth;
-Param<unsigned> executeBranchWidth;
-Param<unsigned> executeMemoryWidth;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<bool> decoupledFrontEnd;
-Param<int> dispatchWidth;
-Param<int> wbWidth;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string> smtFetchPolicy;
-Param<std::string> smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string> smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string> smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string> smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM(numThreads, "number of HW thread contexts"),
-
-#if FULL_SYSTEM
- INIT_PARAM(system, "System object"),
- INIT_PARAM(cpu_id, "processor ID"),
- INIT_PARAM(itb, "Instruction translation buffer"),
- INIT_PARAM(dtb, "Data translation buffer"),
-#else
- INIT_PARAM(workload, "Processes to run"),
-// INIT_PARAM(page_table, "Page table"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM_DFLT(mem, "Memory", NULL),
-
- INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
- INIT_PARAM_DFLT(max_insts_any_thread,
- "Terminate when any thread reaches this inst count",
- 0),
- INIT_PARAM_DFLT(max_insts_all_threads,
- "Terminate when all threads have reached"
- "this inst count",
- 0),
- INIT_PARAM_DFLT(max_loads_any_thread,
- "Terminate when any thread reaches this load count",
- 0),
- INIT_PARAM_DFLT(max_loads_all_threads,
- "Terminate when all threads have reached this load"
- "count",
- 0),
-
- INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
- INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
-
- INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
- INIT_PARAM_DFLT(width, "Width", 1),
- INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
- INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
- INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
- INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
- INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
- INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
-
- INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
- INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
- INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
- "delay"),
- INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
- INIT_PARAM(fetchWidth, "Fetch width"),
- INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
- INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
- "delay"),
- INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
- INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
- INIT_PARAM(decodeWidth, "Decode width"),
-
- INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
- "delay"),
- INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
- INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
- INIT_PARAM(renameWidth, "Rename width"),
-
- INIT_PARAM(commitToIEWDelay, "Commit to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(renameToIEWDelay, "Rename to "
- "Issue/Execute/Writeback delay"),
- INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
- "to the IEW stage)"),
- INIT_PARAM(issueWidth, "Issue width"),
- INIT_PARAM(executeWidth, "Execute width"),
- INIT_PARAM(executeIntWidth, "Integer execute width"),
- INIT_PARAM(executeFloatWidth, "Floating point execute width"),
- INIT_PARAM(executeBranchWidth, "Branch execute width"),
- INIT_PARAM(executeMemoryWidth, "Memory execute width"),
-
- INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
- "delay"),
- INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
- INIT_PARAM(commitWidth, "Commit width"),
- INIT_PARAM(squashWidth, "Squash width"),
-
- INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
- INIT_PARAM(localPredictorSize, "Size of local predictor"),
- INIT_PARAM(localCtrBits, "Bits per counter"),
- INIT_PARAM(localHistoryTableSize, "Size of local history table"),
- INIT_PARAM(localHistoryBits, "Bits for the local history"),
- INIT_PARAM(globalPredictorSize, "Size of global predictor"),
- INIT_PARAM(globalCtrBits, "Bits per counter"),
- INIT_PARAM(globalHistoryBits, "Bits of history"),
- INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
- INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
- INIT_PARAM(BTBEntries, "Number of BTB entries"),
- INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
- INIT_PARAM(RASSize, "RAS size"),
-
- INIT_PARAM(LQEntries, "Number of load queue entries"),
- INIT_PARAM(SQEntries, "Number of store queue entries"),
- INIT_PARAM(LFSTSize, "Last fetched store table size"),
- INIT_PARAM(SSITSize, "Store set ID table size"),
-
- INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
- INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
- "registers"),
- INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
- INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
- INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
- INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
- INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
-
- INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
- INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
- INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
- INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
- INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
- INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
- INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
- INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
-CREATE_SIM_OBJECT(SimpleOzoneCPU)
+SimpleOzoneCPU *
+SimpleOzoneCPUParams::create()
{
SimpleOzoneCPU *cpu;
params->clock = clock;
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = actual_num_threads;
#if FULL_SYSTEM
return cpu;
}
-
-REGISTER_SIM_OBJECT("SimpleOzoneCPU", SimpleOzoneCPU)
-
#include "cpu/simple/atomic.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/AtomicSimpleCPU.hh"
#include "sim/system.hh"
using namespace std;
AtomicSimpleCPU::resume()
{
if (_status != SwitchedOut && _status != Idle) {
- assert(system->getMemoryMode() == System::Atomic);
+ assert(system->getMemoryMode() == Enums::atomic);
changeState(SimObject::Running);
if (thread->status() == ThreadContext::Active) {
//
// AtomicSimpleCPU Simulation Object
//
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
- Param<Counter> max_insts_any_thread;
- Param<Counter> max_insts_all_threads;
- Param<Counter> max_loads_any_thread;
- Param<Counter> max_loads_all_threads;
- Param<Tick> progress_interval;
- SimObjectParam<System *> system;
- Param<int> cpu_id;
-
-#if FULL_SYSTEM
- SimObjectParam<TheISA::ITB *> itb;
- SimObjectParam<TheISA::DTB *> dtb;
- Param<Tick> profile;
-
- Param<bool> do_quiesce;
- Param<bool> do_checkpoint_insts;
- Param<bool> do_statistics_insts;
-#else
- SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
-
- Param<int> clock;
- Param<int> phase;
-
- Param<bool> defer_registration;
- Param<int> width;
- Param<bool> function_trace;
- Param<Tick> function_trace_start;
- Param<bool> simulate_stalls;
-
-END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
- INIT_PARAM(max_insts_any_thread,
- "terminate when any thread reaches this inst count"),
- INIT_PARAM(max_insts_all_threads,
- "terminate when all threads have reached this inst count"),
- INIT_PARAM(max_loads_any_thread,
- "terminate when any thread reaches this load count"),
- INIT_PARAM(max_loads_all_threads,
- "terminate when all threads have reached this load count"),
- INIT_PARAM(progress_interval, "Progress interval"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(cpu_id, "processor ID"),
-
-#if FULL_SYSTEM
- INIT_PARAM(itb, "Instruction TLB"),
- INIT_PARAM(dtb, "Data TLB"),
- INIT_PARAM(profile, ""),
- INIT_PARAM(do_quiesce, ""),
- INIT_PARAM(do_checkpoint_insts, ""),
- INIT_PARAM(do_statistics_insts, ""),
-#else
- INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM_DFLT(phase, "clock phase", 0),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
- INIT_PARAM(width, "cpu width"),
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace"),
- INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
-
-END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
-
-CREATE_SIM_OBJECT(AtomicSimpleCPU)
+AtomicSimpleCPU *
+AtomicSimpleCPUParams::create()
{
AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
params->do_checkpoint_insts = do_checkpoint_insts;
params->do_statistics_insts = do_statistics_insts;
#else
- params->process = workload;
+ if (workload.size() != 1)
+ panic("only one workload allowed");
+ params->process = workload[0];
#endif
AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
return cpu;
}
-
-REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
-
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
-#include "sim/builder.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"
#include "sim/host.hh"
#include "cpu/simple/timing.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/TimingSimpleCPU.hh"
#include "sim/system.hh"
using namespace std;
TimingSimpleCPU::resume()
{
if (_status != SwitchedOut && _status != Idle) {
- assert(system->getMemoryMode() == System::Timing);
+ assert(system->getMemoryMode() == Enums::timing);
// Delete the old event if it existed.
if (fetchEvent) {
//
// TimingSimpleCPU Simulation Object
//
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
- Param<Counter> max_insts_any_thread;
- Param<Counter> max_insts_all_threads;
- Param<Counter> max_loads_any_thread;
- Param<Counter> max_loads_all_threads;
- Param<Tick> progress_interval;
- SimObjectParam<System *> system;
- Param<int> cpu_id;
-
-#if FULL_SYSTEM
- SimObjectParam<TheISA::ITB *> itb;
- SimObjectParam<TheISA::DTB *> dtb;
- Param<Tick> profile;
-
- Param<bool> do_quiesce;
- Param<bool> do_checkpoint_insts;
- Param<bool> do_statistics_insts;
-#else
- SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
-
- Param<int> clock;
- Param<int> phase;
-
- Param<bool> defer_registration;
- Param<int> width;
- Param<bool> function_trace;
- Param<Tick> function_trace_start;
- Param<bool> simulate_stalls;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
- INIT_PARAM(max_insts_any_thread,
- "terminate when any thread reaches this inst count"),
- INIT_PARAM(max_insts_all_threads,
- "terminate when all threads have reached this inst count"),
- INIT_PARAM(max_loads_any_thread,
- "terminate when any thread reaches this load count"),
- INIT_PARAM(max_loads_all_threads,
- "terminate when all threads have reached this load count"),
- INIT_PARAM(progress_interval, "Progress interval"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(cpu_id, "processor ID"),
-
-#if FULL_SYSTEM
- INIT_PARAM(itb, "Instruction TLB"),
- INIT_PARAM(dtb, "Data TLB"),
- INIT_PARAM(profile, ""),
- INIT_PARAM(do_quiesce, ""),
- INIT_PARAM(do_checkpoint_insts, ""),
- INIT_PARAM(do_statistics_insts, ""),
-#else
- INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
- INIT_PARAM(clock, "clock speed"),
- INIT_PARAM_DFLT(phase, "clock phase", 0),
- INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
- INIT_PARAM(width, "cpu width"),
- INIT_PARAM(function_trace, "Enable function trace"),
- INIT_PARAM(function_trace_start, "Cycle to start function trace"),
- INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
-
-END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
-
-CREATE_SIM_OBJECT(TimingSimpleCPU)
+TimingSimpleCPU *
+TimingSimpleCPUParams::create()
{
TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
- params->name = getInstanceName();
+ params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
params->do_checkpoint_insts = do_checkpoint_insts;
params->do_statistics_insts = do_statistics_insts;
#else
- params->process = workload;
+ if (workload.size() != 1)
+ panic("only one workload allowed");
+ params->process = workload[0];
#endif
TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
return cpu;
}
-
-REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
-
#include "cpu/trace/opt_cpu.hh"
#include "cpu/trace/reader/mem_trace_reader.hh"
-
-#include "sim/builder.hh"
+#include "params/OptCPU.hh"
#include "sim/sim_events.hh"
using namespace std;
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(OptCPU)
-
- SimObjectParam<MemTraceReader *> data_trace;
- Param<int> size;
- Param<int> block_size;
-Param<int> assoc;
-
-END_DECLARE_SIM_OBJECT_PARAMS(OptCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(OptCPU)
-
- INIT_PARAM_DFLT(data_trace, "memory trace", NULL),
- INIT_PARAM(size, "cache size"),
- INIT_PARAM(block_size, "block size"),
- INIT_PARAM(assoc,"associativity")
-
-END_INIT_SIM_OBJECT_PARAMS(OptCPU)
-
-CREATE_SIM_OBJECT(OptCPU)
+OptCPU *
+OptCPUParams::create()
{
- return new OptCPU(getInstanceName(),
- data_trace,
- block_size,
- size,
- assoc);
+ return new OptCPU(name, data_trace, block_size, size, assoc);
}
-
-REGISTER_SIM_OBJECT("OptCPU", OptCPU)
*/
#include <sstream>
-#include "cpu/trace/reader/ibm_reader.hh"
-#include "sim/builder.hh"
#include "base/misc.hh" // for fatal
+#include "cpu/trace/reader/ibm_reader.hh"
+#include "params/IBMReader.hh"
using namespace std;
return 0;
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IBMReader)
-
- Param<string> filename;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IBMReader)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IBMReader)
-
- INIT_PARAM(filename, "trace file")
-
-END_INIT_SIM_OBJECT_PARAMS(IBMReader)
-
-
-CREATE_SIM_OBJECT(IBMReader)
+IBMReader *
+IBMReaderParams::create()
{
- return new IBMReader(getInstanceName(), filename);
+ return new IBMReader(name, filename);
}
-
-REGISTER_SIM_OBJECT("IBMReader", IBMReader)
*/
#include <sstream>
-#include "cpu/trace/reader/itx_reader.hh"
-#include "sim/builder.hh"
#include "base/misc.hh" // for fatal
+#include "cpu/trace/reader/itx_reader.hh"
+#include "params/ITXReader.hh"
using namespace std;
return 0;
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
-
- Param<string> filename;
-
-END_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(ITXReader)
-
- INIT_PARAM(filename, "trace file")
-
-END_INIT_SIM_OBJECT_PARAMS(ITXReader)
-
-
-CREATE_SIM_OBJECT(ITXReader)
+ITXReader *
+ITXReaderParams::create()
{
- return new ITXReader(getInstanceName(), filename);
+ return new ITXReader(name, filename);
}
-
-REGISTER_SIM_OBJECT("ITXReader", ITXReader)
#include "cpu/trace/reader/m5_reader.hh"
#include "mem/trace/m5_format.hh"
#include "mem/mem_cmd.hh"
-#include "sim/builder.hh"
+#include "params/M5Reader.hh"
using namespace std;
return ref.cycle;
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
-
- Param<string> filename;
-
-END_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(M5Reader)
-
- INIT_PARAM(filename, "trace file")
-
-END_INIT_SIM_OBJECT_PARAMS(M5Reader)
-
-
-CREATE_SIM_OBJECT(M5Reader)
+M5Reader *
+M5ReaderParams::create()
{
- return new M5Reader(getInstanceName(), filename);
+ return new M5Reader(name, filename);
}
-
-REGISTER_SIM_OBJECT("M5Reader", M5Reader)
+++ /dev/null
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
- */
-
-/**
- * @file
- * SimObject Declaration of pure virtual MemTraceReader class.
- */
-
-#include "cpu/trace/reader/mem_trace_reader.hh"
-#include "sim/param.hh"
-
-DEFINE_SIM_OBJECT_CLASS_NAME("MemTraceReader", MemTraceReader);
#include "cpu/trace/reader/mem_trace_reader.hh"
#include "mem/base_mem.hh" // For PARAM constructor
#include "mem/mem_interface.hh"
-#include "sim/builder.hh"
+#include "params/TraceCPU.hh"
#include "sim/sim_events.hh"
using namespace std;
return "TraceCPU tick event";
}
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
-
- SimObjectParam<BaseMem *> icache;
- SimObjectParam<BaseMem *> dcache;
- SimObjectParam<MemTraceReader *> data_trace;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU)
-
- INIT_PARAM_DFLT(icache, "instruction cache", NULL),
- INIT_PARAM_DFLT(dcache, "data cache", NULL),
- INIT_PARAM_DFLT(data_trace, "data trace", NULL)
-
-END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
-
-CREATE_SIM_OBJECT(TraceCPU)
+TraceCPU *
+TraceCPUParams::create()
{
- return new TraceCPU(getInstanceName(),
+ return new TraceCPU(name,
(icache) ? icache->getInterface() : NULL,
(dcache) ? dcache->getInterface() : NULL,
data_trace);
}
-
-REGISTER_SIM_OBJECT("TraceCPU", TraceCPU)
-
class Sinic(EtherDevBase):
type = 'Sinic'
+ cxx_namespace = 'Sinic'
+ cxx_class = 'Device'
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
tx_max_copy = Param.MemorySize('16kB', "tx max copy")
class SinicInt(EtherInt):
type = 'SinicInt'
+ cxx_namespace = 'Sinic'
+ cxx_class = 'Interface'
+
device = Param.Sinic("Ethernet device of this interface")
Source('etherint.cc')
Source('etherlink.cc')
Source('etherpkt.cc')
- Source('ethertap.cc')
+ Source('ethertap.cc')
Source('i8254xGBe.cc')
Source('ide_ctrl.cc')
Source('ide_disk.cc')
Source('platform.cc')
Source('simconsole.cc')
Source('simple_disk.cc')
- #Source('sinic.cc')
+ Source('sinic.cc')
Source('uart.cc')
Source('uart8250.cc')
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/physical.hh"
-#include "sim/builder.hh"
+#include "params/AlphaConsole.hh"
#include "sim/sim_object.hh"
using namespace std;
using namespace AlphaISA;
-AlphaConsole::AlphaConsole(Params *p)
- : BasicPioDevice(p), disk(p->disk),
- console(params()->cons), system(params()->alpha_sys), cpu(params()->cpu)
+AlphaConsole::AlphaConsole(const Params *p)
+ : BasicPioDevice(p), disk(p->disk), console(p->sim_console),
+ system(p->system), cpu(p->cpu)
{
pioSize = sizeof(struct AlphaAccess);
alphaAccess->unserialize(cp, section);
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
-
- SimObjectParam<SimConsole *> sim_console;
- SimObjectParam<SimpleDisk *> disk;
- Param<Addr> pio_addr;
- SimObjectParam<AlphaSystem *> system;
- SimObjectParam<BaseCPU *> cpu;
- SimObjectParam<Platform *> platform;
- Param<Tick> pio_latency;
-
-END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
-
- INIT_PARAM(sim_console, "The Simulator Console"),
- INIT_PARAM(disk, "Simple Disk"),
- INIT_PARAM(pio_addr, "Device Address"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(cpu, "Processor"),
- INIT_PARAM(platform, "platform"),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000)
-
-END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
-
-CREATE_SIM_OBJECT(AlphaConsole)
+AlphaConsole *
+AlphaConsoleParams::create()
{
- AlphaConsole::Params *p = new AlphaConsole::Params;
- p->name = getInstanceName();
- p->platform = platform;
- p->pio_addr = pio_addr;
- p->pio_delay = pio_latency;
- p->cons = sim_console;
- p->disk = disk;
- p->alpha_sys = system;
- p->system = system;
- p->cpu = cpu;
- return new AlphaConsole(p);
+ return new AlphaConsole(this);
}
-
-REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
#include "base/range.hh"
#include "dev/alpha/access.h"
#include "dev/io_device.hh"
+#include "params/AlphaConsole.hh"
#include "sim/host.hh"
#include "sim/sim_object.hh"
BaseCPU *cpu;
public:
- struct Params : public BasicPioDevice::Params
- {
- SimConsole *cons;
- SimpleDisk *disk;
- AlphaSystem *alpha_sys;
- BaseCPU *cpu;
- };
- protected:
- const Params *params() const {return (const Params *)_params; }
+ typedef AlphaConsoleParams Params;
+ AlphaConsole(const Params *p);
- public:
-
- /** Standard Constructor */
- AlphaConsole(Params *p);
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
virtual void startup();
#include "dev/alpha/tsunami_pchip.hh"
#include "dev/alpha/tsunami_io.hh"
#include "dev/alpha/tsunami.hh"
-#include "sim/builder.hh"
+#include "params/Tsunami.hh"
#include "sim/system.hh"
using namespace std;
UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
-
- SimObjectParam<System *> system;
- SimObjectParam<IntrControl *> intrctrl;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
-
- INIT_PARAM(system, "system"),
- INIT_PARAM(intrctrl, "interrupt controller")
-
-END_INIT_SIM_OBJECT_PARAMS(Tsunami)
-
-CREATE_SIM_OBJECT(Tsunami)
+Tsunami *
+TsunamiParams::create()
{
- return new Tsunami(getInstanceName(), system, intrctrl);
+ return new Tsunami(name, system, intrctrl);
}
-
-REGISTER_SIM_OBJECT("Tsunami", Tsunami)
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh"
-#include "sim/builder.hh"
+#include "params/TsunamiCChip.hh"
#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
-TsunamiCChip::TsunamiCChip(Params *p)
+TsunamiCChip::TsunamiCChip(const Params *p)
: BasicPioDevice(p), tsunami(p->tsunami)
{
pioSize = 0x10000000;
UNSERIALIZE_SCALAR(drir);
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
-
- Param<Addr> pio_addr;
- Param<Tick> pio_latency;
- SimObjectParam<Platform *> platform;
- SimObjectParam<System *> system;
- SimObjectParam<Tsunami *> tsunami;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
-
- INIT_PARAM(pio_addr, "Device Address"),
- INIT_PARAM(pio_latency, "Programmed IO latency"),
- INIT_PARAM(platform, "platform"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(tsunami, "Tsunami")
-
-END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
-
-CREATE_SIM_OBJECT(TsunamiCChip)
+TsunamiCChip *
+TsunamiCChipParams::create()
{
- TsunamiCChip::Params *p = new TsunamiCChip::Params;
- p->name = getInstanceName();
- p->pio_addr = pio_addr;
- p->pio_delay = pio_latency;
- p->platform = platform;
- p->system = system;
- p->tsunami = tsunami;
- return new TsunamiCChip(p);
+ return new TsunamiCChip(this);
}
-
-REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
#ifndef __TSUNAMI_CCHIP_HH__
#define __TSUNAMI_CCHIP_HH__
-#include "dev/alpha/tsunami.hh"
#include "base/range.hh"
+#include "dev/alpha/tsunami.hh"
#include "dev/io_device.hh"
-
+#include "params/TsunamiCChip.hh"
/**
* Tsunami CChip CSR Emulation. This device includes all the interrupt
uint64_t itint;
public:
- struct Params : public BasicPioDevice::Params
- {
- Tsunami *tsunami;
- };
- protected:
- const Params *params() const {return (const Params *)_params; }
-
- public:
+ typedef TsunamiCChipParams Params;
/**
* Initialize the Tsunami CChip by setting all of the
* device register to 0.
* @param p params struct
*/
- TsunamiCChip(Params *p);
+ TsunamiCChip(const Params *p);
+
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
virtual Tick read(PacketPtr pkt);
#include <string>
#include <vector>
+#include "base/time.hh"
#include "base/trace.hh"
#include "dev/pitreg.h"
#include "dev/rtcreg.h"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh"
-#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
-TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami, const vector<int> &t,
- bool bcd, Tick i)
- : _name(n), event(tsunami, i), addr(0), year_is_bcd(bcd)
+TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami,
+ const TsunamiIO::Params *p)
+ : _name(n), event(tsunami, p->frequency), addr(0)
{
memset(clock_data, 0, sizeof(clock_data));
stat_regA = RTCA_32768HZ | RTCA_1024HZ;
stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR;
- struct tm tm;
- parseTime(t, &tm);
+ year = p->time.tm_year;
- year = tm.tm_year;
-
- if (year_is_bcd) {
+ if (p->year_is_bcd) {
// The datasheet says that the year field can be either BCD or
// years since 1900. Linux seems to be happy with years since
// 1900.
}
// Unix is 0-11 for month, data seet says start at 1
- mon = tm.tm_mon + 1;
- mday = tm.tm_mday;
- hour = tm.tm_hour;
- min = tm.tm_min;
- sec = tm.tm_sec;
+ mon = p->time.tm_mon + 1;
+ mday = p->time.tm_mday;
+ hour = p->time.tm_hour;
+ min = p->time.tm_min;
+ sec = p->time.tm_sec;
// Datasheet says 1 is sunday
- wday = tm.tm_wday + 1;
+ wday = p->time.tm_wday + 1;
- DPRINTFN("Real-time clock set to %s", asctime(&tm));
+ DPRINTFN("Real-time clock set to %s", asctime(&p->time));
}
void
return "tsunami 8254 Interval timer";
}
-TsunamiIO::TsunamiIO(Params *p)
+TsunamiIO::TsunamiIO(const Params *p)
: BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"),
- rtc(p->name + ".rtc", p->tsunami, p->init_time, p->year_is_bcd,
- p->frequency)
+ rtc(p->name + ".rtc", p->tsunami, p)
{
pioSize = 0x100;
rtc.unserialize("rtc", cp, section);
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
-
- Param<Addr> pio_addr;
- Param<Tick> pio_latency;
- Param<Tick> frequency;
- SimObjectParam<Platform *> platform;
- SimObjectParam<System *> system;
- VectorParam<int> time;
- Param<bool> year_is_bcd;
- SimObjectParam<Tsunami *> tsunami;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
-
- INIT_PARAM(pio_addr, "Device Address"),
- INIT_PARAM(pio_latency, "Programmed IO latency"),
- INIT_PARAM(frequency, "clock interrupt frequency"),
- INIT_PARAM(platform, "platform"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(time, "System time to use (0 for actual time"),
- INIT_PARAM(year_is_bcd, ""),
- INIT_PARAM(tsunami, "Tsunami")
-
-END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
-
-CREATE_SIM_OBJECT(TsunamiIO)
+TsunamiIO *
+TsunamiIOParams::create()
{
- TsunamiIO::Params *p = new TsunamiIO::Params;
- p->frequency = frequency;
- p->name = getInstanceName();
- p->pio_addr = pio_addr;
- p->pio_delay = pio_latency;
- p->platform = platform;
- p->system = system;
- p->init_time = time;
- p->year_is_bcd = year_is_bcd;
- p->tsunami = tsunami;
- return new TsunamiIO(p);
+ return new TsunamiIO(this);
}
-
-REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)
#ifndef __DEV_TSUNAMI_IO_HH__
#define __DEV_TSUNAMI_IO_HH__
-#include "dev/io_device.hh"
#include "base/range.hh"
#include "dev/alpha/tsunami.hh"
+#include "dev/io_device.hh"
+#include "params/TsunamiIO.hh"
#include "sim/eventq.hh"
/**
/** Current RTC register address/index */
int addr;
- /** should the year be interpreted as BCD? */
- bool year_is_bcd;
-
/** Data for real-time clock function */
union {
uint8_t clock_data[10];
public:
RTC(const std::string &name, Tsunami* tsunami,
- const std::vector<int> &t, bool bcd, Tick i);
+ const TsunamiIOParams *params);
/** RTC address port: write address of RTC RAM data to access */
void writeAddr(const uint8_t data);
*/
Tick frequency() const;
- struct Params : public BasicPioDevice::Params
- {
- Tick frequency;
- Tsunami *tsunami;
- std::vector<int> init_time;
- bool year_is_bcd;
- };
-
- protected:
- const Params *params() const { return (const Params*)_params; }
-
public:
+ typedef TsunamiIOParams Params;
/**
* Initialize all the data for devices supported by Tsunami I/O.
* @param p pointer to Params struct
*/
- TsunamiIO(Params *p);
+ TsunamiIO(const Params *p);
+
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
#include "dev/alpha/tsunami.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
-TsunamiPChip::TsunamiPChip(Params *p)
+TsunamiPChip::TsunamiPChip(const Params *p)
: BasicPioDevice(p)
{
pioSize = 0x1000;
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
-
- Param<Addr> pio_addr;
- Param<Tick> pio_latency;
- SimObjectParam<Platform *> platform;
- SimObjectParam<System *> system;
- SimObjectParam<Tsunami *> tsunami;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
-
- INIT_PARAM(pio_addr, "Device Address"),
- INIT_PARAM(pio_latency, "Programmed IO latency"),
- INIT_PARAM(platform, "platform"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(tsunami, "Tsunami")
-
-END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
-
-CREATE_SIM_OBJECT(TsunamiPChip)
+TsunamiPChip *
+TsunamiPChipParams::create()
{
- TsunamiPChip::Params *p = new TsunamiPChip::Params;
- p->name = getInstanceName();
- p->pio_addr = pio_addr;
- p->pio_delay = pio_latency;
- p->platform = platform;
- p->system = system;
- p->tsunami = tsunami;
- return new TsunamiPChip(p);
+ return new TsunamiPChip(this);
}
-
-REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
#ifndef __TSUNAMI_PCHIP_HH__
#define __TSUNAMI_PCHIP_HH__
-#include "dev/alpha/tsunami.hh"
#include "base/range.hh"
+#include "dev/alpha/tsunami.hh"
#include "dev/io_device.hh"
+#include "params/TsunamiPChip.hh"
/**
* A very simple implementation of the Tsunami PCI interface chips.
uint64_t tba[4];
public:
- struct Params : public BasicPioDevice::Params
- {
- Tsunami *tsunami;
- };
- protected:
- const Params *params() const { return (const Params*)_params; }
-
- public:
+ typedef TsunamiPChipParams Params;
/**
* Register the PChip with the mmu and init all wsba, wsm, and tba to 0
* @param p pointer to the parameters struct
*/
- TsunamiPChip(Params *p);
+ TsunamiPChip(const Params *p);
+
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
/**
* Translate a PCI bus address to a memory address for DMA.
#include "dev/baddev.hh"
#include "dev/platform.hh"
#include "mem/port.hh"
-#include "sim/builder.hh"
+#include "params/BadDevice.hh"
#include "sim/system.hh"
using namespace std;
using namespace TheISA;
BadDevice::BadDevice(Params *p)
- : BasicPioDevice(p), devname(p->device_name)
+ : BasicPioDevice(p), devname(p->devicename)
{
pioSize = 0x10;
}
M5_DUMMY_RETURN
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
-
- Param<string> devicename;
- Param<Addr> pio_addr;
- SimObjectParam<System *> system;
- SimObjectParam<Platform *> platform;
- Param<Tick> pio_latency;
-
-END_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(BadDevice)
-
- INIT_PARAM(devicename, "Name of device to error on"),
- INIT_PARAM(pio_addr, "Device Address"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(platform, "platform"),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000)
-
-END_INIT_SIM_OBJECT_PARAMS(BadDevice)
-
-CREATE_SIM_OBJECT(BadDevice)
+BadDevice *
+BadDeviceParams::create()
{
- BadDevice::Params *p = new BadDevice::Params;
- p->name =getInstanceName();
- p->platform = platform;
- p->pio_addr = pio_addr;
- p->pio_delay = pio_latency;
- p->system = system;
- p->device_name = devicename;
- return new BadDevice(p);
+ return new BadDevice(this);
}
-
-REGISTER_SIM_OBJECT("BadDevice", BadDevice)
#include "base/range.hh"
#include "dev/io_device.hh"
-
+#include "params/BadDevice.hh"
/**
* BadDevice
std::string devname;
public:
- struct Params : public BasicPioDevice::Params
- {
- std::string device_name;
- };
+ typedef BadDeviceParams Params;
+
protected:
- const Params *params() const { return (const Params *)_params; }
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
public:
/**
#include "base/misc.hh"
#include "base/trace.hh"
#include "dev/disk_image.hh"
-#include "sim/builder.hh"
+#include "params/CowDiskImage.hh"
+#include "params/RawDiskImage.hh"
#include "sim/sim_exit.hh"
#include "sim/byteswap.hh"
return stream.tellp() - pos;
}
-DEFINE_SIM_OBJECT_CLASS_NAME("DiskImage", DiskImage)
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(RawDiskImage)
-
- Param<string> image_file;
- Param<bool> read_only;
-
-END_DECLARE_SIM_OBJECT_PARAMS(RawDiskImage)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(RawDiskImage)
-
- INIT_PARAM(image_file, "disk image file"),
- INIT_PARAM_DFLT(read_only, "read only image", false)
-
-END_INIT_SIM_OBJECT_PARAMS(RawDiskImage)
-
-
-CREATE_SIM_OBJECT(RawDiskImage)
+RawDiskImage *
+RawDiskImageParams::create()
{
- return new RawDiskImage(getInstanceName(), image_file, read_only);
+ return new RawDiskImage(name, image_file, read_only);
}
-REGISTER_SIM_OBJECT("RawDiskImage", RawDiskImage)
-
////////////////////////////////////////////////////////////////////////
//
// Copy on Write Disk image
open(cowFilename);
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(CowDiskImage)
-
- SimObjectParam<DiskImage *> child;
- Param<string> image_file;
- Param<int> table_size;
- Param<bool> read_only;
-
-END_DECLARE_SIM_OBJECT_PARAMS(CowDiskImage)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(CowDiskImage)
-
- INIT_PARAM(child, "child image"),
- INIT_PARAM_DFLT(image_file, "disk image file", ""),
- INIT_PARAM_DFLT(table_size, "initial table size", 65536),
- INIT_PARAM_DFLT(read_only, "don't write back to the copy-on-write file",
- true)
-
-END_INIT_SIM_OBJECT_PARAMS(CowDiskImage)
-
-
-CREATE_SIM_OBJECT(CowDiskImage)
+CowDiskImage *
+CowDiskImageParams::create()
{
if (((string)image_file).empty())
- return new CowDiskImage(getInstanceName(), child, table_size);
+ return new CowDiskImage(name, child, table_size);
else
- return new CowDiskImage(getInstanceName(), child, table_size,
+ return new CowDiskImage(name, child, table_size,
image_file, read_only);
}
-
-REGISTER_SIM_OBJECT("CowDiskImage", CowDiskImage)
#include "dev/etherdump.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
-#include "sim/builder.hh"
+#include "params/EtherBus.hh"
#include "sim/core.hh"
using namespace std;
return true;
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherBus)
-
- Param<bool> loopback;
- Param<double> speed;
- SimObjectParam<EtherDump *> packet_dump;
-
-END_DECLARE_SIM_OBJECT_PARAMS(EtherBus)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(EtherBus)
-
- INIT_PARAM(loopback, "send the packet back to the sending interface"),
- INIT_PARAM(speed, "bus speed in ticks per byte"),
- INIT_PARAM(packet_dump, "object to dump network packets to")
-
-END_INIT_SIM_OBJECT_PARAMS(EtherBus)
-
-CREATE_SIM_OBJECT(EtherBus)
+EtherBus *
+EtherBusParams::create()
{
- return new EtherBus(getInstanceName(), speed, loopback, packet_dump);
+ return new EtherBus(name, speed, loopback, dump);
}
-
-REGISTER_SIM_OBJECT("EtherBus", EtherBus)
#include "base/misc.hh"
#include "base/output.hh"
#include "dev/etherdump.hh"
-#include "sim/builder.hh"
+#include "params/EtherDump.hh"
#include "sim/core.hh"
using std::string;
stream.flush();
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
-
- Param<string> file;
- Param<int> maxlen;
-
-END_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(EtherDump)
-
- INIT_PARAM(file, "file to dump packets to"),
- INIT_PARAM(maxlen, "max portion of packet data to dump")
-
-END_INIT_SIM_OBJECT_PARAMS(EtherDump)
-
-CREATE_SIM_OBJECT(EtherDump)
+EtherDump *
+EtherDumpParams::create()
{
- return new EtherDump(getInstanceName(), simout.resolve(file), maxlen);
+ return new EtherDump(name, simout.resolve(file), maxlen);
}
-
-REGISTER_SIM_OBJECT("EtherDump", EtherDump)
#include "dev/etherint.hh"
#include "base/misc.hh"
-#include "sim/param.hh"
#include "sim/sim_object.hh"
void
peer = p;
}
-
-DEFINE_SIM_OBJECT_CLASS_NAME("EtherInt", EtherInt)
-
#include "dev/etherint.hh"
#include "dev/etherlink.hh"
#include "dev/etherpkt.hh"
-#include "sim/builder.hh"
+#include "params/EtherLink.hh"
#include "sim/serialize.hh"
#include "sim/system.hh"
#include "sim/core.hh"
REGISTER_SERIALIZEABLE("LinkDelayEvent", LinkDelayEvent)
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherLink)
-
- SimObjectParam<EtherInt *> int1;
- SimObjectParam<EtherInt *> int2;
- Param<double> speed;
- Param<Tick> delay;
- Param<Tick> delay_var;
- SimObjectParam<EtherDump *> dump;
-
-END_DECLARE_SIM_OBJECT_PARAMS(EtherLink)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(EtherLink)
-
- INIT_PARAM(int1, "interface 1"),
- INIT_PARAM(int2, "interface 2"),
- INIT_PARAM(speed, "link speed in bits per second"),
- INIT_PARAM(delay, "transmit delay of packets in us"),
- INIT_PARAM(delay_var, "Difference in amount of time to traverse wire"),
- INIT_PARAM(dump, "object to dump network packets to")
-
-END_INIT_SIM_OBJECT_PARAMS(EtherLink)
-
-CREATE_SIM_OBJECT(EtherLink)
+EtherLink *
+EtherLinkParams::create()
{
- return new EtherLink(getInstanceName(), int1, int2, speed, delay, delay_var,
- dump);
+ return new EtherLink(name, int1, int2, speed, delay, delay_var, dump);
}
-
-REGISTER_SIM_OBJECT("EtherLink", EtherLink)
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "dev/ethertap.hh"
-#include "sim/builder.hh"
+#include "params/EtherTap.hh"
using namespace std;
//=====================================================================
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherTap)
-
- SimObjectParam<EtherInt *> peer;
- SimObjectParam<EtherDump *> dump;
- Param<unsigned> port;
- Param<unsigned> bufsz;
-
-END_DECLARE_SIM_OBJECT_PARAMS(EtherTap)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(EtherTap)
-
- INIT_PARAM_DFLT(peer, "peer interface", NULL),
- INIT_PARAM_DFLT(dump, "object to dump network packets to", NULL),
- INIT_PARAM_DFLT(port, "tap port", 3500),
- INIT_PARAM_DFLT(bufsz, "tap buffer size", 10000)
-
-END_INIT_SIM_OBJECT_PARAMS(EtherTap)
-
-
-CREATE_SIM_OBJECT(EtherTap)
+EtherTap *
+EtherTapParams::create()
{
- EtherTap *tap = new EtherTap(getInstanceName(), dump, port, bufsz);
+ EtherTap *tap = new EtherTap(name, dump, port, bufsz);
if (peer) {
tap->setPeer(peer);
return tap;
}
-
-REGISTER_SIM_OBJECT("EtherTap", EtherTap)
* @todo really there are multiple dma engines.. we should implement them.
*/
+#include <algorithm>
+
#include "base/inet.hh"
#include "base/trace.hh"
#include "dev/i8254xGBe.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/IGbE.hh"
+#include "params/IGbEInt.hh"
#include "sim/stats.hh"
#include "sim/system.hh"
-#include <algorithm>
-
using namespace iGbReg;
using namespace Net;
rxDescCache.unserialize(cp, csprintf("%s.RxDescCache", section));
}
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
-
- SimObjectParam<EtherInt *> peer;
- SimObjectParam<IGbE *> device;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IGbEInt)
-
- INIT_PARAM_DFLT(peer, "peer interface", NULL),
- INIT_PARAM(device, "Ethernet device of this interface")
-
-END_INIT_SIM_OBJECT_PARAMS(IGbEInt)
-
-CREATE_SIM_OBJECT(IGbEInt)
+IGbEInt *
+IGbEIntParams::create()
{
- IGbEInt *dev_int = new IGbEInt(getInstanceName(), device);
+ IGbEInt *dev_int = new IGbEInt(name, device);
EtherInt *p = (EtherInt *)peer;
if (p) {
return dev_int;
}
-REGISTER_SIM_OBJECT("IGbEInt", IGbEInt)
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbE)
-
- SimObjectParam<System *> system;
- SimObjectParam<Platform *> platform;
- Param<Tick> min_backoff_delay;
- Param<Tick> max_backoff_delay;
- SimObjectParam<PciConfigData *> configdata;
- Param<uint32_t> pci_bus;
- Param<uint32_t> pci_dev;
- Param<uint32_t> pci_func;
- Param<Tick> pio_latency;
- Param<Tick> config_latency;
- Param<std::string> hardware_address;
- Param<bool> use_flow_control;
- Param<int> rx_fifo_size;
- Param<int> tx_fifo_size;
- Param<int> rx_desc_cache_size;
- Param<int> tx_desc_cache_size;
- Param<Tick> clock;
-
-
-END_DECLARE_SIM_OBJECT_PARAMS(IGbE)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IGbE)
-
- INIT_PARAM(system, "System pointer"),
- INIT_PARAM(platform, "Platform pointer"),
- INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
- INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
- INIT_PARAM(configdata, "PCI Config data"),
- INIT_PARAM(pci_bus, "PCI bus ID"),
- INIT_PARAM(pci_dev, "PCI device number"),
- INIT_PARAM(pci_func, "PCI function code"),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
- INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
- INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
- INIT_PARAM(use_flow_control,"Should the device use xon/off packets"),
- INIT_PARAM(rx_fifo_size,"Size of the RX FIFO"),
- INIT_PARAM(tx_fifo_size,"Size of the TX FIFO"),
- INIT_PARAM(rx_desc_cache_size,"Size of the RX descriptor cache"),
- INIT_PARAM(tx_desc_cache_size,"Size of the TX descriptor cache"),
- INIT_PARAM(clock,"Clock rate for the device to tick at")
-
-END_INIT_SIM_OBJECT_PARAMS(IGbE)
-
-
-CREATE_SIM_OBJECT(IGbE)
+IGbE *
+IGbEParams::create()
{
- IGbE::Params *params = new IGbE::Params;
-
- params->name = getInstanceName();
- params->platform = platform;
- params->system = system;
- params->min_backoff_delay = min_backoff_delay;
- params->max_backoff_delay = max_backoff_delay;
- params->configData = configdata;
- params->busNum = pci_bus;
- params->deviceNum = pci_dev;
- params->functionNum = pci_func;
- params->pio_delay = pio_latency;
- params->config_delay = config_latency;
- params->hardware_address = hardware_address;
- params->use_flow_control = use_flow_control;
- params->rx_fifo_size = rx_fifo_size;
- params->tx_fifo_size = tx_fifo_size;
- params->rx_desc_cache_size = rx_desc_cache_size;
- params->tx_desc_cache_size = tx_desc_cache_size;
- params->clock = clock;
-
-
- return new IGbE(params);
+ return new IGbE(this);
}
-
-REGISTER_SIM_OBJECT("IGbE", IGbE)
#include "dev/i8254xGBe_defs.hh"
#include "dev/pcidev.hh"
#include "dev/pktfifo.hh"
+#include "params/IGbE.hh"
#include "sim/eventq.hh"
class IGbEInt;
TxDescCache txDescCache;
public:
- struct Params : public PciDev::Params
+ typedef IGbEParams Params;
+ const Params *
+ params() const
{
- Net::EthAddr hardware_address;
- bool use_flow_control;
- int rx_fifo_size;
- int tx_fifo_size;
- int rx_desc_cache_size;
- int tx_desc_cache_size;
- Tick clock;
- };
-
+ return dynamic_cast<const Params *>(_params);
+ }
IGbE(Params *params);
- ~IGbE() {;}
+ ~IGbE() {}
Tick clock;
inline Tick cycles(int numCycles) const { return numCycles * clock; }
void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
-
- const Params *params() const {return (const Params *)_params; }
-
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string §ion);
virtual unsigned int drain(Event *de);
#include "dev/platform.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/IdeController.hh"
#include "sim/sim_object.hh"
#include "sim/byteswap.hh"
sizeof(cmd_in_progress) / sizeof(cmd_in_progress[0]));
}
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
-
- SimObjectParam<System *> system;
- SimObjectParam<Platform *> platform;
- Param<Tick> min_backoff_delay;
- Param<Tick> max_backoff_delay;
- SimObjectParam<PciConfigData *> configdata;
- Param<uint32_t> pci_bus;
- Param<uint32_t> pci_dev;
- Param<uint32_t> pci_func;
- Param<Tick> pio_latency;
- Param<Tick> config_latency;
- SimObjectVectorParam<IdeDisk *> disks;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
-
- INIT_PARAM(system, "System pointer"),
- INIT_PARAM(platform, "Platform pointer"),
- INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
- INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
- INIT_PARAM(configdata, "PCI Config data"),
- INIT_PARAM(pci_bus, "PCI bus ID"),
- INIT_PARAM(pci_dev, "PCI device number"),
- INIT_PARAM(pci_func, "PCI function code"),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
- INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
- INIT_PARAM(disks, "IDE disks attached to this controller")
-
-END_INIT_SIM_OBJECT_PARAMS(IdeController)
-
-CREATE_SIM_OBJECT(IdeController)
+IdeController *
+IdeControllerParams::create()
{
- IdeController::Params *params = new IdeController::Params;
- params->name = getInstanceName();
- params->platform = platform;
- params->system = system;
- params->min_backoff_delay = min_backoff_delay;
- params->max_backoff_delay = max_backoff_delay;
- params->configData = configdata;
- params->busNum = pci_bus;
- params->deviceNum = pci_dev;
- params->functionNum = pci_func;
- params->pio_delay = pio_latency;
- params->config_delay = config_latency;
- params->disks = disks;
- return new IdeController(params);
+ return new IdeController(this);
}
-
-REGISTER_SIM_OBJECT("IdeController", IdeController)
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
#include "dev/pcidev.hh"
#include "dev/pcireg.h"
#include "dev/io_device.hh"
+#include "params/IdeController.hh"
#define BMIC0 0x0 // Bus master IDE command register
#define BMIS0 0x2 // Bus master IDE status register
bool isDiskSelected(IdeDisk *diskPtr);
public:
- struct Params : public PciDev::Params
- {
- /** Array of disk objects */
- std::vector<IdeDisk *> disks;
- };
+ typedef IdeControllerParams Params;
const Params *params() const { return (const Params *)_params; }
-
- public:
IdeController(Params *p);
~IdeController();
#include <deque>
#include <string>
+#include "arch/isa_traits.hh"
#include "base/chunk_generator.hh"
#include "base/cprintf.hh" // csprintf
#include "base/trace.hh"
#include "dev/disk_image.hh"
-#include "dev/ide_disk.hh"
#include "dev/ide_ctrl.hh"
-#include "dev/alpha/tsunami.hh"
-#include "dev/alpha/tsunami_pchip.hh"
-#include "sim/builder.hh"
-#include "sim/sim_object.hh"
+#include "dev/ide_disk.hh"
+#include "params/IdeDisk.hh"
#include "sim/core.hh"
-#include "arch/isa_traits.hh"
+#include "sim/sim_object.hh"
using namespace std;
using namespace TheISA;
UNSERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
}
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-enum DriveID { master, slave };
-static const char *DriveID_strings[] = { "master", "slave" };
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
-
- SimObjectParam<DiskImage *> image;
- SimpleEnumParam<DriveID> driveID;
- Param<int> delay;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IdeDisk)
-
- INIT_PARAM(image, "Disk image"),
- INIT_ENUM_PARAM(driveID, "Drive ID (0=master 1=slave)", DriveID_strings),
- INIT_PARAM_DFLT(delay, "Fixed disk delay in microseconds", 1)
-
-END_INIT_SIM_OBJECT_PARAMS(IdeDisk)
-
-
-CREATE_SIM_OBJECT(IdeDisk)
+IdeDisk *
+IdeDiskParams::create()
{
- return new IdeDisk(getInstanceName(), image, driveID, delay);
+ return new IdeDisk(name, image, driveID, delay);
}
-
-REGISTER_SIM_OBJECT("IdeDisk", IdeDisk)
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
#include "base/chunk_generator.hh"
#include "base/trace.hh"
#include "dev/io_device.hh"
-#include "sim/builder.hh"
#include "sim/system.hh"
}
+PioDevice::PioDevice(const Params *p)
+ : MemObject(p), platform(p->platform), sys(p->system), pioPort(NULL)
+{}
+
PioDevice::~PioDevice()
{
if (pioPort)
return count;
}
+BasicPioDevice::BasicPioDevice(const Params *p)
+ : PioDevice(p), pioAddr(p->pio_addr), pioSize(0),
+ pioDelay(p->pio_latency)
+{}
+
void
BasicPioDevice::addressRanges(AddrRangeList &range_list)
{
return true;
}
-DmaDevice::DmaDevice(Params *p)
+DmaDevice::DmaDevice(const Params *p)
: PioDevice(p), dmaPort(NULL), minBackoffDelay(p->min_backoff_delay),
maxBackoffDelay(p->max_backoff_delay)
{ }
assert(transmitList.size());
PacketPtr pkt = transmitList.front();
- System::MemoryMode state = sys->getMemoryMode();
- if (state == System::Timing) {
+ Enums::MemoryMode state = sys->getMemoryMode();
+ if (state == Enums::timing) {
if (backoffEvent.scheduled() || inRetry) {
DPRINTF(DMA, "Can't send immediately, waiting for retry or backoff timer\n");
return;
backoffTime+curTick);
backoffEvent.schedule(backoffTime+curTick);
}
- } else if (state == System::Atomic) {
+ } else if (state == Enums::atomic) {
transmitList.pop_front();
Tick lat;
if (dmaPort)
delete dmaPort;
}
-
-
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/tport.hh"
+#include "params/BasicPioDevice.hh"
+#include "params/DmaDevice.hh"
+#include "params/PioDevice.hh"
#include "sim/sim_object.hh"
class Event;
virtual Tick write(PacketPtr pkt) = 0;
public:
- /** Params struct which is extended through each device based on
- * the parameters it needs. Since we are re-writing everything, we
- * might as well start from the bottom this time. */
- struct Params
- {
- std::string name;
- Platform *platform;
- System *system;
- };
-
- protected:
- Params *_params;
-
- public:
- const Params *params() const { return _params; }
-
- PioDevice(Params *p)
- : MemObject(p->name), platform(p->platform), sys(p->system),
- pioPort(NULL), _params(p)
- {}
-
+ typedef PioDeviceParams Params;
+ PioDevice(const Params *p);
virtual ~PioDevice();
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+
virtual void init();
virtual unsigned int drain(Event *de);
class BasicPioDevice : public PioDevice
{
- public:
- struct Params : public PioDevice::Params
- {
- Addr pio_addr;
- Tick pio_delay;
- };
-
protected:
/** Address that the device listens to. */
Addr pioAddr;
Tick pioDelay;
public:
- BasicPioDevice(Params *p)
- : PioDevice(p), pioAddr(p->pio_addr), pioSize(0),
- pioDelay(p->pio_delay)
- {}
+ typedef BasicPioDeviceParams Params;
+ BasicPioDevice(const Params *p);
+
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
/** return the address ranges that this device responds to.
* @param range_list range list to populate with ranges
class DmaDevice : public PioDevice
{
- public:
- struct Params : public PioDevice::Params
- {
- Tick min_backoff_delay;
- Tick max_backoff_delay;
- };
-
protected:
DmaPort *dmaPort;
Tick minBackoffDelay;
Tick maxBackoffDelay;
public:
- DmaDevice(Params *p);
+ typedef DmaDeviceParams Params;
+ DmaDevice(const Params *p);
virtual ~DmaDevice();
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+
void dmaWrite(Addr addr, int size, Event *event, uint8_t *data)
{
dmaPort->dmaAction(MemCmd::WriteInvalidateReq,
#include "dev/isa_fake.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
IsaFake::IsaFake(Params *p)
: BasicPioDevice(p)
{
- if (!params()->retBadAddr)
+ if (!p->ret_bad_addr)
pioSize = p->pio_size;
- retData8 = params()->retData8;
- retData16 = params()->retData16;
- retData32 = params()->retData32;
- retData64 = params()->retData64;
+ retData8 = p->ret_data8;
+ retData16 = p->ret_data16;
+ retData32 = p->ret_data32;
+ retData64 = p->ret_data64;
}
Tick
{
assert(pkt->result == Packet::Unknown);
- if (params()->warnAccess != "")
+ if (params()->warn_access != "")
warn("Device %s accessed by read to address %#x size=%d\n",
name(), pkt->getAddr(), pkt->getSize());
- if (params()->retBadAddr) {
+ if (params()->ret_bad_addr) {
DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
pkt->getAddr(), pkt->getSize());
pkt->result = Packet::BadAddress;
Tick
IsaFake::write(PacketPtr pkt)
{
- if (params()->warnAccess != "") {
+ if (params()->warn_access != "") {
uint64_t data;
switch (pkt->getSize()) {
case sizeof(uint64_t):
warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
name(), pkt->getAddr(), pkt->getSize(), data);
}
- if (params()->retBadAddr) {
+ if (params()->ret_bad_addr) {
DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
pkt->result = Packet::BadAddress;
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
- if (params()->updateData) {
+ if (params()->update_data) {
switch (pkt->getSize()) {
case sizeof(uint64_t):
retData64 = pkt->get<uint64_t>();
return pioDelay;
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
-
- Param<Addr> pio_addr;
- Param<Tick> pio_latency;
- Param<Addr> pio_size;
- Param<bool> ret_bad_addr;
- Param<bool> update_data;
- Param<std::string> warn_access;
- Param<uint8_t> ret_data8;
- Param<uint16_t> ret_data16;
- Param<uint32_t> ret_data32;
- Param<uint64_t> ret_data64;
- SimObjectParam<Platform *> platform;
- SimObjectParam<System *> system;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
-
- INIT_PARAM(pio_addr, "Device Address"),
- INIT_PARAM(pio_latency, "Programmed IO latency"),
- INIT_PARAM(pio_size, "Size of address range"),
- INIT_PARAM(ret_bad_addr, "Return pkt status BadAddr"),
- INIT_PARAM(update_data, "Update returned data"),
- INIT_PARAM(warn_access, "Warn if this device is touched"),
- INIT_PARAM(ret_data8, "Data to return if not bad addr"),
- INIT_PARAM(ret_data16, "Data to return if not bad addr"),
- INIT_PARAM(ret_data32, "Data to return if not bad addr"),
- INIT_PARAM(ret_data64, "Data to return if not bad addr"),
- INIT_PARAM(platform, "platform"),
- INIT_PARAM(system, "system object")
-
-END_INIT_SIM_OBJECT_PARAMS(IsaFake)
-
-CREATE_SIM_OBJECT(IsaFake)
+IsaFake *
+IsaFakeParams::create()
{
- IsaFake::Params *p = new IsaFake::Params;
- p->name = getInstanceName();
- p->pio_addr = pio_addr;
- p->pio_delay = pio_latency;
- p->pio_size = pio_size;
- p->retBadAddr = ret_bad_addr;
- p->updateData = update_data;
- p->warnAccess = warn_access;
- p->retData8= ret_data8;
- p->retData16 = ret_data16;
- p->retData32 = ret_data32;
- p->retData64 = ret_data64;
- p->platform = platform;
- p->system = system;
- return new IsaFake(p);
+ return new IsaFake(this);
}
-
-REGISTER_SIM_OBJECT("IsaFake", IsaFake)
#ifndef __ISA_FAKE_HH__
#define __ISA_FAKE_HH__
+#include <string>
+
#include "base/range.hh"
#include "dev/io_device.hh"
#include "dev/alpha/tsunami.hh"
+#include "params/IsaFake.hh"
#include "mem/packet.hh"
-#include <string>
-
/**
* IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and
* rites. It is meant to be placed at an address range
*/
class IsaFake : public BasicPioDevice
{
- public:
- struct Params : public BasicPioDevice::Params
- {
- Addr pio_size;
- bool retBadAddr;
- bool updateData;
- uint8_t retData8;
- uint16_t retData16;
- uint32_t retData32;
- uint64_t retData64;
- std::string warnAccess;
- };
protected:
- const Params *params() const { return (const Params*)_params; }
uint8_t retData8;
uint16_t retData16;
uint32_t retData32;
uint64_t retData64;
-
public:
+ typedef IsaFakeParams Params;
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
/**
* The constructor for Tsunmami Fake just registers itself with the MMU.
* @param p params structure
#include "dev/pciconfigall.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/NSGigE.hh"
+#include "params/NSGigEInt.hh"
#include "sim/debug.hh"
#include "sim/host.hh"
#include "sim/stats.hh"
regsReset();
- memcpy(&rom.perfectMatch, p->eaddr.bytes(), ETH_ADDR_LEN);
+ memcpy(&rom.perfectMatch, p->hardware_address.bytes(), ETH_ADDR_LEN);
memset(&rxDesc32, 0, sizeof(rxDesc32));
memset(&txDesc32, 0, sizeof(txDesc32));
}
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigEInt)
-
- SimObjectParam<EtherInt *> peer;
- SimObjectParam<NSGigE *> device;
-
-END_DECLARE_SIM_OBJECT_PARAMS(NSGigEInt)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigEInt)
-
- INIT_PARAM_DFLT(peer, "peer interface", NULL),
- INIT_PARAM(device, "Ethernet device of this interface")
-
-END_INIT_SIM_OBJECT_PARAMS(NSGigEInt)
-
-CREATE_SIM_OBJECT(NSGigEInt)
+NSGigEInt *
+NSGigEIntParams::create()
{
- NSGigEInt *dev_int = new NSGigEInt(getInstanceName(), device);
+ NSGigEInt *dev_int = new NSGigEInt(name, device);
EtherInt *p = (EtherInt *)peer;
if (p) {
return dev_int;
}
-REGISTER_SIM_OBJECT("NSGigEInt", NSGigEInt)
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
-
- SimObjectParam<System *> system;
- SimObjectParam<Platform *> platform;
- Param<Tick> min_backoff_delay;
- Param<Tick> max_backoff_delay;
- SimObjectParam<PciConfigData *> configdata;
- Param<uint32_t> pci_bus;
- Param<uint32_t> pci_dev;
- Param<uint32_t> pci_func;
- Param<Tick> pio_latency;
- Param<Tick> config_latency;
-
- Param<Tick> clock;
- Param<bool> dma_desc_free;
- Param<bool> dma_data_free;
- Param<Tick> dma_read_delay;
- Param<Tick> dma_write_delay;
- Param<Tick> dma_read_factor;
- Param<Tick> dma_write_factor;
- Param<bool> dma_no_allocate;
- Param<Tick> intr_delay;
-
- Param<Tick> rx_delay;
- Param<Tick> tx_delay;
- Param<uint32_t> rx_fifo_size;
- Param<uint32_t> tx_fifo_size;
-
- Param<bool> rx_filter;
- Param<string> hardware_address;
- Param<bool> rx_thread;
- Param<bool> tx_thread;
- Param<bool> rss;
-
-END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
-
- INIT_PARAM(system, "System pointer"),
- INIT_PARAM(platform, "Platform pointer"),
- INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
- INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
- INIT_PARAM(configdata, "PCI Config data"),
- INIT_PARAM(pci_bus, "PCI bus ID"),
- INIT_PARAM(pci_dev, "PCI device number"),
- INIT_PARAM(pci_func, "PCI function code"),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
- INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
- INIT_PARAM(clock, "State machine cycle time"),
-
- INIT_PARAM(dma_desc_free, "DMA of Descriptors is free"),
- INIT_PARAM(dma_data_free, "DMA of Data is free"),
- INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
- INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
- INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
- INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
- INIT_PARAM(dma_no_allocate, "Should DMA reads allocate cache lines"),
- INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"),
-
- INIT_PARAM(rx_delay, "Receive Delay"),
- INIT_PARAM(tx_delay, "Transmit Delay"),
- INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
- INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
-
- INIT_PARAM(rx_filter, "Enable Receive Filter"),
- INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
- INIT_PARAM(rx_thread, ""),
- INIT_PARAM(tx_thread, ""),
- INIT_PARAM(rss, "")
-
-END_INIT_SIM_OBJECT_PARAMS(NSGigE)
-
-
-CREATE_SIM_OBJECT(NSGigE)
+NSGigE *
+NSGigEParams::create()
{
- NSGigE::Params *params = new NSGigE::Params;
-
- params->name = getInstanceName();
- params->platform = platform;
- params->system = system;
- params->min_backoff_delay = min_backoff_delay;
- params->max_backoff_delay = max_backoff_delay;
- params->configData = configdata;
- params->busNum = pci_bus;
- params->deviceNum = pci_dev;
- params->functionNum = pci_func;
- params->pio_delay = pio_latency;
- params->config_delay = config_latency;
-
- params->clock = clock;
- params->dma_desc_free = dma_desc_free;
- params->dma_data_free = dma_data_free;
- params->dma_read_delay = dma_read_delay;
- params->dma_write_delay = dma_write_delay;
- params->dma_read_factor = dma_read_factor;
- params->dma_write_factor = dma_write_factor;
- params->dma_no_allocate = dma_no_allocate;
- params->pio_delay = pio_latency;
- params->intr_delay = intr_delay;
-
- params->rx_delay = rx_delay;
- params->tx_delay = tx_delay;
- params->rx_fifo_size = rx_fifo_size;
- params->tx_fifo_size = tx_fifo_size;
-
- params->rx_filter = rx_filter;
- params->eaddr = hardware_address;
- params->rx_thread = rx_thread;
- params->tx_thread = tx_thread;
- params->rss = rss;
-
- return new NSGigE(params);
+ return new NSGigE(this);
}
-
-REGISTER_SIM_OBJECT("NSGigE", NSGigE)
#include "dev/ns_gige_reg.h"
#include "dev/pcidev.hh"
#include "dev/pktfifo.hh"
+#include "params/NSGigE.hh"
#include "sim/eventq.hh"
// Hash filtering constants
NSGigEInt *interface;
public:
- struct Params : public PciDev::Params
- {
- Tick clock;
- Tick intr_delay;
- Tick tx_delay;
- Tick rx_delay;
- bool dma_desc_free;
- bool dma_data_free;
- Tick dma_read_delay;
- Tick dma_write_delay;
- Tick dma_read_factor;
- Tick dma_write_factor;
- bool rx_filter;
- Net::EthAddr eaddr;
- uint32_t tx_fifo_size;
- uint32_t rx_fifo_size;
- bool rx_thread;
- bool tx_thread;
- bool rss;
- bool dma_no_allocate;
- };
-
+ typedef NSGigEParams Params;
+ const Params *params() const { return (const Params *)_params; }
NSGigE(Params *params);
~NSGigE();
- const Params *params() const { return (const Params *)_params; }
virtual Tick writeConfig(PacketPtr pkt);
#include "dev/platform.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/PciConfigAll.hh"
#include "sim/system.hh"
using namespace std;
#ifndef DOXYGEN_SHOULD_SKIP_THIS
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
-
- Param<Tick> pio_latency;
- Param<int> bus;
- Param<Addr> size;
- SimObjectParam<Platform *> platform;
- SimObjectParam<System *> system;
-
-END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
-
- INIT_PARAM(pio_latency, "Programmed IO latency"),
- INIT_PARAM(bus, "Bus that this object handles config space for"),
- INIT_PARAM(size, "The size of config space"),
- INIT_PARAM(platform, "platform"),
- INIT_PARAM(system, "system object")
-
-END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
-
-CREATE_SIM_OBJECT(PciConfigAll)
+PciConfigAll *
+PciConfigAllParams::create()
{
PciConfigAll::Params *p = new PciConfigAll::Params;
p->pio_delay = pio_latency;
return new PciConfigAll(p);
}
-REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
-
#endif // DOXYGEN_SHOULD_SKIP_THIS
#include "dev/alpha/tsunamireg.h"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/PciConfigData.hh"
#include "sim/byteswap.hh"
-#include "sim/param.hh"
#include "sim/core.hh"
using namespace std;
PciDev::PciDev(Params *p)
- : DmaDevice(p), plat(p->platform), configData(p->configData),
- pioDelay(p->pio_delay), configDelay(p->config_delay),
+ : DmaDevice(p), plat(p->platform), configData(p->configdata),
+ pioDelay(p->pio_latency), configDelay(p->config_latency),
configPort(NULL)
{
// copy the config data from the PciConfigData object
memset(BARAddrs, 0, sizeof(BARAddrs));
- plat->registerPciDevice(0, p->deviceNum, p->functionNum,
+ plat->registerPciDevice(0, p->pci_dev, p->pci_func,
letoh(configData->config.interruptLine));
}
pkt->set<uint8_t>(config.data[offset]);
DPRINTF(PCIDEV,
"readConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
- params()->deviceNum, params()->functionNum, offset,
+ params()->pci_dev, params()->pci_func, offset,
(uint32_t)pkt->get<uint8_t>());
break;
case sizeof(uint16_t):
pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]);
DPRINTF(PCIDEV,
"readConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
- params()->deviceNum, params()->functionNum, offset,
+ params()->pci_dev, params()->pci_func, offset,
(uint32_t)pkt->get<uint16_t>());
break;
case sizeof(uint32_t):
pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]);
DPRINTF(PCIDEV,
"readConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
- params()->deviceNum, params()->functionNum, offset,
+ params()->pci_dev, params()->pci_func, offset,
(uint32_t)pkt->get<uint32_t>());
break;
default:
}
DPRINTF(PCIDEV,
"writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
- params()->deviceNum, params()->functionNum, offset,
+ params()->pci_dev, params()->pci_func, offset,
(uint32_t)pkt->get<uint8_t>());
break;
case sizeof(uint16_t):
}
DPRINTF(PCIDEV,
"writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
- params()->deviceNum, params()->functionNum, offset,
+ params()->pci_dev, params()->pci_func, offset,
(uint32_t)pkt->get<uint16_t>());
break;
case sizeof(uint32_t):
}
DPRINTF(PCIDEV,
"writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
- params()->deviceNum, params()->functionNum, offset,
+ params()->pci_dev, params()->pci_func, offset,
(uint32_t)pkt->get<uint32_t>());
break;
default:
}
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
-
- Param<uint16_t> VendorID;
- Param<uint16_t> DeviceID;
- Param<uint16_t> Command;
- Param<uint16_t> Status;
- Param<uint8_t> Revision;
- Param<uint8_t> ProgIF;
- Param<uint8_t> SubClassCode;
- Param<uint8_t> ClassCode;
- Param<uint8_t> CacheLineSize;
- Param<uint8_t> LatencyTimer;
- Param<uint8_t> HeaderType;
- Param<uint8_t> BIST;
- Param<uint32_t> BAR0;
- Param<uint32_t> BAR1;
- Param<uint32_t> BAR2;
- Param<uint32_t> BAR3;
- Param<uint32_t> BAR4;
- Param<uint32_t> BAR5;
- Param<uint32_t> CardbusCIS;
- Param<uint16_t> SubsystemVendorID;
- Param<uint16_t> SubsystemID;
- Param<uint32_t> ExpansionROM;
- Param<uint8_t> InterruptLine;
- Param<uint8_t> InterruptPin;
- Param<uint8_t> MinimumGrant;
- Param<uint8_t> MaximumLatency;
- Param<uint32_t> BAR0Size;
- Param<uint32_t> BAR1Size;
- Param<uint32_t> BAR2Size;
- Param<uint32_t> BAR3Size;
- Param<uint32_t> BAR4Size;
- Param<uint32_t> BAR5Size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
-
- INIT_PARAM(VendorID, "Vendor ID"),
- INIT_PARAM(DeviceID, "Device ID"),
- INIT_PARAM_DFLT(Command, "Command Register", 0x00),
- INIT_PARAM_DFLT(Status, "Status Register", 0x00),
- INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
- INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
- INIT_PARAM(SubClassCode, "Sub-Class Code"),
- INIT_PARAM(ClassCode, "Class Code"),
- INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
- INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
- INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
- INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
- INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
- INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
- INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
- INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
- INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
- INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
- INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
- INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
- INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
- INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
- INIT_PARAM(InterruptLine, "Interrupt Line Register"),
- INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
- INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
- INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
- INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
- INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
- INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
- INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
- INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
- INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
-
-END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
-
-CREATE_SIM_OBJECT(PciConfigData)
+PciConfigData *
+PciConfigDataParams::create()
{
- PciConfigData *data = new PciConfigData(getInstanceName());
-
- data->config.vendor = htole(VendorID.returnValue());
- data->config.device = htole(DeviceID.returnValue());
- data->config.command = htole(Command.returnValue());
- data->config.status = htole(Status.returnValue());
- data->config.revision = htole(Revision.returnValue());
- data->config.progIF = htole(ProgIF.returnValue());
- data->config.subClassCode = htole(SubClassCode.returnValue());
- data->config.classCode = htole(ClassCode.returnValue());
- data->config.cacheLineSize = htole(CacheLineSize.returnValue());
- data->config.latencyTimer = htole(LatencyTimer.returnValue());
- data->config.headerType = htole(HeaderType.returnValue());
- data->config.bist = htole(BIST.returnValue());
-
- data->config.baseAddr[0] = htole(BAR0.returnValue());
- data->config.baseAddr[1] = htole(BAR1.returnValue());
- data->config.baseAddr[2] = htole(BAR2.returnValue());
- data->config.baseAddr[3] = htole(BAR3.returnValue());
- data->config.baseAddr[4] = htole(BAR4.returnValue());
- data->config.baseAddr[5] = htole(BAR5.returnValue());
- data->config.cardbusCIS = htole(CardbusCIS.returnValue());
- data->config.subsystemVendorID = htole(SubsystemVendorID.returnValue());
- data->config.subsystemID = htole(SubsystemID.returnValue());
- data->config.expansionROM = htole(ExpansionROM.returnValue());
- data->config.interruptLine = htole(InterruptLine.returnValue());
- data->config.interruptPin = htole(InterruptPin.returnValue());
- data->config.minimumGrant = htole(MinimumGrant.returnValue());
- data->config.maximumLatency = htole(MaximumLatency.returnValue());
+ PciConfigData *data = new PciConfigData(name);
+
+ data->config.vendor = htole(VendorID);
+ data->config.device = htole(DeviceID);
+ data->config.command = htole(Command);
+ data->config.status = htole(Status);
+ data->config.revision = htole(Revision);
+ data->config.progIF = htole(ProgIF);
+ data->config.subClassCode = htole(SubClassCode);
+ data->config.classCode = htole(ClassCode);
+ data->config.cacheLineSize = htole(CacheLineSize);
+ data->config.latencyTimer = htole(LatencyTimer);
+ data->config.headerType = htole(HeaderType);
+ data->config.bist = htole(BIST);
+
+ data->config.baseAddr[0] = htole(BAR0);
+ data->config.baseAddr[1] = htole(BAR1);
+ data->config.baseAddr[2] = htole(BAR2);
+ data->config.baseAddr[3] = htole(BAR3);
+ data->config.baseAddr[4] = htole(BAR4);
+ data->config.baseAddr[5] = htole(BAR5);
+ data->config.cardbusCIS = htole(CardbusCIS);
+ data->config.subsystemVendorID = htole(SubsystemVendorID);
+ data->config.subsystemID = htole(SubsystemID);
+ data->config.expansionROM = htole(ExpansionROM);
+ data->config.interruptLine = htole(InterruptLine);
+ data->config.interruptPin = htole(InterruptPin);
+ data->config.minimumGrant = htole(MinimumGrant);
+ data->config.maximumLatency = htole(MaximumLatency);
data->BARSize[0] = BAR0Size;
data->BARSize[1] = BAR1Size;
uint32_t barsize = data->BARSize[i];
if (barsize != 0 && !isPowerOf2(barsize)) {
fatal("%s: BAR %d size %d is not a power of 2\n",
- getInstanceName(), i, data->BARSize[i]);
+ name, i, data->BARSize[i]);
}
}
return data;
}
-
-REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS
#include "dev/io_device.hh"
#include "dev/pcireg.h"
#include "dev/platform.hh"
+#include "params/PciDevice.hh"
#include "sim/byteswap.hh"
#define BAR_IO_MASK 0x3
};
public:
- struct Params : public DmaDevice::Params
+ typedef PciDeviceParams Params;
+ const Params *
+ params() const
{
- /**
- * A pointer to the object that contains the first 64 bytes of
- * config space
- */
- PciConfigData *configData;
-
- /** The bus number we are on */
- uint32_t busNum;
-
- /** The device number we have */
- uint32_t deviceNum;
-
- /** The function number */
- uint32_t functionNum;
-
- /** The latency for pio accesses. */
- Tick pio_delay;
-
- /** The latency for a config access. */
- Tick config_delay;
- };
-
- public:
- const Params *params() const { return (const Params *)_params; }
+ return dynamic_cast<const Params *>(_params);
+ }
protected:
/** The current config space. Unlike the PciConfigData this is
if (if_name == "config") {
if (configPort != NULL)
panic("pciconfig port already connected to.");
- configPort = new PciConfigPort(this, params()->busNum,
- params()->deviceNum, params()->functionNum,
+ configPort = new PciConfigPort(this, params()->pci_bus,
+ params()->pci_dev, params()->pci_func,
params()->platform);
return configPort;
}
#include "base/misc.hh"
#include "dev/platform.hh"
-#include "sim/builder.hh"
#include "sim/sim_exit.hh"
using namespace std;
intLines.set(intr);
}
-
-
-DEFINE_SIM_OBJECT_CLASS_NAME("Platform", Platform)
-
#include "dev/platform.hh"
#include "dev/simconsole.hh"
#include "dev/uart.hh"
-#include "sim/builder.hh"
+#include "params/SimConsole.hh"
using namespace std;
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
-
- SimObjectParam<IntrControl *> intr_control;
- Param<string> output;
- Param<int> port;
- Param<bool> append_name;
- Param<int> number;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SimConsole)
-
- INIT_PARAM(intr_control, "interrupt controller"),
- INIT_PARAM(output, "file to dump output to"),
- INIT_PARAM(port, ""),
- INIT_PARAM_DFLT(append_name, "append name() to filename", true),
- INIT_PARAM_DFLT(number, "console number", 0)
-
-END_INIT_SIM_OBJECT_PARAMS(SimConsole)
-
-CREATE_SIM_OBJECT(SimConsole)
+SimConsole *
+SimConsoleParams::create()
{
string filename = output;
ostream *stream = NULL;
if (!filename.empty()) {
if (append_name)
- filename += "." + getInstanceName();
+ filename += "." + name;
stream = simout.find(filename);
}
- return new SimConsole(getInstanceName(), stream, number, port);
+ return new SimConsole(name, stream, number, port);
}
-
-REGISTER_SIM_OBJECT("SimConsole", SimConsole)
#include "dev/disk_image.hh"
#include "dev/simple_disk.hh"
#include "mem/port.hh"
-#include "sim/builder.hh"
+#include "params/SimpleDisk.hh"
#include "sim/system.hh"
using namespace std;
#endif
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
-
- SimObjectParam<System *> system;
- SimObjectParam<DiskImage *> disk;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
-
- INIT_PARAM(system, "System pointer"),
- INIT_PARAM(disk, "Disk Image")
-
-END_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
-
-CREATE_SIM_OBJECT(SimpleDisk)
+SimpleDisk *
+SimpleDiskParams::create()
{
- return new SimpleDisk(getInstanceName(), system, disk);
+ return new SimpleDisk(name, system, disk);
}
-
-REGISTER_SIM_OBJECT("SimpleDisk", SimpleDisk)
#include <limits>
#include <string>
+#include "arch/vtophys.hh"
#include "base/inet.hh"
#include "cpu/thread_context.hh"
#include "cpu/intr_control.hh"
#include "dev/sinic.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
#include "sim/debug.hh"
#include "sim/eventq.hh"
#include "sim/host.hh"
#include "sim/stats.hh"
-#include "arch/vtophys.hh"
using namespace Net;
using namespace TheISA;
regs.TxFifoSize = params()->tx_fifo_size;
regs.RxFifoMark = params()->rx_fifo_threshold;
regs.TxFifoMark = params()->tx_fifo_threshold;
- regs.HwAddr = params()->eaddr;
+ regs.HwAddr = params()->hardware_address;
rxList.clear();
rxBusy.clear();
/* namespace Sinic */ }
-BEGIN_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
-
- SimObjectParam<EtherInt *> peer;
- SimObjectParam<Sinic::Device *> device;
-END_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
-
- INIT_PARAM_DFLT(peer, "peer interface", NULL),
- INIT_PARAM(device, "Ethernet device of this interface")
-
-END_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
-
-CREATE_SIM_OBJECT_WNS(Sinic, SinicInterface)
+Sinic::Interface *
+SinicIntParams::create()
{
- Sinic::Interface *dev_int = new Sinic::Interface(getInstanceName(), device);
+ using namespace Sinic;
+
+ Interface *dev_int = new Interface(name, device);
- EtherInt *p = (EtherInt *)peer;
- if (p) {
- dev_int->setPeer(p);
- p->setPeer(dev_int);
+ if (peer) {
+ dev_int->setPeer(peer);
+ peer->setPeer(dev_int);
}
return dev_int;
}
-REGISTER_SIM_OBJECT_WNS(Sinic, "SinicInt", SinicInterface)
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
-
-
- SimObjectParam<System *> system;
- SimObjectParam<Platform *> platform;
- Param<Tick> min_backoff_delay;
- Param<Tick> max_backoff_delay;
- SimObjectParam<PciConfigData *> configdata;
- Param<uint32_t> pci_bus;
- Param<uint32_t> pci_dev;
- Param<uint32_t> pci_func;
- Param<Tick> pio_latency;
- Param<Tick> config_latency;
- Param<Tick> intr_delay;
-
- Param<Tick> clock;
- Param<Tick> dma_read_delay;
- Param<Tick> dma_read_factor;
- Param<Tick> dma_write_delay;
- Param<Tick> dma_write_factor;
-
- Param<Tick> rx_delay;
- Param<Tick> tx_delay;
- Param<uint32_t> rx_max_copy;
- Param<uint32_t> tx_max_copy;
- Param<uint32_t> rx_max_intr;
- Param<uint32_t> rx_fifo_size;
- Param<uint32_t> tx_fifo_size;
- Param<uint32_t> rx_fifo_threshold;
- Param<uint32_t> rx_fifo_low_mark;
- Param<uint32_t> tx_fifo_high_mark;
- Param<uint32_t> tx_fifo_threshold;
-
- Param<bool> rx_filter;
- Param<std::string> hardware_address;
- Param<bool> rx_thread;
- Param<bool> tx_thread;
- Param<bool> rss;
- Param<uint32_t> virtual_count;
- Param<bool> zero_copy;
- Param<bool> delay_copy;
- Param<bool> virtual_addr;
-
-END_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
-
-
- INIT_PARAM(system, "System pointer"),
- INIT_PARAM(platform, "Platform pointer"),
- INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
- INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
- INIT_PARAM(configdata, "PCI Config data"),
- INIT_PARAM(pci_bus, "PCI bus ID"),
- INIT_PARAM(pci_dev, "PCI device number"),
- INIT_PARAM(pci_func, "PCI function code"),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
- INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
- INIT_PARAM(intr_delay, "Interrupt Delay"),
- INIT_PARAM(clock, "State machine cycle time"),
-
- INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
- INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
- INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
- INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
-
- INIT_PARAM(rx_delay, "Receive Delay"),
- INIT_PARAM(tx_delay, "Transmit Delay"),
- INIT_PARAM(rx_max_copy, "rx max copy"),
- INIT_PARAM(tx_max_copy, "rx max copy"),
- INIT_PARAM(rx_max_intr, "rx max intr"),
- INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
- INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
- INIT_PARAM(rx_fifo_threshold, "max size in bytes of rxFifo"),
- INIT_PARAM(rx_fifo_low_mark, "max size in bytes of rxFifo"),
- INIT_PARAM(tx_fifo_high_mark, "max size in bytes of txFifo"),
- INIT_PARAM(tx_fifo_threshold, "max size in bytes of txFifo"),
-
- INIT_PARAM(rx_filter, "Enable Receive Filter"),
- INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
- INIT_PARAM(rx_thread, ""),
- INIT_PARAM(tx_thread, ""),
- INIT_PARAM(rss, ""),
- INIT_PARAM(virtual_count, ""),
- INIT_PARAM(zero_copy, ""),
- INIT_PARAM(delay_copy, ""),
- INIT_PARAM(virtual_addr, "")
-
-END_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
-
-
-CREATE_SIM_OBJECT_WNS(Sinic, SinicDevice)
+Sinic::Device *
+SinicParams::create()
{
- Sinic::Sinic::Device::Params *params = new Device::Params;
- params->name = getInstanceName();
- params->platform = platform;
- params->system = system;
- params->min_backoff_delay = min_backoff_delay;
- params->max_backoff_delay = max_backoff_delay;
- params->configData = configdata;
- params->busNum = pci_bus;
- params->deviceNum = pci_dev;
- params->functionNum = pci_func;
- params->pio_delay = pio_latency;
- params->config_delay = config_latency;
- params->intr_delay = intr_delay;
- params->clock = clock;
-
- params->dma_read_delay = dma_read_delay;
- params->dma_read_factor = dma_read_factor;
- params->dma_write_delay = dma_write_delay;
- params->dma_write_factor = dma_write_factor;
-
- params->tx_delay = tx_delay;
- params->rx_delay = rx_delay;
- params->rx_max_copy = rx_max_copy;
- params->tx_max_copy = tx_max_copy;
- params->rx_max_intr = rx_max_intr;
- params->rx_fifo_size = rx_fifo_size;
- params->tx_fifo_size = tx_fifo_size;
- params->rx_fifo_threshold = rx_fifo_threshold;
- params->rx_fifo_low_mark = rx_fifo_low_mark;
- params->tx_fifo_high_mark = tx_fifo_high_mark;
- params->tx_fifo_threshold = tx_fifo_threshold;
-
- params->rx_filter = rx_filter;
- params->eaddr = hardware_address;
- params->rx_thread = rx_thread;
- params->tx_thread = tx_thread;
- params->rss = rss;
- params->virtual_count = virtual_count;
- params->zero_copy = zero_copy;
- params->delay_copy = delay_copy;
- params->virtual_addr = virtual_addr;
-
- return new Sinic::Device(params);
+ return new Sinic::Device(this);
}
-
-REGISTER_SIM_OBJECT_WNS(Sinic, "Sinic", SinicDevice)
-
#include "dev/pcidev.hh"
#include "dev/pktfifo.hh"
#include "dev/sinicreg.hh"
+#include "params/Sinic.hh"
+#include "params/SinicInt.hh"
#include "sim/eventq.hh"
namespace Sinic {
* Construction/Destruction/Parameters
*/
public:
- struct Params : public PciDev::Params
- {
- Tick clock;
- Tick intr_delay;
- };
-
+ typedef SinicParams Params;
+ const Params *params() const { return (const Params *)_params; }
Base(Params *p);
};
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string §ion);
-/**
- * Construction/Destruction/Parameters
- */
- public:
- struct Params : public Base::Params
- {
- Tick tx_delay;
- Tick rx_delay;
- bool rx_filter;
- Net::EthAddr eaddr;
- uint32_t rx_max_copy;
- uint32_t tx_max_copy;
- uint32_t rx_max_intr;
- uint32_t rx_fifo_size;
- uint32_t tx_fifo_size;
- uint32_t rx_fifo_threshold;
- uint32_t rx_fifo_low_mark;
- uint32_t tx_fifo_high_mark;
- uint32_t tx_fifo_threshold;
- Tick dma_read_delay;
- Tick dma_read_factor;
- Tick dma_write_delay;
- Tick dma_write_factor;
- bool rx_thread;
- bool tx_thread;
- bool rss;
- uint32_t virtual_count;
- bool zero_copy;
- bool delay_copy;
- bool virtual_addr;
- };
-
- protected:
- const Params *params() const { return (const Params *)_params; }
-
public:
- Device(Params *params);
+ Device(Params *p);
~Device();
};
#include <string>
#include <vector>
+#include "base/time.hh"
#include "base/trace.hh"
#include "dev/sparc/dtod.hh"
#include "dev/platform.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh"
-#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
using namespace TheISA;
-DumbTOD::DumbTOD(Params *p)
+DumbTOD::DumbTOD(const Params *p)
: BasicPioDevice(p)
{
- struct tm tm;
+ struct tm tm = p->time;
char *tz;
pioSize = 0x08;
- parseTime(p->init_time, &tm);
tz = getenv("TZ");
setenv("TZ", "", 1);
tzset();
UNSERIALIZE_SCALAR(todTime);
}
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DumbTOD)
-
- Param<Addr> pio_addr;
- Param<Tick> pio_latency;
- SimObjectParam<Platform *> platform;
- SimObjectParam<System *> system;
- VectorParam<int> time;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DumbTOD)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DumbTOD)
-
- INIT_PARAM(pio_addr, "Device Address"),
- INIT_PARAM(pio_latency, "Programmed IO latency"),
- INIT_PARAM(platform, "platform"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(time, "")
-
-END_INIT_SIM_OBJECT_PARAMS(DumbTOD)
-
-CREATE_SIM_OBJECT(DumbTOD)
+DumbTOD *
+DumbTODParams::create()
{
- DumbTOD::Params *p = new DumbTOD::Params;
- p->name =getInstanceName();
- p->pio_addr = pio_addr;
- p->pio_delay = pio_latency;
- p->platform = platform;
- p->system = system;
- p->init_time = time;
- return new DumbTOD(p);
+ return new DumbTOD(this);
}
-
-REGISTER_SIM_OBJECT("DumbTOD", DumbTOD)
#include "base/range.hh"
#include "dev/io_device.hh"
-
+#include "params/DumbTOD.hh"
/**
* DumbTOD simply returns some idea of time when read. Until we finish with
uint64_t todTime;
public:
- struct Params : public BasicPioDevice::Params
- {
- std::vector<int> init_time;
- };
- protected:
- const Params *params() const { return (const Params *)_params; }
+ typedef DumbTODParams Params;
+ DumbTOD(const Params *p);
- public:
- DumbTOD(Params *p);
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
#include "dev/platform.hh"
#include "mem/port.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
#include "sim/faults.hh"
#include "sim/system.hh"
-Iob::Iob(Params *p)
+Iob::Iob(const Params *p)
: PioDevice(p), ic(p->platform->intrctrl)
{
iobManAddr = ULL(0x9800000000);
};
}
-
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Iob)
- Param<Tick> pio_latency;
- SimObjectParam<Platform *> platform;
- SimObjectParam<System *> system;
-END_DECLARE_SIM_OBJECT_PARAMS(Iob)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Iob)
-
- INIT_PARAM(pio_latency, "Programmed IO latency"),
- INIT_PARAM(platform, "platform"),
- INIT_PARAM(system, "system object")
-
-END_INIT_SIM_OBJECT_PARAMS(Iob)
-
-CREATE_SIM_OBJECT(Iob)
+Iob *
+IobParams::create()
{
- Iob::Params *p = new Iob::Params;
- p->name = getInstanceName();
- p->pio_delay = pio_latency;
- p->platform = platform;
- p->system = system;
- return new Iob(p);
+ return new Iob(this);
}
-
-REGISTER_SIM_OBJECT("Iob", Iob)
#include "base/range.hh"
#include "dev/io_device.hh"
#include "dev/disk_image.hh"
+#include "params/Iob.hh"
class IntrControl;
void readIob(PacketPtr pkt);
void readJBus(PacketPtr pkt);
-
public:
- struct Params : public PioDevice::Params
- {
- Tick pio_delay;
- };
- protected:
- const Params *params() const { return (const Params*)_params; }
+ typedef IobParams Params;
+ Iob(const Params *p);
- public:
- Iob(Params *p);
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
void generateIpi(Type type, int cpu_id, int vector);
void receiveDeviceInterrupt(DeviceId devid);
- bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1);
-
+ bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
+ uint64_t d1);
void addressRanges(AddrRangeList &range_list);
#include "dev/platform.hh"
#include "mem/port.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"
-MmDisk::MmDisk(Params *p)
+MmDisk::MmDisk(const Params *p)
: BasicPioDevice(p), image(p->image), curSector((off_t)-1), dirty(false)
{
std::memset(&diskData, 0, SectorSize);
}
}
-
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(MmDisk)
- Param<Addr> pio_addr;
- Param<Tick> pio_latency;
- Param<Addr> pio_size;
- SimObjectParam<Platform *> platform;
- SimObjectParam<System *> system;
- SimObjectParam<DiskImage *> image;
-END_DECLARE_SIM_OBJECT_PARAMS(MmDisk)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(MmDisk)
-
- INIT_PARAM(pio_addr, "Device Address"),
- INIT_PARAM(pio_latency, "Programmed IO latency"),
- INIT_PARAM(pio_size, "Size of address range"),
- INIT_PARAM(platform, "platform"),
- INIT_PARAM(system, "system object"),
- INIT_PARAM(image, "disk image")
-
-END_INIT_SIM_OBJECT_PARAMS(MmDisk)
-
-CREATE_SIM_OBJECT(MmDisk)
+MmDisk *
+MmDiskParams::create()
{
- MmDisk::Params *p = new MmDisk::Params;
- p->name = getInstanceName();
- p->pio_addr = pio_addr;
- p->pio_delay = pio_latency;
- p->platform = platform;
- p->system = system;
- p->image = image;
- return new MmDisk(p);
+ return new MmDisk(this);
}
-
-REGISTER_SIM_OBJECT("MmDisk", MmDisk)
#include "base/range.hh"
#include "dev/io_device.hh"
#include "dev/disk_image.hh"
+#include "params/MmDisk.hh"
class MmDisk : public BasicPioDevice
{
uint8_t diskData[SectorSize];
public:
- struct Params : public BasicPioDevice::Params
- {
- DiskImage *image;
- };
- protected:
- const Params *params() const { return (const Params*)_params; }
+ typedef MmDiskParams Params;
+ MmDisk(const Params *p);
- public:
- MmDisk(Params *p);
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
#include "cpu/intr_control.hh"
#include "dev/simconsole.hh"
#include "dev/sparc/t1000.hh"
-#include "sim/builder.hh"
+#include "params/T1000.hh"
#include "sim/system.hh"
using namespace std;
M5_DUMMY_RETURN
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(T1000)
-
- SimObjectParam<System *> system;
- SimObjectParam<IntrControl *> intrctrl;
-
-END_DECLARE_SIM_OBJECT_PARAMS(T1000)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(T1000)
-
- INIT_PARAM(system, "system"),
- INIT_PARAM(intrctrl, "interrupt controller")
-
-END_INIT_SIM_OBJECT_PARAMS(T1000)
-
-CREATE_SIM_OBJECT(T1000)
+T1000 *
+T1000Params::create()
{
- return new T1000(getInstanceName(), system, intrctrl);
+ return new T1000(name, system, intrctrl);
}
-
-REGISTER_SIM_OBJECT("T1000", T1000)
#include "dev/simconsole.hh"
#include "dev/uart.hh"
#include "dev/platform.hh"
-#include "sim/builder.hh"
using namespace std;
-Uart::Uart(Params *p)
- : BasicPioDevice(p), platform(p->platform), cons(p->cons)
+Uart::Uart(const Params *p)
+ : BasicPioDevice(p), platform(p->platform), cons(p->sim_console)
{
-
status = 0;
// set back pointers
cons->uart = this;
}
-
-DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)
-
#include "base/range.hh"
#include "dev/io_device.hh"
+#include "params/Uart.hh"
class SimConsole;
class Platform;
const int RX_INT = 0x1;
const int TX_INT = 0x2;
-
class Uart : public BasicPioDevice
{
SimConsole *cons;
public:
- struct Params : public BasicPioDevice::Params
- {
- SimConsole *cons;
- };
+ typedef UartParams Params;
+ Uart(const Params *p);
- Uart(Params *p);
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
/**
* Inform the uart that there is data available.
*/
virtual void dataAvailable() = 0;
-
/**
* Return if we have an interrupt pending
* @return interrupt status
*/
bool intStatus() { return status ? true : false; }
-
- protected:
- const Params *params() const {return (const Params *)_params; }
-
};
#endif // __UART_HH__
#include "dev/platform.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
using namespace std;
using namespace TheISA;
}
-Uart8250::Uart8250(Params *p)
+Uart8250::Uart8250(const Params *p)
: Uart(p), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
{
pioSize = 8;
-
}
Tick
txIntrEvent.schedule(txintrwhen);
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
-
- Param<Addr> pio_addr;
- Param<Tick> pio_latency;
- SimObjectParam<Platform *> platform;
- SimObjectParam<SimConsole *> sim_console;
- SimObjectParam<System *> system;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
-
- INIT_PARAM(pio_addr, "Device Address"),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
- INIT_PARAM(platform, "platform"),
- INIT_PARAM(sim_console, "The Simulator Console"),
- INIT_PARAM(system, "system object")
-
-END_INIT_SIM_OBJECT_PARAMS(Uart8250)
-
-CREATE_SIM_OBJECT(Uart8250)
+Uart8250 *
+Uart8250Params::create()
{
- Uart8250::Params *p = new Uart8250::Params;
- p->name = getInstanceName();
- p->pio_addr = pio_addr;
- p->pio_delay = pio_latency;
- p->platform = platform;
- p->cons = sim_console;
- p->system = system;
- return new Uart8250(p);
+ return new Uart8250(this);
}
-
-REGISTER_SIM_OBJECT("Uart8250", Uart8250)
-
#include "base/range.hh"
#include "dev/io_device.hh"
#include "dev/uart.hh"
-
+#include "params/Uart8250.hh"
/* UART8250 Interrupt ID Register
* bit 0 Interrupt Pending 0 = true, 1 = false
class Uart8250 : public Uart
{
-
-
protected:
uint8_t IER, DLAB, LCR, MCR;
Tick lastTxInt;
IntrEvent rxIntrEvent;
public:
- Uart8250(Params *p);
+ typedef Uart8250Params Params;
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+ Uart8250(const Params *p);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
virtual void addressRanges(AddrRangeList &range_list);
-
/**
* Inform the uart that there is data available.
*/
#
# Authors: Ron Dreslinski
-from m5.SimObject import SimObject
from m5.SimObject import SimObject
class MemObject(SimObject):
#include "base/trace.hh"
#include "mem/bridge.hh"
-#include "sim/builder.hh"
+#include "params/Bridge.hh"
Bridge::BridgePort::BridgePort(const std::string &_name,
Bridge *_bridge, BridgePort *_otherPort,
otherPort->getPeerAddressRanges(resp, snoop);
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bridge)
-
- Param<int> req_size_a;
- Param<int> req_size_b;
- Param<int> resp_size_a;
- Param<int> resp_size_b;
- Param<Tick> delay;
- Param<Tick> nack_delay;
- Param<bool> write_ack;
- Param<bool> fix_partial_write_a;
- Param<bool> fix_partial_write_b;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Bridge)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Bridge)
-
- INIT_PARAM(req_size_a, "The size of the queue for requests coming into side a"),
- INIT_PARAM(req_size_b, "The size of the queue for requests coming into side b"),
- INIT_PARAM(resp_size_a, "The size of the queue for responses coming into side a"),
- INIT_PARAM(resp_size_b, "The size of the queue for responses coming into side b"),
- INIT_PARAM(delay, "The miminum delay to cross this bridge"),
- INIT_PARAM(nack_delay, "The minimum delay to nack a packet"),
- INIT_PARAM(write_ack, "Acknowledge any writes that are received."),
- INIT_PARAM(fix_partial_write_a, "Fixup any partial block writes that are received"),
- INIT_PARAM(fix_partial_write_b, "Fixup any partial block writes that are received")
-
-END_INIT_SIM_OBJECT_PARAMS(Bridge)
-
-CREATE_SIM_OBJECT(Bridge)
+Bridge *
+BridgeParams::create()
{
- Bridge::Params *p = new Bridge::Params;
- p->name = getInstanceName();
- p->req_size_a = req_size_a;
- p->req_size_b = req_size_b;
- p->resp_size_a = resp_size_a;
- p->resp_size_b = resp_size_b;
- p->delay = delay;
- p->nack_delay = nack_delay;
- p->write_ack = write_ack;
- p->fix_partial_write_a = fix_partial_write_a;
- p->fix_partial_write_b = fix_partial_write_b;
- return new Bridge(p);
+ return new Bridge(this);
}
-
-REGISTER_SIM_OBJECT("Bridge", Bridge)
-
-
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
+#include "params/Bridge.hh"
#include "sim/eventq.hh"
class Bridge : public MemObject
bool ackWrites;
public:
- struct Params
- {
- std::string name;
- int req_size_a;
- int req_size_b;
- int resp_size_a;
- int resp_size_b;
- Tick delay;
- Tick nack_delay;
- bool write_ack;
- bool fix_partial_write_a;
- bool fix_partial_write_b;
- };
+ typedef BridgeParams Params;
protected:
Params *_params;
#include "base/misc.hh"
#include "base/trace.hh"
#include "mem/bus.hh"
-#include "sim/builder.hh"
+#include "params/Bus.hh"
Port *
Bus::getPort(const std::string &if_name, int idx)
tickNextIdle = (curTick / clock) * clock + clock;
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
-
- Param<int> bus_id;
- Param<int> clock;
- Param<int> width;
- Param<bool> responder_set;
- Param<int> block_size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Bus)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
- INIT_PARAM(bus_id, "a globally unique bus id"),
- INIT_PARAM(clock, "bus clock speed"),
- INIT_PARAM(width, "width of the bus (bits)"),
- INIT_PARAM(responder_set, "Is a default responder set by the user"),
- INIT_PARAM(block_size, "Default blocksize if no device has one")
-END_INIT_SIM_OBJECT_PARAMS(Bus)
-
-CREATE_SIM_OBJECT(Bus)
+Bus *
+BusParams::create()
{
- return new Bus(getInstanceName(), bus_id, clock, width, responder_set,
- block_size);
+ return new Bus(name, bus_id, clock, width, responder_set, block_size);
}
-
-REGISTER_SIM_OBJECT("Bus", Bus)
#include <vector>
// Must be included first to determine which caches we want
+#include "enums/Prefetch.hh"
#include "mem/config/cache.hh"
#include "mem/config/prefetch.hh"
-
#include "mem/cache/base_cache.hh"
#include "mem/cache/cache.hh"
#include "mem/bus.hh"
#include "mem/cache/coherence/coherence_protocol.hh"
-#include "sim/builder.hh"
+#include "params/BaseCache.hh"
// Tag Templates
#if defined(USE_CACHE_LRU)
using namespace std;
using namespace TheISA;
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
-
- Param<int> size;
- Param<int> assoc;
- Param<int> block_size;
- Param<int> latency;
- Param<int> mshrs;
- Param<int> tgts_per_mshr;
- Param<int> write_buffers;
- Param<bool> prioritizeRequests;
- SimObjectParam<CoherenceProtocol *> protocol;
- Param<Addr> trace_addr;
- Param<int> hash_delay;
-#if defined(USE_CACHE_IIC)
- SimObjectParam<Repl *> repl;
-#endif
- Param<bool> compressed_bus;
- Param<bool> store_compressed;
- Param<bool> adaptive_compression;
- Param<int> compression_latency;
- Param<int> subblock_size;
- Param<Counter> max_miss_count;
- VectorParam<Range<Addr> > addr_range;
-// SimObjectParam<MemTraceWriter *> mem_trace;
- Param<bool> split;
- Param<int> split_size;
- Param<bool> lifo;
- Param<bool> two_queue;
- Param<bool> prefetch_miss;
- Param<bool> prefetch_access;
- Param<int> prefetcher_size;
- Param<bool> prefetch_past_page;
- Param<bool> prefetch_serial_squash;
- Param<Tick> prefetch_latency;
- Param<int> prefetch_degree;
- Param<string> prefetch_policy;
- Param<bool> prefetch_cache_check_push;
- Param<bool> prefetch_use_cpu_id;
- Param<bool> prefetch_data_accesses_only;
-
-END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
-
- INIT_PARAM(size, "capacity in bytes"),
- INIT_PARAM(assoc, "associativity"),
- INIT_PARAM(block_size, "block size in bytes"),
- INIT_PARAM(latency, "hit latency in CPU cycles"),
- INIT_PARAM(mshrs, "number of MSHRs (max outstanding requests)"),
- INIT_PARAM(tgts_per_mshr, "max number of accesses per MSHR"),
- INIT_PARAM_DFLT(write_buffers, "number of write buffers", 8),
- INIT_PARAM_DFLT(prioritizeRequests, "always service demand misses first",
- false),
- INIT_PARAM_DFLT(protocol, "coherence protocol to use in the cache", NULL),
- INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
-
- INIT_PARAM_DFLT(hash_delay, "time in cycles of hash access",1),
-#if defined(USE_CACHE_IIC)
- INIT_PARAM_DFLT(repl, "replacement policy",NULL),
-#endif
- INIT_PARAM_DFLT(compressed_bus,
- "This cache connects to a compressed memory",
- false),
- INIT_PARAM_DFLT(store_compressed, "Store compressed data in the cache",
- false),
- INIT_PARAM_DFLT(adaptive_compression, "Use an adaptive compression scheme",
- false),
- INIT_PARAM_DFLT(compression_latency,
- "Latency in cycles of compression algorithm",
- 0),
- INIT_PARAM_DFLT(subblock_size,
- "Size of subblock in IIC used for compression",
- 0),
- INIT_PARAM_DFLT(max_miss_count,
- "The number of misses to handle before calling exit",
- 0),
- INIT_PARAM_DFLT(addr_range, "The address range in bytes",
- vector<Range<Addr> >(1,RangeIn((Addr)0, MaxAddr))),
-// INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
- INIT_PARAM_DFLT(split, "Whether this is a partitioned cache", false),
- INIT_PARAM_DFLT(split_size, "the number of \"ways\" belonging to the LRU partition", 0),
- INIT_PARAM_DFLT(lifo, "whether you are using a LIFO repl. policy", false),
- INIT_PARAM_DFLT(two_queue, "whether the lifo should have two queue replacement", false),
- INIT_PARAM_DFLT(prefetch_miss, "wheter you are using the hardware prefetcher from Miss stream", false),
- INIT_PARAM_DFLT(prefetch_access, "wheter you are using the hardware prefetcher from Access stream", false),
- INIT_PARAM_DFLT(prefetcher_size, "Number of entries in the harware prefetch queue", 100),
- INIT_PARAM_DFLT(prefetch_past_page, "Allow prefetches to cross virtual page boundaries", false),
- INIT_PARAM_DFLT(prefetch_serial_squash, "Squash prefetches with a later time on a subsequent miss", false),
- INIT_PARAM_DFLT(prefetch_latency, "Latency of the prefetcher", 10),
- INIT_PARAM_DFLT(prefetch_degree, "Degree of the prefetch depth", 1),
- INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
- INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
- INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
- INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
-END_INIT_SIM_OBJECT_PARAMS(BaseCache)
-
-
#define BUILD_CACHE(TAGS, tags, c) \
do { \
- BasePrefetcher *pf; \
- if (pf_policy == "tagged") { \
+ BasePrefetcher *pf; \
+ if (prefetch_policy == Enums::tagged) { \
BUILD_TAGGED_PREFETCHER(TAGS); \
} \
- else if (pf_policy == "stride") { \
+ else if (prefetch_policy == Enums::stride) { \
BUILD_STRIDED_PREFETCHER(TAGS); \
} \
- else if (pf_policy == "ghb") { \
+ else if (prefetch_policy == Enums::ghb) { \
BUILD_GHB_PREFETCHER(TAGS); \
} \
else { \
BUILD_NULL_PREFETCHER(TAGS); \
} \
Cache<TAGS, c>::Params params(tags, mq, coh, base_params, \
- pf, prefetch_access, latency, \
+ pf, prefetch_access, latency, \
true, \
store_compressed, \
adaptive_compression, \
compAlg, compression_latency, \
prefetch_miss); \
Cache<TAGS, c> *retval = \
- new Cache<TAGS, c>(getInstanceName(), params); \
+ new Cache<TAGS, c>(name, params); \
return retval; \
} while (0)
#define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
#endif
-CREATE_SIM_OBJECT(BaseCache)
+BaseCache *
+BaseCacheParams::create()
{
- string name = getInstanceName();
int numSets = size / (assoc * block_size);
- string pf_policy = prefetch_policy;
if (subblock_size == 0) {
subblock_size = block_size;
}
block_size, max_miss_count);
//Warnings about prefetcher policy
- if (pf_policy == "none" && (prefetch_miss || prefetch_access)) {
- panic("With no prefetcher, you shouldn't prefetch from"
- " either miss or access stream\n");
- }
- if ((pf_policy == "tagged" || pf_policy == "stride" ||
- pf_policy == "ghb") && !(prefetch_miss || prefetch_access)) {
- warn("With this prefetcher you should chose a prefetch"
- " stream (miss or access)\nNo Prefetching will occur\n");
+ if (prefetch_policy == Enums::none) {
+ if (prefetch_miss || prefetch_access)
+ panic("With no prefetcher, you shouldn't prefetch from"
+ " either miss or access stream\n");
}
- if ((pf_policy == "tagged" || pf_policy == "stride" ||
- pf_policy == "ghb") && prefetch_miss && prefetch_access) {
- panic("Can't do prefetches from both miss and access"
- " stream\n");
- }
- if (pf_policy != "tagged" && pf_policy != "stride" &&
- pf_policy != "ghb" && pf_policy != "none") {
- panic("Unrecognized form of a prefetcher: %s, try using"
- "['none','stride','tagged','ghb']\n", pf_policy);
+
+ if (prefetch_policy == Enums::tagged || prefetch_policy == Enums::stride ||
+ prefetch_policy == Enums::ghb) {
+
+ if (!prefetch_miss && !prefetch_access)
+ warn("With this prefetcher you should chose a prefetch"
+ " stream (miss or access)\nNo Prefetching will occur\n");
+
+ if (prefetch_miss && prefetch_access)
+ panic("Can't do prefetches from both miss and access stream");
}
#if defined(USE_CACHE_IIC)
}
return NULL;
}
-
-REGISTER_SIM_OBJECT("BaseCache", BaseCache)
-
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
#include "mem/cache/miss/mshr.hh"
#include "mem/cache/cache.hh"
#include "mem/cache/coherence/coherence_protocol.hh"
-#include "sim/builder.hh"
+#include "params/CoherenceProtocol.hh"
using namespace std;
}
CoherenceProtocol::CoherenceProtocol(const string &name,
- const string &protocol,
+ Enums::Coherence protocol,
const bool doUpgrades)
: SimObject(name)
{
- // Python should catch this, but in case it doesn't...
- if (!(protocol == "msi" || protocol == "mesi" ||
- protocol == "mosi" || protocol == "moesi")) {
- fatal("CoherenceProtocol: unrecognized protocol %s\n", protocol);
- }
-
- bool hasOwned = (protocol == "mosi" || protocol == "moesi");
- bool hasExclusive = (protocol == "mesi" || protocol == "moesi");
+ bool hasOwned = (protocol == Enums::mosi || protocol == Enums::moesi);
+ bool hasExclusive = (protocol == Enums::mesi || protocol == Enums::moesi);
if (hasOwned && !doUpgrades) {
fatal("CoherenceProtocol: ownership protocols require upgrade "
return false;
}
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(CoherenceProtocol)
-
- Param<string> protocol;
- Param<bool> do_upgrades;
-
-END_DECLARE_SIM_OBJECT_PARAMS(CoherenceProtocol)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(CoherenceProtocol)
-
- INIT_PARAM(protocol, "name of coherence protocol"),
- INIT_PARAM_DFLT(do_upgrades, "use upgrade transactions?", true)
-
-END_INIT_SIM_OBJECT_PARAMS(CoherenceProtocol)
-
-
-CREATE_SIM_OBJECT(CoherenceProtocol)
+CoherenceProtocol *
+CoherenceProtocolParams::create()
{
- return new CoherenceProtocol(getInstanceName(), protocol,
- do_upgrades);
+ return new CoherenceProtocol(name, protocol, do_upgrades);
}
-
-REGISTER_SIM_OBJECT("CoherenceProtocol", CoherenceProtocol)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS
#include <string>
-#include "sim/sim_object.hh"
-#include "mem/packet.hh"
-#include "mem/cache/cache_blk.hh"
#include "base/statistics.hh"
+#include "enums/Coherence.hh"
+#include "mem/cache/cache_blk.hh"
+#include "mem/packet.hh"
+#include "sim/sim_object.hh"
class BaseCache;
class MSHR;
* @param protocol The string representation of the protocol to use.
* @param doUpgrades True if bus upgrades should be used.
*/
- CoherenceProtocol(const std::string &name, const std::string &protocol,
+ CoherenceProtocol(const std::string &name, Enums::Coherence protocol,
const bool doUpgrades);
/**
SimObject('Repl.py')
Source('repl/gen.cc')
-Source('repl/repl.cc')
#include "base/misc.hh"
#include "mem/cache/tags/iic.hh"
#include "mem/cache/tags/repl/gen.hh"
-#include "sim/builder.hh"
+#include "params/GenRepl.hh"
#include "sim/host.hh"
using namespace std;
return false;
}
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(GenRepl)
-
- Param<int> num_pools;
- Param<int> fresh_res;
- Param<int> pool_res;
-
-END_DECLARE_SIM_OBJECT_PARAMS(GenRepl)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(GenRepl)
-
- INIT_PARAM(num_pools, "capacity in bytes"),
- INIT_PARAM(fresh_res, "associativity"),
- INIT_PARAM(pool_res, "block size in bytes")
-
-END_INIT_SIM_OBJECT_PARAMS(GenRepl)
-
-
-CREATE_SIM_OBJECT(GenRepl)
+GenRepl *
+GenReplParams::create()
{
- return new GenRepl(getInstanceName(), num_pools, fresh_res, pool_res);
+ return new GenRepl(name, num_pools, fresh_res, pool_res);
}
-
-REGISTER_SIM_OBJECT("GenRepl", GenRepl)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
- * Nathan Binkert
- */
-
-/**
- * Definitions of the base replacement class.
- */
-
-#include "sim/param.hh"
-#include "mem/cache/tags/repl/repl.hh"
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-DEFINE_SIM_OBJECT_CLASS_NAME("Repl", Repl)
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
* Definition of a DRAM like main memory.
*/
+#include <cstdlib>
+#include <string>
#include "mem/dram.hh"
-#include "sim/builder.hh"
-#include <stdlib.h>
-#include <string>
extern int maxThreadsPerCPU;
-DRAMMemory::DRAMMemory(Params *p)
+DRAMMemory::DRAMMemory(const Params *p)
: PhysicalMemory(p), cpu_ratio(p->cpu_ratio), bus_width(p->bus_width),
mem_type(p->mem_type), mem_actpolicy(p->mem_actpolicy),
memctrladdr_type(p->memctrladdr_type), act_lat(p->act_lat),
memctrlpipe_enable(false), time_last_access(0)
{
warn("This DRAM module has not been tested with the new memory system at all!");
- bank_size = (params()->addrRange.size() + 1) / num_banks;
+ bank_size = (p->range.size() + 1) / num_banks;
num_rows = bank_size / SD_ROW_SIZE; /* 0x1000 size of row 4Kbtye */
active_row = new int[num_banks];
last_bank = num_banks+1;
return precharge;
}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DRAMMemory)
-
- Param<std::string> file;
- Param<Range<Addr> > range;
- Param<Tick> latency;
- /* additional params for dram protocol*/
- Param<int> cpu_ratio;
- Param<std::string> mem_type;
- Param<std::string> mem_actpolicy;
- Param<std::string> memctrladdr_type;
- Param<int> bus_width;
- Param<int> act_lat;
- Param<int> cas_lat;
- Param<int> war_lat;
- Param<int> pre_lat;
- Param<int> dpl_lat;
- Param<int> trc_lat;
- Param<int> num_banks;
- Param<int> num_cpus;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DRAMMemory)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DRAMMemory)
-
- INIT_PARAM_DFLT(file, "memory mapped file", ""),
- INIT_PARAM(range, "Device Address Range"),
- INIT_PARAM(latency, "Memory access latency"),
-
- /* additional params for dram protocol*/
- INIT_PARAM_DFLT(cpu_ratio,"ratio between CPU speed and memory bus speed",5),
- INIT_PARAM_DFLT(mem_type,"type of DRAM","SDRAM"),
- INIT_PARAM_DFLT(mem_actpolicy,"open / closed page policy","open"),
- INIT_PARAM_DFLT(memctrladdr_type,"interleaved or direct mapping","interleaved"),
- INIT_PARAM_DFLT(bus_width,"memory access bus width",16),
- INIT_PARAM_DFLT(act_lat,"RAS to CAS delay",2),
- INIT_PARAM_DFLT(cas_lat,"CAS delay",1),
- INIT_PARAM_DFLT(war_lat,"write after read delay",2),
- INIT_PARAM_DFLT(pre_lat,"precharge delay",2),
- INIT_PARAM_DFLT(dpl_lat,"data in to precharge delay",2),
- INIT_PARAM_DFLT(trc_lat,"row cycle delay",6),
- INIT_PARAM_DFLT(num_banks,"Number of Banks",4),
- INIT_PARAM_DFLT(num_cpus,"Number of CPUs connected to DRAM",4)
-
-END_INIT_SIM_OBJECT_PARAMS(DRAMMemory)
-
-CREATE_SIM_OBJECT(DRAMMemory)
+DRAMMemory *
+DRAMMemoryParams::create()
{
- DRAMMemory::Params *p = new DRAMMemory::Params;
- p->name = getInstanceName();
- p->addrRange = range;
- p->latency = latency;
-
- /* additional params for dram */
- p->cpu_ratio = cpu_ratio;
- p->bus_width = bus_width;
- p->mem_type = mem_type;
- p->mem_actpolicy = mem_actpolicy;
- p->memctrladdr_type = memctrladdr_type;
- p->act_lat = act_lat;
- p->cas_lat = cas_lat;
- p->war_lat = war_lat;
- p->pre_lat = pre_lat;
- p->dpl_lat = dpl_lat;
- p->trc_lat = trc_lat;
- p->num_banks = num_banks;
- p->num_cpus = num_cpus;
-
- return new DRAMMemory(p);
+ return new DRAMMemory(this);
}
-
-REGISTER_SIM_OBJECT("DRAMMemory", DRAMMemory)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS
-
-
#include "base/statistics.hh"
#include "mem/physical.hh"
+#include "params/DRAMMemory.hh"
class DRAMMemory : public PhysicalMemory
{
int prechargeBanksAround(int bank);
public:
- struct Params : public PhysicalMemory::Params
+ typedef DRAMMemoryParams Params;
+ DRAMMemory(const Params *p);
+
+ const Params *
+ params() const
{
- /* additional params for dram protocol*/
- int cpu_ratio;
- int bus_width;
-
- std::string mem_type; /* DRDRAM, SDRAM */
- std::string mem_actpolicy; /* closed, open */
- std::string memctrladdr_type; /* interleaved, anythingelse */
-
- int act_lat;
- int cas_lat;
- int war_lat;
- int pre_lat;
- int dpl_lat;
- int trc_lat;
- int num_banks;
- int num_cpus;
-
- };
+ return dynamic_cast<const Params *>(_params);
+ }
+
virtual void regStats();
- DRAMMemory(Params *p);
};
#endif// __MEM_DRAM_HH__
*/
#include "mem/mem_object.hh"
-#include "sim/param.hh"
+
+MemObject::MemObject(const Params *params)
+ : SimObject(params)
+{
+}
MemObject::MemObject(const std::string &name)
: SimObject(name)
{
}
+
void
MemObject::deletePortRefs(Port *p)
{
panic("This object does not support port deletion\n");
}
-
-DEFINE_SIM_OBJECT_CLASS_NAME("MemObject", MemObject)
#ifndef __MEM_MEM_OBJECT_HH__
#define __MEM_MEM_OBJECT_HH__
-#include "sim/sim_object.hh"
#include "mem/port.hh"
+#include "params/MemObject.hh"
+#include "sim/sim_object.hh"
/**
* The base MemoryObject class, allows for an accesor function to a
class MemObject : public SimObject
{
public:
+ typedef MemObjectParams Params;
+ MemObject(const Params *params);
MemObject(const std::string &name);
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+
public:
/** Additional function to return the Port of a memory object. */
virtual Port *getPort(const std::string &if_name, int idx = -1) = 0;
#include "base/intmath.hh"
#include "base/trace.hh"
#include "mem/page_table.hh"
-#include "sim/builder.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
#include "config/full_system.hh"
#include "mem/packet_access.hh"
#include "mem/physical.hh"
-#include "sim/builder.hh"
#include "sim/eventq.hh"
#include "sim/host.hh"
using namespace std;
using namespace TheISA;
-PhysicalMemory::PhysicalMemory(Params *p)
- : MemObject(p->name), pmemAddr(NULL), lat(p->latency), _params(p)
+PhysicalMemory::PhysicalMemory(const Params *p)
+ : MemObject(p), pmemAddr(NULL), lat(p->latency)
{
- if (params()->addrRange.size() % TheISA::PageBytes != 0)
+ if (params()->range.size() % TheISA::PageBytes != 0)
panic("Memory Size not divisible by page size\n");
int map_flags = MAP_ANON | MAP_PRIVATE;
- pmemAddr = (uint8_t *)mmap(NULL, params()->addrRange.size(), PROT_READ | PROT_WRITE,
+ pmemAddr = (uint8_t *)mmap(NULL, params()->range.size(), PROT_READ | PROT_WRITE,
map_flags, -1, 0);
if (pmemAddr == (void *)MAP_FAILED) {
}
//If requested, initialize all the memory to 0
- if(params()->zero)
- memset(pmemAddr, 0, params()->addrRange.size());
+ if (p->zero)
+ memset(pmemAddr, 0, p->range.size());
pagePtr = 0;
}
PhysicalMemory::~PhysicalMemory()
{
if (pmemAddr)
- munmap((char*)pmemAddr, params()->addrRange.size());
+ munmap((char*)pmemAddr, params()->range.size());
//Remove memPorts?
}
{
snoop = false;
resp.clear();
- resp.push_back(RangeSize(start(), params()->addrRange.size()));
+ resp.push_back(RangeSize(start(), params()->range.size()));
}
int
fatal("Insufficient memory to allocate compression state for %s\n",
filename);
- if (gzwrite(compressedMem, pmemAddr, params()->addrRange.size()) != params()->addrRange.size()) {
+ if (gzwrite(compressedMem, pmemAddr, params()->range.size()) !=
+ params()->range.size()) {
fatal("Write failed on physical memory checkpoint file '%s'\n",
filename);
}
// unmap file that was mmaped in the constructor
// This is done here to make sure that gzip and open don't muck with our
// nice large space of memory before we reallocate it
- munmap((char*)pmemAddr, params()->addrRange.size());
+ munmap((char*)pmemAddr, params()->range.size());
- pmemAddr = (uint8_t *)mmap(NULL, params()->addrRange.size(), PROT_READ | PROT_WRITE,
- MAP_ANON | MAP_PRIVATE, -1, 0);
+ pmemAddr = (uint8_t *)mmap(NULL, params()->range.size(),
+ PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
if (pmemAddr == (void *)MAP_FAILED) {
perror("mmap");
fatal("Unable to malloc memory to read file %s\n", filename);
/* Only copy bytes that are non-zero, so we don't give the VM system hell */
- while (curSize < params()->addrRange.size()) {
+ while (curSize < params()->range.size()) {
bytesRead = gzread(compressedMem, tempPage, chunkSize);
- if (bytesRead != chunkSize && bytesRead != params()->addrRange.size() - curSize)
+ if (bytesRead != chunkSize &&
+ bytesRead != params()->range.size() - curSize)
fatal("Read failed on physical memory checkpoint file '%s'"
" got %d bytes, expected %d or %d bytes\n",
- filename, bytesRead, chunkSize, params()->addrRange.size()-curSize);
+ filename, bytesRead, chunkSize,
+ params()->range.size() - curSize);
assert(bytesRead % sizeof(long) == 0);
}
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
-
- Param<string> file;
- Param<Range<Addr> > range;
- Param<Tick> latency;
- Param<bool> zero;
-
-END_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
-
- INIT_PARAM_DFLT(file, "memory mapped file", ""),
- INIT_PARAM(range, "Device Address Range"),
- INIT_PARAM(latency, "Memory access latency"),
- INIT_PARAM(zero, "Zero initialize memory")
-
-END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
-
-CREATE_SIM_OBJECT(PhysicalMemory)
+PhysicalMemory *
+PhysicalMemoryParams::create()
{
- PhysicalMemory::Params *p = new PhysicalMemory::Params;
- p->name = getInstanceName();
- p->addrRange = range;
- p->latency = latency;
- p->zero = zero;
- return new PhysicalMemory(p);
+ return new PhysicalMemory(this);
}
-
-REGISTER_SIM_OBJECT("PhysicalMemory", PhysicalMemory)
#ifndef __PHYSICAL_MEMORY_HH__
#define __PHYSICAL_MEMORY_HH__
+#include <map>
+#include <string>
+
#include "base/range.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/tport.hh"
+#include "params/PhysicalMemory.hh"
#include "sim/eventq.hh"
-#include <map>
-#include <string>
//
// Functional model for a contiguous block of physical memory. (i.e. RAM)
public:
Addr new_page();
- uint64_t size() { return params()->addrRange.size(); }
- uint64_t start() { return params()->addrRange.start; }
-
- struct Params
- {
- std::string name;
- Range<Addr> addrRange;
- Tick latency;
- bool zero;
- };
-
- protected:
- Params *_params;
+ uint64_t size() { return params()->range.size(); }
+ uint64_t start() { return params()->range.start; }
public:
- const Params *params() const { return _params; }
- PhysicalMemory(Params *p);
+ typedef PhysicalMemoryParams Params;
+ PhysicalMemory(const Params *p);
virtual ~PhysicalMemory();
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+
public:
int deviceBlockSize();
void getAddressRanges(AddrRangeList &resp, bool &snoop);
# Authors: Steve Reinhardt
# Nathan Binkert
-import os
Import('*')
-Source('swig/init.cc')
Source('swig/pyevent.cc')
Source('swig/pyobject.cc')
PySource('m5', 'm5/multidict.py')
PySource('m5', 'm5/params.py')
PySource('m5', 'm5/proxy.py')
+PySource('m5', 'm5/simulate.py')
PySource('m5', 'm5/smartdict.py')
PySource('m5', 'm5/stats.py')
PySource('m5', 'm5/ticks.py')
PySource('m5', 'm5/util.py')
-PySource('m5', os.path.join(env['ROOT'], 'util/pbs/jobfile.py'))
-
SwigSource('m5.internal', 'swig/core.i')
SwigSource('m5.internal', 'swig/debug.i')
SwigSource('m5.internal', 'swig/event.i')
--- /dev/null
+# Copyright (c) 2004-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+import imp
+import py_compile
+import sys
+import zipfile
+
+from os.path import basename
+from os.path import exists
+
+class DictImporter(object):
+ '''This importer takes a dictionary of arbitrary module names that
+ map to arbitrary filenames.'''
+ def __init__(self, modules, build_env):
+ self.modules = modules
+ self.installed = set()
+ self.build_env = build_env
+
+ def __del__(self):
+ self.unload()
+
+ def unload(self):
+ for module in self.installed:
+ del sys.modules[module]
+
+ def find_module(self, fullname, path):
+ if fullname == '__scons':
+ return self
+
+ if fullname == 'm5.objects':
+ return self
+
+ if fullname.startswith('m5.internal'):
+ return None
+
+ if fullname in self.modules and exists(self.modules[fullname]):
+ return self
+
+ return None
+
+ def load_module(self, fullname):
+ mod = imp.new_module(fullname)
+ sys.modules[fullname] = mod
+ self.installed.add(fullname)
+
+ mod.__loader__ = self
+ if fullname == 'm5.objects':
+ mod.__path__ = fullname.split('.')
+ return mod
+
+ if fullname == '__scons':
+ mod.__dict__['m5_build_env'] = self.build_env
+ return mod
+
+ srcfile = self.modules[fullname]
+ if basename(srcfile) == '__init__.py':
+ mod.__path__ = fullname.split('.')
+ mod.__file__ = srcfile
+
+ exec file(srcfile, 'r') in mod.__dict__
+
+ return mod
+
+class ordered_dict(dict):
+ def keys(self):
+ keys = super(ordered_dict, self).keys()
+ keys.sort()
+ return keys
+
+ def values(self):
+ return [ self[key] for key in self.keys() ]
+
+ def items(self):
+ return [ (key,self[key]) for key in self.keys() ]
+
+ def iterkeys(self):
+ for key in self.keys():
+ yield key
+
+ def itervalues(self):
+ for value in self.values():
+ yield value
+
+ def iteritems(self):
+ for key,value in self.items():
+ yield key, value
+
+class Generate(object):
+ def __init__(self, py_sources, sim_objects, build_env):
+ self.py_sources = py_sources
+ self.py_modules = {}
+ for source in py_sources:
+ self.py_modules[source.modpath] = source.srcpath
+
+ importer = DictImporter(self.py_modules, build_env)
+
+ # install the python importer so we can grab stuff from the source
+ # tree itself.
+ sys.meta_path[0:0] = [ importer ]
+
+ import m5
+ self.m5 = m5
+
+ # import all sim objects so we can populate the all_objects list
+ # make sure that we're working with a list, then let's sort it
+ sim_objects = list(sim_objects)
+ sim_objects.sort()
+ for simobj in sim_objects:
+ exec('from m5.objects import %s' % simobj)
+
+ # we need to unload all of the currently imported modules so that they
+ # will be re-imported the next time the sconscript is run
+ importer.unload()
+ sys.meta_path.remove(importer)
+
+ self.sim_objects = m5.SimObject.allClasses
+ self.enums = m5.params.allEnums
+
+ self.params = {}
+ for name,obj in self.sim_objects.iteritems():
+ for param in obj._params.local.values():
+ if not hasattr(param, 'swig_decl'):
+ continue
+ pname = param.ptype_str
+ if pname not in self.params:
+ self.params[pname] = param
+
+ def createSimObjectParam(self, target, source, env):
+ assert len(target) == 1 and len(source) == 1
+
+ hh_file = file(target[0].abspath, 'w')
+ name = str(source[0].get_contents())
+ obj = self.sim_objects[name]
+
+ print >>hh_file, obj.cxx_decl()
+
+ # Generate Python file containing a dict specifying the current
+ # build_env flags.
+ def makeDefinesPyFile(self, target, source, env):
+ f = file(str(target[0]), 'w')
+ print >>f, "m5_build_env = ", source[0]
+ f.close()
+
+ # Generate python file containing info about the M5 source code
+ def makeInfoPyFile(self, target, source, env):
+ f = file(str(target[0]), 'w')
+ for src in source:
+ data = ''.join(file(src.srcnode().abspath, 'r').xreadlines())
+ print >>f, "%s = %s" % (src, repr(data))
+ f.close()
+
+ # Generate the __init__.py file for m5.objects
+ def makeObjectsInitFile(self, target, source, env):
+ f = file(str(target[0]), 'w')
+ print >>f, 'from params import *'
+ print >>f, 'from m5.SimObject import *'
+ for module in source:
+ print >>f, 'from %s import *' % module.get_contents()
+ f.close()
+
+ def createSwigParam(self, target, source, env):
+ assert len(target) == 1 and len(source) == 1
+
+ i_file = file(target[0].abspath, 'w')
+ name = str(source[0].get_contents())
+ param = self.params[name]
+
+ for line in param.swig_decl():
+ print >>i_file, line
+
+ def createEnumStrings(self, target, source, env):
+ assert len(target) == 1 and len(source) == 1
+
+ cc_file = file(target[0].abspath, 'w')
+ name = str(source[0].get_contents())
+ obj = self.enums[name]
+
+ print >>cc_file, obj.cxx_def()
+ cc_file.close()
+
+ def createEnumParam(self, target, source, env):
+ assert len(target) == 1 and len(source) == 1
+
+ hh_file = file(target[0].abspath, 'w')
+ name = str(source[0].get_contents())
+ obj = self.enums[name]
+
+ print >>hh_file, obj.cxx_decl()
+
+ def buildParams(self, target, source, env):
+ names = [ s.get_contents() for s in source ]
+ objs = [ self.sim_objects[name] for name in names ]
+ out = file(target[0].abspath, 'w')
+
+ ordered_objs = []
+ obj_seen = set()
+ def order_obj(obj):
+ name = str(obj)
+ if name in obj_seen:
+ return
+
+ obj_seen.add(name)
+ if str(obj) != 'SimObject':
+ order_obj(obj.__bases__[0])
+
+ ordered_objs.append(obj)
+
+ for obj in objs:
+ order_obj(obj)
+
+ enums = set()
+ predecls = []
+ pd_seen = set()
+
+ def add_pds(*pds):
+ for pd in pds:
+ if pd not in pd_seen:
+ predecls.append(pd)
+ pd_seen.add(pd)
+
+ for obj in ordered_objs:
+ params = obj._params.local.values()
+ for param in params:
+ ptype = param.ptype
+ if issubclass(ptype, self.m5.params.Enum):
+ if ptype not in enums:
+ enums.add(ptype)
+ pds = param.swig_predecls()
+ if isinstance(pds, (list, tuple)):
+ add_pds(*pds)
+ else:
+ add_pds(pds)
+
+ print >>out, '%module params'
+
+ print >>out, '%{'
+ for obj in ordered_objs:
+ print >>out, '#include "params/%s.hh"' % obj
+ print >>out, '%}'
+
+ for pd in predecls:
+ print >>out, pd
+
+ enums = list(enums)
+ enums.sort()
+ for enum in enums:
+ print >>out, '%%import "enums/%s.hh"' % enum.__name__
+ print >>out
+
+ for obj in ordered_objs:
+ code = 'class %s ' % obj.cxx_class
+ if str(obj) != 'SimObject':
+ code += ': public %s ' % obj.__bases__[0]
+ code += '{};'
+
+ klass = obj.cxx_class;
+ if hasattr(obj, 'cxx_namespace'):
+ code = 'namespace %s { %s }' % (obj.cxx_namespace, code)
+ klass = '%s::%s' % (obj.cxx_namespace, klass)
+
+ print >>out, '%%ignore %s;' % klass
+ print >>out, code
+
+ for obj in ordered_objs:
+ print >>out, '%%include "params/%s.hh"' % obj
+
+ def makeSwigInit(self, target, source, env):
+ f = file(str(target[0]), 'w')
+ print >>f, 'extern "C" {'
+ for module in source:
+ print >>f, ' void init_%s();' % module.get_contents()
+ print >>f, '}'
+ print >>f, 'void init_swig() {'
+ for module in source:
+ print >>f, ' init_%s();' % module.get_contents()
+ print >>f, '}'
+ f.close()
+
+ def compilePyFile(self, target, source, env):
+ '''Action function to compile a .py into a .pyc'''
+ py_compile.compile(str(source[0]), str(target[0]))
+
+ def buildPyZip(self, target, source, env):
+ '''Action function to build the zip archive. Uses the
+ PyZipFile module included in the standard Python library.'''
+
+ py_compiled = {}
+ for s in self.py_sources:
+ compname = str(s.compiled)
+ assert compname not in py_compiled
+ py_compiled[compname] = s
+
+ zf = zipfile.ZipFile(str(target[0]), 'w')
+ for s in source:
+ zipname = str(s)
+ arcname = py_compiled[zipname].arcname
+ zf.write(zipname, arcname)
+ zf.close()
import sys, types
+import proxy
+import m5
from util import *
from multidict import multidict
from params import *
# There are a few things we need that aren't in params.__all__ since
# normal users don't need them
-from params import ParamDesc, isNullPointer, SimObjVector
+from params import ParamDesc, VectorParamDesc, isNullPointer, SimObjVector
noDot = False
try:
#
#####################################################################
+# list of all SimObject classes
+allClasses = {}
+
# dict to look up SimObjects based on path
instanceDict = {}
class MetaSimObject(type):
# Attributes that can be set only at initialization time
init_keywords = { 'abstract' : types.BooleanType,
+ 'cxx_namespace' : types.StringType,
+ 'cxx_class' : types.StringType,
+ 'cxx_type' : types.StringType,
+ 'cxx_predecls' : types.ListType,
+ 'swig_predecls' : types.ListType,
'type' : types.StringType }
# Attributes that can be set any time
- keywords = { 'check' : types.FunctionType,
- 'cxx_type' : types.StringType,
- 'cxx_predecls' : types.ListType,
- 'swig_predecls' : types.ListType }
+ keywords = { 'check' : types.FunctionType }
# __new__ is called before __init__, and is where the statements
# in the body of the class definition get loaded into the class's
# and only allow "private" attributes to be passed to the base
# __new__ (starting with underscore).
def __new__(mcls, name, bases, dict):
+ assert name not in allClasses
+
# Copy "private" attributes, functions, and classes to the
# official dict. Everything else goes in _init_dict to be
# filtered in __init__.
else:
# must be a param/port setting
value_dict[key] = val
+ if 'abstract' not in value_dict:
+ value_dict['abstract'] = False
cls_dict['_value_dict'] = value_dict
- return super(MetaSimObject, mcls).__new__(mcls, name, bases, cls_dict)
+ cls = super(MetaSimObject, mcls).__new__(mcls, name, bases, cls_dict)
+ if 'type' in value_dict:
+ allClasses[name] = cls
+ return cls
# subclass initialization
def __init__(cls, name, bases, dict):
# mark base as having been subclassed
base._instantiated = True
+ # default keyword values
+ if 'type' in cls._value_dict:
+ _type = cls._value_dict['type']
+ if 'cxx_class' not in cls._value_dict:
+ cls._value_dict['cxx_class'] = _type
+
+ namespace = cls._value_dict.get('cxx_namespace', None)
+
+ _cxx_class = cls._value_dict['cxx_class']
+ if 'cxx_type' not in cls._value_dict:
+ t = _cxx_class + '*'
+ if namespace:
+ t = '%s::%s' % (namespace, t)
+ cls._value_dict['cxx_type'] = t
+ if 'cxx_predecls' not in cls._value_dict:
+ # A forward class declaration is sufficient since we are
+ # just declaring a pointer.
+ decl = 'class %s;' % _cxx_class
+ if namespace:
+ decl = 'namespace %s { %s }' % (namespace, decl)
+ cls._value_dict['cxx_predecls'] = [decl]
+
+ if 'swig_predecls' not in cls._value_dict:
+ # A forward class declaration is sufficient since we are
+ # just declaring a pointer.
+ cls._value_dict['swig_predecls'] = \
+ cls._value_dict['cxx_predecls']
+
# Now process the _value_dict items. They could be defining
# new (or overriding existing) parameters or ports, setting
# class keywords (e.g., 'abstract'), or setting parameter
else:
setattr(cls, key, val)
- cls.cxx_type = cls.type + '*'
- # A forward class declaration is sufficient since we are just
- # declaring a pointer.
- cls.cxx_predecls = ['class %s;' % cls.type]
- cls.swig_predecls = cls.cxx_predecls
-
def _set_keyword(cls, keyword, val, kwtype):
if not isinstance(val, kwtype):
raise TypeError, 'keyword %s has bad type %s (expecting %s)' % \
return cls.__name__
def cxx_decl(cls):
- code = "#ifndef __PARAMS__%s\n#define __PARAMS__%s\n\n" % (cls, cls)
-
if str(cls) != 'SimObject':
base = cls.__bases__[0].type
else:
base = None
+ code = "#ifndef __PARAMS__%s\n" % cls
+ code += "#define __PARAMS__%s\n\n" % cls
+
# The 'dict' attribute restricts us to the params declared in
# the object itself, not including inherited params (which
# will also be inherited from the base class's param struct
# here).
- params = cls._params.dict.values()
+ params = cls._params.local.values()
try:
ptypes = [p.ptype for p in params]
except:
raise
# get a list of lists of predeclaration lines
- predecls = [p.cxx_predecls() for p in params]
- # flatten
- predecls = reduce(lambda x,y:x+y, predecls, [])
+ predecls = []
+ predecls.extend(cls.cxx_predecls)
+ for p in params:
+ predecls.extend(p.cxx_predecls())
# remove redundant lines
predecls2 = []
for pd in predecls:
if base:
code += '#include "params/%s.hh"\n\n' % base
- # Generate declarations for locally defined enumerations.
- enum_ptypes = [t for t in ptypes if issubclass(t, Enum)]
- if enum_ptypes:
- code += "\n".join([t.cxx_decl() for t in enum_ptypes])
- code += "\n\n"
+ for ptype in ptypes:
+ if issubclass(ptype, Enum):
+ code += '#include "enums/%s.hh"\n' % ptype.__name__
+ code += "\n\n"
# now generate the actual param struct
code += "struct %sParams" % cls
if base:
code += " : public %sParams" % base
- code += " {\n"
+ code += "\n{\n"
+ if cls == SimObject:
+ code += " virtual ~%sParams() {}\n" % cls
+ if not hasattr(cls, 'abstract') or not cls.abstract:
+ if 'type' in cls.__dict__:
+ code += " %s create();\n" % cls.cxx_type
decls = [p.cxx_decl() for p in params]
decls.sort()
code += "".join([" %s\n" % d for d in decls])
code += "\n#endif\n"
return code
+ def cxx_type_decl(cls):
+ if str(cls) != 'SimObject':
+ base = cls.__bases__[0]
+ else:
+ base = None
+
+ code = ''
+
+ if base:
+ code += '#include "%s_type.h"\n' % base
+
+ # now generate dummy code for inheritance
+ code += "struct %s" % cls.cxx_class
+ if base:
+ code += " : public %s" % base.cxx_class
+ code += "\n{};\n"
+
+ return code
+
def swig_decl(cls):
+ code = '%%module %s\n' % cls
- code = '%%module %sParams\n' % cls
+ code += '%{\n'
+ code += '#include "params/%s.hh"\n' % cls
+ code += '%}\n\n'
if str(cls) != 'SimObject':
- base = cls.__bases__[0].type
+ base = cls.__bases__[0]
else:
base = None
# the object itself, not including inherited params (which
# will also be inherited from the base class's param struct
# here).
- params = cls._params.dict.values()
+ params = cls._params.local.values()
ptypes = [p.ptype for p in params]
# get a list of lists of predeclaration lines
- predecls = [p.swig_predecls() for p in params]
+ predecls = []
+ predecls.extend([ p.swig_predecls() for p in params ])
# flatten
predecls = reduce(lambda x,y:x+y, predecls, [])
# remove redundant lines
code += "\n\n";
if base:
- code += '%%import "python/m5/swig/%sParams.i"\n\n' % base
+ code += '%%import "params/%s.i"\n\n' % base
- code += '%{\n'
- code += '#include "params/%s.hh"\n' % cls
- code += '%}\n\n'
+ for ptype in ptypes:
+ if issubclass(ptype, Enum):
+ code += '%%import "enums/%s.hh"\n' % ptype.__name__
+ code += "\n\n"
+
+ code += '%%import "params/%s_type.hh"\n\n' % cls
code += '%%include "params/%s.hh"\n\n' % cls
return code
# get this metaclass.
__metaclass__ = MetaSimObject
type = 'SimObject'
+ abstract = True
name = Param.String("Object name")
self._parent = None
self._children = {}
self._ccObject = None # pointer to C++ object
+ self._ccParams = None
self._instantiated = False # really "cloned"
# Inherit parameter values from class using multidict so
value._maybe_set_parent(self, attr)
elif isSimObjectSequence(value):
value = SimObjVector(value)
- [v._maybe_set_parent(self, "%s%d" % (attr, i))
- for i,v in enumerate(value)]
+ if len(value) == 1:
+ value[0]._maybe_set_parent(self, attr)
+ else:
+ for i,v in enumerate(value):
+ v._maybe_set_parent(self, "%s%d" % (attr, i))
self._values[attr] = value
for child in child_names:
self._children[child].print_ini()
- # Call C++ to create C++ object corresponding to this object and
- # (recursively) all its children
- def createCCObject(self):
- self.getCCObject() # force creation
- for child in self._children.itervalues():
- child.createCCObject()
+ def getCCParams(self):
+ if self._ccParams:
+ return self._ccParams
+
+ cc_params_struct = eval('m5.objects.params.%sParams' % self.type)
+ cc_params = cc_params_struct()
+ cc_params.object = self
+ cc_params.name = str(self)
+
+ param_names = self._params.keys()
+ param_names.sort()
+ for param in param_names:
+ value = self._values.get(param)
+ if value is None:
+ continue
+
+ value = value.getValue()
+ if isinstance(self._params[param], VectorParamDesc):
+ assert isinstance(value, list)
+ vec = getattr(cc_params, param)
+ assert not len(vec)
+ for v in value:
+ vec.append(v)
+ else:
+ setattr(cc_params, param, value)
+
+ port_names = self._ports.keys()
+ port_names.sort()
+ for port_name in port_names:
+ port = self._port_refs.get(port_name, None)
+ if port != None:
+ setattr(cc_params, port_name, port)
+ self._ccParams = cc_params
+ return self._ccParams
# Get C++ object corresponding to this object, calling C++ if
# necessary to construct it. Does *not* recursively create
# children.
def getCCObject(self):
+ import internal
+ params = self.getCCParams()
if not self._ccObject:
self._ccObject = -1 # flag to catch cycles in recursion
- self._ccObject = internal.sim_object.createSimObject(self.path())
+ self._ccObject = params.create()
elif self._ccObject == -1:
raise RuntimeError, "%s: recursive call to getCCObject()" \
% self.path()
return self._ccObject
+ # Call C++ to create C++ object corresponding to this object and
+ # (recursively) all its children
+ def createCCObject(self):
+ self.getCCParams()
+ self.getCCObject() # force creation
+ for child in self._children.itervalues():
+ child.createCCObject()
+
+ def getValue(self):
+ return self.getCCObject()
+
# Create C++ port connections corresponding to the connections in
# _port_refs (& recursively for all children)
def connectPorts(self):
return system_ptr.getMemoryMode()
def changeTiming(self, mode):
+ import internal
if isinstance(self, m5.objects.System):
# i don't know if there's a better way to do this - calling
# setMemoryMode directly from self._ccObject results in calling
child.changeTiming(mode)
def takeOverFrom(self, old_cpu):
+ import internal
cpu_ptr = internal.sim_object.convertToBaseCPUPtr(old_cpu._ccObject)
self._ccObject.takeOverFrom(cpu_ptr)
# __all__ defines the list of symbols that get exported when
# 'from config import *' is invoked. Try to keep this reasonably
# short to avoid polluting other namespaces.
-__all__ = ['SimObject']
-
-# see comment on imports at end of __init__.py.
-import proxy
-import internal
-import m5
+__all__ = [ 'SimObject' ]
# Authors: Nathan Binkert
# Steve Reinhardt
-import atexit
import os
import sys
-# import the SWIG-wrapped main C++ functions
-import internal
-# import a few SWIG-wrapped items (those that are likely to be used
-# directly by user scripts) completely into this module for
-# convenience
-import event
-
-# import the m5 compile options
-import defines
+import smartdict
# define a MaxTick parameter
MaxTick = 2**63 - 1
sys.path.insert(1, path)
# make a SmartDict out of the build options for our local use
-import smartdict
build_env = smartdict.SmartDict()
-build_env.update(defines.m5_build_env)
# make a SmartDict out of the OS environment too
env = smartdict.SmartDict()
env.update(os.environ)
-# The final hook to generate .ini files. Called from the user script
-# once the config is built.
-def instantiate(root):
- # we need to fix the global frequency
- ticks.fixGlobalFrequency()
-
- root.unproxy_all()
- # ugly temporary hack to get output to config.ini
- sys.stdout = file(os.path.join(options.outdir, 'config.ini'), 'w')
- root.print_ini()
- sys.stdout.close() # close config.ini
- sys.stdout = sys.__stdout__ # restore to original
-
- # load config.ini into C++
- internal.core.loadIniFile(resolveSimObject)
-
- # Initialize the global statistics
- internal.stats.initSimStats()
-
- # Create the C++ sim objects and connect ports
- root.createCCObject()
- root.connectPorts()
-
- # Do a second pass to finish initializing the sim objects
- internal.sim_object.initAll()
-
- # Do a third pass to initialize statistics
- internal.sim_object.regAllStats()
-
- # Check to make sure that the stats package is properly initialized
- internal.stats.check()
-
- # Reset to put the stats in a consistent state.
- internal.stats.reset()
-
-def doDot(root):
- dot = pydot.Dot()
- instance.outputDot(dot)
- dot.orientation = "portrait"
- dot.size = "8.5,11"
- dot.ranksep="equally"
- dot.rank="samerank"
- dot.write("config.dot")
- dot.write_ps("config.ps")
-
-need_resume = []
-need_startup = True
-def simulate(*args, **kwargs):
- global need_resume, need_startup
-
- if need_startup:
- internal.core.SimStartup()
- need_startup = False
-
- for root in need_resume:
- resume(root)
- need_resume = []
-
- return internal.event.simulate(*args, **kwargs)
-
-# Export curTick to user script.
-def curTick():
- return internal.core.cvar.curTick
-
-# Python exit handlers happen in reverse order. We want to dump stats last.
-atexit.register(internal.stats.dump)
-
-# register our C++ exit callback function with Python
-atexit.register(internal.core.doExitCleanup)
-
-# This loops until all objects have been fully drained.
-def doDrain(root):
- all_drained = drain(root)
- while (not all_drained):
- all_drained = drain(root)
-
-# Tries to drain all objects. Draining might not be completed unless
-# all objects return that they are drained on the first call. This is
-# because as objects drain they may cause other objects to no longer
-# be drained.
-def drain(root):
- all_drained = False
- drain_event = internal.event.createCountedDrain()
- unready_objects = root.startDrain(drain_event, True)
- # If we've got some objects that can't drain immediately, then simulate
- if unready_objects > 0:
- drain_event.setCount(unready_objects)
- simulate()
- else:
- all_drained = True
- internal.event.cleanupCountedDrain(drain_event)
- return all_drained
-
-def resume(root):
- root.resume()
-
-def checkpoint(root, dir):
- if not isinstance(root, objects.Root):
- raise TypeError, "Checkpoint must be called on a root object."
- doDrain(root)
- print "Writing checkpoint"
- internal.sim_object.serializeAll(dir)
- resume(root)
-
-def restoreCheckpoint(root, dir):
- print "Restoring from checkpoint"
- internal.sim_object.unserializeAll(dir)
- need_resume.append(root)
-
-def changeToAtomic(system):
- if not isinstance(system, (objects.Root, objects.System)):
- raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \
- (type(system), objects.Root, objects.System)
- if system.getMemoryMode() != internal.sim_object.SimObject.Atomic:
- doDrain(system)
- print "Changing memory mode to atomic"
- system.changeTiming(internal.sim_object.SimObject.Atomic)
-
-def changeToTiming(system):
- if not isinstance(system, (objects.Root, objects.System)):
- raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \
- (type(system), objects.Root, objects.System)
-
- if system.getMemoryMode() != internal.sim_object.SimObject.Timing:
- doDrain(system)
- print "Changing memory mode to timing"
- system.changeTiming(internal.sim_object.SimObject.Timing)
-
-def switchCpus(cpuList):
- print "switching cpus"
- if not isinstance(cpuList, list):
- raise RuntimeError, "Must pass a list to this function"
- for i in cpuList:
- if not isinstance(i, tuple):
- raise RuntimeError, "List must have tuples of (oldCPU,newCPU)"
-
- [old_cpus, new_cpus] = zip(*cpuList)
-
- for cpu in old_cpus:
- if not isinstance(cpu, objects.BaseCPU):
- raise TypeError, "%s is not of type BaseCPU" % cpu
- for cpu in new_cpus:
- if not isinstance(cpu, objects.BaseCPU):
- raise TypeError, "%s is not of type BaseCPU" % cpu
-
- # Drain all of the individual CPUs
- drain_event = internal.event.createCountedDrain()
- unready_cpus = 0
- for old_cpu in old_cpus:
- unready_cpus += old_cpu.startDrain(drain_event, False)
- # If we've got some objects that can't drain immediately, then simulate
- if unready_cpus > 0:
- drain_event.setCount(unready_cpus)
- simulate()
- internal.event.cleanupCountedDrain(drain_event)
- # Now all of the CPUs are ready to be switched out
- for old_cpu in old_cpus:
- old_cpu._ccObject.switchOut()
- index = 0
- for new_cpu in new_cpus:
- new_cpu.takeOverFrom(old_cpus[index])
- new_cpu._ccObject.resume()
- index += 1
-
# Since we have so many mutual imports in this package, we should:
# 1. Put all intra-package imports at the *bottom* of the file, unless
# they're absolutely needed before that (for top-level statements
# you can get the wrong result if foo is only partially imported
# at the point you do that (i.e., because foo is in the middle of
# importing *you*).
-from main import options
-import objects
+try:
+ import internal
+ running_m5 = True
+except ImportError:
+ running_m5 = False
+
+if running_m5:
+ from event import *
+ from simulate import *
+ from main import options
+
+if running_m5:
+ import defines
+ build_env.update(defines.m5_build_env)
+else:
+ import __scons
+ build_env.update(__scons.m5_build_env)
+
+import SimObject
import params
-from SimObject import resolveSimObject
+import objects
--- /dev/null
+# Copyright (c) 2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+# Steve Reinhardt
+
+import os
+
+# import the m5 compile options
+import defines
+
+# make a SmartDict out of the build options for our local use
+import smartdict
+build_env = smartdict.SmartDict()
+build_env.update(defines.m5_build_env)
+
+# make a SmartDict out of the OS environment too
+env = smartdict.SmartDict()
+env.update(os.environ)
+
import copy
import datetime
import inspect
+import re
import sys
import time
import ticks
from util import *
+import SimObject
+
+def isSimObject(*args, **kwargs):
+ return SimObject.isSimObject(*args, **kwargs)
+
+def isSimObjectSequence(*args, **kwargs):
+ return SimObject.isSimObjectSequence(*args, **kwargs)
+
+def isSimObjectClass(*args, **kwargs):
+ return SimObject.isSimObjectClass(*args, **kwargs)
+
# Dummy base class to identify types that are legitimate for SimObject
# parameters.
class ParamValue(object):
def __getattr__(self, attr):
if attr == 'ptype':
try:
- ptype = eval(self.ptype_str, objects.__dict__)
+ ptype = SimObject.allClasses[self.ptype_str]
if not isinstance(ptype, type):
raise NameError
self.ptype = ptype
return ptype
except NameError:
- raise TypeError, \
- "Param qualifier '%s' is not a type" % self.ptype_str
+ raise
+ #raise TypeError, \
+ # "Param qualifier '%s' is not a type" % self.ptype_str
raise AttributeError, "'%s' object has no attribute '%s'" % \
(type(self).__name__, attr)
def ini_str(self):
return ' '.join([v.ini_str() for v in self])
+ def getValue(self):
+ return [ v.getValue() for v in self ]
+
def unproxy(self, base):
return [v.unproxy(base) for v in self]
if isinstance(value, (list, tuple)):
# list: coerce each element into new list
tmp_list = [ ParamDesc.convert(self, v) for v in value ]
- if isSimObjectSequence(tmp_list):
- return SimObjVector(tmp_list)
- else:
- return VectorParamValue(tmp_list)
else:
- # singleton: leave it be (could coerce to a single-element
- # list here, but for some historical reason we don't...
- return ParamDesc.convert(self, value)
+ # singleton: coerce to a single-element list
+ tmp_list = [ ParamDesc.convert(self, value) ]
- def cxx_predecls(self):
- return ['#include <vector>'] + self.ptype.cxx_predecls
+ if isSimObjectSequence(tmp_list):
+ return SimObjVector(tmp_list)
+ else:
+ return VectorParamValue(tmp_list)
def swig_predecls(self):
- return ['%include "std_vector.i"'] + self.ptype.swig_predecls
+ return ['%%include "%s_vptype.i"' % self.ptype_str]
+
+ def swig_decl(self):
+ cxx_type = re.sub('std::', '', self.ptype.cxx_type)
+ vdecl = 'namespace std { %%template(vector_%s) vector< %s >; }' % \
+ (self.ptype_str, cxx_type)
+ return ['%include "std_vector.i"'] + self.ptype.swig_predecls + [vdecl]
+
+ def cxx_predecls(self):
+ return ['#include <vector>'] + self.ptype.cxx_predecls
def cxx_decl(self):
return 'std::vector< %s > %s;' % (self.ptype.cxx_type, self.name)
cxx_predecls = ['#include <string>']
swig_predecls = ['%include "std_string.i"\n' +
'%apply const std::string& {std::string *};']
- pass
+ swig_predecls = ['%include "std_string.i"' ]
+
+ def getValue(self):
+ return self
# superclass for "numeric" parameter values, to emulate math
# operations in a type-safe way. e.g., a Latency times an int returns
if not cls.swig_predecls:
# most derived types require this, so we just do it here once
- cls.swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
+ cls.swig_predecls = ['%import "stdint.i"\n' +
'%import "sim/host.hh"']
if not (hasattr(cls, 'min') and hasattr(cls, 'max')):
% type(value).__name__
self._check()
+ def getValue(self):
+ return long(self.value)
+
class Int(CheckedInt): cxx_type = 'int'; size = 32; unsigned = False
class Unsigned(CheckedInt): cxx_type = 'unsigned'; size = 32; unsigned = True
class Float(ParamValue, float):
cxx_type = 'double'
+ def getValue(self):
+ return float(self.value)
+
class MemorySize(CheckedInt):
cxx_type = 'uint64_t'
size = 64
class Addr(CheckedInt):
cxx_type = 'Addr'
- cxx_predecls = ['#include "targetarch/isa_traits.hh"']
+ cxx_predecls = ['#include "arch/isa_traits.hh"']
size = 64
unsigned = True
def __init__(self, value):
class AddrRange(Range):
type = Addr
+ swig_predecls = ['%include "python/swig/range.i"']
+
+ def getValue(self):
+ from m5.objects.params import AddrRange
+
+ value = AddrRange()
+ value.start = long(self.first)
+ value.end = long(self.second)
+ return value
class TickRange(Range):
type = Tick
+ swig_predecls = ['%include "python/swig/range.i"']
+
+ def getValue(self):
+ from m5.objects.params import TickRange
+
+ value = TickRange()
+ value.start = long(self.first)
+ value.end = long(self.second)
+ return value
# Boolean parameter type. Python doesn't let you subclass bool, since
# it doesn't want to let you create multiple instances of True and
except TypeError:
self.value = bool(value)
+ def getValue(self):
+ return bool(self.value)
+
def __str__(self):
return str(self.value)
class EthernetAddr(ParamValue):
cxx_type = 'Net::EthAddr'
cxx_predecls = ['#include "base/inet.hh"']
- swig_predecls = ['class Net::EthAddr;']
+ swig_predecls = ['%include "python/swig/inet.i"']
def __init__(self, value):
if value == NextEthernetAddr:
self.value = value
return EthernetAddr(self.value())
return self
+ def getValue(self):
+ from m5.objects.params import EthAddr
+ return EthAddr(self.value)
+
def ini_str(self):
return self.value
raise ValueError, "Could not parse '%s' as a time" % value
class Time(ParamValue):
- cxx_type = 'time_t'
+ cxx_type = 'tm'
+ cxx_predecls = [ '#include <time.h>' ]
+ swig_predecls = [ '%include "python/swig/time.i"' ]
def __init__(self, value):
self.value = parse_time(value)
+ def getValue(self):
+ from m5.objects.params import tm
+
+ c_time = tm()
+ py_time = self.value
+
+ # UNIX is years since 1900
+ c_time.tm_year = py_time.tm_year - 1900;
+
+ # Python starts at 1, UNIX starts at 0
+ c_time.tm_mon = py_time.tm_mon - 1;
+ c_time.tm_mday = py_time.tm_mday;
+ c_time.tm_hour = py_time.tm_hour;
+ c_time.tm_min = py_time.tm_min;
+ c_time.tm_sec = py_time.tm_sec;
+
+ # Python has 0 as Monday, UNIX is 0 as sunday
+ c_time.tm_wday = py_time.tm_wday + 1
+ if c_time.tm_wday > 6:
+ c_time.tm_wday -= 7;
+
+ # Python starts at 1, Unix starts at 0
+ c_time.tm_yday = py_time.tm_yday - 1;
+
+ return c_time
+
def __str__(self):
- tm = self.value
- return ' '.join([ str(tm[i]) for i in xrange(8)])
+ return time.asctime(self.value)
def ini_str(self):
return str(self)
# classes (_ListEnum and _DictEnum) to serve as base classes, then
# derive the new type from the appropriate base class on the fly.
-
+allEnums = {}
# Metaclass for Enum types
class MetaEnum(type):
+ def __new__(mcls, name, bases, dict):
+ assert name not in allEnums
+
+ cls = super(MetaEnum, mcls).__new__(mcls, name, bases, dict)
+ allEnums[name] = cls
+ return cls
+
def __init__(cls, name, bases, init_dict):
if init_dict.has_key('map'):
if not isinstance(cls.map, dict):
raise TypeError, "Enum-derived class must define "\
"attribute 'map' or 'vals'"
- cls.cxx_type = name + '::Enum'
+ cls.cxx_type = 'Enums::%s' % name
super(MetaEnum, cls).__init__(name, bases, init_dict)
+ def __str__(cls):
+ return cls.__name__
+
# Generate C++ class declaration for this enum type.
# Note that we wrap the enum in a class/struct to act as a namespace,
# so that the enum strings can be brief w/o worrying about collisions.
def cxx_decl(cls):
- s = 'struct %s {\n enum Enum {\n ' % cls.__name__
- s += ',\n '.join(['%s = %d' % (v,cls.map[v]) for v in cls.vals])
- s += '\n };\n};\n'
- return s
+ code = "#ifndef __ENUM__%s\n" % cls
+ code += '#define __ENUM__%s\n' % cls
+ code += '\n'
+ code += 'namespace Enums {\n'
+ code += ' enum %s {\n' % cls
+ for val in cls.vals:
+ code += ' %s = %d,\n' % (val, cls.map[val])
+ code += ' Num_%s = %d,\n' % (cls, len(cls.vals))
+ code += ' };\n'
+ code += ' extern const char *%sStrings[Num_%s];\n' % (cls, cls)
+ code += '}\n'
+ code += '\n'
+ code += '#endif\n'
+ return code
+
+ def cxx_def(cls):
+ code = '#include "enums/%s.hh"\n' % cls
+ code += 'namespace Enums {\n'
+ code += ' const char *%sStrings[Num_%s] =\n' % (cls, cls)
+ code += ' {\n'
+ for val in cls.vals:
+ code += ' "%s",\n' % val
+ code += ' };\n'
+ code += '}\n'
+ return code
# Base class for enum types.
class Enum(ParamValue):
% (value, self.vals)
self.value = value
+ def getValue(self):
+ return int(self.map[self.value])
+
def __str__(self):
return self.value
class TickParamValue(NumericParamValue):
cxx_type = 'Tick'
cxx_predecls = ['#include "sim/host.hh"']
- swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
+ swig_predecls = ['%import "stdint.i"\n' +
'%import "sim/host.hh"']
+ def getValue(self):
+ return long(self.value)
+
class Latency(TickParamValue):
def __init__(self, value):
if isinstance(value, (Latency, Clock)):
return Frequency(self)
raise AttributeError, "Latency object has no attribute '%s'" % attr
- # convert latency to ticks
- def ini_str(self):
+ def getValue(self):
if self.ticks or self.value == 0:
- return '%d' % self.value
+ value = self.value
else:
- return '%d' % (ticks.fromSeconds(self.value))
+ value = ticks.fromSeconds(self.value)
+ return long(value)
+
+ # convert latency to ticks
+ def ini_str(self):
+ return '%d' % self.getValue()
class Frequency(TickParamValue):
def __init__(self, value):
raise AttributeError, "Frequency object has no attribute '%s'" % attr
# convert latency to ticks
- def ini_str(self):
+ def getValue(self):
if self.ticks or self.value == 0:
- return '%d' % self.value
+ value = self.value
else:
- return '%d' % (ticks.fromSeconds(1.0 / self.value))
+ value = ticks.fromSeconds(1.0 / self.value)
+ return long(value)
+
+ def ini_str(self):
+ return '%d' % self.getValue()
# A generic frequency and/or Latency value. Value is stored as a latency,
# but to avoid ambiguity this object does not support numeric ops (* or /).
class Clock(ParamValue):
cxx_type = 'Tick'
cxx_predecls = ['#include "sim/host.hh"']
- swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
+ swig_predecls = ['%import "stdint.i"\n' +
'%import "sim/host.hh"']
def __init__(self, value):
if isinstance(value, (Latency, Clock)):
return Latency(self)
raise AttributeError, "Frequency object has no attribute '%s'" % attr
+ def getValue(self):
+ return self.period.getValue()
+
def ini_str(self):
return self.period.ini_str()
def __str__(self):
return str(self.val)
- def ini_str(self):
+ def getValue(self):
# convert to seconds per byte
value = 8.0 / float(self)
# convert to ticks per byte
- return '%f' % (ticks.fromSeconds(value))
+ value = ticks.fromSeconds(value)
+ return float(value)
+
+ def ini_str(self):
+ return '%f' % self.getValue()
class MemoryBandwidth(float,ParamValue):
cxx_type = 'float'
def __str__(self):
return str(self.val)
- def ini_str(self):
+ def getValue(self):
# convert to seconds per byte
value = 1.0 / float(self)
# convert to ticks per byte
- return '%f' % (ticks.fromSeconds(value))
+ value = ticks.fromSeconds(value)
+ return float(value)
+
+ def ini_str(self):
+ return '%f' % self.getValue()
#
# "Constants"... handy aliases for various values.
def set_path(self, parent, name):
pass
+
def __str__(self):
return 'Null'
+ def getValue(self):
+ return None
+
# The only instance you'll ever need...
NULL = NullSimObject()
# Call C++ to create corresponding port connection between C++ objects
def ccConnect(self):
+ import internal
+
if self.ccConnected: # already done this
return
peer = self.peer
ptype_str = 'Port'
ptype = Port
-
__all__ = ['Param', 'VectorParam',
'Enum', 'Bool', 'String', 'Float',
'Int', 'Unsigned', 'Int8', 'UInt8', 'Int16', 'UInt16',
'Time',
'NextEthernetAddr', 'NULL',
'Port', 'VectorPort']
-
-# see comment on imports at end of __init__.py.
-from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass
-import objects
-import internal
--- /dev/null
+# Copyright (c) 2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+# Steve Reinhardt
+
+import atexit
+import os
+import sys
+
+# import the SWIG-wrapped main C++ functions
+import internal
+from main import options
+import SimObject
+import ticks
+
+# The final hook to generate .ini files. Called from the user script
+# once the config is built.
+def instantiate(root):
+ # we need to fix the global frequency
+ ticks.fixGlobalFrequency()
+
+ root.unproxy_all()
+ # ugly temporary hack to get output to config.ini
+ sys.stdout = file(os.path.join(options.outdir, 'config.ini'), 'w')
+ root.print_ini()
+ sys.stdout.close() # close config.ini
+ sys.stdout = sys.__stdout__ # restore to original
+
+ # Initialize the global statistics
+ internal.stats.initSimStats()
+
+ # Create the C++ sim objects and connect ports
+ root.createCCObject()
+ root.connectPorts()
+
+ # Do a second pass to finish initializing the sim objects
+ internal.sim_object.initAll()
+
+ # Do a third pass to initialize statistics
+ internal.sim_object.regAllStats()
+
+ # Check to make sure that the stats package is properly initialized
+ internal.stats.check()
+
+ # Reset to put the stats in a consistent state.
+ internal.stats.reset()
+
+def doDot(root):
+ dot = pydot.Dot()
+ instance.outputDot(dot)
+ dot.orientation = "portrait"
+ dot.size = "8.5,11"
+ dot.ranksep="equally"
+ dot.rank="samerank"
+ dot.write("config.dot")
+ dot.write_ps("config.ps")
+
+need_resume = []
+need_startup = True
+def simulate(*args, **kwargs):
+ global need_resume, need_startup
+
+ if need_startup:
+ internal.core.SimStartup()
+ need_startup = False
+
+ for root in need_resume:
+ resume(root)
+ need_resume = []
+
+ return internal.event.simulate(*args, **kwargs)
+
+# Export curTick to user script.
+def curTick():
+ return internal.core.cvar.curTick
+
+# Python exit handlers happen in reverse order. We want to dump stats last.
+atexit.register(internal.stats.dump)
+
+# register our C++ exit callback function with Python
+atexit.register(internal.core.doExitCleanup)
+
+# This loops until all objects have been fully drained.
+def doDrain(root):
+ all_drained = drain(root)
+ while (not all_drained):
+ all_drained = drain(root)
+
+# Tries to drain all objects. Draining might not be completed unless
+# all objects return that they are drained on the first call. This is
+# because as objects drain they may cause other objects to no longer
+# be drained.
+def drain(root):
+ all_drained = False
+ drain_event = internal.event.createCountedDrain()
+ unready_objects = root.startDrain(drain_event, True)
+ # If we've got some objects that can't drain immediately, then simulate
+ if unready_objects > 0:
+ drain_event.setCount(unready_objects)
+ simulate()
+ else:
+ all_drained = True
+ internal.event.cleanupCountedDrain(drain_event)
+ return all_drained
+
+def resume(root):
+ root.resume()
+
+def checkpoint(root, dir):
+ if not isinstance(root, objects.Root):
+ raise TypeError, "Checkpoint must be called on a root object."
+ doDrain(root)
+ print "Writing checkpoint"
+ internal.sim_object.serializeAll(dir)
+ resume(root)
+
+def restoreCheckpoint(root, dir):
+ print "Restoring from checkpoint"
+ internal.sim_object.unserializeAll(dir)
+ need_resume.append(root)
+
+def changeToAtomic(system):
+ if not isinstance(system, (objects.Root, objects.System)):
+ raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \
+ (type(system), objects.Root, objects.System)
+ if system.getMemoryMode() != internal.sim_object.SimObject.Atomic:
+ doDrain(system)
+ print "Changing memory mode to atomic"
+ system.changeTiming(internal.sim_object.SimObject.Atomic)
+
+def changeToTiming(system):
+ if not isinstance(system, (objects.Root, objects.System)):
+ raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \
+ (type(system), objects.Root, objects.System)
+
+ if system.getMemoryMode() != internal.sim_object.SimObject.Timing:
+ doDrain(system)
+ print "Changing memory mode to timing"
+ system.changeTiming(internal.sim_object.SimObject.Timing)
+
+def switchCpus(cpuList):
+ print "switching cpus"
+ if not isinstance(cpuList, list):
+ raise RuntimeError, "Must pass a list to this function"
+ for i in cpuList:
+ if not isinstance(i, tuple):
+ raise RuntimeError, "List must have tuples of (oldCPU,newCPU)"
+
+ [old_cpus, new_cpus] = zip(*cpuList)
+
+ for cpu in old_cpus:
+ if not isinstance(cpu, objects.BaseCPU):
+ raise TypeError, "%s is not of type BaseCPU" % cpu
+ for cpu in new_cpus:
+ if not isinstance(cpu, objects.BaseCPU):
+ raise TypeError, "%s is not of type BaseCPU" % cpu
+
+ # Drain all of the individual CPUs
+ drain_event = internal.event.createCountedDrain()
+ unready_cpus = 0
+ for old_cpu in old_cpus:
+ unready_cpus += old_cpu.startDrain(drain_event, False)
+ # If we've got some objects that can't drain immediately, then simulate
+ if unready_cpus > 0:
+ drain_event.setCount(unready_cpus)
+ simulate()
+ internal.event.cleanupCountedDrain(drain_event)
+ # Now all of the CPUs are ready to be switched out
+ for old_cpu in old_cpus:
+ old_cpu._ccObject.switchOut()
+ index = 0
+ for new_cpu in new_cpus:
+ new_cpu.takeOverFrom(old_cpus[index])
+ new_cpu._ccObject.resume()
+ index += 1
import sys
-import convert
-import internal
-
tps = 1.0e12 # default to 1 THz (1 Tick == 1 ps)
tps_fixed = False # once set to true, can't be changed
# fix the global frequency and tell C++ about it
def fixGlobalFrequency():
+ import internal
global tps, tps_fixed
if not tps_fixed:
tps_fixed = True
print "Global frequency set at %d ticks per second" % int(tps)
def setGlobalFrequency(ticksPerSecond):
+ import convert
+
global tps, tps_fixed
if tps_fixed:
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+%{
+#include "base/inet.hh"
+%}
+
+namespace Net {
+struct EthAddr
+{
+ EthAddr();
+ EthAddr(const uint8_t ea[6]);
+ EthAddr(const std::string &addr);
+};
+}
+
#include "base/output.hh"
#include "mem/mem_object.hh"
#include "mem/port.hh"
-#include "sim/builder.hh"
#include "sim/sim_object.hh"
using namespace std;
return inifile;
}
-SimObject *
-createSimObject(const string &name)
-{
- return SimObjectClass::createObject(inifile(), name);
-}
-
/**
* Pointer to the Python function that maps names to SimObjects.
*/
loadIniFile(PyObject *_resolveFunc)
{
resolveFunc = _resolveFunc;
- configStream = simout.find("config.out");
// The configuration database is now complete; start processing it.
inifile().load(simout.resolve("config.ini"));
#include "sim/sim_object.hh"
#include "sim/system.hh"
-SimObject *createSimObject(const std::string &name);
extern "C" SimObject *convertSwigSimObjectPtr(PyObject *);
SimObject *resolveSimObject(const std::string &name);
void loadIniFile(PyObject *_resolveFunc);
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+%include "base/range.hh"
+%include "sim/host.hh"
+
+%template(AddrRange) Range<Addr>;
+%template(TickRange) Range<Tick>;
%module sim_object
%{
+#include "enums/MemoryMode.hh"
#include "python/swig/pyobject.hh"
%}
Drained
};
- enum MemoryMode {
- Invalid,
- Atomic,
- Timing
- };
-
unsigned int drain(Event *drain_event);
void resume();
void switchOut();
private:
System();
public:
- SimObject::MemoryMode getMemoryMode();
- void setMemoryMode(SimObject::MemoryMode mode);
+ Enums::MemoryMode getMemoryMode();
+ void setMemoryMode(Enums::MemoryMode mode);
};
-SimObject *createSimObject(const std::string &name);
-
int connectPorts(SimObject *o1, const std::string &name1, int i1,
SimObject *o2, const std::string &name2, int i2);
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+%{
+#include <sys/time.h>
+%}
+
+struct tm {
+ int tm_sec; /* seconds after the minute [0-60] */
+ int tm_min; /* minutes after the hour [0-59] */
+ int tm_hour; /* hours since midnight [0-23] */
+ int tm_mday; /* day of the month [1-31] */
+ int tm_mon; /* months since January [0-11] */
+ int tm_year; /* years since 1900 */
+ int tm_wday; /* days since Sunday [0-6] */
+ int tm_yday; /* days since January 1 [0-365] */
+};
SimObject('System.py')
Source('async.cc')
-Source('builder.cc')
Source('core.cc')
Source('debug.cc')
Source('eventq.cc')
Source('faults.cc')
Source('main.cc')
-Source('param.cc')
Source('root.cc')
Source('serialize.cc')
Source('sim_events.cc')
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- */
-
-#include <assert.h>
-
-#include "base/inifile.hh"
-#include "base/misc.hh"
-#include "sim/builder.hh"
-#include "sim/host.hh"
-#include "sim/sim_object.hh"
-#include "sim/core.hh"
-
-using namespace std;
-
-SimObjectBuilder::SimObjectBuilder(const std::string &_iniSection)
- : ParamContext(_iniSection)
-{
-}
-
-SimObjectBuilder::~SimObjectBuilder()
-{
-}
-
-///////////////////////////////////////////
-//
-// SimObjectBuilder member definitions
-//
-///////////////////////////////////////////
-
-// override ParamContext::parseParams() to check params based on
-// instance name first. If not found, then check based on iniSection
-// (as in default ParamContext implementation).
-void
-SimObjectBuilder::parseParams(IniFile &iniFile)
-{
- iniFilePtr = &iniFile; // set object member
-
- ParamList::iterator i;
-
- for (i = paramList->begin(); i != paramList->end(); ++i) {
- string string_value;
- if (iniFile.find(iniSection, (*i)->name, string_value))
- (*i)->parse(string_value);
- }
-}
-
-
-void
-SimObjectBuilder::printErrorProlog(ostream &os)
-{
- ccprintf(os, "Error creating object '%s':\n", iniSection);
-}
-
-
-////////////////////////////////////////////////////////////////////////
-//
-// SimObjectClass member definitions
-//
-////////////////////////////////////////////////////////////////////////
-
-// Map of class names to SimObjectBuilder creation functions. Need to
-// make this a pointer so we can force initialization on the first
-// reference; otherwise, some SimObjectClass constructors may be invoked
-// before the classMap constructor.
-map<string,SimObjectClass::CreateFunc> *SimObjectClass::classMap = NULL;
-
-// SimObjectClass constructor: add mapping to classMap
-SimObjectClass::SimObjectClass(const string &className, CreateFunc createFunc)
-{
- if (classMap == NULL)
- classMap = new map<string,SimObjectClass::CreateFunc>();
-
- if ((*classMap)[className])
- panic("Error: simulation object class '%s' redefined\n", className);
-
- // add className --> createFunc to class map
- (*classMap)[className] = createFunc;
-}
-
-
-//
-//
-SimObject *
-SimObjectClass::createObject(IniFile &configDB, const std::string &iniSection)
-{
- string type;
- if (!configDB.find(iniSection, "type", type)) {
- // no C++ type associated with this object
- return NULL;
- }
-
- // look up className to get appropriate createFunc
- if (classMap->find(type) == classMap->end())
- panic("Simulator object type '%s' not found.\n", type);
-
-
- CreateFunc createFunc = (*classMap)[type];
-
- // call createFunc with config hierarchy node to get object
- // builder instance (context with parameters for object creation)
- SimObjectBuilder *objectBuilder = (*createFunc)(iniSection);
-
- assert(objectBuilder != NULL);
-
- // parse all parameters in context to generate parameter values
- objectBuilder->parseParams(configDB);
-
- // now create the actual simulation object
- SimObject *object = objectBuilder->create();
-
- assert(object != NULL);
-
- // echo object parameters to stats file (for documenting the
- // config used to generate the associated stats)
- ccprintf(*configStream, "[%s]\n", object->name());
- ccprintf(*configStream, "type=%s\n", type);
- objectBuilder->showParams(*configStream);
- ccprintf(*configStream, "\n");
-
- // done with the SimObjectBuilder now
- delete objectBuilder;
-
- return object;
-}
-
-
-//
-// static method:
-//
-void
-SimObjectClass::describeAllClasses(ostream &os)
-{
- map<string,CreateFunc>::iterator iter;
-
- for (iter = classMap->begin(); iter != classMap->end(); ++iter) {
- const string &className = iter->first;
- CreateFunc createFunc = iter->second;
-
- os << "[" << className << "]\n";
-
- // create dummy object builder just to instantiate parameters
- SimObjectBuilder *objectBuilder = (*createFunc)("");
-
- // now get the object builder to describe ite params
- objectBuilder->describeParams(os);
-
- os << endl;
-
- // done with the object builder now
- delete objectBuilder;
- }
-}
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- */
-
-#ifndef __BUILDER_HH__
-#define __BUILDER_HH__
-
-#include <iosfwd>
-#include <list>
-#include <map>
-#include <vector>
-
-#include "sim/param.hh"
-
-class SimObject;
-
-//
-// A SimObjectBuilder serves as an evaluation context for a set of
-// parameters that describe a specific instance of a SimObject. This
-// evaluation context corresponds to a section in the .ini file (as
-// with the base ParamContext) plus an optional node in the
-// configuration hierarchy (the configNode member) for resolving
-// SimObject references. SimObjectBuilder is an abstract superclass;
-// derived classes specialize the class for particular subclasses of
-// SimObject (e.g., BaseCache).
-//
-// For typical usage, see the definition of
-// SimObjectClass::createObject().
-//
-class SimObjectBuilder : public ParamContext
-{
- public:
- SimObjectBuilder(const std::string &_iniSection);
-
- virtual ~SimObjectBuilder();
-
- // call parse() on all params in this context to convert string
- // representations to parameter values
- virtual void parseParams(IniFile &iniFile);
-
- // parameter error prolog (override of ParamContext)
- virtual void printErrorProlog(std::ostream &);
-
- // generate the name for this SimObject instance (derived from the
- // configuration hierarchy node label and position)
- virtual const std::string &getInstanceName() { return iniSection; }
-
- // Create the actual SimObject corresponding to the parameter
- // values in this context. This function is overridden in derived
- // classes to call a specific constructor for a particular
- // subclass of SimObject.
- virtual SimObject *create() = 0;
-};
-
-
-//
-// Handy macros for initializing parameter members of classes derived
-// from SimObjectBuilder. Assumes that the name of the parameter
-// member object is the same as the textual parameter name seen by the
-// user. (Note that '#p' is expanded by the preprocessor to '"p"'.)
-//
-#define INIT_PARAM(p, desc) p(this, #p, desc)
-#define INIT_PARAM_DFLT(p, desc, dflt) p(this, #p, desc, dflt)
-
-//
-// Initialize an enumeration variable... assumes that 'map' is the
-// name of an array of mappings (char * for SimpleEnumParam, or
-// EnumParamMap for MappedEnumParam).
-//
-#define INIT_ENUM_PARAM(p, desc, map) \
- p(this, #p, desc, map, sizeof(map)/sizeof(map[0]))
-#define INIT_ENUM_PARAM_DFLT(p, desc, map, dflt) \
- p(this, #p, desc, map, sizeof(map)/sizeof(map[0]), dflt)
-
-//
-// An instance of SimObjectClass corresponds to a class derived from
-// SimObject. The SimObjectClass instance serves to bind the string
-// name (found in the config file) to a function that creates an
-// instance of the appropriate derived class.
-//
-// This would be much cleaner in Smalltalk or Objective-C, where types
-// are first-class objects themselves.
-//
-class SimObjectClass
-{
- public:
- // Type CreateFunc is a pointer to a function that creates a new
- // simulation object builder based on a .ini-file parameter
- // section (specified by the first string argument), a unique name
- // for the object (specified by the second string argument), and
- // an optional config hierarchy node (specified by the third
- // argument). A pointer to the new SimObjectBuilder is returned.
- typedef SimObjectBuilder *(*CreateFunc)(const std::string &iniSection);
-
- static std::map<std::string,CreateFunc> *classMap;
-
- // Constructor. For example:
- //
- // SimObjectClass baseCacheClass("BaseCache", newBaseCacheBuilder);
- //
- SimObjectClass(const std::string &className, CreateFunc createFunc);
-
- // create SimObject given name of class and pointer to
- // configuration hierarchy node
- static SimObject *createObject(IniFile &configDB,
- const std::string &iniSection);
-
- // print descriptions of all parameters registered with all
- // SimObject classes
- static void describeAllClasses(std::ostream &os);
-};
-
-//
-// Macros to encapsulate the magic of declaring & defining
-// SimObjectBuilder and SimObjectClass objects
-//
-
-#define BEGIN_DECLARE_SIM_OBJECT_PARAMS(OBJ_CLASS) \
-class OBJ_CLASS##Builder : public SimObjectBuilder \
-{ \
- public:
-
-#define END_DECLARE_SIM_OBJECT_PARAMS(OBJ_CLASS) \
- \
- OBJ_CLASS##Builder(const std::string &iniSection); \
- virtual ~OBJ_CLASS##Builder() {} \
- \
- OBJ_CLASS *create(); \
-};
-
-#define BEGIN_INIT_SIM_OBJECT_PARAMS(OBJ_CLASS) \
- OBJ_CLASS##Builder::OBJ_CLASS##Builder(const std::string &iSec) \
- : SimObjectBuilder(iSec),
-
-
-#define END_INIT_SIM_OBJECT_PARAMS(OBJ_CLASS) \
-{ \
-}
-
-#define CREATE_SIM_OBJECT(OBJ_CLASS) \
-OBJ_CLASS *OBJ_CLASS##Builder::create()
-
-#define REGISTER_SIM_OBJECT(CLASS_NAME, OBJ_CLASS) \
-SimObjectBuilder * \
-new##OBJ_CLASS##Builder(const std::string &iniSection) \
-{ \
- return new OBJ_CLASS##Builder(iniSection); \
-} \
- \
-SimObjectClass the##OBJ_CLASS##Class(CLASS_NAME, \
- new##OBJ_CLASS##Builder); \
- \
-/* see param.hh */ \
-DEFINE_SIM_OBJECT_CLASS_NAME(CLASS_NAME, OBJ_CLASS)
-
-/* Macros that use the namespace for sinic... yuk. */
-#define BEGIN_DECLARE_SIM_OBJECT_PARAMS_WNS(NAME_SPACE, OBJ_CLASS) \
-class NAME_SPACE##OBJ_CLASS##Builder : public SimObjectBuilder \
-{ \
- public:
-
-#define END_DECLARE_SIM_OBJECT_PARAMS_WNS(NAME_SPACE, OBJ_CLASS) \
- \
- NAME_SPACE##OBJ_CLASS##Builder(const std::string &iniSection); \
- virtual ~NAME_SPACE##OBJ_CLASS##Builder() {} \
- \
- NAME_SPACE::OBJ_CLASS *create(); \
-};
-
-#define BEGIN_INIT_SIM_OBJECT_PARAMS_WNS(NAME_SPACE, OBJ_CLASS) \
- NAME_SPACE::OBJ_CLASS##Builder::OBJ_CLASS##Builder(const std::string &iSec) \
- : SimObjectBuilder(iSec),
-
-
-#define END_INIT_SIM_OBJECT_PARAMS_WNS(NAME_SPACE, OBJ_CLASS) \
-{ \
-}
-
-#define CREATE_SIM_OBJECT_WNS(NAME_SPACE, OBJ_CLASS) \
-NAME_SPACE::OBJ_CLASS *NAME_SPACE##OBJ_CLASS##Builder::create()
-
-#define REGISTER_SIM_OBJECT_WNS(NAME_SPACE, CLASS_NAME, OBJ_CLASS) \
-SimObjectBuilder * \
-new##NAME_SPACEi##OBJ_CLASS##Builder(const std::string &iniSection) \
-{ \
- return new NAME_SPACE##OBJ_CLASS##Builder(iniSection); \
-} \
- \
-SimObjectClass the##NAME_SPACE##OBJ_CLASS##Class(CLASS_NAME, \
- new##NAME_SPACE##OBJ_CLASS##Builder); \
- \
-/* see param.hh */ \
-DEFINE_SIM_OBJECT_CLASS_NAME(CLASS_NAME, NAME_SPACE##OBJ_CLASS)
-
-
-
-#endif // __BUILDER_HH__
}
ostream *outputStream;
-ostream *configStream;
void
setOutputFile(const string &file)
void setOutputFile(const std::string &file);
void setOutputDir(const std::string &dir);
-/// Output stream for configuration dump.
-extern std::ostream *configStream;
-
struct Callback;
void registerExitCallback(Callback *callback);
void doExitCleanup();
#include "sim/debug.hh"
#include "sim/eventq.hh"
-#include "sim/param.hh"
#include "sim/sim_events.hh"
using namespace std;
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- */
-
-#include <algorithm>
-#include <cassert>
-#include <list>
-#include <string>
-#include <vector>
-
-#include "base/inifile.hh"
-#include "base/misc.hh"
-#include "base/range.hh"
-#include "base/str.hh"
-#include "base/trace.hh"
-#include "sim/param.hh"
-#include "sim/sim_object.hh"
-
-using namespace std;
-
-
-////////////////////////////////////////////////////////////////////////
-//
-// BaseParam member definitions
-//
-////////////////////////////////////////////////////////////////////////
-
-void
-BaseParam::die(const string &err) const
-{
- context->printErrorProlog(cerr);
- cerr << " parameter '" << name << "': "
- << err << endl;
- abort();
-}
-
-
-////////////////////////////////////////////////////////////////////////
-//
-// Param<T> and VectorParam<T> member definitions
-//
-// We implement parsing & displaying values for various parameter
-// types T using a set of overloaded functions:
-//
-// - parseParam(string s, T &value) parses s into value
-// - showParam(ostream &os, T &value) displays value on os
-//
-// By making these independent functions, we can reuse the same code
-// for type T in both Param<T> and VectorParam<T>.
-//
-// For enum types, the parseParam function requires additional
-// arguments, in which case we must specialize the Param<T>::parse and
-// VectorParam<T>::parse calls as well.
-//
-// Type-specific instances come first, followed by more generic
-// templated versions and their instantiations.
-//
-////////////////////////////////////////////////////////////////////////
-
-//
-// The base implementations use to_number for parsing and '<<' for
-// displaying, suitable for integer types.
-//
-template <class T>
-bool
-parseParam(const string &s, T &value)
-{
- return to_number(s, value);
-}
-
-template <class T>
-void
-showParam(ostream &os, T const &value)
-{
- os << value;
-}
-
-//
-// Template specializations:
-// - char (8-bit integer)
-// - floating-point types
-// - bool
-// - string
-//
-
-// Treat 8-bit ints (chars) as ints on output, not as chars
-template <>
-void
-showParam(ostream &os, const char &value)
-{
- os << (int)value;
-}
-
-
-template <>
-void
-showParam(ostream &os, const unsigned char &value)
-{
- os << (unsigned int)value;
-}
-
-
-// Use sscanf() for FP types as to_number() only handles integers
-template <>
-bool
-parseParam(const string &s, float &value)
-{
- return (sscanf(s.c_str(), "%f", &value) == 1);
-}
-
-template <>
-bool
-parseParam(const string &s, double &value)
-{
- return (sscanf(s.c_str(), "%lf", &value) == 1);
-}
-
-// Be flexible about what we take for bool
-template <>
-bool
-parseParam(const string &s, bool &value)
-{
- const string &ls = to_lower(s);
-
- if (ls == "true" || ls == "t" || ls == "yes" || ls == "y" || ls == "1") {
- value = true;
- return true;
- }
-
- if (ls == "false" || ls == "f" || ls == "no" || ls == "n" || ls == "0") {
- value = false;
- return true;
- }
-
- return false;
-}
-
-// Display bools as strings
-template <>
-void
-showParam(ostream &os, const bool &value)
-{
- os << (value ? "true" : "false");
-}
-
-
-// String requires no processing to speak of
-template <>
-bool
-parseParam(const string &s, string &value)
-{
- value = s;
- return true;
-}
-
-template <>
-bool
-parseParam(const string &s, Range<uint32_t> &value)
-{
- value = s;
- return value.valid();
-}
-
-template <>
-bool
-parseParam(const string &s, Range<uint64_t> &value)
-{
- value = s;
- return value.valid();
-}
-
-//
-// End of parseParam/showParam definitions. Now we move on to
-// incorporate them into the Param/VectorParam parse() and showValue()
-// methods.
-//
-
-// These definitions for Param<T>::parse and VectorParam<T>::parse
-// work for any type for which parseParam() takes only two arguments
-// (i.e., all the fundamental types like int, bool, etc.), thanks to
-// overloading.
-template <class T>
-void
-Param<T>::parse(const string &s)
-{
- if (parseParam(s, value)) {
- wasSet = true;
- }
- else {
- string err("could not parse \"");
-
- err += s;
- err += "\"";
-
- die(err);
- }
-}
-
-template <class T>
-void
-VectorParam<T>::parse(const string &s)
-{
- if (s.empty()) {
- wasSet = true;
- return;
- }
-
- vector<string> tokens;
-
- tokenize(tokens, s, ' ');
-
- value.resize(tokens.size());
-
- for (int i = 0; i < tokens.size(); i++) {
- // need to parse into local variable to handle vector<bool>,
- // for which operator[] returns a special reference class
- // that's not the same as 'bool&', (since it's a packed
- // vector)
- T scalar_value;
- if (!parseParam(tokens[i], scalar_value)) {
- string err("could not parse \"");
-
- err += s;
- err += "\"";
-
- die(err);
- }
-
- // assign parsed value to vector
- value[i] = scalar_value;
- }
-
- wasSet = true;
-}
-
-// These definitions for Param<T>::showValue() and
-// VectorParam<T>::showValue() work for any type where showParam()
-// takes only two arguments (i.e., everything but the SimpleEnum and
-// MappedEnum classes).
-template <class T>
-void
-Param<T>::showValue(ostream &os) const
-{
- showParam(os, value);
-}
-
-template <class T>
-void
-VectorParam<T>::showValue(ostream &os) const
-{
- for (int i = 0; i < value.size(); i++) {
- if (i != 0) {
- os << " ";
- }
- showParam(os, value[i]);
- }
-}
-
-
-#ifdef INSURE_BUILD
-#define INSTANTIATE_PARAM_TEMPLATES(type, typestr) \
-void Param<type>::showType(ostream &os) const { os << typestr; } \
-void VectorParam<type>::showType(ostream &os) const { \
- os << "vector of " << typestr; \
-} \
-template Param<type>; \
-template VectorParam<type>;
-
-#else
-// instantiate all four methods (parse/show, scalar/vector) for basic
-// types that can use the above templates
-#define INSTANTIATE_PARAM_TEMPLATES(type, typestr) \
-template bool parseParam<type>(const string &s, type &value); \
-template void showParam<type>(ostream &os, type const &value); \
-template void Param<type>::parse(const string &); \
-template void VectorParam<type>::parse(const string &); \
-template void Param<type>::showValue(ostream &) const; \
-template void VectorParam<type>::showValue(ostream &) const; \
-template <> void Param<type>::showType(ostream &os) const { os << typestr; } \
-template <> void VectorParam<type>::showType(ostream &os) const { \
- os << "vector of " << typestr; \
-}
-#endif
-
-INSTANTIATE_PARAM_TEMPLATES(unsigned long long, "ull")
-INSTANTIATE_PARAM_TEMPLATES(signed long long, "sll")
-INSTANTIATE_PARAM_TEMPLATES(unsigned long, "uns long")
-INSTANTIATE_PARAM_TEMPLATES(signed long, "long")
-INSTANTIATE_PARAM_TEMPLATES(unsigned int, "uns")
-INSTANTIATE_PARAM_TEMPLATES(signed int, "int")
-INSTANTIATE_PARAM_TEMPLATES(unsigned short, "uns short")
-INSTANTIATE_PARAM_TEMPLATES(signed short, "short")
-INSTANTIATE_PARAM_TEMPLATES(unsigned char, "uns char")
-INSTANTIATE_PARAM_TEMPLATES(signed char, "char")
-
-INSTANTIATE_PARAM_TEMPLATES(float, "float")
-INSTANTIATE_PARAM_TEMPLATES(double, "double")
-
-INSTANTIATE_PARAM_TEMPLATES(bool, "bool")
-INSTANTIATE_PARAM_TEMPLATES(string, "string")
-
-INSTANTIATE_PARAM_TEMPLATES(Range<uint64_t>, "uint64 range")
-INSTANTIATE_PARAM_TEMPLATES(Range<uint32_t>, "uint32 range")
-
-#undef INSTANTIATE_PARAM_TEMPLATES
-
-//
-// SimpleEnumParam & MappedEnumParam must specialize their parse(),
-// showValue(), and showType() methods.
-//
-
-//
-// SimpleEnumParam & SimpleEnumVectorParam
-//
-bool
-parseEnumParam(const char *const *map, const int num_values,
- const string &s, int &value)
-{
- for (int i = 0; i < num_values; ++i) {
- if (s == map[i]) {
- value = i;
- return true;
- }
- }
-
- return false;
-}
-
-void
-showEnumParam(ostream &os,
- const char *const *map, const int num_values,
- int value)
-{
- assert(0 <= value && value < num_values);
- os << map[value];
-}
-
-void
-showEnumType(ostream &os,
- const char *const *map, const int num_values)
-{
- os << "{" << map[0];
- for (int i = 1; i < num_values; ++i)
- os << "," << map[i];
-
- os << "}";
-}
-
-
-//
-// MappedEnumParam & MappedEnumVectorParam
-//
-bool
-parseEnumParam(const EnumParamMap *map, const int num_values,
- const string &s, int &value)
-{
- for (int i = 0; i < num_values; ++i) {
- if (s == map[i].name) {
- value = map[i].value;
- return true;
- }
- }
-
- return false;
-}
-
-void
-showEnumParam(ostream &os,
- const EnumParamMap *map, const int num_values,
- int value)
-{
- for (int i = 0; i < num_values; ++i) {
- if (value == map[i].value) {
- os << map[i].name;
- return;
- }
- }
-
- // if we can't find a reverse mapping just print the int value
- os << value;
-}
-
-void
-showEnumType(ostream &os,
- const EnumParamMap *map, const int num_values)
-{
- os << "{" << map[0].name;
- for (int i = 1; i < num_values; ++i)
- os << "," << map[i].name;
-
- os << "}";
-}
-
-
-template <class Map>
-void
-EnumParam<Map>::parse(const string &s)
-{
- if (parseEnumParam(map, num_values, s, value)) {
- wasSet = true;
- } else {
- string err("no match for enum string \"");
-
- err += s;
- err += "\"";
-
- die(err);
- }
-}
-
-template <class Map>
-void
-EnumVectorParam<Map>::parse(const string &s)
-{
- vector<string> tokens;
-
- if (s.empty()) {
- wasSet = true;
- return;
- }
-
- tokenize(tokens, s, ' ');
-
- value.resize(tokens.size());
-
- for (int i = 0; i < tokens.size(); i++) {
- if (!parseEnumParam(map, num_values, tokens[i], value[i])) {
- string err("no match for enum string \"");
-
- err += s;
- err += "\"";
-
- die(err);
- }
- }
-
- wasSet = true;
-}
-
-template <class Map>
-void
-EnumParam<Map>::showValue(ostream &os) const
-{
- showEnumParam(os, map, num_values, value);
-}
-
-template <class Map>
-void
-EnumVectorParam<Map>::showValue(ostream &os) const
-{
- for (int i = 0; i < value.size(); i++) {
- if (i != 0) {
- os << " ";
- }
- showEnumParam(os, map, num_values, value[i]);
- }
-}
-
-template <class Map>
-void
-EnumParam<Map>::showType(ostream &os) const
-{
- showEnumType(os, map, num_values);
-}
-
-template <class Map>
-void
-EnumVectorParam<Map>::showType(ostream &os) const
-{
- os << "vector of";
- showEnumType(os, map, num_values);
-}
-
-template class EnumParam<const char *>;
-template class EnumVectorParam<const char *>;
-
-template class EnumParam<EnumParamMap>;
-template class EnumVectorParam<EnumParamMap>;
-
-////////////////////////////////////////////////////////////////////////
-//
-// SimObjectBaseParam methods
-//
-////////////////////////////////////////////////////////////////////////
-
-bool
-parseSimObjectParam(ParamContext *context, const string &s, SimObject *&value)
-{
- SimObject *obj;
-
- if (to_lower(s) == "null") {
- // explicitly set to null by user; assume that's OK
- obj = NULL;
- }
- else {
- // defined in main.cc
- extern SimObject *resolveSimObject(const string &);
- obj = resolveSimObject(s);
-
- if (obj == NULL)
- return false;
- }
-
- value = obj;
- return true;
-}
-
-
-void
-SimObjectBaseParam::showValue(ostream &os, SimObject *value) const
-{
- os << (value ? value->name() : "null");
-}
-
-void
-SimObjectBaseParam::parse(const string &s, SimObject *&value)
-{
- if (parseSimObjectParam(context, s, value)) {
- wasSet = true;
- }
- else {
- string err("could not resolve object name \"");
-
- err += s;
- err += "\"";
-
- die(err);
- }
-}
-
-void
-SimObjectBaseParam::parse(const string &s, vector<SimObject *>&value)
-{
- vector<string> tokens;
-
- tokenize(tokens, s, ' ');
-
- value.resize(tokens.size());
-
- for (int i = 0; i < tokens.size(); i++) {
- if (!parseSimObjectParam(context, tokens[i], value[i])) {
- string err("could not resolve object name \"");
-
- err += s;
- err += "\"";
-
- die(err);
- }
- }
-
- wasSet = true;
-}
-
-////////////////////////////////////////////////////////////////////////
-//
-// ParamContext member definitions
-//
-////////////////////////////////////////////////////////////////////////
-
-ParamContext::ParamContext(const string &_iniSection)
- : iniFilePtr(NULL), // initialized on call to parseParams()
- iniSection(_iniSection), paramList(NULL)
-{
-}
-
-
-void
-ParamContext::addParam(BaseParam *param)
-{
- getParamList()->push_back(param);
-}
-
-
-void
-ParamContext::parseParams(IniFile &iniFile)
-{
- iniFilePtr = &iniFile; // set object member
-
- ParamList::iterator i;
-
- for (i = getParamList()->begin(); i != getParamList()->end(); ++i) {
- string string_value;
-
- if (iniFile.find(iniSection, (*i)->name, string_value))
- (*i)->parse(string_value);
- }
-}
-
-
-// Check parameter values for validity & consistency. Default
-// implementation is no-op; derive subclass & override to add
-// actual functionality here.
-void
-ParamContext::checkParams()
-{
- // nada
-}
-
-
-// Clean up context-related objects at end of execution. Default
-// implementation is no-op; derive subclass & override to add actual
-// functionality here.
-void
-ParamContext::cleanup()
-{
- // nada
-}
-
-
-void
-ParamContext::describeParams(ostream &os)
-{
- ParamList::iterator i;
-
- for (i = getParamList()->begin(); i != getParamList()->end(); ++i) {
- BaseParam *p = *i;
-
- os << p->name << " (";
- p->showType(os);
- os << "): " << p->description << "\n";
- }
-}
-
-
-
-void
-ParamContext::showParams(ostream &os)
-{
- ParamList::iterator i;
-
- for (i = getParamList()->begin(); i != getParamList()->end(); ++i) {
- BaseParam *p = *i;
-
- if (p->isValid()) {
- os << p->name << "=";
- p->showValue(os);
- os << endl;
- }
- else {
- os << "// "<< p->name << " not specified" << endl;
- }
- }
-}
-
-
-void
-ParamContext::printErrorProlog(ostream &os)
-{
- os << "Parameter error in section [" << iniSection << "]: " << endl;
-}
-
-void
-parseTime(const std::vector<int> &time, struct tm *tm)
-{
- memset(tm, 0, sizeof(struct tm));
-
- // UNIX is years since 1900
- tm->tm_year = time[0] - 1900;
-
- // Python starts at 1, UNIX starts at 0
- tm->tm_mon = time[1] - 1;
- tm->tm_mday = time[2];
- tm->tm_hour = time[3];
- tm->tm_min = time[4];
- tm->tm_sec = time[5];
-
- // Python has 0 as Monday, UNIX is 0 as sunday
- tm->tm_wday = time[6] + 1;
- if (tm->tm_wday > 6)
- tm->tm_wday -= 7;
-
- // Python starts at 1, Unix starts at 0
- tm->tm_yday = time[7] - 1;
-}
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- */
-
-#ifndef __SIM_PARAM_HH__
-#define __SIM_PARAM_HH__
-
-#include <iostream>
-#include <list>
-#include <string>
-#include <vector>
-
-#include "sim/startup.hh"
-
-// forward decls
-class IniFile;
-class BaseParam;
-class SimObject;
-
-//
-// The context of a parameter definition... usually a subclass of
-// SimObjectBuilder (which derives from ParamContext), but abstracted
-// here to support more global simulator control parameters as well.
-//
-class ParamContext : protected StartupCallback
-{
- protected:
-
- // .ini file (database) for parameter lookup... initialized on call
- // to parseParams()
- IniFile *iniFilePtr;
-
- // .ini file section for parameter lookup
- const std::string iniSection;
-
- typedef std::vector<BaseParam *> ParamList;
-
- // list of parameters defined in this context
- ParamList *paramList;
-
- ParamList *getParamList() {
- if (!paramList)
- paramList = new ParamList;
- return paramList;
- }
-
- public:
-
- /// Constructor.
- /// @param _iniSection Name of .ini section corresponding to this context.
- /// @param _initPhase Initialization phase (see InitPhase).
- ParamContext(const std::string &_iniSection);
- virtual ~ParamContext() {}
-
- // add a parameter to the context... called from the parameter
- // object's constructor (see BaseParam::BaseParam())
- void addParam(BaseParam *);
-
- // call parse() on all params in this context to convert string
- // representations to parameter values
- virtual void parseParams(IniFile &iniFile);
-
- // Check parameter values for validity & consistency. Default
- // implementation is no-op; derive subclass & override to add
- // actual functionality here
- virtual void checkParams();
-
- // Clean up at end of execution: close file descriptors, etc.
- // Default implementation is no-op; derive subclass & override to
- // add actual functionality here
- virtual void cleanup();
-
- // dump parameter descriptions
- void describeParams(std::ostream &);
-
- // Display the parameters & values used
- void showParams(std::ostream &);
-
- // print context information for parameter error
- virtual void printErrorProlog(std::ostream &);
-
- // generate the name for this instance of this context (used as a
- // prefix to create unique names in resolveSimObject()
- virtual const std::string &getInstanceName() { return iniSection; }
-};
-
-
-//
-// Base class for all parameter objects
-//
-class BaseParam
-{
- public:
-
- ParamContext *context;
- std::string name;
- std::string description; // text description for help message
- bool wasSet; // true if parameter was set by user
- bool hasDefault; // true if parameter has default value
-
- BaseParam(ParamContext *_context, const std::string &_name,
- const std::string &_description, bool _hasDefault)
- : context(_context), name(_name), description(_description),
- wasSet(false), hasDefault(_hasDefault)
- {
- context->addParam(this);
- }
-
- virtual ~BaseParam() {}
-
- // a parameter is valid only if its value was set by the user or
- // it has a default value
- bool isValid() const
- {
- return (wasSet || hasDefault);
- }
-
- // set value by parsing string
- virtual void parse(const std::string &s) = 0;
-
- // display value to stream
- virtual void showValue(std::ostream &) const = 0;
-
- // display type to stream
- virtual void showType(std::ostream &) const = 0;
-
- // signal parse or usage error
- virtual void die(const std::string &err) const;
-};
-
-//
-// Template classes to specialize parameters to specific types.
-//
-// Param<T> is for single-valued (scalar) parameters of type T.
-// VectorParam<T> is for multi-valued (vector) parameters of type T.
-// These are specified in the .ini file as a space-delimited list of
-// arguments.
-//
-template <class T>
-class Param : public BaseParam
-{
- protected:
-
- T value;
-
- public:
-
- // Param with default value: set value to default
- Param(ParamContext *context,
- const std::string &name, const std::string &description, T dfltValue)
- : BaseParam(context, name, description, true),
- value(dfltValue)
- {
- }
-
- // Param with no default value: leave value uninitialized
- Param(ParamContext *context,
- const std::string &name, const std::string &description)
- : BaseParam(context, name, description, false)
- {
- }
-
- virtual ~Param() {}
-
- operator T&()
- {
- // if we attempt to reference an invalid parameter (i.e., one
- // with no default value that was not set by the user), die.
- if (!isValid())
- die("not found");
- return value;
- }
-
- T returnValue() const { return value; }
-
- // display value to stream
- virtual void showValue(std::ostream &os) const;
-
- // display type to stream
- virtual void showType(std::ostream &) const;
-
- // set value by parsing string
- virtual void parse(const std::string &s);
-};
-
-
-//
-// Template class for vector-valued parameters (lists)
-//
-template <class T>
-class VectorParam : public BaseParam
-{
- protected:
-
- std::vector<T> value;
-
- public:
-
- typedef typename std::vector<T>::size_type size_type;
-
- // Param with default value: set value to default
- VectorParam(ParamContext *context, const std::string &name,
- const std::string &description,
- const std::vector<T> &dfltValue)
- : BaseParam(context, name, description, true),
- value(dfltValue)
- {
- }
-
- // Param with no default value: leave value uninitialized
- VectorParam(ParamContext *context,
- const std::string &name, const std::string &description)
- : BaseParam(context, name, description, false)
- {
- }
-
- virtual ~VectorParam() {}
-
- // basic vector access methods
- size_type size() const
- {
- if (!isValid())
- die("not found");
- return value.size();
- }
-
- const T &operator[](size_type n) const
- {
- if (!isValid())
- die("not found");
- return value[n];
- }
-
- // return reference to value vector
- operator std::vector<T>&()
- {
- if (!isValid())
- die("not found");
- return value;
- }
-
- // display value to stream
- virtual void showValue(std::ostream &os) const;
-
- // display type to stream
- virtual void showType(std::ostream &) const;
-
- // set value by parsing string
- virtual void parse(const std::string &s);
-};
-
-//
-// Specialization of Param<int> and VectorParam<int> to handle
-// enumerated types is done in two ways, using SimpleEnumParam and
-// MappedEnumParam (and their vector counterparts,
-// SimpleEnumVectorParam and MappedEnumVectorParam). SimpleEnumParam
-// takes an array of strings and maps them to integers based on array
-// index. MappedEnumParam takes an array of string-to-int mappings,
-// allowing for mapping strings to non-contiguous integer values, or
-// mapping multiple strings to the same integer value.
-//
-// Both SimpleEnumParam and MappedEnumParam are implemented using a
-// single template class, EnumParam<Map>, which takes the type of the map
-// as a parameter (const char * or EnumParamMap). Similarly,
-// SimpleEnumVectorParam and MappedEnumVectorParam are both
-// implemented using EnumVectorParam<Map>.
-//
-template <class Map>
-class EnumParam : public Param<int>
-{
- const int num_values;
- const Map *map;
-
- public:
-
- // Param with default value: set value to default
- EnumParam(ParamContext *context,
- const std::string &name, const std::string &description,
- const Map *_map, int _num_values,
- int dfltValue)
- : Param<int>(context, name, description, dfltValue),
- num_values(_num_values), map(_map)
- {
- }
-
- // Param with no default value: leave value uninitialized
- EnumParam(ParamContext *context,
- const std::string &name, const std::string &description,
- const Map *_map, int _num_values)
- : Param<int>(context, name, description),
- num_values(_num_values), map(_map)
- {
- }
-
- virtual ~EnumParam() {}
-
- // display value to stream
- virtual void showValue(std::ostream &os) const;
-
- // display type to stream
- virtual void showType(std::ostream &) const;
-
- // set value by parsing string
- virtual void parse(const std::string &s);
-};
-
-//
-// Vector counterpart to SimpleEnumParam
-//
-template <class Map>
-class EnumVectorParam : public VectorParam<int>
-{
- const int num_values;
- const Map *map;
-
- public:
-
- // Param with default value: set value to default
- EnumVectorParam(ParamContext *context,
- const std::string &name, const std::string &description,
- const Map *_map, int _num_values,
- std::vector<int> &dfltValue)
- : VectorParam<int>(context, name, description, dfltValue),
- num_values(_num_values), map(_map)
- {
- }
-
- // Param with no default value: leave value uninitialized
- EnumVectorParam(ParamContext *context,
- const std::string &name, const std::string &description,
- const Map *_map, int _num_values)
- : VectorParam<int>(context, name, description),
- num_values(_num_values), map(_map)
- {
- }
-
- virtual ~EnumVectorParam() {}
-
- // display value to stream
- virtual void showValue(std::ostream &os) const;
-
- // display type to stream
- virtual void showType(std::ostream &) const;
-
- // set value by parsing string
- virtual void parse(const std::string &s);
-};
-
-// Specialize EnumParam for a particular enumeration type ENUM
-// (automates casting to get value of enum type)
-
-template <class ENUM>
-class SimpleEnumParam : public EnumParam<const char *>
-{
- public:
-
- SimpleEnumParam(ParamContext *context,
- const std::string &name, const std::string &description,
- const char **_map, int _num_values,
- ENUM dfltValue)
- : EnumParam<const char *>(context, name, description,
- _map, _num_values, (int)dfltValue)
- {
- }
-
- SimpleEnumParam(ParamContext *context,
- const std::string &name, const std::string &description,
- const char **_map, int _num_values)
- : EnumParam<const char *>(context, name, description,
- _map, _num_values)
- {
- }
-
- operator ENUM() const
- {
- if (!isValid())
- die("not found");
- return (ENUM)value;
- }
-};
-
-
-// Specialize EnumParam for a particular enumeration type ENUM
-// (automates casting to get value of enum type)
-
-template <class ENUM>
-class SimpleEnumVectorParam : public EnumVectorParam<const char *>
-{
- public:
-
- // skip default value constructor: too much pain to convert
- // vector<ENUM> initializer to vector<int>
-
-
- SimpleEnumVectorParam(ParamContext *context,
- const std::string &name,
- const std::string &description,
- const char **_map, int _num_values)
- : EnumVectorParam<const char *>(context, name, description,
- _map, _num_values)
- {
- }
-
- ENUM operator[](size_type n)
- {
- if (!isValid())
- die("not found");
- return (ENUM)value[n];
- }
-};
-
-
-//
-// Handle enums via string-to-int map (see comment above).
-//
-
-// An array of string-to-int mappings must be supplied using the
-// following type.
-typedef struct {
- const char *name;
- int value;
-} EnumParamMap;
-
-// Specialize EnumParam for a particular enumeration type ENUM
-// (automates casting to get value of enum type)
-
-template <class ENUM>
-class MappedEnumParam : public EnumParam<EnumParamMap>
-{
- public:
-
- MappedEnumParam(ParamContext *context,
- const std::string &name, const std::string &description,
- const EnumParamMap *_map, int _num_values,
- ENUM dfltValue)
- : EnumParam<EnumParamMap>(context, name, description,
- _map, _num_values, (int)dfltValue)
- {
- }
-
- MappedEnumParam(ParamContext *context,
- const std::string &name, const std::string &description,
- const EnumParamMap *_map, int _num_values)
- : EnumParam<EnumParamMap>(context, name, description,
- _map, _num_values)
- {
- }
-
- operator ENUM()
- {
- if (!isValid())
- die("not found");
- return (ENUM)value[this->n];
- }
-};
-
-
-// Specialize EnumParam for a particular enumeration type ENUM
-// (automates casting to get value of enum type)
-
-template <class ENUM>
-class MappedEnumVectorParam : public EnumVectorParam<EnumParamMap>
-{
- public:
-
- // skip default value constructor: too much pain to convert
- // vector<ENUM> initializer to vector<int>
-
-
- MappedEnumVectorParam(ParamContext *context,
- const std::string &name,
- const std::string &description,
- const EnumParamMap *_map, int _num_values)
- : EnumVectorParam<EnumParamMap>(context, name, description,
- _map, _num_values)
- {
- }
-
- ENUM operator[](size_type n)
- {
- if (!isValid())
- die("not found");
- return (ENUM)value[n];
- }
-};
-
-
-//
-// Parameters that point to other simulation objects (e.g. caches,
-// busses, etc.) are handled by specializing SimObjectBaseParam to the
-// specific subtype. The main purpose of SimObjectBaseParam is to
-// provide a place to stick several helper functions common to all
-// SimObject-derived parameters.
-//
-class SimObjectBaseParam : public BaseParam
-{
- public:
-
- SimObjectBaseParam(ParamContext *context, const std::string &name,
- const std::string &description, bool hasDefault)
- : BaseParam(context, name, description, hasDefault)
- {
- }
-
- virtual ~SimObjectBaseParam() {}
-
- // helper function for SimObjectParam<T>::showValue()
- void showValue(std::ostream &os, SimObject *obj) const;
-
- // helper function for SimObjectParam<T>::parse()
- void parse(const std::string &s, SimObject *&value);
-
- // helper function for SimObjectParam<T>::parse()
- void parse(const std::string &s, std::vector<SimObject *>&value_vec);
-};
-
-
-//
-// Parameter to a specific type of SimObject. Note that T must be a
-// pointer to a class derived from SimObject (e.g., <CPU *>).
-//
-
-template <class T> class SimObjectParam;
-
-template <class T>
-class SimObjectParam<T *> : public SimObjectBaseParam
-{
- protected:
-
- T *value;
-
- public:
-
- // initialization w/o default
- SimObjectParam(ParamContext *context,
- const std::string &name, const std::string &description)
- : SimObjectBaseParam(context, name, description, false)
- {
- }
-
- // initialization wit=h default
- SimObjectParam(ParamContext *context,
- const std::string &name, const std::string &description,
- T *dfltValue)
- : SimObjectBaseParam(context, name, description, true),
- value(dfltValue)
- {
- }
-
- virtual ~SimObjectParam() {}
-
- // convert to pointer
- operator T*()
- {
- if (!isValid())
- die("not found");
- return value;
- }
-
- T *operator->() const
- {
- if (!isValid())
- die("not found");
- return value;
- }
-
- // display value to stream
- virtual void showValue(std::ostream &os) const
- {
- SimObjectBaseParam::showValue(os, value);
- }
-
- // display type to stream: see REGISTER_SIM_OBJECT macro in
- // sim_object.hh for declaration
- virtual void showType(std::ostream &os) const;
-
- // set value by parsing string
- virtual void parse(const std::string &s)
- {
- SimObject *so_ptr;
- // first parse to generic SimObject *
- SimObjectBaseParam::parse(s, so_ptr);
- // now dynamic_cast to specific derived type
- value = dynamic_cast<T *>(so_ptr);
- // check for failure of dynamic_cast
- if (value == NULL && so_ptr != NULL)
- die("not of appropriate type");
- }
-};
-
-
-//
-// Vector counterpart to SimObjectParam<T>
-//
-
-template <class T> class SimObjectVectorParam;
-
-template <class T>
-class SimObjectVectorParam<T *> : public SimObjectBaseParam
-{
- protected:
-
- std::vector<T *> value;
-
- public:
-
- typedef typename std::vector<T *>::size_type size_type;
-
- SimObjectVectorParam(ParamContext *context,
- const std::string &name,
- const std::string &description)
- : SimObjectBaseParam(context, name, description, false)
- {
- }
-
- SimObjectVectorParam(ParamContext *context,
- const std::string &name,
- const std::string &description,
- std::vector<T *> dfltValue)
- : SimObjectBaseParam(context, name, description, true),
- value(dfltValue)
- {
- }
-
- virtual ~SimObjectVectorParam() {}
-
- // basic vector access methods
- size_type size() const
- {
- if (!isValid())
- die("not found");
- return value.size();
- }
-
- T *&operator[](size_type n)
- {
- if (!isValid())
- die("not found");
- return value[n];
- }
-
- // return reference to value vector
- operator std::vector<T *>&()
- {
- if (!isValid())
- die("not found");
- return value;
- }
-
- // display value to stream
- virtual void showValue(std::ostream &os) const
- {
- for (int i = 0; i < value.size(); i++) {
- if (i != 0)
- os << " ";
- SimObjectBaseParam::showValue(os, value[i]);
- }
- }
-
- // display type to stream: see
- virtual void showType(std::ostream &os) const;
-
- // set value by parsing string
- virtual void parse(const std::string &s)
- {
- std::vector<SimObject *> so_ptr_vec;
- // first parse to generic SimObject * vector (from SimObjectBaseParam)
- SimObjectBaseParam::parse(s, so_ptr_vec);
-
- value.resize(so_ptr_vec.size());
-
- for (int i = 0; i < so_ptr_vec.size(); ++i) {
- // now dynamic_cast to specific derived type
- value[i] = dynamic_cast<T *>(so_ptr_vec[i]);
- // check for failure of dynamic_cast
- if (value[i] == NULL && so_ptr_vec[i] != NULL)
- die("not of appropriate type");
- }
- }
-};
-
-//
-// Macro to define showType() methods for SimObjectParam &
-// SimObjectVectorParam. Can't do this automatically as it requires a
-// string name for the type, which you can't get from a template
-// argument. For concrete derived SimObject types, this macro is
-// automatically invoked by REGISTER_SIM_OBJECT() (see sim_object.hh).
-//
-#define DEFINE_SIM_OBJECT_CLASS_NAME(CLASS_NAME, OBJ_CLASS) \
-template<> \
-void \
-SimObjectParam<OBJ_CLASS *>::showType(std::ostream &os) const \
-{ \
- os << CLASS_NAME; \
-} \
- \
-template<> \
-void \
-SimObjectVectorParam<OBJ_CLASS *>::showType(std::ostream &os) const \
-{ \
- os << "vector of " << CLASS_NAME; \
-}
-
-
-//
-// Declarations for low-level parsing & displaying functions. These
-// are used internally, but should not be used directly by clients of
-// the parameter mechanism, but are declared here so they can be
-// shared with the serialization code (see sim/serialize.cc).
-template <class T> bool parseParam(const std::string &str, T &data);
-template <class T> void showParam(std::ostream &os, const T &data);
-
-void parseTime(const std::vector<int> &time, struct tm *tm);
-#endif // _SIM_PARAM_HH_
#include "mem/page_table.hh"
#include "mem/physical.hh"
#include "mem/translating_port.hh"
-#include "sim/builder.hh"
+#include "params/LiveProcess.hh"
#include "sim/process.hh"
#include "sim/process_impl.hh"
#include "sim/stats.hh"
}
-//
-// need to declare these here since there is no concrete Process type
-// that can be constructed (i.e., no REGISTER_SIM_OBJECT() macro call,
-// which is where these get declared for concrete types).
-//
-DEFINE_SIM_OBJECT_CLASS_NAME("Process", Process)
-
-
////////////////////////////////////////////////////////////////////////
//
// LiveProcess member definitions
return process;
}
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(LiveProcess)
-
- VectorParam<string> cmd;
- Param<string> executable;
- Param<string> input;
- Param<string> output;
- VectorParam<string> env;
- Param<string> cwd;
- SimObjectParam<System *> system;
- Param<uint64_t> uid;
- Param<uint64_t> euid;
- Param<uint64_t> gid;
- Param<uint64_t> egid;
- Param<uint64_t> pid;
- Param<uint64_t> ppid;
-
-END_DECLARE_SIM_OBJECT_PARAMS(LiveProcess)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(LiveProcess)
-
- INIT_PARAM(cmd, "command line (executable plus arguments)"),
- INIT_PARAM(executable, "executable (overrides cmd[0] if set)"),
- INIT_PARAM(input, "filename for stdin (dflt: use sim stdin)"),
- INIT_PARAM(output, "filename for stdout/stderr (dflt: use sim stdout)"),
- INIT_PARAM(env, "environment settings"),
- INIT_PARAM(cwd, "current working directory"),
- INIT_PARAM(system, "system"),
- INIT_PARAM(uid, "user id"),
- INIT_PARAM(euid, "effective user id"),
- INIT_PARAM(gid, "group id"),
- INIT_PARAM(egid, "effective group id"),
- INIT_PARAM(pid, "process id"),
- INIT_PARAM(ppid, "parent process id")
-
-END_INIT_SIM_OBJECT_PARAMS(LiveProcess)
-
-
-CREATE_SIM_OBJECT(LiveProcess)
+LiveProcess *
+LiveProcessParams::create()
{
string in = input;
string out = output;
stderr_fd = (stdout_fd != STDOUT_FILENO) ? stdout_fd : STDERR_FILENO;
- return LiveProcess::create(getInstanceName(), system,
+ return LiveProcess::create(name, system,
stdin_fd, stdout_fd, stderr_fd,
(string)executable == "" ? cmd[0] : executable,
cmd, env, cwd,
uid, euid, gid, egid, pid, ppid);
}
-
-
-REGISTER_SIM_OBJECT("LiveProcess", LiveProcess)
#include <vector>
#include "base/misc.hh"
-#include "sim/builder.hh"
+#include "params/Root.hh"
#include "sim/sim_object.hh"
// Dummy Object
struct Root : public SimObject
{
- Root(const std::string &name) : SimObject(name) {}
+ Root(RootParams *params) : SimObject(params) {}
};
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Root)
-
- Param<int> dummy; // needed below
-
-END_DECLARE_SIM_OBJECT_PARAMS(Root)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Root)
-
- INIT_PARAM(dummy, "") // All SimObjects must have params
-
-END_INIT_SIM_OBJECT_PARAMS(Root)
-
-CREATE_SIM_OBJECT(Root)
+Root *
+RootParams::create()
{
static bool created = false;
if (created)
created = true;
- return new Root(getInstanceName());
+ return new Root(this);
}
-
-REGISTER_SIM_OBJECT("Root", Root)
#include "base/str.hh"
#include "base/trace.hh"
#include "sim/eventq.hh"
-#include "sim/param.hh"
#include "sim/serialize.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
extern SimObject *resolveSimObject(const string &);
+//
+// The base implementations use to_number for parsing and '<<' for
+// displaying, suitable for integer types.
+//
+template <class T>
+bool
+parseParam(const string &s, T &value)
+{
+ return to_number(s, value);
+}
+
+template <class T>
+void
+showParam(ostream &os, const T &value)
+{
+ os << value;
+}
+
+//
+// Template specializations:
+// - char (8-bit integer)
+// - floating-point types
+// - bool
+// - string
+//
+
+// Treat 8-bit ints (chars) as ints on output, not as chars
+template <>
+void
+showParam(ostream &os, const char &value)
+{
+ os << (int)value;
+}
+
+
+template <>
+void
+showParam(ostream &os, const unsigned char &value)
+{
+ os << (unsigned int)value;
+}
+
+
+// Use sscanf() for FP types as to_number() only handles integers
+template <>
+bool
+parseParam(const string &s, float &value)
+{
+ return (sscanf(s.c_str(), "%f", &value) == 1);
+}
+
+template <>
+bool
+parseParam(const string &s, double &value)
+{
+ return (sscanf(s.c_str(), "%lf", &value) == 1);
+}
+
+template <>
+bool
+parseParam(const string &s, bool &value)
+{
+ const string &ls = to_lower(s);
+
+ if (ls == "true") {
+ value = true;
+ return true;
+ }
+
+ if (ls == "false") {
+ value = false;
+ return true;
+ }
+
+ return false;
+}
+
+// Display bools as strings
+template <>
+void
+showParam(ostream &os, const bool &value)
+{
+ os << (value ? "true" : "false");
+}
+
+
+// String requires no processing to speak of
+template <>
+bool
+parseParam(const string &s, string &value)
+{
+ value = s;
+ return true;
+}
+
int Serializable::ckptMaxCount = 0;
int Serializable::ckptCount = 0;
int Serializable::ckptPrevCount = -1;
#include "base/callback.hh"
#include "base/hostinfo.hh"
#include "sim/eventq.hh"
-#include "sim/param.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
#include "sim/startup.hh"
#include "sim/host.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
-#include "sim/param.hh"
using namespace std;
//
// SimObject constructor: used to maintain static simObjectList
//
-SimObject::SimObject(Params *p)
+SimObject::SimObject(const Params *p)
: _params(p)
{
#ifdef DEBUG
state = Running;
}
-//
-// SimObject constructor: used to maintain static simObjectList
-//
+SimObjectParams *
+makeParams(const string &name)
+{
+ SimObjectParams *params = new SimObjectParams;
+ params->name = name;
+
+ return params;
+}
+
SimObject::SimObject(const string &_name)
- : _params(new Params)
+ : _params(makeParams(_name))
{
- _params->name = _name;
#ifdef DEBUG
doDebugBreak = false;
#endif
{
panic("Unimplemented!");
}
-
-DEFINE_SIM_OBJECT_CLASS_NAME("SimObject", SimObject)
#include <vector>
#include <iostream>
+#include "params/SimObject.hh"
#include "sim/serialize.hh"
#include "sim/startup.hh"
class SimObject : public Serializable, protected StartupCallback
{
public:
- struct Params {
- std::string name;
- };
-
enum State {
Running,
Draining,
Drained
};
- enum MemoryMode {
- Invalid=0,
- Atomic,
- Timing
- };
-
private:
State state;
protected:
- Params *_params;
-
void changeState(State new_state) { state = new_state; }
public:
- const Params *params() const { return _params; }
-
State getState() { return state; }
private:
// list of all instantiated simulation objects
static SimObjectList simObjectList;
+ protected:
+ const SimObjectParams *_params;
+
public:
- SimObject(Params *_params);
+ typedef SimObjectParams Params;
+ const Params *params() const { return _params; }
+ SimObject(const Params *_params);
SimObject(const std::string &_name);
-
virtual ~SimObject() {}
virtual const std::string name() const { return params()->name; }
#include "cpu/thread_context.hh"
#include "mem/mem_object.hh"
#include "mem/physical.hh"
-#include "sim/builder.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"
#if FULL_SYSTEM
#include "arch/vtophys.hh"
#include "kern/kernel_stats.hh"
+#else
+#include "params/System.hh"
#endif
using namespace std;
/**
* Load the kernel code into memory
*/
- if (params()->kernel_path == "") {
+ if (params()->kernel == "") {
warn("No kernel set for full system simulation. Assuming you know what"
" you're doing...\n");
} else {
// Load kernel code
- kernel = createObjectFile(params()->kernel_path);
+ kernel = createObjectFile(params()->kernel);
if (kernel == NULL)
- fatal("Could not load kernel file %s", params()->kernel_path);
+ fatal("Could not load kernel file %s", params()->kernel);
// Load program sections into memory
kernel->loadSections(&functionalPort, LoadAddrMask);
int rgdb_enable = true;
void
-System::setMemoryMode(MemoryMode mode)
+System::setMemoryMode(Enums::MemoryMode mode)
{
assert(getState() == Drained);
memoryMode = mode;
const char *System::MemoryModeStrings[3] = {"invalid", "atomic",
"timing"};
-#if FULL_SYSTEM
-
-// In full system mode, only derived classes (e.g. AlphaLinuxSystem)
-// can be created directly.
-
-DEFINE_SIM_OBJECT_CLASS_NAME("System", System)
-
-#else
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(System)
-
- SimObjectParam<PhysicalMemory *> physmem;
- SimpleEnumParam<System::MemoryMode> mem_mode;
-
-END_DECLARE_SIM_OBJECT_PARAMS(System)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(System)
-
- INIT_PARAM(physmem, "physical memory"),
- INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
- System::MemoryModeStrings)
-
-END_INIT_SIM_OBJECT_PARAMS(System)
+#if !FULL_SYSTEM
-CREATE_SIM_OBJECT(System)
+System *
+SystemParams::create()
{
System::Params *p = new System::Params;
- p->name = getInstanceName();
+ p->name = name;
p->physmem = physmem;
p->mem_mode = mem_mode;
return new System(p);
}
-REGISTER_SIM_OBJECT("System", System)
-
#endif
#include "base/statistics.hh"
#include "config/full_system.hh"
#include "cpu/pc_event.hh"
+#include "enums/MemoryMode.hh"
#include "mem/port.hh"
+#include "params/System.hh"
#include "sim/sim_object.hh"
#if FULL_SYSTEM
#include "kern/system_events.hh"
static const char *MemoryModeStrings[3];
- SimObject::MemoryMode getMemoryMode() { assert(memoryMode); return memoryMode; }
+ Enums::MemoryMode
+ getMemoryMode()
+ {
+ assert(memoryMode);
+ return memoryMode;
+ }
/** Change the memory mode of the system. This should only be called by the
* python!!
* @param mode Mode to change to (atomic/timing)
*/
- void setMemoryMode(SimObject::MemoryMode mode);
+ void setMemoryMode(Enums::MemoryMode mode);
PhysicalMemory *physmem;
PCEventQueue pcEventQueue;
#endif // FULL_SYSTEM
protected:
-
- SimObject::MemoryMode memoryMode;
+ Enums::MemoryMode memoryMode;
#if FULL_SYSTEM
/**
bool breakpoint();
public:
- struct Params
- {
- std::string name;
- PhysicalMemory *physmem;
- SimObject::MemoryMode mem_mode;
-
-#if FULL_SYSTEM
- Tick boot_cpu_frequency;
- std::string boot_osflags;
- uint64_t init_param;
-
- std::string kernel_path;
- std::string readfile;
- std::string symbolfile;
-#endif
- };
+ typedef SystemParams Params;
protected:
Params *_params;
--- /dev/null
+# -*- mode:python -*-
+
+# Copyright (c) 2004-2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+# Nathan Binkert
+
+Import('*')
+
+PySource('m5', 'jobfile.py')
projects / gem5.git / commitdiff