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dewildcard cache.py
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 11 Mar 2020 16:54:29 +0000
(16:54 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 11 Mar 2020 16:54:29 +0000
(16:54 +0000)
src/soc/minerva/cache.py
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diff --git
a/src/soc/minerva/cache.py
b/src/soc/minerva/cache.py
index 5cdc1e89344b1d08fec480defc1925e68ac4b187..474429116e929de7b371044709e446ca4f6a0415 100644
(file)
--- a/
src/soc/minerva/cache.py
+++ b/
src/soc/minerva/cache.py
@@
-1,5
+1,6
@@
-from nmigen import *
-from nmigen.asserts import *
+from nmigen import (Elaboratable, Module, Const, Signal, Record, Array,
+ Mux, Memory)
+from nmigen.asserts import Assume, Initial
from nmigen.lib.coding import Encoder
from nmigen.utils import log2_int