attempting to add mtcrf test, requires bringing CR and other regs into ops

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 647e58d62668819e0d9ad46c4632c67bc539afed..050e1c85c2cb45d44cd2c0a9bb870de71351e527 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -6,7 +6,8 @@ from collections import namedtuple
 import math
 
 instruction_info = namedtuple('instruction_info',
-                              'func read_regs uninit_regs write_regs op_fields form asmregs')
+                              'func read_regs uninit_regs write_regs ' + \
+                              'special_regs op_fields form asmregs')
 
 
 def create_args(reglist, extra=None):
@@ -188,7 +189,8 @@ class ISACaller:
         info = self.instrs[name]
         yield from self.prep_namespace(info.form, info.op_fields)
 
-        input_names = create_args(info.read_regs | info.uninit_regs)
+        input_names = create_args(info.read_regs | info.uninit_regs |
+                                  info.special_regs)
         print(input_names)
 
         inputs = []

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 0a26c8169883112d431b55828535038066e56633..2d2f5bdcc78977ce74f10f08285576652307443d 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -89,6 +89,15 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(2), SelectableInt(0x10008, 64))
             self.assertEqual(sim.gpr(3), SelectableInt(0x1000c, 64))
 
+    def test_mtcrf(self):
+        lst = ["addi 1, 0, 0xffffffff",
+               "mtcrf 1, 0x1",
+                               ]
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+        print ("cr", sim.cr)
+        self.assertEqual(sim.cr, SelectableInt(0xffffffff, 32))
+
     def run_tst_program(self, prog, initial_regs=[0] * 32):
         simulator = self.run_tst(prog, initial_regs)
         simulator.gpr.dump()

diff --git a/src/soc/decoder/power_pseudo.py b/src/soc/decoder/power_pseudo.py
index 3e6e064e3a59ea21d061e3a270d5475dafbabb82..67ae8bc83fef15a3f198d06afd3f442ae41083bc 100644 (file)
--- a/src/soc/decoder/power_pseudo.py
+++ b/src/soc/decoder/power_pseudo.py
@@ -221,6 +221,7 @@ def convert_to_python(pcode, form):
     regsused = {'read_regs': gsc.parser.read_regs,
                 'write_regs': gsc.parser.write_regs,
                 'uninit_regs': gsc.parser.uninit_regs,
+                'special_regs': gsc.parser.special_regs,
                 'op_fields': gsc.parser.op_fields }
     return astor.to_source(tree), regsused
 

diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py
index 664cc2f738884c3cbcfaf4cd8c8b0de360c18252..e413f4d6c8f5fb6f73c9062d1b2a29c1e7e39251 100644 (file)
--- a/src/soc/decoder/pseudo/parser.py
+++ b/src/soc/decoder/pseudo/parser.py
@@ -244,6 +244,7 @@ class PowerParser:
         self.read_regs = OrderedSet()
         self.uninit_regs = OrderedSet()
         self.write_regs = OrderedSet()
+        self.special_regs = OrderedSet() # see p_atom_name
 
     # The grammar comments come from Python's Grammar/Grammar file
 
@@ -605,6 +606,8 @@ class PowerParser:
         name = p[1]
         if name in self.available_op_fields:
             self.op_fields.add(name)
+        if name in ['CR', 'LR', 'CTR', 'TAR', 'FPSCR']:
+            self.special_regs.add(name)
         p[0] = ast.Name(id=name, ctx=ast.Load())
 
     def p_atom_number(self, p):

diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index 4b6b03abbf800e957bb8cbc367174bff443e8280..6be4ff5347460355eda511d0a86ee9e7f0975aba 100644 (file)
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -29,7 +29,8 @@ class %s:
 iinfo_template = """instruction_info(func=%s,
                 read_regs=%s,
                 uninit_regs=%s, write_regs=%s,
-                op_fields=%s, form='%s',
+                special_regs=%s, op_fields=%s,
+                form='%s',
                 asmregs=%s)"""
 
 class PyISAWriter(ISA):
@@ -75,6 +76,7 @@ class PyISAWriter(ISA):
                 iinfo = iinfo_template % (op_fname, rused['read_regs'],
                                           rused['uninit_regs'],
                                           rused['write_regs'],
+                                          rused['special_regs'],
                                           ops, d.form, d.regs)
                 iinf += "    %s_instrs['%s'] = %s\n" % (pagename, page, iinfo)
             # write out initialisation of info, for ISACaller to use
@@ -110,4 +112,4 @@ if __name__ == '__main__':
         sources = sys.argv[1:]
     for source in sources:
         isa.write_pysource(source)
-    isa.write_isa_class()
+    #isa.write_isa_class()