comment
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 31 Jul 2019 23:18:39 +0000 (00:18 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 31 Jul 2019 23:18:39 +0000 (00:18 +0100)
src/ieee754/fcvt/downsize.py

index b76e3f5e2c42a574e8ea555b601c72daad739b2a..c02dedee86fb7caabb094e03403260ca4517be20 100644 (file)
@@ -72,7 +72,7 @@ class FPCVTDownConvertMod(PipeModBase):
             comb += self.o.of.guard.eq(a1.m[ms-1])
             comb += self.o.of.round_bit.eq(a1.m[ms-2])
             comb += self.o.of.sticky.eq(a1.m[:ms-2].bool())
-            comb += self.o.of.m0.eq(a1.m[ms])  # bit of a1
+            comb += self.o.of.m0.eq(a1.m[ms])  # LSB bit of a1
 
             comb += self.o.z.s.eq(a1.s)
             comb += self.o.z.e.eq(a1.e)