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add JTAG IOpads and rename rst to sys_rst
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 22 Sep 2020 11:47:49 +0000 (12:47 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 22 Sep 2020 11:47:49 +0000 (12:47 +0100)
src/soc/litex/florent/libresoc/ls180.py patch | blob | history

diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py
index 01823135f35046979707fb2d7c13cfaf78981ddb..bcf363b5289e168068ee7325b8c835f00b6572e1 100644 (file)
--- a/src/soc/litex/florent/libresoc/ls180.py
+++ b/src/soc/litex/florent/libresoc/ls180.py
@@ -23,7 +23,14 @@ import os
 
 _io = [
     ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
-    ("rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
+    ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
+
+    ("jtag", 0,
+        Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")),
+        Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")),
+        Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")),
+        Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")),
+    ),
 
     ("serial", 0,
         Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),