("branch", [Format.PSEUDO_BRANCH], 'Pseudo_branch_instruction', itertools.product([1], [0, 1])),
("barrier", [Format.PSEUDO_BARRIER], 'Pseudo_barrier_instruction', [(0, 0)]),
("reduction", [Format.PSEUDO_REDUCTION], 'Pseudo_reduction_instruction', [(3, 2)]),
- ("vop1", [Format.VOP1], 'VOP1_instruction', [(1, 1), (2, 2)]),
+ ("vop1", [Format.VOP1], 'VOP1_instruction', [(0, 0), (1, 1), (2, 2)]),
("vop2", [Format.VOP2], 'VOP2_instruction', itertools.product([1, 2], [2, 3])),
("vop2_sdwa", [Format.VOP2, Format.SDWA], 'SDWA_instruction', itertools.product([1, 2], [2, 3])),
("vopc", [Format.VOPC], 'VOPC_instruction', itertools.product([1, 2], [2])),
finish_assembler_test();
}
END_TEST
+
+BEGIN_TEST(assembler.branch_3f)
+ if (!setup_cs(NULL, (chip_class)GFX10))
+ return;
+
+ //! BB0:
+ //! s_branch BB1 ; bf820040
+ //! s_nop 0 ; bf800000
+ bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 1);
+
+ for (unsigned i = 0; i < 0x3f; i++)
+ bld.vop1(aco_opcode::v_nop);
+
+ bld.reset(program->create_and_insert_block());
+
+ program->blocks[1].linear_preds.push_back(0u);
+
+ finish_assembler_test();
+END_TEST