# Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os)
-autoidx 3702
+autoidx 3715
attribute \src "libresoc.v:5.1-277.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.jtag._fsm"
+attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm"
attribute \generator "nMigen"
module \_fsm
attribute \src "libresoc.v:125.3-239.6"
end
attribute \src "libresoc.v:281.1-392.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.jtag._idblock"
+attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock"
attribute \generator "nMigen"
module \_idblock
attribute \src "libresoc.v:365.3-385.6"
end
attribute \src "libresoc.v:396.1-480.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.jtag._irblock"
+attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock"
attribute \generator "nMigen"
module \_irblock
attribute \src "libresoc.v:397.7-397.20"
connect \$7 $and$libresoc.v:440$73_Y
connect \tdo \ir [0]
end
-attribute \src "libresoc.v:484.1-1198.10"
+attribute \src "libresoc.v:484.1-671.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dbg"
+attribute \nmigen.hierarchy "test_issuer.clksel"
+attribute \generator "nMigen"
+module \clksel
+ attribute \src "libresoc.v:621.3-640.6"
+ wire $0\clk1$next[0:0]$115
+ attribute \src "libresoc.v:555.3-556.25"
+ wire $0\clk1[0:0]
+ attribute \src "libresoc.v:574.3-588.6"
+ wire $0\clk2$next[0:0]$103
+ attribute \src "libresoc.v:561.3-562.25"
+ wire $0\clk2[0:0]
+ attribute \src "libresoc.v:606.3-620.6"
+ wire $0\clk3$next[0:0]$111
+ attribute \src "libresoc.v:557.3-558.25"
+ wire $0\clk3[0:0]
+ attribute \src "libresoc.v:565.3-573.6"
+ wire $0\clk4$next[0:0]$100
+ attribute \src "libresoc.v:563.3-564.25"
+ wire $0\clk4[0:0]
+ attribute \src "libresoc.v:641.3-663.6"
+ wire $0\core_clk_o[0:0]
+ attribute \src "libresoc.v:589.3-605.6"
+ wire width 2 $0\counter3$next[1:0]$107
+ attribute \src "libresoc.v:559.3-560.33"
+ wire width 2 $0\counter3[1:0]
+ attribute \src "libresoc.v:485.7-485.20"
+ wire $0\initial[0:0]
+ attribute \src "libresoc.v:621.3-640.6"
+ wire $1\clk1$next[0:0]$116
+ attribute \src "libresoc.v:507.7-507.18"
+ wire $1\clk1[0:0]
+ attribute \src "libresoc.v:574.3-588.6"
+ wire $1\clk2$next[0:0]$104
+ attribute \src "libresoc.v:511.7-511.18"
+ wire $1\clk2[0:0]
+ attribute \src "libresoc.v:606.3-620.6"
+ wire $1\clk3$next[0:0]$112
+ attribute \src "libresoc.v:515.7-515.18"
+ wire $1\clk3[0:0]
+ attribute \src "libresoc.v:565.3-573.6"
+ wire $1\clk4$next[0:0]$101
+ attribute \src "libresoc.v:519.7-519.18"
+ wire $1\clk4[0:0]
+ attribute \src "libresoc.v:641.3-663.6"
+ wire $1\core_clk_o[0:0]
+ attribute \src "libresoc.v:589.3-605.6"
+ wire width 2 $1\counter3$next[1:0]$108
+ attribute \src "libresoc.v:536.13-536.28"
+ wire width 2 $1\counter3[1:0]
+ attribute \src "libresoc.v:621.3-640.6"
+ wire $2\clk1$next[0:0]$117
+ attribute \src "libresoc.v:574.3-588.6"
+ wire $2\clk2$next[0:0]$105
+ attribute \src "libresoc.v:606.3-620.6"
+ wire $2\clk3$next[0:0]$113
+ attribute \src "libresoc.v:589.3-605.6"
+ wire width 2 $2\counter3$next[1:0]$109
+ attribute \src "libresoc.v:621.3-640.6"
+ wire $3\clk1$next[0:0]$118
+ attribute \src "libresoc.v:554.17-554.101"
+ wire width 3 $add$libresoc.v:554$93_Y
+ attribute \src "libresoc.v:547.18-547.103"
+ wire $eq$libresoc.v:547$86_Y
+ attribute \src "libresoc.v:549.18-549.103"
+ wire $eq$libresoc.v:549$88_Y
+ attribute \src "libresoc.v:553.17-553.102"
+ wire $eq$libresoc.v:553$92_Y
+ attribute \src "libresoc.v:548.18-548.93"
+ wire $not$libresoc.v:548$87_Y
+ attribute \src "libresoc.v:550.18-550.93"
+ wire $not$libresoc.v:550$89_Y
+ attribute \src "libresoc.v:551.17-551.92"
+ wire $not$libresoc.v:551$90_Y
+ attribute \src "libresoc.v:552.17-552.92"
+ wire $not$libresoc.v:552$91_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:55"
+ wire \$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58"
+ wire \$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:60"
+ wire \$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58"
+ wire \$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:62"
+ wire \$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:57"
+ wire \$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58"
+ wire \$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:64"
+ wire width 3 \$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:64"
+ wire width 3 \$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46"
+ wire \clk0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46"
+ wire \clk1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46"
+ wire \clk1$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46"
+ wire \clk2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46"
+ wire \clk2$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46"
+ wire \clk3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46"
+ wire \clk3$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46"
+ wire \clk4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46"
+ wire \clk4$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46"
+ wire \clk5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46"
+ wire \clk6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46"
+ wire \clk7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:34"
+ wire input 2 \clk_24_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:36"
+ wire width 3 input 4 \clk_sel_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:37"
+ wire output 6 \core_clk_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:47"
+ wire width 2 \counter3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:47"
+ wire width 2 \counter3$next
+ attribute \src "libresoc.v:485.7-485.15"
+ wire \initial
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:35"
+ wire output 5 \pll_48_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458"
+ wire input 1 \pllclk_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458"
+ wire \pllclk_rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:38"
+ wire input 3 \rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:64"
+ cell $add $add$libresoc.v:554$93
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 3
+ connect \A \counter3
+ connect \B 1'1
+ connect \Y $add$libresoc.v:554$93_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58"
+ cell $eq $eq$libresoc.v:547$86
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A \counter3
+ connect \B 2'10
+ connect \Y $eq$libresoc.v:547$86_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58"
+ cell $eq $eq$libresoc.v:549$88
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A \counter3
+ connect \B 2'10
+ connect \Y $eq$libresoc.v:549$88_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58"
+ cell $eq $eq$libresoc.v:553$92
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A \counter3
+ connect \B 2'10
+ connect \Y $eq$libresoc.v:553$92_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:60"
+ cell $not $not$libresoc.v:548$87
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \clk3
+ connect \Y $not$libresoc.v:548$87_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:62"
+ cell $not $not$libresoc.v:550$89
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \clk1
+ connect \Y $not$libresoc.v:550$89_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:55"
+ cell $not $not$libresoc.v:551$90
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \clk4
+ connect \Y $not$libresoc.v:551$90_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:57"
+ cell $not $not$libresoc.v:552$91
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \clk2
+ connect \Y $not$libresoc.v:552$91_Y
+ end
+ attribute \src "libresoc.v:485.7-485.20"
+ process $proc$libresoc.v:485$120
+ assign { } { }
+ assign $0\initial[0:0] 1'0
+ sync always
+ update \initial $0\initial[0:0]
+ sync init
+ end
+ attribute \src "libresoc.v:507.7-507.18"
+ process $proc$libresoc.v:507$121
+ assign { } { }
+ assign $1\clk1[0:0] 1'0
+ sync always
+ sync init
+ update \clk1 $1\clk1[0:0]
+ end
+ attribute \src "libresoc.v:511.7-511.18"
+ process $proc$libresoc.v:511$122
+ assign { } { }
+ assign $1\clk2[0:0] 1'0
+ sync always
+ sync init
+ update \clk2 $1\clk2[0:0]
+ end
+ attribute \src "libresoc.v:515.7-515.18"
+ process $proc$libresoc.v:515$123
+ assign { } { }
+ assign $1\clk3[0:0] 1'0
+ sync always
+ sync init
+ update \clk3 $1\clk3[0:0]
+ end
+ attribute \src "libresoc.v:519.7-519.18"
+ process $proc$libresoc.v:519$124
+ assign { } { }
+ assign $1\clk4[0:0] 1'0
+ sync always
+ sync init
+ update \clk4 $1\clk4[0:0]
+ end
+ attribute \src "libresoc.v:536.13-536.28"
+ process $proc$libresoc.v:536$125
+ assign { } { }
+ assign $1\counter3[1:0] 2'00
+ sync always
+ sync init
+ update \counter3 $1\counter3[1:0]
+ end
+ attribute \src "libresoc.v:555.3-556.25"
+ process $proc$libresoc.v:555$94
+ assign { } { }
+ assign $0\clk1[0:0] \clk1$next
+ sync posedge \pllclk_clk
+ update \clk1 $0\clk1[0:0]
+ end
+ attribute \src "libresoc.v:557.3-558.25"
+ process $proc$libresoc.v:557$95
+ assign { } { }
+ assign $0\clk3[0:0] \clk3$next
+ sync posedge \pllclk_clk
+ update \clk3 $0\clk3[0:0]
+ end
+ attribute \src "libresoc.v:559.3-560.33"
+ process $proc$libresoc.v:559$96
+ assign { } { }
+ assign $0\counter3[1:0] \counter3$next
+ sync posedge \pllclk_clk
+ update \counter3 $0\counter3[1:0]
+ end
+ attribute \src "libresoc.v:561.3-562.25"
+ process $proc$libresoc.v:561$97
+ assign { } { }
+ assign $0\clk2[0:0] \clk2$next
+ sync posedge \pllclk_clk
+ update \clk2 $0\clk2[0:0]
+ end
+ attribute \src "libresoc.v:563.3-564.25"
+ process $proc$libresoc.v:563$98
+ assign { } { }
+ assign $0\clk4[0:0] \clk4$next
+ sync posedge \pllclk_clk
+ update \clk4 $0\clk4[0:0]
+ end
+ attribute \src "libresoc.v:565.3-573.6"
+ process $proc$libresoc.v:565$99
+ assign { } { }
+ assign { } { }
+ assign $0\clk4$next[0:0]$100 $1\clk4$next[0:0]$101
+ attribute \src "libresoc.v:566.5-566.29"
+ switch \initial
+ attribute \src "libresoc.v:566.9-566.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \pllclk_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\clk4$next[0:0]$101 1'0
+ case
+ assign $1\clk4$next[0:0]$101 \$1
+ end
+ sync always
+ update \clk4$next $0\clk4$next[0:0]$100
+ end
+ attribute \src "libresoc.v:574.3-588.6"
+ process $proc$libresoc.v:574$102
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $0\clk2$next[0:0]$103 $2\clk2$next[0:0]$105
+ attribute \src "libresoc.v:575.5-575.29"
+ switch \initial
+ attribute \src "libresoc.v:575.9-575.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56"
+ switch \clk4
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\clk2$next[0:0]$104 \$3
+ case
+ assign $1\clk2$next[0:0]$104 \clk2
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \pllclk_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $2\clk2$next[0:0]$105 1'0
+ case
+ assign $2\clk2$next[0:0]$105 $1\clk2$next[0:0]$104
+ end
+ sync always
+ update \clk2$next $0\clk2$next[0:0]$103
+ end
+ attribute \src "libresoc.v:589.3-605.6"
+ process $proc$libresoc.v:589$106
+ assign { } { }
+ assign { } { }
+ assign $0\counter3$next[1:0]$107 $2\counter3$next[1:0]$109
+ attribute \src "libresoc.v:590.5-590.29"
+ switch \initial
+ attribute \src "libresoc.v:590.9-590.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58"
+ switch \$5
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\counter3$next[1:0]$108 2'00
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $1\counter3$next[1:0]$108 \$7 [1:0]
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \pllclk_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $2\counter3$next[1:0]$109 2'00
+ case
+ assign $2\counter3$next[1:0]$109 $1\counter3$next[1:0]$108
+ end
+ sync always
+ update \counter3$next $0\counter3$next[1:0]$107
+ end
+ attribute \src "libresoc.v:606.3-620.6"
+ process $proc$libresoc.v:606$110
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $0\clk3$next[0:0]$111 $2\clk3$next[0:0]$113
+ attribute \src "libresoc.v:607.5-607.29"
+ switch \initial
+ attribute \src "libresoc.v:607.9-607.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58"
+ switch \$10
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\clk3$next[0:0]$112 \$12
+ case
+ assign $1\clk3$next[0:0]$112 \clk3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \pllclk_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $2\clk3$next[0:0]$113 1'0
+ case
+ assign $2\clk3$next[0:0]$113 $1\clk3$next[0:0]$112
+ end
+ sync always
+ update \clk3$next $0\clk3$next[0:0]$111
+ end
+ attribute \src "libresoc.v:621.3-640.6"
+ process $proc$libresoc.v:621$114
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $0\clk1$next[0:0]$115 $3\clk1$next[0:0]$118
+ attribute \src "libresoc.v:622.5-622.29"
+ switch \initial
+ attribute \src "libresoc.v:622.9-622.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58"
+ switch \$14
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\clk1$next[0:0]$116 $2\clk1$next[0:0]$117
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:61"
+ switch \clk3
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $2\clk1$next[0:0]$117 \$16
+ case
+ assign $2\clk1$next[0:0]$117 \clk1
+ end
+ case
+ assign $1\clk1$next[0:0]$116 \clk1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \pllclk_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $3\clk1$next[0:0]$118 1'0
+ case
+ assign $3\clk1$next[0:0]$118 $1\clk1$next[0:0]$116
+ end
+ sync always
+ update \clk1$next $0\clk1$next[0:0]$115
+ end
+ attribute \src "libresoc.v:641.3-663.6"
+ process $proc$libresoc.v:641$119
+ assign { } { }
+ assign { } { }
+ assign $0\core_clk_o[0:0] $1\core_clk_o[0:0]
+ attribute \src "libresoc.v:642.5-642.29"
+ switch \initial
+ attribute \src "libresoc.v:642.9-642.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:67"
+ switch \clk_sel_i
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'000
+ assign { } { }
+ assign $1\core_clk_o[0:0] \clk0
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'001
+ assign { } { }
+ assign $1\core_clk_o[0:0] \clk1
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'010
+ assign { } { }
+ assign $1\core_clk_o[0:0] \clk2
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'011
+ assign { } { }
+ assign $1\core_clk_o[0:0] \clk3
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'100
+ assign { } { }
+ assign $1\core_clk_o[0:0] \clk4
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'101
+ assign { } { }
+ assign $1\core_clk_o[0:0] \clk5
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'110
+ assign { } { }
+ assign $1\core_clk_o[0:0] \clk6
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'---
+ assign { } { }
+ assign $1\core_clk_o[0:0] \clk7
+ case
+ assign $1\core_clk_o[0:0] 1'0
+ end
+ sync always
+ update \core_clk_o $0\core_clk_o[0:0]
+ end
+ connect \$10 $eq$libresoc.v:547$86_Y
+ connect \$12 $not$libresoc.v:548$87_Y
+ connect \$14 $eq$libresoc.v:549$88_Y
+ connect \$16 $not$libresoc.v:550$89_Y
+ connect \$1 $not$libresoc.v:551$90_Y
+ connect \$3 $not$libresoc.v:552$91_Y
+ connect \$5 $eq$libresoc.v:553$92_Y
+ connect \$8 $add$libresoc.v:554$93_Y
+ connect \$7 \$8
+ connect \clk5 1'0
+ connect \pll_48_o \clk1
+ connect \clk7 1'1
+ connect \clk6 1'0
+ connect \clk0 \clk_24_i
+ connect \pllclk_rst \rst
+end
+attribute \src "libresoc.v:675.1-1389.10"
+attribute \cells_not_processed 1
+attribute \nmigen.hierarchy "test_issuer.ti.dbg"
attribute \generator "nMigen"
module \dbg
- attribute \src "libresoc.v:1014.3-1023.6"
+ attribute \src "libresoc.v:1205.3-1214.6"
wire $0\d_cr_req[0:0]
- attribute \src "libresoc.v:821.3-830.6"
+ attribute \src "libresoc.v:1012.3-1021.6"
wire $0\d_gpr_req[0:0]
- attribute \src "libresoc.v:1024.3-1033.6"
+ attribute \src "libresoc.v:1215.3-1224.6"
wire $0\d_xer_req[0:0]
- attribute \src "libresoc.v:803.3-820.6"
+ attribute \src "libresoc.v:994.3-1011.6"
wire $0\dmi_ack_o[0:0]
- attribute \src "libresoc.v:1034.3-1064.6"
+ attribute \src "libresoc.v:1225.3-1255.6"
wire width 64 $0\dmi_dout[63:0]
- attribute \src "libresoc.v:1005.3-1013.6"
- wire $0\dmi_read_log_data$next[0:0]$199
- attribute \src "libresoc.v:781.3-782.51"
+ attribute \src "libresoc.v:1196.3-1204.6"
+ wire $0\dmi_read_log_data$next[0:0]$239
+ attribute \src "libresoc.v:972.3-973.51"
wire $0\dmi_read_log_data[0:0]
- attribute \src "libresoc.v:996.3-1004.6"
- wire $0\dmi_read_log_data_1$next[0:0]$196
- attribute \src "libresoc.v:783.3-784.55"
+ attribute \src "libresoc.v:1187.3-1195.6"
+ wire $0\dmi_read_log_data_1$next[0:0]$236
+ attribute \src "libresoc.v:974.3-975.55"
wire $0\dmi_read_log_data_1[0:0]
- attribute \src "libresoc.v:831.3-839.6"
- wire $0\dmi_req_i_1$next[0:0]$162
- attribute \src "libresoc.v:793.3-794.39"
+ attribute \src "libresoc.v:1022.3-1030.6"
+ wire $0\dmi_req_i_1$next[0:0]$202
+ attribute \src "libresoc.v:984.3-985.39"
wire $0\dmi_req_i_1[0:0]
- attribute \src "libresoc.v:1155.3-1188.6"
- wire $0\do_dmi_log_rd$next[0:0]$226
- attribute \src "libresoc.v:795.3-796.43"
+ attribute \src "libresoc.v:1346.3-1379.6"
+ wire $0\do_dmi_log_rd$next[0:0]$266
+ attribute \src "libresoc.v:986.3-987.43"
wire $0\do_dmi_log_rd[0:0]
- attribute \src "libresoc.v:1125.3-1154.6"
- wire $0\do_icreset$next[0:0]$219
- attribute \src "libresoc.v:797.3-798.37"
+ attribute \src "libresoc.v:1316.3-1345.6"
+ wire $0\do_icreset$next[0:0]$259
+ attribute \src "libresoc.v:988.3-989.37"
wire $0\do_icreset[0:0]
- attribute \src "libresoc.v:1095.3-1124.6"
- wire $0\do_reset$next[0:0]$212
- attribute \src "libresoc.v:799.3-800.33"
+ attribute \src "libresoc.v:1286.3-1315.6"
+ wire $0\do_reset$next[0:0]$252
+ attribute \src "libresoc.v:990.3-991.33"
wire $0\do_reset[0:0]
- attribute \src "libresoc.v:1065.3-1094.6"
- wire $0\do_step$next[0:0]$205
- attribute \src "libresoc.v:801.3-802.31"
+ attribute \src "libresoc.v:1256.3-1285.6"
+ wire $0\do_step$next[0:0]$245
+ attribute \src "libresoc.v:992.3-993.31"
wire $0\do_step[0:0]
- attribute \src "libresoc.v:934.3-961.6"
- wire width 7 $0\gspr_index$next[6:0]$184
- attribute \src "libresoc.v:787.3-788.37"
+ attribute \src "libresoc.v:1125.3-1152.6"
+ wire width 7 $0\gspr_index$next[6:0]$224
+ attribute \src "libresoc.v:978.3-979.37"
wire width 7 $0\gspr_index[6:0]
- attribute \src "libresoc.v:485.7-485.20"
+ attribute \src "libresoc.v:676.7-676.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:962.3-995.6"
- wire width 32 $0\log_dmi_addr$next[31:0]$190
- attribute \src "libresoc.v:785.3-786.41"
+ attribute \src "libresoc.v:1153.3-1186.6"
+ wire width 32 $0\log_dmi_addr$next[31:0]$230
+ attribute \src "libresoc.v:976.3-977.41"
wire width 32 $0\log_dmi_addr[31:0]
- attribute \src "libresoc.v:890.3-933.6"
- wire $0\stopping$next[0:0]$175
- attribute \src "libresoc.v:789.3-790.33"
+ attribute \src "libresoc.v:1081.3-1124.6"
+ wire $0\stopping$next[0:0]$215
+ attribute \src "libresoc.v:980.3-981.33"
wire $0\stopping[0:0]
- attribute \src "libresoc.v:840.3-889.6"
- wire $0\terminated$next[0:0]$165
- attribute \src "libresoc.v:791.3-792.37"
+ attribute \src "libresoc.v:1031.3-1080.6"
+ wire $0\terminated$next[0:0]$205
+ attribute \src "libresoc.v:982.3-983.37"
wire $0\terminated[0:0]
- attribute \src "libresoc.v:1014.3-1023.6"
+ attribute \src "libresoc.v:1205.3-1214.6"
wire $1\d_cr_req[0:0]
- attribute \src "libresoc.v:821.3-830.6"
+ attribute \src "libresoc.v:1012.3-1021.6"
wire $1\d_gpr_req[0:0]
- attribute \src "libresoc.v:1024.3-1033.6"
+ attribute \src "libresoc.v:1215.3-1224.6"
wire $1\d_xer_req[0:0]
- attribute \src "libresoc.v:803.3-820.6"
+ attribute \src "libresoc.v:994.3-1011.6"
wire $1\dmi_ack_o[0:0]
- attribute \src "libresoc.v:1034.3-1064.6"
+ attribute \src "libresoc.v:1225.3-1255.6"
wire width 64 $1\dmi_dout[63:0]
- attribute \src "libresoc.v:1005.3-1013.6"
- wire $1\dmi_read_log_data$next[0:0]$200
- attribute \src "libresoc.v:658.7-658.31"
+ attribute \src "libresoc.v:1196.3-1204.6"
+ wire $1\dmi_read_log_data$next[0:0]$240
+ attribute \src "libresoc.v:847.7-847.31"
wire $1\dmi_read_log_data[0:0]
- attribute \src "libresoc.v:996.3-1004.6"
- wire $1\dmi_read_log_data_1$next[0:0]$197
- attribute \src "libresoc.v:662.7-662.33"
+ attribute \src "libresoc.v:1187.3-1195.6"
+ wire $1\dmi_read_log_data_1$next[0:0]$237
+ attribute \src "libresoc.v:851.7-851.33"
wire $1\dmi_read_log_data_1[0:0]
- attribute \src "libresoc.v:831.3-839.6"
- wire $1\dmi_req_i_1$next[0:0]$163
- attribute \src "libresoc.v:668.7-668.25"
+ attribute \src "libresoc.v:1022.3-1030.6"
+ wire $1\dmi_req_i_1$next[0:0]$203
+ attribute \src "libresoc.v:857.7-857.25"
wire $1\dmi_req_i_1[0:0]
- attribute \src "libresoc.v:1155.3-1188.6"
- wire $1\do_dmi_log_rd$next[0:0]$227
- attribute \src "libresoc.v:674.7-674.27"
+ attribute \src "libresoc.v:1346.3-1379.6"
+ wire $1\do_dmi_log_rd$next[0:0]$267
+ attribute \src "libresoc.v:863.7-863.27"
wire $1\do_dmi_log_rd[0:0]
- attribute \src "libresoc.v:1125.3-1154.6"
- wire $1\do_icreset$next[0:0]$220
- attribute \src "libresoc.v:678.7-678.24"
+ attribute \src "libresoc.v:1316.3-1345.6"
+ wire $1\do_icreset$next[0:0]$260
+ attribute \src "libresoc.v:867.7-867.24"
wire $1\do_icreset[0:0]
- attribute \src "libresoc.v:1095.3-1124.6"
- wire $1\do_reset$next[0:0]$213
- attribute \src "libresoc.v:682.7-682.22"
+ attribute \src "libresoc.v:1286.3-1315.6"
+ wire $1\do_reset$next[0:0]$253
+ attribute \src "libresoc.v:871.7-871.22"
wire $1\do_reset[0:0]
- attribute \src "libresoc.v:1065.3-1094.6"
- wire $1\do_step$next[0:0]$206
- attribute \src "libresoc.v:686.7-686.21"
+ attribute \src "libresoc.v:1256.3-1285.6"
+ wire $1\do_step$next[0:0]$246
+ attribute \src "libresoc.v:875.7-875.21"
wire $1\do_step[0:0]
- attribute \src "libresoc.v:934.3-961.6"
- wire width 7 $1\gspr_index$next[6:0]$185
- attribute \src "libresoc.v:690.13-690.31"
+ attribute \src "libresoc.v:1125.3-1152.6"
+ wire width 7 $1\gspr_index$next[6:0]$225
+ attribute \src "libresoc.v:879.13-879.31"
wire width 7 $1\gspr_index[6:0]
- attribute \src "libresoc.v:962.3-995.6"
- wire width 32 $1\log_dmi_addr$next[31:0]$191
- attribute \src "libresoc.v:696.14-696.34"
+ attribute \src "libresoc.v:1153.3-1186.6"
+ wire width 32 $1\log_dmi_addr$next[31:0]$231
+ attribute \src "libresoc.v:889.14-889.34"
wire width 32 $1\log_dmi_addr[31:0]
- attribute \src "libresoc.v:890.3-933.6"
- wire $1\stopping$next[0:0]$176
- attribute \src "libresoc.v:708.7-708.22"
+ attribute \src "libresoc.v:1081.3-1124.6"
+ wire $1\stopping$next[0:0]$216
+ attribute \src "libresoc.v:899.7-899.22"
wire $1\stopping[0:0]
- attribute \src "libresoc.v:840.3-889.6"
- wire $1\terminated$next[0:0]$166
- attribute \src "libresoc.v:714.7-714.24"
+ attribute \src "libresoc.v:1031.3-1080.6"
+ wire $1\terminated$next[0:0]$206
+ attribute \src "libresoc.v:905.7-905.24"
wire $1\terminated[0:0]
- attribute \src "libresoc.v:1155.3-1188.6"
- wire $2\do_dmi_log_rd$next[0:0]$228
- attribute \src "libresoc.v:1125.3-1154.6"
- wire $2\do_icreset$next[0:0]$221
- attribute \src "libresoc.v:1095.3-1124.6"
- wire $2\do_reset$next[0:0]$214
- attribute \src "libresoc.v:1065.3-1094.6"
- wire $2\do_step$next[0:0]$207
- attribute \src "libresoc.v:934.3-961.6"
- wire width 7 $2\gspr_index$next[6:0]$186
- attribute \src "libresoc.v:962.3-995.6"
- wire width 32 $2\log_dmi_addr$next[31:0]$192
- attribute \src "libresoc.v:890.3-933.6"
- wire $2\stopping$next[0:0]$177
- attribute \src "libresoc.v:840.3-889.6"
- wire $2\terminated$next[0:0]$167
- attribute \src "libresoc.v:1155.3-1188.6"
- wire $3\do_dmi_log_rd$next[0:0]$229
- attribute \src "libresoc.v:1125.3-1154.6"
- wire $3\do_icreset$next[0:0]$222
- attribute \src "libresoc.v:1095.3-1124.6"
- wire $3\do_reset$next[0:0]$215
- attribute \src "libresoc.v:1065.3-1094.6"
- wire $3\do_step$next[0:0]$208
- attribute \src "libresoc.v:934.3-961.6"
- wire width 7 $3\gspr_index$next[6:0]$187
- attribute \src "libresoc.v:962.3-995.6"
- wire width 32 $3\log_dmi_addr$next[31:0]$193
- attribute \src "libresoc.v:890.3-933.6"
- wire $3\stopping$next[0:0]$178
- attribute \src "libresoc.v:840.3-889.6"
- wire $3\terminated$next[0:0]$168
- attribute \src "libresoc.v:1155.3-1188.6"
- wire $4\do_dmi_log_rd$next[0:0]$230
- attribute \src "libresoc.v:1125.3-1154.6"
- wire $4\do_icreset$next[0:0]$223
- attribute \src "libresoc.v:1095.3-1124.6"
- wire $4\do_reset$next[0:0]$216
- attribute \src "libresoc.v:1065.3-1094.6"
- wire $4\do_step$next[0:0]$209
- attribute \src "libresoc.v:934.3-961.6"
- wire width 7 $4\gspr_index$next[6:0]$188
- attribute \src "libresoc.v:962.3-995.6"
- wire width 32 $4\log_dmi_addr$next[31:0]$194
- attribute \src "libresoc.v:890.3-933.6"
- wire $4\stopping$next[0:0]$179
- attribute \src "libresoc.v:840.3-889.6"
- wire $4\terminated$next[0:0]$169
- attribute \src "libresoc.v:1125.3-1154.6"
- wire $5\do_icreset$next[0:0]$224
- attribute \src "libresoc.v:1095.3-1124.6"
- wire $5\do_reset$next[0:0]$217
- attribute \src "libresoc.v:1065.3-1094.6"
- wire $5\do_step$next[0:0]$210
- attribute \src "libresoc.v:890.3-933.6"
- wire $5\stopping$next[0:0]$180
- attribute \src "libresoc.v:840.3-889.6"
- wire $5\terminated$next[0:0]$170
- attribute \src "libresoc.v:890.3-933.6"
- wire $6\stopping$next[0:0]$181
- attribute \src "libresoc.v:840.3-889.6"
- wire $6\terminated$next[0:0]$171
- attribute \src "libresoc.v:890.3-933.6"
- wire $7\stopping$next[0:0]$182
- attribute \src "libresoc.v:840.3-889.6"
- wire $7\terminated$next[0:0]$172
- attribute \src "libresoc.v:840.3-889.6"
- wire $8\terminated$next[0:0]$173
- attribute \src "libresoc.v:728.19-728.110"
- wire width 3 $add$libresoc.v:728$95_Y
- attribute \src "libresoc.v:719.17-719.109"
- wire $and$libresoc.v:719$86_Y
- attribute \src "libresoc.v:722.19-722.103"
- wire $and$libresoc.v:722$89_Y
- attribute \src "libresoc.v:724.19-724.113"
- wire $and$libresoc.v:724$91_Y
- attribute \src "libresoc.v:731.19-731.103"
- wire $and$libresoc.v:731$98_Y
- attribute \src "libresoc.v:733.19-733.102"
- wire $and$libresoc.v:733$100_Y
- attribute \src "libresoc.v:738.18-738.101"
- wire $and$libresoc.v:738$105_Y
- attribute \src "libresoc.v:740.18-740.111"
- wire $and$libresoc.v:740$107_Y
- attribute \src "libresoc.v:745.18-745.101"
- wire $and$libresoc.v:745$112_Y
- attribute \src "libresoc.v:747.18-747.111"
- wire $and$libresoc.v:747$114_Y
- attribute \src "libresoc.v:753.18-753.101"
- wire $and$libresoc.v:753$120_Y
- attribute \src "libresoc.v:755.18-755.111"
- wire $and$libresoc.v:755$122_Y
- attribute \src "libresoc.v:759.17-759.99"
- wire $and$libresoc.v:759$126_Y
- attribute \src "libresoc.v:761.18-761.101"
- wire $and$libresoc.v:761$128_Y
- attribute \src "libresoc.v:763.18-763.111"
- wire $and$libresoc.v:763$130_Y
- attribute \src "libresoc.v:768.18-768.101"
- wire $and$libresoc.v:768$135_Y
- attribute \src "libresoc.v:771.18-771.111"
- wire $and$libresoc.v:771$138_Y
- attribute \src "libresoc.v:776.18-776.101"
- wire $and$libresoc.v:776$143_Y
- attribute \src "libresoc.v:778.18-778.111"
- wire $and$libresoc.v:778$145_Y
- attribute \src "libresoc.v:720.18-720.103"
- wire $eq$libresoc.v:720$87_Y
- attribute \src "libresoc.v:725.19-725.104"
- wire $eq$libresoc.v:725$92_Y
- attribute \src "libresoc.v:726.19-726.104"
- wire $eq$libresoc.v:726$93_Y
- attribute \src "libresoc.v:727.19-727.104"
- wire $eq$libresoc.v:727$94_Y
- attribute \src "libresoc.v:729.19-729.104"
- wire $eq$libresoc.v:729$96_Y
- attribute \src "libresoc.v:730.18-730.103"
- wire $eq$libresoc.v:730$97_Y
- attribute \src "libresoc.v:734.18-734.103"
- wire $eq$libresoc.v:734$101_Y
- attribute \src "libresoc.v:735.18-735.103"
- wire $eq$libresoc.v:735$102_Y
- attribute \src "libresoc.v:741.18-741.103"
- wire $eq$libresoc.v:741$108_Y
- attribute \src "libresoc.v:742.18-742.103"
- wire $eq$libresoc.v:742$109_Y
- attribute \src "libresoc.v:743.18-743.103"
- wire $eq$libresoc.v:743$110_Y
- attribute \src "libresoc.v:749.18-749.103"
- wire $eq$libresoc.v:749$116_Y
- attribute \src "libresoc.v:750.18-750.103"
- wire $eq$libresoc.v:750$117_Y
- attribute \src "libresoc.v:751.18-751.103"
- wire $eq$libresoc.v:751$118_Y
- attribute \src "libresoc.v:756.18-756.103"
- wire $eq$libresoc.v:756$123_Y
- attribute \src "libresoc.v:757.18-757.103"
- wire $eq$libresoc.v:757$124_Y
- attribute \src "libresoc.v:758.18-758.103"
- wire $eq$libresoc.v:758$125_Y
- attribute \src "libresoc.v:764.18-764.103"
- wire $eq$libresoc.v:764$131_Y
- attribute \src "libresoc.v:765.18-765.103"
- wire $eq$libresoc.v:765$132_Y
- attribute \src "libresoc.v:766.18-766.103"
- wire $eq$libresoc.v:766$133_Y
- attribute \src "libresoc.v:772.18-772.103"
- wire $eq$libresoc.v:772$139_Y
- attribute \src "libresoc.v:773.18-773.103"
- wire $eq$libresoc.v:773$140_Y
- attribute \src "libresoc.v:774.18-774.103"
- wire $eq$libresoc.v:774$141_Y
- attribute \src "libresoc.v:779.18-779.103"
- wire $eq$libresoc.v:779$146_Y
- attribute \src "libresoc.v:780.18-780.103"
- wire $eq$libresoc.v:780$147_Y
- attribute \src "libresoc.v:721.19-721.99"
- wire $not$libresoc.v:721$88_Y
- attribute \src "libresoc.v:723.19-723.105"
- wire $not$libresoc.v:723$90_Y
- attribute \src "libresoc.v:732.19-732.95"
- wire $not$libresoc.v:732$99_Y
- attribute \src "libresoc.v:736.18-736.98"
- wire $not$libresoc.v:736$103_Y
- attribute \src "libresoc.v:739.18-739.104"
- wire $not$libresoc.v:739$106_Y
- attribute \src "libresoc.v:744.18-744.98"
- wire $not$libresoc.v:744$111_Y
- attribute \src "libresoc.v:746.18-746.104"
- wire $not$libresoc.v:746$113_Y
- attribute \src "libresoc.v:748.17-748.97"
- wire $not$libresoc.v:748$115_Y
- attribute \src "libresoc.v:752.18-752.98"
- wire $not$libresoc.v:752$119_Y
- attribute \src "libresoc.v:754.18-754.104"
- wire $not$libresoc.v:754$121_Y
- attribute \src "libresoc.v:760.18-760.98"
- wire $not$libresoc.v:760$127_Y
- attribute \src "libresoc.v:762.18-762.104"
- wire $not$libresoc.v:762$129_Y
- attribute \src "libresoc.v:767.18-767.98"
- wire $not$libresoc.v:767$134_Y
- attribute \src "libresoc.v:769.18-769.104"
- wire $not$libresoc.v:769$136_Y
- attribute \src "libresoc.v:770.17-770.103"
- wire $not$libresoc.v:770$137_Y
- attribute \src "libresoc.v:775.18-775.98"
- wire $not$libresoc.v:775$142_Y
- attribute \src "libresoc.v:777.18-777.104"
- wire $not$libresoc.v:777$144_Y
- attribute \src "libresoc.v:737.17-737.126"
- wire width 64 $pos$libresoc.v:737$104_Y
+ attribute \src "libresoc.v:1346.3-1379.6"
+ wire $2\do_dmi_log_rd$next[0:0]$268
+ attribute \src "libresoc.v:1316.3-1345.6"
+ wire $2\do_icreset$next[0:0]$261
+ attribute \src "libresoc.v:1286.3-1315.6"
+ wire $2\do_reset$next[0:0]$254
+ attribute \src "libresoc.v:1256.3-1285.6"
+ wire $2\do_step$next[0:0]$247
+ attribute \src "libresoc.v:1125.3-1152.6"
+ wire width 7 $2\gspr_index$next[6:0]$226
+ attribute \src "libresoc.v:1153.3-1186.6"
+ wire width 32 $2\log_dmi_addr$next[31:0]$232
+ attribute \src "libresoc.v:1081.3-1124.6"
+ wire $2\stopping$next[0:0]$217
+ attribute \src "libresoc.v:1031.3-1080.6"
+ wire $2\terminated$next[0:0]$207
+ attribute \src "libresoc.v:1346.3-1379.6"
+ wire $3\do_dmi_log_rd$next[0:0]$269
+ attribute \src "libresoc.v:1316.3-1345.6"
+ wire $3\do_icreset$next[0:0]$262
+ attribute \src "libresoc.v:1286.3-1315.6"
+ wire $3\do_reset$next[0:0]$255
+ attribute \src "libresoc.v:1256.3-1285.6"
+ wire $3\do_step$next[0:0]$248
+ attribute \src "libresoc.v:1125.3-1152.6"
+ wire width 7 $3\gspr_index$next[6:0]$227
+ attribute \src "libresoc.v:1153.3-1186.6"
+ wire width 32 $3\log_dmi_addr$next[31:0]$233
+ attribute \src "libresoc.v:1081.3-1124.6"
+ wire $3\stopping$next[0:0]$218
+ attribute \src "libresoc.v:1031.3-1080.6"
+ wire $3\terminated$next[0:0]$208
+ attribute \src "libresoc.v:1346.3-1379.6"
+ wire $4\do_dmi_log_rd$next[0:0]$270
+ attribute \src "libresoc.v:1316.3-1345.6"
+ wire $4\do_icreset$next[0:0]$263
+ attribute \src "libresoc.v:1286.3-1315.6"
+ wire $4\do_reset$next[0:0]$256
+ attribute \src "libresoc.v:1256.3-1285.6"
+ wire $4\do_step$next[0:0]$249
+ attribute \src "libresoc.v:1125.3-1152.6"
+ wire width 7 $4\gspr_index$next[6:0]$228
+ attribute \src "libresoc.v:1153.3-1186.6"
+ wire width 32 $4\log_dmi_addr$next[31:0]$234
+ attribute \src "libresoc.v:1081.3-1124.6"
+ wire $4\stopping$next[0:0]$219
+ attribute \src "libresoc.v:1031.3-1080.6"
+ wire $4\terminated$next[0:0]$209
+ attribute \src "libresoc.v:1316.3-1345.6"
+ wire $5\do_icreset$next[0:0]$264
+ attribute \src "libresoc.v:1286.3-1315.6"
+ wire $5\do_reset$next[0:0]$257
+ attribute \src "libresoc.v:1256.3-1285.6"
+ wire $5\do_step$next[0:0]$250
+ attribute \src "libresoc.v:1081.3-1124.6"
+ wire $5\stopping$next[0:0]$220
+ attribute \src "libresoc.v:1031.3-1080.6"
+ wire $5\terminated$next[0:0]$210
+ attribute \src "libresoc.v:1081.3-1124.6"
+ wire $6\stopping$next[0:0]$221
+ attribute \src "libresoc.v:1031.3-1080.6"
+ wire $6\terminated$next[0:0]$211
+ attribute \src "libresoc.v:1081.3-1124.6"
+ wire $7\stopping$next[0:0]$222
+ attribute \src "libresoc.v:1031.3-1080.6"
+ wire $7\terminated$next[0:0]$212
+ attribute \src "libresoc.v:1031.3-1080.6"
+ wire $8\terminated$next[0:0]$213
+ attribute \src "libresoc.v:919.19-919.110"
+ wire width 3 $add$libresoc.v:919$135_Y
+ attribute \src "libresoc.v:910.17-910.109"
+ wire $and$libresoc.v:910$126_Y
+ attribute \src "libresoc.v:913.19-913.103"
+ wire $and$libresoc.v:913$129_Y
+ attribute \src "libresoc.v:915.19-915.113"
+ wire $and$libresoc.v:915$131_Y
+ attribute \src "libresoc.v:922.19-922.103"
+ wire $and$libresoc.v:922$138_Y
+ attribute \src "libresoc.v:924.19-924.102"
+ wire $and$libresoc.v:924$140_Y
+ attribute \src "libresoc.v:929.18-929.101"
+ wire $and$libresoc.v:929$145_Y
+ attribute \src "libresoc.v:931.18-931.111"
+ wire $and$libresoc.v:931$147_Y
+ attribute \src "libresoc.v:936.18-936.101"
+ wire $and$libresoc.v:936$152_Y
+ attribute \src "libresoc.v:938.18-938.111"
+ wire $and$libresoc.v:938$154_Y
+ attribute \src "libresoc.v:944.18-944.101"
+ wire $and$libresoc.v:944$160_Y
+ attribute \src "libresoc.v:946.18-946.111"
+ wire $and$libresoc.v:946$162_Y
+ attribute \src "libresoc.v:950.17-950.99"
+ wire $and$libresoc.v:950$166_Y
+ attribute \src "libresoc.v:952.18-952.101"
+ wire $and$libresoc.v:952$168_Y
+ attribute \src "libresoc.v:954.18-954.111"
+ wire $and$libresoc.v:954$170_Y
+ attribute \src "libresoc.v:959.18-959.101"
+ wire $and$libresoc.v:959$175_Y
+ attribute \src "libresoc.v:962.18-962.111"
+ wire $and$libresoc.v:962$178_Y
+ attribute \src "libresoc.v:967.18-967.101"
+ wire $and$libresoc.v:967$183_Y
+ attribute \src "libresoc.v:969.18-969.111"
+ wire $and$libresoc.v:969$185_Y
+ attribute \src "libresoc.v:911.18-911.103"
+ wire $eq$libresoc.v:911$127_Y
+ attribute \src "libresoc.v:916.19-916.104"
+ wire $eq$libresoc.v:916$132_Y
+ attribute \src "libresoc.v:917.19-917.104"
+ wire $eq$libresoc.v:917$133_Y
+ attribute \src "libresoc.v:918.19-918.104"
+ wire $eq$libresoc.v:918$134_Y
+ attribute \src "libresoc.v:920.19-920.104"
+ wire $eq$libresoc.v:920$136_Y
+ attribute \src "libresoc.v:921.18-921.103"
+ wire $eq$libresoc.v:921$137_Y
+ attribute \src "libresoc.v:925.18-925.103"
+ wire $eq$libresoc.v:925$141_Y
+ attribute \src "libresoc.v:926.18-926.103"
+ wire $eq$libresoc.v:926$142_Y
+ attribute \src "libresoc.v:932.18-932.103"
+ wire $eq$libresoc.v:932$148_Y
+ attribute \src "libresoc.v:933.18-933.103"
+ wire $eq$libresoc.v:933$149_Y
+ attribute \src "libresoc.v:934.18-934.103"
+ wire $eq$libresoc.v:934$150_Y
+ attribute \src "libresoc.v:940.18-940.103"
+ wire $eq$libresoc.v:940$156_Y
+ attribute \src "libresoc.v:941.18-941.103"
+ wire $eq$libresoc.v:941$157_Y
+ attribute \src "libresoc.v:942.18-942.103"
+ wire $eq$libresoc.v:942$158_Y
+ attribute \src "libresoc.v:947.18-947.103"
+ wire $eq$libresoc.v:947$163_Y
+ attribute \src "libresoc.v:948.18-948.103"
+ wire $eq$libresoc.v:948$164_Y
+ attribute \src "libresoc.v:949.18-949.103"
+ wire $eq$libresoc.v:949$165_Y
+ attribute \src "libresoc.v:955.18-955.103"
+ wire $eq$libresoc.v:955$171_Y
+ attribute \src "libresoc.v:956.18-956.103"
+ wire $eq$libresoc.v:956$172_Y
+ attribute \src "libresoc.v:957.18-957.103"
+ wire $eq$libresoc.v:957$173_Y
+ attribute \src "libresoc.v:963.18-963.103"
+ wire $eq$libresoc.v:963$179_Y
+ attribute \src "libresoc.v:964.18-964.103"
+ wire $eq$libresoc.v:964$180_Y
+ attribute \src "libresoc.v:965.18-965.103"
+ wire $eq$libresoc.v:965$181_Y
+ attribute \src "libresoc.v:970.18-970.103"
+ wire $eq$libresoc.v:970$186_Y
+ attribute \src "libresoc.v:971.18-971.103"
+ wire $eq$libresoc.v:971$187_Y
+ attribute \src "libresoc.v:912.19-912.99"
+ wire $not$libresoc.v:912$128_Y
+ attribute \src "libresoc.v:914.19-914.105"
+ wire $not$libresoc.v:914$130_Y
+ attribute \src "libresoc.v:923.19-923.95"
+ wire $not$libresoc.v:923$139_Y
+ attribute \src "libresoc.v:927.18-927.98"
+ wire $not$libresoc.v:927$143_Y
+ attribute \src "libresoc.v:930.18-930.104"
+ wire $not$libresoc.v:930$146_Y
+ attribute \src "libresoc.v:935.18-935.98"
+ wire $not$libresoc.v:935$151_Y
+ attribute \src "libresoc.v:937.18-937.104"
+ wire $not$libresoc.v:937$153_Y
+ attribute \src "libresoc.v:939.17-939.97"
+ wire $not$libresoc.v:939$155_Y
+ attribute \src "libresoc.v:943.18-943.98"
+ wire $not$libresoc.v:943$159_Y
+ attribute \src "libresoc.v:945.18-945.104"
+ wire $not$libresoc.v:945$161_Y
+ attribute \src "libresoc.v:951.18-951.98"
+ wire $not$libresoc.v:951$167_Y
+ attribute \src "libresoc.v:953.18-953.104"
+ wire $not$libresoc.v:953$169_Y
+ attribute \src "libresoc.v:958.18-958.98"
+ wire $not$libresoc.v:958$174_Y
+ attribute \src "libresoc.v:960.18-960.104"
+ wire $not$libresoc.v:960$176_Y
+ attribute \src "libresoc.v:961.17-961.103"
+ wire $not$libresoc.v:961$177_Y
+ attribute \src "libresoc.v:966.18-966.98"
+ wire $not$libresoc.v:966$182_Y
+ attribute \src "libresoc.v:968.18-968.104"
+ wire $not$libresoc.v:968$184_Y
+ attribute \src "libresoc.v:928.17-928.126"
+ wire width 64 $pos$libresoc.v:928$144_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170"
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
wire \$97
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
wire \$99
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151"
- wire input 6 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
wire width 64 input 10 \core_dbg_msr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
wire width 7 \gspr_index$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99"
wire \icache_rst_o
- attribute \src "libresoc.v:485.7-485.15"
+ attribute \src "libresoc.v:676.7-676.15"
wire \initial
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153"
+ wire input 6 \intclk_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153"
+ wire input 23 \intclk_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145"
wire width 32 \log_dmi_addr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145"
wire width 64 \log_dmi_data
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119"
wire width 32 \log_write_addr_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151"
- wire input 23 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134"
wire width 64 \stat_reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122"
wire \terminated_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
- cell $add $add$libresoc.v:728$95
+ cell $add $add$libresoc.v:919$135
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \log_dmi_addr [1:0]
connect \B 1'1
- connect \Y $add$libresoc.v:728$95_Y
+ connect \Y $add$libresoc.v:919$135_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:719$86
+ cell $and $and$libresoc.v:910$126
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$7
- connect \Y $and$libresoc.v:719$86_Y
+ connect \Y $and$libresoc.v:910$126_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:722$89
+ cell $and $and$libresoc.v:913$129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$101
- connect \Y $and$libresoc.v:722$89_Y
+ connect \Y $and$libresoc.v:913$129_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:724$91
+ cell $and $and$libresoc.v:915$131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$105
- connect \Y $and$libresoc.v:724$91_Y
+ connect \Y $and$libresoc.v:915$131_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242"
- cell $and $and$libresoc.v:731$98
+ cell $and $and$libresoc.v:922$138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$118
- connect \Y $and$libresoc.v:731$98_Y
+ connect \Y $and$libresoc.v:922$138_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254"
- cell $and $and$libresoc.v:733$100
+ cell $and $and$libresoc.v:924$140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \stopping
connect \B \$122
- connect \Y $and$libresoc.v:733$100_Y
+ connect \Y $and$libresoc.v:924$140_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:738$105
+ cell $and $and$libresoc.v:929$145
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$17
- connect \Y $and$libresoc.v:738$105_Y
+ connect \Y $and$libresoc.v:929$145_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:740$107
+ cell $and $and$libresoc.v:931$147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$21
- connect \Y $and$libresoc.v:740$107_Y
+ connect \Y $and$libresoc.v:931$147_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:745$112
+ cell $and $and$libresoc.v:936$152
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$31
- connect \Y $and$libresoc.v:745$112_Y
+ connect \Y $and$libresoc.v:936$152_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:747$114
+ cell $and $and$libresoc.v:938$154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$35
- connect \Y $and$libresoc.v:747$114_Y
+ connect \Y $and$libresoc.v:938$154_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:753$120
+ cell $and $and$libresoc.v:944$160
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$45
- connect \Y $and$libresoc.v:753$120_Y
+ connect \Y $and$libresoc.v:944$160_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:755$122
+ cell $and $and$libresoc.v:946$162
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$49
- connect \Y $and$libresoc.v:755$122_Y
+ connect \Y $and$libresoc.v:946$162_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:759$126
+ cell $and $and$libresoc.v:950$166
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$3
- connect \Y $and$libresoc.v:759$126_Y
+ connect \Y $and$libresoc.v:950$166_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:761$128
+ cell $and $and$libresoc.v:952$168
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$59
- connect \Y $and$libresoc.v:761$128_Y
+ connect \Y $and$libresoc.v:952$168_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:763$130
+ cell $and $and$libresoc.v:954$170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$63
- connect \Y $and$libresoc.v:763$130_Y
+ connect \Y $and$libresoc.v:954$170_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:768$135
+ cell $and $and$libresoc.v:959$175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$73
- connect \Y $and$libresoc.v:768$135_Y
+ connect \Y $and$libresoc.v:959$175_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:771$138
+ cell $and $and$libresoc.v:962$178
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$77
- connect \Y $and$libresoc.v:771$138_Y
+ connect \Y $and$libresoc.v:962$178_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $and $and$libresoc.v:776$143
+ cell $and $and$libresoc.v:967$183
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_req_i
connect \B \$87
- connect \Y $and$libresoc.v:776$143_Y
+ connect \Y $and$libresoc.v:967$183_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $and $and$libresoc.v:778$145
+ cell $and $and$libresoc.v:969$185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data_1
connect \B \$91
- connect \Y $and$libresoc.v:778$145_Y
+ connect \Y $and$libresoc.v:969$185_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:720$87
+ cell $eq $eq$libresoc.v:911$127
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:720$87_Y
+ connect \Y $eq$libresoc.v:911$127_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:725$92
+ cell $eq $eq$libresoc.v:916$132
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:725$92_Y
+ connect \Y $eq$libresoc.v:916$132_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:726$93
+ cell $eq $eq$libresoc.v:917$133
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:726$93_Y
+ connect \Y $eq$libresoc.v:917$133_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:727$94
+ cell $eq $eq$libresoc.v:918$134
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:727$94_Y
+ connect \Y $eq$libresoc.v:918$134_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242"
- cell $eq $eq$libresoc.v:729$96
+ cell $eq $eq$libresoc.v:920$136
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'111
- connect \Y $eq$libresoc.v:729$96_Y
+ connect \Y $eq$libresoc.v:920$136_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:730$97
+ cell $eq $eq$libresoc.v:921$137
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:730$97_Y
+ connect \Y $eq$libresoc.v:921$137_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:734$101
+ cell $eq $eq$libresoc.v:925$141
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:734$101_Y
+ connect \Y $eq$libresoc.v:925$141_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:735$102
+ cell $eq $eq$libresoc.v:926$142
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:735$102_Y
+ connect \Y $eq$libresoc.v:926$142_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:741$108
+ cell $eq $eq$libresoc.v:932$148
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:741$108_Y
+ connect \Y $eq$libresoc.v:932$148_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:742$109
+ cell $eq $eq$libresoc.v:933$149
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:742$109_Y
+ connect \Y $eq$libresoc.v:933$149_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:743$110
+ cell $eq $eq$libresoc.v:934$150
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:743$110_Y
+ connect \Y $eq$libresoc.v:934$150_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:749$116
+ cell $eq $eq$libresoc.v:940$156
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:749$116_Y
+ connect \Y $eq$libresoc.v:940$156_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:750$117
+ cell $eq $eq$libresoc.v:941$157
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:750$117_Y
+ connect \Y $eq$libresoc.v:941$157_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:751$118
+ cell $eq $eq$libresoc.v:942$158
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:751$118_Y
+ connect \Y $eq$libresoc.v:942$158_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:756$123
+ cell $eq $eq$libresoc.v:947$163
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:756$123_Y
+ connect \Y $eq$libresoc.v:947$163_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:757$124
+ cell $eq $eq$libresoc.v:948$164
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:757$124_Y
+ connect \Y $eq$libresoc.v:948$164_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:758$125
+ cell $eq $eq$libresoc.v:949$165
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:758$125_Y
+ connect \Y $eq$libresoc.v:949$165_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:764$131
+ cell $eq $eq$libresoc.v:955$171
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:764$131_Y
+ connect \Y $eq$libresoc.v:955$171_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:765$132
+ cell $eq $eq$libresoc.v:956$172
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:765$132_Y
+ connect \Y $eq$libresoc.v:956$172_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:766$133
+ cell $eq $eq$libresoc.v:957$173
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:766$133_Y
+ connect \Y $eq$libresoc.v:957$173_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:772$139
+ cell $eq $eq$libresoc.v:963$179
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:772$139_Y
+ connect \Y $eq$libresoc.v:963$179_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:773$140
+ cell $eq $eq$libresoc.v:964$180
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:773$140_Y
+ connect \Y $eq$libresoc.v:964$180_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
- cell $eq $eq$libresoc.v:774$141
+ cell $eq $eq$libresoc.v:965$181
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'110
- connect \Y $eq$libresoc.v:774$141_Y
+ connect \Y $eq$libresoc.v:965$181_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- cell $eq $eq$libresoc.v:779$146
+ cell $eq $eq$libresoc.v:970$186
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 1'0
- connect \Y $eq$libresoc.v:779$146_Y
+ connect \Y $eq$libresoc.v:970$186_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
- cell $eq $eq$libresoc.v:780$147
+ cell $eq $eq$libresoc.v:971$187
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi_addr_i
connect \B 3'100
- connect \Y $eq$libresoc.v:780$147_Y
+ connect \Y $eq$libresoc.v:971$187_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:721$88
+ cell $not $not$libresoc.v:912$128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:721$88_Y
+ connect \Y $not$libresoc.v:912$128_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:723$90
+ cell $not $not$libresoc.v:914$130
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:723$90_Y
+ connect \Y $not$libresoc.v:914$130_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254"
- cell $not $not$libresoc.v:732$99
+ cell $not $not$libresoc.v:923$139
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \do_step
- connect \Y $not$libresoc.v:732$99_Y
+ connect \Y $not$libresoc.v:923$139_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:736$103
+ cell $not $not$libresoc.v:927$143
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:736$103_Y
+ connect \Y $not$libresoc.v:927$143_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:739$106
+ cell $not $not$libresoc.v:930$146
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:739$106_Y
+ connect \Y $not$libresoc.v:930$146_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:744$111
+ cell $not $not$libresoc.v:935$151
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:744$111_Y
+ connect \Y $not$libresoc.v:935$151_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:746$113
+ cell $not $not$libresoc.v:937$153
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:746$113_Y
+ connect \Y $not$libresoc.v:937$153_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:748$115
+ cell $not $not$libresoc.v:939$155
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:748$115_Y
+ connect \Y $not$libresoc.v:939$155_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:752$119
+ cell $not $not$libresoc.v:943$159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:752$119_Y
+ connect \Y $not$libresoc.v:943$159_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:754$121
+ cell $not $not$libresoc.v:945$161
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:754$121_Y
+ connect \Y $not$libresoc.v:945$161_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:760$127
+ cell $not $not$libresoc.v:951$167
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:760$127_Y
+ connect \Y $not$libresoc.v:951$167_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:762$129
+ cell $not $not$libresoc.v:953$169
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:762$129_Y
+ connect \Y $not$libresoc.v:953$169_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:767$134
+ cell $not $not$libresoc.v:958$174
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:767$134_Y
+ connect \Y $not$libresoc.v:958$174_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:769$136
+ cell $not $not$libresoc.v:960$176
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:769$136_Y
+ connect \Y $not$libresoc.v:960$176_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:770$137
+ cell $not $not$libresoc.v:961$177
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:770$137_Y
+ connect \Y $not$libresoc.v:961$177_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- cell $not $not$libresoc.v:775$142
+ cell $not $not$libresoc.v:966$182
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_req_i_1
- connect \Y $not$libresoc.v:775$142_Y
+ connect \Y $not$libresoc.v:966$182_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
- cell $not $not$libresoc.v:777$144
+ cell $not $not$libresoc.v:968$184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi_read_log_data
- connect \Y $not$libresoc.v:777$144_Y
+ connect \Y $not$libresoc.v:968$184_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170"
- cell $pos $pos$libresoc.v:737$104
+ cell $pos $pos$libresoc.v:928$144
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping }
- connect \Y $pos$libresoc.v:737$104_Y
- end
- attribute \src "libresoc.v:1005.3-1013.6"
- process $proc$libresoc.v:1005$198
- assign { } { }
- assign { } { }
- assign $0\dmi_read_log_data$next[0:0]$199 $1\dmi_read_log_data$next[0:0]$200
- attribute \src "libresoc.v:1006.5-1006.29"
- switch \initial
- attribute \src "libresoc.v:1006.9-1006.17"
- case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\dmi_read_log_data$next[0:0]$200 1'0
- case
- assign $1\dmi_read_log_data$next[0:0]$200 \$120
- end
- sync always
- update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$199
+ connect \Y $pos$libresoc.v:928$144_Y
end
- attribute \src "libresoc.v:1014.3-1023.6"
- process $proc$libresoc.v:1014$201
+ attribute \src "libresoc.v:1012.3-1021.6"
+ process $proc$libresoc.v:1012$200
assign { } { }
assign { } { }
- assign $0\d_cr_req[0:0] $1\d_cr_req[0:0]
- attribute \src "libresoc.v:1015.5-1015.29"
+ assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0]
+ attribute \src "libresoc.v:1013.5-1013.29"
switch \initial
- attribute \src "libresoc.v:1015.9-1015.17"
+ attribute \src "libresoc.v:1013.9-1013.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154"
switch \dmi_addr_i
attribute \src "libresoc.v:0.0-0.0"
- case 4'1000
+ case 4'0101
assign { } { }
- assign $1\d_cr_req[0:0] \dmi_req_i
+ assign $1\d_gpr_req[0:0] \dmi_req_i
case
- assign $1\d_cr_req[0:0] 1'0
+ assign $1\d_gpr_req[0:0] 1'0
end
sync always
- update \d_cr_req $0\d_cr_req[0:0]
+ update \d_gpr_req $0\d_gpr_req[0:0]
end
- attribute \src "libresoc.v:1024.3-1033.6"
- process $proc$libresoc.v:1024$202
+ attribute \src "libresoc.v:1022.3-1030.6"
+ process $proc$libresoc.v:1022$201
assign { } { }
assign { } { }
- assign $0\d_xer_req[0:0] $1\d_xer_req[0:0]
- attribute \src "libresoc.v:1025.5-1025.29"
+ assign $0\dmi_req_i_1$next[0:0]$202 $1\dmi_req_i_1$next[0:0]$203
+ attribute \src "libresoc.v:1023.5-1023.29"
switch \initial
- attribute \src "libresoc.v:1025.9-1025.17"
+ attribute \src "libresoc.v:1023.9-1023.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154"
- switch \dmi_addr_i
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
- case 4'1001
- assign { } { }
- assign $1\d_xer_req[0:0] \dmi_req_i
- case
- assign $1\d_xer_req[0:0] 1'0
- end
- sync always
- update \d_xer_req $0\d_xer_req[0:0]
- end
- attribute \src "libresoc.v:1034.3-1064.6"
- process $proc$libresoc.v:1034$203
- assign { } { }
- assign { } { }
- assign $0\dmi_dout[63:0] $1\dmi_dout[63:0]
- attribute \src "libresoc.v:1035.5-1035.29"
- switch \initial
- attribute \src "libresoc.v:1035.9-1035.17"
case 1'1
- case
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173"
- switch \dmi_addr_i
- attribute \src "libresoc.v:0.0-0.0"
- case 4'0001
assign { } { }
- assign $1\dmi_dout[63:0] \stat_reg
- attribute \src "libresoc.v:0.0-0.0"
- case 4'0010
- assign { } { }
- assign $1\dmi_dout[63:0] \core_dbg_pc
- attribute \src "libresoc.v:0.0-0.0"
- case 4'0011
- assign { } { }
- assign $1\dmi_dout[63:0] \core_dbg_msr
- attribute \src "libresoc.v:0.0-0.0"
- case 4'0101
- assign { } { }
- assign $1\dmi_dout[63:0] \d_gpr_data
- attribute \src "libresoc.v:0.0-0.0"
- case 4'0110
- assign { } { }
- assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr }
- attribute \src "libresoc.v:0.0-0.0"
- case 4'0111
- assign { } { }
- assign $1\dmi_dout[63:0] \log_dmi_data
- attribute \src "libresoc.v:0.0-0.0"
- case 4'1000
- assign { } { }
- assign $1\dmi_dout[63:0] \d_cr_data
- attribute \src "libresoc.v:0.0-0.0"
- case 4'1001
- assign { } { }
- assign $1\dmi_dout[63:0] \d_xer_data
+ assign $1\dmi_req_i_1$next[0:0]$203 1'0
case
- assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\dmi_req_i_1$next[0:0]$203 \dmi_req_i
end
sync always
- update \dmi_dout $0\dmi_dout[63:0]
+ update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$202
end
- attribute \src "libresoc.v:1065.3-1094.6"
- process $proc$libresoc.v:1065$204
+ attribute \src "libresoc.v:1031.3-1080.6"
+ process $proc$libresoc.v:1031$204
+ assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\do_step$next[0:0]$205 $5\do_step$next[0:0]$210
- attribute \src "libresoc.v:1066.5-1066.29"
+ assign $0\terminated$next[0:0]$205 $8\terminated$next[0:0]$213
+ attribute \src "libresoc.v:1032.5-1032.29"
switch \initial
- attribute \src "libresoc.v:1066.9-1066.17"
+ attribute \src "libresoc.v:1032.9-1032.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$9 \$5 }
+ switch { \$65 \$61 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\do_step$next[0:0]$206 $2\do_step$next[0:0]$207
+ assign $1\terminated$next[0:0]$206 $2\terminated$next[0:0]$207
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\do_step$next[0:0]$207 $3\do_step$next[0:0]$208
+ assign $2\terminated$next[0:0]$207 $3\terminated$next[0:0]$208
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$15 \$13 \$11 }
+ switch { \$71 \$69 \$67 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $3\do_step$next[0:0]$208 $4\do_step$next[0:0]$209
+ assign { } { }
+ assign { } { }
+ assign $3\terminated$next[0:0]$208 $6\terminated$next[0:0]$211
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208"
+ switch \dmi_din [1]
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $4\terminated$next[0:0]$209 1'0
+ case
+ assign $4\terminated$next[0:0]$209 \terminated
+ end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213"
switch \dmi_din [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\do_step$next[0:0]$209 1'1
+ assign $5\terminated$next[0:0]$210 1'0
case
- assign $4\do_step$next[0:0]$209 1'0
+ assign $5\terminated$next[0:0]$210 $4\terminated$next[0:0]$209
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218"
+ switch \dmi_din [4]
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $6\terminated$next[0:0]$211 1'0
+ case
+ assign $6\terminated$next[0:0]$211 $5\terminated$next[0:0]$210
end
case
- assign $3\do_step$next[0:0]$208 1'0
+ assign $3\terminated$next[0:0]$208 \terminated
end
case
- assign $2\do_step$next[0:0]$207 1'0
+ assign $2\terminated$next[0:0]$207 \terminated
end
case
- assign $1\do_step$next[0:0]$206 1'0
+ assign $1\terminated$next[0:0]$206 \terminated
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247"
+ switch \terminate_i
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $7\terminated$next[0:0]$212 1'1
+ case
+ assign $7\terminated$next[0:0]$212 $1\terminated$next[0:0]$206
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\do_step$next[0:0]$210 1'0
+ assign $8\terminated$next[0:0]$213 1'0
case
- assign $5\do_step$next[0:0]$210 $1\do_step$next[0:0]$206
+ assign $8\terminated$next[0:0]$213 $7\terminated$next[0:0]$212
end
sync always
- update \do_step$next $0\do_step$next[0:0]$205
+ update \terminated$next $0\terminated$next[0:0]$205
end
- attribute \src "libresoc.v:1095.3-1124.6"
- process $proc$libresoc.v:1095$211
+ attribute \src "libresoc.v:1081.3-1124.6"
+ process $proc$libresoc.v:1081$214
assign { } { }
assign { } { }
assign { } { }
- assign $0\do_reset$next[0:0]$212 $5\do_reset$next[0:0]$217
- attribute \src "libresoc.v:1096.5-1096.29"
+ assign { } { }
+ assign $0\stopping$next[0:0]$215 $7\stopping$next[0:0]$222
+ attribute \src "libresoc.v:1082.5-1082.29"
switch \initial
- attribute \src "libresoc.v:1096.9-1096.17"
+ attribute \src "libresoc.v:1082.9-1082.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$23 \$19 }
+ switch { \$79 \$75 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\do_reset$next[0:0]$213 $2\do_reset$next[0:0]$214
+ assign $1\stopping$next[0:0]$216 $2\stopping$next[0:0]$217
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\do_reset$next[0:0]$214 $3\do_reset$next[0:0]$215
+ assign $2\stopping$next[0:0]$217 $3\stopping$next[0:0]$218
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$29 \$27 \$25 }
+ switch { \$85 \$83 \$81 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $3\do_reset$next[0:0]$215 $4\do_reset$next[0:0]$216
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208"
- switch \dmi_din [1]
+ assign { } { }
+ assign $3\stopping$next[0:0]$218 $5\stopping$next[0:0]$220
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211"
+ switch \dmi_din [0]
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $4\stopping$next[0:0]$219 1'1
+ case
+ assign $4\stopping$next[0:0]$219 \stopping
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218"
+ switch \dmi_din [4]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\do_reset$next[0:0]$216 1'1
+ assign $5\stopping$next[0:0]$220 1'0
case
- assign $4\do_reset$next[0:0]$216 1'0
+ assign $5\stopping$next[0:0]$220 $4\stopping$next[0:0]$219
end
case
- assign $3\do_reset$next[0:0]$215 1'0
+ assign $3\stopping$next[0:0]$218 \stopping
end
case
- assign $2\do_reset$next[0:0]$214 1'0
+ assign $2\stopping$next[0:0]$217 \stopping
end
case
- assign $1\do_reset$next[0:0]$213 1'0
+ assign $1\stopping$next[0:0]$216 \stopping
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247"
+ switch \terminate_i
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $6\stopping$next[0:0]$221 1'1
+ case
+ assign $6\stopping$next[0:0]$221 $1\stopping$next[0:0]$216
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\do_reset$next[0:0]$217 1'0
+ assign $7\stopping$next[0:0]$222 1'0
case
- assign $5\do_reset$next[0:0]$217 $1\do_reset$next[0:0]$213
+ assign $7\stopping$next[0:0]$222 $6\stopping$next[0:0]$221
end
sync always
- update \do_reset$next $0\do_reset$next[0:0]$212
+ update \stopping$next $0\stopping$next[0:0]$215
end
- attribute \src "libresoc.v:1125.3-1154.6"
- process $proc$libresoc.v:1125$218
+ attribute \src "libresoc.v:1125.3-1152.6"
+ process $proc$libresoc.v:1125$223
assign { } { }
assign { } { }
assign { } { }
- assign $0\do_icreset$next[0:0]$219 $5\do_icreset$next[0:0]$224
+ assign $0\gspr_index$next[6:0]$224 $4\gspr_index$next[6:0]$228
attribute \src "libresoc.v:1126.5-1126.29"
switch \initial
attribute \src "libresoc.v:1126.9-1126.17"
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$37 \$33 }
+ switch { \$93 \$89 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\do_icreset$next[0:0]$220 $2\do_icreset$next[0:0]$221
+ assign $1\gspr_index$next[6:0]$225 $2\gspr_index$next[6:0]$226
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\do_icreset$next[0:0]$221 $3\do_icreset$next[0:0]$222
+ assign $2\gspr_index$next[6:0]$226 $3\gspr_index$next[6:0]$227
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$43 \$41 \$39 }
+ switch { \$99 \$97 \$95 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
+ assign $3\gspr_index$next[6:0]$227 \gspr_index
+ attribute \src "libresoc.v:0.0-0.0"
+ case 3'-1-
assign { } { }
- assign $3\do_icreset$next[0:0]$222 $4\do_icreset$next[0:0]$223
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216"
- switch \dmi_din [2]
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\do_icreset$next[0:0]$223 1'1
- case
- assign $4\do_icreset$next[0:0]$223 1'0
- end
+ assign $3\gspr_index$next[6:0]$227 \dmi_din [6:0]
case
- assign $3\do_icreset$next[0:0]$222 1'0
+ assign $3\gspr_index$next[6:0]$227 \gspr_index
end
case
- assign $2\do_icreset$next[0:0]$221 1'0
+ assign $2\gspr_index$next[6:0]$226 \gspr_index
end
case
- assign $1\do_icreset$next[0:0]$220 1'0
+ assign $1\gspr_index$next[6:0]$225 \gspr_index
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\do_icreset$next[0:0]$224 1'0
+ assign $4\gspr_index$next[6:0]$228 7'0000000
case
- assign $5\do_icreset$next[0:0]$224 $1\do_icreset$next[0:0]$220
+ assign $4\gspr_index$next[6:0]$228 $1\gspr_index$next[6:0]$225
end
sync always
- update \do_icreset$next $0\do_icreset$next[0:0]$219
+ update \gspr_index$next $0\gspr_index$next[6:0]$224
end
- attribute \src "libresoc.v:1155.3-1188.6"
- process $proc$libresoc.v:1155$225
+ attribute \src "libresoc.v:1153.3-1186.6"
+ process $proc$libresoc.v:1153$229
assign { } { }
assign { } { }
assign { } { }
- assign $0\do_dmi_log_rd$next[0:0]$226 $4\do_dmi_log_rd$next[0:0]$230
- attribute \src "libresoc.v:1156.5-1156.29"
+ assign $0\log_dmi_addr$next[31:0]$230 $4\log_dmi_addr$next[31:0]$234
+ attribute \src "libresoc.v:1154.5-1154.29"
switch \initial
- attribute \src "libresoc.v:1156.9-1156.17"
+ attribute \src "libresoc.v:1154.9-1154.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$51 \$47 }
+ switch { \$107 \$103 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\do_dmi_log_rd$next[0:0]$227 $2\do_dmi_log_rd$next[0:0]$228
+ assign $1\log_dmi_addr$next[31:0]$231 $2\log_dmi_addr$next[31:0]$232
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\do_dmi_log_rd$next[0:0]$228 $3\do_dmi_log_rd$next[0:0]$229
+ assign $2\log_dmi_addr$next[31:0]$232 $3\log_dmi_addr$next[31:0]$233
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$57 \$55 \$53 }
+ switch { \$113 \$111 \$109 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $3\do_dmi_log_rd$next[0:0]$229 1'0
+ assign $3\log_dmi_addr$next[31:0]$233 \log_dmi_addr
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $3\do_dmi_log_rd$next[0:0]$229 1'0
+ assign $3\log_dmi_addr$next[31:0]$233 \log_dmi_addr
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $3\do_dmi_log_rd$next[0:0]$229 1'1
+ assign $3\log_dmi_addr$next[31:0]$233 \dmi_din [31:0]
case
- assign $3\do_dmi_log_rd$next[0:0]$229 1'0
+ assign $3\log_dmi_addr$next[31:0]$233 \log_dmi_addr
end
case
- assign $2\do_dmi_log_rd$next[0:0]$228 1'0
+ assign $2\log_dmi_addr$next[31:0]$232 \log_dmi_addr
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
- assign { } { }
- assign $1\do_dmi_log_rd$next[0:0]$227 1'1
+ assign $1\log_dmi_addr$next[31:0]$231 [31:2] \log_dmi_addr [31:2]
+ assign $1\log_dmi_addr$next[31:0]$231 [1:0] \$115 [1:0]
case
- assign $1\do_dmi_log_rd$next[0:0]$227 1'0
+ assign $1\log_dmi_addr$next[31:0]$231 \log_dmi_addr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\do_dmi_log_rd$next[0:0]$230 1'0
+ assign $4\log_dmi_addr$next[31:0]$234 0
case
- assign $4\do_dmi_log_rd$next[0:0]$230 $1\do_dmi_log_rd$next[0:0]$227
+ assign $4\log_dmi_addr$next[31:0]$234 $1\log_dmi_addr$next[31:0]$231
end
sync always
- update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$226
- end
- attribute \src "libresoc.v:485.7-485.20"
- process $proc$libresoc.v:485$231
- assign { } { }
- assign $0\initial[0:0] 1'0
- sync always
- update \initial $0\initial[0:0]
- sync init
- end
- attribute \src "libresoc.v:658.7-658.31"
- process $proc$libresoc.v:658$232
- assign { } { }
- assign $1\dmi_read_log_data[0:0] 1'0
- sync always
- sync init
- update \dmi_read_log_data $1\dmi_read_log_data[0:0]
- end
- attribute \src "libresoc.v:662.7-662.33"
- process $proc$libresoc.v:662$233
- assign { } { }
- assign $1\dmi_read_log_data_1[0:0] 1'0
- sync always
- sync init
- update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0]
- end
- attribute \src "libresoc.v:668.7-668.25"
- process $proc$libresoc.v:668$234
- assign { } { }
- assign $1\dmi_req_i_1[0:0] 1'0
- sync always
- sync init
- update \dmi_req_i_1 $1\dmi_req_i_1[0:0]
- end
- attribute \src "libresoc.v:674.7-674.27"
- process $proc$libresoc.v:674$235
- assign { } { }
- assign $1\do_dmi_log_rd[0:0] 1'0
- sync always
- sync init
- update \do_dmi_log_rd $1\do_dmi_log_rd[0:0]
- end
- attribute \src "libresoc.v:678.7-678.24"
- process $proc$libresoc.v:678$236
- assign { } { }
- assign $1\do_icreset[0:0] 1'0
- sync always
- sync init
- update \do_icreset $1\do_icreset[0:0]
- end
- attribute \src "libresoc.v:682.7-682.22"
- process $proc$libresoc.v:682$237
- assign { } { }
- assign $1\do_reset[0:0] 1'0
- sync always
- sync init
- update \do_reset $1\do_reset[0:0]
- end
- attribute \src "libresoc.v:686.7-686.21"
- process $proc$libresoc.v:686$238
- assign { } { }
- assign $1\do_step[0:0] 1'0
- sync always
- sync init
- update \do_step $1\do_step[0:0]
+ update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$230
end
- attribute \src "libresoc.v:690.13-690.31"
- process $proc$libresoc.v:690$239
+ attribute \src "libresoc.v:1187.3-1195.6"
+ process $proc$libresoc.v:1187$235
assign { } { }
- assign $1\gspr_index[6:0] 7'0000000
- sync always
- sync init
- update \gspr_index $1\gspr_index[6:0]
- end
- attribute \src "libresoc.v:696.14-696.34"
- process $proc$libresoc.v:696$240
assign { } { }
- assign $1\log_dmi_addr[31:0] 0
+ assign $0\dmi_read_log_data_1$next[0:0]$236 $1\dmi_read_log_data_1$next[0:0]$237
+ attribute \src "libresoc.v:1188.5-1188.29"
+ switch \initial
+ attribute \src "libresoc.v:1188.9-1188.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \intclk_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\dmi_read_log_data_1$next[0:0]$237 1'0
+ case
+ assign $1\dmi_read_log_data_1$next[0:0]$237 \dmi_read_log_data
+ end
sync always
- sync init
- update \log_dmi_addr $1\log_dmi_addr[31:0]
+ update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$236
end
- attribute \src "libresoc.v:708.7-708.22"
- process $proc$libresoc.v:708$241
+ attribute \src "libresoc.v:1196.3-1204.6"
+ process $proc$libresoc.v:1196$238
assign { } { }
- assign $1\stopping[0:0] 1'0
- sync always
- sync init
- update \stopping $1\stopping[0:0]
- end
- attribute \src "libresoc.v:714.7-714.24"
- process $proc$libresoc.v:714$242
assign { } { }
- assign $1\terminated[0:0] 1'0
+ assign $0\dmi_read_log_data$next[0:0]$239 $1\dmi_read_log_data$next[0:0]$240
+ attribute \src "libresoc.v:1197.5-1197.29"
+ switch \initial
+ attribute \src "libresoc.v:1197.9-1197.17"
+ case 1'1
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
+ switch \intclk_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\dmi_read_log_data$next[0:0]$240 1'0
+ case
+ assign $1\dmi_read_log_data$next[0:0]$240 \$120
+ end
sync always
- sync init
- update \terminated $1\terminated[0:0]
- end
- attribute \src "libresoc.v:781.3-782.51"
- process $proc$libresoc.v:781$148
- assign { } { }
- assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next
- sync posedge \clk
- update \dmi_read_log_data $0\dmi_read_log_data[0:0]
- end
- attribute \src "libresoc.v:783.3-784.55"
- process $proc$libresoc.v:783$149
- assign { } { }
- assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next
- sync posedge \clk
- update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0]
- end
- attribute \src "libresoc.v:785.3-786.41"
- process $proc$libresoc.v:785$150
- assign { } { }
- assign $0\log_dmi_addr[31:0] \log_dmi_addr$next
- sync posedge \clk
- update \log_dmi_addr $0\log_dmi_addr[31:0]
+ update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$239
end
- attribute \src "libresoc.v:787.3-788.37"
- process $proc$libresoc.v:787$151
+ attribute \src "libresoc.v:1205.3-1214.6"
+ process $proc$libresoc.v:1205$241
assign { } { }
- assign $0\gspr_index[6:0] \gspr_index$next
- sync posedge \clk
- update \gspr_index $0\gspr_index[6:0]
- end
- attribute \src "libresoc.v:789.3-790.33"
- process $proc$libresoc.v:789$152
- assign { } { }
- assign $0\stopping[0:0] \stopping$next
- sync posedge \clk
- update \stopping $0\stopping[0:0]
- end
- attribute \src "libresoc.v:791.3-792.37"
- process $proc$libresoc.v:791$153
- assign { } { }
- assign $0\terminated[0:0] \terminated$next
- sync posedge \clk
- update \terminated $0\terminated[0:0]
- end
- attribute \src "libresoc.v:793.3-794.39"
- process $proc$libresoc.v:793$154
- assign { } { }
- assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next
- sync posedge \clk
- update \dmi_req_i_1 $0\dmi_req_i_1[0:0]
- end
- attribute \src "libresoc.v:795.3-796.43"
- process $proc$libresoc.v:795$155
assign { } { }
- assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next
- sync posedge \clk
- update \do_dmi_log_rd $0\do_dmi_log_rd[0:0]
- end
- attribute \src "libresoc.v:797.3-798.37"
- process $proc$libresoc.v:797$156
- assign { } { }
- assign $0\do_icreset[0:0] \do_icreset$next
- sync posedge \clk
- update \do_icreset $0\do_icreset[0:0]
- end
- attribute \src "libresoc.v:799.3-800.33"
- process $proc$libresoc.v:799$157
- assign { } { }
- assign $0\do_reset[0:0] \do_reset$next
- sync posedge \clk
- update \do_reset $0\do_reset[0:0]
- end
- attribute \src "libresoc.v:801.3-802.31"
- process $proc$libresoc.v:801$158
- assign { } { }
- assign $0\do_step[0:0] \do_step$next
- sync posedge \clk
- update \do_step $0\do_step[0:0]
- end
- attribute \src "libresoc.v:803.3-820.6"
- process $proc$libresoc.v:803$159
- assign { } { }
- assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0]
- attribute \src "libresoc.v:804.5-804.29"
+ assign $0\d_cr_req[0:0] $1\d_cr_req[0:0]
+ attribute \src "libresoc.v:1206.5-1206.29"
switch \initial
- attribute \src "libresoc.v:804.9-804.17"
+ attribute \src "libresoc.v:1206.9-1206.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154"
switch \dmi_addr_i
attribute \src "libresoc.v:0.0-0.0"
- case 4'0101
- assign { } { }
- assign $1\dmi_ack_o[0:0] \d_gpr_ack
- attribute \src "libresoc.v:0.0-0.0"
case 4'1000
assign { } { }
- assign $1\dmi_ack_o[0:0] \d_cr_ack
- attribute \src "libresoc.v:0.0-0.0"
- case 4'1001
- assign { } { }
- assign $1\dmi_ack_o[0:0] \d_xer_ack
- attribute \src "libresoc.v:0.0-0.0"
+ assign $1\d_cr_req[0:0] \dmi_req_i
case
- assign { } { }
- assign $1\dmi_ack_o[0:0] \dmi_req_i
+ assign $1\d_cr_req[0:0] 1'0
end
sync always
- update \dmi_ack_o $0\dmi_ack_o[0:0]
+ update \d_cr_req $0\d_cr_req[0:0]
end
- attribute \src "libresoc.v:821.3-830.6"
- process $proc$libresoc.v:821$160
+ attribute \src "libresoc.v:1215.3-1224.6"
+ process $proc$libresoc.v:1215$242
assign { } { }
assign { } { }
- assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0]
- attribute \src "libresoc.v:822.5-822.29"
+ assign $0\d_xer_req[0:0] $1\d_xer_req[0:0]
+ attribute \src "libresoc.v:1216.5-1216.29"
switch \initial
- attribute \src "libresoc.v:822.9-822.17"
+ attribute \src "libresoc.v:1216.9-1216.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154"
switch \dmi_addr_i
attribute \src "libresoc.v:0.0-0.0"
- case 4'0101
+ case 4'1001
assign { } { }
- assign $1\d_gpr_req[0:0] \dmi_req_i
+ assign $1\d_xer_req[0:0] \dmi_req_i
case
- assign $1\d_gpr_req[0:0] 1'0
+ assign $1\d_xer_req[0:0] 1'0
end
sync always
- update \d_gpr_req $0\d_gpr_req[0:0]
+ update \d_xer_req $0\d_xer_req[0:0]
end
- attribute \src "libresoc.v:831.3-839.6"
- process $proc$libresoc.v:831$161
+ attribute \src "libresoc.v:1225.3-1255.6"
+ process $proc$libresoc.v:1225$243
assign { } { }
assign { } { }
- assign $0\dmi_req_i_1$next[0:0]$162 $1\dmi_req_i_1$next[0:0]$163
- attribute \src "libresoc.v:832.5-832.29"
+ assign $0\dmi_dout[63:0] $1\dmi_dout[63:0]
+ attribute \src "libresoc.v:1226.5-1226.29"
switch \initial
- attribute \src "libresoc.v:832.9-832.17"
+ attribute \src "libresoc.v:1226.9-1226.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173"
+ switch \dmi_addr_i
attribute \src "libresoc.v:0.0-0.0"
- case 1'1
+ case 4'0001
+ assign { } { }
+ assign $1\dmi_dout[63:0] \stat_reg
+ attribute \src "libresoc.v:0.0-0.0"
+ case 4'0010
+ assign { } { }
+ assign $1\dmi_dout[63:0] \core_dbg_pc
+ attribute \src "libresoc.v:0.0-0.0"
+ case 4'0011
+ assign { } { }
+ assign $1\dmi_dout[63:0] \core_dbg_msr
+ attribute \src "libresoc.v:0.0-0.0"
+ case 4'0101
assign { } { }
- assign $1\dmi_req_i_1$next[0:0]$163 1'0
+ assign $1\dmi_dout[63:0] \d_gpr_data
+ attribute \src "libresoc.v:0.0-0.0"
+ case 4'0110
+ assign { } { }
+ assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr }
+ attribute \src "libresoc.v:0.0-0.0"
+ case 4'0111
+ assign { } { }
+ assign $1\dmi_dout[63:0] \log_dmi_data
+ attribute \src "libresoc.v:0.0-0.0"
+ case 4'1000
+ assign { } { }
+ assign $1\dmi_dout[63:0] \d_cr_data
+ attribute \src "libresoc.v:0.0-0.0"
+ case 4'1001
+ assign { } { }
+ assign $1\dmi_dout[63:0] \d_xer_data
case
- assign $1\dmi_req_i_1$next[0:0]$163 \dmi_req_i
+ assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$162
+ update \dmi_dout $0\dmi_dout[63:0]
end
- attribute \src "libresoc.v:840.3-889.6"
- process $proc$libresoc.v:840$164
+ attribute \src "libresoc.v:1256.3-1285.6"
+ process $proc$libresoc.v:1256$244
assign { } { }
assign { } { }
assign { } { }
- assign { } { }
- assign $0\terminated$next[0:0]$165 $8\terminated$next[0:0]$173
- attribute \src "libresoc.v:841.5-841.29"
+ assign $0\do_step$next[0:0]$245 $5\do_step$next[0:0]$250
+ attribute \src "libresoc.v:1257.5-1257.29"
switch \initial
- attribute \src "libresoc.v:841.9-841.17"
+ attribute \src "libresoc.v:1257.9-1257.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$65 \$61 }
+ switch { \$9 \$5 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\terminated$next[0:0]$166 $2\terminated$next[0:0]$167
+ assign $1\do_step$next[0:0]$246 $2\do_step$next[0:0]$247
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\terminated$next[0:0]$167 $3\terminated$next[0:0]$168
+ assign $2\do_step$next[0:0]$247 $3\do_step$next[0:0]$248
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$71 \$69 \$67 }
+ switch { \$15 \$13 \$11 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign { } { }
- assign { } { }
- assign $3\terminated$next[0:0]$168 $6\terminated$next[0:0]$171
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208"
- switch \dmi_din [1]
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\terminated$next[0:0]$169 1'0
- case
- assign $4\terminated$next[0:0]$169 \terminated
- end
+ assign $3\do_step$next[0:0]$248 $4\do_step$next[0:0]$249
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213"
switch \dmi_din [3]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\terminated$next[0:0]$170 1'0
- case
- assign $5\terminated$next[0:0]$170 $4\terminated$next[0:0]$169
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218"
- switch \dmi_din [4]
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $6\terminated$next[0:0]$171 1'0
+ assign $4\do_step$next[0:0]$249 1'1
case
- assign $6\terminated$next[0:0]$171 $5\terminated$next[0:0]$170
+ assign $4\do_step$next[0:0]$249 1'0
end
case
- assign $3\terminated$next[0:0]$168 \terminated
+ assign $3\do_step$next[0:0]$248 1'0
end
case
- assign $2\terminated$next[0:0]$167 \terminated
+ assign $2\do_step$next[0:0]$247 1'0
end
case
- assign $1\terminated$next[0:0]$166 \terminated
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247"
- switch \terminate_i
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $7\terminated$next[0:0]$172 1'1
- case
- assign $7\terminated$next[0:0]$172 $1\terminated$next[0:0]$166
+ assign $1\do_step$next[0:0]$246 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $8\terminated$next[0:0]$173 1'0
+ assign $5\do_step$next[0:0]$250 1'0
case
- assign $8\terminated$next[0:0]$173 $7\terminated$next[0:0]$172
+ assign $5\do_step$next[0:0]$250 $1\do_step$next[0:0]$246
end
sync always
- update \terminated$next $0\terminated$next[0:0]$165
+ update \do_step$next $0\do_step$next[0:0]$245
end
- attribute \src "libresoc.v:890.3-933.6"
- process $proc$libresoc.v:890$174
- assign { } { }
+ attribute \src "libresoc.v:1286.3-1315.6"
+ process $proc$libresoc.v:1286$251
assign { } { }
assign { } { }
assign { } { }
- assign $0\stopping$next[0:0]$175 $7\stopping$next[0:0]$182
- attribute \src "libresoc.v:891.5-891.29"
+ assign $0\do_reset$next[0:0]$252 $5\do_reset$next[0:0]$257
+ attribute \src "libresoc.v:1287.5-1287.29"
switch \initial
- attribute \src "libresoc.v:891.9-891.17"
+ attribute \src "libresoc.v:1287.9-1287.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$79 \$75 }
+ switch { \$23 \$19 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\stopping$next[0:0]$176 $2\stopping$next[0:0]$177
+ assign $1\do_reset$next[0:0]$253 $2\do_reset$next[0:0]$254
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\stopping$next[0:0]$177 $3\stopping$next[0:0]$178
+ assign $2\do_reset$next[0:0]$254 $3\do_reset$next[0:0]$255
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$85 \$83 \$81 }
+ switch { \$29 \$27 \$25 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign { } { }
- assign $3\stopping$next[0:0]$178 $5\stopping$next[0:0]$180
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211"
- switch \dmi_din [0]
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $4\stopping$next[0:0]$179 1'1
- case
- assign $4\stopping$next[0:0]$179 \stopping
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218"
- switch \dmi_din [4]
+ assign $3\do_reset$next[0:0]$255 $4\do_reset$next[0:0]$256
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208"
+ switch \dmi_din [1]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\stopping$next[0:0]$180 1'0
+ assign $4\do_reset$next[0:0]$256 1'1
case
- assign $5\stopping$next[0:0]$180 $4\stopping$next[0:0]$179
+ assign $4\do_reset$next[0:0]$256 1'0
end
case
- assign $3\stopping$next[0:0]$178 \stopping
+ assign $3\do_reset$next[0:0]$255 1'0
end
case
- assign $2\stopping$next[0:0]$177 \stopping
+ assign $2\do_reset$next[0:0]$254 1'0
end
case
- assign $1\stopping$next[0:0]$176 \stopping
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247"
- switch \terminate_i
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $6\stopping$next[0:0]$181 1'1
- case
- assign $6\stopping$next[0:0]$181 $1\stopping$next[0:0]$176
+ assign $1\do_reset$next[0:0]$253 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\stopping$next[0:0]$182 1'0
+ assign $5\do_reset$next[0:0]$257 1'0
case
- assign $7\stopping$next[0:0]$182 $6\stopping$next[0:0]$181
+ assign $5\do_reset$next[0:0]$257 $1\do_reset$next[0:0]$253
end
sync always
- update \stopping$next $0\stopping$next[0:0]$175
+ update \do_reset$next $0\do_reset$next[0:0]$252
end
- attribute \src "libresoc.v:934.3-961.6"
- process $proc$libresoc.v:934$183
+ attribute \src "libresoc.v:1316.3-1345.6"
+ process $proc$libresoc.v:1316$258
assign { } { }
assign { } { }
assign { } { }
- assign $0\gspr_index$next[6:0]$184 $4\gspr_index$next[6:0]$188
- attribute \src "libresoc.v:935.5-935.29"
+ assign $0\do_icreset$next[0:0]$259 $5\do_icreset$next[0:0]$264
+ attribute \src "libresoc.v:1317.5-1317.29"
switch \initial
- attribute \src "libresoc.v:935.9-935.17"
+ attribute \src "libresoc.v:1317.9-1317.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$93 \$89 }
+ switch { \$37 \$33 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\gspr_index$next[6:0]$185 $2\gspr_index$next[6:0]$186
+ assign $1\do_icreset$next[0:0]$260 $2\do_icreset$next[0:0]$261
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\gspr_index$next[6:0]$186 $3\gspr_index$next[6:0]$187
+ assign $2\do_icreset$next[0:0]$261 $3\do_icreset$next[0:0]$262
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$99 \$97 \$95 }
+ switch { \$43 \$41 \$39 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $3\gspr_index$next[6:0]$187 \gspr_index
- attribute \src "libresoc.v:0.0-0.0"
- case 3'-1-
assign { } { }
- assign $3\gspr_index$next[6:0]$187 \dmi_din [6:0]
+ assign $3\do_icreset$next[0:0]$262 $4\do_icreset$next[0:0]$263
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216"
+ switch \dmi_din [2]
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $4\do_icreset$next[0:0]$263 1'1
+ case
+ assign $4\do_icreset$next[0:0]$263 1'0
+ end
case
- assign $3\gspr_index$next[6:0]$187 \gspr_index
+ assign $3\do_icreset$next[0:0]$262 1'0
end
case
- assign $2\gspr_index$next[6:0]$186 \gspr_index
+ assign $2\do_icreset$next[0:0]$261 1'0
end
case
- assign $1\gspr_index$next[6:0]$185 \gspr_index
+ assign $1\do_icreset$next[0:0]$260 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\gspr_index$next[6:0]$188 7'0000000
+ assign $5\do_icreset$next[0:0]$264 1'0
case
- assign $4\gspr_index$next[6:0]$188 $1\gspr_index$next[6:0]$185
+ assign $5\do_icreset$next[0:0]$264 $1\do_icreset$next[0:0]$260
end
sync always
- update \gspr_index$next $0\gspr_index$next[6:0]$184
+ update \do_icreset$next $0\do_icreset$next[0:0]$259
end
- attribute \src "libresoc.v:962.3-995.6"
- process $proc$libresoc.v:962$189
+ attribute \src "libresoc.v:1346.3-1379.6"
+ process $proc$libresoc.v:1346$265
assign { } { }
assign { } { }
assign { } { }
- assign $0\log_dmi_addr$next[31:0]$190 $4\log_dmi_addr$next[31:0]$194
- attribute \src "libresoc.v:963.5-963.29"
+ assign $0\do_dmi_log_rd$next[0:0]$266 $4\do_dmi_log_rd$next[0:0]$270
+ attribute \src "libresoc.v:1347.5-1347.29"
switch \initial
- attribute \src "libresoc.v:963.9-963.17"
+ attribute \src "libresoc.v:1347.9-1347.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
- switch { \$107 \$103 }
+ switch { \$51 \$47 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\log_dmi_addr$next[31:0]$191 $2\log_dmi_addr$next[31:0]$192
+ assign $1\do_dmi_log_rd$next[0:0]$267 $2\do_dmi_log_rd$next[0:0]$268
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
switch \dmi_we_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\log_dmi_addr$next[31:0]$192 $3\log_dmi_addr$next[31:0]$193
+ assign $2\do_dmi_log_rd$next[0:0]$268 $3\do_dmi_log_rd$next[0:0]$269
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
- switch { \$113 \$111 \$109 }
+ switch { \$57 \$55 \$53 }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $3\log_dmi_addr$next[31:0]$193 \log_dmi_addr
+ assign $3\do_dmi_log_rd$next[0:0]$269 1'0
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $3\log_dmi_addr$next[31:0]$193 \log_dmi_addr
+ assign $3\do_dmi_log_rd$next[0:0]$269 1'0
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $3\log_dmi_addr$next[31:0]$193 \dmi_din [31:0]
+ assign $3\do_dmi_log_rd$next[0:0]$269 1'1
case
- assign $3\log_dmi_addr$next[31:0]$193 \log_dmi_addr
+ assign $3\do_dmi_log_rd$next[0:0]$269 1'0
end
case
- assign $2\log_dmi_addr$next[31:0]$192 \log_dmi_addr
+ assign $2\do_dmi_log_rd$next[0:0]$268 1'0
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
- assign $1\log_dmi_addr$next[31:0]$191 [31:2] \log_dmi_addr [31:2]
- assign $1\log_dmi_addr$next[31:0]$191 [1:0] \$115 [1:0]
+ assign { } { }
+ assign $1\do_dmi_log_rd$next[0:0]$267 1'1
case
- assign $1\log_dmi_addr$next[31:0]$191 \log_dmi_addr
+ assign $1\do_dmi_log_rd$next[0:0]$267 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\log_dmi_addr$next[31:0]$194 0
+ assign $4\do_dmi_log_rd$next[0:0]$270 1'0
case
- assign $4\log_dmi_addr$next[31:0]$194 $1\log_dmi_addr$next[31:0]$191
+ assign $4\do_dmi_log_rd$next[0:0]$270 $1\do_dmi_log_rd$next[0:0]$267
end
sync always
- update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$190
+ update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$266
end
- attribute \src "libresoc.v:996.3-1004.6"
- process $proc$libresoc.v:996$195
+ attribute \src "libresoc.v:676.7-676.20"
+ process $proc$libresoc.v:676$271
assign { } { }
+ assign $0\initial[0:0] 1'0
+ sync always
+ update \initial $0\initial[0:0]
+ sync init
+ end
+ attribute \src "libresoc.v:847.7-847.31"
+ process $proc$libresoc.v:847$272
assign { } { }
- assign $0\dmi_read_log_data_1$next[0:0]$196 $1\dmi_read_log_data_1$next[0:0]$197
- attribute \src "libresoc.v:997.5-997.29"
+ assign $1\dmi_read_log_data[0:0] 1'0
+ sync always
+ sync init
+ update \dmi_read_log_data $1\dmi_read_log_data[0:0]
+ end
+ attribute \src "libresoc.v:851.7-851.33"
+ process $proc$libresoc.v:851$273
+ assign { } { }
+ assign $1\dmi_read_log_data_1[0:0] 1'0
+ sync always
+ sync init
+ update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0]
+ end
+ attribute \src "libresoc.v:857.7-857.25"
+ process $proc$libresoc.v:857$274
+ assign { } { }
+ assign $1\dmi_req_i_1[0:0] 1'0
+ sync always
+ sync init
+ update \dmi_req_i_1 $1\dmi_req_i_1[0:0]
+ end
+ attribute \src "libresoc.v:863.7-863.27"
+ process $proc$libresoc.v:863$275
+ assign { } { }
+ assign $1\do_dmi_log_rd[0:0] 1'0
+ sync always
+ sync init
+ update \do_dmi_log_rd $1\do_dmi_log_rd[0:0]
+ end
+ attribute \src "libresoc.v:867.7-867.24"
+ process $proc$libresoc.v:867$276
+ assign { } { }
+ assign $1\do_icreset[0:0] 1'0
+ sync always
+ sync init
+ update \do_icreset $1\do_icreset[0:0]
+ end
+ attribute \src "libresoc.v:871.7-871.22"
+ process $proc$libresoc.v:871$277
+ assign { } { }
+ assign $1\do_reset[0:0] 1'0
+ sync always
+ sync init
+ update \do_reset $1\do_reset[0:0]
+ end
+ attribute \src "libresoc.v:875.7-875.21"
+ process $proc$libresoc.v:875$278
+ assign { } { }
+ assign $1\do_step[0:0] 1'0
+ sync always
+ sync init
+ update \do_step $1\do_step[0:0]
+ end
+ attribute \src "libresoc.v:879.13-879.31"
+ process $proc$libresoc.v:879$279
+ assign { } { }
+ assign $1\gspr_index[6:0] 7'0000000
+ sync always
+ sync init
+ update \gspr_index $1\gspr_index[6:0]
+ end
+ attribute \src "libresoc.v:889.14-889.34"
+ process $proc$libresoc.v:889$280
+ assign { } { }
+ assign $1\log_dmi_addr[31:0] 0
+ sync always
+ sync init
+ update \log_dmi_addr $1\log_dmi_addr[31:0]
+ end
+ attribute \src "libresoc.v:899.7-899.22"
+ process $proc$libresoc.v:899$281
+ assign { } { }
+ assign $1\stopping[0:0] 1'0
+ sync always
+ sync init
+ update \stopping $1\stopping[0:0]
+ end
+ attribute \src "libresoc.v:905.7-905.24"
+ process $proc$libresoc.v:905$282
+ assign { } { }
+ assign $1\terminated[0:0] 1'0
+ sync always
+ sync init
+ update \terminated $1\terminated[0:0]
+ end
+ attribute \src "libresoc.v:972.3-973.51"
+ process $proc$libresoc.v:972$188
+ assign { } { }
+ assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next
+ sync posedge \intclk_clk
+ update \dmi_read_log_data $0\dmi_read_log_data[0:0]
+ end
+ attribute \src "libresoc.v:974.3-975.55"
+ process $proc$libresoc.v:974$189
+ assign { } { }
+ assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next
+ sync posedge \intclk_clk
+ update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0]
+ end
+ attribute \src "libresoc.v:976.3-977.41"
+ process $proc$libresoc.v:976$190
+ assign { } { }
+ assign $0\log_dmi_addr[31:0] \log_dmi_addr$next
+ sync posedge \intclk_clk
+ update \log_dmi_addr $0\log_dmi_addr[31:0]
+ end
+ attribute \src "libresoc.v:978.3-979.37"
+ process $proc$libresoc.v:978$191
+ assign { } { }
+ assign $0\gspr_index[6:0] \gspr_index$next
+ sync posedge \intclk_clk
+ update \gspr_index $0\gspr_index[6:0]
+ end
+ attribute \src "libresoc.v:980.3-981.33"
+ process $proc$libresoc.v:980$192
+ assign { } { }
+ assign $0\stopping[0:0] \stopping$next
+ sync posedge \intclk_clk
+ update \stopping $0\stopping[0:0]
+ end
+ attribute \src "libresoc.v:982.3-983.37"
+ process $proc$libresoc.v:982$193
+ assign { } { }
+ assign $0\terminated[0:0] \terminated$next
+ sync posedge \intclk_clk
+ update \terminated $0\terminated[0:0]
+ end
+ attribute \src "libresoc.v:984.3-985.39"
+ process $proc$libresoc.v:984$194
+ assign { } { }
+ assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next
+ sync posedge \intclk_clk
+ update \dmi_req_i_1 $0\dmi_req_i_1[0:0]
+ end
+ attribute \src "libresoc.v:986.3-987.43"
+ process $proc$libresoc.v:986$195
+ assign { } { }
+ assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next
+ sync posedge \intclk_clk
+ update \do_dmi_log_rd $0\do_dmi_log_rd[0:0]
+ end
+ attribute \src "libresoc.v:988.3-989.37"
+ process $proc$libresoc.v:988$196
+ assign { } { }
+ assign $0\do_icreset[0:0] \do_icreset$next
+ sync posedge \intclk_clk
+ update \do_icreset $0\do_icreset[0:0]
+ end
+ attribute \src "libresoc.v:990.3-991.33"
+ process $proc$libresoc.v:990$197
+ assign { } { }
+ assign $0\do_reset[0:0] \do_reset$next
+ sync posedge \intclk_clk
+ update \do_reset $0\do_reset[0:0]
+ end
+ attribute \src "libresoc.v:992.3-993.31"
+ process $proc$libresoc.v:992$198
+ assign { } { }
+ assign $0\do_step[0:0] \do_step$next
+ sync posedge \intclk_clk
+ update \do_step $0\do_step[0:0]
+ end
+ attribute \src "libresoc.v:994.3-1011.6"
+ process $proc$libresoc.v:994$199
+ assign { } { }
+ assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0]
+ attribute \src "libresoc.v:995.5-995.29"
switch \initial
- attribute \src "libresoc.v:997.9-997.17"
+ attribute \src "libresoc.v:995.9-995.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\dmi_read_log_data_1$next[0:0]$197 1'0
- case
- assign $1\dmi_read_log_data_1$next[0:0]$197 \dmi_read_log_data
- end
- sync always
- update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$196
- end
- connect \$9 $and$libresoc.v:719$86_Y
- connect \$99 $eq$libresoc.v:720$87_Y
- connect \$101 $not$libresoc.v:721$88_Y
- connect \$103 $and$libresoc.v:722$89_Y
- connect \$105 $not$libresoc.v:723$90_Y
- connect \$107 $and$libresoc.v:724$91_Y
- connect \$109 $eq$libresoc.v:725$92_Y
- connect \$111 $eq$libresoc.v:726$93_Y
- connect \$113 $eq$libresoc.v:727$94_Y
- connect \$116 $add$libresoc.v:728$95_Y
- connect \$118 $eq$libresoc.v:729$96_Y
- connect \$11 $eq$libresoc.v:730$97_Y
- connect \$120 $and$libresoc.v:731$98_Y
- connect \$122 $not$libresoc.v:732$99_Y
- connect \$124 $and$libresoc.v:733$100_Y
- connect \$13 $eq$libresoc.v:734$101_Y
- connect \$15 $eq$libresoc.v:735$102_Y
- connect \$17 $not$libresoc.v:736$103_Y
- connect \$1 $pos$libresoc.v:737$104_Y
- connect \$19 $and$libresoc.v:738$105_Y
- connect \$21 $not$libresoc.v:739$106_Y
- connect \$23 $and$libresoc.v:740$107_Y
- connect \$25 $eq$libresoc.v:741$108_Y
- connect \$27 $eq$libresoc.v:742$109_Y
- connect \$29 $eq$libresoc.v:743$110_Y
- connect \$31 $not$libresoc.v:744$111_Y
- connect \$33 $and$libresoc.v:745$112_Y
- connect \$35 $not$libresoc.v:746$113_Y
- connect \$37 $and$libresoc.v:747$114_Y
- connect \$3 $not$libresoc.v:748$115_Y
- connect \$39 $eq$libresoc.v:749$116_Y
- connect \$41 $eq$libresoc.v:750$117_Y
- connect \$43 $eq$libresoc.v:751$118_Y
- connect \$45 $not$libresoc.v:752$119_Y
- connect \$47 $and$libresoc.v:753$120_Y
- connect \$49 $not$libresoc.v:754$121_Y
- connect \$51 $and$libresoc.v:755$122_Y
- connect \$53 $eq$libresoc.v:756$123_Y
- connect \$55 $eq$libresoc.v:757$124_Y
- connect \$57 $eq$libresoc.v:758$125_Y
- connect \$5 $and$libresoc.v:759$126_Y
- connect \$59 $not$libresoc.v:760$127_Y
- connect \$61 $and$libresoc.v:761$128_Y
- connect \$63 $not$libresoc.v:762$129_Y
- connect \$65 $and$libresoc.v:763$130_Y
- connect \$67 $eq$libresoc.v:764$131_Y
- connect \$69 $eq$libresoc.v:765$132_Y
- connect \$71 $eq$libresoc.v:766$133_Y
- connect \$73 $not$libresoc.v:767$134_Y
- connect \$75 $and$libresoc.v:768$135_Y
- connect \$77 $not$libresoc.v:769$136_Y
- connect \$7 $not$libresoc.v:770$137_Y
- connect \$79 $and$libresoc.v:771$138_Y
- connect \$81 $eq$libresoc.v:772$139_Y
- connect \$83 $eq$libresoc.v:773$140_Y
- connect \$85 $eq$libresoc.v:774$141_Y
- connect \$87 $not$libresoc.v:775$142_Y
- connect \$89 $and$libresoc.v:776$143_Y
- connect \$91 $not$libresoc.v:777$144_Y
- connect \$93 $and$libresoc.v:778$145_Y
- connect \$95 $eq$libresoc.v:779$146_Y
- connect \$97 $eq$libresoc.v:780$147_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154"
+ switch \dmi_addr_i
+ attribute \src "libresoc.v:0.0-0.0"
+ case 4'0101
+ assign { } { }
+ assign $1\dmi_ack_o[0:0] \d_gpr_ack
+ attribute \src "libresoc.v:0.0-0.0"
+ case 4'1000
+ assign { } { }
+ assign $1\dmi_ack_o[0:0] \d_cr_ack
+ attribute \src "libresoc.v:0.0-0.0"
+ case 4'1001
+ assign { } { }
+ assign $1\dmi_ack_o[0:0] \d_xer_ack
+ attribute \src "libresoc.v:0.0-0.0"
+ case
+ assign { } { }
+ assign $1\dmi_ack_o[0:0] \dmi_req_i
+ end
+ sync always
+ update \dmi_ack_o $0\dmi_ack_o[0:0]
+ end
+ connect \$9 $and$libresoc.v:910$126_Y
+ connect \$99 $eq$libresoc.v:911$127_Y
+ connect \$101 $not$libresoc.v:912$128_Y
+ connect \$103 $and$libresoc.v:913$129_Y
+ connect \$105 $not$libresoc.v:914$130_Y
+ connect \$107 $and$libresoc.v:915$131_Y
+ connect \$109 $eq$libresoc.v:916$132_Y
+ connect \$111 $eq$libresoc.v:917$133_Y
+ connect \$113 $eq$libresoc.v:918$134_Y
+ connect \$116 $add$libresoc.v:919$135_Y
+ connect \$118 $eq$libresoc.v:920$136_Y
+ connect \$11 $eq$libresoc.v:921$137_Y
+ connect \$120 $and$libresoc.v:922$138_Y
+ connect \$122 $not$libresoc.v:923$139_Y
+ connect \$124 $and$libresoc.v:924$140_Y
+ connect \$13 $eq$libresoc.v:925$141_Y
+ connect \$15 $eq$libresoc.v:926$142_Y
+ connect \$17 $not$libresoc.v:927$143_Y
+ connect \$1 $pos$libresoc.v:928$144_Y
+ connect \$19 $and$libresoc.v:929$145_Y
+ connect \$21 $not$libresoc.v:930$146_Y
+ connect \$23 $and$libresoc.v:931$147_Y
+ connect \$25 $eq$libresoc.v:932$148_Y
+ connect \$27 $eq$libresoc.v:933$149_Y
+ connect \$29 $eq$libresoc.v:934$150_Y
+ connect \$31 $not$libresoc.v:935$151_Y
+ connect \$33 $and$libresoc.v:936$152_Y
+ connect \$35 $not$libresoc.v:937$153_Y
+ connect \$37 $and$libresoc.v:938$154_Y
+ connect \$3 $not$libresoc.v:939$155_Y
+ connect \$39 $eq$libresoc.v:940$156_Y
+ connect \$41 $eq$libresoc.v:941$157_Y
+ connect \$43 $eq$libresoc.v:942$158_Y
+ connect \$45 $not$libresoc.v:943$159_Y
+ connect \$47 $and$libresoc.v:944$160_Y
+ connect \$49 $not$libresoc.v:945$161_Y
+ connect \$51 $and$libresoc.v:946$162_Y
+ connect \$53 $eq$libresoc.v:947$163_Y
+ connect \$55 $eq$libresoc.v:948$164_Y
+ connect \$57 $eq$libresoc.v:949$165_Y
+ connect \$5 $and$libresoc.v:950$166_Y
+ connect \$59 $not$libresoc.v:951$167_Y
+ connect \$61 $and$libresoc.v:952$168_Y
+ connect \$63 $not$libresoc.v:953$169_Y
+ connect \$65 $and$libresoc.v:954$170_Y
+ connect \$67 $eq$libresoc.v:955$171_Y
+ connect \$69 $eq$libresoc.v:956$172_Y
+ connect \$71 $eq$libresoc.v:957$173_Y
+ connect \$73 $not$libresoc.v:958$174_Y
+ connect \$75 $and$libresoc.v:959$175_Y
+ connect \$77 $not$libresoc.v:960$176_Y
+ connect \$7 $not$libresoc.v:961$177_Y
+ connect \$79 $and$libresoc.v:962$178_Y
+ connect \$81 $eq$libresoc.v:963$179_Y
+ connect \$83 $eq$libresoc.v:964$180_Y
+ connect \$85 $eq$libresoc.v:965$181_Y
+ connect \$87 $not$libresoc.v:966$182_Y
+ connect \$89 $and$libresoc.v:967$183_Y
+ connect \$91 $not$libresoc.v:968$184_Y
+ connect \$93 $and$libresoc.v:969$185_Y
+ connect \$95 $eq$libresoc.v:970$186_Y
+ connect \$97 $eq$libresoc.v:971$187_Y
connect \$115 \$116
connect \log_write_addr_o 0
connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000
connect \d_gpr_addr \gspr_index
connect \stat_reg \$1
end
-attribute \src "libresoc.v:1202.1-7135.10"
+attribute \src "libresoc.v:1393.1-7326.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec"
attribute \generator "nMigen"
module \dec
- attribute \src "libresoc.v:3396.3-3534.6"
+ attribute \src "libresoc.v:3587.3-3725.6"
wire width 8 $0\asmcode[7:0]
- attribute \src "libresoc.v:5381.3-5522.6"
+ attribute \src "libresoc.v:5572.3-5713.6"
wire $0\br[0:0]
- attribute \src "libresoc.v:4103.3-4244.6"
+ attribute \src "libresoc.v:4294.3-4435.6"
wire width 3 $0\cr_in[2:0]
- attribute \src "libresoc.v:4245.3-4386.6"
+ attribute \src "libresoc.v:4436.3-4577.6"
wire width 3 $0\cr_out[2:0]
- attribute \src "libresoc.v:4813.3-4954.6"
+ attribute \src "libresoc.v:5004.3-5145.6"
wire width 2 $0\cry_in[1:0]
- attribute \src "libresoc.v:5239.3-5380.6"
+ attribute \src "libresoc.v:5430.3-5571.6"
wire $0\cry_out[0:0]
- attribute \src "libresoc.v:6659.3-6800.6"
+ attribute \src "libresoc.v:6850.3-6991.6"
wire width 5 $0\form[4:0]
- attribute \src "libresoc.v:6375.3-6516.6"
+ attribute \src "libresoc.v:6566.3-6707.6"
wire width 12 $0\function_unit[11:0]
- attribute \src "libresoc.v:3535.3-3676.6"
+ attribute \src "libresoc.v:3726.3-3867.6"
wire width 3 $0\in1_sel[2:0]
- attribute \src "libresoc.v:3677.3-3818.6"
+ attribute \src "libresoc.v:3868.3-4009.6"
wire width 4 $0\in2_sel[3:0]
- attribute \src "libresoc.v:3819.3-3960.6"
+ attribute \src "libresoc.v:4010.3-4151.6"
wire width 2 $0\in3_sel[1:0]
- attribute \src "libresoc.v:1203.7-1203.20"
+ attribute \src "libresoc.v:1394.7-1394.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:6517.3-6658.6"
+ attribute \src "libresoc.v:6708.3-6849.6"
wire width 7 $0\internal_op[6:0]
- attribute \src "libresoc.v:4955.3-5096.6"
+ attribute \src "libresoc.v:5146.3-5287.6"
wire $0\inv_a[0:0]
- attribute \src "libresoc.v:5097.3-5238.6"
+ attribute \src "libresoc.v:5288.3-5429.6"
wire $0\inv_out[0:0]
- attribute \src "libresoc.v:5807.3-5948.6"
+ attribute \src "libresoc.v:5998.3-6139.6"
wire $0\is_32b[0:0]
- attribute \src "libresoc.v:4387.3-4528.6"
+ attribute \src "libresoc.v:4578.3-4719.6"
wire width 4 $0\ldst_len[3:0]
- attribute \src "libresoc.v:6091.3-6232.6"
+ attribute \src "libresoc.v:6282.3-6423.6"
wire $0\lk[0:0]
- attribute \src "libresoc.v:3961.3-4102.6"
+ attribute \src "libresoc.v:4152.3-4293.6"
wire width 2 $0\out_sel[1:0]
- attribute \src "libresoc.v:4671.3-4812.6"
+ attribute \src "libresoc.v:4862.3-5003.6"
wire width 2 $0\rc_sel[1:0]
- attribute \src "libresoc.v:5665.3-5806.6"
+ attribute \src "libresoc.v:5856.3-5997.6"
wire $0\rsrv[0:0]
- attribute \src "libresoc.v:6233.3-6374.6"
+ attribute \src "libresoc.v:6424.3-6565.6"
wire $0\sgl_pipe[0:0]
- attribute \src "libresoc.v:5949.3-6090.6"
+ attribute \src "libresoc.v:6140.3-6281.6"
wire $0\sgn[0:0]
- attribute \src "libresoc.v:5523.3-5664.6"
+ attribute \src "libresoc.v:5714.3-5855.6"
wire $0\sgn_ext[0:0]
- attribute \src "libresoc.v:4529.3-4670.6"
+ attribute \src "libresoc.v:4720.3-4861.6"
wire width 2 $0\upd[1:0]
- attribute \src "libresoc.v:3396.3-3534.6"
+ attribute \src "libresoc.v:3587.3-3725.6"
wire width 8 $1\asmcode[7:0]
- attribute \src "libresoc.v:5381.3-5522.6"
+ attribute \src "libresoc.v:5572.3-5713.6"
wire $1\br[0:0]
- attribute \src "libresoc.v:4103.3-4244.6"
+ attribute \src "libresoc.v:4294.3-4435.6"
wire width 3 $1\cr_in[2:0]
- attribute \src "libresoc.v:4245.3-4386.6"
+ attribute \src "libresoc.v:4436.3-4577.6"
wire width 3 $1\cr_out[2:0]
- attribute \src "libresoc.v:4813.3-4954.6"
+ attribute \src "libresoc.v:5004.3-5145.6"
wire width 2 $1\cry_in[1:0]
- attribute \src "libresoc.v:5239.3-5380.6"
+ attribute \src "libresoc.v:5430.3-5571.6"
wire $1\cry_out[0:0]
- attribute \src "libresoc.v:6659.3-6800.6"
+ attribute \src "libresoc.v:6850.3-6991.6"
wire width 5 $1\form[4:0]
- attribute \src "libresoc.v:6375.3-6516.6"
+ attribute \src "libresoc.v:6566.3-6707.6"
wire width 12 $1\function_unit[11:0]
- attribute \src "libresoc.v:3535.3-3676.6"
+ attribute \src "libresoc.v:3726.3-3867.6"
wire width 3 $1\in1_sel[2:0]
- attribute \src "libresoc.v:3677.3-3818.6"
+ attribute \src "libresoc.v:3868.3-4009.6"
wire width 4 $1\in2_sel[3:0]
- attribute \src "libresoc.v:3819.3-3960.6"
+ attribute \src "libresoc.v:4010.3-4151.6"
wire width 2 $1\in3_sel[1:0]
- attribute \src "libresoc.v:6517.3-6658.6"
+ attribute \src "libresoc.v:6708.3-6849.6"
wire width 7 $1\internal_op[6:0]
- attribute \src "libresoc.v:4955.3-5096.6"
+ attribute \src "libresoc.v:5146.3-5287.6"
wire $1\inv_a[0:0]
- attribute \src "libresoc.v:5097.3-5238.6"
+ attribute \src "libresoc.v:5288.3-5429.6"
wire $1\inv_out[0:0]
- attribute \src "libresoc.v:5807.3-5948.6"
+ attribute \src "libresoc.v:5998.3-6139.6"
wire $1\is_32b[0:0]
- attribute \src "libresoc.v:4387.3-4528.6"
+ attribute \src "libresoc.v:4578.3-4719.6"
wire width 4 $1\ldst_len[3:0]
- attribute \src "libresoc.v:6091.3-6232.6"
+ attribute \src "libresoc.v:6282.3-6423.6"
wire $1\lk[0:0]
- attribute \src "libresoc.v:3961.3-4102.6"
+ attribute \src "libresoc.v:4152.3-4293.6"
wire width 2 $1\out_sel[1:0]
- attribute \src "libresoc.v:4671.3-4812.6"
+ attribute \src "libresoc.v:4862.3-5003.6"
wire width 2 $1\rc_sel[1:0]
- attribute \src "libresoc.v:5665.3-5806.6"
+ attribute \src "libresoc.v:5856.3-5997.6"
wire $1\rsrv[0:0]
- attribute \src "libresoc.v:6233.3-6374.6"
+ attribute \src "libresoc.v:6424.3-6565.6"
wire $1\sgl_pipe[0:0]
- attribute \src "libresoc.v:5949.3-6090.6"
+ attribute \src "libresoc.v:6140.3-6281.6"
wire $1\sgn[0:0]
- attribute \src "libresoc.v:5523.3-5664.6"
+ attribute \src "libresoc.v:5714.3-5855.6"
wire $1\sgn_ext[0:0]
- attribute \src "libresoc.v:4529.3-4670.6"
+ attribute \src "libresoc.v:4720.3-4861.6"
wire width 2 $1\upd[1:0]
- attribute \src "libresoc.v:3396.3-3534.6"
+ attribute \src "libresoc.v:3587.3-3725.6"
wire width 8 $2\asmcode[7:0]
- attribute \src "libresoc.v:5381.3-5522.6"
+ attribute \src "libresoc.v:5572.3-5713.6"
wire $2\br[0:0]
- attribute \src "libresoc.v:4103.3-4244.6"
+ attribute \src "libresoc.v:4294.3-4435.6"
wire width 3 $2\cr_in[2:0]
- attribute \src "libresoc.v:4245.3-4386.6"
+ attribute \src "libresoc.v:4436.3-4577.6"
wire width 3 $2\cr_out[2:0]
- attribute \src "libresoc.v:4813.3-4954.6"
+ attribute \src "libresoc.v:5004.3-5145.6"
wire width 2 $2\cry_in[1:0]
- attribute \src "libresoc.v:5239.3-5380.6"
+ attribute \src "libresoc.v:5430.3-5571.6"
wire $2\cry_out[0:0]
- attribute \src "libresoc.v:6659.3-6800.6"
+ attribute \src "libresoc.v:6850.3-6991.6"
wire width 5 $2\form[4:0]
- attribute \src "libresoc.v:6375.3-6516.6"
+ attribute \src "libresoc.v:6566.3-6707.6"
wire width 12 $2\function_unit[11:0]
- attribute \src "libresoc.v:3535.3-3676.6"
+ attribute \src "libresoc.v:3726.3-3867.6"
wire width 3 $2\in1_sel[2:0]
- attribute \src "libresoc.v:3677.3-3818.6"
+ attribute \src "libresoc.v:3868.3-4009.6"
wire width 4 $2\in2_sel[3:0]
- attribute \src "libresoc.v:3819.3-3960.6"
+ attribute \src "libresoc.v:4010.3-4151.6"
wire width 2 $2\in3_sel[1:0]
- attribute \src "libresoc.v:6517.3-6658.6"
+ attribute \src "libresoc.v:6708.3-6849.6"
wire width 7 $2\internal_op[6:0]
- attribute \src "libresoc.v:4955.3-5096.6"
+ attribute \src "libresoc.v:5146.3-5287.6"
wire $2\inv_a[0:0]
- attribute \src "libresoc.v:5097.3-5238.6"
+ attribute \src "libresoc.v:5288.3-5429.6"
wire $2\inv_out[0:0]
- attribute \src "libresoc.v:5807.3-5948.6"
+ attribute \src "libresoc.v:5998.3-6139.6"
wire $2\is_32b[0:0]
- attribute \src "libresoc.v:4387.3-4528.6"
+ attribute \src "libresoc.v:4578.3-4719.6"
wire width 4 $2\ldst_len[3:0]
- attribute \src "libresoc.v:6091.3-6232.6"
+ attribute \src "libresoc.v:6282.3-6423.6"
wire $2\lk[0:0]
- attribute \src "libresoc.v:3961.3-4102.6"
+ attribute \src "libresoc.v:4152.3-4293.6"
wire width 2 $2\out_sel[1:0]
- attribute \src "libresoc.v:4671.3-4812.6"
+ attribute \src "libresoc.v:4862.3-5003.6"
wire width 2 $2\rc_sel[1:0]
- attribute \src "libresoc.v:5665.3-5806.6"
+ attribute \src "libresoc.v:5856.3-5997.6"
wire $2\rsrv[0:0]
- attribute \src "libresoc.v:6233.3-6374.6"
+ attribute \src "libresoc.v:6424.3-6565.6"
wire $2\sgl_pipe[0:0]
- attribute \src "libresoc.v:5949.3-6090.6"
+ attribute \src "libresoc.v:6140.3-6281.6"
wire $2\sgn[0:0]
- attribute \src "libresoc.v:5523.3-5664.6"
+ attribute \src "libresoc.v:5714.3-5855.6"
wire $2\sgn_ext[0:0]
- attribute \src "libresoc.v:4529.3-4670.6"
+ attribute \src "libresoc.v:4720.3-4861.6"
wire width 2 $2\upd[1:0]
- attribute \src "libresoc.v:3260.17-3260.211"
- wire width 32 $ternary$libresoc.v:3260$243_Y
+ attribute \src "libresoc.v:3451.17-3451.211"
+ wire width 32 $ternary$libresoc.v:3451$283_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478"
wire width 32 \$2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447"
attribute \enum_value_10 "RB"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 14 \in3_sel
- attribute \src "libresoc.v:1203.7-1203.15"
+ attribute \src "libresoc.v:1394.7-1394.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 17 \upd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478"
- cell $mux $ternary$libresoc.v:3260$243
+ cell $mux $ternary$libresoc.v:3451$283
parameter \WIDTH 32
connect \A \raw_opcode_in
connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
- connect \Y $ternary$libresoc.v:3260$243_Y
+ connect \Y $ternary$libresoc.v:3451$283_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:3261.9-3287.4"
+ attribute \src "libresoc.v:3452.9-3478.4"
cell \dec19 \dec19
connect \dec19_asmcode \dec19_dec19_asmcode
connect \dec19_br \dec19_dec19_br
connect \opcode_in \dec19_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:3288.9-3314.4"
+ attribute \src "libresoc.v:3479.9-3505.4"
cell \dec30 \dec30
connect \dec30_asmcode \dec30_dec30_asmcode
connect \dec30_br \dec30_dec30_br
connect \opcode_in \dec30_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:3315.9-3341.4"
+ attribute \src "libresoc.v:3506.9-3532.4"
cell \dec31 \dec31
connect \dec31_asmcode \dec31_dec31_asmcode
connect \dec31_br \dec31_dec31_br
connect \opcode_in \dec31_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:3342.9-3368.4"
+ attribute \src "libresoc.v:3533.9-3559.4"
cell \dec58 \dec58
connect \dec58_asmcode \dec58_dec58_asmcode
connect \dec58_br \dec58_dec58_br
connect \opcode_in \dec58_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:3369.9-3395.4"
+ attribute \src "libresoc.v:3560.9-3586.4"
cell \dec62 \dec62
connect \dec62_asmcode \dec62_dec62_asmcode
connect \dec62_br \dec62_dec62_br
connect \dec62_upd \dec62_dec62_upd
connect \opcode_in \dec62_opcode_in
end
- attribute \src "libresoc.v:1203.7-1203.20"
- process $proc$libresoc.v:1203$268
+ attribute \src "libresoc.v:1394.7-1394.20"
+ process $proc$libresoc.v:1394$308
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:3396.3-3534.6"
- process $proc$libresoc.v:3396$244
+ attribute \src "libresoc.v:3587.3-3725.6"
+ process $proc$libresoc.v:3587$284
assign { } { }
assign { } { }
assign { } { }
assign $0\asmcode[7:0] $2\asmcode[7:0]
- attribute \src "libresoc.v:3397.5-3397.29"
+ attribute \src "libresoc.v:3588.5-3588.29"
switch \initial
- attribute \src "libresoc.v:3397.9-3397.17"
+ attribute \src "libresoc.v:3588.9-3588.17"
case 1'1
case
end
sync always
update \asmcode $0\asmcode[7:0]
end
- attribute \src "libresoc.v:3535.3-3676.6"
- process $proc$libresoc.v:3535$245
+ attribute \src "libresoc.v:3726.3-3867.6"
+ process $proc$libresoc.v:3726$285
assign { } { }
assign { } { }
assign { } { }
assign $0\in1_sel[2:0] $2\in1_sel[2:0]
- attribute \src "libresoc.v:3536.5-3536.29"
+ attribute \src "libresoc.v:3727.5-3727.29"
switch \initial
- attribute \src "libresoc.v:3536.9-3536.17"
+ attribute \src "libresoc.v:3727.9-3727.17"
case 1'1
case
end
sync always
update \in1_sel $0\in1_sel[2:0]
end
- attribute \src "libresoc.v:3677.3-3818.6"
- process $proc$libresoc.v:3677$246
+ attribute \src "libresoc.v:3868.3-4009.6"
+ process $proc$libresoc.v:3868$286
assign { } { }
assign { } { }
assign { } { }
assign $0\in2_sel[3:0] $2\in2_sel[3:0]
- attribute \src "libresoc.v:3678.5-3678.29"
+ attribute \src "libresoc.v:3869.5-3869.29"
switch \initial
- attribute \src "libresoc.v:3678.9-3678.17"
+ attribute \src "libresoc.v:3869.9-3869.17"
case 1'1
case
end
sync always
update \in2_sel $0\in2_sel[3:0]
end
- attribute \src "libresoc.v:3819.3-3960.6"
- process $proc$libresoc.v:3819$247
+ attribute \src "libresoc.v:4010.3-4151.6"
+ process $proc$libresoc.v:4010$287
assign { } { }
assign { } { }
assign { } { }
assign $0\in3_sel[1:0] $2\in3_sel[1:0]
- attribute \src "libresoc.v:3820.5-3820.29"
+ attribute \src "libresoc.v:4011.5-4011.29"
switch \initial
- attribute \src "libresoc.v:3820.9-3820.17"
+ attribute \src "libresoc.v:4011.9-4011.17"
case 1'1
case
end
sync always
update \in3_sel $0\in3_sel[1:0]
end
- attribute \src "libresoc.v:3961.3-4102.6"
- process $proc$libresoc.v:3961$248
+ attribute \src "libresoc.v:4152.3-4293.6"
+ process $proc$libresoc.v:4152$288
assign { } { }
assign { } { }
assign { } { }
assign $0\out_sel[1:0] $2\out_sel[1:0]
- attribute \src "libresoc.v:3962.5-3962.29"
+ attribute \src "libresoc.v:4153.5-4153.29"
switch \initial
- attribute \src "libresoc.v:3962.9-3962.17"
+ attribute \src "libresoc.v:4153.9-4153.17"
case 1'1
case
end
sync always
update \out_sel $0\out_sel[1:0]
end
- attribute \src "libresoc.v:4103.3-4244.6"
- process $proc$libresoc.v:4103$249
+ attribute \src "libresoc.v:4294.3-4435.6"
+ process $proc$libresoc.v:4294$289
assign { } { }
assign { } { }
assign { } { }
assign $0\cr_in[2:0] $2\cr_in[2:0]
- attribute \src "libresoc.v:4104.5-4104.29"
+ attribute \src "libresoc.v:4295.5-4295.29"
switch \initial
- attribute \src "libresoc.v:4104.9-4104.17"
+ attribute \src "libresoc.v:4295.9-4295.17"
case 1'1
case
end
sync always
update \cr_in $0\cr_in[2:0]
end
- attribute \src "libresoc.v:4245.3-4386.6"
- process $proc$libresoc.v:4245$250
+ attribute \src "libresoc.v:4436.3-4577.6"
+ process $proc$libresoc.v:4436$290
assign { } { }
assign { } { }
assign { } { }
assign $0\cr_out[2:0] $2\cr_out[2:0]
- attribute \src "libresoc.v:4246.5-4246.29"
+ attribute \src "libresoc.v:4437.5-4437.29"
switch \initial
- attribute \src "libresoc.v:4246.9-4246.17"
+ attribute \src "libresoc.v:4437.9-4437.17"
case 1'1
case
end
sync always
update \cr_out $0\cr_out[2:0]
end
- attribute \src "libresoc.v:4387.3-4528.6"
- process $proc$libresoc.v:4387$251
+ attribute \src "libresoc.v:4578.3-4719.6"
+ process $proc$libresoc.v:4578$291
assign { } { }
assign { } { }
assign { } { }
assign $0\ldst_len[3:0] $2\ldst_len[3:0]
- attribute \src "libresoc.v:4388.5-4388.29"
+ attribute \src "libresoc.v:4579.5-4579.29"
switch \initial
- attribute \src "libresoc.v:4388.9-4388.17"
+ attribute \src "libresoc.v:4579.9-4579.17"
case 1'1
case
end
sync always
update \ldst_len $0\ldst_len[3:0]
end
- attribute \src "libresoc.v:4529.3-4670.6"
- process $proc$libresoc.v:4529$252
+ attribute \src "libresoc.v:4720.3-4861.6"
+ process $proc$libresoc.v:4720$292
assign { } { }
assign { } { }
assign { } { }
assign $0\upd[1:0] $2\upd[1:0]
- attribute \src "libresoc.v:4530.5-4530.29"
+ attribute \src "libresoc.v:4721.5-4721.29"
switch \initial
- attribute \src "libresoc.v:4530.9-4530.17"
+ attribute \src "libresoc.v:4721.9-4721.17"
case 1'1
case
end
sync always
update \upd $0\upd[1:0]
end
- attribute \src "libresoc.v:4671.3-4812.6"
- process $proc$libresoc.v:4671$253
+ attribute \src "libresoc.v:4862.3-5003.6"
+ process $proc$libresoc.v:4862$293
assign { } { }
assign { } { }
assign { } { }
assign $0\rc_sel[1:0] $2\rc_sel[1:0]
- attribute \src "libresoc.v:4672.5-4672.29"
+ attribute \src "libresoc.v:4863.5-4863.29"
switch \initial
- attribute \src "libresoc.v:4672.9-4672.17"
+ attribute \src "libresoc.v:4863.9-4863.17"
case 1'1
case
end
sync always
update \rc_sel $0\rc_sel[1:0]
end
- attribute \src "libresoc.v:4813.3-4954.6"
- process $proc$libresoc.v:4813$254
+ attribute \src "libresoc.v:5004.3-5145.6"
+ process $proc$libresoc.v:5004$294
assign { } { }
assign { } { }
assign { } { }
assign $0\cry_in[1:0] $2\cry_in[1:0]
- attribute \src "libresoc.v:4814.5-4814.29"
+ attribute \src "libresoc.v:5005.5-5005.29"
switch \initial
- attribute \src "libresoc.v:4814.9-4814.17"
+ attribute \src "libresoc.v:5005.9-5005.17"
case 1'1
case
end
sync always
update \cry_in $0\cry_in[1:0]
end
- attribute \src "libresoc.v:4955.3-5096.6"
- process $proc$libresoc.v:4955$255
+ attribute \src "libresoc.v:5146.3-5287.6"
+ process $proc$libresoc.v:5146$295
assign { } { }
assign { } { }
assign { } { }
assign $0\inv_a[0:0] $2\inv_a[0:0]
- attribute \src "libresoc.v:4956.5-4956.29"
+ attribute \src "libresoc.v:5147.5-5147.29"
switch \initial
- attribute \src "libresoc.v:4956.9-4956.17"
+ attribute \src "libresoc.v:5147.9-5147.17"
case 1'1
case
end
sync always
update \inv_a $0\inv_a[0:0]
end
- attribute \src "libresoc.v:5097.3-5238.6"
- process $proc$libresoc.v:5097$256
+ attribute \src "libresoc.v:5288.3-5429.6"
+ process $proc$libresoc.v:5288$296
assign { } { }
assign { } { }
assign { } { }
assign $0\inv_out[0:0] $2\inv_out[0:0]
- attribute \src "libresoc.v:5098.5-5098.29"
+ attribute \src "libresoc.v:5289.5-5289.29"
switch \initial
- attribute \src "libresoc.v:5098.9-5098.17"
+ attribute \src "libresoc.v:5289.9-5289.17"
case 1'1
case
end
sync always
update \inv_out $0\inv_out[0:0]
end
- attribute \src "libresoc.v:5239.3-5380.6"
- process $proc$libresoc.v:5239$257
+ attribute \src "libresoc.v:5430.3-5571.6"
+ process $proc$libresoc.v:5430$297
assign { } { }
assign { } { }
assign { } { }
assign $0\cry_out[0:0] $2\cry_out[0:0]
- attribute \src "libresoc.v:5240.5-5240.29"
+ attribute \src "libresoc.v:5431.5-5431.29"
switch \initial
- attribute \src "libresoc.v:5240.9-5240.17"
+ attribute \src "libresoc.v:5431.9-5431.17"
case 1'1
case
end
sync always
update \cry_out $0\cry_out[0:0]
end
- attribute \src "libresoc.v:5381.3-5522.6"
- process $proc$libresoc.v:5381$258
+ attribute \src "libresoc.v:5572.3-5713.6"
+ process $proc$libresoc.v:5572$298
assign { } { }
assign { } { }
assign { } { }
assign $0\br[0:0] $2\br[0:0]
- attribute \src "libresoc.v:5382.5-5382.29"
+ attribute \src "libresoc.v:5573.5-5573.29"
switch \initial
- attribute \src "libresoc.v:5382.9-5382.17"
+ attribute \src "libresoc.v:5573.9-5573.17"
case 1'1
case
end
sync always
update \br $0\br[0:0]
end
- attribute \src "libresoc.v:5523.3-5664.6"
- process $proc$libresoc.v:5523$259
+ attribute \src "libresoc.v:5714.3-5855.6"
+ process $proc$libresoc.v:5714$299
assign { } { }
assign { } { }
assign { } { }
assign $0\sgn_ext[0:0] $2\sgn_ext[0:0]
- attribute \src "libresoc.v:5524.5-5524.29"
+ attribute \src "libresoc.v:5715.5-5715.29"
switch \initial
- attribute \src "libresoc.v:5524.9-5524.17"
+ attribute \src "libresoc.v:5715.9-5715.17"
case 1'1
case
end
sync always
update \sgn_ext $0\sgn_ext[0:0]
end
- attribute \src "libresoc.v:5665.3-5806.6"
- process $proc$libresoc.v:5665$260
+ attribute \src "libresoc.v:5856.3-5997.6"
+ process $proc$libresoc.v:5856$300
assign { } { }
assign { } { }
assign { } { }
assign $0\rsrv[0:0] $2\rsrv[0:0]
- attribute \src "libresoc.v:5666.5-5666.29"
+ attribute \src "libresoc.v:5857.5-5857.29"
switch \initial
- attribute \src "libresoc.v:5666.9-5666.17"
+ attribute \src "libresoc.v:5857.9-5857.17"
case 1'1
case
end
sync always
update \rsrv $0\rsrv[0:0]
end
- attribute \src "libresoc.v:5807.3-5948.6"
- process $proc$libresoc.v:5807$261
+ attribute \src "libresoc.v:5998.3-6139.6"
+ process $proc$libresoc.v:5998$301
assign { } { }
assign { } { }
assign { } { }
assign $0\is_32b[0:0] $2\is_32b[0:0]
- attribute \src "libresoc.v:5808.5-5808.29"
+ attribute \src "libresoc.v:5999.5-5999.29"
switch \initial
- attribute \src "libresoc.v:5808.9-5808.17"
+ attribute \src "libresoc.v:5999.9-5999.17"
case 1'1
case
end
sync always
update \is_32b $0\is_32b[0:0]
end
- attribute \src "libresoc.v:5949.3-6090.6"
- process $proc$libresoc.v:5949$262
+ attribute \src "libresoc.v:6140.3-6281.6"
+ process $proc$libresoc.v:6140$302
assign { } { }
assign { } { }
assign { } { }
assign $0\sgn[0:0] $2\sgn[0:0]
- attribute \src "libresoc.v:5950.5-5950.29"
+ attribute \src "libresoc.v:6141.5-6141.29"
switch \initial
- attribute \src "libresoc.v:5950.9-5950.17"
+ attribute \src "libresoc.v:6141.9-6141.17"
case 1'1
case
end
sync always
update \sgn $0\sgn[0:0]
end
- attribute \src "libresoc.v:6091.3-6232.6"
- process $proc$libresoc.v:6091$263
+ attribute \src "libresoc.v:6282.3-6423.6"
+ process $proc$libresoc.v:6282$303
assign { } { }
assign { } { }
assign { } { }
assign $0\lk[0:0] $2\lk[0:0]
- attribute \src "libresoc.v:6092.5-6092.29"
+ attribute \src "libresoc.v:6283.5-6283.29"
switch \initial
- attribute \src "libresoc.v:6092.9-6092.17"
+ attribute \src "libresoc.v:6283.9-6283.17"
case 1'1
case
end
sync always
update \lk $0\lk[0:0]
end
- attribute \src "libresoc.v:6233.3-6374.6"
- process $proc$libresoc.v:6233$264
+ attribute \src "libresoc.v:6424.3-6565.6"
+ process $proc$libresoc.v:6424$304
assign { } { }
assign { } { }
assign { } { }
assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0]
- attribute \src "libresoc.v:6234.5-6234.29"
+ attribute \src "libresoc.v:6425.5-6425.29"
switch \initial
- attribute \src "libresoc.v:6234.9-6234.17"
+ attribute \src "libresoc.v:6425.9-6425.17"
case 1'1
case
end
sync always
update \sgl_pipe $0\sgl_pipe[0:0]
end
- attribute \src "libresoc.v:6375.3-6516.6"
- process $proc$libresoc.v:6375$265
+ attribute \src "libresoc.v:6566.3-6707.6"
+ process $proc$libresoc.v:6566$305
assign { } { }
assign { } { }
assign { } { }
assign $0\function_unit[11:0] $2\function_unit[11:0]
- attribute \src "libresoc.v:6376.5-6376.29"
+ attribute \src "libresoc.v:6567.5-6567.29"
switch \initial
- attribute \src "libresoc.v:6376.9-6376.17"
+ attribute \src "libresoc.v:6567.9-6567.17"
case 1'1
case
end
sync always
update \function_unit $0\function_unit[11:0]
end
- attribute \src "libresoc.v:6517.3-6658.6"
- process $proc$libresoc.v:6517$266
+ attribute \src "libresoc.v:6708.3-6849.6"
+ process $proc$libresoc.v:6708$306
assign { } { }
assign { } { }
assign { } { }
assign $0\internal_op[6:0] $2\internal_op[6:0]
- attribute \src "libresoc.v:6518.5-6518.29"
+ attribute \src "libresoc.v:6709.5-6709.29"
switch \initial
- attribute \src "libresoc.v:6518.9-6518.17"
+ attribute \src "libresoc.v:6709.9-6709.17"
case 1'1
case
end
sync always
update \internal_op $0\internal_op[6:0]
end
- attribute \src "libresoc.v:6659.3-6800.6"
- process $proc$libresoc.v:6659$267
+ attribute \src "libresoc.v:6850.3-6991.6"
+ process $proc$libresoc.v:6850$307
assign { } { }
assign { } { }
assign { } { }
assign $0\form[4:0] $2\form[4:0]
- attribute \src "libresoc.v:6660.5-6660.29"
+ attribute \src "libresoc.v:6851.5-6851.29"
switch \initial
- attribute \src "libresoc.v:6660.9-6660.17"
+ attribute \src "libresoc.v:6851.9-6851.17"
case 1'1
case
end
sync always
update \form $0\form[4:0]
end
- connect \$2 $ternary$libresoc.v:3260$243_Y
+ connect \$2 $ternary$libresoc.v:3451$283_Y
connect \VC_XO \opcode_in [9:0]
connect \VC_VRT \opcode_in [25:21]
connect \VC_VRB \opcode_in [15:11]
connect \dec19_opcode_in \opcode_in
connect \opcode_switch \opcode_in [31:26]
end
-attribute \src "libresoc.v:7139.1-8646.10"
+attribute \src "libresoc.v:7330.1-8837.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec19"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19"
attribute \generator "nMigen"
module \dec19
- attribute \src "libresoc.v:7657.3-7708.6"
+ attribute \src "libresoc.v:7848.3-7899.6"
wire width 8 $0\dec19_asmcode[7:0]
- attribute \src "libresoc.v:7865.3-7916.6"
+ attribute \src "libresoc.v:8056.3-8107.6"
wire $0\dec19_br[0:0]
- attribute \src "libresoc.v:8541.3-8592.6"
+ attribute \src "libresoc.v:8732.3-8783.6"
wire width 3 $0\dec19_cr_in[2:0]
- attribute \src "libresoc.v:8593.3-8644.6"
+ attribute \src "libresoc.v:8784.3-8835.6"
wire width 3 $0\dec19_cr_out[2:0]
- attribute \src "libresoc.v:7605.3-7656.6"
+ attribute \src "libresoc.v:7796.3-7847.6"
wire width 2 $0\dec19_cry_in[1:0]
- attribute \src "libresoc.v:7813.3-7864.6"
+ attribute \src "libresoc.v:8004.3-8055.6"
wire $0\dec19_cry_out[0:0]
- attribute \src "libresoc.v:8281.3-8332.6"
+ attribute \src "libresoc.v:8472.3-8523.6"
wire width 5 $0\dec19_form[4:0]
- attribute \src "libresoc.v:7397.3-7448.6"
+ attribute \src "libresoc.v:7588.3-7639.6"
wire width 12 $0\dec19_function_unit[11:0]
- attribute \src "libresoc.v:8333.3-8384.6"
+ attribute \src "libresoc.v:8524.3-8575.6"
wire width 3 $0\dec19_in1_sel[2:0]
- attribute \src "libresoc.v:8385.3-8436.6"
+ attribute \src "libresoc.v:8576.3-8627.6"
wire width 4 $0\dec19_in2_sel[3:0]
- attribute \src "libresoc.v:8437.3-8488.6"
+ attribute \src "libresoc.v:8628.3-8679.6"
wire width 2 $0\dec19_in3_sel[1:0]
- attribute \src "libresoc.v:7969.3-8020.6"
+ attribute \src "libresoc.v:8160.3-8211.6"
wire width 7 $0\dec19_internal_op[6:0]
- attribute \src "libresoc.v:7709.3-7760.6"
+ attribute \src "libresoc.v:7900.3-7951.6"
wire $0\dec19_inv_a[0:0]
- attribute \src "libresoc.v:7761.3-7812.6"
+ attribute \src "libresoc.v:7952.3-8003.6"
wire $0\dec19_inv_out[0:0]
- attribute \src "libresoc.v:8073.3-8124.6"
+ attribute \src "libresoc.v:8264.3-8315.6"
wire $0\dec19_is_32b[0:0]
- attribute \src "libresoc.v:7449.3-7500.6"
+ attribute \src "libresoc.v:7640.3-7691.6"
wire width 4 $0\dec19_ldst_len[3:0]
- attribute \src "libresoc.v:8177.3-8228.6"
+ attribute \src "libresoc.v:8368.3-8419.6"
wire $0\dec19_lk[0:0]
- attribute \src "libresoc.v:8489.3-8540.6"
+ attribute \src "libresoc.v:8680.3-8731.6"
wire width 2 $0\dec19_out_sel[1:0]
- attribute \src "libresoc.v:7553.3-7604.6"
+ attribute \src "libresoc.v:7744.3-7795.6"
wire width 2 $0\dec19_rc_sel[1:0]
- attribute \src "libresoc.v:8021.3-8072.6"
+ attribute \src "libresoc.v:8212.3-8263.6"
wire $0\dec19_rsrv[0:0]
- attribute \src "libresoc.v:8229.3-8280.6"
+ attribute \src "libresoc.v:8420.3-8471.6"
wire $0\dec19_sgl_pipe[0:0]
- attribute \src "libresoc.v:8125.3-8176.6"
+ attribute \src "libresoc.v:8316.3-8367.6"
wire $0\dec19_sgn[0:0]
- attribute \src "libresoc.v:7917.3-7968.6"
+ attribute \src "libresoc.v:8108.3-8159.6"
wire $0\dec19_sgn_ext[0:0]
- attribute \src "libresoc.v:7501.3-7552.6"
+ attribute \src "libresoc.v:7692.3-7743.6"
wire width 2 $0\dec19_upd[1:0]
- attribute \src "libresoc.v:7140.7-7140.20"
+ attribute \src "libresoc.v:7331.7-7331.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:7657.3-7708.6"
+ attribute \src "libresoc.v:7848.3-7899.6"
wire width 8 $1\dec19_asmcode[7:0]
- attribute \src "libresoc.v:7865.3-7916.6"
+ attribute \src "libresoc.v:8056.3-8107.6"
wire $1\dec19_br[0:0]
- attribute \src "libresoc.v:8541.3-8592.6"
+ attribute \src "libresoc.v:8732.3-8783.6"
wire width 3 $1\dec19_cr_in[2:0]
- attribute \src "libresoc.v:8593.3-8644.6"
+ attribute \src "libresoc.v:8784.3-8835.6"
wire width 3 $1\dec19_cr_out[2:0]
- attribute \src "libresoc.v:7605.3-7656.6"
+ attribute \src "libresoc.v:7796.3-7847.6"
wire width 2 $1\dec19_cry_in[1:0]
- attribute \src "libresoc.v:7813.3-7864.6"
+ attribute \src "libresoc.v:8004.3-8055.6"
wire $1\dec19_cry_out[0:0]
- attribute \src "libresoc.v:8281.3-8332.6"
+ attribute \src "libresoc.v:8472.3-8523.6"
wire width 5 $1\dec19_form[4:0]
- attribute \src "libresoc.v:7397.3-7448.6"
+ attribute \src "libresoc.v:7588.3-7639.6"
wire width 12 $1\dec19_function_unit[11:0]
- attribute \src "libresoc.v:8333.3-8384.6"
+ attribute \src "libresoc.v:8524.3-8575.6"
wire width 3 $1\dec19_in1_sel[2:0]
- attribute \src "libresoc.v:8385.3-8436.6"
+ attribute \src "libresoc.v:8576.3-8627.6"
wire width 4 $1\dec19_in2_sel[3:0]
- attribute \src "libresoc.v:8437.3-8488.6"
+ attribute \src "libresoc.v:8628.3-8679.6"
wire width 2 $1\dec19_in3_sel[1:0]
- attribute \src "libresoc.v:7969.3-8020.6"
+ attribute \src "libresoc.v:8160.3-8211.6"
wire width 7 $1\dec19_internal_op[6:0]
- attribute \src "libresoc.v:7709.3-7760.6"
+ attribute \src "libresoc.v:7900.3-7951.6"
wire $1\dec19_inv_a[0:0]
- attribute \src "libresoc.v:7761.3-7812.6"
+ attribute \src "libresoc.v:7952.3-8003.6"
wire $1\dec19_inv_out[0:0]
- attribute \src "libresoc.v:8073.3-8124.6"
+ attribute \src "libresoc.v:8264.3-8315.6"
wire $1\dec19_is_32b[0:0]
- attribute \src "libresoc.v:7449.3-7500.6"
+ attribute \src "libresoc.v:7640.3-7691.6"
wire width 4 $1\dec19_ldst_len[3:0]
- attribute \src "libresoc.v:8177.3-8228.6"
+ attribute \src "libresoc.v:8368.3-8419.6"
wire $1\dec19_lk[0:0]
- attribute \src "libresoc.v:8489.3-8540.6"
+ attribute \src "libresoc.v:8680.3-8731.6"
wire width 2 $1\dec19_out_sel[1:0]
- attribute \src "libresoc.v:7553.3-7604.6"
+ attribute \src "libresoc.v:7744.3-7795.6"
wire width 2 $1\dec19_rc_sel[1:0]
- attribute \src "libresoc.v:8021.3-8072.6"
+ attribute \src "libresoc.v:8212.3-8263.6"
wire $1\dec19_rsrv[0:0]
- attribute \src "libresoc.v:8229.3-8280.6"
+ attribute \src "libresoc.v:8420.3-8471.6"
wire $1\dec19_sgl_pipe[0:0]
- attribute \src "libresoc.v:8125.3-8176.6"
+ attribute \src "libresoc.v:8316.3-8367.6"
wire $1\dec19_sgn[0:0]
- attribute \src "libresoc.v:7917.3-7968.6"
+ attribute \src "libresoc.v:8108.3-8159.6"
wire $1\dec19_sgn_ext[0:0]
- attribute \src "libresoc.v:7501.3-7552.6"
+ attribute \src "libresoc.v:7692.3-7743.6"
wire width 2 $1\dec19_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec19_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec19_upd
- attribute \src "libresoc.v:7140.7-7140.15"
+ attribute \src "libresoc.v:7331.7-7331.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 10 \opcode_switch
- attribute \src "libresoc.v:7140.7-7140.20"
- process $proc$libresoc.v:7140$293
+ attribute \src "libresoc.v:7331.7-7331.20"
+ process $proc$libresoc.v:7331$333
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:7397.3-7448.6"
- process $proc$libresoc.v:7397$269
+ attribute \src "libresoc.v:7588.3-7639.6"
+ process $proc$libresoc.v:7588$309
assign { } { }
assign { } { }
assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0]
- attribute \src "libresoc.v:7398.5-7398.29"
+ attribute \src "libresoc.v:7589.5-7589.29"
switch \initial
- attribute \src "libresoc.v:7398.9-7398.17"
+ attribute \src "libresoc.v:7589.9-7589.17"
case 1'1
case
end
sync always
update \dec19_function_unit $0\dec19_function_unit[11:0]
end
- attribute \src "libresoc.v:7449.3-7500.6"
- process $proc$libresoc.v:7449$270
+ attribute \src "libresoc.v:7640.3-7691.6"
+ process $proc$libresoc.v:7640$310
assign { } { }
assign { } { }
assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0]
- attribute \src "libresoc.v:7450.5-7450.29"
+ attribute \src "libresoc.v:7641.5-7641.29"
switch \initial
- attribute \src "libresoc.v:7450.9-7450.17"
+ attribute \src "libresoc.v:7641.9-7641.17"
case 1'1
case
end
sync always
update \dec19_ldst_len $0\dec19_ldst_len[3:0]
end
- attribute \src "libresoc.v:7501.3-7552.6"
- process $proc$libresoc.v:7501$271
+ attribute \src "libresoc.v:7692.3-7743.6"
+ process $proc$libresoc.v:7692$311
assign { } { }
assign { } { }
assign $0\dec19_upd[1:0] $1\dec19_upd[1:0]
- attribute \src "libresoc.v:7502.5-7502.29"
+ attribute \src "libresoc.v:7693.5-7693.29"
switch \initial
- attribute \src "libresoc.v:7502.9-7502.17"
+ attribute \src "libresoc.v:7693.9-7693.17"
case 1'1
case
end
sync always
update \dec19_upd $0\dec19_upd[1:0]
end
- attribute \src "libresoc.v:7553.3-7604.6"
- process $proc$libresoc.v:7553$272
+ attribute \src "libresoc.v:7744.3-7795.6"
+ process $proc$libresoc.v:7744$312
assign { } { }
assign { } { }
assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0]
- attribute \src "libresoc.v:7554.5-7554.29"
+ attribute \src "libresoc.v:7745.5-7745.29"
switch \initial
- attribute \src "libresoc.v:7554.9-7554.17"
+ attribute \src "libresoc.v:7745.9-7745.17"
case 1'1
case
end
sync always
update \dec19_rc_sel $0\dec19_rc_sel[1:0]
end
- attribute \src "libresoc.v:7605.3-7656.6"
- process $proc$libresoc.v:7605$273
+ attribute \src "libresoc.v:7796.3-7847.6"
+ process $proc$libresoc.v:7796$313
assign { } { }
assign { } { }
assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0]
- attribute \src "libresoc.v:7606.5-7606.29"
+ attribute \src "libresoc.v:7797.5-7797.29"
switch \initial
- attribute \src "libresoc.v:7606.9-7606.17"
+ attribute \src "libresoc.v:7797.9-7797.17"
case 1'1
case
end
sync always
update \dec19_cry_in $0\dec19_cry_in[1:0]
end
- attribute \src "libresoc.v:7657.3-7708.6"
- process $proc$libresoc.v:7657$274
+ attribute \src "libresoc.v:7848.3-7899.6"
+ process $proc$libresoc.v:7848$314
assign { } { }
assign { } { }
assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0]
- attribute \src "libresoc.v:7658.5-7658.29"
+ attribute \src "libresoc.v:7849.5-7849.29"
switch \initial
- attribute \src "libresoc.v:7658.9-7658.17"
+ attribute \src "libresoc.v:7849.9-7849.17"
case 1'1
case
end
sync always
update \dec19_asmcode $0\dec19_asmcode[7:0]
end
- attribute \src "libresoc.v:7709.3-7760.6"
- process $proc$libresoc.v:7709$275
+ attribute \src "libresoc.v:7900.3-7951.6"
+ process $proc$libresoc.v:7900$315
assign { } { }
assign { } { }
assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0]
- attribute \src "libresoc.v:7710.5-7710.29"
+ attribute \src "libresoc.v:7901.5-7901.29"
switch \initial
- attribute \src "libresoc.v:7710.9-7710.17"
+ attribute \src "libresoc.v:7901.9-7901.17"
case 1'1
case
end
sync always
update \dec19_inv_a $0\dec19_inv_a[0:0]
end
- attribute \src "libresoc.v:7761.3-7812.6"
- process $proc$libresoc.v:7761$276
+ attribute \src "libresoc.v:7952.3-8003.6"
+ process $proc$libresoc.v:7952$316
assign { } { }
assign { } { }
assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0]
- attribute \src "libresoc.v:7762.5-7762.29"
+ attribute \src "libresoc.v:7953.5-7953.29"
switch \initial
- attribute \src "libresoc.v:7762.9-7762.17"
+ attribute \src "libresoc.v:7953.9-7953.17"
case 1'1
case
end
sync always
update \dec19_inv_out $0\dec19_inv_out[0:0]
end
- attribute \src "libresoc.v:7813.3-7864.6"
- process $proc$libresoc.v:7813$277
+ attribute \src "libresoc.v:8004.3-8055.6"
+ process $proc$libresoc.v:8004$317
assign { } { }
assign { } { }
assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0]
- attribute \src "libresoc.v:7814.5-7814.29"
+ attribute \src "libresoc.v:8005.5-8005.29"
switch \initial
- attribute \src "libresoc.v:7814.9-7814.17"
+ attribute \src "libresoc.v:8005.9-8005.17"
case 1'1
case
end
sync always
update \dec19_cry_out $0\dec19_cry_out[0:0]
end
- attribute \src "libresoc.v:7865.3-7916.6"
- process $proc$libresoc.v:7865$278
+ attribute \src "libresoc.v:8056.3-8107.6"
+ process $proc$libresoc.v:8056$318
assign { } { }
assign { } { }
assign $0\dec19_br[0:0] $1\dec19_br[0:0]
- attribute \src "libresoc.v:7866.5-7866.29"
+ attribute \src "libresoc.v:8057.5-8057.29"
switch \initial
- attribute \src "libresoc.v:7866.9-7866.17"
+ attribute \src "libresoc.v:8057.9-8057.17"
case 1'1
case
end
sync always
update \dec19_br $0\dec19_br[0:0]
end
- attribute \src "libresoc.v:7917.3-7968.6"
- process $proc$libresoc.v:7917$279
+ attribute \src "libresoc.v:8108.3-8159.6"
+ process $proc$libresoc.v:8108$319
assign { } { }
assign { } { }
assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0]
- attribute \src "libresoc.v:7918.5-7918.29"
+ attribute \src "libresoc.v:8109.5-8109.29"
switch \initial
- attribute \src "libresoc.v:7918.9-7918.17"
+ attribute \src "libresoc.v:8109.9-8109.17"
case 1'1
case
end
sync always
update \dec19_sgn_ext $0\dec19_sgn_ext[0:0]
end
- attribute \src "libresoc.v:7969.3-8020.6"
- process $proc$libresoc.v:7969$280
+ attribute \src "libresoc.v:8160.3-8211.6"
+ process $proc$libresoc.v:8160$320
assign { } { }
assign { } { }
assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0]
- attribute \src "libresoc.v:7970.5-7970.29"
+ attribute \src "libresoc.v:8161.5-8161.29"
switch \initial
- attribute \src "libresoc.v:7970.9-7970.17"
+ attribute \src "libresoc.v:8161.9-8161.17"
case 1'1
case
end
sync always
update \dec19_internal_op $0\dec19_internal_op[6:0]
end
- attribute \src "libresoc.v:8021.3-8072.6"
- process $proc$libresoc.v:8021$281
+ attribute \src "libresoc.v:8212.3-8263.6"
+ process $proc$libresoc.v:8212$321
assign { } { }
assign { } { }
assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0]
- attribute \src "libresoc.v:8022.5-8022.29"
+ attribute \src "libresoc.v:8213.5-8213.29"
switch \initial
- attribute \src "libresoc.v:8022.9-8022.17"
+ attribute \src "libresoc.v:8213.9-8213.17"
case 1'1
case
end
sync always
update \dec19_rsrv $0\dec19_rsrv[0:0]
end
- attribute \src "libresoc.v:8073.3-8124.6"
- process $proc$libresoc.v:8073$282
+ attribute \src "libresoc.v:8264.3-8315.6"
+ process $proc$libresoc.v:8264$322
assign { } { }
assign { } { }
assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0]
- attribute \src "libresoc.v:8074.5-8074.29"
+ attribute \src "libresoc.v:8265.5-8265.29"
switch \initial
- attribute \src "libresoc.v:8074.9-8074.17"
+ attribute \src "libresoc.v:8265.9-8265.17"
case 1'1
case
end
sync always
update \dec19_is_32b $0\dec19_is_32b[0:0]
end
- attribute \src "libresoc.v:8125.3-8176.6"
- process $proc$libresoc.v:8125$283
+ attribute \src "libresoc.v:8316.3-8367.6"
+ process $proc$libresoc.v:8316$323
assign { } { }
assign { } { }
assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0]
- attribute \src "libresoc.v:8126.5-8126.29"
+ attribute \src "libresoc.v:8317.5-8317.29"
switch \initial
- attribute \src "libresoc.v:8126.9-8126.17"
+ attribute \src "libresoc.v:8317.9-8317.17"
case 1'1
case
end
sync always
update \dec19_sgn $0\dec19_sgn[0:0]
end
- attribute \src "libresoc.v:8177.3-8228.6"
- process $proc$libresoc.v:8177$284
+ attribute \src "libresoc.v:8368.3-8419.6"
+ process $proc$libresoc.v:8368$324
assign { } { }
assign { } { }
assign $0\dec19_lk[0:0] $1\dec19_lk[0:0]
- attribute \src "libresoc.v:8178.5-8178.29"
+ attribute \src "libresoc.v:8369.5-8369.29"
switch \initial
- attribute \src "libresoc.v:8178.9-8178.17"
+ attribute \src "libresoc.v:8369.9-8369.17"
case 1'1
case
end
sync always
update \dec19_lk $0\dec19_lk[0:0]
end
- attribute \src "libresoc.v:8229.3-8280.6"
- process $proc$libresoc.v:8229$285
+ attribute \src "libresoc.v:8420.3-8471.6"
+ process $proc$libresoc.v:8420$325
assign { } { }
assign { } { }
assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0]
- attribute \src "libresoc.v:8230.5-8230.29"
+ attribute \src "libresoc.v:8421.5-8421.29"
switch \initial
- attribute \src "libresoc.v:8230.9-8230.17"
+ attribute \src "libresoc.v:8421.9-8421.17"
case 1'1
case
end
sync always
update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:8281.3-8332.6"
- process $proc$libresoc.v:8281$286
+ attribute \src "libresoc.v:8472.3-8523.6"
+ process $proc$libresoc.v:8472$326
assign { } { }
assign { } { }
assign $0\dec19_form[4:0] $1\dec19_form[4:0]
- attribute \src "libresoc.v:8282.5-8282.29"
+ attribute \src "libresoc.v:8473.5-8473.29"
switch \initial
- attribute \src "libresoc.v:8282.9-8282.17"
+ attribute \src "libresoc.v:8473.9-8473.17"
case 1'1
case
end
sync always
update \dec19_form $0\dec19_form[4:0]
end
- attribute \src "libresoc.v:8333.3-8384.6"
- process $proc$libresoc.v:8333$287
+ attribute \src "libresoc.v:8524.3-8575.6"
+ process $proc$libresoc.v:8524$327
assign { } { }
assign { } { }
assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0]
- attribute \src "libresoc.v:8334.5-8334.29"
+ attribute \src "libresoc.v:8525.5-8525.29"
switch \initial
- attribute \src "libresoc.v:8334.9-8334.17"
+ attribute \src "libresoc.v:8525.9-8525.17"
case 1'1
case
end
sync always
update \dec19_in1_sel $0\dec19_in1_sel[2:0]
end
- attribute \src "libresoc.v:8385.3-8436.6"
- process $proc$libresoc.v:8385$288
+ attribute \src "libresoc.v:8576.3-8627.6"
+ process $proc$libresoc.v:8576$328
assign { } { }
assign { } { }
assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0]
- attribute \src "libresoc.v:8386.5-8386.29"
+ attribute \src "libresoc.v:8577.5-8577.29"
switch \initial
- attribute \src "libresoc.v:8386.9-8386.17"
+ attribute \src "libresoc.v:8577.9-8577.17"
case 1'1
case
end
sync always
update \dec19_in2_sel $0\dec19_in2_sel[3:0]
end
- attribute \src "libresoc.v:8437.3-8488.6"
- process $proc$libresoc.v:8437$289
+ attribute \src "libresoc.v:8628.3-8679.6"
+ process $proc$libresoc.v:8628$329
assign { } { }
assign { } { }
assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0]
- attribute \src "libresoc.v:8438.5-8438.29"
+ attribute \src "libresoc.v:8629.5-8629.29"
switch \initial
- attribute \src "libresoc.v:8438.9-8438.17"
+ attribute \src "libresoc.v:8629.9-8629.17"
case 1'1
case
end
sync always
update \dec19_in3_sel $0\dec19_in3_sel[1:0]
end
- attribute \src "libresoc.v:8489.3-8540.6"
- process $proc$libresoc.v:8489$290
+ attribute \src "libresoc.v:8680.3-8731.6"
+ process $proc$libresoc.v:8680$330
assign { } { }
assign { } { }
assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0]
- attribute \src "libresoc.v:8490.5-8490.29"
+ attribute \src "libresoc.v:8681.5-8681.29"
switch \initial
- attribute \src "libresoc.v:8490.9-8490.17"
+ attribute \src "libresoc.v:8681.9-8681.17"
case 1'1
case
end
sync always
update \dec19_out_sel $0\dec19_out_sel[1:0]
end
- attribute \src "libresoc.v:8541.3-8592.6"
- process $proc$libresoc.v:8541$291
+ attribute \src "libresoc.v:8732.3-8783.6"
+ process $proc$libresoc.v:8732$331
assign { } { }
assign { } { }
assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0]
- attribute \src "libresoc.v:8542.5-8542.29"
+ attribute \src "libresoc.v:8733.5-8733.29"
switch \initial
- attribute \src "libresoc.v:8542.9-8542.17"
+ attribute \src "libresoc.v:8733.9-8733.17"
case 1'1
case
end
sync always
update \dec19_cr_in $0\dec19_cr_in[2:0]
end
- attribute \src "libresoc.v:8593.3-8644.6"
- process $proc$libresoc.v:8593$292
+ attribute \src "libresoc.v:8784.3-8835.6"
+ process $proc$libresoc.v:8784$332
assign { } { }
assign { } { }
assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0]
- attribute \src "libresoc.v:8594.5-8594.29"
+ attribute \src "libresoc.v:8785.5-8785.29"
switch \initial
- attribute \src "libresoc.v:8594.9-8594.17"
+ attribute \src "libresoc.v:8785.9-8785.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:1]
end
-attribute \src "libresoc.v:8650.1-10539.10"
+attribute \src "libresoc.v:8841.1-10730.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2"
attribute \generator "nMigen"
module \dec2
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 8 $0\asmcode[7:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 64 $0\cia[63:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $0\cr_in1[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\cr_in1_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
- wire width 3 $0\cr_in2$1[2:0]$312
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
+ wire width 3 $0\cr_in2$1[2:0]$352
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $0\cr_in2[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
- wire $0\cr_in2_ok$2[0:0]$313
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
+ wire $0\cr_in2_ok$2[0:0]$353
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\cr_in2_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $0\cr_out[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\cr_out_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 8 $0\cr_rd[7:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\cr_rd_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 8 $0\cr_wr[7:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\cr_wr_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 5 $0\ea[4:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\ea_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $0\fast1[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $0\fast2[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\fast2_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $0\fasto1[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\fasto1_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $0\fasto2[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\fasto2_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 12 $0\fn_unit[11:0]
- attribute \src "libresoc.v:8651.7-8651.20"
+ attribute \src "libresoc.v:8842.7-8842.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 2 $0\input_carry[1:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 32 $0\insn[31:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 7 $0\insn_type[6:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\is_32bit[0:0]
- attribute \src "libresoc.v:10385.3-10404.6"
+ attribute \src "libresoc.v:10576.3-10595.6"
wire $0\is_priv_insn[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\lk[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 64 $0\msr[63:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 5 $0\reg1[4:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\reg1_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 5 $0\reg2[4:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\reg2_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 5 $0\reg3[4:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\reg3_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 5 $0\rego[4:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\rego_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 10 $0\spr1[9:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\spr1_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 10 $0\spro[9:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\spro_ok[0:0]
- attribute \src "libresoc.v:10339.3-10348.6"
+ attribute \src "libresoc.v:10530.3-10539.6"
wire $0\tmp_tmp_lk[0:0]
- attribute \src "libresoc.v:10375.3-10384.6"
+ attribute \src "libresoc.v:10566.3-10575.6"
wire width 13 $0\tmp_tmp_trapaddr[12:0]
- attribute \src "libresoc.v:10349.3-10364.6"
+ attribute \src "libresoc.v:10540.3-10555.6"
wire width 3 $0\tmp_xer_in[2:0]
- attribute \src "libresoc.v:10365.3-10374.6"
+ attribute \src "libresoc.v:10556.3-10565.6"
wire $0\tmp_xer_out[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 13 $0\trapaddr[12:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 7 $0\traptype[6:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $0\xer_in[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $0\xer_out[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 8 $1\asmcode[7:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 64 $1\cia[63:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $1\cr_in1[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\cr_in1_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
- wire width 3 $1\cr_in2$1[2:0]$314
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
+ wire width 3 $1\cr_in2$1[2:0]$354
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $1\cr_in2[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
- wire $1\cr_in2_ok$2[0:0]$315
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
+ wire $1\cr_in2_ok$2[0:0]$355
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\cr_in2_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $1\cr_out[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\cr_out_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 8 $1\cr_rd[7:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\cr_rd_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 8 $1\cr_wr[7:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\cr_wr_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 5 $1\ea[4:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\ea_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $1\fast1[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $1\fast2[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\fast2_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $1\fasto1[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\fasto1_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $1\fasto2[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\fasto2_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 12 $1\fn_unit[11:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 2 $1\input_carry[1:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 32 $1\insn[31:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 7 $1\insn_type[6:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\is_32bit[0:0]
- attribute \src "libresoc.v:10385.3-10404.6"
+ attribute \src "libresoc.v:10576.3-10595.6"
wire $1\is_priv_insn[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\lk[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 64 $1\msr[63:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\rc_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 5 $1\reg1[4:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\reg1_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 5 $1\reg2[4:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\reg2_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 5 $1\reg3[4:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\reg3_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 5 $1\rego[4:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\rego_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 10 $1\spr1[9:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\spr1_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 10 $1\spro[9:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\spro_ok[0:0]
- attribute \src "libresoc.v:10339.3-10348.6"
+ attribute \src "libresoc.v:10530.3-10539.6"
wire $1\tmp_tmp_lk[0:0]
- attribute \src "libresoc.v:10375.3-10384.6"
+ attribute \src "libresoc.v:10566.3-10575.6"
wire width 13 $1\tmp_tmp_trapaddr[12:0]
- attribute \src "libresoc.v:10349.3-10364.6"
+ attribute \src "libresoc.v:10540.3-10555.6"
wire width 3 $1\tmp_xer_in[2:0]
- attribute \src "libresoc.v:10365.3-10374.6"
+ attribute \src "libresoc.v:10556.3-10565.6"
wire $1\tmp_xer_out[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 13 $1\trapaddr[12:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 7 $1\traptype[6:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $1\xer_in[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $1\xer_out[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $2\fast1[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $2\fast1_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $2\fast2[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $2\fast2_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $2\fasto1[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $2\fasto1_ok[0:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire width 3 $2\fasto2[2:0]
- attribute \src "libresoc.v:10405.3-10486.6"
+ attribute \src "libresoc.v:10596.3-10677.6"
wire $2\fasto2_ok[0:0]
- attribute \src "libresoc.v:10385.3-10404.6"
+ attribute \src "libresoc.v:10576.3-10595.6"
wire $2\is_priv_insn[0:0]
- attribute \src "libresoc.v:10349.3-10364.6"
+ attribute \src "libresoc.v:10540.3-10555.6"
wire width 3 $2\tmp_xer_in[2:0]
- attribute \src "libresoc.v:10190.18-10190.120"
- wire $and$libresoc.v:10190$298_Y
- attribute \src "libresoc.v:10191.18-10191.123"
- wire $and$libresoc.v:10191$299_Y
- attribute \src "libresoc.v:10192.18-10192.124"
- wire $and$libresoc.v:10192$300_Y
- attribute \src "libresoc.v:10186.18-10186.122"
- wire $eq$libresoc.v:10186$294_Y
- attribute \src "libresoc.v:10187.18-10187.122"
- wire $eq$libresoc.v:10187$295_Y
- attribute \src "libresoc.v:10188.18-10188.122"
- wire $eq$libresoc.v:10188$296_Y
- attribute \src "libresoc.v:10189.18-10189.122"
- wire $eq$libresoc.v:10189$297_Y
- attribute \src "libresoc.v:10193.18-10193.122"
- wire $eq$libresoc.v:10193$301_Y
- attribute \src "libresoc.v:10194.18-10194.116"
- wire $eq$libresoc.v:10194$302_Y
- attribute \src "libresoc.v:10195.18-10195.116"
- wire $eq$libresoc.v:10195$303_Y
- attribute \src "libresoc.v:10197.18-10197.116"
- wire $eq$libresoc.v:10197$305_Y
- attribute \src "libresoc.v:10196.18-10196.110"
- wire $or$libresoc.v:10196$304_Y
+ attribute \src "libresoc.v:10381.18-10381.120"
+ wire $and$libresoc.v:10381$338_Y
+ attribute \src "libresoc.v:10382.18-10382.123"
+ wire $and$libresoc.v:10382$339_Y
+ attribute \src "libresoc.v:10383.18-10383.124"
+ wire $and$libresoc.v:10383$340_Y
+ attribute \src "libresoc.v:10377.18-10377.122"
+ wire $eq$libresoc.v:10377$334_Y
+ attribute \src "libresoc.v:10378.18-10378.122"
+ wire $eq$libresoc.v:10378$335_Y
+ attribute \src "libresoc.v:10379.18-10379.122"
+ wire $eq$libresoc.v:10379$336_Y
+ attribute \src "libresoc.v:10380.18-10380.122"
+ wire $eq$libresoc.v:10380$337_Y
+ attribute \src "libresoc.v:10384.18-10384.122"
+ wire $eq$libresoc.v:10384$341_Y
+ attribute \src "libresoc.v:10385.18-10385.116"
+ wire $eq$libresoc.v:10385$342_Y
+ attribute \src "libresoc.v:10386.18-10386.116"
+ wire $eq$libresoc.v:10386$343_Y
+ attribute \src "libresoc.v:10388.18-10388.116"
+ wire $eq$libresoc.v:10388$345_Y
+ attribute \src "libresoc.v:10387.18-10387.110"
+ wire $or$libresoc.v:10387$344_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859"
wire \$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861"
wire width 12 output 42 \fn_unit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887"
wire \illeg_ok
- attribute \src "libresoc.v:8651.7-8651.15"
+ attribute \src "libresoc.v:8842.7-8842.15"
wire \initial
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103"
wire output 21 \xer_out
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889"
- cell $and $and$libresoc.v:10190$298
+ cell $and $and$libresoc.v:10381$338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_eint
connect \B \cur_msr [15]
- connect \Y $and$libresoc.v:10190$298_Y
+ connect \Y $and$libresoc.v:10381$338_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:890"
- cell $and $and$libresoc.v:10191$299
+ cell $and $and$libresoc.v:10382$339
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_dec [63]
connect \B \cur_msr [15]
- connect \Y $and$libresoc.v:10191$299_Y
+ connect \Y $and$libresoc.v:10382$339_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:891"
- cell $and $and$libresoc.v:10192$300
+ cell $and $and$libresoc.v:10383$340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_priv_insn
connect \B \cur_msr [14]
- connect \Y $and$libresoc.v:10192$300_Y
+ connect \Y $and$libresoc.v:10383$340_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859"
- cell $eq $eq$libresoc.v:10186$294
+ cell $eq $eq$libresoc.v:10377$334
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0101110
- connect \Y $eq$libresoc.v:10186$294_Y
+ connect \Y $eq$libresoc.v:10377$334_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861"
- cell $eq $eq$libresoc.v:10187$295
+ cell $eq $eq$libresoc.v:10378$335
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0001010
- connect \Y $eq$libresoc.v:10187$295_Y
+ connect \Y $eq$libresoc.v:10378$335_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863"
- cell $eq $eq$libresoc.v:10188$296
+ cell $eq $eq$libresoc.v:10379$336
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:10188$296_Y
+ connect \Y $eq$libresoc.v:10379$336_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867"
- cell $eq $eq$libresoc.v:10189$297
+ cell $eq $eq$libresoc.v:10380$337
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0111111
- connect \Y $eq$libresoc.v:10189$297_Y
+ connect \Y $eq$libresoc.v:10380$337_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892"
- cell $eq $eq$libresoc.v:10193$301
+ cell $eq $eq$libresoc.v:10384$341
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dec_internal_op
connect \B 7'0000000
- connect \Y $eq$libresoc.v:10193$301_Y
+ connect \Y $eq$libresoc.v:10384$341_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:923"
- cell $eq $eq$libresoc.v:10194$302
+ cell $eq $eq$libresoc.v:10385$342
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \insn_type
connect \B 7'0111111
- connect \Y $eq$libresoc.v:10194$302_Y
+ connect \Y $eq$libresoc.v:10385$342_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924"
- cell $eq $eq$libresoc.v:10195$303
+ cell $eq $eq$libresoc.v:10386$343
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \insn_type
connect \B 7'1001001
- connect \Y $eq$libresoc.v:10195$303_Y
+ connect \Y $eq$libresoc.v:10386$343_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933"
- cell $eq $eq$libresoc.v:10197$305
+ cell $eq $eq$libresoc.v:10388$345
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \insn_type
connect \B 7'1000110
- connect \Y $eq$libresoc.v:10197$305_Y
+ connect \Y $eq$libresoc.v:10388$345_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924"
- cell $or $or$libresoc.v:10196$304
+ cell $or $or$libresoc.v:10387$344
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$29
connect \B \$31
- connect \Y $or$libresoc.v:10196$304_Y
+ connect \Y $or$libresoc.v:10387$344_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:10198.7-10235.4"
+ attribute \src "libresoc.v:10389.7-10426.4"
cell \dec \dec
connect \BA \dec_BA
connect \BB \dec_BB
connect \upd \dec_upd
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:10236.9-10250.4"
+ attribute \src "libresoc.v:10427.9-10441.4"
cell \dec_a \dec_a
connect \BO \dec_BO
connect \RA \dec_RA
connect \spr_a_ok \dec_a_spr_a_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:10251.9-10261.4"
+ attribute \src "libresoc.v:10442.9-10452.4"
cell \dec_b \dec_b
connect \RB \dec_RB
connect \RS \dec_RS
connect \sel_in \dec_b_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:10262.9-10268.4"
+ attribute \src "libresoc.v:10453.9-10459.4"
cell \dec_c \dec_c
connect \RB \dec_RB
connect \RS \dec_RS
connect \sel_in \dec_c_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:10269.13-10288.4"
+ attribute \src "libresoc.v:10460.13-10479.4"
cell \dec_cr_in \dec_cr_in$3
connect \BA \dec_BA
connect \BB \dec_BB
connect \sel_in \dec_cr_in_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:10289.14-10301.4"
+ attribute \src "libresoc.v:10480.14-10492.4"
cell \dec_cr_out \dec_cr_out$4
connect \FXM \dec_FXM
connect \XL_BT \dec_XL_BT
connect \sel_in \dec_cr_out_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:10302.9-10315.4"
+ attribute \src "libresoc.v:10493.9-10506.4"
cell \dec_o \dec_o
connect \BO \dec_BO
connect \RA \dec_RA
connect \spr_o_ok \dec_o_spr_o_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:10316.10-10325.4"
+ attribute \src "libresoc.v:10507.10-10516.4"
cell \dec_o2 \dec_o2
connect \RA \dec_RA
connect \fast_o \dec_o2_fast_o
connect \upd \dec_upd
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:10326.10-10332.4"
+ attribute \src "libresoc.v:10517.10-10523.4"
cell \dec_oe \dec_oe
connect \OE \dec_OE
connect \internal_op \dec_internal_op
connect \sel_in \dec_oe_sel_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:10333.10-10338.4"
+ attribute \src "libresoc.v:10524.10-10529.4"
cell \dec_rc \dec_rc
connect \Rc \dec_Rc
connect \rc \dec_rc_rc
connect \rc_ok \dec_rc_rc_ok
connect \sel_in \dec_rc_sel_in
end
- attribute \src "libresoc.v:10339.3-10348.6"
- process $proc$libresoc.v:10339$306
+ attribute \src "libresoc.v:10530.3-10539.6"
+ process $proc$libresoc.v:10530$346
assign { } { }
assign { } { }
assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0]
- attribute \src "libresoc.v:10340.5-10340.29"
+ attribute \src "libresoc.v:10531.5-10531.29"
switch \initial
- attribute \src "libresoc.v:10340.9-10340.17"
+ attribute \src "libresoc.v:10531.9-10531.17"
case 1'1
case
end
sync always
update \tmp_tmp_lk $0\tmp_tmp_lk[0:0]
end
- attribute \src "libresoc.v:10349.3-10364.6"
- process $proc$libresoc.v:10349$307
+ attribute \src "libresoc.v:10540.3-10555.6"
+ process $proc$libresoc.v:10540$347
assign { } { }
assign { } { }
assign { } { }
assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0]
- attribute \src "libresoc.v:10350.5-10350.29"
+ attribute \src "libresoc.v:10541.5-10541.29"
switch \initial
- attribute \src "libresoc.v:10350.9-10350.17"
+ attribute \src "libresoc.v:10541.9-10541.17"
case 1'1
case
end
sync always
update \tmp_xer_in $0\tmp_xer_in[2:0]
end
- attribute \src "libresoc.v:10365.3-10374.6"
- process $proc$libresoc.v:10365$308
+ attribute \src "libresoc.v:10556.3-10565.6"
+ process $proc$libresoc.v:10556$348
assign { } { }
assign { } { }
assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0]
- attribute \src "libresoc.v:10366.5-10366.29"
+ attribute \src "libresoc.v:10557.5-10557.29"
switch \initial
- attribute \src "libresoc.v:10366.9-10366.17"
+ attribute \src "libresoc.v:10557.9-10557.17"
case 1'1
case
end
sync always
update \tmp_xer_out $0\tmp_xer_out[0:0]
end
- attribute \src "libresoc.v:10375.3-10384.6"
- process $proc$libresoc.v:10375$309
+ attribute \src "libresoc.v:10566.3-10575.6"
+ process $proc$libresoc.v:10566$349
assign { } { }
assign { } { }
assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0]
- attribute \src "libresoc.v:10376.5-10376.29"
+ attribute \src "libresoc.v:10567.5-10567.29"
switch \initial
- attribute \src "libresoc.v:10376.9-10376.17"
+ attribute \src "libresoc.v:10567.9-10567.17"
case 1'1
case
end
sync always
update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0]
end
- attribute \src "libresoc.v:10385.3-10404.6"
- process $proc$libresoc.v:10385$310
+ attribute \src "libresoc.v:10576.3-10595.6"
+ process $proc$libresoc.v:10576$350
assign { } { }
assign { } { }
assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0]
- attribute \src "libresoc.v:10386.5-10386.29"
+ attribute \src "libresoc.v:10577.5-10577.29"
switch \initial
- attribute \src "libresoc.v:10386.9-10386.17"
+ attribute \src "libresoc.v:10577.9-10577.17"
case 1'1
case
end
sync always
update \is_priv_insn $0\is_priv_insn[0:0]
end
- attribute \src "libresoc.v:10405.3-10486.6"
- process $proc$libresoc.v:10405$311
+ attribute \src "libresoc.v:10596.3-10677.6"
+ process $proc$libresoc.v:10596$351
assign { } { }
assign { } { }
assign { } { }
assign $0\cr_in1[2:0] $1\cr_in1[2:0]
assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0]
assign $0\cr_in2[2:0] $1\cr_in2[2:0]
- assign $0\cr_in2$1[2:0]$312 $1\cr_in2$1[2:0]$314
+ assign $0\cr_in2$1[2:0]$352 $1\cr_in2$1[2:0]$354
assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0]
- assign $0\cr_in2_ok$2[0:0]$313 $1\cr_in2_ok$2[0:0]$315
+ assign $0\cr_in2_ok$2[0:0]$353 $1\cr_in2_ok$2[0:0]$355
assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0]
assign $0\cr_rd[7:0] $1\cr_rd[7:0]
assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0]
assign $0\fast2[2:0] $2\fast2[2:0]
assign $0\fast2_ok[0:0] $2\fast2_ok[0:0]
assign $0\asmcode[7:0] \dec_asmcode
- attribute \src "libresoc.v:10406.5-10406.29"
+ attribute \src "libresoc.v:10597.5-10597.29"
switch \initial
- attribute \src "libresoc.v:10406.9-10406.17"
+ attribute \src "libresoc.v:10597.9-10597.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$315 $1\cr_in2$1[2:0]$314 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $1\insn[31:0] \dec_opcode_in
assign $1\insn_type[6:0] 7'0111111
assign $1\fn_unit[11:0] 12'000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$315 $1\cr_in2$1[2:0]$314 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $1\insn[31:0] \dec_opcode_in
assign $1\insn_type[6:0] 7'0111111
assign $1\fn_unit[11:0] 12'000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$315 $1\cr_in2$1[2:0]$314 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $1\insn[31:0] \dec_opcode_in
assign $1\insn_type[6:0] 7'0111111
assign $1\fn_unit[11:0] 12'000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$315 $1\cr_in2$1[2:0]$314 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign $1\insn[31:0] \dec_opcode_in
assign $1\insn_type[6:0] 7'0111111
assign $1\fn_unit[11:0] 12'000010000000
assign { } { }
assign { } { }
assign { } { }
- assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\traptype[6:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$315 $1\cr_in2$1[2:0]$314 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$12 \tmp_cr_in2$11 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode }
+ assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\traptype[6:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$12 \tmp_cr_in2$11 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode }
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924"
switch \$33
update \cr_in1 $0\cr_in1[2:0]
update \cr_in1_ok $0\cr_in1_ok[0:0]
update \cr_in2 $0\cr_in2[2:0]
- update \cr_in2$1 $0\cr_in2$1[2:0]$312
+ update \cr_in2$1 $0\cr_in2$1[2:0]$352
update \cr_in2_ok $0\cr_in2_ok[0:0]
- update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$313
+ update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$353
update \cr_out_ok $0\cr_out_ok[0:0]
update \cr_rd $0\cr_rd[7:0]
update \cr_rd_ok $0\cr_rd_ok[0:0]
update \xer_in $0\xer_in[2:0]
update \xer_out $0\xer_out[0:0]
end
- attribute \src "libresoc.v:8651.7-8651.20"
- process $proc$libresoc.v:8651$316
+ attribute \src "libresoc.v:8842.7-8842.20"
+ process $proc$libresoc.v:8842$356
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- connect \$13 $eq$libresoc.v:10186$294_Y
- connect \$15 $eq$libresoc.v:10187$295_Y
- connect \$17 $eq$libresoc.v:10188$296_Y
- connect \$19 $eq$libresoc.v:10189$297_Y
- connect \$21 $and$libresoc.v:10190$298_Y
- connect \$23 $and$libresoc.v:10191$299_Y
- connect \$25 $and$libresoc.v:10192$300_Y
- connect \$27 $eq$libresoc.v:10193$301_Y
- connect \$29 $eq$libresoc.v:10194$302_Y
- connect \$31 $eq$libresoc.v:10195$303_Y
- connect \$33 $or$libresoc.v:10196$304_Y
- connect \$35 $eq$libresoc.v:10197$305_Y
+ connect \$13 $eq$libresoc.v:10377$334_Y
+ connect \$15 $eq$libresoc.v:10378$335_Y
+ connect \$17 $eq$libresoc.v:10379$336_Y
+ connect \$19 $eq$libresoc.v:10380$337_Y
+ connect \$21 $and$libresoc.v:10381$338_Y
+ connect \$23 $and$libresoc.v:10382$339_Y
+ connect \$25 $and$libresoc.v:10383$340_Y
+ connect \$27 $eq$libresoc.v:10384$341_Y
+ connect \$29 $eq$libresoc.v:10385$342_Y
+ connect \$31 $eq$libresoc.v:10386$343_Y
+ connect \$33 $or$libresoc.v:10387$344_Y
+ connect \$35 $eq$libresoc.v:10388$345_Y
connect \tmp_asmcode 8'00000000
connect \tmp_tmp_traptype 7'0000000
connect \illeg_ok \$27
connect \insn_in \dec_opcode_in
connect \tmp_tmp_insn \dec_opcode_in
end
-attribute \src "libresoc.v:10543.1-11690.10"
+attribute \src "libresoc.v:10734.1-11881.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec30"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30"
attribute \generator "nMigen"
module \dec30
- attribute \src "libresoc.v:10986.3-11022.6"
+ attribute \src "libresoc.v:11177.3-11213.6"
wire width 8 $0\dec30_asmcode[7:0]
- attribute \src "libresoc.v:11134.3-11170.6"
+ attribute \src "libresoc.v:11325.3-11361.6"
wire $0\dec30_br[0:0]
- attribute \src "libresoc.v:11615.3-11651.6"
+ attribute \src "libresoc.v:11806.3-11842.6"
wire width 3 $0\dec30_cr_in[2:0]
- attribute \src "libresoc.v:11652.3-11688.6"
+ attribute \src "libresoc.v:11843.3-11879.6"
wire width 3 $0\dec30_cr_out[2:0]
- attribute \src "libresoc.v:10949.3-10985.6"
+ attribute \src "libresoc.v:11140.3-11176.6"
wire width 2 $0\dec30_cry_in[1:0]
- attribute \src "libresoc.v:11097.3-11133.6"
+ attribute \src "libresoc.v:11288.3-11324.6"
wire $0\dec30_cry_out[0:0]
- attribute \src "libresoc.v:11430.3-11466.6"
+ attribute \src "libresoc.v:11621.3-11657.6"
wire width 5 $0\dec30_form[4:0]
- attribute \src "libresoc.v:10801.3-10837.6"
+ attribute \src "libresoc.v:10992.3-11028.6"
wire width 12 $0\dec30_function_unit[11:0]
- attribute \src "libresoc.v:11467.3-11503.6"
+ attribute \src "libresoc.v:11658.3-11694.6"
wire width 3 $0\dec30_in1_sel[2:0]
- attribute \src "libresoc.v:11504.3-11540.6"
+ attribute \src "libresoc.v:11695.3-11731.6"
wire width 4 $0\dec30_in2_sel[3:0]
- attribute \src "libresoc.v:11541.3-11577.6"
+ attribute \src "libresoc.v:11732.3-11768.6"
wire width 2 $0\dec30_in3_sel[1:0]
- attribute \src "libresoc.v:11208.3-11244.6"
+ attribute \src "libresoc.v:11399.3-11435.6"
wire width 7 $0\dec30_internal_op[6:0]
- attribute \src "libresoc.v:11023.3-11059.6"
+ attribute \src "libresoc.v:11214.3-11250.6"
wire $0\dec30_inv_a[0:0]
- attribute \src "libresoc.v:11060.3-11096.6"
+ attribute \src "libresoc.v:11251.3-11287.6"
wire $0\dec30_inv_out[0:0]
- attribute \src "libresoc.v:11282.3-11318.6"
+ attribute \src "libresoc.v:11473.3-11509.6"
wire $0\dec30_is_32b[0:0]
- attribute \src "libresoc.v:10838.3-10874.6"
+ attribute \src "libresoc.v:11029.3-11065.6"
wire width 4 $0\dec30_ldst_len[3:0]
- attribute \src "libresoc.v:11356.3-11392.6"
+ attribute \src "libresoc.v:11547.3-11583.6"
wire $0\dec30_lk[0:0]
- attribute \src "libresoc.v:11578.3-11614.6"
+ attribute \src "libresoc.v:11769.3-11805.6"
wire width 2 $0\dec30_out_sel[1:0]
- attribute \src "libresoc.v:10912.3-10948.6"
+ attribute \src "libresoc.v:11103.3-11139.6"
wire width 2 $0\dec30_rc_sel[1:0]
- attribute \src "libresoc.v:11245.3-11281.6"
+ attribute \src "libresoc.v:11436.3-11472.6"
wire $0\dec30_rsrv[0:0]
- attribute \src "libresoc.v:11393.3-11429.6"
+ attribute \src "libresoc.v:11584.3-11620.6"
wire $0\dec30_sgl_pipe[0:0]
- attribute \src "libresoc.v:11319.3-11355.6"
+ attribute \src "libresoc.v:11510.3-11546.6"
wire $0\dec30_sgn[0:0]
- attribute \src "libresoc.v:11171.3-11207.6"
+ attribute \src "libresoc.v:11362.3-11398.6"
wire $0\dec30_sgn_ext[0:0]
- attribute \src "libresoc.v:10875.3-10911.6"
+ attribute \src "libresoc.v:11066.3-11102.6"
wire width 2 $0\dec30_upd[1:0]
- attribute \src "libresoc.v:10544.7-10544.20"
+ attribute \src "libresoc.v:10735.7-10735.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:10986.3-11022.6"
+ attribute \src "libresoc.v:11177.3-11213.6"
wire width 8 $1\dec30_asmcode[7:0]
- attribute \src "libresoc.v:11134.3-11170.6"
+ attribute \src "libresoc.v:11325.3-11361.6"
wire $1\dec30_br[0:0]
- attribute \src "libresoc.v:11615.3-11651.6"
+ attribute \src "libresoc.v:11806.3-11842.6"
wire width 3 $1\dec30_cr_in[2:0]
- attribute \src "libresoc.v:11652.3-11688.6"
+ attribute \src "libresoc.v:11843.3-11879.6"
wire width 3 $1\dec30_cr_out[2:0]
- attribute \src "libresoc.v:10949.3-10985.6"
+ attribute \src "libresoc.v:11140.3-11176.6"
wire width 2 $1\dec30_cry_in[1:0]
- attribute \src "libresoc.v:11097.3-11133.6"
+ attribute \src "libresoc.v:11288.3-11324.6"
wire $1\dec30_cry_out[0:0]
- attribute \src "libresoc.v:11430.3-11466.6"
+ attribute \src "libresoc.v:11621.3-11657.6"
wire width 5 $1\dec30_form[4:0]
- attribute \src "libresoc.v:10801.3-10837.6"
+ attribute \src "libresoc.v:10992.3-11028.6"
wire width 12 $1\dec30_function_unit[11:0]
- attribute \src "libresoc.v:11467.3-11503.6"
+ attribute \src "libresoc.v:11658.3-11694.6"
wire width 3 $1\dec30_in1_sel[2:0]
- attribute \src "libresoc.v:11504.3-11540.6"
+ attribute \src "libresoc.v:11695.3-11731.6"
wire width 4 $1\dec30_in2_sel[3:0]
- attribute \src "libresoc.v:11541.3-11577.6"
+ attribute \src "libresoc.v:11732.3-11768.6"
wire width 2 $1\dec30_in3_sel[1:0]
- attribute \src "libresoc.v:11208.3-11244.6"
+ attribute \src "libresoc.v:11399.3-11435.6"
wire width 7 $1\dec30_internal_op[6:0]
- attribute \src "libresoc.v:11023.3-11059.6"
+ attribute \src "libresoc.v:11214.3-11250.6"
wire $1\dec30_inv_a[0:0]
- attribute \src "libresoc.v:11060.3-11096.6"
+ attribute \src "libresoc.v:11251.3-11287.6"
wire $1\dec30_inv_out[0:0]
- attribute \src "libresoc.v:11282.3-11318.6"
+ attribute \src "libresoc.v:11473.3-11509.6"
wire $1\dec30_is_32b[0:0]
- attribute \src "libresoc.v:10838.3-10874.6"
+ attribute \src "libresoc.v:11029.3-11065.6"
wire width 4 $1\dec30_ldst_len[3:0]
- attribute \src "libresoc.v:11356.3-11392.6"
+ attribute \src "libresoc.v:11547.3-11583.6"
wire $1\dec30_lk[0:0]
- attribute \src "libresoc.v:11578.3-11614.6"
+ attribute \src "libresoc.v:11769.3-11805.6"
wire width 2 $1\dec30_out_sel[1:0]
- attribute \src "libresoc.v:10912.3-10948.6"
+ attribute \src "libresoc.v:11103.3-11139.6"
wire width 2 $1\dec30_rc_sel[1:0]
- attribute \src "libresoc.v:11245.3-11281.6"
+ attribute \src "libresoc.v:11436.3-11472.6"
wire $1\dec30_rsrv[0:0]
- attribute \src "libresoc.v:11393.3-11429.6"
+ attribute \src "libresoc.v:11584.3-11620.6"
wire $1\dec30_sgl_pipe[0:0]
- attribute \src "libresoc.v:11319.3-11355.6"
+ attribute \src "libresoc.v:11510.3-11546.6"
wire $1\dec30_sgn[0:0]
- attribute \src "libresoc.v:11171.3-11207.6"
+ attribute \src "libresoc.v:11362.3-11398.6"
wire $1\dec30_sgn_ext[0:0]
- attribute \src "libresoc.v:10875.3-10911.6"
+ attribute \src "libresoc.v:11066.3-11102.6"
wire width 2 $1\dec30_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec30_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec30_upd
- attribute \src "libresoc.v:10544.7-10544.15"
+ attribute \src "libresoc.v:10735.7-10735.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 4 \opcode_switch
- attribute \src "libresoc.v:10544.7-10544.20"
- process $proc$libresoc.v:10544$341
+ attribute \src "libresoc.v:10735.7-10735.20"
+ process $proc$libresoc.v:10735$381
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:10801.3-10837.6"
- process $proc$libresoc.v:10801$317
+ attribute \src "libresoc.v:10992.3-11028.6"
+ process $proc$libresoc.v:10992$357
assign { } { }
assign { } { }
assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0]
- attribute \src "libresoc.v:10802.5-10802.29"
+ attribute \src "libresoc.v:10993.5-10993.29"
switch \initial
- attribute \src "libresoc.v:10802.9-10802.17"
+ attribute \src "libresoc.v:10993.9-10993.17"
case 1'1
case
end
sync always
update \dec30_function_unit $0\dec30_function_unit[11:0]
end
- attribute \src "libresoc.v:10838.3-10874.6"
- process $proc$libresoc.v:10838$318
+ attribute \src "libresoc.v:11029.3-11065.6"
+ process $proc$libresoc.v:11029$358
assign { } { }
assign { } { }
assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0]
- attribute \src "libresoc.v:10839.5-10839.29"
+ attribute \src "libresoc.v:11030.5-11030.29"
switch \initial
- attribute \src "libresoc.v:10839.9-10839.17"
+ attribute \src "libresoc.v:11030.9-11030.17"
case 1'1
case
end
sync always
update \dec30_ldst_len $0\dec30_ldst_len[3:0]
end
- attribute \src "libresoc.v:10875.3-10911.6"
- process $proc$libresoc.v:10875$319
+ attribute \src "libresoc.v:11066.3-11102.6"
+ process $proc$libresoc.v:11066$359
assign { } { }
assign { } { }
assign $0\dec30_upd[1:0] $1\dec30_upd[1:0]
- attribute \src "libresoc.v:10876.5-10876.29"
+ attribute \src "libresoc.v:11067.5-11067.29"
switch \initial
- attribute \src "libresoc.v:10876.9-10876.17"
+ attribute \src "libresoc.v:11067.9-11067.17"
case 1'1
case
end
sync always
update \dec30_upd $0\dec30_upd[1:0]
end
- attribute \src "libresoc.v:10912.3-10948.6"
- process $proc$libresoc.v:10912$320
+ attribute \src "libresoc.v:11103.3-11139.6"
+ process $proc$libresoc.v:11103$360
assign { } { }
assign { } { }
assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0]
- attribute \src "libresoc.v:10913.5-10913.29"
+ attribute \src "libresoc.v:11104.5-11104.29"
switch \initial
- attribute \src "libresoc.v:10913.9-10913.17"
+ attribute \src "libresoc.v:11104.9-11104.17"
case 1'1
case
end
sync always
update \dec30_rc_sel $0\dec30_rc_sel[1:0]
end
- attribute \src "libresoc.v:10949.3-10985.6"
- process $proc$libresoc.v:10949$321
+ attribute \src "libresoc.v:11140.3-11176.6"
+ process $proc$libresoc.v:11140$361
assign { } { }
assign { } { }
assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0]
- attribute \src "libresoc.v:10950.5-10950.29"
+ attribute \src "libresoc.v:11141.5-11141.29"
switch \initial
- attribute \src "libresoc.v:10950.9-10950.17"
+ attribute \src "libresoc.v:11141.9-11141.17"
case 1'1
case
end
sync always
update \dec30_cry_in $0\dec30_cry_in[1:0]
end
- attribute \src "libresoc.v:10986.3-11022.6"
- process $proc$libresoc.v:10986$322
+ attribute \src "libresoc.v:11177.3-11213.6"
+ process $proc$libresoc.v:11177$362
assign { } { }
assign { } { }
assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0]
- attribute \src "libresoc.v:10987.5-10987.29"
+ attribute \src "libresoc.v:11178.5-11178.29"
switch \initial
- attribute \src "libresoc.v:10987.9-10987.17"
+ attribute \src "libresoc.v:11178.9-11178.17"
case 1'1
case
end
sync always
update \dec30_asmcode $0\dec30_asmcode[7:0]
end
- attribute \src "libresoc.v:11023.3-11059.6"
- process $proc$libresoc.v:11023$323
+ attribute \src "libresoc.v:11214.3-11250.6"
+ process $proc$libresoc.v:11214$363
assign { } { }
assign { } { }
assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0]
- attribute \src "libresoc.v:11024.5-11024.29"
+ attribute \src "libresoc.v:11215.5-11215.29"
switch \initial
- attribute \src "libresoc.v:11024.9-11024.17"
+ attribute \src "libresoc.v:11215.9-11215.17"
case 1'1
case
end
sync always
update \dec30_inv_a $0\dec30_inv_a[0:0]
end
- attribute \src "libresoc.v:11060.3-11096.6"
- process $proc$libresoc.v:11060$324
+ attribute \src "libresoc.v:11251.3-11287.6"
+ process $proc$libresoc.v:11251$364
assign { } { }
assign { } { }
assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0]
- attribute \src "libresoc.v:11061.5-11061.29"
+ attribute \src "libresoc.v:11252.5-11252.29"
switch \initial
- attribute \src "libresoc.v:11061.9-11061.17"
+ attribute \src "libresoc.v:11252.9-11252.17"
case 1'1
case
end
sync always
update \dec30_inv_out $0\dec30_inv_out[0:0]
end
- attribute \src "libresoc.v:11097.3-11133.6"
- process $proc$libresoc.v:11097$325
+ attribute \src "libresoc.v:11288.3-11324.6"
+ process $proc$libresoc.v:11288$365
assign { } { }
assign { } { }
assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0]
- attribute \src "libresoc.v:11098.5-11098.29"
+ attribute \src "libresoc.v:11289.5-11289.29"
switch \initial
- attribute \src "libresoc.v:11098.9-11098.17"
+ attribute \src "libresoc.v:11289.9-11289.17"
case 1'1
case
end
sync always
update \dec30_cry_out $0\dec30_cry_out[0:0]
end
- attribute \src "libresoc.v:11134.3-11170.6"
- process $proc$libresoc.v:11134$326
+ attribute \src "libresoc.v:11325.3-11361.6"
+ process $proc$libresoc.v:11325$366
assign { } { }
assign { } { }
assign $0\dec30_br[0:0] $1\dec30_br[0:0]
- attribute \src "libresoc.v:11135.5-11135.29"
+ attribute \src "libresoc.v:11326.5-11326.29"
switch \initial
- attribute \src "libresoc.v:11135.9-11135.17"
+ attribute \src "libresoc.v:11326.9-11326.17"
case 1'1
case
end
sync always
update \dec30_br $0\dec30_br[0:0]
end
- attribute \src "libresoc.v:11171.3-11207.6"
- process $proc$libresoc.v:11171$327
+ attribute \src "libresoc.v:11362.3-11398.6"
+ process $proc$libresoc.v:11362$367
assign { } { }
assign { } { }
assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0]
- attribute \src "libresoc.v:11172.5-11172.29"
+ attribute \src "libresoc.v:11363.5-11363.29"
switch \initial
- attribute \src "libresoc.v:11172.9-11172.17"
+ attribute \src "libresoc.v:11363.9-11363.17"
case 1'1
case
end
sync always
update \dec30_sgn_ext $0\dec30_sgn_ext[0:0]
end
- attribute \src "libresoc.v:11208.3-11244.6"
- process $proc$libresoc.v:11208$328
+ attribute \src "libresoc.v:11399.3-11435.6"
+ process $proc$libresoc.v:11399$368
assign { } { }
assign { } { }
assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0]
- attribute \src "libresoc.v:11209.5-11209.29"
+ attribute \src "libresoc.v:11400.5-11400.29"
switch \initial
- attribute \src "libresoc.v:11209.9-11209.17"
+ attribute \src "libresoc.v:11400.9-11400.17"
case 1'1
case
end
sync always
update \dec30_internal_op $0\dec30_internal_op[6:0]
end
- attribute \src "libresoc.v:11245.3-11281.6"
- process $proc$libresoc.v:11245$329
+ attribute \src "libresoc.v:11436.3-11472.6"
+ process $proc$libresoc.v:11436$369
assign { } { }
assign { } { }
assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0]
- attribute \src "libresoc.v:11246.5-11246.29"
+ attribute \src "libresoc.v:11437.5-11437.29"
switch \initial
- attribute \src "libresoc.v:11246.9-11246.17"
+ attribute \src "libresoc.v:11437.9-11437.17"
case 1'1
case
end
sync always
update \dec30_rsrv $0\dec30_rsrv[0:0]
end
- attribute \src "libresoc.v:11282.3-11318.6"
- process $proc$libresoc.v:11282$330
+ attribute \src "libresoc.v:11473.3-11509.6"
+ process $proc$libresoc.v:11473$370
assign { } { }
assign { } { }
assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0]
- attribute \src "libresoc.v:11283.5-11283.29"
+ attribute \src "libresoc.v:11474.5-11474.29"
switch \initial
- attribute \src "libresoc.v:11283.9-11283.17"
+ attribute \src "libresoc.v:11474.9-11474.17"
case 1'1
case
end
sync always
update \dec30_is_32b $0\dec30_is_32b[0:0]
end
- attribute \src "libresoc.v:11319.3-11355.6"
- process $proc$libresoc.v:11319$331
+ attribute \src "libresoc.v:11510.3-11546.6"
+ process $proc$libresoc.v:11510$371
assign { } { }
assign { } { }
assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0]
- attribute \src "libresoc.v:11320.5-11320.29"
+ attribute \src "libresoc.v:11511.5-11511.29"
switch \initial
- attribute \src "libresoc.v:11320.9-11320.17"
+ attribute \src "libresoc.v:11511.9-11511.17"
case 1'1
case
end
sync always
update \dec30_sgn $0\dec30_sgn[0:0]
end
- attribute \src "libresoc.v:11356.3-11392.6"
- process $proc$libresoc.v:11356$332
+ attribute \src "libresoc.v:11547.3-11583.6"
+ process $proc$libresoc.v:11547$372
assign { } { }
assign { } { }
assign $0\dec30_lk[0:0] $1\dec30_lk[0:0]
- attribute \src "libresoc.v:11357.5-11357.29"
+ attribute \src "libresoc.v:11548.5-11548.29"
switch \initial
- attribute \src "libresoc.v:11357.9-11357.17"
+ attribute \src "libresoc.v:11548.9-11548.17"
case 1'1
case
end
sync always
update \dec30_lk $0\dec30_lk[0:0]
end
- attribute \src "libresoc.v:11393.3-11429.6"
- process $proc$libresoc.v:11393$333
+ attribute \src "libresoc.v:11584.3-11620.6"
+ process $proc$libresoc.v:11584$373
assign { } { }
assign { } { }
assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0]
- attribute \src "libresoc.v:11394.5-11394.29"
+ attribute \src "libresoc.v:11585.5-11585.29"
switch \initial
- attribute \src "libresoc.v:11394.9-11394.17"
+ attribute \src "libresoc.v:11585.9-11585.17"
case 1'1
case
end
sync always
update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:11430.3-11466.6"
- process $proc$libresoc.v:11430$334
+ attribute \src "libresoc.v:11621.3-11657.6"
+ process $proc$libresoc.v:11621$374
assign { } { }
assign { } { }
assign $0\dec30_form[4:0] $1\dec30_form[4:0]
- attribute \src "libresoc.v:11431.5-11431.29"
+ attribute \src "libresoc.v:11622.5-11622.29"
switch \initial
- attribute \src "libresoc.v:11431.9-11431.17"
+ attribute \src "libresoc.v:11622.9-11622.17"
case 1'1
case
end
sync always
update \dec30_form $0\dec30_form[4:0]
end
- attribute \src "libresoc.v:11467.3-11503.6"
- process $proc$libresoc.v:11467$335
+ attribute \src "libresoc.v:11658.3-11694.6"
+ process $proc$libresoc.v:11658$375
assign { } { }
assign { } { }
assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0]
- attribute \src "libresoc.v:11468.5-11468.29"
+ attribute \src "libresoc.v:11659.5-11659.29"
switch \initial
- attribute \src "libresoc.v:11468.9-11468.17"
+ attribute \src "libresoc.v:11659.9-11659.17"
case 1'1
case
end
sync always
update \dec30_in1_sel $0\dec30_in1_sel[2:0]
end
- attribute \src "libresoc.v:11504.3-11540.6"
- process $proc$libresoc.v:11504$336
+ attribute \src "libresoc.v:11695.3-11731.6"
+ process $proc$libresoc.v:11695$376
assign { } { }
assign { } { }
assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0]
- attribute \src "libresoc.v:11505.5-11505.29"
+ attribute \src "libresoc.v:11696.5-11696.29"
switch \initial
- attribute \src "libresoc.v:11505.9-11505.17"
+ attribute \src "libresoc.v:11696.9-11696.17"
case 1'1
case
end
sync always
update \dec30_in2_sel $0\dec30_in2_sel[3:0]
end
- attribute \src "libresoc.v:11541.3-11577.6"
- process $proc$libresoc.v:11541$337
+ attribute \src "libresoc.v:11732.3-11768.6"
+ process $proc$libresoc.v:11732$377
assign { } { }
assign { } { }
assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0]
- attribute \src "libresoc.v:11542.5-11542.29"
+ attribute \src "libresoc.v:11733.5-11733.29"
switch \initial
- attribute \src "libresoc.v:11542.9-11542.17"
+ attribute \src "libresoc.v:11733.9-11733.17"
case 1'1
case
end
sync always
update \dec30_in3_sel $0\dec30_in3_sel[1:0]
end
- attribute \src "libresoc.v:11578.3-11614.6"
- process $proc$libresoc.v:11578$338
+ attribute \src "libresoc.v:11769.3-11805.6"
+ process $proc$libresoc.v:11769$378
assign { } { }
assign { } { }
assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0]
- attribute \src "libresoc.v:11579.5-11579.29"
+ attribute \src "libresoc.v:11770.5-11770.29"
switch \initial
- attribute \src "libresoc.v:11579.9-11579.17"
+ attribute \src "libresoc.v:11770.9-11770.17"
case 1'1
case
end
sync always
update \dec30_out_sel $0\dec30_out_sel[1:0]
end
- attribute \src "libresoc.v:11615.3-11651.6"
- process $proc$libresoc.v:11615$339
+ attribute \src "libresoc.v:11806.3-11842.6"
+ process $proc$libresoc.v:11806$379
assign { } { }
assign { } { }
assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0]
- attribute \src "libresoc.v:11616.5-11616.29"
+ attribute \src "libresoc.v:11807.5-11807.29"
switch \initial
- attribute \src "libresoc.v:11616.9-11616.17"
+ attribute \src "libresoc.v:11807.9-11807.17"
case 1'1
case
end
sync always
update \dec30_cr_in $0\dec30_cr_in[2:0]
end
- attribute \src "libresoc.v:11652.3-11688.6"
- process $proc$libresoc.v:11652$340
+ attribute \src "libresoc.v:11843.3-11879.6"
+ process $proc$libresoc.v:11843$380
assign { } { }
assign { } { }
assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0]
- attribute \src "libresoc.v:11653.5-11653.29"
+ attribute \src "libresoc.v:11844.5-11844.29"
switch \initial
- attribute \src "libresoc.v:11653.9-11653.17"
+ attribute \src "libresoc.v:11844.9-11844.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [4:1]
end
-attribute \src "libresoc.v:11694.1-18064.10"
+attribute \src "libresoc.v:11885.1-18255.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31"
attribute \generator "nMigen"
module \dec31
- attribute \src "libresoc.v:16763.3-16823.6"
+ attribute \src "libresoc.v:16954.3-17014.6"
wire width 8 $0\dec31_asmcode[7:0]
- attribute \src "libresoc.v:17617.3-17677.6"
+ attribute \src "libresoc.v:17808.3-17868.6"
wire $0\dec31_br[0:0]
- attribute \src "libresoc.v:17068.3-17128.6"
+ attribute \src "libresoc.v:17259.3-17319.6"
wire width 3 $0\dec31_cr_in[2:0]
- attribute \src "libresoc.v:17129.3-17189.6"
+ attribute \src "libresoc.v:17320.3-17380.6"
wire width 3 $0\dec31_cr_out[2:0]
- attribute \src "libresoc.v:17373.3-17433.6"
+ attribute \src "libresoc.v:17564.3-17624.6"
wire width 2 $0\dec31_cry_in[1:0]
- attribute \src "libresoc.v:17556.3-17616.6"
+ attribute \src "libresoc.v:17747.3-17807.6"
wire $0\dec31_cry_out[0:0]
- attribute \src "libresoc.v:16702.3-16762.6"
+ attribute \src "libresoc.v:16893.3-16953.6"
wire width 5 $0\dec31_form[4:0]
- attribute \src "libresoc.v:16580.3-16640.6"
+ attribute \src "libresoc.v:16771.3-16831.6"
wire width 12 $0\dec31_function_unit[11:0]
- attribute \src "libresoc.v:16824.3-16884.6"
+ attribute \src "libresoc.v:17015.3-17075.6"
wire width 3 $0\dec31_in1_sel[2:0]
- attribute \src "libresoc.v:16885.3-16945.6"
+ attribute \src "libresoc.v:17076.3-17136.6"
wire width 4 $0\dec31_in2_sel[3:0]
- attribute \src "libresoc.v:16946.3-17006.6"
+ attribute \src "libresoc.v:17137.3-17197.6"
wire width 2 $0\dec31_in3_sel[1:0]
- attribute \src "libresoc.v:16641.3-16701.6"
+ attribute \src "libresoc.v:16832.3-16892.6"
wire width 7 $0\dec31_internal_op[6:0]
- attribute \src "libresoc.v:17434.3-17494.6"
+ attribute \src "libresoc.v:17625.3-17685.6"
wire $0\dec31_inv_a[0:0]
- attribute \src "libresoc.v:17495.3-17555.6"
+ attribute \src "libresoc.v:17686.3-17746.6"
wire $0\dec31_inv_out[0:0]
- attribute \src "libresoc.v:17800.3-17860.6"
+ attribute \src "libresoc.v:17991.3-18051.6"
wire $0\dec31_is_32b[0:0]
- attribute \src "libresoc.v:17190.3-17250.6"
+ attribute \src "libresoc.v:17381.3-17441.6"
wire width 4 $0\dec31_ldst_len[3:0]
- attribute \src "libresoc.v:17922.3-17982.6"
+ attribute \src "libresoc.v:18113.3-18173.6"
wire $0\dec31_lk[0:0]
- attribute \src "libresoc.v:17007.3-17067.6"
+ attribute \src "libresoc.v:17198.3-17258.6"
wire width 2 $0\dec31_out_sel[1:0]
- attribute \src "libresoc.v:17312.3-17372.6"
+ attribute \src "libresoc.v:17503.3-17563.6"
wire width 2 $0\dec31_rc_sel[1:0]
- attribute \src "libresoc.v:17739.3-17799.6"
+ attribute \src "libresoc.v:17930.3-17990.6"
wire $0\dec31_rsrv[0:0]
- attribute \src "libresoc.v:17983.3-18043.6"
+ attribute \src "libresoc.v:18174.3-18234.6"
wire $0\dec31_sgl_pipe[0:0]
- attribute \src "libresoc.v:17861.3-17921.6"
+ attribute \src "libresoc.v:18052.3-18112.6"
wire $0\dec31_sgn[0:0]
- attribute \src "libresoc.v:17678.3-17738.6"
+ attribute \src "libresoc.v:17869.3-17929.6"
wire $0\dec31_sgn_ext[0:0]
- attribute \src "libresoc.v:17251.3-17311.6"
+ attribute \src "libresoc.v:17442.3-17502.6"
wire width 2 $0\dec31_upd[1:0]
- attribute \src "libresoc.v:11695.7-11695.20"
+ attribute \src "libresoc.v:11886.7-11886.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:16763.3-16823.6"
+ attribute \src "libresoc.v:16954.3-17014.6"
wire width 8 $1\dec31_asmcode[7:0]
- attribute \src "libresoc.v:17617.3-17677.6"
+ attribute \src "libresoc.v:17808.3-17868.6"
wire $1\dec31_br[0:0]
- attribute \src "libresoc.v:17068.3-17128.6"
+ attribute \src "libresoc.v:17259.3-17319.6"
wire width 3 $1\dec31_cr_in[2:0]
- attribute \src "libresoc.v:17129.3-17189.6"
+ attribute \src "libresoc.v:17320.3-17380.6"
wire width 3 $1\dec31_cr_out[2:0]
- attribute \src "libresoc.v:17373.3-17433.6"
+ attribute \src "libresoc.v:17564.3-17624.6"
wire width 2 $1\dec31_cry_in[1:0]
- attribute \src "libresoc.v:17556.3-17616.6"
+ attribute \src "libresoc.v:17747.3-17807.6"
wire $1\dec31_cry_out[0:0]
- attribute \src "libresoc.v:16702.3-16762.6"
+ attribute \src "libresoc.v:16893.3-16953.6"
wire width 5 $1\dec31_form[4:0]
- attribute \src "libresoc.v:16580.3-16640.6"
+ attribute \src "libresoc.v:16771.3-16831.6"
wire width 12 $1\dec31_function_unit[11:0]
- attribute \src "libresoc.v:16824.3-16884.6"
+ attribute \src "libresoc.v:17015.3-17075.6"
wire width 3 $1\dec31_in1_sel[2:0]
- attribute \src "libresoc.v:16885.3-16945.6"
+ attribute \src "libresoc.v:17076.3-17136.6"
wire width 4 $1\dec31_in2_sel[3:0]
- attribute \src "libresoc.v:16946.3-17006.6"
+ attribute \src "libresoc.v:17137.3-17197.6"
wire width 2 $1\dec31_in3_sel[1:0]
- attribute \src "libresoc.v:16641.3-16701.6"
+ attribute \src "libresoc.v:16832.3-16892.6"
wire width 7 $1\dec31_internal_op[6:0]
- attribute \src "libresoc.v:17434.3-17494.6"
+ attribute \src "libresoc.v:17625.3-17685.6"
wire $1\dec31_inv_a[0:0]
- attribute \src "libresoc.v:17495.3-17555.6"
+ attribute \src "libresoc.v:17686.3-17746.6"
wire $1\dec31_inv_out[0:0]
- attribute \src "libresoc.v:17800.3-17860.6"
+ attribute \src "libresoc.v:17991.3-18051.6"
wire $1\dec31_is_32b[0:0]
- attribute \src "libresoc.v:17190.3-17250.6"
+ attribute \src "libresoc.v:17381.3-17441.6"
wire width 4 $1\dec31_ldst_len[3:0]
- attribute \src "libresoc.v:17922.3-17982.6"
+ attribute \src "libresoc.v:18113.3-18173.6"
wire $1\dec31_lk[0:0]
- attribute \src "libresoc.v:17007.3-17067.6"
+ attribute \src "libresoc.v:17198.3-17258.6"
wire width 2 $1\dec31_out_sel[1:0]
- attribute \src "libresoc.v:17312.3-17372.6"
+ attribute \src "libresoc.v:17503.3-17563.6"
wire width 2 $1\dec31_rc_sel[1:0]
- attribute \src "libresoc.v:17739.3-17799.6"
+ attribute \src "libresoc.v:17930.3-17990.6"
wire $1\dec31_rsrv[0:0]
- attribute \src "libresoc.v:17983.3-18043.6"
+ attribute \src "libresoc.v:18174.3-18234.6"
wire $1\dec31_sgl_pipe[0:0]
- attribute \src "libresoc.v:17861.3-17921.6"
+ attribute \src "libresoc.v:18052.3-18112.6"
wire $1\dec31_sgn[0:0]
- attribute \src "libresoc.v:17678.3-17738.6"
+ attribute \src "libresoc.v:17869.3-17929.6"
wire $1\dec31_sgn_ext[0:0]
- attribute \src "libresoc.v:17251.3-17311.6"
+ attribute \src "libresoc.v:17442.3-17502.6"
wire width 2 $1\dec31_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_upd
- attribute \src "libresoc.v:11695.7-11695.15"
+ attribute \src "libresoc.v:11886.7-11886.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326"
wire width 5 \opc_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 10 \opcode_switch
attribute \module_not_derived 1
- attribute \src "libresoc.v:16094.18-16120.4"
+ attribute \src "libresoc.v:16285.18-16311.4"
cell \dec31_dec_sub0 \dec31_dec_sub0
connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode
connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br
connect \opcode_in \dec31_dec_sub0_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16121.19-16147.4"
+ attribute \src "libresoc.v:16312.19-16338.4"
cell \dec31_dec_sub10 \dec31_dec_sub10
connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode
connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br
connect \opcode_in \dec31_dec_sub10_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16148.19-16174.4"
+ attribute \src "libresoc.v:16339.19-16365.4"
cell \dec31_dec_sub11 \dec31_dec_sub11
connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode
connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br
connect \opcode_in \dec31_dec_sub11_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16175.19-16201.4"
+ attribute \src "libresoc.v:16366.19-16392.4"
cell \dec31_dec_sub15 \dec31_dec_sub15
connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode
connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br
connect \opcode_in \dec31_dec_sub15_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16202.19-16228.4"
+ attribute \src "libresoc.v:16393.19-16419.4"
cell \dec31_dec_sub16 \dec31_dec_sub16
connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode
connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br
connect \opcode_in \dec31_dec_sub16_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16229.19-16255.4"
+ attribute \src "libresoc.v:16420.19-16446.4"
cell \dec31_dec_sub18 \dec31_dec_sub18
connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode
connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br
connect \opcode_in \dec31_dec_sub18_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16256.19-16282.4"
+ attribute \src "libresoc.v:16447.19-16473.4"
cell \dec31_dec_sub19 \dec31_dec_sub19
connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode
connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br
connect \opcode_in \dec31_dec_sub19_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16283.19-16309.4"
+ attribute \src "libresoc.v:16474.19-16500.4"
cell \dec31_dec_sub20 \dec31_dec_sub20
connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode
connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br
connect \opcode_in \dec31_dec_sub20_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16310.19-16336.4"
+ attribute \src "libresoc.v:16501.19-16527.4"
cell \dec31_dec_sub21 \dec31_dec_sub21
connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode
connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br
connect \opcode_in \dec31_dec_sub21_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16337.19-16363.4"
+ attribute \src "libresoc.v:16528.19-16554.4"
cell \dec31_dec_sub22 \dec31_dec_sub22
connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode
connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br
connect \opcode_in \dec31_dec_sub22_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16364.19-16390.4"
+ attribute \src "libresoc.v:16555.19-16581.4"
cell \dec31_dec_sub23 \dec31_dec_sub23
connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode
connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br
connect \opcode_in \dec31_dec_sub23_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16391.19-16417.4"
+ attribute \src "libresoc.v:16582.19-16608.4"
cell \dec31_dec_sub24 \dec31_dec_sub24
connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode
connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br
connect \opcode_in \dec31_dec_sub24_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16418.19-16444.4"
+ attribute \src "libresoc.v:16609.19-16635.4"
cell \dec31_dec_sub26 \dec31_dec_sub26
connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode
connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br
connect \opcode_in \dec31_dec_sub26_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16445.19-16471.4"
+ attribute \src "libresoc.v:16636.19-16662.4"
cell \dec31_dec_sub27 \dec31_dec_sub27
connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode
connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br
connect \opcode_in \dec31_dec_sub27_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16472.19-16498.4"
+ attribute \src "libresoc.v:16663.19-16689.4"
cell \dec31_dec_sub28 \dec31_dec_sub28
connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode
connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br
connect \opcode_in \dec31_dec_sub28_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16499.18-16525.4"
+ attribute \src "libresoc.v:16690.18-16716.4"
cell \dec31_dec_sub4 \dec31_dec_sub4
connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode
connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br
connect \opcode_in \dec31_dec_sub4_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16526.18-16552.4"
+ attribute \src "libresoc.v:16717.18-16743.4"
cell \dec31_dec_sub8 \dec31_dec_sub8
connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode
connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br
connect \opcode_in \dec31_dec_sub8_opcode_in
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:16553.18-16579.4"
+ attribute \src "libresoc.v:16744.18-16770.4"
cell \dec31_dec_sub9 \dec31_dec_sub9
connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode
connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br
connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd
connect \opcode_in \dec31_dec_sub9_opcode_in
end
- attribute \src "libresoc.v:11695.7-11695.20"
- process $proc$libresoc.v:11695$366
+ attribute \src "libresoc.v:11886.7-11886.20"
+ process $proc$libresoc.v:11886$406
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:16580.3-16640.6"
- process $proc$libresoc.v:16580$342
+ attribute \src "libresoc.v:16771.3-16831.6"
+ process $proc$libresoc.v:16771$382
assign { } { }
assign { } { }
assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0]
- attribute \src "libresoc.v:16581.5-16581.29"
+ attribute \src "libresoc.v:16772.5-16772.29"
switch \initial
- attribute \src "libresoc.v:16581.9-16581.17"
+ attribute \src "libresoc.v:16772.9-16772.17"
case 1'1
case
end
sync always
update \dec31_function_unit $0\dec31_function_unit[11:0]
end
- attribute \src "libresoc.v:16641.3-16701.6"
- process $proc$libresoc.v:16641$343
+ attribute \src "libresoc.v:16832.3-16892.6"
+ process $proc$libresoc.v:16832$383
assign { } { }
assign { } { }
assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0]
- attribute \src "libresoc.v:16642.5-16642.29"
+ attribute \src "libresoc.v:16833.5-16833.29"
switch \initial
- attribute \src "libresoc.v:16642.9-16642.17"
+ attribute \src "libresoc.v:16833.9-16833.17"
case 1'1
case
end
sync always
update \dec31_internal_op $0\dec31_internal_op[6:0]
end
- attribute \src "libresoc.v:16702.3-16762.6"
- process $proc$libresoc.v:16702$344
+ attribute \src "libresoc.v:16893.3-16953.6"
+ process $proc$libresoc.v:16893$384
assign { } { }
assign { } { }
assign $0\dec31_form[4:0] $1\dec31_form[4:0]
- attribute \src "libresoc.v:16703.5-16703.29"
+ attribute \src "libresoc.v:16894.5-16894.29"
switch \initial
- attribute \src "libresoc.v:16703.9-16703.17"
+ attribute \src "libresoc.v:16894.9-16894.17"
case 1'1
case
end
sync always
update \dec31_form $0\dec31_form[4:0]
end
- attribute \src "libresoc.v:16763.3-16823.6"
- process $proc$libresoc.v:16763$345
+ attribute \src "libresoc.v:16954.3-17014.6"
+ process $proc$libresoc.v:16954$385
assign { } { }
assign { } { }
assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0]
- attribute \src "libresoc.v:16764.5-16764.29"
+ attribute \src "libresoc.v:16955.5-16955.29"
switch \initial
- attribute \src "libresoc.v:16764.9-16764.17"
+ attribute \src "libresoc.v:16955.9-16955.17"
case 1'1
case
end
sync always
update \dec31_asmcode $0\dec31_asmcode[7:0]
end
- attribute \src "libresoc.v:16824.3-16884.6"
- process $proc$libresoc.v:16824$346
+ attribute \src "libresoc.v:17015.3-17075.6"
+ process $proc$libresoc.v:17015$386
assign { } { }
assign { } { }
assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0]
- attribute \src "libresoc.v:16825.5-16825.29"
+ attribute \src "libresoc.v:17016.5-17016.29"
switch \initial
- attribute \src "libresoc.v:16825.9-16825.17"
+ attribute \src "libresoc.v:17016.9-17016.17"
case 1'1
case
end
sync always
update \dec31_in1_sel $0\dec31_in1_sel[2:0]
end
- attribute \src "libresoc.v:16885.3-16945.6"
- process $proc$libresoc.v:16885$347
+ attribute \src "libresoc.v:17076.3-17136.6"
+ process $proc$libresoc.v:17076$387
assign { } { }
assign { } { }
assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0]
- attribute \src "libresoc.v:16886.5-16886.29"
+ attribute \src "libresoc.v:17077.5-17077.29"
switch \initial
- attribute \src "libresoc.v:16886.9-16886.17"
+ attribute \src "libresoc.v:17077.9-17077.17"
case 1'1
case
end
sync always
update \dec31_in2_sel $0\dec31_in2_sel[3:0]
end
- attribute \src "libresoc.v:16946.3-17006.6"
- process $proc$libresoc.v:16946$348
+ attribute \src "libresoc.v:17137.3-17197.6"
+ process $proc$libresoc.v:17137$388
assign { } { }
assign { } { }
assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0]
- attribute \src "libresoc.v:16947.5-16947.29"
+ attribute \src "libresoc.v:17138.5-17138.29"
switch \initial
- attribute \src "libresoc.v:16947.9-16947.17"
+ attribute \src "libresoc.v:17138.9-17138.17"
case 1'1
case
end
sync always
update \dec31_in3_sel $0\dec31_in3_sel[1:0]
end
- attribute \src "libresoc.v:17007.3-17067.6"
- process $proc$libresoc.v:17007$349
+ attribute \src "libresoc.v:17198.3-17258.6"
+ process $proc$libresoc.v:17198$389
assign { } { }
assign { } { }
assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0]
- attribute \src "libresoc.v:17008.5-17008.29"
+ attribute \src "libresoc.v:17199.5-17199.29"
switch \initial
- attribute \src "libresoc.v:17008.9-17008.17"
+ attribute \src "libresoc.v:17199.9-17199.17"
case 1'1
case
end
sync always
update \dec31_out_sel $0\dec31_out_sel[1:0]
end
- attribute \src "libresoc.v:17068.3-17128.6"
- process $proc$libresoc.v:17068$350
+ attribute \src "libresoc.v:17259.3-17319.6"
+ process $proc$libresoc.v:17259$390
assign { } { }
assign { } { }
assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0]
- attribute \src "libresoc.v:17069.5-17069.29"
+ attribute \src "libresoc.v:17260.5-17260.29"
switch \initial
- attribute \src "libresoc.v:17069.9-17069.17"
+ attribute \src "libresoc.v:17260.9-17260.17"
case 1'1
case
end
sync always
update \dec31_cr_in $0\dec31_cr_in[2:0]
end
- attribute \src "libresoc.v:17129.3-17189.6"
- process $proc$libresoc.v:17129$351
+ attribute \src "libresoc.v:17320.3-17380.6"
+ process $proc$libresoc.v:17320$391
assign { } { }
assign { } { }
assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0]
- attribute \src "libresoc.v:17130.5-17130.29"
+ attribute \src "libresoc.v:17321.5-17321.29"
switch \initial
- attribute \src "libresoc.v:17130.9-17130.17"
+ attribute \src "libresoc.v:17321.9-17321.17"
case 1'1
case
end
sync always
update \dec31_cr_out $0\dec31_cr_out[2:0]
end
- attribute \src "libresoc.v:17190.3-17250.6"
- process $proc$libresoc.v:17190$352
+ attribute \src "libresoc.v:17381.3-17441.6"
+ process $proc$libresoc.v:17381$392
assign { } { }
assign { } { }
assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0]
- attribute \src "libresoc.v:17191.5-17191.29"
+ attribute \src "libresoc.v:17382.5-17382.29"
switch \initial
- attribute \src "libresoc.v:17191.9-17191.17"
+ attribute \src "libresoc.v:17382.9-17382.17"
case 1'1
case
end
sync always
update \dec31_ldst_len $0\dec31_ldst_len[3:0]
end
- attribute \src "libresoc.v:17251.3-17311.6"
- process $proc$libresoc.v:17251$353
+ attribute \src "libresoc.v:17442.3-17502.6"
+ process $proc$libresoc.v:17442$393
assign { } { }
assign { } { }
assign $0\dec31_upd[1:0] $1\dec31_upd[1:0]
- attribute \src "libresoc.v:17252.5-17252.29"
+ attribute \src "libresoc.v:17443.5-17443.29"
switch \initial
- attribute \src "libresoc.v:17252.9-17252.17"
+ attribute \src "libresoc.v:17443.9-17443.17"
case 1'1
case
end
sync always
update \dec31_upd $0\dec31_upd[1:0]
end
- attribute \src "libresoc.v:17312.3-17372.6"
- process $proc$libresoc.v:17312$354
+ attribute \src "libresoc.v:17503.3-17563.6"
+ process $proc$libresoc.v:17503$394
assign { } { }
assign { } { }
assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0]
- attribute \src "libresoc.v:17313.5-17313.29"
+ attribute \src "libresoc.v:17504.5-17504.29"
switch \initial
- attribute \src "libresoc.v:17313.9-17313.17"
+ attribute \src "libresoc.v:17504.9-17504.17"
case 1'1
case
end
sync always
update \dec31_rc_sel $0\dec31_rc_sel[1:0]
end
- attribute \src "libresoc.v:17373.3-17433.6"
- process $proc$libresoc.v:17373$355
+ attribute \src "libresoc.v:17564.3-17624.6"
+ process $proc$libresoc.v:17564$395
assign { } { }
assign { } { }
assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0]
- attribute \src "libresoc.v:17374.5-17374.29"
+ attribute \src "libresoc.v:17565.5-17565.29"
switch \initial
- attribute \src "libresoc.v:17374.9-17374.17"
+ attribute \src "libresoc.v:17565.9-17565.17"
case 1'1
case
end
sync always
update \dec31_cry_in $0\dec31_cry_in[1:0]
end
- attribute \src "libresoc.v:17434.3-17494.6"
- process $proc$libresoc.v:17434$356
+ attribute \src "libresoc.v:17625.3-17685.6"
+ process $proc$libresoc.v:17625$396
assign { } { }
assign { } { }
assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0]
- attribute \src "libresoc.v:17435.5-17435.29"
+ attribute \src "libresoc.v:17626.5-17626.29"
switch \initial
- attribute \src "libresoc.v:17435.9-17435.17"
+ attribute \src "libresoc.v:17626.9-17626.17"
case 1'1
case
end
sync always
update \dec31_inv_a $0\dec31_inv_a[0:0]
end
- attribute \src "libresoc.v:17495.3-17555.6"
- process $proc$libresoc.v:17495$357
+ attribute \src "libresoc.v:17686.3-17746.6"
+ process $proc$libresoc.v:17686$397
assign { } { }
assign { } { }
assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0]
- attribute \src "libresoc.v:17496.5-17496.29"
+ attribute \src "libresoc.v:17687.5-17687.29"
switch \initial
- attribute \src "libresoc.v:17496.9-17496.17"
+ attribute \src "libresoc.v:17687.9-17687.17"
case 1'1
case
end
sync always
update \dec31_inv_out $0\dec31_inv_out[0:0]
end
- attribute \src "libresoc.v:17556.3-17616.6"
- process $proc$libresoc.v:17556$358
+ attribute \src "libresoc.v:17747.3-17807.6"
+ process $proc$libresoc.v:17747$398
assign { } { }
assign { } { }
assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0]
- attribute \src "libresoc.v:17557.5-17557.29"
+ attribute \src "libresoc.v:17748.5-17748.29"
switch \initial
- attribute \src "libresoc.v:17557.9-17557.17"
+ attribute \src "libresoc.v:17748.9-17748.17"
case 1'1
case
end
sync always
update \dec31_cry_out $0\dec31_cry_out[0:0]
end
- attribute \src "libresoc.v:17617.3-17677.6"
- process $proc$libresoc.v:17617$359
+ attribute \src "libresoc.v:17808.3-17868.6"
+ process $proc$libresoc.v:17808$399
assign { } { }
assign { } { }
assign $0\dec31_br[0:0] $1\dec31_br[0:0]
- attribute \src "libresoc.v:17618.5-17618.29"
+ attribute \src "libresoc.v:17809.5-17809.29"
switch \initial
- attribute \src "libresoc.v:17618.9-17618.17"
+ attribute \src "libresoc.v:17809.9-17809.17"
case 1'1
case
end
sync always
update \dec31_br $0\dec31_br[0:0]
end
- attribute \src "libresoc.v:17678.3-17738.6"
- process $proc$libresoc.v:17678$360
+ attribute \src "libresoc.v:17869.3-17929.6"
+ process $proc$libresoc.v:17869$400
assign { } { }
assign { } { }
assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0]
- attribute \src "libresoc.v:17679.5-17679.29"
+ attribute \src "libresoc.v:17870.5-17870.29"
switch \initial
- attribute \src "libresoc.v:17679.9-17679.17"
+ attribute \src "libresoc.v:17870.9-17870.17"
case 1'1
case
end
sync always
update \dec31_sgn_ext $0\dec31_sgn_ext[0:0]
end
- attribute \src "libresoc.v:17739.3-17799.6"
- process $proc$libresoc.v:17739$361
+ attribute \src "libresoc.v:17930.3-17990.6"
+ process $proc$libresoc.v:17930$401
assign { } { }
assign { } { }
assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0]
- attribute \src "libresoc.v:17740.5-17740.29"
+ attribute \src "libresoc.v:17931.5-17931.29"
switch \initial
- attribute \src "libresoc.v:17740.9-17740.17"
+ attribute \src "libresoc.v:17931.9-17931.17"
case 1'1
case
end
sync always
update \dec31_rsrv $0\dec31_rsrv[0:0]
end
- attribute \src "libresoc.v:17800.3-17860.6"
- process $proc$libresoc.v:17800$362
+ attribute \src "libresoc.v:17991.3-18051.6"
+ process $proc$libresoc.v:17991$402
assign { } { }
assign { } { }
assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0]
- attribute \src "libresoc.v:17801.5-17801.29"
+ attribute \src "libresoc.v:17992.5-17992.29"
switch \initial
- attribute \src "libresoc.v:17801.9-17801.17"
+ attribute \src "libresoc.v:17992.9-17992.17"
case 1'1
case
end
sync always
update \dec31_is_32b $0\dec31_is_32b[0:0]
end
- attribute \src "libresoc.v:17861.3-17921.6"
- process $proc$libresoc.v:17861$363
+ attribute \src "libresoc.v:18052.3-18112.6"
+ process $proc$libresoc.v:18052$403
assign { } { }
assign { } { }
assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0]
- attribute \src "libresoc.v:17862.5-17862.29"
+ attribute \src "libresoc.v:18053.5-18053.29"
switch \initial
- attribute \src "libresoc.v:17862.9-17862.17"
+ attribute \src "libresoc.v:18053.9-18053.17"
case 1'1
case
end
sync always
update \dec31_sgn $0\dec31_sgn[0:0]
end
- attribute \src "libresoc.v:17922.3-17982.6"
- process $proc$libresoc.v:17922$364
+ attribute \src "libresoc.v:18113.3-18173.6"
+ process $proc$libresoc.v:18113$404
assign { } { }
assign { } { }
assign $0\dec31_lk[0:0] $1\dec31_lk[0:0]
- attribute \src "libresoc.v:17923.5-17923.29"
+ attribute \src "libresoc.v:18114.5-18114.29"
switch \initial
- attribute \src "libresoc.v:17923.9-17923.17"
+ attribute \src "libresoc.v:18114.9-18114.17"
case 1'1
case
end
sync always
update \dec31_lk $0\dec31_lk[0:0]
end
- attribute \src "libresoc.v:17983.3-18043.6"
- process $proc$libresoc.v:17983$365
+ attribute \src "libresoc.v:18174.3-18234.6"
+ process $proc$libresoc.v:18174$405
assign { } { }
assign { } { }
assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0]
- attribute \src "libresoc.v:17984.5-17984.29"
+ attribute \src "libresoc.v:18175.5-18175.29"
switch \initial
- attribute \src "libresoc.v:17984.9-17984.17"
+ attribute \src "libresoc.v:18175.9-18175.17"
case 1'1
case
end
connect \opc_in \opcode_switch [4:0]
connect \opcode_switch \opcode_in [10:1]
end
-attribute \src "libresoc.v:18068.1-18783.10"
+attribute \src "libresoc.v:18259.1-18974.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub0"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0"
attribute \generator "nMigen"
module \dec31_dec_sub0
- attribute \src "libresoc.v:18421.3-18439.6"
+ attribute \src "libresoc.v:18612.3-18630.6"
wire width 8 $0\dec31_dec_sub0_asmcode[7:0]
- attribute \src "libresoc.v:18497.3-18515.6"
+ attribute \src "libresoc.v:18688.3-18706.6"
wire $0\dec31_dec_sub0_br[0:0]
- attribute \src "libresoc.v:18744.3-18762.6"
+ attribute \src "libresoc.v:18935.3-18953.6"
wire width 3 $0\dec31_dec_sub0_cr_in[2:0]
- attribute \src "libresoc.v:18763.3-18781.6"
+ attribute \src "libresoc.v:18954.3-18972.6"
wire width 3 $0\dec31_dec_sub0_cr_out[2:0]
- attribute \src "libresoc.v:18402.3-18420.6"
+ attribute \src "libresoc.v:18593.3-18611.6"
wire width 2 $0\dec31_dec_sub0_cry_in[1:0]
- attribute \src "libresoc.v:18478.3-18496.6"
+ attribute \src "libresoc.v:18669.3-18687.6"
wire $0\dec31_dec_sub0_cry_out[0:0]
- attribute \src "libresoc.v:18649.3-18667.6"
+ attribute \src "libresoc.v:18840.3-18858.6"
wire width 5 $0\dec31_dec_sub0_form[4:0]
- attribute \src "libresoc.v:18326.3-18344.6"
+ attribute \src "libresoc.v:18517.3-18535.6"
wire width 12 $0\dec31_dec_sub0_function_unit[11:0]
- attribute \src "libresoc.v:18668.3-18686.6"
+ attribute \src "libresoc.v:18859.3-18877.6"
wire width 3 $0\dec31_dec_sub0_in1_sel[2:0]
- attribute \src "libresoc.v:18687.3-18705.6"
+ attribute \src "libresoc.v:18878.3-18896.6"
wire width 4 $0\dec31_dec_sub0_in2_sel[3:0]
- attribute \src "libresoc.v:18706.3-18724.6"
+ attribute \src "libresoc.v:18897.3-18915.6"
wire width 2 $0\dec31_dec_sub0_in3_sel[1:0]
- attribute \src "libresoc.v:18535.3-18553.6"
+ attribute \src "libresoc.v:18726.3-18744.6"
wire width 7 $0\dec31_dec_sub0_internal_op[6:0]
- attribute \src "libresoc.v:18440.3-18458.6"
+ attribute \src "libresoc.v:18631.3-18649.6"
wire $0\dec31_dec_sub0_inv_a[0:0]
- attribute \src "libresoc.v:18459.3-18477.6"
+ attribute \src "libresoc.v:18650.3-18668.6"
wire $0\dec31_dec_sub0_inv_out[0:0]
- attribute \src "libresoc.v:18573.3-18591.6"
+ attribute \src "libresoc.v:18764.3-18782.6"
wire $0\dec31_dec_sub0_is_32b[0:0]
- attribute \src "libresoc.v:18345.3-18363.6"
+ attribute \src "libresoc.v:18536.3-18554.6"
wire width 4 $0\dec31_dec_sub0_ldst_len[3:0]
- attribute \src "libresoc.v:18611.3-18629.6"
+ attribute \src "libresoc.v:18802.3-18820.6"
wire $0\dec31_dec_sub0_lk[0:0]
- attribute \src "libresoc.v:18725.3-18743.6"
+ attribute \src "libresoc.v:18916.3-18934.6"
wire width 2 $0\dec31_dec_sub0_out_sel[1:0]
- attribute \src "libresoc.v:18383.3-18401.6"
+ attribute \src "libresoc.v:18574.3-18592.6"
wire width 2 $0\dec31_dec_sub0_rc_sel[1:0]
- attribute \src "libresoc.v:18554.3-18572.6"
+ attribute \src "libresoc.v:18745.3-18763.6"
wire $0\dec31_dec_sub0_rsrv[0:0]
- attribute \src "libresoc.v:18630.3-18648.6"
+ attribute \src "libresoc.v:18821.3-18839.6"
wire $0\dec31_dec_sub0_sgl_pipe[0:0]
- attribute \src "libresoc.v:18592.3-18610.6"
+ attribute \src "libresoc.v:18783.3-18801.6"
wire $0\dec31_dec_sub0_sgn[0:0]
- attribute \src "libresoc.v:18516.3-18534.6"
+ attribute \src "libresoc.v:18707.3-18725.6"
wire $0\dec31_dec_sub0_sgn_ext[0:0]
- attribute \src "libresoc.v:18364.3-18382.6"
+ attribute \src "libresoc.v:18555.3-18573.6"
wire width 2 $0\dec31_dec_sub0_upd[1:0]
- attribute \src "libresoc.v:18069.7-18069.20"
+ attribute \src "libresoc.v:18260.7-18260.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:18421.3-18439.6"
+ attribute \src "libresoc.v:18612.3-18630.6"
wire width 8 $1\dec31_dec_sub0_asmcode[7:0]
- attribute \src "libresoc.v:18497.3-18515.6"
+ attribute \src "libresoc.v:18688.3-18706.6"
wire $1\dec31_dec_sub0_br[0:0]
- attribute \src "libresoc.v:18744.3-18762.6"
+ attribute \src "libresoc.v:18935.3-18953.6"
wire width 3 $1\dec31_dec_sub0_cr_in[2:0]
- attribute \src "libresoc.v:18763.3-18781.6"
+ attribute \src "libresoc.v:18954.3-18972.6"
wire width 3 $1\dec31_dec_sub0_cr_out[2:0]
- attribute \src "libresoc.v:18402.3-18420.6"
+ attribute \src "libresoc.v:18593.3-18611.6"
wire width 2 $1\dec31_dec_sub0_cry_in[1:0]
- attribute \src "libresoc.v:18478.3-18496.6"
+ attribute \src "libresoc.v:18669.3-18687.6"
wire $1\dec31_dec_sub0_cry_out[0:0]
- attribute \src "libresoc.v:18649.3-18667.6"
+ attribute \src "libresoc.v:18840.3-18858.6"
wire width 5 $1\dec31_dec_sub0_form[4:0]
- attribute \src "libresoc.v:18326.3-18344.6"
+ attribute \src "libresoc.v:18517.3-18535.6"
wire width 12 $1\dec31_dec_sub0_function_unit[11:0]
- attribute \src "libresoc.v:18668.3-18686.6"
+ attribute \src "libresoc.v:18859.3-18877.6"
wire width 3 $1\dec31_dec_sub0_in1_sel[2:0]
- attribute \src "libresoc.v:18687.3-18705.6"
+ attribute \src "libresoc.v:18878.3-18896.6"
wire width 4 $1\dec31_dec_sub0_in2_sel[3:0]
- attribute \src "libresoc.v:18706.3-18724.6"
+ attribute \src "libresoc.v:18897.3-18915.6"
wire width 2 $1\dec31_dec_sub0_in3_sel[1:0]
- attribute \src "libresoc.v:18535.3-18553.6"
+ attribute \src "libresoc.v:18726.3-18744.6"
wire width 7 $1\dec31_dec_sub0_internal_op[6:0]
- attribute \src "libresoc.v:18440.3-18458.6"
+ attribute \src "libresoc.v:18631.3-18649.6"
wire $1\dec31_dec_sub0_inv_a[0:0]
- attribute \src "libresoc.v:18459.3-18477.6"
+ attribute \src "libresoc.v:18650.3-18668.6"
wire $1\dec31_dec_sub0_inv_out[0:0]
- attribute \src "libresoc.v:18573.3-18591.6"
+ attribute \src "libresoc.v:18764.3-18782.6"
wire $1\dec31_dec_sub0_is_32b[0:0]
- attribute \src "libresoc.v:18345.3-18363.6"
+ attribute \src "libresoc.v:18536.3-18554.6"
wire width 4 $1\dec31_dec_sub0_ldst_len[3:0]
- attribute \src "libresoc.v:18611.3-18629.6"
+ attribute \src "libresoc.v:18802.3-18820.6"
wire $1\dec31_dec_sub0_lk[0:0]
- attribute \src "libresoc.v:18725.3-18743.6"
+ attribute \src "libresoc.v:18916.3-18934.6"
wire width 2 $1\dec31_dec_sub0_out_sel[1:0]
- attribute \src "libresoc.v:18383.3-18401.6"
+ attribute \src "libresoc.v:18574.3-18592.6"
wire width 2 $1\dec31_dec_sub0_rc_sel[1:0]
- attribute \src "libresoc.v:18554.3-18572.6"
+ attribute \src "libresoc.v:18745.3-18763.6"
wire $1\dec31_dec_sub0_rsrv[0:0]
- attribute \src "libresoc.v:18630.3-18648.6"
+ attribute \src "libresoc.v:18821.3-18839.6"
wire $1\dec31_dec_sub0_sgl_pipe[0:0]
- attribute \src "libresoc.v:18592.3-18610.6"
+ attribute \src "libresoc.v:18783.3-18801.6"
wire $1\dec31_dec_sub0_sgn[0:0]
- attribute \src "libresoc.v:18516.3-18534.6"
+ attribute \src "libresoc.v:18707.3-18725.6"
wire $1\dec31_dec_sub0_sgn_ext[0:0]
- attribute \src "libresoc.v:18364.3-18382.6"
+ attribute \src "libresoc.v:18555.3-18573.6"
wire width 2 $1\dec31_dec_sub0_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub0_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub0_upd
- attribute \src "libresoc.v:18069.7-18069.15"
+ attribute \src "libresoc.v:18260.7-18260.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:18069.7-18069.20"
- process $proc$libresoc.v:18069$391
+ attribute \src "libresoc.v:18260.7-18260.20"
+ process $proc$libresoc.v:18260$431
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:18326.3-18344.6"
- process $proc$libresoc.v:18326$367
+ attribute \src "libresoc.v:18517.3-18535.6"
+ process $proc$libresoc.v:18517$407
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0]
- attribute \src "libresoc.v:18327.5-18327.29"
+ attribute \src "libresoc.v:18518.5-18518.29"
switch \initial
- attribute \src "libresoc.v:18327.9-18327.17"
+ attribute \src "libresoc.v:18518.9-18518.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0]
end
- attribute \src "libresoc.v:18345.3-18363.6"
- process $proc$libresoc.v:18345$368
+ attribute \src "libresoc.v:18536.3-18554.6"
+ process $proc$libresoc.v:18536$408
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0]
- attribute \src "libresoc.v:18346.5-18346.29"
+ attribute \src "libresoc.v:18537.5-18537.29"
switch \initial
- attribute \src "libresoc.v:18346.9-18346.17"
+ attribute \src "libresoc.v:18537.9-18537.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0]
end
- attribute \src "libresoc.v:18364.3-18382.6"
- process $proc$libresoc.v:18364$369
+ attribute \src "libresoc.v:18555.3-18573.6"
+ process $proc$libresoc.v:18555$409
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0]
- attribute \src "libresoc.v:18365.5-18365.29"
+ attribute \src "libresoc.v:18556.5-18556.29"
switch \initial
- attribute \src "libresoc.v:18365.9-18365.17"
+ attribute \src "libresoc.v:18556.9-18556.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0]
end
- attribute \src "libresoc.v:18383.3-18401.6"
- process $proc$libresoc.v:18383$370
+ attribute \src "libresoc.v:18574.3-18592.6"
+ process $proc$libresoc.v:18574$410
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0]
- attribute \src "libresoc.v:18384.5-18384.29"
+ attribute \src "libresoc.v:18575.5-18575.29"
switch \initial
- attribute \src "libresoc.v:18384.9-18384.17"
+ attribute \src "libresoc.v:18575.9-18575.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0]
end
- attribute \src "libresoc.v:18402.3-18420.6"
- process $proc$libresoc.v:18402$371
+ attribute \src "libresoc.v:18593.3-18611.6"
+ process $proc$libresoc.v:18593$411
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0]
- attribute \src "libresoc.v:18403.5-18403.29"
+ attribute \src "libresoc.v:18594.5-18594.29"
switch \initial
- attribute \src "libresoc.v:18403.9-18403.17"
+ attribute \src "libresoc.v:18594.9-18594.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0]
end
- attribute \src "libresoc.v:18421.3-18439.6"
- process $proc$libresoc.v:18421$372
+ attribute \src "libresoc.v:18612.3-18630.6"
+ process $proc$libresoc.v:18612$412
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0]
- attribute \src "libresoc.v:18422.5-18422.29"
+ attribute \src "libresoc.v:18613.5-18613.29"
switch \initial
- attribute \src "libresoc.v:18422.9-18422.17"
+ attribute \src "libresoc.v:18613.9-18613.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0]
end
- attribute \src "libresoc.v:18440.3-18458.6"
- process $proc$libresoc.v:18440$373
+ attribute \src "libresoc.v:18631.3-18649.6"
+ process $proc$libresoc.v:18631$413
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0]
- attribute \src "libresoc.v:18441.5-18441.29"
+ attribute \src "libresoc.v:18632.5-18632.29"
switch \initial
- attribute \src "libresoc.v:18441.9-18441.17"
+ attribute \src "libresoc.v:18632.9-18632.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0]
end
- attribute \src "libresoc.v:18459.3-18477.6"
- process $proc$libresoc.v:18459$374
+ attribute \src "libresoc.v:18650.3-18668.6"
+ process $proc$libresoc.v:18650$414
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0]
- attribute \src "libresoc.v:18460.5-18460.29"
+ attribute \src "libresoc.v:18651.5-18651.29"
switch \initial
- attribute \src "libresoc.v:18460.9-18460.17"
+ attribute \src "libresoc.v:18651.9-18651.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0]
end
- attribute \src "libresoc.v:18478.3-18496.6"
- process $proc$libresoc.v:18478$375
+ attribute \src "libresoc.v:18669.3-18687.6"
+ process $proc$libresoc.v:18669$415
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0]
- attribute \src "libresoc.v:18479.5-18479.29"
+ attribute \src "libresoc.v:18670.5-18670.29"
switch \initial
- attribute \src "libresoc.v:18479.9-18479.17"
+ attribute \src "libresoc.v:18670.9-18670.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0]
end
- attribute \src "libresoc.v:18497.3-18515.6"
- process $proc$libresoc.v:18497$376
+ attribute \src "libresoc.v:18688.3-18706.6"
+ process $proc$libresoc.v:18688$416
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0]
- attribute \src "libresoc.v:18498.5-18498.29"
+ attribute \src "libresoc.v:18689.5-18689.29"
switch \initial
- attribute \src "libresoc.v:18498.9-18498.17"
+ attribute \src "libresoc.v:18689.9-18689.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0]
end
- attribute \src "libresoc.v:18516.3-18534.6"
- process $proc$libresoc.v:18516$377
+ attribute \src "libresoc.v:18707.3-18725.6"
+ process $proc$libresoc.v:18707$417
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0]
- attribute \src "libresoc.v:18517.5-18517.29"
+ attribute \src "libresoc.v:18708.5-18708.29"
switch \initial
- attribute \src "libresoc.v:18517.9-18517.17"
+ attribute \src "libresoc.v:18708.9-18708.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0]
end
- attribute \src "libresoc.v:18535.3-18553.6"
- process $proc$libresoc.v:18535$378
+ attribute \src "libresoc.v:18726.3-18744.6"
+ process $proc$libresoc.v:18726$418
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0]
- attribute \src "libresoc.v:18536.5-18536.29"
+ attribute \src "libresoc.v:18727.5-18727.29"
switch \initial
- attribute \src "libresoc.v:18536.9-18536.17"
+ attribute \src "libresoc.v:18727.9-18727.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0]
end
- attribute \src "libresoc.v:18554.3-18572.6"
- process $proc$libresoc.v:18554$379
+ attribute \src "libresoc.v:18745.3-18763.6"
+ process $proc$libresoc.v:18745$419
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0]
- attribute \src "libresoc.v:18555.5-18555.29"
+ attribute \src "libresoc.v:18746.5-18746.29"
switch \initial
- attribute \src "libresoc.v:18555.9-18555.17"
+ attribute \src "libresoc.v:18746.9-18746.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0]
end
- attribute \src "libresoc.v:18573.3-18591.6"
- process $proc$libresoc.v:18573$380
+ attribute \src "libresoc.v:18764.3-18782.6"
+ process $proc$libresoc.v:18764$420
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0]
- attribute \src "libresoc.v:18574.5-18574.29"
+ attribute \src "libresoc.v:18765.5-18765.29"
switch \initial
- attribute \src "libresoc.v:18574.9-18574.17"
+ attribute \src "libresoc.v:18765.9-18765.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0]
end
- attribute \src "libresoc.v:18592.3-18610.6"
- process $proc$libresoc.v:18592$381
+ attribute \src "libresoc.v:18783.3-18801.6"
+ process $proc$libresoc.v:18783$421
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0]
- attribute \src "libresoc.v:18593.5-18593.29"
+ attribute \src "libresoc.v:18784.5-18784.29"
switch \initial
- attribute \src "libresoc.v:18593.9-18593.17"
+ attribute \src "libresoc.v:18784.9-18784.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0]
end
- attribute \src "libresoc.v:18611.3-18629.6"
- process $proc$libresoc.v:18611$382
+ attribute \src "libresoc.v:18802.3-18820.6"
+ process $proc$libresoc.v:18802$422
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0]
- attribute \src "libresoc.v:18612.5-18612.29"
+ attribute \src "libresoc.v:18803.5-18803.29"
switch \initial
- attribute \src "libresoc.v:18612.9-18612.17"
+ attribute \src "libresoc.v:18803.9-18803.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0]
end
- attribute \src "libresoc.v:18630.3-18648.6"
- process $proc$libresoc.v:18630$383
+ attribute \src "libresoc.v:18821.3-18839.6"
+ process $proc$libresoc.v:18821$423
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0]
- attribute \src "libresoc.v:18631.5-18631.29"
+ attribute \src "libresoc.v:18822.5-18822.29"
switch \initial
- attribute \src "libresoc.v:18631.9-18631.17"
+ attribute \src "libresoc.v:18822.9-18822.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:18649.3-18667.6"
- process $proc$libresoc.v:18649$384
+ attribute \src "libresoc.v:18840.3-18858.6"
+ process $proc$libresoc.v:18840$424
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0]
- attribute \src "libresoc.v:18650.5-18650.29"
+ attribute \src "libresoc.v:18841.5-18841.29"
switch \initial
- attribute \src "libresoc.v:18650.9-18650.17"
+ attribute \src "libresoc.v:18841.9-18841.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0]
end
- attribute \src "libresoc.v:18668.3-18686.6"
- process $proc$libresoc.v:18668$385
+ attribute \src "libresoc.v:18859.3-18877.6"
+ process $proc$libresoc.v:18859$425
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0]
- attribute \src "libresoc.v:18669.5-18669.29"
+ attribute \src "libresoc.v:18860.5-18860.29"
switch \initial
- attribute \src "libresoc.v:18669.9-18669.17"
+ attribute \src "libresoc.v:18860.9-18860.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0]
end
- attribute \src "libresoc.v:18687.3-18705.6"
- process $proc$libresoc.v:18687$386
+ attribute \src "libresoc.v:18878.3-18896.6"
+ process $proc$libresoc.v:18878$426
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0]
- attribute \src "libresoc.v:18688.5-18688.29"
+ attribute \src "libresoc.v:18879.5-18879.29"
switch \initial
- attribute \src "libresoc.v:18688.9-18688.17"
+ attribute \src "libresoc.v:18879.9-18879.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0]
end
- attribute \src "libresoc.v:18706.3-18724.6"
- process $proc$libresoc.v:18706$387
+ attribute \src "libresoc.v:18897.3-18915.6"
+ process $proc$libresoc.v:18897$427
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0]
- attribute \src "libresoc.v:18707.5-18707.29"
+ attribute \src "libresoc.v:18898.5-18898.29"
switch \initial
- attribute \src "libresoc.v:18707.9-18707.17"
+ attribute \src "libresoc.v:18898.9-18898.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0]
end
- attribute \src "libresoc.v:18725.3-18743.6"
- process $proc$libresoc.v:18725$388
+ attribute \src "libresoc.v:18916.3-18934.6"
+ process $proc$libresoc.v:18916$428
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0]
- attribute \src "libresoc.v:18726.5-18726.29"
+ attribute \src "libresoc.v:18917.5-18917.29"
switch \initial
- attribute \src "libresoc.v:18726.9-18726.17"
+ attribute \src "libresoc.v:18917.9-18917.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0]
end
- attribute \src "libresoc.v:18744.3-18762.6"
- process $proc$libresoc.v:18744$389
+ attribute \src "libresoc.v:18935.3-18953.6"
+ process $proc$libresoc.v:18935$429
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0]
- attribute \src "libresoc.v:18745.5-18745.29"
+ attribute \src "libresoc.v:18936.5-18936.29"
switch \initial
- attribute \src "libresoc.v:18745.9-18745.17"
+ attribute \src "libresoc.v:18936.9-18936.17"
case 1'1
case
end
sync always
update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0]
end
- attribute \src "libresoc.v:18763.3-18781.6"
- process $proc$libresoc.v:18763$390
+ attribute \src "libresoc.v:18954.3-18972.6"
+ process $proc$libresoc.v:18954$430
assign { } { }
assign { } { }
assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0]
- attribute \src "libresoc.v:18764.5-18764.29"
+ attribute \src "libresoc.v:18955.5-18955.29"
switch \initial
- attribute \src "libresoc.v:18764.9-18764.17"
+ attribute \src "libresoc.v:18955.9-18955.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:18787.1-19934.10"
+attribute \src "libresoc.v:18978.1-20125.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub10"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10"
attribute \generator "nMigen"
module \dec31_dec_sub10
- attribute \src "libresoc.v:19230.3-19266.6"
+ attribute \src "libresoc.v:19421.3-19457.6"
wire width 8 $0\dec31_dec_sub10_asmcode[7:0]
- attribute \src "libresoc.v:19378.3-19414.6"
+ attribute \src "libresoc.v:19569.3-19605.6"
wire $0\dec31_dec_sub10_br[0:0]
- attribute \src "libresoc.v:19859.3-19895.6"
+ attribute \src "libresoc.v:20050.3-20086.6"
wire width 3 $0\dec31_dec_sub10_cr_in[2:0]
- attribute \src "libresoc.v:19896.3-19932.6"
+ attribute \src "libresoc.v:20087.3-20123.6"
wire width 3 $0\dec31_dec_sub10_cr_out[2:0]
- attribute \src "libresoc.v:19193.3-19229.6"
+ attribute \src "libresoc.v:19384.3-19420.6"
wire width 2 $0\dec31_dec_sub10_cry_in[1:0]
- attribute \src "libresoc.v:19341.3-19377.6"
+ attribute \src "libresoc.v:19532.3-19568.6"
wire $0\dec31_dec_sub10_cry_out[0:0]
- attribute \src "libresoc.v:19674.3-19710.6"
+ attribute \src "libresoc.v:19865.3-19901.6"
wire width 5 $0\dec31_dec_sub10_form[4:0]
- attribute \src "libresoc.v:19045.3-19081.6"
+ attribute \src "libresoc.v:19236.3-19272.6"
wire width 12 $0\dec31_dec_sub10_function_unit[11:0]
- attribute \src "libresoc.v:19711.3-19747.6"
+ attribute \src "libresoc.v:19902.3-19938.6"
wire width 3 $0\dec31_dec_sub10_in1_sel[2:0]
- attribute \src "libresoc.v:19748.3-19784.6"
+ attribute \src "libresoc.v:19939.3-19975.6"
wire width 4 $0\dec31_dec_sub10_in2_sel[3:0]
- attribute \src "libresoc.v:19785.3-19821.6"
+ attribute \src "libresoc.v:19976.3-20012.6"
wire width 2 $0\dec31_dec_sub10_in3_sel[1:0]
- attribute \src "libresoc.v:19452.3-19488.6"
+ attribute \src "libresoc.v:19643.3-19679.6"
wire width 7 $0\dec31_dec_sub10_internal_op[6:0]
- attribute \src "libresoc.v:19267.3-19303.6"
+ attribute \src "libresoc.v:19458.3-19494.6"
wire $0\dec31_dec_sub10_inv_a[0:0]
- attribute \src "libresoc.v:19304.3-19340.6"
+ attribute \src "libresoc.v:19495.3-19531.6"
wire $0\dec31_dec_sub10_inv_out[0:0]
- attribute \src "libresoc.v:19526.3-19562.6"
+ attribute \src "libresoc.v:19717.3-19753.6"
wire $0\dec31_dec_sub10_is_32b[0:0]
- attribute \src "libresoc.v:19082.3-19118.6"
+ attribute \src "libresoc.v:19273.3-19309.6"
wire width 4 $0\dec31_dec_sub10_ldst_len[3:0]
- attribute \src "libresoc.v:19600.3-19636.6"
+ attribute \src "libresoc.v:19791.3-19827.6"
wire $0\dec31_dec_sub10_lk[0:0]
- attribute \src "libresoc.v:19822.3-19858.6"
+ attribute \src "libresoc.v:20013.3-20049.6"
wire width 2 $0\dec31_dec_sub10_out_sel[1:0]
- attribute \src "libresoc.v:19156.3-19192.6"
+ attribute \src "libresoc.v:19347.3-19383.6"
wire width 2 $0\dec31_dec_sub10_rc_sel[1:0]
- attribute \src "libresoc.v:19489.3-19525.6"
+ attribute \src "libresoc.v:19680.3-19716.6"
wire $0\dec31_dec_sub10_rsrv[0:0]
- attribute \src "libresoc.v:19637.3-19673.6"
+ attribute \src "libresoc.v:19828.3-19864.6"
wire $0\dec31_dec_sub10_sgl_pipe[0:0]
- attribute \src "libresoc.v:19563.3-19599.6"
+ attribute \src "libresoc.v:19754.3-19790.6"
wire $0\dec31_dec_sub10_sgn[0:0]
- attribute \src "libresoc.v:19415.3-19451.6"
+ attribute \src "libresoc.v:19606.3-19642.6"
wire $0\dec31_dec_sub10_sgn_ext[0:0]
- attribute \src "libresoc.v:19119.3-19155.6"
+ attribute \src "libresoc.v:19310.3-19346.6"
wire width 2 $0\dec31_dec_sub10_upd[1:0]
- attribute \src "libresoc.v:18788.7-18788.20"
+ attribute \src "libresoc.v:18979.7-18979.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:19230.3-19266.6"
+ attribute \src "libresoc.v:19421.3-19457.6"
wire width 8 $1\dec31_dec_sub10_asmcode[7:0]
- attribute \src "libresoc.v:19378.3-19414.6"
+ attribute \src "libresoc.v:19569.3-19605.6"
wire $1\dec31_dec_sub10_br[0:0]
- attribute \src "libresoc.v:19859.3-19895.6"
+ attribute \src "libresoc.v:20050.3-20086.6"
wire width 3 $1\dec31_dec_sub10_cr_in[2:0]
- attribute \src "libresoc.v:19896.3-19932.6"
+ attribute \src "libresoc.v:20087.3-20123.6"
wire width 3 $1\dec31_dec_sub10_cr_out[2:0]
- attribute \src "libresoc.v:19193.3-19229.6"
+ attribute \src "libresoc.v:19384.3-19420.6"
wire width 2 $1\dec31_dec_sub10_cry_in[1:0]
- attribute \src "libresoc.v:19341.3-19377.6"
+ attribute \src "libresoc.v:19532.3-19568.6"
wire $1\dec31_dec_sub10_cry_out[0:0]
- attribute \src "libresoc.v:19674.3-19710.6"
+ attribute \src "libresoc.v:19865.3-19901.6"
wire width 5 $1\dec31_dec_sub10_form[4:0]
- attribute \src "libresoc.v:19045.3-19081.6"
+ attribute \src "libresoc.v:19236.3-19272.6"
wire width 12 $1\dec31_dec_sub10_function_unit[11:0]
- attribute \src "libresoc.v:19711.3-19747.6"
+ attribute \src "libresoc.v:19902.3-19938.6"
wire width 3 $1\dec31_dec_sub10_in1_sel[2:0]
- attribute \src "libresoc.v:19748.3-19784.6"
+ attribute \src "libresoc.v:19939.3-19975.6"
wire width 4 $1\dec31_dec_sub10_in2_sel[3:0]
- attribute \src "libresoc.v:19785.3-19821.6"
+ attribute \src "libresoc.v:19976.3-20012.6"
wire width 2 $1\dec31_dec_sub10_in3_sel[1:0]
- attribute \src "libresoc.v:19452.3-19488.6"
+ attribute \src "libresoc.v:19643.3-19679.6"
wire width 7 $1\dec31_dec_sub10_internal_op[6:0]
- attribute \src "libresoc.v:19267.3-19303.6"
+ attribute \src "libresoc.v:19458.3-19494.6"
wire $1\dec31_dec_sub10_inv_a[0:0]
- attribute \src "libresoc.v:19304.3-19340.6"
+ attribute \src "libresoc.v:19495.3-19531.6"
wire $1\dec31_dec_sub10_inv_out[0:0]
- attribute \src "libresoc.v:19526.3-19562.6"
+ attribute \src "libresoc.v:19717.3-19753.6"
wire $1\dec31_dec_sub10_is_32b[0:0]
- attribute \src "libresoc.v:19082.3-19118.6"
+ attribute \src "libresoc.v:19273.3-19309.6"
wire width 4 $1\dec31_dec_sub10_ldst_len[3:0]
- attribute \src "libresoc.v:19600.3-19636.6"
+ attribute \src "libresoc.v:19791.3-19827.6"
wire $1\dec31_dec_sub10_lk[0:0]
- attribute \src "libresoc.v:19822.3-19858.6"
+ attribute \src "libresoc.v:20013.3-20049.6"
wire width 2 $1\dec31_dec_sub10_out_sel[1:0]
- attribute \src "libresoc.v:19156.3-19192.6"
+ attribute \src "libresoc.v:19347.3-19383.6"
wire width 2 $1\dec31_dec_sub10_rc_sel[1:0]
- attribute \src "libresoc.v:19489.3-19525.6"
+ attribute \src "libresoc.v:19680.3-19716.6"
wire $1\dec31_dec_sub10_rsrv[0:0]
- attribute \src "libresoc.v:19637.3-19673.6"
+ attribute \src "libresoc.v:19828.3-19864.6"
wire $1\dec31_dec_sub10_sgl_pipe[0:0]
- attribute \src "libresoc.v:19563.3-19599.6"
+ attribute \src "libresoc.v:19754.3-19790.6"
wire $1\dec31_dec_sub10_sgn[0:0]
- attribute \src "libresoc.v:19415.3-19451.6"
+ attribute \src "libresoc.v:19606.3-19642.6"
wire $1\dec31_dec_sub10_sgn_ext[0:0]
- attribute \src "libresoc.v:19119.3-19155.6"
+ attribute \src "libresoc.v:19310.3-19346.6"
wire width 2 $1\dec31_dec_sub10_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub10_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub10_upd
- attribute \src "libresoc.v:18788.7-18788.15"
+ attribute \src "libresoc.v:18979.7-18979.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:18788.7-18788.20"
- process $proc$libresoc.v:18788$416
+ attribute \src "libresoc.v:18979.7-18979.20"
+ process $proc$libresoc.v:18979$456
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:19045.3-19081.6"
- process $proc$libresoc.v:19045$392
+ attribute \src "libresoc.v:19236.3-19272.6"
+ process $proc$libresoc.v:19236$432
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0]
- attribute \src "libresoc.v:19046.5-19046.29"
+ attribute \src "libresoc.v:19237.5-19237.29"
switch \initial
- attribute \src "libresoc.v:19046.9-19046.17"
+ attribute \src "libresoc.v:19237.9-19237.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0]
end
- attribute \src "libresoc.v:19082.3-19118.6"
- process $proc$libresoc.v:19082$393
+ attribute \src "libresoc.v:19273.3-19309.6"
+ process $proc$libresoc.v:19273$433
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0]
- attribute \src "libresoc.v:19083.5-19083.29"
+ attribute \src "libresoc.v:19274.5-19274.29"
switch \initial
- attribute \src "libresoc.v:19083.9-19083.17"
+ attribute \src "libresoc.v:19274.9-19274.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0]
end
- attribute \src "libresoc.v:19119.3-19155.6"
- process $proc$libresoc.v:19119$394
+ attribute \src "libresoc.v:19310.3-19346.6"
+ process $proc$libresoc.v:19310$434
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0]
- attribute \src "libresoc.v:19120.5-19120.29"
+ attribute \src "libresoc.v:19311.5-19311.29"
switch \initial
- attribute \src "libresoc.v:19120.9-19120.17"
+ attribute \src "libresoc.v:19311.9-19311.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0]
end
- attribute \src "libresoc.v:19156.3-19192.6"
- process $proc$libresoc.v:19156$395
+ attribute \src "libresoc.v:19347.3-19383.6"
+ process $proc$libresoc.v:19347$435
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0]
- attribute \src "libresoc.v:19157.5-19157.29"
+ attribute \src "libresoc.v:19348.5-19348.29"
switch \initial
- attribute \src "libresoc.v:19157.9-19157.17"
+ attribute \src "libresoc.v:19348.9-19348.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0]
end
- attribute \src "libresoc.v:19193.3-19229.6"
- process $proc$libresoc.v:19193$396
+ attribute \src "libresoc.v:19384.3-19420.6"
+ process $proc$libresoc.v:19384$436
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0]
- attribute \src "libresoc.v:19194.5-19194.29"
+ attribute \src "libresoc.v:19385.5-19385.29"
switch \initial
- attribute \src "libresoc.v:19194.9-19194.17"
+ attribute \src "libresoc.v:19385.9-19385.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0]
end
- attribute \src "libresoc.v:19230.3-19266.6"
- process $proc$libresoc.v:19230$397
+ attribute \src "libresoc.v:19421.3-19457.6"
+ process $proc$libresoc.v:19421$437
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0]
- attribute \src "libresoc.v:19231.5-19231.29"
+ attribute \src "libresoc.v:19422.5-19422.29"
switch \initial
- attribute \src "libresoc.v:19231.9-19231.17"
+ attribute \src "libresoc.v:19422.9-19422.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0]
end
- attribute \src "libresoc.v:19267.3-19303.6"
- process $proc$libresoc.v:19267$398
+ attribute \src "libresoc.v:19458.3-19494.6"
+ process $proc$libresoc.v:19458$438
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0]
- attribute \src "libresoc.v:19268.5-19268.29"
+ attribute \src "libresoc.v:19459.5-19459.29"
switch \initial
- attribute \src "libresoc.v:19268.9-19268.17"
+ attribute \src "libresoc.v:19459.9-19459.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0]
end
- attribute \src "libresoc.v:19304.3-19340.6"
- process $proc$libresoc.v:19304$399
+ attribute \src "libresoc.v:19495.3-19531.6"
+ process $proc$libresoc.v:19495$439
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0]
- attribute \src "libresoc.v:19305.5-19305.29"
+ attribute \src "libresoc.v:19496.5-19496.29"
switch \initial
- attribute \src "libresoc.v:19305.9-19305.17"
+ attribute \src "libresoc.v:19496.9-19496.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0]
end
- attribute \src "libresoc.v:19341.3-19377.6"
- process $proc$libresoc.v:19341$400
+ attribute \src "libresoc.v:19532.3-19568.6"
+ process $proc$libresoc.v:19532$440
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0]
- attribute \src "libresoc.v:19342.5-19342.29"
+ attribute \src "libresoc.v:19533.5-19533.29"
switch \initial
- attribute \src "libresoc.v:19342.9-19342.17"
+ attribute \src "libresoc.v:19533.9-19533.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0]
end
- attribute \src "libresoc.v:19378.3-19414.6"
- process $proc$libresoc.v:19378$401
+ attribute \src "libresoc.v:19569.3-19605.6"
+ process $proc$libresoc.v:19569$441
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0]
- attribute \src "libresoc.v:19379.5-19379.29"
+ attribute \src "libresoc.v:19570.5-19570.29"
switch \initial
- attribute \src "libresoc.v:19379.9-19379.17"
+ attribute \src "libresoc.v:19570.9-19570.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0]
end
- attribute \src "libresoc.v:19415.3-19451.6"
- process $proc$libresoc.v:19415$402
+ attribute \src "libresoc.v:19606.3-19642.6"
+ process $proc$libresoc.v:19606$442
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0]
- attribute \src "libresoc.v:19416.5-19416.29"
+ attribute \src "libresoc.v:19607.5-19607.29"
switch \initial
- attribute \src "libresoc.v:19416.9-19416.17"
+ attribute \src "libresoc.v:19607.9-19607.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0]
end
- attribute \src "libresoc.v:19452.3-19488.6"
- process $proc$libresoc.v:19452$403
+ attribute \src "libresoc.v:19643.3-19679.6"
+ process $proc$libresoc.v:19643$443
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0]
- attribute \src "libresoc.v:19453.5-19453.29"
+ attribute \src "libresoc.v:19644.5-19644.29"
switch \initial
- attribute \src "libresoc.v:19453.9-19453.17"
+ attribute \src "libresoc.v:19644.9-19644.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0]
end
- attribute \src "libresoc.v:19489.3-19525.6"
- process $proc$libresoc.v:19489$404
+ attribute \src "libresoc.v:19680.3-19716.6"
+ process $proc$libresoc.v:19680$444
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0]
- attribute \src "libresoc.v:19490.5-19490.29"
+ attribute \src "libresoc.v:19681.5-19681.29"
switch \initial
- attribute \src "libresoc.v:19490.9-19490.17"
+ attribute \src "libresoc.v:19681.9-19681.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0]
end
- attribute \src "libresoc.v:19526.3-19562.6"
- process $proc$libresoc.v:19526$405
+ attribute \src "libresoc.v:19717.3-19753.6"
+ process $proc$libresoc.v:19717$445
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0]
- attribute \src "libresoc.v:19527.5-19527.29"
+ attribute \src "libresoc.v:19718.5-19718.29"
switch \initial
- attribute \src "libresoc.v:19527.9-19527.17"
+ attribute \src "libresoc.v:19718.9-19718.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0]
end
- attribute \src "libresoc.v:19563.3-19599.6"
- process $proc$libresoc.v:19563$406
+ attribute \src "libresoc.v:19754.3-19790.6"
+ process $proc$libresoc.v:19754$446
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0]
- attribute \src "libresoc.v:19564.5-19564.29"
+ attribute \src "libresoc.v:19755.5-19755.29"
switch \initial
- attribute \src "libresoc.v:19564.9-19564.17"
+ attribute \src "libresoc.v:19755.9-19755.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0]
end
- attribute \src "libresoc.v:19600.3-19636.6"
- process $proc$libresoc.v:19600$407
+ attribute \src "libresoc.v:19791.3-19827.6"
+ process $proc$libresoc.v:19791$447
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0]
- attribute \src "libresoc.v:19601.5-19601.29"
+ attribute \src "libresoc.v:19792.5-19792.29"
switch \initial
- attribute \src "libresoc.v:19601.9-19601.17"
+ attribute \src "libresoc.v:19792.9-19792.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0]
end
- attribute \src "libresoc.v:19637.3-19673.6"
- process $proc$libresoc.v:19637$408
+ attribute \src "libresoc.v:19828.3-19864.6"
+ process $proc$libresoc.v:19828$448
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0]
- attribute \src "libresoc.v:19638.5-19638.29"
+ attribute \src "libresoc.v:19829.5-19829.29"
switch \initial
- attribute \src "libresoc.v:19638.9-19638.17"
+ attribute \src "libresoc.v:19829.9-19829.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:19674.3-19710.6"
- process $proc$libresoc.v:19674$409
+ attribute \src "libresoc.v:19865.3-19901.6"
+ process $proc$libresoc.v:19865$449
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0]
- attribute \src "libresoc.v:19675.5-19675.29"
+ attribute \src "libresoc.v:19866.5-19866.29"
switch \initial
- attribute \src "libresoc.v:19675.9-19675.17"
+ attribute \src "libresoc.v:19866.9-19866.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0]
end
- attribute \src "libresoc.v:19711.3-19747.6"
- process $proc$libresoc.v:19711$410
+ attribute \src "libresoc.v:19902.3-19938.6"
+ process $proc$libresoc.v:19902$450
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0]
- attribute \src "libresoc.v:19712.5-19712.29"
+ attribute \src "libresoc.v:19903.5-19903.29"
switch \initial
- attribute \src "libresoc.v:19712.9-19712.17"
+ attribute \src "libresoc.v:19903.9-19903.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0]
end
- attribute \src "libresoc.v:19748.3-19784.6"
- process $proc$libresoc.v:19748$411
+ attribute \src "libresoc.v:19939.3-19975.6"
+ process $proc$libresoc.v:19939$451
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0]
- attribute \src "libresoc.v:19749.5-19749.29"
+ attribute \src "libresoc.v:19940.5-19940.29"
switch \initial
- attribute \src "libresoc.v:19749.9-19749.17"
+ attribute \src "libresoc.v:19940.9-19940.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0]
end
- attribute \src "libresoc.v:19785.3-19821.6"
- process $proc$libresoc.v:19785$412
+ attribute \src "libresoc.v:19976.3-20012.6"
+ process $proc$libresoc.v:19976$452
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0]
- attribute \src "libresoc.v:19786.5-19786.29"
+ attribute \src "libresoc.v:19977.5-19977.29"
switch \initial
- attribute \src "libresoc.v:19786.9-19786.17"
+ attribute \src "libresoc.v:19977.9-19977.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0]
end
- attribute \src "libresoc.v:19822.3-19858.6"
- process $proc$libresoc.v:19822$413
+ attribute \src "libresoc.v:20013.3-20049.6"
+ process $proc$libresoc.v:20013$453
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0]
- attribute \src "libresoc.v:19823.5-19823.29"
+ attribute \src "libresoc.v:20014.5-20014.29"
switch \initial
- attribute \src "libresoc.v:19823.9-19823.17"
+ attribute \src "libresoc.v:20014.9-20014.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0]
end
- attribute \src "libresoc.v:19859.3-19895.6"
- process $proc$libresoc.v:19859$414
+ attribute \src "libresoc.v:20050.3-20086.6"
+ process $proc$libresoc.v:20050$454
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0]
- attribute \src "libresoc.v:19860.5-19860.29"
+ attribute \src "libresoc.v:20051.5-20051.29"
switch \initial
- attribute \src "libresoc.v:19860.9-19860.17"
+ attribute \src "libresoc.v:20051.9-20051.17"
case 1'1
case
end
sync always
update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0]
end
- attribute \src "libresoc.v:19896.3-19932.6"
- process $proc$libresoc.v:19896$415
+ attribute \src "libresoc.v:20087.3-20123.6"
+ process $proc$libresoc.v:20087$455
assign { } { }
assign { } { }
assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0]
- attribute \src "libresoc.v:19897.5-19897.29"
+ attribute \src "libresoc.v:20088.5-20088.29"
switch \initial
- attribute \src "libresoc.v:19897.9-19897.17"
+ attribute \src "libresoc.v:20088.9-20088.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:19938.1-21517.10"
+attribute \src "libresoc.v:20129.1-21708.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub11"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11"
attribute \generator "nMigen"
module \dec31_dec_sub11
- attribute \src "libresoc.v:20471.3-20525.6"
+ attribute \src "libresoc.v:20662.3-20716.6"
wire width 8 $0\dec31_dec_sub11_asmcode[7:0]
- attribute \src "libresoc.v:20691.3-20745.6"
+ attribute \src "libresoc.v:20882.3-20936.6"
wire $0\dec31_dec_sub11_br[0:0]
- attribute \src "libresoc.v:21406.3-21460.6"
+ attribute \src "libresoc.v:21597.3-21651.6"
wire width 3 $0\dec31_dec_sub11_cr_in[2:0]
- attribute \src "libresoc.v:21461.3-21515.6"
+ attribute \src "libresoc.v:21652.3-21706.6"
wire width 3 $0\dec31_dec_sub11_cr_out[2:0]
- attribute \src "libresoc.v:20416.3-20470.6"
+ attribute \src "libresoc.v:20607.3-20661.6"
wire width 2 $0\dec31_dec_sub11_cry_in[1:0]
- attribute \src "libresoc.v:20636.3-20690.6"
+ attribute \src "libresoc.v:20827.3-20881.6"
wire $0\dec31_dec_sub11_cry_out[0:0]
- attribute \src "libresoc.v:21131.3-21185.6"
+ attribute \src "libresoc.v:21322.3-21376.6"
wire width 5 $0\dec31_dec_sub11_form[4:0]
- attribute \src "libresoc.v:20196.3-20250.6"
+ attribute \src "libresoc.v:20387.3-20441.6"
wire width 12 $0\dec31_dec_sub11_function_unit[11:0]
- attribute \src "libresoc.v:21186.3-21240.6"
+ attribute \src "libresoc.v:21377.3-21431.6"
wire width 3 $0\dec31_dec_sub11_in1_sel[2:0]
- attribute \src "libresoc.v:21241.3-21295.6"
+ attribute \src "libresoc.v:21432.3-21486.6"
wire width 4 $0\dec31_dec_sub11_in2_sel[3:0]
- attribute \src "libresoc.v:21296.3-21350.6"
+ attribute \src "libresoc.v:21487.3-21541.6"
wire width 2 $0\dec31_dec_sub11_in3_sel[1:0]
- attribute \src "libresoc.v:20801.3-20855.6"
+ attribute \src "libresoc.v:20992.3-21046.6"
wire width 7 $0\dec31_dec_sub11_internal_op[6:0]
- attribute \src "libresoc.v:20526.3-20580.6"
+ attribute \src "libresoc.v:20717.3-20771.6"
wire $0\dec31_dec_sub11_inv_a[0:0]
- attribute \src "libresoc.v:20581.3-20635.6"
+ attribute \src "libresoc.v:20772.3-20826.6"
wire $0\dec31_dec_sub11_inv_out[0:0]
- attribute \src "libresoc.v:20911.3-20965.6"
+ attribute \src "libresoc.v:21102.3-21156.6"
wire $0\dec31_dec_sub11_is_32b[0:0]
- attribute \src "libresoc.v:20251.3-20305.6"
+ attribute \src "libresoc.v:20442.3-20496.6"
wire width 4 $0\dec31_dec_sub11_ldst_len[3:0]
- attribute \src "libresoc.v:21021.3-21075.6"
+ attribute \src "libresoc.v:21212.3-21266.6"
wire $0\dec31_dec_sub11_lk[0:0]
- attribute \src "libresoc.v:21351.3-21405.6"
+ attribute \src "libresoc.v:21542.3-21596.6"
wire width 2 $0\dec31_dec_sub11_out_sel[1:0]
- attribute \src "libresoc.v:20361.3-20415.6"
+ attribute \src "libresoc.v:20552.3-20606.6"
wire width 2 $0\dec31_dec_sub11_rc_sel[1:0]
- attribute \src "libresoc.v:20856.3-20910.6"
+ attribute \src "libresoc.v:21047.3-21101.6"
wire $0\dec31_dec_sub11_rsrv[0:0]
- attribute \src "libresoc.v:21076.3-21130.6"
+ attribute \src "libresoc.v:21267.3-21321.6"
wire $0\dec31_dec_sub11_sgl_pipe[0:0]
- attribute \src "libresoc.v:20966.3-21020.6"
+ attribute \src "libresoc.v:21157.3-21211.6"
wire $0\dec31_dec_sub11_sgn[0:0]
- attribute \src "libresoc.v:20746.3-20800.6"
+ attribute \src "libresoc.v:20937.3-20991.6"
wire $0\dec31_dec_sub11_sgn_ext[0:0]
- attribute \src "libresoc.v:20306.3-20360.6"
+ attribute \src "libresoc.v:20497.3-20551.6"
wire width 2 $0\dec31_dec_sub11_upd[1:0]
- attribute \src "libresoc.v:19939.7-19939.20"
+ attribute \src "libresoc.v:20130.7-20130.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:20471.3-20525.6"
+ attribute \src "libresoc.v:20662.3-20716.6"
wire width 8 $1\dec31_dec_sub11_asmcode[7:0]
- attribute \src "libresoc.v:20691.3-20745.6"
+ attribute \src "libresoc.v:20882.3-20936.6"
wire $1\dec31_dec_sub11_br[0:0]
- attribute \src "libresoc.v:21406.3-21460.6"
+ attribute \src "libresoc.v:21597.3-21651.6"
wire width 3 $1\dec31_dec_sub11_cr_in[2:0]
- attribute \src "libresoc.v:21461.3-21515.6"
+ attribute \src "libresoc.v:21652.3-21706.6"
wire width 3 $1\dec31_dec_sub11_cr_out[2:0]
- attribute \src "libresoc.v:20416.3-20470.6"
+ attribute \src "libresoc.v:20607.3-20661.6"
wire width 2 $1\dec31_dec_sub11_cry_in[1:0]
- attribute \src "libresoc.v:20636.3-20690.6"
+ attribute \src "libresoc.v:20827.3-20881.6"
wire $1\dec31_dec_sub11_cry_out[0:0]
- attribute \src "libresoc.v:21131.3-21185.6"
+ attribute \src "libresoc.v:21322.3-21376.6"
wire width 5 $1\dec31_dec_sub11_form[4:0]
- attribute \src "libresoc.v:20196.3-20250.6"
+ attribute \src "libresoc.v:20387.3-20441.6"
wire width 12 $1\dec31_dec_sub11_function_unit[11:0]
- attribute \src "libresoc.v:21186.3-21240.6"
+ attribute \src "libresoc.v:21377.3-21431.6"
wire width 3 $1\dec31_dec_sub11_in1_sel[2:0]
- attribute \src "libresoc.v:21241.3-21295.6"
+ attribute \src "libresoc.v:21432.3-21486.6"
wire width 4 $1\dec31_dec_sub11_in2_sel[3:0]
- attribute \src "libresoc.v:21296.3-21350.6"
+ attribute \src "libresoc.v:21487.3-21541.6"
wire width 2 $1\dec31_dec_sub11_in3_sel[1:0]
- attribute \src "libresoc.v:20801.3-20855.6"
+ attribute \src "libresoc.v:20992.3-21046.6"
wire width 7 $1\dec31_dec_sub11_internal_op[6:0]
- attribute \src "libresoc.v:20526.3-20580.6"
+ attribute \src "libresoc.v:20717.3-20771.6"
wire $1\dec31_dec_sub11_inv_a[0:0]
- attribute \src "libresoc.v:20581.3-20635.6"
+ attribute \src "libresoc.v:20772.3-20826.6"
wire $1\dec31_dec_sub11_inv_out[0:0]
- attribute \src "libresoc.v:20911.3-20965.6"
+ attribute \src "libresoc.v:21102.3-21156.6"
wire $1\dec31_dec_sub11_is_32b[0:0]
- attribute \src "libresoc.v:20251.3-20305.6"
+ attribute \src "libresoc.v:20442.3-20496.6"
wire width 4 $1\dec31_dec_sub11_ldst_len[3:0]
- attribute \src "libresoc.v:21021.3-21075.6"
+ attribute \src "libresoc.v:21212.3-21266.6"
wire $1\dec31_dec_sub11_lk[0:0]
- attribute \src "libresoc.v:21351.3-21405.6"
+ attribute \src "libresoc.v:21542.3-21596.6"
wire width 2 $1\dec31_dec_sub11_out_sel[1:0]
- attribute \src "libresoc.v:20361.3-20415.6"
+ attribute \src "libresoc.v:20552.3-20606.6"
wire width 2 $1\dec31_dec_sub11_rc_sel[1:0]
- attribute \src "libresoc.v:20856.3-20910.6"
+ attribute \src "libresoc.v:21047.3-21101.6"
wire $1\dec31_dec_sub11_rsrv[0:0]
- attribute \src "libresoc.v:21076.3-21130.6"
+ attribute \src "libresoc.v:21267.3-21321.6"
wire $1\dec31_dec_sub11_sgl_pipe[0:0]
- attribute \src "libresoc.v:20966.3-21020.6"
+ attribute \src "libresoc.v:21157.3-21211.6"
wire $1\dec31_dec_sub11_sgn[0:0]
- attribute \src "libresoc.v:20746.3-20800.6"
+ attribute \src "libresoc.v:20937.3-20991.6"
wire $1\dec31_dec_sub11_sgn_ext[0:0]
- attribute \src "libresoc.v:20306.3-20360.6"
+ attribute \src "libresoc.v:20497.3-20551.6"
wire width 2 $1\dec31_dec_sub11_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub11_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub11_upd
- attribute \src "libresoc.v:19939.7-19939.15"
+ attribute \src "libresoc.v:20130.7-20130.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:19939.7-19939.20"
- process $proc$libresoc.v:19939$441
+ attribute \src "libresoc.v:20130.7-20130.20"
+ process $proc$libresoc.v:20130$481
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:20196.3-20250.6"
- process $proc$libresoc.v:20196$417
+ attribute \src "libresoc.v:20387.3-20441.6"
+ process $proc$libresoc.v:20387$457
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0]
- attribute \src "libresoc.v:20197.5-20197.29"
+ attribute \src "libresoc.v:20388.5-20388.29"
switch \initial
- attribute \src "libresoc.v:20197.9-20197.17"
+ attribute \src "libresoc.v:20388.9-20388.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0]
end
- attribute \src "libresoc.v:20251.3-20305.6"
- process $proc$libresoc.v:20251$418
+ attribute \src "libresoc.v:20442.3-20496.6"
+ process $proc$libresoc.v:20442$458
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0]
- attribute \src "libresoc.v:20252.5-20252.29"
+ attribute \src "libresoc.v:20443.5-20443.29"
switch \initial
- attribute \src "libresoc.v:20252.9-20252.17"
+ attribute \src "libresoc.v:20443.9-20443.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0]
end
- attribute \src "libresoc.v:20306.3-20360.6"
- process $proc$libresoc.v:20306$419
+ attribute \src "libresoc.v:20497.3-20551.6"
+ process $proc$libresoc.v:20497$459
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0]
- attribute \src "libresoc.v:20307.5-20307.29"
+ attribute \src "libresoc.v:20498.5-20498.29"
switch \initial
- attribute \src "libresoc.v:20307.9-20307.17"
+ attribute \src "libresoc.v:20498.9-20498.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0]
end
- attribute \src "libresoc.v:20361.3-20415.6"
- process $proc$libresoc.v:20361$420
+ attribute \src "libresoc.v:20552.3-20606.6"
+ process $proc$libresoc.v:20552$460
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0]
- attribute \src "libresoc.v:20362.5-20362.29"
+ attribute \src "libresoc.v:20553.5-20553.29"
switch \initial
- attribute \src "libresoc.v:20362.9-20362.17"
+ attribute \src "libresoc.v:20553.9-20553.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0]
end
- attribute \src "libresoc.v:20416.3-20470.6"
- process $proc$libresoc.v:20416$421
+ attribute \src "libresoc.v:20607.3-20661.6"
+ process $proc$libresoc.v:20607$461
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0]
- attribute \src "libresoc.v:20417.5-20417.29"
+ attribute \src "libresoc.v:20608.5-20608.29"
switch \initial
- attribute \src "libresoc.v:20417.9-20417.17"
+ attribute \src "libresoc.v:20608.9-20608.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0]
end
- attribute \src "libresoc.v:20471.3-20525.6"
- process $proc$libresoc.v:20471$422
+ attribute \src "libresoc.v:20662.3-20716.6"
+ process $proc$libresoc.v:20662$462
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0]
- attribute \src "libresoc.v:20472.5-20472.29"
+ attribute \src "libresoc.v:20663.5-20663.29"
switch \initial
- attribute \src "libresoc.v:20472.9-20472.17"
+ attribute \src "libresoc.v:20663.9-20663.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0]
end
- attribute \src "libresoc.v:20526.3-20580.6"
- process $proc$libresoc.v:20526$423
+ attribute \src "libresoc.v:20717.3-20771.6"
+ process $proc$libresoc.v:20717$463
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0]
- attribute \src "libresoc.v:20527.5-20527.29"
+ attribute \src "libresoc.v:20718.5-20718.29"
switch \initial
- attribute \src "libresoc.v:20527.9-20527.17"
+ attribute \src "libresoc.v:20718.9-20718.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0]
end
- attribute \src "libresoc.v:20581.3-20635.6"
- process $proc$libresoc.v:20581$424
+ attribute \src "libresoc.v:20772.3-20826.6"
+ process $proc$libresoc.v:20772$464
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0]
- attribute \src "libresoc.v:20582.5-20582.29"
+ attribute \src "libresoc.v:20773.5-20773.29"
switch \initial
- attribute \src "libresoc.v:20582.9-20582.17"
+ attribute \src "libresoc.v:20773.9-20773.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0]
end
- attribute \src "libresoc.v:20636.3-20690.6"
- process $proc$libresoc.v:20636$425
+ attribute \src "libresoc.v:20827.3-20881.6"
+ process $proc$libresoc.v:20827$465
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0]
- attribute \src "libresoc.v:20637.5-20637.29"
+ attribute \src "libresoc.v:20828.5-20828.29"
switch \initial
- attribute \src "libresoc.v:20637.9-20637.17"
+ attribute \src "libresoc.v:20828.9-20828.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0]
end
- attribute \src "libresoc.v:20691.3-20745.6"
- process $proc$libresoc.v:20691$426
+ attribute \src "libresoc.v:20882.3-20936.6"
+ process $proc$libresoc.v:20882$466
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0]
- attribute \src "libresoc.v:20692.5-20692.29"
+ attribute \src "libresoc.v:20883.5-20883.29"
switch \initial
- attribute \src "libresoc.v:20692.9-20692.17"
+ attribute \src "libresoc.v:20883.9-20883.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0]
end
- attribute \src "libresoc.v:20746.3-20800.6"
- process $proc$libresoc.v:20746$427
+ attribute \src "libresoc.v:20937.3-20991.6"
+ process $proc$libresoc.v:20937$467
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0]
- attribute \src "libresoc.v:20747.5-20747.29"
+ attribute \src "libresoc.v:20938.5-20938.29"
switch \initial
- attribute \src "libresoc.v:20747.9-20747.17"
+ attribute \src "libresoc.v:20938.9-20938.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0]
end
- attribute \src "libresoc.v:20801.3-20855.6"
- process $proc$libresoc.v:20801$428
+ attribute \src "libresoc.v:20992.3-21046.6"
+ process $proc$libresoc.v:20992$468
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0]
- attribute \src "libresoc.v:20802.5-20802.29"
+ attribute \src "libresoc.v:20993.5-20993.29"
switch \initial
- attribute \src "libresoc.v:20802.9-20802.17"
+ attribute \src "libresoc.v:20993.9-20993.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0]
end
- attribute \src "libresoc.v:20856.3-20910.6"
- process $proc$libresoc.v:20856$429
+ attribute \src "libresoc.v:21047.3-21101.6"
+ process $proc$libresoc.v:21047$469
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0]
- attribute \src "libresoc.v:20857.5-20857.29"
+ attribute \src "libresoc.v:21048.5-21048.29"
switch \initial
- attribute \src "libresoc.v:20857.9-20857.17"
+ attribute \src "libresoc.v:21048.9-21048.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0]
end
- attribute \src "libresoc.v:20911.3-20965.6"
- process $proc$libresoc.v:20911$430
+ attribute \src "libresoc.v:21102.3-21156.6"
+ process $proc$libresoc.v:21102$470
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0]
- attribute \src "libresoc.v:20912.5-20912.29"
+ attribute \src "libresoc.v:21103.5-21103.29"
switch \initial
- attribute \src "libresoc.v:20912.9-20912.17"
+ attribute \src "libresoc.v:21103.9-21103.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0]
end
- attribute \src "libresoc.v:20966.3-21020.6"
- process $proc$libresoc.v:20966$431
+ attribute \src "libresoc.v:21157.3-21211.6"
+ process $proc$libresoc.v:21157$471
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0]
- attribute \src "libresoc.v:20967.5-20967.29"
+ attribute \src "libresoc.v:21158.5-21158.29"
switch \initial
- attribute \src "libresoc.v:20967.9-20967.17"
+ attribute \src "libresoc.v:21158.9-21158.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0]
end
- attribute \src "libresoc.v:21021.3-21075.6"
- process $proc$libresoc.v:21021$432
+ attribute \src "libresoc.v:21212.3-21266.6"
+ process $proc$libresoc.v:21212$472
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0]
- attribute \src "libresoc.v:21022.5-21022.29"
+ attribute \src "libresoc.v:21213.5-21213.29"
switch \initial
- attribute \src "libresoc.v:21022.9-21022.17"
+ attribute \src "libresoc.v:21213.9-21213.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0]
end
- attribute \src "libresoc.v:21076.3-21130.6"
- process $proc$libresoc.v:21076$433
+ attribute \src "libresoc.v:21267.3-21321.6"
+ process $proc$libresoc.v:21267$473
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0]
- attribute \src "libresoc.v:21077.5-21077.29"
+ attribute \src "libresoc.v:21268.5-21268.29"
switch \initial
- attribute \src "libresoc.v:21077.9-21077.17"
+ attribute \src "libresoc.v:21268.9-21268.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:21131.3-21185.6"
- process $proc$libresoc.v:21131$434
+ attribute \src "libresoc.v:21322.3-21376.6"
+ process $proc$libresoc.v:21322$474
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0]
- attribute \src "libresoc.v:21132.5-21132.29"
+ attribute \src "libresoc.v:21323.5-21323.29"
switch \initial
- attribute \src "libresoc.v:21132.9-21132.17"
+ attribute \src "libresoc.v:21323.9-21323.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0]
end
- attribute \src "libresoc.v:21186.3-21240.6"
- process $proc$libresoc.v:21186$435
+ attribute \src "libresoc.v:21377.3-21431.6"
+ process $proc$libresoc.v:21377$475
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0]
- attribute \src "libresoc.v:21187.5-21187.29"
+ attribute \src "libresoc.v:21378.5-21378.29"
switch \initial
- attribute \src "libresoc.v:21187.9-21187.17"
+ attribute \src "libresoc.v:21378.9-21378.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0]
end
- attribute \src "libresoc.v:21241.3-21295.6"
- process $proc$libresoc.v:21241$436
+ attribute \src "libresoc.v:21432.3-21486.6"
+ process $proc$libresoc.v:21432$476
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0]
- attribute \src "libresoc.v:21242.5-21242.29"
+ attribute \src "libresoc.v:21433.5-21433.29"
switch \initial
- attribute \src "libresoc.v:21242.9-21242.17"
+ attribute \src "libresoc.v:21433.9-21433.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0]
end
- attribute \src "libresoc.v:21296.3-21350.6"
- process $proc$libresoc.v:21296$437
+ attribute \src "libresoc.v:21487.3-21541.6"
+ process $proc$libresoc.v:21487$477
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0]
- attribute \src "libresoc.v:21297.5-21297.29"
+ attribute \src "libresoc.v:21488.5-21488.29"
switch \initial
- attribute \src "libresoc.v:21297.9-21297.17"
+ attribute \src "libresoc.v:21488.9-21488.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0]
end
- attribute \src "libresoc.v:21351.3-21405.6"
- process $proc$libresoc.v:21351$438
+ attribute \src "libresoc.v:21542.3-21596.6"
+ process $proc$libresoc.v:21542$478
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0]
- attribute \src "libresoc.v:21352.5-21352.29"
+ attribute \src "libresoc.v:21543.5-21543.29"
switch \initial
- attribute \src "libresoc.v:21352.9-21352.17"
+ attribute \src "libresoc.v:21543.9-21543.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0]
end
- attribute \src "libresoc.v:21406.3-21460.6"
- process $proc$libresoc.v:21406$439
+ attribute \src "libresoc.v:21597.3-21651.6"
+ process $proc$libresoc.v:21597$479
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0]
- attribute \src "libresoc.v:21407.5-21407.29"
+ attribute \src "libresoc.v:21598.5-21598.29"
switch \initial
- attribute \src "libresoc.v:21407.9-21407.17"
+ attribute \src "libresoc.v:21598.9-21598.17"
case 1'1
case
end
sync always
update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0]
end
- attribute \src "libresoc.v:21461.3-21515.6"
- process $proc$libresoc.v:21461$440
+ attribute \src "libresoc.v:21652.3-21706.6"
+ process $proc$libresoc.v:21652$480
assign { } { }
assign { } { }
assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0]
- attribute \src "libresoc.v:21462.5-21462.29"
+ attribute \src "libresoc.v:21653.5-21653.29"
switch \initial
- attribute \src "libresoc.v:21462.9-21462.17"
+ attribute \src "libresoc.v:21653.9-21653.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:21521.1-24252.10"
+attribute \src "libresoc.v:21712.1-24443.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub15"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15"
attribute \generator "nMigen"
module \dec31_dec_sub15
- attribute \src "libresoc.v:22294.3-22396.6"
+ attribute \src "libresoc.v:22485.3-22587.6"
wire width 8 $0\dec31_dec_sub15_asmcode[7:0]
- attribute \src "libresoc.v:22706.3-22808.6"
+ attribute \src "libresoc.v:22897.3-22999.6"
wire $0\dec31_dec_sub15_br[0:0]
- attribute \src "libresoc.v:24045.3-24147.6"
+ attribute \src "libresoc.v:24236.3-24338.6"
wire width 3 $0\dec31_dec_sub15_cr_in[2:0]
- attribute \src "libresoc.v:24148.3-24250.6"
+ attribute \src "libresoc.v:24339.3-24441.6"
wire width 3 $0\dec31_dec_sub15_cr_out[2:0]
- attribute \src "libresoc.v:22191.3-22293.6"
+ attribute \src "libresoc.v:22382.3-22484.6"
wire width 2 $0\dec31_dec_sub15_cry_in[1:0]
- attribute \src "libresoc.v:22603.3-22705.6"
+ attribute \src "libresoc.v:22794.3-22896.6"
wire $0\dec31_dec_sub15_cry_out[0:0]
- attribute \src "libresoc.v:23530.3-23632.6"
+ attribute \src "libresoc.v:23721.3-23823.6"
wire width 5 $0\dec31_dec_sub15_form[4:0]
- attribute \src "libresoc.v:21779.3-21881.6"
+ attribute \src "libresoc.v:21970.3-22072.6"
wire width 12 $0\dec31_dec_sub15_function_unit[11:0]
- attribute \src "libresoc.v:23633.3-23735.6"
+ attribute \src "libresoc.v:23824.3-23926.6"
wire width 3 $0\dec31_dec_sub15_in1_sel[2:0]
- attribute \src "libresoc.v:23736.3-23838.6"
+ attribute \src "libresoc.v:23927.3-24029.6"
wire width 4 $0\dec31_dec_sub15_in2_sel[3:0]
- attribute \src "libresoc.v:23839.3-23941.6"
+ attribute \src "libresoc.v:24030.3-24132.6"
wire width 2 $0\dec31_dec_sub15_in3_sel[1:0]
- attribute \src "libresoc.v:22912.3-23014.6"
+ attribute \src "libresoc.v:23103.3-23205.6"
wire width 7 $0\dec31_dec_sub15_internal_op[6:0]
- attribute \src "libresoc.v:22397.3-22499.6"
+ attribute \src "libresoc.v:22588.3-22690.6"
wire $0\dec31_dec_sub15_inv_a[0:0]
- attribute \src "libresoc.v:22500.3-22602.6"
+ attribute \src "libresoc.v:22691.3-22793.6"
wire $0\dec31_dec_sub15_inv_out[0:0]
- attribute \src "libresoc.v:23118.3-23220.6"
+ attribute \src "libresoc.v:23309.3-23411.6"
wire $0\dec31_dec_sub15_is_32b[0:0]
- attribute \src "libresoc.v:21882.3-21984.6"
+ attribute \src "libresoc.v:22073.3-22175.6"
wire width 4 $0\dec31_dec_sub15_ldst_len[3:0]
- attribute \src "libresoc.v:23324.3-23426.6"
+ attribute \src "libresoc.v:23515.3-23617.6"
wire $0\dec31_dec_sub15_lk[0:0]
- attribute \src "libresoc.v:23942.3-24044.6"
+ attribute \src "libresoc.v:24133.3-24235.6"
wire width 2 $0\dec31_dec_sub15_out_sel[1:0]
- attribute \src "libresoc.v:22088.3-22190.6"
+ attribute \src "libresoc.v:22279.3-22381.6"
wire width 2 $0\dec31_dec_sub15_rc_sel[1:0]
- attribute \src "libresoc.v:23015.3-23117.6"
+ attribute \src "libresoc.v:23206.3-23308.6"
wire $0\dec31_dec_sub15_rsrv[0:0]
- attribute \src "libresoc.v:23427.3-23529.6"
+ attribute \src "libresoc.v:23618.3-23720.6"
wire $0\dec31_dec_sub15_sgl_pipe[0:0]
- attribute \src "libresoc.v:23221.3-23323.6"
+ attribute \src "libresoc.v:23412.3-23514.6"
wire $0\dec31_dec_sub15_sgn[0:0]
- attribute \src "libresoc.v:22809.3-22911.6"
+ attribute \src "libresoc.v:23000.3-23102.6"
wire $0\dec31_dec_sub15_sgn_ext[0:0]
- attribute \src "libresoc.v:21985.3-22087.6"
+ attribute \src "libresoc.v:22176.3-22278.6"
wire width 2 $0\dec31_dec_sub15_upd[1:0]
- attribute \src "libresoc.v:21522.7-21522.20"
+ attribute \src "libresoc.v:21713.7-21713.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:22294.3-22396.6"
+ attribute \src "libresoc.v:22485.3-22587.6"
wire width 8 $1\dec31_dec_sub15_asmcode[7:0]
- attribute \src "libresoc.v:22706.3-22808.6"
+ attribute \src "libresoc.v:22897.3-22999.6"
wire $1\dec31_dec_sub15_br[0:0]
- attribute \src "libresoc.v:24045.3-24147.6"
+ attribute \src "libresoc.v:24236.3-24338.6"
wire width 3 $1\dec31_dec_sub15_cr_in[2:0]
- attribute \src "libresoc.v:24148.3-24250.6"
+ attribute \src "libresoc.v:24339.3-24441.6"
wire width 3 $1\dec31_dec_sub15_cr_out[2:0]
- attribute \src "libresoc.v:22191.3-22293.6"
+ attribute \src "libresoc.v:22382.3-22484.6"
wire width 2 $1\dec31_dec_sub15_cry_in[1:0]
- attribute \src "libresoc.v:22603.3-22705.6"
+ attribute \src "libresoc.v:22794.3-22896.6"
wire $1\dec31_dec_sub15_cry_out[0:0]
- attribute \src "libresoc.v:23530.3-23632.6"
+ attribute \src "libresoc.v:23721.3-23823.6"
wire width 5 $1\dec31_dec_sub15_form[4:0]
- attribute \src "libresoc.v:21779.3-21881.6"
+ attribute \src "libresoc.v:21970.3-22072.6"
wire width 12 $1\dec31_dec_sub15_function_unit[11:0]
- attribute \src "libresoc.v:23633.3-23735.6"
+ attribute \src "libresoc.v:23824.3-23926.6"
wire width 3 $1\dec31_dec_sub15_in1_sel[2:0]
- attribute \src "libresoc.v:23736.3-23838.6"
+ attribute \src "libresoc.v:23927.3-24029.6"
wire width 4 $1\dec31_dec_sub15_in2_sel[3:0]
- attribute \src "libresoc.v:23839.3-23941.6"
+ attribute \src "libresoc.v:24030.3-24132.6"
wire width 2 $1\dec31_dec_sub15_in3_sel[1:0]
- attribute \src "libresoc.v:22912.3-23014.6"
+ attribute \src "libresoc.v:23103.3-23205.6"
wire width 7 $1\dec31_dec_sub15_internal_op[6:0]
- attribute \src "libresoc.v:22397.3-22499.6"
+ attribute \src "libresoc.v:22588.3-22690.6"
wire $1\dec31_dec_sub15_inv_a[0:0]
- attribute \src "libresoc.v:22500.3-22602.6"
+ attribute \src "libresoc.v:22691.3-22793.6"
wire $1\dec31_dec_sub15_inv_out[0:0]
- attribute \src "libresoc.v:23118.3-23220.6"
+ attribute \src "libresoc.v:23309.3-23411.6"
wire $1\dec31_dec_sub15_is_32b[0:0]
- attribute \src "libresoc.v:21882.3-21984.6"
+ attribute \src "libresoc.v:22073.3-22175.6"
wire width 4 $1\dec31_dec_sub15_ldst_len[3:0]
- attribute \src "libresoc.v:23324.3-23426.6"
+ attribute \src "libresoc.v:23515.3-23617.6"
wire $1\dec31_dec_sub15_lk[0:0]
- attribute \src "libresoc.v:23942.3-24044.6"
+ attribute \src "libresoc.v:24133.3-24235.6"
wire width 2 $1\dec31_dec_sub15_out_sel[1:0]
- attribute \src "libresoc.v:22088.3-22190.6"
+ attribute \src "libresoc.v:22279.3-22381.6"
wire width 2 $1\dec31_dec_sub15_rc_sel[1:0]
- attribute \src "libresoc.v:23015.3-23117.6"
+ attribute \src "libresoc.v:23206.3-23308.6"
wire $1\dec31_dec_sub15_rsrv[0:0]
- attribute \src "libresoc.v:23427.3-23529.6"
+ attribute \src "libresoc.v:23618.3-23720.6"
wire $1\dec31_dec_sub15_sgl_pipe[0:0]
- attribute \src "libresoc.v:23221.3-23323.6"
+ attribute \src "libresoc.v:23412.3-23514.6"
wire $1\dec31_dec_sub15_sgn[0:0]
- attribute \src "libresoc.v:22809.3-22911.6"
+ attribute \src "libresoc.v:23000.3-23102.6"
wire $1\dec31_dec_sub15_sgn_ext[0:0]
- attribute \src "libresoc.v:21985.3-22087.6"
+ attribute \src "libresoc.v:22176.3-22278.6"
wire width 2 $1\dec31_dec_sub15_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub15_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub15_upd
- attribute \src "libresoc.v:21522.7-21522.15"
+ attribute \src "libresoc.v:21713.7-21713.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:21522.7-21522.20"
- process $proc$libresoc.v:21522$466
+ attribute \src "libresoc.v:21713.7-21713.20"
+ process $proc$libresoc.v:21713$506
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:21779.3-21881.6"
- process $proc$libresoc.v:21779$442
+ attribute \src "libresoc.v:21970.3-22072.6"
+ process $proc$libresoc.v:21970$482
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0]
- attribute \src "libresoc.v:21780.5-21780.29"
+ attribute \src "libresoc.v:21971.5-21971.29"
switch \initial
- attribute \src "libresoc.v:21780.9-21780.17"
+ attribute \src "libresoc.v:21971.9-21971.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0]
end
- attribute \src "libresoc.v:21882.3-21984.6"
- process $proc$libresoc.v:21882$443
+ attribute \src "libresoc.v:22073.3-22175.6"
+ process $proc$libresoc.v:22073$483
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0]
- attribute \src "libresoc.v:21883.5-21883.29"
+ attribute \src "libresoc.v:22074.5-22074.29"
switch \initial
- attribute \src "libresoc.v:21883.9-21883.17"
+ attribute \src "libresoc.v:22074.9-22074.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0]
end
- attribute \src "libresoc.v:21985.3-22087.6"
- process $proc$libresoc.v:21985$444
+ attribute \src "libresoc.v:22176.3-22278.6"
+ process $proc$libresoc.v:22176$484
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0]
- attribute \src "libresoc.v:21986.5-21986.29"
+ attribute \src "libresoc.v:22177.5-22177.29"
switch \initial
- attribute \src "libresoc.v:21986.9-21986.17"
+ attribute \src "libresoc.v:22177.9-22177.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0]
end
- attribute \src "libresoc.v:22088.3-22190.6"
- process $proc$libresoc.v:22088$445
+ attribute \src "libresoc.v:22279.3-22381.6"
+ process $proc$libresoc.v:22279$485
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0]
- attribute \src "libresoc.v:22089.5-22089.29"
+ attribute \src "libresoc.v:22280.5-22280.29"
switch \initial
- attribute \src "libresoc.v:22089.9-22089.17"
+ attribute \src "libresoc.v:22280.9-22280.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0]
end
- attribute \src "libresoc.v:22191.3-22293.6"
- process $proc$libresoc.v:22191$446
+ attribute \src "libresoc.v:22382.3-22484.6"
+ process $proc$libresoc.v:22382$486
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0]
- attribute \src "libresoc.v:22192.5-22192.29"
+ attribute \src "libresoc.v:22383.5-22383.29"
switch \initial
- attribute \src "libresoc.v:22192.9-22192.17"
+ attribute \src "libresoc.v:22383.9-22383.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0]
end
- attribute \src "libresoc.v:22294.3-22396.6"
- process $proc$libresoc.v:22294$447
+ attribute \src "libresoc.v:22485.3-22587.6"
+ process $proc$libresoc.v:22485$487
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0]
- attribute \src "libresoc.v:22295.5-22295.29"
+ attribute \src "libresoc.v:22486.5-22486.29"
switch \initial
- attribute \src "libresoc.v:22295.9-22295.17"
+ attribute \src "libresoc.v:22486.9-22486.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0]
end
- attribute \src "libresoc.v:22397.3-22499.6"
- process $proc$libresoc.v:22397$448
+ attribute \src "libresoc.v:22588.3-22690.6"
+ process $proc$libresoc.v:22588$488
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0]
- attribute \src "libresoc.v:22398.5-22398.29"
+ attribute \src "libresoc.v:22589.5-22589.29"
switch \initial
- attribute \src "libresoc.v:22398.9-22398.17"
+ attribute \src "libresoc.v:22589.9-22589.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0]
end
- attribute \src "libresoc.v:22500.3-22602.6"
- process $proc$libresoc.v:22500$449
+ attribute \src "libresoc.v:22691.3-22793.6"
+ process $proc$libresoc.v:22691$489
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0]
- attribute \src "libresoc.v:22501.5-22501.29"
+ attribute \src "libresoc.v:22692.5-22692.29"
switch \initial
- attribute \src "libresoc.v:22501.9-22501.17"
+ attribute \src "libresoc.v:22692.9-22692.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0]
end
- attribute \src "libresoc.v:22603.3-22705.6"
- process $proc$libresoc.v:22603$450
+ attribute \src "libresoc.v:22794.3-22896.6"
+ process $proc$libresoc.v:22794$490
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0]
- attribute \src "libresoc.v:22604.5-22604.29"
+ attribute \src "libresoc.v:22795.5-22795.29"
switch \initial
- attribute \src "libresoc.v:22604.9-22604.17"
+ attribute \src "libresoc.v:22795.9-22795.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0]
end
- attribute \src "libresoc.v:22706.3-22808.6"
- process $proc$libresoc.v:22706$451
+ attribute \src "libresoc.v:22897.3-22999.6"
+ process $proc$libresoc.v:22897$491
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0]
- attribute \src "libresoc.v:22707.5-22707.29"
+ attribute \src "libresoc.v:22898.5-22898.29"
switch \initial
- attribute \src "libresoc.v:22707.9-22707.17"
+ attribute \src "libresoc.v:22898.9-22898.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0]
end
- attribute \src "libresoc.v:22809.3-22911.6"
- process $proc$libresoc.v:22809$452
+ attribute \src "libresoc.v:23000.3-23102.6"
+ process $proc$libresoc.v:23000$492
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0]
- attribute \src "libresoc.v:22810.5-22810.29"
+ attribute \src "libresoc.v:23001.5-23001.29"
switch \initial
- attribute \src "libresoc.v:22810.9-22810.17"
+ attribute \src "libresoc.v:23001.9-23001.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0]
end
- attribute \src "libresoc.v:22912.3-23014.6"
- process $proc$libresoc.v:22912$453
+ attribute \src "libresoc.v:23103.3-23205.6"
+ process $proc$libresoc.v:23103$493
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0]
- attribute \src "libresoc.v:22913.5-22913.29"
+ attribute \src "libresoc.v:23104.5-23104.29"
switch \initial
- attribute \src "libresoc.v:22913.9-22913.17"
+ attribute \src "libresoc.v:23104.9-23104.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0]
end
- attribute \src "libresoc.v:23015.3-23117.6"
- process $proc$libresoc.v:23015$454
+ attribute \src "libresoc.v:23206.3-23308.6"
+ process $proc$libresoc.v:23206$494
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0]
- attribute \src "libresoc.v:23016.5-23016.29"
+ attribute \src "libresoc.v:23207.5-23207.29"
switch \initial
- attribute \src "libresoc.v:23016.9-23016.17"
+ attribute \src "libresoc.v:23207.9-23207.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0]
end
- attribute \src "libresoc.v:23118.3-23220.6"
- process $proc$libresoc.v:23118$455
+ attribute \src "libresoc.v:23309.3-23411.6"
+ process $proc$libresoc.v:23309$495
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0]
- attribute \src "libresoc.v:23119.5-23119.29"
+ attribute \src "libresoc.v:23310.5-23310.29"
switch \initial
- attribute \src "libresoc.v:23119.9-23119.17"
+ attribute \src "libresoc.v:23310.9-23310.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0]
end
- attribute \src "libresoc.v:23221.3-23323.6"
- process $proc$libresoc.v:23221$456
+ attribute \src "libresoc.v:23412.3-23514.6"
+ process $proc$libresoc.v:23412$496
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0]
- attribute \src "libresoc.v:23222.5-23222.29"
+ attribute \src "libresoc.v:23413.5-23413.29"
switch \initial
- attribute \src "libresoc.v:23222.9-23222.17"
+ attribute \src "libresoc.v:23413.9-23413.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0]
end
- attribute \src "libresoc.v:23324.3-23426.6"
- process $proc$libresoc.v:23324$457
+ attribute \src "libresoc.v:23515.3-23617.6"
+ process $proc$libresoc.v:23515$497
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0]
- attribute \src "libresoc.v:23325.5-23325.29"
+ attribute \src "libresoc.v:23516.5-23516.29"
switch \initial
- attribute \src "libresoc.v:23325.9-23325.17"
+ attribute \src "libresoc.v:23516.9-23516.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0]
end
- attribute \src "libresoc.v:23427.3-23529.6"
- process $proc$libresoc.v:23427$458
+ attribute \src "libresoc.v:23618.3-23720.6"
+ process $proc$libresoc.v:23618$498
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0]
- attribute \src "libresoc.v:23428.5-23428.29"
+ attribute \src "libresoc.v:23619.5-23619.29"
switch \initial
- attribute \src "libresoc.v:23428.9-23428.17"
+ attribute \src "libresoc.v:23619.9-23619.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:23530.3-23632.6"
- process $proc$libresoc.v:23530$459
+ attribute \src "libresoc.v:23721.3-23823.6"
+ process $proc$libresoc.v:23721$499
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0]
- attribute \src "libresoc.v:23531.5-23531.29"
+ attribute \src "libresoc.v:23722.5-23722.29"
switch \initial
- attribute \src "libresoc.v:23531.9-23531.17"
+ attribute \src "libresoc.v:23722.9-23722.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0]
end
- attribute \src "libresoc.v:23633.3-23735.6"
- process $proc$libresoc.v:23633$460
+ attribute \src "libresoc.v:23824.3-23926.6"
+ process $proc$libresoc.v:23824$500
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0]
- attribute \src "libresoc.v:23634.5-23634.29"
+ attribute \src "libresoc.v:23825.5-23825.29"
switch \initial
- attribute \src "libresoc.v:23634.9-23634.17"
+ attribute \src "libresoc.v:23825.9-23825.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0]
end
- attribute \src "libresoc.v:23736.3-23838.6"
- process $proc$libresoc.v:23736$461
+ attribute \src "libresoc.v:23927.3-24029.6"
+ process $proc$libresoc.v:23927$501
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0]
- attribute \src "libresoc.v:23737.5-23737.29"
+ attribute \src "libresoc.v:23928.5-23928.29"
switch \initial
- attribute \src "libresoc.v:23737.9-23737.17"
+ attribute \src "libresoc.v:23928.9-23928.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0]
end
- attribute \src "libresoc.v:23839.3-23941.6"
- process $proc$libresoc.v:23839$462
+ attribute \src "libresoc.v:24030.3-24132.6"
+ process $proc$libresoc.v:24030$502
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0]
- attribute \src "libresoc.v:23840.5-23840.29"
+ attribute \src "libresoc.v:24031.5-24031.29"
switch \initial
- attribute \src "libresoc.v:23840.9-23840.17"
+ attribute \src "libresoc.v:24031.9-24031.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0]
end
- attribute \src "libresoc.v:23942.3-24044.6"
- process $proc$libresoc.v:23942$463
+ attribute \src "libresoc.v:24133.3-24235.6"
+ process $proc$libresoc.v:24133$503
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0]
- attribute \src "libresoc.v:23943.5-23943.29"
+ attribute \src "libresoc.v:24134.5-24134.29"
switch \initial
- attribute \src "libresoc.v:23943.9-23943.17"
+ attribute \src "libresoc.v:24134.9-24134.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0]
end
- attribute \src "libresoc.v:24045.3-24147.6"
- process $proc$libresoc.v:24045$464
+ attribute \src "libresoc.v:24236.3-24338.6"
+ process $proc$libresoc.v:24236$504
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0]
- attribute \src "libresoc.v:24046.5-24046.29"
+ attribute \src "libresoc.v:24237.5-24237.29"
switch \initial
- attribute \src "libresoc.v:24046.9-24046.17"
+ attribute \src "libresoc.v:24237.9-24237.17"
case 1'1
case
end
sync always
update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0]
end
- attribute \src "libresoc.v:24148.3-24250.6"
- process $proc$libresoc.v:24148$465
+ attribute \src "libresoc.v:24339.3-24441.6"
+ process $proc$libresoc.v:24339$505
assign { } { }
assign { } { }
assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0]
- attribute \src "libresoc.v:24149.5-24149.29"
+ attribute \src "libresoc.v:24340.5-24340.29"
switch \initial
- attribute \src "libresoc.v:24149.9-24149.17"
+ attribute \src "libresoc.v:24340.9-24340.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:24256.1-24755.10"
+attribute \src "libresoc.v:24447.1-24946.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub16"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16"
attribute \generator "nMigen"
module \dec31_dec_sub16
- attribute \src "libresoc.v:24564.3-24573.6"
+ attribute \src "libresoc.v:24755.3-24764.6"
wire width 8 $0\dec31_dec_sub16_asmcode[7:0]
- attribute \src "libresoc.v:24604.3-24613.6"
+ attribute \src "libresoc.v:24795.3-24804.6"
wire $0\dec31_dec_sub16_br[0:0]
- attribute \src "libresoc.v:24734.3-24743.6"
+ attribute \src "libresoc.v:24925.3-24934.6"
wire width 3 $0\dec31_dec_sub16_cr_in[2:0]
- attribute \src "libresoc.v:24744.3-24753.6"
+ attribute \src "libresoc.v:24935.3-24944.6"
wire width 3 $0\dec31_dec_sub16_cr_out[2:0]
- attribute \src "libresoc.v:24554.3-24563.6"
+ attribute \src "libresoc.v:24745.3-24754.6"
wire width 2 $0\dec31_dec_sub16_cry_in[1:0]
- attribute \src "libresoc.v:24594.3-24603.6"
+ attribute \src "libresoc.v:24785.3-24794.6"
wire $0\dec31_dec_sub16_cry_out[0:0]
- attribute \src "libresoc.v:24684.3-24693.6"
+ attribute \src "libresoc.v:24875.3-24884.6"
wire width 5 $0\dec31_dec_sub16_form[4:0]
- attribute \src "libresoc.v:24514.3-24523.6"
+ attribute \src "libresoc.v:24705.3-24714.6"
wire width 12 $0\dec31_dec_sub16_function_unit[11:0]
- attribute \src "libresoc.v:24694.3-24703.6"
+ attribute \src "libresoc.v:24885.3-24894.6"
wire width 3 $0\dec31_dec_sub16_in1_sel[2:0]
- attribute \src "libresoc.v:24704.3-24713.6"
+ attribute \src "libresoc.v:24895.3-24904.6"
wire width 4 $0\dec31_dec_sub16_in2_sel[3:0]
- attribute \src "libresoc.v:24714.3-24723.6"
+ attribute \src "libresoc.v:24905.3-24914.6"
wire width 2 $0\dec31_dec_sub16_in3_sel[1:0]
- attribute \src "libresoc.v:24624.3-24633.6"
+ attribute \src "libresoc.v:24815.3-24824.6"
wire width 7 $0\dec31_dec_sub16_internal_op[6:0]
- attribute \src "libresoc.v:24574.3-24583.6"
+ attribute \src "libresoc.v:24765.3-24774.6"
wire $0\dec31_dec_sub16_inv_a[0:0]
- attribute \src "libresoc.v:24584.3-24593.6"
+ attribute \src "libresoc.v:24775.3-24784.6"
wire $0\dec31_dec_sub16_inv_out[0:0]
- attribute \src "libresoc.v:24644.3-24653.6"
+ attribute \src "libresoc.v:24835.3-24844.6"
wire $0\dec31_dec_sub16_is_32b[0:0]
- attribute \src "libresoc.v:24524.3-24533.6"
+ attribute \src "libresoc.v:24715.3-24724.6"
wire width 4 $0\dec31_dec_sub16_ldst_len[3:0]
- attribute \src "libresoc.v:24664.3-24673.6"
+ attribute \src "libresoc.v:24855.3-24864.6"
wire $0\dec31_dec_sub16_lk[0:0]
- attribute \src "libresoc.v:24724.3-24733.6"
+ attribute \src "libresoc.v:24915.3-24924.6"
wire width 2 $0\dec31_dec_sub16_out_sel[1:0]
- attribute \src "libresoc.v:24544.3-24553.6"
+ attribute \src "libresoc.v:24735.3-24744.6"
wire width 2 $0\dec31_dec_sub16_rc_sel[1:0]
- attribute \src "libresoc.v:24634.3-24643.6"
+ attribute \src "libresoc.v:24825.3-24834.6"
wire $0\dec31_dec_sub16_rsrv[0:0]
- attribute \src "libresoc.v:24674.3-24683.6"
+ attribute \src "libresoc.v:24865.3-24874.6"
wire $0\dec31_dec_sub16_sgl_pipe[0:0]
- attribute \src "libresoc.v:24654.3-24663.6"
+ attribute \src "libresoc.v:24845.3-24854.6"
wire $0\dec31_dec_sub16_sgn[0:0]
- attribute \src "libresoc.v:24614.3-24623.6"
+ attribute \src "libresoc.v:24805.3-24814.6"
wire $0\dec31_dec_sub16_sgn_ext[0:0]
- attribute \src "libresoc.v:24534.3-24543.6"
+ attribute \src "libresoc.v:24725.3-24734.6"
wire width 2 $0\dec31_dec_sub16_upd[1:0]
- attribute \src "libresoc.v:24257.7-24257.20"
+ attribute \src "libresoc.v:24448.7-24448.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:24564.3-24573.6"
+ attribute \src "libresoc.v:24755.3-24764.6"
wire width 8 $1\dec31_dec_sub16_asmcode[7:0]
- attribute \src "libresoc.v:24604.3-24613.6"
+ attribute \src "libresoc.v:24795.3-24804.6"
wire $1\dec31_dec_sub16_br[0:0]
- attribute \src "libresoc.v:24734.3-24743.6"
+ attribute \src "libresoc.v:24925.3-24934.6"
wire width 3 $1\dec31_dec_sub16_cr_in[2:0]
- attribute \src "libresoc.v:24744.3-24753.6"
+ attribute \src "libresoc.v:24935.3-24944.6"
wire width 3 $1\dec31_dec_sub16_cr_out[2:0]
- attribute \src "libresoc.v:24554.3-24563.6"
+ attribute \src "libresoc.v:24745.3-24754.6"
wire width 2 $1\dec31_dec_sub16_cry_in[1:0]
- attribute \src "libresoc.v:24594.3-24603.6"
+ attribute \src "libresoc.v:24785.3-24794.6"
wire $1\dec31_dec_sub16_cry_out[0:0]
- attribute \src "libresoc.v:24684.3-24693.6"
+ attribute \src "libresoc.v:24875.3-24884.6"
wire width 5 $1\dec31_dec_sub16_form[4:0]
- attribute \src "libresoc.v:24514.3-24523.6"
+ attribute \src "libresoc.v:24705.3-24714.6"
wire width 12 $1\dec31_dec_sub16_function_unit[11:0]
- attribute \src "libresoc.v:24694.3-24703.6"
+ attribute \src "libresoc.v:24885.3-24894.6"
wire width 3 $1\dec31_dec_sub16_in1_sel[2:0]
- attribute \src "libresoc.v:24704.3-24713.6"
+ attribute \src "libresoc.v:24895.3-24904.6"
wire width 4 $1\dec31_dec_sub16_in2_sel[3:0]
- attribute \src "libresoc.v:24714.3-24723.6"
+ attribute \src "libresoc.v:24905.3-24914.6"
wire width 2 $1\dec31_dec_sub16_in3_sel[1:0]
- attribute \src "libresoc.v:24624.3-24633.6"
+ attribute \src "libresoc.v:24815.3-24824.6"
wire width 7 $1\dec31_dec_sub16_internal_op[6:0]
- attribute \src "libresoc.v:24574.3-24583.6"
+ attribute \src "libresoc.v:24765.3-24774.6"
wire $1\dec31_dec_sub16_inv_a[0:0]
- attribute \src "libresoc.v:24584.3-24593.6"
+ attribute \src "libresoc.v:24775.3-24784.6"
wire $1\dec31_dec_sub16_inv_out[0:0]
- attribute \src "libresoc.v:24644.3-24653.6"
+ attribute \src "libresoc.v:24835.3-24844.6"
wire $1\dec31_dec_sub16_is_32b[0:0]
- attribute \src "libresoc.v:24524.3-24533.6"
+ attribute \src "libresoc.v:24715.3-24724.6"
wire width 4 $1\dec31_dec_sub16_ldst_len[3:0]
- attribute \src "libresoc.v:24664.3-24673.6"
+ attribute \src "libresoc.v:24855.3-24864.6"
wire $1\dec31_dec_sub16_lk[0:0]
- attribute \src "libresoc.v:24724.3-24733.6"
+ attribute \src "libresoc.v:24915.3-24924.6"
wire width 2 $1\dec31_dec_sub16_out_sel[1:0]
- attribute \src "libresoc.v:24544.3-24553.6"
+ attribute \src "libresoc.v:24735.3-24744.6"
wire width 2 $1\dec31_dec_sub16_rc_sel[1:0]
- attribute \src "libresoc.v:24634.3-24643.6"
+ attribute \src "libresoc.v:24825.3-24834.6"
wire $1\dec31_dec_sub16_rsrv[0:0]
- attribute \src "libresoc.v:24674.3-24683.6"
+ attribute \src "libresoc.v:24865.3-24874.6"
wire $1\dec31_dec_sub16_sgl_pipe[0:0]
- attribute \src "libresoc.v:24654.3-24663.6"
+ attribute \src "libresoc.v:24845.3-24854.6"
wire $1\dec31_dec_sub16_sgn[0:0]
- attribute \src "libresoc.v:24614.3-24623.6"
+ attribute \src "libresoc.v:24805.3-24814.6"
wire $1\dec31_dec_sub16_sgn_ext[0:0]
- attribute \src "libresoc.v:24534.3-24543.6"
+ attribute \src "libresoc.v:24725.3-24734.6"
wire width 2 $1\dec31_dec_sub16_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub16_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub16_upd
- attribute \src "libresoc.v:24257.7-24257.15"
+ attribute \src "libresoc.v:24448.7-24448.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:24257.7-24257.20"
- process $proc$libresoc.v:24257$491
+ attribute \src "libresoc.v:24448.7-24448.20"
+ process $proc$libresoc.v:24448$531
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:24514.3-24523.6"
- process $proc$libresoc.v:24514$467
+ attribute \src "libresoc.v:24705.3-24714.6"
+ process $proc$libresoc.v:24705$507
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0]
- attribute \src "libresoc.v:24515.5-24515.29"
+ attribute \src "libresoc.v:24706.5-24706.29"
switch \initial
- attribute \src "libresoc.v:24515.9-24515.17"
+ attribute \src "libresoc.v:24706.9-24706.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0]
end
- attribute \src "libresoc.v:24524.3-24533.6"
- process $proc$libresoc.v:24524$468
+ attribute \src "libresoc.v:24715.3-24724.6"
+ process $proc$libresoc.v:24715$508
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0]
- attribute \src "libresoc.v:24525.5-24525.29"
+ attribute \src "libresoc.v:24716.5-24716.29"
switch \initial
- attribute \src "libresoc.v:24525.9-24525.17"
+ attribute \src "libresoc.v:24716.9-24716.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0]
end
- attribute \src "libresoc.v:24534.3-24543.6"
- process $proc$libresoc.v:24534$469
+ attribute \src "libresoc.v:24725.3-24734.6"
+ process $proc$libresoc.v:24725$509
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0]
- attribute \src "libresoc.v:24535.5-24535.29"
+ attribute \src "libresoc.v:24726.5-24726.29"
switch \initial
- attribute \src "libresoc.v:24535.9-24535.17"
+ attribute \src "libresoc.v:24726.9-24726.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0]
end
- attribute \src "libresoc.v:24544.3-24553.6"
- process $proc$libresoc.v:24544$470
+ attribute \src "libresoc.v:24735.3-24744.6"
+ process $proc$libresoc.v:24735$510
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0]
- attribute \src "libresoc.v:24545.5-24545.29"
+ attribute \src "libresoc.v:24736.5-24736.29"
switch \initial
- attribute \src "libresoc.v:24545.9-24545.17"
+ attribute \src "libresoc.v:24736.9-24736.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0]
end
- attribute \src "libresoc.v:24554.3-24563.6"
- process $proc$libresoc.v:24554$471
+ attribute \src "libresoc.v:24745.3-24754.6"
+ process $proc$libresoc.v:24745$511
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0]
- attribute \src "libresoc.v:24555.5-24555.29"
+ attribute \src "libresoc.v:24746.5-24746.29"
switch \initial
- attribute \src "libresoc.v:24555.9-24555.17"
+ attribute \src "libresoc.v:24746.9-24746.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0]
end
- attribute \src "libresoc.v:24564.3-24573.6"
- process $proc$libresoc.v:24564$472
+ attribute \src "libresoc.v:24755.3-24764.6"
+ process $proc$libresoc.v:24755$512
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0]
- attribute \src "libresoc.v:24565.5-24565.29"
+ attribute \src "libresoc.v:24756.5-24756.29"
switch \initial
- attribute \src "libresoc.v:24565.9-24565.17"
+ attribute \src "libresoc.v:24756.9-24756.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0]
end
- attribute \src "libresoc.v:24574.3-24583.6"
- process $proc$libresoc.v:24574$473
+ attribute \src "libresoc.v:24765.3-24774.6"
+ process $proc$libresoc.v:24765$513
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0]
- attribute \src "libresoc.v:24575.5-24575.29"
+ attribute \src "libresoc.v:24766.5-24766.29"
switch \initial
- attribute \src "libresoc.v:24575.9-24575.17"
+ attribute \src "libresoc.v:24766.9-24766.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0]
end
- attribute \src "libresoc.v:24584.3-24593.6"
- process $proc$libresoc.v:24584$474
+ attribute \src "libresoc.v:24775.3-24784.6"
+ process $proc$libresoc.v:24775$514
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0]
- attribute \src "libresoc.v:24585.5-24585.29"
+ attribute \src "libresoc.v:24776.5-24776.29"
switch \initial
- attribute \src "libresoc.v:24585.9-24585.17"
+ attribute \src "libresoc.v:24776.9-24776.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0]
end
- attribute \src "libresoc.v:24594.3-24603.6"
- process $proc$libresoc.v:24594$475
+ attribute \src "libresoc.v:24785.3-24794.6"
+ process $proc$libresoc.v:24785$515
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0]
- attribute \src "libresoc.v:24595.5-24595.29"
+ attribute \src "libresoc.v:24786.5-24786.29"
switch \initial
- attribute \src "libresoc.v:24595.9-24595.17"
+ attribute \src "libresoc.v:24786.9-24786.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0]
end
- attribute \src "libresoc.v:24604.3-24613.6"
- process $proc$libresoc.v:24604$476
+ attribute \src "libresoc.v:24795.3-24804.6"
+ process $proc$libresoc.v:24795$516
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0]
- attribute \src "libresoc.v:24605.5-24605.29"
+ attribute \src "libresoc.v:24796.5-24796.29"
switch \initial
- attribute \src "libresoc.v:24605.9-24605.17"
+ attribute \src "libresoc.v:24796.9-24796.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0]
end
- attribute \src "libresoc.v:24614.3-24623.6"
- process $proc$libresoc.v:24614$477
+ attribute \src "libresoc.v:24805.3-24814.6"
+ process $proc$libresoc.v:24805$517
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0]
- attribute \src "libresoc.v:24615.5-24615.29"
+ attribute \src "libresoc.v:24806.5-24806.29"
switch \initial
- attribute \src "libresoc.v:24615.9-24615.17"
+ attribute \src "libresoc.v:24806.9-24806.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0]
end
- attribute \src "libresoc.v:24624.3-24633.6"
- process $proc$libresoc.v:24624$478
+ attribute \src "libresoc.v:24815.3-24824.6"
+ process $proc$libresoc.v:24815$518
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0]
- attribute \src "libresoc.v:24625.5-24625.29"
+ attribute \src "libresoc.v:24816.5-24816.29"
switch \initial
- attribute \src "libresoc.v:24625.9-24625.17"
+ attribute \src "libresoc.v:24816.9-24816.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0]
end
- attribute \src "libresoc.v:24634.3-24643.6"
- process $proc$libresoc.v:24634$479
+ attribute \src "libresoc.v:24825.3-24834.6"
+ process $proc$libresoc.v:24825$519
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0]
- attribute \src "libresoc.v:24635.5-24635.29"
+ attribute \src "libresoc.v:24826.5-24826.29"
switch \initial
- attribute \src "libresoc.v:24635.9-24635.17"
+ attribute \src "libresoc.v:24826.9-24826.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0]
end
- attribute \src "libresoc.v:24644.3-24653.6"
- process $proc$libresoc.v:24644$480
+ attribute \src "libresoc.v:24835.3-24844.6"
+ process $proc$libresoc.v:24835$520
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0]
- attribute \src "libresoc.v:24645.5-24645.29"
+ attribute \src "libresoc.v:24836.5-24836.29"
switch \initial
- attribute \src "libresoc.v:24645.9-24645.17"
+ attribute \src "libresoc.v:24836.9-24836.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0]
end
- attribute \src "libresoc.v:24654.3-24663.6"
- process $proc$libresoc.v:24654$481
+ attribute \src "libresoc.v:24845.3-24854.6"
+ process $proc$libresoc.v:24845$521
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0]
- attribute \src "libresoc.v:24655.5-24655.29"
+ attribute \src "libresoc.v:24846.5-24846.29"
switch \initial
- attribute \src "libresoc.v:24655.9-24655.17"
+ attribute \src "libresoc.v:24846.9-24846.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0]
end
- attribute \src "libresoc.v:24664.3-24673.6"
- process $proc$libresoc.v:24664$482
+ attribute \src "libresoc.v:24855.3-24864.6"
+ process $proc$libresoc.v:24855$522
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0]
- attribute \src "libresoc.v:24665.5-24665.29"
+ attribute \src "libresoc.v:24856.5-24856.29"
switch \initial
- attribute \src "libresoc.v:24665.9-24665.17"
+ attribute \src "libresoc.v:24856.9-24856.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0]
end
- attribute \src "libresoc.v:24674.3-24683.6"
- process $proc$libresoc.v:24674$483
+ attribute \src "libresoc.v:24865.3-24874.6"
+ process $proc$libresoc.v:24865$523
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0]
- attribute \src "libresoc.v:24675.5-24675.29"
+ attribute \src "libresoc.v:24866.5-24866.29"
switch \initial
- attribute \src "libresoc.v:24675.9-24675.17"
+ attribute \src "libresoc.v:24866.9-24866.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:24684.3-24693.6"
- process $proc$libresoc.v:24684$484
+ attribute \src "libresoc.v:24875.3-24884.6"
+ process $proc$libresoc.v:24875$524
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0]
- attribute \src "libresoc.v:24685.5-24685.29"
+ attribute \src "libresoc.v:24876.5-24876.29"
switch \initial
- attribute \src "libresoc.v:24685.9-24685.17"
+ attribute \src "libresoc.v:24876.9-24876.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0]
end
- attribute \src "libresoc.v:24694.3-24703.6"
- process $proc$libresoc.v:24694$485
+ attribute \src "libresoc.v:24885.3-24894.6"
+ process $proc$libresoc.v:24885$525
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0]
- attribute \src "libresoc.v:24695.5-24695.29"
+ attribute \src "libresoc.v:24886.5-24886.29"
switch \initial
- attribute \src "libresoc.v:24695.9-24695.17"
+ attribute \src "libresoc.v:24886.9-24886.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0]
end
- attribute \src "libresoc.v:24704.3-24713.6"
- process $proc$libresoc.v:24704$486
+ attribute \src "libresoc.v:24895.3-24904.6"
+ process $proc$libresoc.v:24895$526
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0]
- attribute \src "libresoc.v:24705.5-24705.29"
+ attribute \src "libresoc.v:24896.5-24896.29"
switch \initial
- attribute \src "libresoc.v:24705.9-24705.17"
+ attribute \src "libresoc.v:24896.9-24896.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0]
end
- attribute \src "libresoc.v:24714.3-24723.6"
- process $proc$libresoc.v:24714$487
+ attribute \src "libresoc.v:24905.3-24914.6"
+ process $proc$libresoc.v:24905$527
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0]
- attribute \src "libresoc.v:24715.5-24715.29"
+ attribute \src "libresoc.v:24906.5-24906.29"
switch \initial
- attribute \src "libresoc.v:24715.9-24715.17"
+ attribute \src "libresoc.v:24906.9-24906.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0]
end
- attribute \src "libresoc.v:24724.3-24733.6"
- process $proc$libresoc.v:24724$488
+ attribute \src "libresoc.v:24915.3-24924.6"
+ process $proc$libresoc.v:24915$528
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0]
- attribute \src "libresoc.v:24725.5-24725.29"
+ attribute \src "libresoc.v:24916.5-24916.29"
switch \initial
- attribute \src "libresoc.v:24725.9-24725.17"
+ attribute \src "libresoc.v:24916.9-24916.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0]
end
- attribute \src "libresoc.v:24734.3-24743.6"
- process $proc$libresoc.v:24734$489
+ attribute \src "libresoc.v:24925.3-24934.6"
+ process $proc$libresoc.v:24925$529
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0]
- attribute \src "libresoc.v:24735.5-24735.29"
+ attribute \src "libresoc.v:24926.5-24926.29"
switch \initial
- attribute \src "libresoc.v:24735.9-24735.17"
+ attribute \src "libresoc.v:24926.9-24926.17"
case 1'1
case
end
sync always
update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0]
end
- attribute \src "libresoc.v:24744.3-24753.6"
- process $proc$libresoc.v:24744$490
+ attribute \src "libresoc.v:24935.3-24944.6"
+ process $proc$libresoc.v:24935$530
assign { } { }
assign { } { }
assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0]
- attribute \src "libresoc.v:24745.5-24745.29"
+ attribute \src "libresoc.v:24936.5-24936.29"
switch \initial
- attribute \src "libresoc.v:24745.9-24745.17"
+ attribute \src "libresoc.v:24936.9-24936.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:24759.1-25546.10"
+attribute \src "libresoc.v:24950.1-25737.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub18"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18"
attribute \generator "nMigen"
module \dec31_dec_sub18
- attribute \src "libresoc.v:25127.3-25148.6"
+ attribute \src "libresoc.v:25318.3-25339.6"
wire width 8 $0\dec31_dec_sub18_asmcode[7:0]
- attribute \src "libresoc.v:25215.3-25236.6"
+ attribute \src "libresoc.v:25406.3-25427.6"
wire $0\dec31_dec_sub18_br[0:0]
- attribute \src "libresoc.v:25501.3-25522.6"
+ attribute \src "libresoc.v:25692.3-25713.6"
wire width 3 $0\dec31_dec_sub18_cr_in[2:0]
- attribute \src "libresoc.v:25523.3-25544.6"
+ attribute \src "libresoc.v:25714.3-25735.6"
wire width 3 $0\dec31_dec_sub18_cr_out[2:0]
- attribute \src "libresoc.v:25105.3-25126.6"
+ attribute \src "libresoc.v:25296.3-25317.6"
wire width 2 $0\dec31_dec_sub18_cry_in[1:0]
- attribute \src "libresoc.v:25193.3-25214.6"
+ attribute \src "libresoc.v:25384.3-25405.6"
wire $0\dec31_dec_sub18_cry_out[0:0]
- attribute \src "libresoc.v:25391.3-25412.6"
+ attribute \src "libresoc.v:25582.3-25603.6"
wire width 5 $0\dec31_dec_sub18_form[4:0]
- attribute \src "libresoc.v:25017.3-25038.6"
+ attribute \src "libresoc.v:25208.3-25229.6"
wire width 12 $0\dec31_dec_sub18_function_unit[11:0]
- attribute \src "libresoc.v:25413.3-25434.6"
+ attribute \src "libresoc.v:25604.3-25625.6"
wire width 3 $0\dec31_dec_sub18_in1_sel[2:0]
- attribute \src "libresoc.v:25435.3-25456.6"
+ attribute \src "libresoc.v:25626.3-25647.6"
wire width 4 $0\dec31_dec_sub18_in2_sel[3:0]
- attribute \src "libresoc.v:25457.3-25478.6"
+ attribute \src "libresoc.v:25648.3-25669.6"
wire width 2 $0\dec31_dec_sub18_in3_sel[1:0]
- attribute \src "libresoc.v:25259.3-25280.6"
+ attribute \src "libresoc.v:25450.3-25471.6"
wire width 7 $0\dec31_dec_sub18_internal_op[6:0]
- attribute \src "libresoc.v:25149.3-25170.6"
+ attribute \src "libresoc.v:25340.3-25361.6"
wire $0\dec31_dec_sub18_inv_a[0:0]
- attribute \src "libresoc.v:25171.3-25192.6"
+ attribute \src "libresoc.v:25362.3-25383.6"
wire $0\dec31_dec_sub18_inv_out[0:0]
- attribute \src "libresoc.v:25303.3-25324.6"
+ attribute \src "libresoc.v:25494.3-25515.6"
wire $0\dec31_dec_sub18_is_32b[0:0]
- attribute \src "libresoc.v:25039.3-25060.6"
+ attribute \src "libresoc.v:25230.3-25251.6"
wire width 4 $0\dec31_dec_sub18_ldst_len[3:0]
- attribute \src "libresoc.v:25347.3-25368.6"
+ attribute \src "libresoc.v:25538.3-25559.6"
wire $0\dec31_dec_sub18_lk[0:0]
- attribute \src "libresoc.v:25479.3-25500.6"
+ attribute \src "libresoc.v:25670.3-25691.6"
wire width 2 $0\dec31_dec_sub18_out_sel[1:0]
- attribute \src "libresoc.v:25083.3-25104.6"
+ attribute \src "libresoc.v:25274.3-25295.6"
wire width 2 $0\dec31_dec_sub18_rc_sel[1:0]
- attribute \src "libresoc.v:25281.3-25302.6"
+ attribute \src "libresoc.v:25472.3-25493.6"
wire $0\dec31_dec_sub18_rsrv[0:0]
- attribute \src "libresoc.v:25369.3-25390.6"
+ attribute \src "libresoc.v:25560.3-25581.6"
wire $0\dec31_dec_sub18_sgl_pipe[0:0]
- attribute \src "libresoc.v:25325.3-25346.6"
+ attribute \src "libresoc.v:25516.3-25537.6"
wire $0\dec31_dec_sub18_sgn[0:0]
- attribute \src "libresoc.v:25237.3-25258.6"
+ attribute \src "libresoc.v:25428.3-25449.6"
wire $0\dec31_dec_sub18_sgn_ext[0:0]
- attribute \src "libresoc.v:25061.3-25082.6"
+ attribute \src "libresoc.v:25252.3-25273.6"
wire width 2 $0\dec31_dec_sub18_upd[1:0]
- attribute \src "libresoc.v:24760.7-24760.20"
+ attribute \src "libresoc.v:24951.7-24951.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:25127.3-25148.6"
+ attribute \src "libresoc.v:25318.3-25339.6"
wire width 8 $1\dec31_dec_sub18_asmcode[7:0]
- attribute \src "libresoc.v:25215.3-25236.6"
+ attribute \src "libresoc.v:25406.3-25427.6"
wire $1\dec31_dec_sub18_br[0:0]
- attribute \src "libresoc.v:25501.3-25522.6"
+ attribute \src "libresoc.v:25692.3-25713.6"
wire width 3 $1\dec31_dec_sub18_cr_in[2:0]
- attribute \src "libresoc.v:25523.3-25544.6"
+ attribute \src "libresoc.v:25714.3-25735.6"
wire width 3 $1\dec31_dec_sub18_cr_out[2:0]
- attribute \src "libresoc.v:25105.3-25126.6"
+ attribute \src "libresoc.v:25296.3-25317.6"
wire width 2 $1\dec31_dec_sub18_cry_in[1:0]
- attribute \src "libresoc.v:25193.3-25214.6"
+ attribute \src "libresoc.v:25384.3-25405.6"
wire $1\dec31_dec_sub18_cry_out[0:0]
- attribute \src "libresoc.v:25391.3-25412.6"
+ attribute \src "libresoc.v:25582.3-25603.6"
wire width 5 $1\dec31_dec_sub18_form[4:0]
- attribute \src "libresoc.v:25017.3-25038.6"
+ attribute \src "libresoc.v:25208.3-25229.6"
wire width 12 $1\dec31_dec_sub18_function_unit[11:0]
- attribute \src "libresoc.v:25413.3-25434.6"
+ attribute \src "libresoc.v:25604.3-25625.6"
wire width 3 $1\dec31_dec_sub18_in1_sel[2:0]
- attribute \src "libresoc.v:25435.3-25456.6"
+ attribute \src "libresoc.v:25626.3-25647.6"
wire width 4 $1\dec31_dec_sub18_in2_sel[3:0]
- attribute \src "libresoc.v:25457.3-25478.6"
+ attribute \src "libresoc.v:25648.3-25669.6"
wire width 2 $1\dec31_dec_sub18_in3_sel[1:0]
- attribute \src "libresoc.v:25259.3-25280.6"
+ attribute \src "libresoc.v:25450.3-25471.6"
wire width 7 $1\dec31_dec_sub18_internal_op[6:0]
- attribute \src "libresoc.v:25149.3-25170.6"
+ attribute \src "libresoc.v:25340.3-25361.6"
wire $1\dec31_dec_sub18_inv_a[0:0]
- attribute \src "libresoc.v:25171.3-25192.6"
+ attribute \src "libresoc.v:25362.3-25383.6"
wire $1\dec31_dec_sub18_inv_out[0:0]
- attribute \src "libresoc.v:25303.3-25324.6"
+ attribute \src "libresoc.v:25494.3-25515.6"
wire $1\dec31_dec_sub18_is_32b[0:0]
- attribute \src "libresoc.v:25039.3-25060.6"
+ attribute \src "libresoc.v:25230.3-25251.6"
wire width 4 $1\dec31_dec_sub18_ldst_len[3:0]
- attribute \src "libresoc.v:25347.3-25368.6"
+ attribute \src "libresoc.v:25538.3-25559.6"
wire $1\dec31_dec_sub18_lk[0:0]
- attribute \src "libresoc.v:25479.3-25500.6"
+ attribute \src "libresoc.v:25670.3-25691.6"
wire width 2 $1\dec31_dec_sub18_out_sel[1:0]
- attribute \src "libresoc.v:25083.3-25104.6"
+ attribute \src "libresoc.v:25274.3-25295.6"
wire width 2 $1\dec31_dec_sub18_rc_sel[1:0]
- attribute \src "libresoc.v:25281.3-25302.6"
+ attribute \src "libresoc.v:25472.3-25493.6"
wire $1\dec31_dec_sub18_rsrv[0:0]
- attribute \src "libresoc.v:25369.3-25390.6"
+ attribute \src "libresoc.v:25560.3-25581.6"
wire $1\dec31_dec_sub18_sgl_pipe[0:0]
- attribute \src "libresoc.v:25325.3-25346.6"
+ attribute \src "libresoc.v:25516.3-25537.6"
wire $1\dec31_dec_sub18_sgn[0:0]
- attribute \src "libresoc.v:25237.3-25258.6"
+ attribute \src "libresoc.v:25428.3-25449.6"
wire $1\dec31_dec_sub18_sgn_ext[0:0]
- attribute \src "libresoc.v:25061.3-25082.6"
+ attribute \src "libresoc.v:25252.3-25273.6"
wire width 2 $1\dec31_dec_sub18_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub18_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub18_upd
- attribute \src "libresoc.v:24760.7-24760.15"
+ attribute \src "libresoc.v:24951.7-24951.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:24760.7-24760.20"
- process $proc$libresoc.v:24760$516
+ attribute \src "libresoc.v:24951.7-24951.20"
+ process $proc$libresoc.v:24951$556
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:25017.3-25038.6"
- process $proc$libresoc.v:25017$492
+ attribute \src "libresoc.v:25208.3-25229.6"
+ process $proc$libresoc.v:25208$532
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0]
- attribute \src "libresoc.v:25018.5-25018.29"
+ attribute \src "libresoc.v:25209.5-25209.29"
switch \initial
- attribute \src "libresoc.v:25018.9-25018.17"
+ attribute \src "libresoc.v:25209.9-25209.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0]
end
- attribute \src "libresoc.v:25039.3-25060.6"
- process $proc$libresoc.v:25039$493
+ attribute \src "libresoc.v:25230.3-25251.6"
+ process $proc$libresoc.v:25230$533
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0]
- attribute \src "libresoc.v:25040.5-25040.29"
+ attribute \src "libresoc.v:25231.5-25231.29"
switch \initial
- attribute \src "libresoc.v:25040.9-25040.17"
+ attribute \src "libresoc.v:25231.9-25231.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0]
end
- attribute \src "libresoc.v:25061.3-25082.6"
- process $proc$libresoc.v:25061$494
+ attribute \src "libresoc.v:25252.3-25273.6"
+ process $proc$libresoc.v:25252$534
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0]
- attribute \src "libresoc.v:25062.5-25062.29"
+ attribute \src "libresoc.v:25253.5-25253.29"
switch \initial
- attribute \src "libresoc.v:25062.9-25062.17"
+ attribute \src "libresoc.v:25253.9-25253.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0]
end
- attribute \src "libresoc.v:25083.3-25104.6"
- process $proc$libresoc.v:25083$495
+ attribute \src "libresoc.v:25274.3-25295.6"
+ process $proc$libresoc.v:25274$535
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0]
- attribute \src "libresoc.v:25084.5-25084.29"
+ attribute \src "libresoc.v:25275.5-25275.29"
switch \initial
- attribute \src "libresoc.v:25084.9-25084.17"
+ attribute \src "libresoc.v:25275.9-25275.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0]
end
- attribute \src "libresoc.v:25105.3-25126.6"
- process $proc$libresoc.v:25105$496
+ attribute \src "libresoc.v:25296.3-25317.6"
+ process $proc$libresoc.v:25296$536
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0]
- attribute \src "libresoc.v:25106.5-25106.29"
+ attribute \src "libresoc.v:25297.5-25297.29"
switch \initial
- attribute \src "libresoc.v:25106.9-25106.17"
+ attribute \src "libresoc.v:25297.9-25297.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0]
end
- attribute \src "libresoc.v:25127.3-25148.6"
- process $proc$libresoc.v:25127$497
+ attribute \src "libresoc.v:25318.3-25339.6"
+ process $proc$libresoc.v:25318$537
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0]
- attribute \src "libresoc.v:25128.5-25128.29"
+ attribute \src "libresoc.v:25319.5-25319.29"
switch \initial
- attribute \src "libresoc.v:25128.9-25128.17"
+ attribute \src "libresoc.v:25319.9-25319.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0]
end
- attribute \src "libresoc.v:25149.3-25170.6"
- process $proc$libresoc.v:25149$498
+ attribute \src "libresoc.v:25340.3-25361.6"
+ process $proc$libresoc.v:25340$538
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0]
- attribute \src "libresoc.v:25150.5-25150.29"
+ attribute \src "libresoc.v:25341.5-25341.29"
switch \initial
- attribute \src "libresoc.v:25150.9-25150.17"
+ attribute \src "libresoc.v:25341.9-25341.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0]
end
- attribute \src "libresoc.v:25171.3-25192.6"
- process $proc$libresoc.v:25171$499
+ attribute \src "libresoc.v:25362.3-25383.6"
+ process $proc$libresoc.v:25362$539
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0]
- attribute \src "libresoc.v:25172.5-25172.29"
+ attribute \src "libresoc.v:25363.5-25363.29"
switch \initial
- attribute \src "libresoc.v:25172.9-25172.17"
+ attribute \src "libresoc.v:25363.9-25363.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0]
end
- attribute \src "libresoc.v:25193.3-25214.6"
- process $proc$libresoc.v:25193$500
+ attribute \src "libresoc.v:25384.3-25405.6"
+ process $proc$libresoc.v:25384$540
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0]
- attribute \src "libresoc.v:25194.5-25194.29"
+ attribute \src "libresoc.v:25385.5-25385.29"
switch \initial
- attribute \src "libresoc.v:25194.9-25194.17"
+ attribute \src "libresoc.v:25385.9-25385.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0]
end
- attribute \src "libresoc.v:25215.3-25236.6"
- process $proc$libresoc.v:25215$501
+ attribute \src "libresoc.v:25406.3-25427.6"
+ process $proc$libresoc.v:25406$541
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0]
- attribute \src "libresoc.v:25216.5-25216.29"
+ attribute \src "libresoc.v:25407.5-25407.29"
switch \initial
- attribute \src "libresoc.v:25216.9-25216.17"
+ attribute \src "libresoc.v:25407.9-25407.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0]
end
- attribute \src "libresoc.v:25237.3-25258.6"
- process $proc$libresoc.v:25237$502
+ attribute \src "libresoc.v:25428.3-25449.6"
+ process $proc$libresoc.v:25428$542
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0]
- attribute \src "libresoc.v:25238.5-25238.29"
+ attribute \src "libresoc.v:25429.5-25429.29"
switch \initial
- attribute \src "libresoc.v:25238.9-25238.17"
+ attribute \src "libresoc.v:25429.9-25429.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0]
end
- attribute \src "libresoc.v:25259.3-25280.6"
- process $proc$libresoc.v:25259$503
+ attribute \src "libresoc.v:25450.3-25471.6"
+ process $proc$libresoc.v:25450$543
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0]
- attribute \src "libresoc.v:25260.5-25260.29"
+ attribute \src "libresoc.v:25451.5-25451.29"
switch \initial
- attribute \src "libresoc.v:25260.9-25260.17"
+ attribute \src "libresoc.v:25451.9-25451.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0]
end
- attribute \src "libresoc.v:25281.3-25302.6"
- process $proc$libresoc.v:25281$504
+ attribute \src "libresoc.v:25472.3-25493.6"
+ process $proc$libresoc.v:25472$544
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0]
- attribute \src "libresoc.v:25282.5-25282.29"
+ attribute \src "libresoc.v:25473.5-25473.29"
switch \initial
- attribute \src "libresoc.v:25282.9-25282.17"
+ attribute \src "libresoc.v:25473.9-25473.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0]
end
- attribute \src "libresoc.v:25303.3-25324.6"
- process $proc$libresoc.v:25303$505
+ attribute \src "libresoc.v:25494.3-25515.6"
+ process $proc$libresoc.v:25494$545
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0]
- attribute \src "libresoc.v:25304.5-25304.29"
+ attribute \src "libresoc.v:25495.5-25495.29"
switch \initial
- attribute \src "libresoc.v:25304.9-25304.17"
+ attribute \src "libresoc.v:25495.9-25495.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0]
end
- attribute \src "libresoc.v:25325.3-25346.6"
- process $proc$libresoc.v:25325$506
+ attribute \src "libresoc.v:25516.3-25537.6"
+ process $proc$libresoc.v:25516$546
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0]
- attribute \src "libresoc.v:25326.5-25326.29"
+ attribute \src "libresoc.v:25517.5-25517.29"
switch \initial
- attribute \src "libresoc.v:25326.9-25326.17"
+ attribute \src "libresoc.v:25517.9-25517.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0]
end
- attribute \src "libresoc.v:25347.3-25368.6"
- process $proc$libresoc.v:25347$507
+ attribute \src "libresoc.v:25538.3-25559.6"
+ process $proc$libresoc.v:25538$547
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0]
- attribute \src "libresoc.v:25348.5-25348.29"
+ attribute \src "libresoc.v:25539.5-25539.29"
switch \initial
- attribute \src "libresoc.v:25348.9-25348.17"
+ attribute \src "libresoc.v:25539.9-25539.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0]
end
- attribute \src "libresoc.v:25369.3-25390.6"
- process $proc$libresoc.v:25369$508
+ attribute \src "libresoc.v:25560.3-25581.6"
+ process $proc$libresoc.v:25560$548
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0]
- attribute \src "libresoc.v:25370.5-25370.29"
+ attribute \src "libresoc.v:25561.5-25561.29"
switch \initial
- attribute \src "libresoc.v:25370.9-25370.17"
+ attribute \src "libresoc.v:25561.9-25561.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:25391.3-25412.6"
- process $proc$libresoc.v:25391$509
+ attribute \src "libresoc.v:25582.3-25603.6"
+ process $proc$libresoc.v:25582$549
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0]
- attribute \src "libresoc.v:25392.5-25392.29"
+ attribute \src "libresoc.v:25583.5-25583.29"
switch \initial
- attribute \src "libresoc.v:25392.9-25392.17"
+ attribute \src "libresoc.v:25583.9-25583.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0]
end
- attribute \src "libresoc.v:25413.3-25434.6"
- process $proc$libresoc.v:25413$510
+ attribute \src "libresoc.v:25604.3-25625.6"
+ process $proc$libresoc.v:25604$550
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0]
- attribute \src "libresoc.v:25414.5-25414.29"
+ attribute \src "libresoc.v:25605.5-25605.29"
switch \initial
- attribute \src "libresoc.v:25414.9-25414.17"
+ attribute \src "libresoc.v:25605.9-25605.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0]
end
- attribute \src "libresoc.v:25435.3-25456.6"
- process $proc$libresoc.v:25435$511
+ attribute \src "libresoc.v:25626.3-25647.6"
+ process $proc$libresoc.v:25626$551
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0]
- attribute \src "libresoc.v:25436.5-25436.29"
+ attribute \src "libresoc.v:25627.5-25627.29"
switch \initial
- attribute \src "libresoc.v:25436.9-25436.17"
+ attribute \src "libresoc.v:25627.9-25627.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0]
end
- attribute \src "libresoc.v:25457.3-25478.6"
- process $proc$libresoc.v:25457$512
+ attribute \src "libresoc.v:25648.3-25669.6"
+ process $proc$libresoc.v:25648$552
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0]
- attribute \src "libresoc.v:25458.5-25458.29"
+ attribute \src "libresoc.v:25649.5-25649.29"
switch \initial
- attribute \src "libresoc.v:25458.9-25458.17"
+ attribute \src "libresoc.v:25649.9-25649.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0]
end
- attribute \src "libresoc.v:25479.3-25500.6"
- process $proc$libresoc.v:25479$513
+ attribute \src "libresoc.v:25670.3-25691.6"
+ process $proc$libresoc.v:25670$553
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0]
- attribute \src "libresoc.v:25480.5-25480.29"
+ attribute \src "libresoc.v:25671.5-25671.29"
switch \initial
- attribute \src "libresoc.v:25480.9-25480.17"
+ attribute \src "libresoc.v:25671.9-25671.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0]
end
- attribute \src "libresoc.v:25501.3-25522.6"
- process $proc$libresoc.v:25501$514
+ attribute \src "libresoc.v:25692.3-25713.6"
+ process $proc$libresoc.v:25692$554
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0]
- attribute \src "libresoc.v:25502.5-25502.29"
+ attribute \src "libresoc.v:25693.5-25693.29"
switch \initial
- attribute \src "libresoc.v:25502.9-25502.17"
+ attribute \src "libresoc.v:25693.9-25693.17"
case 1'1
case
end
sync always
update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0]
end
- attribute \src "libresoc.v:25523.3-25544.6"
- process $proc$libresoc.v:25523$515
+ attribute \src "libresoc.v:25714.3-25735.6"
+ process $proc$libresoc.v:25714$555
assign { } { }
assign { } { }
assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0]
- attribute \src "libresoc.v:25524.5-25524.29"
+ attribute \src "libresoc.v:25715.5-25715.29"
switch \initial
- attribute \src "libresoc.v:25524.9-25524.17"
+ attribute \src "libresoc.v:25715.9-25715.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:25550.1-26265.10"
+attribute \src "libresoc.v:25741.1-26456.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub19"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19"
attribute \generator "nMigen"
module \dec31_dec_sub19
- attribute \src "libresoc.v:25903.3-25921.6"
+ attribute \src "libresoc.v:26094.3-26112.6"
wire width 8 $0\dec31_dec_sub19_asmcode[7:0]
- attribute \src "libresoc.v:25979.3-25997.6"
+ attribute \src "libresoc.v:26170.3-26188.6"
wire $0\dec31_dec_sub19_br[0:0]
- attribute \src "libresoc.v:26226.3-26244.6"
+ attribute \src "libresoc.v:26417.3-26435.6"
wire width 3 $0\dec31_dec_sub19_cr_in[2:0]
- attribute \src "libresoc.v:26245.3-26263.6"
+ attribute \src "libresoc.v:26436.3-26454.6"
wire width 3 $0\dec31_dec_sub19_cr_out[2:0]
- attribute \src "libresoc.v:25884.3-25902.6"
+ attribute \src "libresoc.v:26075.3-26093.6"
wire width 2 $0\dec31_dec_sub19_cry_in[1:0]
- attribute \src "libresoc.v:25960.3-25978.6"
+ attribute \src "libresoc.v:26151.3-26169.6"
wire $0\dec31_dec_sub19_cry_out[0:0]
- attribute \src "libresoc.v:26131.3-26149.6"
+ attribute \src "libresoc.v:26322.3-26340.6"
wire width 5 $0\dec31_dec_sub19_form[4:0]
- attribute \src "libresoc.v:25808.3-25826.6"
+ attribute \src "libresoc.v:25999.3-26017.6"
wire width 12 $0\dec31_dec_sub19_function_unit[11:0]
- attribute \src "libresoc.v:26150.3-26168.6"
+ attribute \src "libresoc.v:26341.3-26359.6"
wire width 3 $0\dec31_dec_sub19_in1_sel[2:0]
- attribute \src "libresoc.v:26169.3-26187.6"
+ attribute \src "libresoc.v:26360.3-26378.6"
wire width 4 $0\dec31_dec_sub19_in2_sel[3:0]
- attribute \src "libresoc.v:26188.3-26206.6"
+ attribute \src "libresoc.v:26379.3-26397.6"
wire width 2 $0\dec31_dec_sub19_in3_sel[1:0]
- attribute \src "libresoc.v:26017.3-26035.6"
+ attribute \src "libresoc.v:26208.3-26226.6"
wire width 7 $0\dec31_dec_sub19_internal_op[6:0]
- attribute \src "libresoc.v:25922.3-25940.6"
+ attribute \src "libresoc.v:26113.3-26131.6"
wire $0\dec31_dec_sub19_inv_a[0:0]
- attribute \src "libresoc.v:25941.3-25959.6"
+ attribute \src "libresoc.v:26132.3-26150.6"
wire $0\dec31_dec_sub19_inv_out[0:0]
- attribute \src "libresoc.v:26055.3-26073.6"
+ attribute \src "libresoc.v:26246.3-26264.6"
wire $0\dec31_dec_sub19_is_32b[0:0]
- attribute \src "libresoc.v:25827.3-25845.6"
+ attribute \src "libresoc.v:26018.3-26036.6"
wire width 4 $0\dec31_dec_sub19_ldst_len[3:0]
- attribute \src "libresoc.v:26093.3-26111.6"
+ attribute \src "libresoc.v:26284.3-26302.6"
wire $0\dec31_dec_sub19_lk[0:0]
- attribute \src "libresoc.v:26207.3-26225.6"
+ attribute \src "libresoc.v:26398.3-26416.6"
wire width 2 $0\dec31_dec_sub19_out_sel[1:0]
- attribute \src "libresoc.v:25865.3-25883.6"
+ attribute \src "libresoc.v:26056.3-26074.6"
wire width 2 $0\dec31_dec_sub19_rc_sel[1:0]
- attribute \src "libresoc.v:26036.3-26054.6"
+ attribute \src "libresoc.v:26227.3-26245.6"
wire $0\dec31_dec_sub19_rsrv[0:0]
- attribute \src "libresoc.v:26112.3-26130.6"
+ attribute \src "libresoc.v:26303.3-26321.6"
wire $0\dec31_dec_sub19_sgl_pipe[0:0]
- attribute \src "libresoc.v:26074.3-26092.6"
+ attribute \src "libresoc.v:26265.3-26283.6"
wire $0\dec31_dec_sub19_sgn[0:0]
- attribute \src "libresoc.v:25998.3-26016.6"
+ attribute \src "libresoc.v:26189.3-26207.6"
wire $0\dec31_dec_sub19_sgn_ext[0:0]
- attribute \src "libresoc.v:25846.3-25864.6"
+ attribute \src "libresoc.v:26037.3-26055.6"
wire width 2 $0\dec31_dec_sub19_upd[1:0]
- attribute \src "libresoc.v:25551.7-25551.20"
+ attribute \src "libresoc.v:25742.7-25742.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:25903.3-25921.6"
+ attribute \src "libresoc.v:26094.3-26112.6"
wire width 8 $1\dec31_dec_sub19_asmcode[7:0]
- attribute \src "libresoc.v:25979.3-25997.6"
+ attribute \src "libresoc.v:26170.3-26188.6"
wire $1\dec31_dec_sub19_br[0:0]
- attribute \src "libresoc.v:26226.3-26244.6"
+ attribute \src "libresoc.v:26417.3-26435.6"
wire width 3 $1\dec31_dec_sub19_cr_in[2:0]
- attribute \src "libresoc.v:26245.3-26263.6"
+ attribute \src "libresoc.v:26436.3-26454.6"
wire width 3 $1\dec31_dec_sub19_cr_out[2:0]
- attribute \src "libresoc.v:25884.3-25902.6"
+ attribute \src "libresoc.v:26075.3-26093.6"
wire width 2 $1\dec31_dec_sub19_cry_in[1:0]
- attribute \src "libresoc.v:25960.3-25978.6"
+ attribute \src "libresoc.v:26151.3-26169.6"
wire $1\dec31_dec_sub19_cry_out[0:0]
- attribute \src "libresoc.v:26131.3-26149.6"
+ attribute \src "libresoc.v:26322.3-26340.6"
wire width 5 $1\dec31_dec_sub19_form[4:0]
- attribute \src "libresoc.v:25808.3-25826.6"
+ attribute \src "libresoc.v:25999.3-26017.6"
wire width 12 $1\dec31_dec_sub19_function_unit[11:0]
- attribute \src "libresoc.v:26150.3-26168.6"
+ attribute \src "libresoc.v:26341.3-26359.6"
wire width 3 $1\dec31_dec_sub19_in1_sel[2:0]
- attribute \src "libresoc.v:26169.3-26187.6"
+ attribute \src "libresoc.v:26360.3-26378.6"
wire width 4 $1\dec31_dec_sub19_in2_sel[3:0]
- attribute \src "libresoc.v:26188.3-26206.6"
+ attribute \src "libresoc.v:26379.3-26397.6"
wire width 2 $1\dec31_dec_sub19_in3_sel[1:0]
- attribute \src "libresoc.v:26017.3-26035.6"
+ attribute \src "libresoc.v:26208.3-26226.6"
wire width 7 $1\dec31_dec_sub19_internal_op[6:0]
- attribute \src "libresoc.v:25922.3-25940.6"
+ attribute \src "libresoc.v:26113.3-26131.6"
wire $1\dec31_dec_sub19_inv_a[0:0]
- attribute \src "libresoc.v:25941.3-25959.6"
+ attribute \src "libresoc.v:26132.3-26150.6"
wire $1\dec31_dec_sub19_inv_out[0:0]
- attribute \src "libresoc.v:26055.3-26073.6"
+ attribute \src "libresoc.v:26246.3-26264.6"
wire $1\dec31_dec_sub19_is_32b[0:0]
- attribute \src "libresoc.v:25827.3-25845.6"
+ attribute \src "libresoc.v:26018.3-26036.6"
wire width 4 $1\dec31_dec_sub19_ldst_len[3:0]
- attribute \src "libresoc.v:26093.3-26111.6"
+ attribute \src "libresoc.v:26284.3-26302.6"
wire $1\dec31_dec_sub19_lk[0:0]
- attribute \src "libresoc.v:26207.3-26225.6"
+ attribute \src "libresoc.v:26398.3-26416.6"
wire width 2 $1\dec31_dec_sub19_out_sel[1:0]
- attribute \src "libresoc.v:25865.3-25883.6"
+ attribute \src "libresoc.v:26056.3-26074.6"
wire width 2 $1\dec31_dec_sub19_rc_sel[1:0]
- attribute \src "libresoc.v:26036.3-26054.6"
+ attribute \src "libresoc.v:26227.3-26245.6"
wire $1\dec31_dec_sub19_rsrv[0:0]
- attribute \src "libresoc.v:26112.3-26130.6"
+ attribute \src "libresoc.v:26303.3-26321.6"
wire $1\dec31_dec_sub19_sgl_pipe[0:0]
- attribute \src "libresoc.v:26074.3-26092.6"
+ attribute \src "libresoc.v:26265.3-26283.6"
wire $1\dec31_dec_sub19_sgn[0:0]
- attribute \src "libresoc.v:25998.3-26016.6"
+ attribute \src "libresoc.v:26189.3-26207.6"
wire $1\dec31_dec_sub19_sgn_ext[0:0]
- attribute \src "libresoc.v:25846.3-25864.6"
+ attribute \src "libresoc.v:26037.3-26055.6"
wire width 2 $1\dec31_dec_sub19_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub19_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub19_upd
- attribute \src "libresoc.v:25551.7-25551.15"
+ attribute \src "libresoc.v:25742.7-25742.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:25551.7-25551.20"
- process $proc$libresoc.v:25551$541
+ attribute \src "libresoc.v:25742.7-25742.20"
+ process $proc$libresoc.v:25742$581
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:25808.3-25826.6"
- process $proc$libresoc.v:25808$517
+ attribute \src "libresoc.v:25999.3-26017.6"
+ process $proc$libresoc.v:25999$557
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0]
- attribute \src "libresoc.v:25809.5-25809.29"
+ attribute \src "libresoc.v:26000.5-26000.29"
switch \initial
- attribute \src "libresoc.v:25809.9-25809.17"
+ attribute \src "libresoc.v:26000.9-26000.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0]
end
- attribute \src "libresoc.v:25827.3-25845.6"
- process $proc$libresoc.v:25827$518
+ attribute \src "libresoc.v:26018.3-26036.6"
+ process $proc$libresoc.v:26018$558
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0]
- attribute \src "libresoc.v:25828.5-25828.29"
+ attribute \src "libresoc.v:26019.5-26019.29"
switch \initial
- attribute \src "libresoc.v:25828.9-25828.17"
+ attribute \src "libresoc.v:26019.9-26019.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0]
end
- attribute \src "libresoc.v:25846.3-25864.6"
- process $proc$libresoc.v:25846$519
+ attribute \src "libresoc.v:26037.3-26055.6"
+ process $proc$libresoc.v:26037$559
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0]
- attribute \src "libresoc.v:25847.5-25847.29"
+ attribute \src "libresoc.v:26038.5-26038.29"
switch \initial
- attribute \src "libresoc.v:25847.9-25847.17"
+ attribute \src "libresoc.v:26038.9-26038.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0]
end
- attribute \src "libresoc.v:25865.3-25883.6"
- process $proc$libresoc.v:25865$520
+ attribute \src "libresoc.v:26056.3-26074.6"
+ process $proc$libresoc.v:26056$560
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0]
- attribute \src "libresoc.v:25866.5-25866.29"
+ attribute \src "libresoc.v:26057.5-26057.29"
switch \initial
- attribute \src "libresoc.v:25866.9-25866.17"
+ attribute \src "libresoc.v:26057.9-26057.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0]
end
- attribute \src "libresoc.v:25884.3-25902.6"
- process $proc$libresoc.v:25884$521
+ attribute \src "libresoc.v:26075.3-26093.6"
+ process $proc$libresoc.v:26075$561
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0]
- attribute \src "libresoc.v:25885.5-25885.29"
+ attribute \src "libresoc.v:26076.5-26076.29"
switch \initial
- attribute \src "libresoc.v:25885.9-25885.17"
+ attribute \src "libresoc.v:26076.9-26076.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0]
end
- attribute \src "libresoc.v:25903.3-25921.6"
- process $proc$libresoc.v:25903$522
+ attribute \src "libresoc.v:26094.3-26112.6"
+ process $proc$libresoc.v:26094$562
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0]
- attribute \src "libresoc.v:25904.5-25904.29"
+ attribute \src "libresoc.v:26095.5-26095.29"
switch \initial
- attribute \src "libresoc.v:25904.9-25904.17"
+ attribute \src "libresoc.v:26095.9-26095.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0]
end
- attribute \src "libresoc.v:25922.3-25940.6"
- process $proc$libresoc.v:25922$523
+ attribute \src "libresoc.v:26113.3-26131.6"
+ process $proc$libresoc.v:26113$563
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0]
- attribute \src "libresoc.v:25923.5-25923.29"
+ attribute \src "libresoc.v:26114.5-26114.29"
switch \initial
- attribute \src "libresoc.v:25923.9-25923.17"
+ attribute \src "libresoc.v:26114.9-26114.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0]
end
- attribute \src "libresoc.v:25941.3-25959.6"
- process $proc$libresoc.v:25941$524
+ attribute \src "libresoc.v:26132.3-26150.6"
+ process $proc$libresoc.v:26132$564
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0]
- attribute \src "libresoc.v:25942.5-25942.29"
+ attribute \src "libresoc.v:26133.5-26133.29"
switch \initial
- attribute \src "libresoc.v:25942.9-25942.17"
+ attribute \src "libresoc.v:26133.9-26133.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0]
end
- attribute \src "libresoc.v:25960.3-25978.6"
- process $proc$libresoc.v:25960$525
+ attribute \src "libresoc.v:26151.3-26169.6"
+ process $proc$libresoc.v:26151$565
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0]
- attribute \src "libresoc.v:25961.5-25961.29"
+ attribute \src "libresoc.v:26152.5-26152.29"
switch \initial
- attribute \src "libresoc.v:25961.9-25961.17"
+ attribute \src "libresoc.v:26152.9-26152.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0]
end
- attribute \src "libresoc.v:25979.3-25997.6"
- process $proc$libresoc.v:25979$526
+ attribute \src "libresoc.v:26170.3-26188.6"
+ process $proc$libresoc.v:26170$566
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0]
- attribute \src "libresoc.v:25980.5-25980.29"
+ attribute \src "libresoc.v:26171.5-26171.29"
switch \initial
- attribute \src "libresoc.v:25980.9-25980.17"
+ attribute \src "libresoc.v:26171.9-26171.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0]
end
- attribute \src "libresoc.v:25998.3-26016.6"
- process $proc$libresoc.v:25998$527
+ attribute \src "libresoc.v:26189.3-26207.6"
+ process $proc$libresoc.v:26189$567
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0]
- attribute \src "libresoc.v:25999.5-25999.29"
+ attribute \src "libresoc.v:26190.5-26190.29"
switch \initial
- attribute \src "libresoc.v:25999.9-25999.17"
+ attribute \src "libresoc.v:26190.9-26190.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0]
end
- attribute \src "libresoc.v:26017.3-26035.6"
- process $proc$libresoc.v:26017$528
+ attribute \src "libresoc.v:26208.3-26226.6"
+ process $proc$libresoc.v:26208$568
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0]
- attribute \src "libresoc.v:26018.5-26018.29"
+ attribute \src "libresoc.v:26209.5-26209.29"
switch \initial
- attribute \src "libresoc.v:26018.9-26018.17"
+ attribute \src "libresoc.v:26209.9-26209.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0]
end
- attribute \src "libresoc.v:26036.3-26054.6"
- process $proc$libresoc.v:26036$529
+ attribute \src "libresoc.v:26227.3-26245.6"
+ process $proc$libresoc.v:26227$569
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0]
- attribute \src "libresoc.v:26037.5-26037.29"
+ attribute \src "libresoc.v:26228.5-26228.29"
switch \initial
- attribute \src "libresoc.v:26037.9-26037.17"
+ attribute \src "libresoc.v:26228.9-26228.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0]
end
- attribute \src "libresoc.v:26055.3-26073.6"
- process $proc$libresoc.v:26055$530
+ attribute \src "libresoc.v:26246.3-26264.6"
+ process $proc$libresoc.v:26246$570
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0]
- attribute \src "libresoc.v:26056.5-26056.29"
+ attribute \src "libresoc.v:26247.5-26247.29"
switch \initial
- attribute \src "libresoc.v:26056.9-26056.17"
+ attribute \src "libresoc.v:26247.9-26247.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0]
end
- attribute \src "libresoc.v:26074.3-26092.6"
- process $proc$libresoc.v:26074$531
+ attribute \src "libresoc.v:26265.3-26283.6"
+ process $proc$libresoc.v:26265$571
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0]
- attribute \src "libresoc.v:26075.5-26075.29"
+ attribute \src "libresoc.v:26266.5-26266.29"
switch \initial
- attribute \src "libresoc.v:26075.9-26075.17"
+ attribute \src "libresoc.v:26266.9-26266.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0]
end
- attribute \src "libresoc.v:26093.3-26111.6"
- process $proc$libresoc.v:26093$532
+ attribute \src "libresoc.v:26284.3-26302.6"
+ process $proc$libresoc.v:26284$572
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0]
- attribute \src "libresoc.v:26094.5-26094.29"
+ attribute \src "libresoc.v:26285.5-26285.29"
switch \initial
- attribute \src "libresoc.v:26094.9-26094.17"
+ attribute \src "libresoc.v:26285.9-26285.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0]
end
- attribute \src "libresoc.v:26112.3-26130.6"
- process $proc$libresoc.v:26112$533
+ attribute \src "libresoc.v:26303.3-26321.6"
+ process $proc$libresoc.v:26303$573
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0]
- attribute \src "libresoc.v:26113.5-26113.29"
+ attribute \src "libresoc.v:26304.5-26304.29"
switch \initial
- attribute \src "libresoc.v:26113.9-26113.17"
+ attribute \src "libresoc.v:26304.9-26304.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:26131.3-26149.6"
- process $proc$libresoc.v:26131$534
+ attribute \src "libresoc.v:26322.3-26340.6"
+ process $proc$libresoc.v:26322$574
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0]
- attribute \src "libresoc.v:26132.5-26132.29"
+ attribute \src "libresoc.v:26323.5-26323.29"
switch \initial
- attribute \src "libresoc.v:26132.9-26132.17"
+ attribute \src "libresoc.v:26323.9-26323.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0]
end
- attribute \src "libresoc.v:26150.3-26168.6"
- process $proc$libresoc.v:26150$535
+ attribute \src "libresoc.v:26341.3-26359.6"
+ process $proc$libresoc.v:26341$575
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0]
- attribute \src "libresoc.v:26151.5-26151.29"
+ attribute \src "libresoc.v:26342.5-26342.29"
switch \initial
- attribute \src "libresoc.v:26151.9-26151.17"
+ attribute \src "libresoc.v:26342.9-26342.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0]
end
- attribute \src "libresoc.v:26169.3-26187.6"
- process $proc$libresoc.v:26169$536
+ attribute \src "libresoc.v:26360.3-26378.6"
+ process $proc$libresoc.v:26360$576
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0]
- attribute \src "libresoc.v:26170.5-26170.29"
+ attribute \src "libresoc.v:26361.5-26361.29"
switch \initial
- attribute \src "libresoc.v:26170.9-26170.17"
+ attribute \src "libresoc.v:26361.9-26361.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0]
end
- attribute \src "libresoc.v:26188.3-26206.6"
- process $proc$libresoc.v:26188$537
+ attribute \src "libresoc.v:26379.3-26397.6"
+ process $proc$libresoc.v:26379$577
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0]
- attribute \src "libresoc.v:26189.5-26189.29"
+ attribute \src "libresoc.v:26380.5-26380.29"
switch \initial
- attribute \src "libresoc.v:26189.9-26189.17"
+ attribute \src "libresoc.v:26380.9-26380.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0]
end
- attribute \src "libresoc.v:26207.3-26225.6"
- process $proc$libresoc.v:26207$538
+ attribute \src "libresoc.v:26398.3-26416.6"
+ process $proc$libresoc.v:26398$578
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0]
- attribute \src "libresoc.v:26208.5-26208.29"
+ attribute \src "libresoc.v:26399.5-26399.29"
switch \initial
- attribute \src "libresoc.v:26208.9-26208.17"
+ attribute \src "libresoc.v:26399.9-26399.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0]
end
- attribute \src "libresoc.v:26226.3-26244.6"
- process $proc$libresoc.v:26226$539
+ attribute \src "libresoc.v:26417.3-26435.6"
+ process $proc$libresoc.v:26417$579
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0]
- attribute \src "libresoc.v:26227.5-26227.29"
+ attribute \src "libresoc.v:26418.5-26418.29"
switch \initial
- attribute \src "libresoc.v:26227.9-26227.17"
+ attribute \src "libresoc.v:26418.9-26418.17"
case 1'1
case
end
sync always
update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0]
end
- attribute \src "libresoc.v:26245.3-26263.6"
- process $proc$libresoc.v:26245$540
+ attribute \src "libresoc.v:26436.3-26454.6"
+ process $proc$libresoc.v:26436$580
assign { } { }
assign { } { }
assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0]
- attribute \src "libresoc.v:26246.5-26246.29"
+ attribute \src "libresoc.v:26437.5-26437.29"
switch \initial
- attribute \src "libresoc.v:26246.9-26246.17"
+ attribute \src "libresoc.v:26437.9-26437.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:26269.1-27128.10"
+attribute \src "libresoc.v:26460.1-27319.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub20"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20"
attribute \generator "nMigen"
module \dec31_dec_sub20
- attribute \src "libresoc.v:26652.3-26676.6"
+ attribute \src "libresoc.v:26843.3-26867.6"
wire width 8 $0\dec31_dec_sub20_asmcode[7:0]
- attribute \src "libresoc.v:26752.3-26776.6"
+ attribute \src "libresoc.v:26943.3-26967.6"
wire $0\dec31_dec_sub20_br[0:0]
- attribute \src "libresoc.v:27077.3-27101.6"
+ attribute \src "libresoc.v:27268.3-27292.6"
wire width 3 $0\dec31_dec_sub20_cr_in[2:0]
- attribute \src "libresoc.v:27102.3-27126.6"
+ attribute \src "libresoc.v:27293.3-27317.6"
wire width 3 $0\dec31_dec_sub20_cr_out[2:0]
- attribute \src "libresoc.v:26627.3-26651.6"
+ attribute \src "libresoc.v:26818.3-26842.6"
wire width 2 $0\dec31_dec_sub20_cry_in[1:0]
- attribute \src "libresoc.v:26727.3-26751.6"
+ attribute \src "libresoc.v:26918.3-26942.6"
wire $0\dec31_dec_sub20_cry_out[0:0]
- attribute \src "libresoc.v:26952.3-26976.6"
+ attribute \src "libresoc.v:27143.3-27167.6"
wire width 5 $0\dec31_dec_sub20_form[4:0]
- attribute \src "libresoc.v:26527.3-26551.6"
+ attribute \src "libresoc.v:26718.3-26742.6"
wire width 12 $0\dec31_dec_sub20_function_unit[11:0]
- attribute \src "libresoc.v:26977.3-27001.6"
+ attribute \src "libresoc.v:27168.3-27192.6"
wire width 3 $0\dec31_dec_sub20_in1_sel[2:0]
- attribute \src "libresoc.v:27002.3-27026.6"
+ attribute \src "libresoc.v:27193.3-27217.6"
wire width 4 $0\dec31_dec_sub20_in2_sel[3:0]
- attribute \src "libresoc.v:27027.3-27051.6"
+ attribute \src "libresoc.v:27218.3-27242.6"
wire width 2 $0\dec31_dec_sub20_in3_sel[1:0]
- attribute \src "libresoc.v:26802.3-26826.6"
+ attribute \src "libresoc.v:26993.3-27017.6"
wire width 7 $0\dec31_dec_sub20_internal_op[6:0]
- attribute \src "libresoc.v:26677.3-26701.6"
+ attribute \src "libresoc.v:26868.3-26892.6"
wire $0\dec31_dec_sub20_inv_a[0:0]
- attribute \src "libresoc.v:26702.3-26726.6"
+ attribute \src "libresoc.v:26893.3-26917.6"
wire $0\dec31_dec_sub20_inv_out[0:0]
- attribute \src "libresoc.v:26852.3-26876.6"
+ attribute \src "libresoc.v:27043.3-27067.6"
wire $0\dec31_dec_sub20_is_32b[0:0]
- attribute \src "libresoc.v:26552.3-26576.6"
+ attribute \src "libresoc.v:26743.3-26767.6"
wire width 4 $0\dec31_dec_sub20_ldst_len[3:0]
- attribute \src "libresoc.v:26902.3-26926.6"
+ attribute \src "libresoc.v:27093.3-27117.6"
wire $0\dec31_dec_sub20_lk[0:0]
- attribute \src "libresoc.v:27052.3-27076.6"
+ attribute \src "libresoc.v:27243.3-27267.6"
wire width 2 $0\dec31_dec_sub20_out_sel[1:0]
- attribute \src "libresoc.v:26602.3-26626.6"
+ attribute \src "libresoc.v:26793.3-26817.6"
wire width 2 $0\dec31_dec_sub20_rc_sel[1:0]
- attribute \src "libresoc.v:26827.3-26851.6"
+ attribute \src "libresoc.v:27018.3-27042.6"
wire $0\dec31_dec_sub20_rsrv[0:0]
- attribute \src "libresoc.v:26927.3-26951.6"
+ attribute \src "libresoc.v:27118.3-27142.6"
wire $0\dec31_dec_sub20_sgl_pipe[0:0]
- attribute \src "libresoc.v:26877.3-26901.6"
+ attribute \src "libresoc.v:27068.3-27092.6"
wire $0\dec31_dec_sub20_sgn[0:0]
- attribute \src "libresoc.v:26777.3-26801.6"
+ attribute \src "libresoc.v:26968.3-26992.6"
wire $0\dec31_dec_sub20_sgn_ext[0:0]
- attribute \src "libresoc.v:26577.3-26601.6"
+ attribute \src "libresoc.v:26768.3-26792.6"
wire width 2 $0\dec31_dec_sub20_upd[1:0]
- attribute \src "libresoc.v:26270.7-26270.20"
+ attribute \src "libresoc.v:26461.7-26461.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:26652.3-26676.6"
+ attribute \src "libresoc.v:26843.3-26867.6"
wire width 8 $1\dec31_dec_sub20_asmcode[7:0]
- attribute \src "libresoc.v:26752.3-26776.6"
+ attribute \src "libresoc.v:26943.3-26967.6"
wire $1\dec31_dec_sub20_br[0:0]
- attribute \src "libresoc.v:27077.3-27101.6"
+ attribute \src "libresoc.v:27268.3-27292.6"
wire width 3 $1\dec31_dec_sub20_cr_in[2:0]
- attribute \src "libresoc.v:27102.3-27126.6"
+ attribute \src "libresoc.v:27293.3-27317.6"
wire width 3 $1\dec31_dec_sub20_cr_out[2:0]
- attribute \src "libresoc.v:26627.3-26651.6"
+ attribute \src "libresoc.v:26818.3-26842.6"
wire width 2 $1\dec31_dec_sub20_cry_in[1:0]
- attribute \src "libresoc.v:26727.3-26751.6"
+ attribute \src "libresoc.v:26918.3-26942.6"
wire $1\dec31_dec_sub20_cry_out[0:0]
- attribute \src "libresoc.v:26952.3-26976.6"
+ attribute \src "libresoc.v:27143.3-27167.6"
wire width 5 $1\dec31_dec_sub20_form[4:0]
- attribute \src "libresoc.v:26527.3-26551.6"
+ attribute \src "libresoc.v:26718.3-26742.6"
wire width 12 $1\dec31_dec_sub20_function_unit[11:0]
- attribute \src "libresoc.v:26977.3-27001.6"
+ attribute \src "libresoc.v:27168.3-27192.6"
wire width 3 $1\dec31_dec_sub20_in1_sel[2:0]
- attribute \src "libresoc.v:27002.3-27026.6"
+ attribute \src "libresoc.v:27193.3-27217.6"
wire width 4 $1\dec31_dec_sub20_in2_sel[3:0]
- attribute \src "libresoc.v:27027.3-27051.6"
+ attribute \src "libresoc.v:27218.3-27242.6"
wire width 2 $1\dec31_dec_sub20_in3_sel[1:0]
- attribute \src "libresoc.v:26802.3-26826.6"
+ attribute \src "libresoc.v:26993.3-27017.6"
wire width 7 $1\dec31_dec_sub20_internal_op[6:0]
- attribute \src "libresoc.v:26677.3-26701.6"
+ attribute \src "libresoc.v:26868.3-26892.6"
wire $1\dec31_dec_sub20_inv_a[0:0]
- attribute \src "libresoc.v:26702.3-26726.6"
+ attribute \src "libresoc.v:26893.3-26917.6"
wire $1\dec31_dec_sub20_inv_out[0:0]
- attribute \src "libresoc.v:26852.3-26876.6"
+ attribute \src "libresoc.v:27043.3-27067.6"
wire $1\dec31_dec_sub20_is_32b[0:0]
- attribute \src "libresoc.v:26552.3-26576.6"
+ attribute \src "libresoc.v:26743.3-26767.6"
wire width 4 $1\dec31_dec_sub20_ldst_len[3:0]
- attribute \src "libresoc.v:26902.3-26926.6"
+ attribute \src "libresoc.v:27093.3-27117.6"
wire $1\dec31_dec_sub20_lk[0:0]
- attribute \src "libresoc.v:27052.3-27076.6"
+ attribute \src "libresoc.v:27243.3-27267.6"
wire width 2 $1\dec31_dec_sub20_out_sel[1:0]
- attribute \src "libresoc.v:26602.3-26626.6"
+ attribute \src "libresoc.v:26793.3-26817.6"
wire width 2 $1\dec31_dec_sub20_rc_sel[1:0]
- attribute \src "libresoc.v:26827.3-26851.6"
+ attribute \src "libresoc.v:27018.3-27042.6"
wire $1\dec31_dec_sub20_rsrv[0:0]
- attribute \src "libresoc.v:26927.3-26951.6"
+ attribute \src "libresoc.v:27118.3-27142.6"
wire $1\dec31_dec_sub20_sgl_pipe[0:0]
- attribute \src "libresoc.v:26877.3-26901.6"
+ attribute \src "libresoc.v:27068.3-27092.6"
wire $1\dec31_dec_sub20_sgn[0:0]
- attribute \src "libresoc.v:26777.3-26801.6"
+ attribute \src "libresoc.v:26968.3-26992.6"
wire $1\dec31_dec_sub20_sgn_ext[0:0]
- attribute \src "libresoc.v:26577.3-26601.6"
+ attribute \src "libresoc.v:26768.3-26792.6"
wire width 2 $1\dec31_dec_sub20_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub20_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub20_upd
- attribute \src "libresoc.v:26270.7-26270.15"
+ attribute \src "libresoc.v:26461.7-26461.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:26270.7-26270.20"
- process $proc$libresoc.v:26270$566
+ attribute \src "libresoc.v:26461.7-26461.20"
+ process $proc$libresoc.v:26461$606
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:26527.3-26551.6"
- process $proc$libresoc.v:26527$542
+ attribute \src "libresoc.v:26718.3-26742.6"
+ process $proc$libresoc.v:26718$582
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0]
- attribute \src "libresoc.v:26528.5-26528.29"
+ attribute \src "libresoc.v:26719.5-26719.29"
switch \initial
- attribute \src "libresoc.v:26528.9-26528.17"
+ attribute \src "libresoc.v:26719.9-26719.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0]
end
- attribute \src "libresoc.v:26552.3-26576.6"
- process $proc$libresoc.v:26552$543
+ attribute \src "libresoc.v:26743.3-26767.6"
+ process $proc$libresoc.v:26743$583
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0]
- attribute \src "libresoc.v:26553.5-26553.29"
+ attribute \src "libresoc.v:26744.5-26744.29"
switch \initial
- attribute \src "libresoc.v:26553.9-26553.17"
+ attribute \src "libresoc.v:26744.9-26744.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0]
end
- attribute \src "libresoc.v:26577.3-26601.6"
- process $proc$libresoc.v:26577$544
+ attribute \src "libresoc.v:26768.3-26792.6"
+ process $proc$libresoc.v:26768$584
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0]
- attribute \src "libresoc.v:26578.5-26578.29"
+ attribute \src "libresoc.v:26769.5-26769.29"
switch \initial
- attribute \src "libresoc.v:26578.9-26578.17"
+ attribute \src "libresoc.v:26769.9-26769.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0]
end
- attribute \src "libresoc.v:26602.3-26626.6"
- process $proc$libresoc.v:26602$545
+ attribute \src "libresoc.v:26793.3-26817.6"
+ process $proc$libresoc.v:26793$585
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0]
- attribute \src "libresoc.v:26603.5-26603.29"
+ attribute \src "libresoc.v:26794.5-26794.29"
switch \initial
- attribute \src "libresoc.v:26603.9-26603.17"
+ attribute \src "libresoc.v:26794.9-26794.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0]
end
- attribute \src "libresoc.v:26627.3-26651.6"
- process $proc$libresoc.v:26627$546
+ attribute \src "libresoc.v:26818.3-26842.6"
+ process $proc$libresoc.v:26818$586
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0]
- attribute \src "libresoc.v:26628.5-26628.29"
+ attribute \src "libresoc.v:26819.5-26819.29"
switch \initial
- attribute \src "libresoc.v:26628.9-26628.17"
+ attribute \src "libresoc.v:26819.9-26819.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0]
end
- attribute \src "libresoc.v:26652.3-26676.6"
- process $proc$libresoc.v:26652$547
+ attribute \src "libresoc.v:26843.3-26867.6"
+ process $proc$libresoc.v:26843$587
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0]
- attribute \src "libresoc.v:26653.5-26653.29"
+ attribute \src "libresoc.v:26844.5-26844.29"
switch \initial
- attribute \src "libresoc.v:26653.9-26653.17"
+ attribute \src "libresoc.v:26844.9-26844.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0]
end
- attribute \src "libresoc.v:26677.3-26701.6"
- process $proc$libresoc.v:26677$548
+ attribute \src "libresoc.v:26868.3-26892.6"
+ process $proc$libresoc.v:26868$588
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0]
- attribute \src "libresoc.v:26678.5-26678.29"
+ attribute \src "libresoc.v:26869.5-26869.29"
switch \initial
- attribute \src "libresoc.v:26678.9-26678.17"
+ attribute \src "libresoc.v:26869.9-26869.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0]
end
- attribute \src "libresoc.v:26702.3-26726.6"
- process $proc$libresoc.v:26702$549
+ attribute \src "libresoc.v:26893.3-26917.6"
+ process $proc$libresoc.v:26893$589
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0]
- attribute \src "libresoc.v:26703.5-26703.29"
+ attribute \src "libresoc.v:26894.5-26894.29"
switch \initial
- attribute \src "libresoc.v:26703.9-26703.17"
+ attribute \src "libresoc.v:26894.9-26894.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0]
end
- attribute \src "libresoc.v:26727.3-26751.6"
- process $proc$libresoc.v:26727$550
+ attribute \src "libresoc.v:26918.3-26942.6"
+ process $proc$libresoc.v:26918$590
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0]
- attribute \src "libresoc.v:26728.5-26728.29"
+ attribute \src "libresoc.v:26919.5-26919.29"
switch \initial
- attribute \src "libresoc.v:26728.9-26728.17"
+ attribute \src "libresoc.v:26919.9-26919.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0]
end
- attribute \src "libresoc.v:26752.3-26776.6"
- process $proc$libresoc.v:26752$551
+ attribute \src "libresoc.v:26943.3-26967.6"
+ process $proc$libresoc.v:26943$591
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0]
- attribute \src "libresoc.v:26753.5-26753.29"
+ attribute \src "libresoc.v:26944.5-26944.29"
switch \initial
- attribute \src "libresoc.v:26753.9-26753.17"
+ attribute \src "libresoc.v:26944.9-26944.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0]
end
- attribute \src "libresoc.v:26777.3-26801.6"
- process $proc$libresoc.v:26777$552
+ attribute \src "libresoc.v:26968.3-26992.6"
+ process $proc$libresoc.v:26968$592
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0]
- attribute \src "libresoc.v:26778.5-26778.29"
+ attribute \src "libresoc.v:26969.5-26969.29"
switch \initial
- attribute \src "libresoc.v:26778.9-26778.17"
+ attribute \src "libresoc.v:26969.9-26969.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0]
end
- attribute \src "libresoc.v:26802.3-26826.6"
- process $proc$libresoc.v:26802$553
+ attribute \src "libresoc.v:26993.3-27017.6"
+ process $proc$libresoc.v:26993$593
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0]
- attribute \src "libresoc.v:26803.5-26803.29"
+ attribute \src "libresoc.v:26994.5-26994.29"
switch \initial
- attribute \src "libresoc.v:26803.9-26803.17"
+ attribute \src "libresoc.v:26994.9-26994.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0]
end
- attribute \src "libresoc.v:26827.3-26851.6"
- process $proc$libresoc.v:26827$554
+ attribute \src "libresoc.v:27018.3-27042.6"
+ process $proc$libresoc.v:27018$594
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0]
- attribute \src "libresoc.v:26828.5-26828.29"
+ attribute \src "libresoc.v:27019.5-27019.29"
switch \initial
- attribute \src "libresoc.v:26828.9-26828.17"
+ attribute \src "libresoc.v:27019.9-27019.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0]
end
- attribute \src "libresoc.v:26852.3-26876.6"
- process $proc$libresoc.v:26852$555
+ attribute \src "libresoc.v:27043.3-27067.6"
+ process $proc$libresoc.v:27043$595
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0]
- attribute \src "libresoc.v:26853.5-26853.29"
+ attribute \src "libresoc.v:27044.5-27044.29"
switch \initial
- attribute \src "libresoc.v:26853.9-26853.17"
+ attribute \src "libresoc.v:27044.9-27044.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0]
end
- attribute \src "libresoc.v:26877.3-26901.6"
- process $proc$libresoc.v:26877$556
+ attribute \src "libresoc.v:27068.3-27092.6"
+ process $proc$libresoc.v:27068$596
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0]
- attribute \src "libresoc.v:26878.5-26878.29"
+ attribute \src "libresoc.v:27069.5-27069.29"
switch \initial
- attribute \src "libresoc.v:26878.9-26878.17"
+ attribute \src "libresoc.v:27069.9-27069.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0]
end
- attribute \src "libresoc.v:26902.3-26926.6"
- process $proc$libresoc.v:26902$557
+ attribute \src "libresoc.v:27093.3-27117.6"
+ process $proc$libresoc.v:27093$597
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0]
- attribute \src "libresoc.v:26903.5-26903.29"
+ attribute \src "libresoc.v:27094.5-27094.29"
switch \initial
- attribute \src "libresoc.v:26903.9-26903.17"
+ attribute \src "libresoc.v:27094.9-27094.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0]
end
- attribute \src "libresoc.v:26927.3-26951.6"
- process $proc$libresoc.v:26927$558
+ attribute \src "libresoc.v:27118.3-27142.6"
+ process $proc$libresoc.v:27118$598
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0]
- attribute \src "libresoc.v:26928.5-26928.29"
+ attribute \src "libresoc.v:27119.5-27119.29"
switch \initial
- attribute \src "libresoc.v:26928.9-26928.17"
+ attribute \src "libresoc.v:27119.9-27119.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:26952.3-26976.6"
- process $proc$libresoc.v:26952$559
+ attribute \src "libresoc.v:27143.3-27167.6"
+ process $proc$libresoc.v:27143$599
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0]
- attribute \src "libresoc.v:26953.5-26953.29"
+ attribute \src "libresoc.v:27144.5-27144.29"
switch \initial
- attribute \src "libresoc.v:26953.9-26953.17"
+ attribute \src "libresoc.v:27144.9-27144.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0]
end
- attribute \src "libresoc.v:26977.3-27001.6"
- process $proc$libresoc.v:26977$560
+ attribute \src "libresoc.v:27168.3-27192.6"
+ process $proc$libresoc.v:27168$600
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0]
- attribute \src "libresoc.v:26978.5-26978.29"
+ attribute \src "libresoc.v:27169.5-27169.29"
switch \initial
- attribute \src "libresoc.v:26978.9-26978.17"
+ attribute \src "libresoc.v:27169.9-27169.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0]
end
- attribute \src "libresoc.v:27002.3-27026.6"
- process $proc$libresoc.v:27002$561
+ attribute \src "libresoc.v:27193.3-27217.6"
+ process $proc$libresoc.v:27193$601
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0]
- attribute \src "libresoc.v:27003.5-27003.29"
+ attribute \src "libresoc.v:27194.5-27194.29"
switch \initial
- attribute \src "libresoc.v:27003.9-27003.17"
+ attribute \src "libresoc.v:27194.9-27194.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0]
end
- attribute \src "libresoc.v:27027.3-27051.6"
- process $proc$libresoc.v:27027$562
+ attribute \src "libresoc.v:27218.3-27242.6"
+ process $proc$libresoc.v:27218$602
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0]
- attribute \src "libresoc.v:27028.5-27028.29"
+ attribute \src "libresoc.v:27219.5-27219.29"
switch \initial
- attribute \src "libresoc.v:27028.9-27028.17"
+ attribute \src "libresoc.v:27219.9-27219.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0]
end
- attribute \src "libresoc.v:27052.3-27076.6"
- process $proc$libresoc.v:27052$563
+ attribute \src "libresoc.v:27243.3-27267.6"
+ process $proc$libresoc.v:27243$603
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0]
- attribute \src "libresoc.v:27053.5-27053.29"
+ attribute \src "libresoc.v:27244.5-27244.29"
switch \initial
- attribute \src "libresoc.v:27053.9-27053.17"
+ attribute \src "libresoc.v:27244.9-27244.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0]
end
- attribute \src "libresoc.v:27077.3-27101.6"
- process $proc$libresoc.v:27077$564
+ attribute \src "libresoc.v:27268.3-27292.6"
+ process $proc$libresoc.v:27268$604
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0]
- attribute \src "libresoc.v:27078.5-27078.29"
+ attribute \src "libresoc.v:27269.5-27269.29"
switch \initial
- attribute \src "libresoc.v:27078.9-27078.17"
+ attribute \src "libresoc.v:27269.9-27269.17"
case 1'1
case
end
sync always
update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0]
end
- attribute \src "libresoc.v:27102.3-27126.6"
- process $proc$libresoc.v:27102$565
+ attribute \src "libresoc.v:27293.3-27317.6"
+ process $proc$libresoc.v:27293$605
assign { } { }
assign { } { }
assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0]
- attribute \src "libresoc.v:27103.5-27103.29"
+ attribute \src "libresoc.v:27294.5-27294.29"
switch \initial
- attribute \src "libresoc.v:27103.9-27103.17"
+ attribute \src "libresoc.v:27294.9-27294.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:27132.1-28549.10"
+attribute \src "libresoc.v:27323.1-28740.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub21"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21"
attribute \generator "nMigen"
module \dec31_dec_sub21
- attribute \src "libresoc.v:28174.3-28204.6"
+ attribute \src "libresoc.v:28365.3-28395.6"
wire width 8 $0\dec31_dec_sub21_asmcode[7:0]
- attribute \src "libresoc.v:27782.3-27830.6"
+ attribute \src "libresoc.v:27973.3-28021.6"
wire $0\dec31_dec_sub21_br[0:0]
- attribute \src "libresoc.v:28450.3-28498.6"
+ attribute \src "libresoc.v:28641.3-28689.6"
wire width 3 $0\dec31_dec_sub21_cr_in[2:0]
- attribute \src "libresoc.v:28499.3-28547.6"
+ attribute \src "libresoc.v:28690.3-28738.6"
wire width 3 $0\dec31_dec_sub21_cr_out[2:0]
- attribute \src "libresoc.v:27586.3-27634.6"
+ attribute \src "libresoc.v:27777.3-27825.6"
wire width 2 $0\dec31_dec_sub21_cry_in[1:0]
- attribute \src "libresoc.v:27733.3-27781.6"
+ attribute \src "libresoc.v:27924.3-27972.6"
wire $0\dec31_dec_sub21_cry_out[0:0]
- attribute \src "libresoc.v:28205.3-28253.6"
+ attribute \src "libresoc.v:28396.3-28444.6"
wire width 5 $0\dec31_dec_sub21_form[4:0]
- attribute \src "libresoc.v:27390.3-27438.6"
+ attribute \src "libresoc.v:27581.3-27629.6"
wire width 12 $0\dec31_dec_sub21_function_unit[11:0]
- attribute \src "libresoc.v:28254.3-28302.6"
+ attribute \src "libresoc.v:28445.3-28493.6"
wire width 3 $0\dec31_dec_sub21_in1_sel[2:0]
- attribute \src "libresoc.v:28303.3-28351.6"
+ attribute \src "libresoc.v:28494.3-28542.6"
wire width 4 $0\dec31_dec_sub21_in2_sel[3:0]
- attribute \src "libresoc.v:28352.3-28400.6"
+ attribute \src "libresoc.v:28543.3-28591.6"
wire width 2 $0\dec31_dec_sub21_in3_sel[1:0]
- attribute \src "libresoc.v:27929.3-27977.6"
+ attribute \src "libresoc.v:28120.3-28168.6"
wire width 7 $0\dec31_dec_sub21_internal_op[6:0]
- attribute \src "libresoc.v:27635.3-27683.6"
+ attribute \src "libresoc.v:27826.3-27874.6"
wire $0\dec31_dec_sub21_inv_a[0:0]
- attribute \src "libresoc.v:27684.3-27732.6"
+ attribute \src "libresoc.v:27875.3-27923.6"
wire $0\dec31_dec_sub21_inv_out[0:0]
- attribute \src "libresoc.v:27978.3-28026.6"
+ attribute \src "libresoc.v:28169.3-28217.6"
wire $0\dec31_dec_sub21_is_32b[0:0]
- attribute \src "libresoc.v:27439.3-27487.6"
+ attribute \src "libresoc.v:27630.3-27678.6"
wire width 4 $0\dec31_dec_sub21_ldst_len[3:0]
- attribute \src "libresoc.v:28076.3-28124.6"
+ attribute \src "libresoc.v:28267.3-28315.6"
wire $0\dec31_dec_sub21_lk[0:0]
- attribute \src "libresoc.v:28401.3-28449.6"
+ attribute \src "libresoc.v:28592.3-28640.6"
wire width 2 $0\dec31_dec_sub21_out_sel[1:0]
- attribute \src "libresoc.v:27537.3-27585.6"
+ attribute \src "libresoc.v:27728.3-27776.6"
wire width 2 $0\dec31_dec_sub21_rc_sel[1:0]
- attribute \src "libresoc.v:27880.3-27928.6"
+ attribute \src "libresoc.v:28071.3-28119.6"
wire $0\dec31_dec_sub21_rsrv[0:0]
- attribute \src "libresoc.v:28125.3-28173.6"
+ attribute \src "libresoc.v:28316.3-28364.6"
wire $0\dec31_dec_sub21_sgl_pipe[0:0]
- attribute \src "libresoc.v:28027.3-28075.6"
+ attribute \src "libresoc.v:28218.3-28266.6"
wire $0\dec31_dec_sub21_sgn[0:0]
- attribute \src "libresoc.v:27831.3-27879.6"
+ attribute \src "libresoc.v:28022.3-28070.6"
wire $0\dec31_dec_sub21_sgn_ext[0:0]
- attribute \src "libresoc.v:27488.3-27536.6"
+ attribute \src "libresoc.v:27679.3-27727.6"
wire width 2 $0\dec31_dec_sub21_upd[1:0]
- attribute \src "libresoc.v:27133.7-27133.20"
+ attribute \src "libresoc.v:27324.7-27324.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:28174.3-28204.6"
+ attribute \src "libresoc.v:28365.3-28395.6"
wire width 8 $1\dec31_dec_sub21_asmcode[7:0]
- attribute \src "libresoc.v:27782.3-27830.6"
+ attribute \src "libresoc.v:27973.3-28021.6"
wire $1\dec31_dec_sub21_br[0:0]
- attribute \src "libresoc.v:28450.3-28498.6"
+ attribute \src "libresoc.v:28641.3-28689.6"
wire width 3 $1\dec31_dec_sub21_cr_in[2:0]
- attribute \src "libresoc.v:28499.3-28547.6"
+ attribute \src "libresoc.v:28690.3-28738.6"
wire width 3 $1\dec31_dec_sub21_cr_out[2:0]
- attribute \src "libresoc.v:27586.3-27634.6"
+ attribute \src "libresoc.v:27777.3-27825.6"
wire width 2 $1\dec31_dec_sub21_cry_in[1:0]
- attribute \src "libresoc.v:27733.3-27781.6"
+ attribute \src "libresoc.v:27924.3-27972.6"
wire $1\dec31_dec_sub21_cry_out[0:0]
- attribute \src "libresoc.v:28205.3-28253.6"
+ attribute \src "libresoc.v:28396.3-28444.6"
wire width 5 $1\dec31_dec_sub21_form[4:0]
- attribute \src "libresoc.v:27390.3-27438.6"
+ attribute \src "libresoc.v:27581.3-27629.6"
wire width 12 $1\dec31_dec_sub21_function_unit[11:0]
- attribute \src "libresoc.v:28254.3-28302.6"
+ attribute \src "libresoc.v:28445.3-28493.6"
wire width 3 $1\dec31_dec_sub21_in1_sel[2:0]
- attribute \src "libresoc.v:28303.3-28351.6"
+ attribute \src "libresoc.v:28494.3-28542.6"
wire width 4 $1\dec31_dec_sub21_in2_sel[3:0]
- attribute \src "libresoc.v:28352.3-28400.6"
+ attribute \src "libresoc.v:28543.3-28591.6"
wire width 2 $1\dec31_dec_sub21_in3_sel[1:0]
- attribute \src "libresoc.v:27929.3-27977.6"
+ attribute \src "libresoc.v:28120.3-28168.6"
wire width 7 $1\dec31_dec_sub21_internal_op[6:0]
- attribute \src "libresoc.v:27635.3-27683.6"
+ attribute \src "libresoc.v:27826.3-27874.6"
wire $1\dec31_dec_sub21_inv_a[0:0]
- attribute \src "libresoc.v:27684.3-27732.6"
+ attribute \src "libresoc.v:27875.3-27923.6"
wire $1\dec31_dec_sub21_inv_out[0:0]
- attribute \src "libresoc.v:27978.3-28026.6"
+ attribute \src "libresoc.v:28169.3-28217.6"
wire $1\dec31_dec_sub21_is_32b[0:0]
- attribute \src "libresoc.v:27439.3-27487.6"
+ attribute \src "libresoc.v:27630.3-27678.6"
wire width 4 $1\dec31_dec_sub21_ldst_len[3:0]
- attribute \src "libresoc.v:28076.3-28124.6"
+ attribute \src "libresoc.v:28267.3-28315.6"
wire $1\dec31_dec_sub21_lk[0:0]
- attribute \src "libresoc.v:28401.3-28449.6"
+ attribute \src "libresoc.v:28592.3-28640.6"
wire width 2 $1\dec31_dec_sub21_out_sel[1:0]
- attribute \src "libresoc.v:27537.3-27585.6"
+ attribute \src "libresoc.v:27728.3-27776.6"
wire width 2 $1\dec31_dec_sub21_rc_sel[1:0]
- attribute \src "libresoc.v:27880.3-27928.6"
+ attribute \src "libresoc.v:28071.3-28119.6"
wire $1\dec31_dec_sub21_rsrv[0:0]
- attribute \src "libresoc.v:28125.3-28173.6"
+ attribute \src "libresoc.v:28316.3-28364.6"
wire $1\dec31_dec_sub21_sgl_pipe[0:0]
- attribute \src "libresoc.v:28027.3-28075.6"
+ attribute \src "libresoc.v:28218.3-28266.6"
wire $1\dec31_dec_sub21_sgn[0:0]
- attribute \src "libresoc.v:27831.3-27879.6"
+ attribute \src "libresoc.v:28022.3-28070.6"
wire $1\dec31_dec_sub21_sgn_ext[0:0]
- attribute \src "libresoc.v:27488.3-27536.6"
+ attribute \src "libresoc.v:27679.3-27727.6"
wire width 2 $1\dec31_dec_sub21_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub21_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub21_upd
- attribute \src "libresoc.v:27133.7-27133.15"
+ attribute \src "libresoc.v:27324.7-27324.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:27133.7-27133.20"
- process $proc$libresoc.v:27133$591
+ attribute \src "libresoc.v:27324.7-27324.20"
+ process $proc$libresoc.v:27324$631
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:27390.3-27438.6"
- process $proc$libresoc.v:27390$567
+ attribute \src "libresoc.v:27581.3-27629.6"
+ process $proc$libresoc.v:27581$607
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0]
- attribute \src "libresoc.v:27391.5-27391.29"
+ attribute \src "libresoc.v:27582.5-27582.29"
switch \initial
- attribute \src "libresoc.v:27391.9-27391.17"
+ attribute \src "libresoc.v:27582.9-27582.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0]
end
- attribute \src "libresoc.v:27439.3-27487.6"
- process $proc$libresoc.v:27439$568
+ attribute \src "libresoc.v:27630.3-27678.6"
+ process $proc$libresoc.v:27630$608
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0]
- attribute \src "libresoc.v:27440.5-27440.29"
+ attribute \src "libresoc.v:27631.5-27631.29"
switch \initial
- attribute \src "libresoc.v:27440.9-27440.17"
+ attribute \src "libresoc.v:27631.9-27631.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0]
end
- attribute \src "libresoc.v:27488.3-27536.6"
- process $proc$libresoc.v:27488$569
+ attribute \src "libresoc.v:27679.3-27727.6"
+ process $proc$libresoc.v:27679$609
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0]
- attribute \src "libresoc.v:27489.5-27489.29"
+ attribute \src "libresoc.v:27680.5-27680.29"
switch \initial
- attribute \src "libresoc.v:27489.9-27489.17"
+ attribute \src "libresoc.v:27680.9-27680.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0]
end
- attribute \src "libresoc.v:27537.3-27585.6"
- process $proc$libresoc.v:27537$570
+ attribute \src "libresoc.v:27728.3-27776.6"
+ process $proc$libresoc.v:27728$610
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0]
- attribute \src "libresoc.v:27538.5-27538.29"
+ attribute \src "libresoc.v:27729.5-27729.29"
switch \initial
- attribute \src "libresoc.v:27538.9-27538.17"
+ attribute \src "libresoc.v:27729.9-27729.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0]
end
- attribute \src "libresoc.v:27586.3-27634.6"
- process $proc$libresoc.v:27586$571
+ attribute \src "libresoc.v:27777.3-27825.6"
+ process $proc$libresoc.v:27777$611
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0]
- attribute \src "libresoc.v:27587.5-27587.29"
+ attribute \src "libresoc.v:27778.5-27778.29"
switch \initial
- attribute \src "libresoc.v:27587.9-27587.17"
+ attribute \src "libresoc.v:27778.9-27778.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0]
end
- attribute \src "libresoc.v:27635.3-27683.6"
- process $proc$libresoc.v:27635$572
+ attribute \src "libresoc.v:27826.3-27874.6"
+ process $proc$libresoc.v:27826$612
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0]
- attribute \src "libresoc.v:27636.5-27636.29"
+ attribute \src "libresoc.v:27827.5-27827.29"
switch \initial
- attribute \src "libresoc.v:27636.9-27636.17"
+ attribute \src "libresoc.v:27827.9-27827.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0]
end
- attribute \src "libresoc.v:27684.3-27732.6"
- process $proc$libresoc.v:27684$573
+ attribute \src "libresoc.v:27875.3-27923.6"
+ process $proc$libresoc.v:27875$613
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0]
- attribute \src "libresoc.v:27685.5-27685.29"
+ attribute \src "libresoc.v:27876.5-27876.29"
switch \initial
- attribute \src "libresoc.v:27685.9-27685.17"
+ attribute \src "libresoc.v:27876.9-27876.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0]
end
- attribute \src "libresoc.v:27733.3-27781.6"
- process $proc$libresoc.v:27733$574
+ attribute \src "libresoc.v:27924.3-27972.6"
+ process $proc$libresoc.v:27924$614
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0]
- attribute \src "libresoc.v:27734.5-27734.29"
+ attribute \src "libresoc.v:27925.5-27925.29"
switch \initial
- attribute \src "libresoc.v:27734.9-27734.17"
+ attribute \src "libresoc.v:27925.9-27925.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0]
end
- attribute \src "libresoc.v:27782.3-27830.6"
- process $proc$libresoc.v:27782$575
+ attribute \src "libresoc.v:27973.3-28021.6"
+ process $proc$libresoc.v:27973$615
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0]
- attribute \src "libresoc.v:27783.5-27783.29"
+ attribute \src "libresoc.v:27974.5-27974.29"
switch \initial
- attribute \src "libresoc.v:27783.9-27783.17"
+ attribute \src "libresoc.v:27974.9-27974.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0]
end
- attribute \src "libresoc.v:27831.3-27879.6"
- process $proc$libresoc.v:27831$576
+ attribute \src "libresoc.v:28022.3-28070.6"
+ process $proc$libresoc.v:28022$616
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0]
- attribute \src "libresoc.v:27832.5-27832.29"
+ attribute \src "libresoc.v:28023.5-28023.29"
switch \initial
- attribute \src "libresoc.v:27832.9-27832.17"
+ attribute \src "libresoc.v:28023.9-28023.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0]
end
- attribute \src "libresoc.v:27880.3-27928.6"
- process $proc$libresoc.v:27880$577
+ attribute \src "libresoc.v:28071.3-28119.6"
+ process $proc$libresoc.v:28071$617
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0]
- attribute \src "libresoc.v:27881.5-27881.29"
+ attribute \src "libresoc.v:28072.5-28072.29"
switch \initial
- attribute \src "libresoc.v:27881.9-27881.17"
+ attribute \src "libresoc.v:28072.9-28072.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0]
end
- attribute \src "libresoc.v:27929.3-27977.6"
- process $proc$libresoc.v:27929$578
+ attribute \src "libresoc.v:28120.3-28168.6"
+ process $proc$libresoc.v:28120$618
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0]
- attribute \src "libresoc.v:27930.5-27930.29"
+ attribute \src "libresoc.v:28121.5-28121.29"
switch \initial
- attribute \src "libresoc.v:27930.9-27930.17"
+ attribute \src "libresoc.v:28121.9-28121.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0]
end
- attribute \src "libresoc.v:27978.3-28026.6"
- process $proc$libresoc.v:27978$579
+ attribute \src "libresoc.v:28169.3-28217.6"
+ process $proc$libresoc.v:28169$619
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0]
- attribute \src "libresoc.v:27979.5-27979.29"
+ attribute \src "libresoc.v:28170.5-28170.29"
switch \initial
- attribute \src "libresoc.v:27979.9-27979.17"
+ attribute \src "libresoc.v:28170.9-28170.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0]
end
- attribute \src "libresoc.v:28027.3-28075.6"
- process $proc$libresoc.v:28027$580
+ attribute \src "libresoc.v:28218.3-28266.6"
+ process $proc$libresoc.v:28218$620
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0]
- attribute \src "libresoc.v:28028.5-28028.29"
+ attribute \src "libresoc.v:28219.5-28219.29"
switch \initial
- attribute \src "libresoc.v:28028.9-28028.17"
+ attribute \src "libresoc.v:28219.9-28219.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0]
end
- attribute \src "libresoc.v:28076.3-28124.6"
- process $proc$libresoc.v:28076$581
+ attribute \src "libresoc.v:28267.3-28315.6"
+ process $proc$libresoc.v:28267$621
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0]
- attribute \src "libresoc.v:28077.5-28077.29"
+ attribute \src "libresoc.v:28268.5-28268.29"
switch \initial
- attribute \src "libresoc.v:28077.9-28077.17"
+ attribute \src "libresoc.v:28268.9-28268.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0]
end
- attribute \src "libresoc.v:28125.3-28173.6"
- process $proc$libresoc.v:28125$582
+ attribute \src "libresoc.v:28316.3-28364.6"
+ process $proc$libresoc.v:28316$622
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0]
- attribute \src "libresoc.v:28126.5-28126.29"
+ attribute \src "libresoc.v:28317.5-28317.29"
switch \initial
- attribute \src "libresoc.v:28126.9-28126.17"
+ attribute \src "libresoc.v:28317.9-28317.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:28174.3-28204.6"
- process $proc$libresoc.v:28174$583
+ attribute \src "libresoc.v:28365.3-28395.6"
+ process $proc$libresoc.v:28365$623
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0]
- attribute \src "libresoc.v:28175.5-28175.29"
+ attribute \src "libresoc.v:28366.5-28366.29"
switch \initial
- attribute \src "libresoc.v:28175.9-28175.17"
+ attribute \src "libresoc.v:28366.9-28366.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0]
end
- attribute \src "libresoc.v:28205.3-28253.6"
- process $proc$libresoc.v:28205$584
+ attribute \src "libresoc.v:28396.3-28444.6"
+ process $proc$libresoc.v:28396$624
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0]
- attribute \src "libresoc.v:28206.5-28206.29"
+ attribute \src "libresoc.v:28397.5-28397.29"
switch \initial
- attribute \src "libresoc.v:28206.9-28206.17"
+ attribute \src "libresoc.v:28397.9-28397.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0]
end
- attribute \src "libresoc.v:28254.3-28302.6"
- process $proc$libresoc.v:28254$585
+ attribute \src "libresoc.v:28445.3-28493.6"
+ process $proc$libresoc.v:28445$625
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0]
- attribute \src "libresoc.v:28255.5-28255.29"
+ attribute \src "libresoc.v:28446.5-28446.29"
switch \initial
- attribute \src "libresoc.v:28255.9-28255.17"
+ attribute \src "libresoc.v:28446.9-28446.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0]
end
- attribute \src "libresoc.v:28303.3-28351.6"
- process $proc$libresoc.v:28303$586
+ attribute \src "libresoc.v:28494.3-28542.6"
+ process $proc$libresoc.v:28494$626
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0]
- attribute \src "libresoc.v:28304.5-28304.29"
+ attribute \src "libresoc.v:28495.5-28495.29"
switch \initial
- attribute \src "libresoc.v:28304.9-28304.17"
+ attribute \src "libresoc.v:28495.9-28495.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0]
end
- attribute \src "libresoc.v:28352.3-28400.6"
- process $proc$libresoc.v:28352$587
+ attribute \src "libresoc.v:28543.3-28591.6"
+ process $proc$libresoc.v:28543$627
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0]
- attribute \src "libresoc.v:28353.5-28353.29"
+ attribute \src "libresoc.v:28544.5-28544.29"
switch \initial
- attribute \src "libresoc.v:28353.9-28353.17"
+ attribute \src "libresoc.v:28544.9-28544.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0]
end
- attribute \src "libresoc.v:28401.3-28449.6"
- process $proc$libresoc.v:28401$588
+ attribute \src "libresoc.v:28592.3-28640.6"
+ process $proc$libresoc.v:28592$628
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0]
- attribute \src "libresoc.v:28402.5-28402.29"
+ attribute \src "libresoc.v:28593.5-28593.29"
switch \initial
- attribute \src "libresoc.v:28402.9-28402.17"
+ attribute \src "libresoc.v:28593.9-28593.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0]
end
- attribute \src "libresoc.v:28450.3-28498.6"
- process $proc$libresoc.v:28450$589
+ attribute \src "libresoc.v:28641.3-28689.6"
+ process $proc$libresoc.v:28641$629
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0]
- attribute \src "libresoc.v:28451.5-28451.29"
+ attribute \src "libresoc.v:28642.5-28642.29"
switch \initial
- attribute \src "libresoc.v:28451.9-28451.17"
+ attribute \src "libresoc.v:28642.9-28642.17"
case 1'1
case
end
sync always
update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0]
end
- attribute \src "libresoc.v:28499.3-28547.6"
- process $proc$libresoc.v:28499$590
+ attribute \src "libresoc.v:28690.3-28738.6"
+ process $proc$libresoc.v:28690$630
assign { } { }
assign { } { }
assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0]
- attribute \src "libresoc.v:28500.5-28500.29"
+ attribute \src "libresoc.v:28691.5-28691.29"
switch \initial
- attribute \src "libresoc.v:28500.9-28500.17"
+ attribute \src "libresoc.v:28691.9-28691.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:28553.1-30132.10"
+attribute \src "libresoc.v:28744.1-30323.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub22"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22"
attribute \generator "nMigen"
module \dec31_dec_sub22
- attribute \src "libresoc.v:29086.3-29140.6"
+ attribute \src "libresoc.v:29277.3-29331.6"
wire width 8 $0\dec31_dec_sub22_asmcode[7:0]
- attribute \src "libresoc.v:29306.3-29360.6"
+ attribute \src "libresoc.v:29497.3-29551.6"
wire $0\dec31_dec_sub22_br[0:0]
- attribute \src "libresoc.v:30021.3-30075.6"
+ attribute \src "libresoc.v:30212.3-30266.6"
wire width 3 $0\dec31_dec_sub22_cr_in[2:0]
- attribute \src "libresoc.v:30076.3-30130.6"
+ attribute \src "libresoc.v:30267.3-30321.6"
wire width 3 $0\dec31_dec_sub22_cr_out[2:0]
- attribute \src "libresoc.v:29031.3-29085.6"
+ attribute \src "libresoc.v:29222.3-29276.6"
wire width 2 $0\dec31_dec_sub22_cry_in[1:0]
- attribute \src "libresoc.v:29251.3-29305.6"
+ attribute \src "libresoc.v:29442.3-29496.6"
wire $0\dec31_dec_sub22_cry_out[0:0]
- attribute \src "libresoc.v:29746.3-29800.6"
+ attribute \src "libresoc.v:29937.3-29991.6"
wire width 5 $0\dec31_dec_sub22_form[4:0]
- attribute \src "libresoc.v:28811.3-28865.6"
+ attribute \src "libresoc.v:29002.3-29056.6"
wire width 12 $0\dec31_dec_sub22_function_unit[11:0]
- attribute \src "libresoc.v:29801.3-29855.6"
+ attribute \src "libresoc.v:29992.3-30046.6"
wire width 3 $0\dec31_dec_sub22_in1_sel[2:0]
- attribute \src "libresoc.v:29856.3-29910.6"
+ attribute \src "libresoc.v:30047.3-30101.6"
wire width 4 $0\dec31_dec_sub22_in2_sel[3:0]
- attribute \src "libresoc.v:29911.3-29965.6"
+ attribute \src "libresoc.v:30102.3-30156.6"
wire width 2 $0\dec31_dec_sub22_in3_sel[1:0]
- attribute \src "libresoc.v:29416.3-29470.6"
+ attribute \src "libresoc.v:29607.3-29661.6"
wire width 7 $0\dec31_dec_sub22_internal_op[6:0]
- attribute \src "libresoc.v:29141.3-29195.6"
+ attribute \src "libresoc.v:29332.3-29386.6"
wire $0\dec31_dec_sub22_inv_a[0:0]
- attribute \src "libresoc.v:29196.3-29250.6"
+ attribute \src "libresoc.v:29387.3-29441.6"
wire $0\dec31_dec_sub22_inv_out[0:0]
- attribute \src "libresoc.v:29526.3-29580.6"
+ attribute \src "libresoc.v:29717.3-29771.6"
wire $0\dec31_dec_sub22_is_32b[0:0]
- attribute \src "libresoc.v:28866.3-28920.6"
+ attribute \src "libresoc.v:29057.3-29111.6"
wire width 4 $0\dec31_dec_sub22_ldst_len[3:0]
- attribute \src "libresoc.v:29636.3-29690.6"
+ attribute \src "libresoc.v:29827.3-29881.6"
wire $0\dec31_dec_sub22_lk[0:0]
- attribute \src "libresoc.v:29966.3-30020.6"
+ attribute \src "libresoc.v:30157.3-30211.6"
wire width 2 $0\dec31_dec_sub22_out_sel[1:0]
- attribute \src "libresoc.v:28976.3-29030.6"
+ attribute \src "libresoc.v:29167.3-29221.6"
wire width 2 $0\dec31_dec_sub22_rc_sel[1:0]
- attribute \src "libresoc.v:29471.3-29525.6"
+ attribute \src "libresoc.v:29662.3-29716.6"
wire $0\dec31_dec_sub22_rsrv[0:0]
- attribute \src "libresoc.v:29691.3-29745.6"
+ attribute \src "libresoc.v:29882.3-29936.6"
wire $0\dec31_dec_sub22_sgl_pipe[0:0]
- attribute \src "libresoc.v:29581.3-29635.6"
+ attribute \src "libresoc.v:29772.3-29826.6"
wire $0\dec31_dec_sub22_sgn[0:0]
- attribute \src "libresoc.v:29361.3-29415.6"
+ attribute \src "libresoc.v:29552.3-29606.6"
wire $0\dec31_dec_sub22_sgn_ext[0:0]
- attribute \src "libresoc.v:28921.3-28975.6"
+ attribute \src "libresoc.v:29112.3-29166.6"
wire width 2 $0\dec31_dec_sub22_upd[1:0]
- attribute \src "libresoc.v:28554.7-28554.20"
+ attribute \src "libresoc.v:28745.7-28745.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:29086.3-29140.6"
+ attribute \src "libresoc.v:29277.3-29331.6"
wire width 8 $1\dec31_dec_sub22_asmcode[7:0]
- attribute \src "libresoc.v:29306.3-29360.6"
+ attribute \src "libresoc.v:29497.3-29551.6"
wire $1\dec31_dec_sub22_br[0:0]
- attribute \src "libresoc.v:30021.3-30075.6"
+ attribute \src "libresoc.v:30212.3-30266.6"
wire width 3 $1\dec31_dec_sub22_cr_in[2:0]
- attribute \src "libresoc.v:30076.3-30130.6"
+ attribute \src "libresoc.v:30267.3-30321.6"
wire width 3 $1\dec31_dec_sub22_cr_out[2:0]
- attribute \src "libresoc.v:29031.3-29085.6"
+ attribute \src "libresoc.v:29222.3-29276.6"
wire width 2 $1\dec31_dec_sub22_cry_in[1:0]
- attribute \src "libresoc.v:29251.3-29305.6"
+ attribute \src "libresoc.v:29442.3-29496.6"
wire $1\dec31_dec_sub22_cry_out[0:0]
- attribute \src "libresoc.v:29746.3-29800.6"
+ attribute \src "libresoc.v:29937.3-29991.6"
wire width 5 $1\dec31_dec_sub22_form[4:0]
- attribute \src "libresoc.v:28811.3-28865.6"
+ attribute \src "libresoc.v:29002.3-29056.6"
wire width 12 $1\dec31_dec_sub22_function_unit[11:0]
- attribute \src "libresoc.v:29801.3-29855.6"
+ attribute \src "libresoc.v:29992.3-30046.6"
wire width 3 $1\dec31_dec_sub22_in1_sel[2:0]
- attribute \src "libresoc.v:29856.3-29910.6"
+ attribute \src "libresoc.v:30047.3-30101.6"
wire width 4 $1\dec31_dec_sub22_in2_sel[3:0]
- attribute \src "libresoc.v:29911.3-29965.6"
+ attribute \src "libresoc.v:30102.3-30156.6"
wire width 2 $1\dec31_dec_sub22_in3_sel[1:0]
- attribute \src "libresoc.v:29416.3-29470.6"
+ attribute \src "libresoc.v:29607.3-29661.6"
wire width 7 $1\dec31_dec_sub22_internal_op[6:0]
- attribute \src "libresoc.v:29141.3-29195.6"
+ attribute \src "libresoc.v:29332.3-29386.6"
wire $1\dec31_dec_sub22_inv_a[0:0]
- attribute \src "libresoc.v:29196.3-29250.6"
+ attribute \src "libresoc.v:29387.3-29441.6"
wire $1\dec31_dec_sub22_inv_out[0:0]
- attribute \src "libresoc.v:29526.3-29580.6"
+ attribute \src "libresoc.v:29717.3-29771.6"
wire $1\dec31_dec_sub22_is_32b[0:0]
- attribute \src "libresoc.v:28866.3-28920.6"
+ attribute \src "libresoc.v:29057.3-29111.6"
wire width 4 $1\dec31_dec_sub22_ldst_len[3:0]
- attribute \src "libresoc.v:29636.3-29690.6"
+ attribute \src "libresoc.v:29827.3-29881.6"
wire $1\dec31_dec_sub22_lk[0:0]
- attribute \src "libresoc.v:29966.3-30020.6"
+ attribute \src "libresoc.v:30157.3-30211.6"
wire width 2 $1\dec31_dec_sub22_out_sel[1:0]
- attribute \src "libresoc.v:28976.3-29030.6"
+ attribute \src "libresoc.v:29167.3-29221.6"
wire width 2 $1\dec31_dec_sub22_rc_sel[1:0]
- attribute \src "libresoc.v:29471.3-29525.6"
+ attribute \src "libresoc.v:29662.3-29716.6"
wire $1\dec31_dec_sub22_rsrv[0:0]
- attribute \src "libresoc.v:29691.3-29745.6"
+ attribute \src "libresoc.v:29882.3-29936.6"
wire $1\dec31_dec_sub22_sgl_pipe[0:0]
- attribute \src "libresoc.v:29581.3-29635.6"
+ attribute \src "libresoc.v:29772.3-29826.6"
wire $1\dec31_dec_sub22_sgn[0:0]
- attribute \src "libresoc.v:29361.3-29415.6"
+ attribute \src "libresoc.v:29552.3-29606.6"
wire $1\dec31_dec_sub22_sgn_ext[0:0]
- attribute \src "libresoc.v:28921.3-28975.6"
+ attribute \src "libresoc.v:29112.3-29166.6"
wire width 2 $1\dec31_dec_sub22_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub22_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub22_upd
- attribute \src "libresoc.v:28554.7-28554.15"
+ attribute \src "libresoc.v:28745.7-28745.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:28554.7-28554.20"
- process $proc$libresoc.v:28554$616
+ attribute \src "libresoc.v:28745.7-28745.20"
+ process $proc$libresoc.v:28745$656
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:28811.3-28865.6"
- process $proc$libresoc.v:28811$592
+ attribute \src "libresoc.v:29002.3-29056.6"
+ process $proc$libresoc.v:29002$632
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0]
- attribute \src "libresoc.v:28812.5-28812.29"
+ attribute \src "libresoc.v:29003.5-29003.29"
switch \initial
- attribute \src "libresoc.v:28812.9-28812.17"
+ attribute \src "libresoc.v:29003.9-29003.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0]
end
- attribute \src "libresoc.v:28866.3-28920.6"
- process $proc$libresoc.v:28866$593
+ attribute \src "libresoc.v:29057.3-29111.6"
+ process $proc$libresoc.v:29057$633
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0]
- attribute \src "libresoc.v:28867.5-28867.29"
+ attribute \src "libresoc.v:29058.5-29058.29"
switch \initial
- attribute \src "libresoc.v:28867.9-28867.17"
+ attribute \src "libresoc.v:29058.9-29058.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0]
end
- attribute \src "libresoc.v:28921.3-28975.6"
- process $proc$libresoc.v:28921$594
+ attribute \src "libresoc.v:29112.3-29166.6"
+ process $proc$libresoc.v:29112$634
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0]
- attribute \src "libresoc.v:28922.5-28922.29"
+ attribute \src "libresoc.v:29113.5-29113.29"
switch \initial
- attribute \src "libresoc.v:28922.9-28922.17"
+ attribute \src "libresoc.v:29113.9-29113.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0]
end
- attribute \src "libresoc.v:28976.3-29030.6"
- process $proc$libresoc.v:28976$595
+ attribute \src "libresoc.v:29167.3-29221.6"
+ process $proc$libresoc.v:29167$635
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0]
- attribute \src "libresoc.v:28977.5-28977.29"
+ attribute \src "libresoc.v:29168.5-29168.29"
switch \initial
- attribute \src "libresoc.v:28977.9-28977.17"
+ attribute \src "libresoc.v:29168.9-29168.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0]
end
- attribute \src "libresoc.v:29031.3-29085.6"
- process $proc$libresoc.v:29031$596
+ attribute \src "libresoc.v:29222.3-29276.6"
+ process $proc$libresoc.v:29222$636
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0]
- attribute \src "libresoc.v:29032.5-29032.29"
+ attribute \src "libresoc.v:29223.5-29223.29"
switch \initial
- attribute \src "libresoc.v:29032.9-29032.17"
+ attribute \src "libresoc.v:29223.9-29223.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0]
end
- attribute \src "libresoc.v:29086.3-29140.6"
- process $proc$libresoc.v:29086$597
+ attribute \src "libresoc.v:29277.3-29331.6"
+ process $proc$libresoc.v:29277$637
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0]
- attribute \src "libresoc.v:29087.5-29087.29"
+ attribute \src "libresoc.v:29278.5-29278.29"
switch \initial
- attribute \src "libresoc.v:29087.9-29087.17"
+ attribute \src "libresoc.v:29278.9-29278.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0]
end
- attribute \src "libresoc.v:29141.3-29195.6"
- process $proc$libresoc.v:29141$598
+ attribute \src "libresoc.v:29332.3-29386.6"
+ process $proc$libresoc.v:29332$638
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0]
- attribute \src "libresoc.v:29142.5-29142.29"
+ attribute \src "libresoc.v:29333.5-29333.29"
switch \initial
- attribute \src "libresoc.v:29142.9-29142.17"
+ attribute \src "libresoc.v:29333.9-29333.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0]
end
- attribute \src "libresoc.v:29196.3-29250.6"
- process $proc$libresoc.v:29196$599
+ attribute \src "libresoc.v:29387.3-29441.6"
+ process $proc$libresoc.v:29387$639
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0]
- attribute \src "libresoc.v:29197.5-29197.29"
+ attribute \src "libresoc.v:29388.5-29388.29"
switch \initial
- attribute \src "libresoc.v:29197.9-29197.17"
+ attribute \src "libresoc.v:29388.9-29388.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0]
end
- attribute \src "libresoc.v:29251.3-29305.6"
- process $proc$libresoc.v:29251$600
+ attribute \src "libresoc.v:29442.3-29496.6"
+ process $proc$libresoc.v:29442$640
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0]
- attribute \src "libresoc.v:29252.5-29252.29"
+ attribute \src "libresoc.v:29443.5-29443.29"
switch \initial
- attribute \src "libresoc.v:29252.9-29252.17"
+ attribute \src "libresoc.v:29443.9-29443.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0]
end
- attribute \src "libresoc.v:29306.3-29360.6"
- process $proc$libresoc.v:29306$601
+ attribute \src "libresoc.v:29497.3-29551.6"
+ process $proc$libresoc.v:29497$641
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0]
- attribute \src "libresoc.v:29307.5-29307.29"
+ attribute \src "libresoc.v:29498.5-29498.29"
switch \initial
- attribute \src "libresoc.v:29307.9-29307.17"
+ attribute \src "libresoc.v:29498.9-29498.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0]
end
- attribute \src "libresoc.v:29361.3-29415.6"
- process $proc$libresoc.v:29361$602
+ attribute \src "libresoc.v:29552.3-29606.6"
+ process $proc$libresoc.v:29552$642
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0]
- attribute \src "libresoc.v:29362.5-29362.29"
+ attribute \src "libresoc.v:29553.5-29553.29"
switch \initial
- attribute \src "libresoc.v:29362.9-29362.17"
+ attribute \src "libresoc.v:29553.9-29553.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0]
end
- attribute \src "libresoc.v:29416.3-29470.6"
- process $proc$libresoc.v:29416$603
+ attribute \src "libresoc.v:29607.3-29661.6"
+ process $proc$libresoc.v:29607$643
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0]
- attribute \src "libresoc.v:29417.5-29417.29"
+ attribute \src "libresoc.v:29608.5-29608.29"
switch \initial
- attribute \src "libresoc.v:29417.9-29417.17"
+ attribute \src "libresoc.v:29608.9-29608.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0]
end
- attribute \src "libresoc.v:29471.3-29525.6"
- process $proc$libresoc.v:29471$604
+ attribute \src "libresoc.v:29662.3-29716.6"
+ process $proc$libresoc.v:29662$644
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0]
- attribute \src "libresoc.v:29472.5-29472.29"
+ attribute \src "libresoc.v:29663.5-29663.29"
switch \initial
- attribute \src "libresoc.v:29472.9-29472.17"
+ attribute \src "libresoc.v:29663.9-29663.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0]
end
- attribute \src "libresoc.v:29526.3-29580.6"
- process $proc$libresoc.v:29526$605
+ attribute \src "libresoc.v:29717.3-29771.6"
+ process $proc$libresoc.v:29717$645
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0]
- attribute \src "libresoc.v:29527.5-29527.29"
+ attribute \src "libresoc.v:29718.5-29718.29"
switch \initial
- attribute \src "libresoc.v:29527.9-29527.17"
+ attribute \src "libresoc.v:29718.9-29718.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0]
end
- attribute \src "libresoc.v:29581.3-29635.6"
- process $proc$libresoc.v:29581$606
+ attribute \src "libresoc.v:29772.3-29826.6"
+ process $proc$libresoc.v:29772$646
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0]
- attribute \src "libresoc.v:29582.5-29582.29"
+ attribute \src "libresoc.v:29773.5-29773.29"
switch \initial
- attribute \src "libresoc.v:29582.9-29582.17"
+ attribute \src "libresoc.v:29773.9-29773.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0]
end
- attribute \src "libresoc.v:29636.3-29690.6"
- process $proc$libresoc.v:29636$607
+ attribute \src "libresoc.v:29827.3-29881.6"
+ process $proc$libresoc.v:29827$647
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0]
- attribute \src "libresoc.v:29637.5-29637.29"
+ attribute \src "libresoc.v:29828.5-29828.29"
switch \initial
- attribute \src "libresoc.v:29637.9-29637.17"
+ attribute \src "libresoc.v:29828.9-29828.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0]
end
- attribute \src "libresoc.v:29691.3-29745.6"
- process $proc$libresoc.v:29691$608
+ attribute \src "libresoc.v:29882.3-29936.6"
+ process $proc$libresoc.v:29882$648
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0]
- attribute \src "libresoc.v:29692.5-29692.29"
+ attribute \src "libresoc.v:29883.5-29883.29"
switch \initial
- attribute \src "libresoc.v:29692.9-29692.17"
+ attribute \src "libresoc.v:29883.9-29883.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:29746.3-29800.6"
- process $proc$libresoc.v:29746$609
+ attribute \src "libresoc.v:29937.3-29991.6"
+ process $proc$libresoc.v:29937$649
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0]
- attribute \src "libresoc.v:29747.5-29747.29"
+ attribute \src "libresoc.v:29938.5-29938.29"
switch \initial
- attribute \src "libresoc.v:29747.9-29747.17"
+ attribute \src "libresoc.v:29938.9-29938.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0]
end
- attribute \src "libresoc.v:29801.3-29855.6"
- process $proc$libresoc.v:29801$610
+ attribute \src "libresoc.v:29992.3-30046.6"
+ process $proc$libresoc.v:29992$650
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0]
- attribute \src "libresoc.v:29802.5-29802.29"
+ attribute \src "libresoc.v:29993.5-29993.29"
switch \initial
- attribute \src "libresoc.v:29802.9-29802.17"
+ attribute \src "libresoc.v:29993.9-29993.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0]
end
- attribute \src "libresoc.v:29856.3-29910.6"
- process $proc$libresoc.v:29856$611
+ attribute \src "libresoc.v:30047.3-30101.6"
+ process $proc$libresoc.v:30047$651
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0]
- attribute \src "libresoc.v:29857.5-29857.29"
+ attribute \src "libresoc.v:30048.5-30048.29"
switch \initial
- attribute \src "libresoc.v:29857.9-29857.17"
+ attribute \src "libresoc.v:30048.9-30048.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0]
end
- attribute \src "libresoc.v:29911.3-29965.6"
- process $proc$libresoc.v:29911$612
+ attribute \src "libresoc.v:30102.3-30156.6"
+ process $proc$libresoc.v:30102$652
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0]
- attribute \src "libresoc.v:29912.5-29912.29"
+ attribute \src "libresoc.v:30103.5-30103.29"
switch \initial
- attribute \src "libresoc.v:29912.9-29912.17"
+ attribute \src "libresoc.v:30103.9-30103.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0]
end
- attribute \src "libresoc.v:29966.3-30020.6"
- process $proc$libresoc.v:29966$613
+ attribute \src "libresoc.v:30157.3-30211.6"
+ process $proc$libresoc.v:30157$653
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0]
- attribute \src "libresoc.v:29967.5-29967.29"
+ attribute \src "libresoc.v:30158.5-30158.29"
switch \initial
- attribute \src "libresoc.v:29967.9-29967.17"
+ attribute \src "libresoc.v:30158.9-30158.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0]
end
- attribute \src "libresoc.v:30021.3-30075.6"
- process $proc$libresoc.v:30021$614
+ attribute \src "libresoc.v:30212.3-30266.6"
+ process $proc$libresoc.v:30212$654
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0]
- attribute \src "libresoc.v:30022.5-30022.29"
+ attribute \src "libresoc.v:30213.5-30213.29"
switch \initial
- attribute \src "libresoc.v:30022.9-30022.17"
+ attribute \src "libresoc.v:30213.9-30213.17"
case 1'1
case
end
sync always
update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0]
end
- attribute \src "libresoc.v:30076.3-30130.6"
- process $proc$libresoc.v:30076$615
+ attribute \src "libresoc.v:30267.3-30321.6"
+ process $proc$libresoc.v:30267$655
assign { } { }
assign { } { }
assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0]
- attribute \src "libresoc.v:30077.5-30077.29"
+ attribute \src "libresoc.v:30268.5-30268.29"
switch \initial
- attribute \src "libresoc.v:30077.9-30077.17"
+ attribute \src "libresoc.v:30268.9-30268.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:30136.1-31571.10"
+attribute \src "libresoc.v:30327.1-31762.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub23"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23"
attribute \generator "nMigen"
module \dec31_dec_sub23
- attribute \src "libresoc.v:30639.3-30687.6"
+ attribute \src "libresoc.v:30830.3-30878.6"
wire width 8 $0\dec31_dec_sub23_asmcode[7:0]
- attribute \src "libresoc.v:30835.3-30883.6"
+ attribute \src "libresoc.v:31026.3-31074.6"
wire $0\dec31_dec_sub23_br[0:0]
- attribute \src "libresoc.v:31472.3-31520.6"
+ attribute \src "libresoc.v:31663.3-31711.6"
wire width 3 $0\dec31_dec_sub23_cr_in[2:0]
- attribute \src "libresoc.v:31521.3-31569.6"
+ attribute \src "libresoc.v:31712.3-31760.6"
wire width 3 $0\dec31_dec_sub23_cr_out[2:0]
- attribute \src "libresoc.v:30590.3-30638.6"
+ attribute \src "libresoc.v:30781.3-30829.6"
wire width 2 $0\dec31_dec_sub23_cry_in[1:0]
- attribute \src "libresoc.v:30786.3-30834.6"
+ attribute \src "libresoc.v:30977.3-31025.6"
wire $0\dec31_dec_sub23_cry_out[0:0]
- attribute \src "libresoc.v:31227.3-31275.6"
+ attribute \src "libresoc.v:31418.3-31466.6"
wire width 5 $0\dec31_dec_sub23_form[4:0]
- attribute \src "libresoc.v:30394.3-30442.6"
+ attribute \src "libresoc.v:30585.3-30633.6"
wire width 12 $0\dec31_dec_sub23_function_unit[11:0]
- attribute \src "libresoc.v:31276.3-31324.6"
+ attribute \src "libresoc.v:31467.3-31515.6"
wire width 3 $0\dec31_dec_sub23_in1_sel[2:0]
- attribute \src "libresoc.v:31325.3-31373.6"
+ attribute \src "libresoc.v:31516.3-31564.6"
wire width 4 $0\dec31_dec_sub23_in2_sel[3:0]
- attribute \src "libresoc.v:31374.3-31422.6"
+ attribute \src "libresoc.v:31565.3-31613.6"
wire width 2 $0\dec31_dec_sub23_in3_sel[1:0]
- attribute \src "libresoc.v:30933.3-30981.6"
+ attribute \src "libresoc.v:31124.3-31172.6"
wire width 7 $0\dec31_dec_sub23_internal_op[6:0]
- attribute \src "libresoc.v:30688.3-30736.6"
+ attribute \src "libresoc.v:30879.3-30927.6"
wire $0\dec31_dec_sub23_inv_a[0:0]
- attribute \src "libresoc.v:30737.3-30785.6"
+ attribute \src "libresoc.v:30928.3-30976.6"
wire $0\dec31_dec_sub23_inv_out[0:0]
- attribute \src "libresoc.v:31031.3-31079.6"
+ attribute \src "libresoc.v:31222.3-31270.6"
wire $0\dec31_dec_sub23_is_32b[0:0]
- attribute \src "libresoc.v:30443.3-30491.6"
+ attribute \src "libresoc.v:30634.3-30682.6"
wire width 4 $0\dec31_dec_sub23_ldst_len[3:0]
- attribute \src "libresoc.v:31129.3-31177.6"
+ attribute \src "libresoc.v:31320.3-31368.6"
wire $0\dec31_dec_sub23_lk[0:0]
- attribute \src "libresoc.v:31423.3-31471.6"
+ attribute \src "libresoc.v:31614.3-31662.6"
wire width 2 $0\dec31_dec_sub23_out_sel[1:0]
- attribute \src "libresoc.v:30541.3-30589.6"
+ attribute \src "libresoc.v:30732.3-30780.6"
wire width 2 $0\dec31_dec_sub23_rc_sel[1:0]
- attribute \src "libresoc.v:30982.3-31030.6"
+ attribute \src "libresoc.v:31173.3-31221.6"
wire $0\dec31_dec_sub23_rsrv[0:0]
- attribute \src "libresoc.v:31178.3-31226.6"
+ attribute \src "libresoc.v:31369.3-31417.6"
wire $0\dec31_dec_sub23_sgl_pipe[0:0]
- attribute \src "libresoc.v:31080.3-31128.6"
+ attribute \src "libresoc.v:31271.3-31319.6"
wire $0\dec31_dec_sub23_sgn[0:0]
- attribute \src "libresoc.v:30884.3-30932.6"
+ attribute \src "libresoc.v:31075.3-31123.6"
wire $0\dec31_dec_sub23_sgn_ext[0:0]
- attribute \src "libresoc.v:30492.3-30540.6"
+ attribute \src "libresoc.v:30683.3-30731.6"
wire width 2 $0\dec31_dec_sub23_upd[1:0]
- attribute \src "libresoc.v:30137.7-30137.20"
+ attribute \src "libresoc.v:30328.7-30328.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:30639.3-30687.6"
+ attribute \src "libresoc.v:30830.3-30878.6"
wire width 8 $1\dec31_dec_sub23_asmcode[7:0]
- attribute \src "libresoc.v:30835.3-30883.6"
+ attribute \src "libresoc.v:31026.3-31074.6"
wire $1\dec31_dec_sub23_br[0:0]
- attribute \src "libresoc.v:31472.3-31520.6"
+ attribute \src "libresoc.v:31663.3-31711.6"
wire width 3 $1\dec31_dec_sub23_cr_in[2:0]
- attribute \src "libresoc.v:31521.3-31569.6"
+ attribute \src "libresoc.v:31712.3-31760.6"
wire width 3 $1\dec31_dec_sub23_cr_out[2:0]
- attribute \src "libresoc.v:30590.3-30638.6"
+ attribute \src "libresoc.v:30781.3-30829.6"
wire width 2 $1\dec31_dec_sub23_cry_in[1:0]
- attribute \src "libresoc.v:30786.3-30834.6"
+ attribute \src "libresoc.v:30977.3-31025.6"
wire $1\dec31_dec_sub23_cry_out[0:0]
- attribute \src "libresoc.v:31227.3-31275.6"
+ attribute \src "libresoc.v:31418.3-31466.6"
wire width 5 $1\dec31_dec_sub23_form[4:0]
- attribute \src "libresoc.v:30394.3-30442.6"
+ attribute \src "libresoc.v:30585.3-30633.6"
wire width 12 $1\dec31_dec_sub23_function_unit[11:0]
- attribute \src "libresoc.v:31276.3-31324.6"
+ attribute \src "libresoc.v:31467.3-31515.6"
wire width 3 $1\dec31_dec_sub23_in1_sel[2:0]
- attribute \src "libresoc.v:31325.3-31373.6"
+ attribute \src "libresoc.v:31516.3-31564.6"
wire width 4 $1\dec31_dec_sub23_in2_sel[3:0]
- attribute \src "libresoc.v:31374.3-31422.6"
+ attribute \src "libresoc.v:31565.3-31613.6"
wire width 2 $1\dec31_dec_sub23_in3_sel[1:0]
- attribute \src "libresoc.v:30933.3-30981.6"
+ attribute \src "libresoc.v:31124.3-31172.6"
wire width 7 $1\dec31_dec_sub23_internal_op[6:0]
- attribute \src "libresoc.v:30688.3-30736.6"
+ attribute \src "libresoc.v:30879.3-30927.6"
wire $1\dec31_dec_sub23_inv_a[0:0]
- attribute \src "libresoc.v:30737.3-30785.6"
+ attribute \src "libresoc.v:30928.3-30976.6"
wire $1\dec31_dec_sub23_inv_out[0:0]
- attribute \src "libresoc.v:31031.3-31079.6"
+ attribute \src "libresoc.v:31222.3-31270.6"
wire $1\dec31_dec_sub23_is_32b[0:0]
- attribute \src "libresoc.v:30443.3-30491.6"
+ attribute \src "libresoc.v:30634.3-30682.6"
wire width 4 $1\dec31_dec_sub23_ldst_len[3:0]
- attribute \src "libresoc.v:31129.3-31177.6"
+ attribute \src "libresoc.v:31320.3-31368.6"
wire $1\dec31_dec_sub23_lk[0:0]
- attribute \src "libresoc.v:31423.3-31471.6"
+ attribute \src "libresoc.v:31614.3-31662.6"
wire width 2 $1\dec31_dec_sub23_out_sel[1:0]
- attribute \src "libresoc.v:30541.3-30589.6"
+ attribute \src "libresoc.v:30732.3-30780.6"
wire width 2 $1\dec31_dec_sub23_rc_sel[1:0]
- attribute \src "libresoc.v:30982.3-31030.6"
+ attribute \src "libresoc.v:31173.3-31221.6"
wire $1\dec31_dec_sub23_rsrv[0:0]
- attribute \src "libresoc.v:31178.3-31226.6"
+ attribute \src "libresoc.v:31369.3-31417.6"
wire $1\dec31_dec_sub23_sgl_pipe[0:0]
- attribute \src "libresoc.v:31080.3-31128.6"
+ attribute \src "libresoc.v:31271.3-31319.6"
wire $1\dec31_dec_sub23_sgn[0:0]
- attribute \src "libresoc.v:30884.3-30932.6"
+ attribute \src "libresoc.v:31075.3-31123.6"
wire $1\dec31_dec_sub23_sgn_ext[0:0]
- attribute \src "libresoc.v:30492.3-30540.6"
+ attribute \src "libresoc.v:30683.3-30731.6"
wire width 2 $1\dec31_dec_sub23_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub23_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub23_upd
- attribute \src "libresoc.v:30137.7-30137.15"
+ attribute \src "libresoc.v:30328.7-30328.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:30137.7-30137.20"
- process $proc$libresoc.v:30137$641
+ attribute \src "libresoc.v:30328.7-30328.20"
+ process $proc$libresoc.v:30328$681
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:30394.3-30442.6"
- process $proc$libresoc.v:30394$617
+ attribute \src "libresoc.v:30585.3-30633.6"
+ process $proc$libresoc.v:30585$657
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0]
- attribute \src "libresoc.v:30395.5-30395.29"
+ attribute \src "libresoc.v:30586.5-30586.29"
switch \initial
- attribute \src "libresoc.v:30395.9-30395.17"
+ attribute \src "libresoc.v:30586.9-30586.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0]
end
- attribute \src "libresoc.v:30443.3-30491.6"
- process $proc$libresoc.v:30443$618
+ attribute \src "libresoc.v:30634.3-30682.6"
+ process $proc$libresoc.v:30634$658
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0]
- attribute \src "libresoc.v:30444.5-30444.29"
+ attribute \src "libresoc.v:30635.5-30635.29"
switch \initial
- attribute \src "libresoc.v:30444.9-30444.17"
+ attribute \src "libresoc.v:30635.9-30635.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0]
end
- attribute \src "libresoc.v:30492.3-30540.6"
- process $proc$libresoc.v:30492$619
+ attribute \src "libresoc.v:30683.3-30731.6"
+ process $proc$libresoc.v:30683$659
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0]
- attribute \src "libresoc.v:30493.5-30493.29"
+ attribute \src "libresoc.v:30684.5-30684.29"
switch \initial
- attribute \src "libresoc.v:30493.9-30493.17"
+ attribute \src "libresoc.v:30684.9-30684.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0]
end
- attribute \src "libresoc.v:30541.3-30589.6"
- process $proc$libresoc.v:30541$620
+ attribute \src "libresoc.v:30732.3-30780.6"
+ process $proc$libresoc.v:30732$660
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0]
- attribute \src "libresoc.v:30542.5-30542.29"
+ attribute \src "libresoc.v:30733.5-30733.29"
switch \initial
- attribute \src "libresoc.v:30542.9-30542.17"
+ attribute \src "libresoc.v:30733.9-30733.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0]
end
- attribute \src "libresoc.v:30590.3-30638.6"
- process $proc$libresoc.v:30590$621
+ attribute \src "libresoc.v:30781.3-30829.6"
+ process $proc$libresoc.v:30781$661
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0]
- attribute \src "libresoc.v:30591.5-30591.29"
+ attribute \src "libresoc.v:30782.5-30782.29"
switch \initial
- attribute \src "libresoc.v:30591.9-30591.17"
+ attribute \src "libresoc.v:30782.9-30782.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0]
end
- attribute \src "libresoc.v:30639.3-30687.6"
- process $proc$libresoc.v:30639$622
+ attribute \src "libresoc.v:30830.3-30878.6"
+ process $proc$libresoc.v:30830$662
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0]
- attribute \src "libresoc.v:30640.5-30640.29"
+ attribute \src "libresoc.v:30831.5-30831.29"
switch \initial
- attribute \src "libresoc.v:30640.9-30640.17"
+ attribute \src "libresoc.v:30831.9-30831.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0]
end
- attribute \src "libresoc.v:30688.3-30736.6"
- process $proc$libresoc.v:30688$623
+ attribute \src "libresoc.v:30879.3-30927.6"
+ process $proc$libresoc.v:30879$663
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0]
- attribute \src "libresoc.v:30689.5-30689.29"
+ attribute \src "libresoc.v:30880.5-30880.29"
switch \initial
- attribute \src "libresoc.v:30689.9-30689.17"
+ attribute \src "libresoc.v:30880.9-30880.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0]
end
- attribute \src "libresoc.v:30737.3-30785.6"
- process $proc$libresoc.v:30737$624
+ attribute \src "libresoc.v:30928.3-30976.6"
+ process $proc$libresoc.v:30928$664
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0]
- attribute \src "libresoc.v:30738.5-30738.29"
+ attribute \src "libresoc.v:30929.5-30929.29"
switch \initial
- attribute \src "libresoc.v:30738.9-30738.17"
+ attribute \src "libresoc.v:30929.9-30929.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0]
end
- attribute \src "libresoc.v:30786.3-30834.6"
- process $proc$libresoc.v:30786$625
+ attribute \src "libresoc.v:30977.3-31025.6"
+ process $proc$libresoc.v:30977$665
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0]
- attribute \src "libresoc.v:30787.5-30787.29"
+ attribute \src "libresoc.v:30978.5-30978.29"
switch \initial
- attribute \src "libresoc.v:30787.9-30787.17"
+ attribute \src "libresoc.v:30978.9-30978.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0]
end
- attribute \src "libresoc.v:30835.3-30883.6"
- process $proc$libresoc.v:30835$626
+ attribute \src "libresoc.v:31026.3-31074.6"
+ process $proc$libresoc.v:31026$666
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0]
- attribute \src "libresoc.v:30836.5-30836.29"
+ attribute \src "libresoc.v:31027.5-31027.29"
switch \initial
- attribute \src "libresoc.v:30836.9-30836.17"
+ attribute \src "libresoc.v:31027.9-31027.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0]
end
- attribute \src "libresoc.v:30884.3-30932.6"
- process $proc$libresoc.v:30884$627
+ attribute \src "libresoc.v:31075.3-31123.6"
+ process $proc$libresoc.v:31075$667
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0]
- attribute \src "libresoc.v:30885.5-30885.29"
+ attribute \src "libresoc.v:31076.5-31076.29"
switch \initial
- attribute \src "libresoc.v:30885.9-30885.17"
+ attribute \src "libresoc.v:31076.9-31076.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0]
end
- attribute \src "libresoc.v:30933.3-30981.6"
- process $proc$libresoc.v:30933$628
+ attribute \src "libresoc.v:31124.3-31172.6"
+ process $proc$libresoc.v:31124$668
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0]
- attribute \src "libresoc.v:30934.5-30934.29"
+ attribute \src "libresoc.v:31125.5-31125.29"
switch \initial
- attribute \src "libresoc.v:30934.9-30934.17"
+ attribute \src "libresoc.v:31125.9-31125.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0]
end
- attribute \src "libresoc.v:30982.3-31030.6"
- process $proc$libresoc.v:30982$629
+ attribute \src "libresoc.v:31173.3-31221.6"
+ process $proc$libresoc.v:31173$669
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0]
- attribute \src "libresoc.v:30983.5-30983.29"
+ attribute \src "libresoc.v:31174.5-31174.29"
switch \initial
- attribute \src "libresoc.v:30983.9-30983.17"
+ attribute \src "libresoc.v:31174.9-31174.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0]
end
- attribute \src "libresoc.v:31031.3-31079.6"
- process $proc$libresoc.v:31031$630
+ attribute \src "libresoc.v:31222.3-31270.6"
+ process $proc$libresoc.v:31222$670
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0]
- attribute \src "libresoc.v:31032.5-31032.29"
+ attribute \src "libresoc.v:31223.5-31223.29"
switch \initial
- attribute \src "libresoc.v:31032.9-31032.17"
+ attribute \src "libresoc.v:31223.9-31223.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0]
end
- attribute \src "libresoc.v:31080.3-31128.6"
- process $proc$libresoc.v:31080$631
+ attribute \src "libresoc.v:31271.3-31319.6"
+ process $proc$libresoc.v:31271$671
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0]
- attribute \src "libresoc.v:31081.5-31081.29"
+ attribute \src "libresoc.v:31272.5-31272.29"
switch \initial
- attribute \src "libresoc.v:31081.9-31081.17"
+ attribute \src "libresoc.v:31272.9-31272.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0]
end
- attribute \src "libresoc.v:31129.3-31177.6"
- process $proc$libresoc.v:31129$632
+ attribute \src "libresoc.v:31320.3-31368.6"
+ process $proc$libresoc.v:31320$672
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0]
- attribute \src "libresoc.v:31130.5-31130.29"
+ attribute \src "libresoc.v:31321.5-31321.29"
switch \initial
- attribute \src "libresoc.v:31130.9-31130.17"
+ attribute \src "libresoc.v:31321.9-31321.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0]
end
- attribute \src "libresoc.v:31178.3-31226.6"
- process $proc$libresoc.v:31178$633
+ attribute \src "libresoc.v:31369.3-31417.6"
+ process $proc$libresoc.v:31369$673
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0]
- attribute \src "libresoc.v:31179.5-31179.29"
+ attribute \src "libresoc.v:31370.5-31370.29"
switch \initial
- attribute \src "libresoc.v:31179.9-31179.17"
+ attribute \src "libresoc.v:31370.9-31370.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:31227.3-31275.6"
- process $proc$libresoc.v:31227$634
+ attribute \src "libresoc.v:31418.3-31466.6"
+ process $proc$libresoc.v:31418$674
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0]
- attribute \src "libresoc.v:31228.5-31228.29"
+ attribute \src "libresoc.v:31419.5-31419.29"
switch \initial
- attribute \src "libresoc.v:31228.9-31228.17"
+ attribute \src "libresoc.v:31419.9-31419.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0]
end
- attribute \src "libresoc.v:31276.3-31324.6"
- process $proc$libresoc.v:31276$635
+ attribute \src "libresoc.v:31467.3-31515.6"
+ process $proc$libresoc.v:31467$675
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0]
- attribute \src "libresoc.v:31277.5-31277.29"
+ attribute \src "libresoc.v:31468.5-31468.29"
switch \initial
- attribute \src "libresoc.v:31277.9-31277.17"
+ attribute \src "libresoc.v:31468.9-31468.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0]
end
- attribute \src "libresoc.v:31325.3-31373.6"
- process $proc$libresoc.v:31325$636
+ attribute \src "libresoc.v:31516.3-31564.6"
+ process $proc$libresoc.v:31516$676
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0]
- attribute \src "libresoc.v:31326.5-31326.29"
+ attribute \src "libresoc.v:31517.5-31517.29"
switch \initial
- attribute \src "libresoc.v:31326.9-31326.17"
+ attribute \src "libresoc.v:31517.9-31517.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0]
end
- attribute \src "libresoc.v:31374.3-31422.6"
- process $proc$libresoc.v:31374$637
+ attribute \src "libresoc.v:31565.3-31613.6"
+ process $proc$libresoc.v:31565$677
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0]
- attribute \src "libresoc.v:31375.5-31375.29"
+ attribute \src "libresoc.v:31566.5-31566.29"
switch \initial
- attribute \src "libresoc.v:31375.9-31375.17"
+ attribute \src "libresoc.v:31566.9-31566.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0]
end
- attribute \src "libresoc.v:31423.3-31471.6"
- process $proc$libresoc.v:31423$638
+ attribute \src "libresoc.v:31614.3-31662.6"
+ process $proc$libresoc.v:31614$678
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0]
- attribute \src "libresoc.v:31424.5-31424.29"
+ attribute \src "libresoc.v:31615.5-31615.29"
switch \initial
- attribute \src "libresoc.v:31424.9-31424.17"
+ attribute \src "libresoc.v:31615.9-31615.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0]
end
- attribute \src "libresoc.v:31472.3-31520.6"
- process $proc$libresoc.v:31472$639
+ attribute \src "libresoc.v:31663.3-31711.6"
+ process $proc$libresoc.v:31663$679
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0]
- attribute \src "libresoc.v:31473.5-31473.29"
+ attribute \src "libresoc.v:31664.5-31664.29"
switch \initial
- attribute \src "libresoc.v:31473.9-31473.17"
+ attribute \src "libresoc.v:31664.9-31664.17"
case 1'1
case
end
sync always
update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0]
end
- attribute \src "libresoc.v:31521.3-31569.6"
- process $proc$libresoc.v:31521$640
+ attribute \src "libresoc.v:31712.3-31760.6"
+ process $proc$libresoc.v:31712$680
assign { } { }
assign { } { }
assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0]
- attribute \src "libresoc.v:31522.5-31522.29"
+ attribute \src "libresoc.v:31713.5-31713.29"
switch \initial
- attribute \src "libresoc.v:31522.9-31522.17"
+ attribute \src "libresoc.v:31713.9-31713.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:31575.1-32290.10"
+attribute \src "libresoc.v:31766.1-32481.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub24"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24"
attribute \generator "nMigen"
module \dec31_dec_sub24
- attribute \src "libresoc.v:31928.3-31946.6"
+ attribute \src "libresoc.v:32119.3-32137.6"
wire width 8 $0\dec31_dec_sub24_asmcode[7:0]
- attribute \src "libresoc.v:32004.3-32022.6"
+ attribute \src "libresoc.v:32195.3-32213.6"
wire $0\dec31_dec_sub24_br[0:0]
- attribute \src "libresoc.v:32251.3-32269.6"
+ attribute \src "libresoc.v:32442.3-32460.6"
wire width 3 $0\dec31_dec_sub24_cr_in[2:0]
- attribute \src "libresoc.v:32270.3-32288.6"
+ attribute \src "libresoc.v:32461.3-32479.6"
wire width 3 $0\dec31_dec_sub24_cr_out[2:0]
- attribute \src "libresoc.v:31909.3-31927.6"
+ attribute \src "libresoc.v:32100.3-32118.6"
wire width 2 $0\dec31_dec_sub24_cry_in[1:0]
- attribute \src "libresoc.v:31985.3-32003.6"
+ attribute \src "libresoc.v:32176.3-32194.6"
wire $0\dec31_dec_sub24_cry_out[0:0]
- attribute \src "libresoc.v:32156.3-32174.6"
+ attribute \src "libresoc.v:32347.3-32365.6"
wire width 5 $0\dec31_dec_sub24_form[4:0]
- attribute \src "libresoc.v:31833.3-31851.6"
+ attribute \src "libresoc.v:32024.3-32042.6"
wire width 12 $0\dec31_dec_sub24_function_unit[11:0]
- attribute \src "libresoc.v:32175.3-32193.6"
+ attribute \src "libresoc.v:32366.3-32384.6"
wire width 3 $0\dec31_dec_sub24_in1_sel[2:0]
- attribute \src "libresoc.v:32194.3-32212.6"
+ attribute \src "libresoc.v:32385.3-32403.6"
wire width 4 $0\dec31_dec_sub24_in2_sel[3:0]
- attribute \src "libresoc.v:32213.3-32231.6"
+ attribute \src "libresoc.v:32404.3-32422.6"
wire width 2 $0\dec31_dec_sub24_in3_sel[1:0]
- attribute \src "libresoc.v:32042.3-32060.6"
+ attribute \src "libresoc.v:32233.3-32251.6"
wire width 7 $0\dec31_dec_sub24_internal_op[6:0]
- attribute \src "libresoc.v:31947.3-31965.6"
+ attribute \src "libresoc.v:32138.3-32156.6"
wire $0\dec31_dec_sub24_inv_a[0:0]
- attribute \src "libresoc.v:31966.3-31984.6"
+ attribute \src "libresoc.v:32157.3-32175.6"
wire $0\dec31_dec_sub24_inv_out[0:0]
- attribute \src "libresoc.v:32080.3-32098.6"
+ attribute \src "libresoc.v:32271.3-32289.6"
wire $0\dec31_dec_sub24_is_32b[0:0]
- attribute \src "libresoc.v:31852.3-31870.6"
+ attribute \src "libresoc.v:32043.3-32061.6"
wire width 4 $0\dec31_dec_sub24_ldst_len[3:0]
- attribute \src "libresoc.v:32118.3-32136.6"
+ attribute \src "libresoc.v:32309.3-32327.6"
wire $0\dec31_dec_sub24_lk[0:0]
- attribute \src "libresoc.v:32232.3-32250.6"
+ attribute \src "libresoc.v:32423.3-32441.6"
wire width 2 $0\dec31_dec_sub24_out_sel[1:0]
- attribute \src "libresoc.v:31890.3-31908.6"
+ attribute \src "libresoc.v:32081.3-32099.6"
wire width 2 $0\dec31_dec_sub24_rc_sel[1:0]
- attribute \src "libresoc.v:32061.3-32079.6"
+ attribute \src "libresoc.v:32252.3-32270.6"
wire $0\dec31_dec_sub24_rsrv[0:0]
- attribute \src "libresoc.v:32137.3-32155.6"
+ attribute \src "libresoc.v:32328.3-32346.6"
wire $0\dec31_dec_sub24_sgl_pipe[0:0]
- attribute \src "libresoc.v:32099.3-32117.6"
+ attribute \src "libresoc.v:32290.3-32308.6"
wire $0\dec31_dec_sub24_sgn[0:0]
- attribute \src "libresoc.v:32023.3-32041.6"
+ attribute \src "libresoc.v:32214.3-32232.6"
wire $0\dec31_dec_sub24_sgn_ext[0:0]
- attribute \src "libresoc.v:31871.3-31889.6"
+ attribute \src "libresoc.v:32062.3-32080.6"
wire width 2 $0\dec31_dec_sub24_upd[1:0]
- attribute \src "libresoc.v:31576.7-31576.20"
+ attribute \src "libresoc.v:31767.7-31767.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:31928.3-31946.6"
+ attribute \src "libresoc.v:32119.3-32137.6"
wire width 8 $1\dec31_dec_sub24_asmcode[7:0]
- attribute \src "libresoc.v:32004.3-32022.6"
+ attribute \src "libresoc.v:32195.3-32213.6"
wire $1\dec31_dec_sub24_br[0:0]
- attribute \src "libresoc.v:32251.3-32269.6"
+ attribute \src "libresoc.v:32442.3-32460.6"
wire width 3 $1\dec31_dec_sub24_cr_in[2:0]
- attribute \src "libresoc.v:32270.3-32288.6"
+ attribute \src "libresoc.v:32461.3-32479.6"
wire width 3 $1\dec31_dec_sub24_cr_out[2:0]
- attribute \src "libresoc.v:31909.3-31927.6"
+ attribute \src "libresoc.v:32100.3-32118.6"
wire width 2 $1\dec31_dec_sub24_cry_in[1:0]
- attribute \src "libresoc.v:31985.3-32003.6"
+ attribute \src "libresoc.v:32176.3-32194.6"
wire $1\dec31_dec_sub24_cry_out[0:0]
- attribute \src "libresoc.v:32156.3-32174.6"
+ attribute \src "libresoc.v:32347.3-32365.6"
wire width 5 $1\dec31_dec_sub24_form[4:0]
- attribute \src "libresoc.v:31833.3-31851.6"
+ attribute \src "libresoc.v:32024.3-32042.6"
wire width 12 $1\dec31_dec_sub24_function_unit[11:0]
- attribute \src "libresoc.v:32175.3-32193.6"
+ attribute \src "libresoc.v:32366.3-32384.6"
wire width 3 $1\dec31_dec_sub24_in1_sel[2:0]
- attribute \src "libresoc.v:32194.3-32212.6"
+ attribute \src "libresoc.v:32385.3-32403.6"
wire width 4 $1\dec31_dec_sub24_in2_sel[3:0]
- attribute \src "libresoc.v:32213.3-32231.6"
+ attribute \src "libresoc.v:32404.3-32422.6"
wire width 2 $1\dec31_dec_sub24_in3_sel[1:0]
- attribute \src "libresoc.v:32042.3-32060.6"
+ attribute \src "libresoc.v:32233.3-32251.6"
wire width 7 $1\dec31_dec_sub24_internal_op[6:0]
- attribute \src "libresoc.v:31947.3-31965.6"
+ attribute \src "libresoc.v:32138.3-32156.6"
wire $1\dec31_dec_sub24_inv_a[0:0]
- attribute \src "libresoc.v:31966.3-31984.6"
+ attribute \src "libresoc.v:32157.3-32175.6"
wire $1\dec31_dec_sub24_inv_out[0:0]
- attribute \src "libresoc.v:32080.3-32098.6"
+ attribute \src "libresoc.v:32271.3-32289.6"
wire $1\dec31_dec_sub24_is_32b[0:0]
- attribute \src "libresoc.v:31852.3-31870.6"
+ attribute \src "libresoc.v:32043.3-32061.6"
wire width 4 $1\dec31_dec_sub24_ldst_len[3:0]
- attribute \src "libresoc.v:32118.3-32136.6"
+ attribute \src "libresoc.v:32309.3-32327.6"
wire $1\dec31_dec_sub24_lk[0:0]
- attribute \src "libresoc.v:32232.3-32250.6"
+ attribute \src "libresoc.v:32423.3-32441.6"
wire width 2 $1\dec31_dec_sub24_out_sel[1:0]
- attribute \src "libresoc.v:31890.3-31908.6"
+ attribute \src "libresoc.v:32081.3-32099.6"
wire width 2 $1\dec31_dec_sub24_rc_sel[1:0]
- attribute \src "libresoc.v:32061.3-32079.6"
+ attribute \src "libresoc.v:32252.3-32270.6"
wire $1\dec31_dec_sub24_rsrv[0:0]
- attribute \src "libresoc.v:32137.3-32155.6"
+ attribute \src "libresoc.v:32328.3-32346.6"
wire $1\dec31_dec_sub24_sgl_pipe[0:0]
- attribute \src "libresoc.v:32099.3-32117.6"
+ attribute \src "libresoc.v:32290.3-32308.6"
wire $1\dec31_dec_sub24_sgn[0:0]
- attribute \src "libresoc.v:32023.3-32041.6"
+ attribute \src "libresoc.v:32214.3-32232.6"
wire $1\dec31_dec_sub24_sgn_ext[0:0]
- attribute \src "libresoc.v:31871.3-31889.6"
+ attribute \src "libresoc.v:32062.3-32080.6"
wire width 2 $1\dec31_dec_sub24_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub24_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub24_upd
- attribute \src "libresoc.v:31576.7-31576.15"
+ attribute \src "libresoc.v:31767.7-31767.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:31576.7-31576.20"
- process $proc$libresoc.v:31576$666
+ attribute \src "libresoc.v:31767.7-31767.20"
+ process $proc$libresoc.v:31767$706
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:31833.3-31851.6"
- process $proc$libresoc.v:31833$642
+ attribute \src "libresoc.v:32024.3-32042.6"
+ process $proc$libresoc.v:32024$682
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0]
- attribute \src "libresoc.v:31834.5-31834.29"
+ attribute \src "libresoc.v:32025.5-32025.29"
switch \initial
- attribute \src "libresoc.v:31834.9-31834.17"
+ attribute \src "libresoc.v:32025.9-32025.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0]
end
- attribute \src "libresoc.v:31852.3-31870.6"
- process $proc$libresoc.v:31852$643
+ attribute \src "libresoc.v:32043.3-32061.6"
+ process $proc$libresoc.v:32043$683
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0]
- attribute \src "libresoc.v:31853.5-31853.29"
+ attribute \src "libresoc.v:32044.5-32044.29"
switch \initial
- attribute \src "libresoc.v:31853.9-31853.17"
+ attribute \src "libresoc.v:32044.9-32044.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0]
end
- attribute \src "libresoc.v:31871.3-31889.6"
- process $proc$libresoc.v:31871$644
+ attribute \src "libresoc.v:32062.3-32080.6"
+ process $proc$libresoc.v:32062$684
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0]
- attribute \src "libresoc.v:31872.5-31872.29"
+ attribute \src "libresoc.v:32063.5-32063.29"
switch \initial
- attribute \src "libresoc.v:31872.9-31872.17"
+ attribute \src "libresoc.v:32063.9-32063.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0]
end
- attribute \src "libresoc.v:31890.3-31908.6"
- process $proc$libresoc.v:31890$645
+ attribute \src "libresoc.v:32081.3-32099.6"
+ process $proc$libresoc.v:32081$685
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0]
- attribute \src "libresoc.v:31891.5-31891.29"
+ attribute \src "libresoc.v:32082.5-32082.29"
switch \initial
- attribute \src "libresoc.v:31891.9-31891.17"
+ attribute \src "libresoc.v:32082.9-32082.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0]
end
- attribute \src "libresoc.v:31909.3-31927.6"
- process $proc$libresoc.v:31909$646
+ attribute \src "libresoc.v:32100.3-32118.6"
+ process $proc$libresoc.v:32100$686
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0]
- attribute \src "libresoc.v:31910.5-31910.29"
+ attribute \src "libresoc.v:32101.5-32101.29"
switch \initial
- attribute \src "libresoc.v:31910.9-31910.17"
+ attribute \src "libresoc.v:32101.9-32101.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0]
end
- attribute \src "libresoc.v:31928.3-31946.6"
- process $proc$libresoc.v:31928$647
+ attribute \src "libresoc.v:32119.3-32137.6"
+ process $proc$libresoc.v:32119$687
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0]
- attribute \src "libresoc.v:31929.5-31929.29"
+ attribute \src "libresoc.v:32120.5-32120.29"
switch \initial
- attribute \src "libresoc.v:31929.9-31929.17"
+ attribute \src "libresoc.v:32120.9-32120.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0]
end
- attribute \src "libresoc.v:31947.3-31965.6"
- process $proc$libresoc.v:31947$648
+ attribute \src "libresoc.v:32138.3-32156.6"
+ process $proc$libresoc.v:32138$688
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0]
- attribute \src "libresoc.v:31948.5-31948.29"
+ attribute \src "libresoc.v:32139.5-32139.29"
switch \initial
- attribute \src "libresoc.v:31948.9-31948.17"
+ attribute \src "libresoc.v:32139.9-32139.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0]
end
- attribute \src "libresoc.v:31966.3-31984.6"
- process $proc$libresoc.v:31966$649
+ attribute \src "libresoc.v:32157.3-32175.6"
+ process $proc$libresoc.v:32157$689
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0]
- attribute \src "libresoc.v:31967.5-31967.29"
+ attribute \src "libresoc.v:32158.5-32158.29"
switch \initial
- attribute \src "libresoc.v:31967.9-31967.17"
+ attribute \src "libresoc.v:32158.9-32158.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0]
end
- attribute \src "libresoc.v:31985.3-32003.6"
- process $proc$libresoc.v:31985$650
+ attribute \src "libresoc.v:32176.3-32194.6"
+ process $proc$libresoc.v:32176$690
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0]
- attribute \src "libresoc.v:31986.5-31986.29"
+ attribute \src "libresoc.v:32177.5-32177.29"
switch \initial
- attribute \src "libresoc.v:31986.9-31986.17"
+ attribute \src "libresoc.v:32177.9-32177.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0]
end
- attribute \src "libresoc.v:32004.3-32022.6"
- process $proc$libresoc.v:32004$651
+ attribute \src "libresoc.v:32195.3-32213.6"
+ process $proc$libresoc.v:32195$691
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0]
- attribute \src "libresoc.v:32005.5-32005.29"
+ attribute \src "libresoc.v:32196.5-32196.29"
switch \initial
- attribute \src "libresoc.v:32005.9-32005.17"
+ attribute \src "libresoc.v:32196.9-32196.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0]
end
- attribute \src "libresoc.v:32023.3-32041.6"
- process $proc$libresoc.v:32023$652
+ attribute \src "libresoc.v:32214.3-32232.6"
+ process $proc$libresoc.v:32214$692
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0]
- attribute \src "libresoc.v:32024.5-32024.29"
+ attribute \src "libresoc.v:32215.5-32215.29"
switch \initial
- attribute \src "libresoc.v:32024.9-32024.17"
+ attribute \src "libresoc.v:32215.9-32215.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0]
end
- attribute \src "libresoc.v:32042.3-32060.6"
- process $proc$libresoc.v:32042$653
+ attribute \src "libresoc.v:32233.3-32251.6"
+ process $proc$libresoc.v:32233$693
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0]
- attribute \src "libresoc.v:32043.5-32043.29"
+ attribute \src "libresoc.v:32234.5-32234.29"
switch \initial
- attribute \src "libresoc.v:32043.9-32043.17"
+ attribute \src "libresoc.v:32234.9-32234.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0]
end
- attribute \src "libresoc.v:32061.3-32079.6"
- process $proc$libresoc.v:32061$654
+ attribute \src "libresoc.v:32252.3-32270.6"
+ process $proc$libresoc.v:32252$694
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0]
- attribute \src "libresoc.v:32062.5-32062.29"
+ attribute \src "libresoc.v:32253.5-32253.29"
switch \initial
- attribute \src "libresoc.v:32062.9-32062.17"
+ attribute \src "libresoc.v:32253.9-32253.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0]
end
- attribute \src "libresoc.v:32080.3-32098.6"
- process $proc$libresoc.v:32080$655
+ attribute \src "libresoc.v:32271.3-32289.6"
+ process $proc$libresoc.v:32271$695
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0]
- attribute \src "libresoc.v:32081.5-32081.29"
+ attribute \src "libresoc.v:32272.5-32272.29"
switch \initial
- attribute \src "libresoc.v:32081.9-32081.17"
+ attribute \src "libresoc.v:32272.9-32272.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0]
end
- attribute \src "libresoc.v:32099.3-32117.6"
- process $proc$libresoc.v:32099$656
+ attribute \src "libresoc.v:32290.3-32308.6"
+ process $proc$libresoc.v:32290$696
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0]
- attribute \src "libresoc.v:32100.5-32100.29"
+ attribute \src "libresoc.v:32291.5-32291.29"
switch \initial
- attribute \src "libresoc.v:32100.9-32100.17"
+ attribute \src "libresoc.v:32291.9-32291.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0]
end
- attribute \src "libresoc.v:32118.3-32136.6"
- process $proc$libresoc.v:32118$657
+ attribute \src "libresoc.v:32309.3-32327.6"
+ process $proc$libresoc.v:32309$697
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0]
- attribute \src "libresoc.v:32119.5-32119.29"
+ attribute \src "libresoc.v:32310.5-32310.29"
switch \initial
- attribute \src "libresoc.v:32119.9-32119.17"
+ attribute \src "libresoc.v:32310.9-32310.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0]
end
- attribute \src "libresoc.v:32137.3-32155.6"
- process $proc$libresoc.v:32137$658
+ attribute \src "libresoc.v:32328.3-32346.6"
+ process $proc$libresoc.v:32328$698
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0]
- attribute \src "libresoc.v:32138.5-32138.29"
+ attribute \src "libresoc.v:32329.5-32329.29"
switch \initial
- attribute \src "libresoc.v:32138.9-32138.17"
+ attribute \src "libresoc.v:32329.9-32329.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:32156.3-32174.6"
- process $proc$libresoc.v:32156$659
+ attribute \src "libresoc.v:32347.3-32365.6"
+ process $proc$libresoc.v:32347$699
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0]
- attribute \src "libresoc.v:32157.5-32157.29"
+ attribute \src "libresoc.v:32348.5-32348.29"
switch \initial
- attribute \src "libresoc.v:32157.9-32157.17"
+ attribute \src "libresoc.v:32348.9-32348.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0]
end
- attribute \src "libresoc.v:32175.3-32193.6"
- process $proc$libresoc.v:32175$660
+ attribute \src "libresoc.v:32366.3-32384.6"
+ process $proc$libresoc.v:32366$700
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0]
- attribute \src "libresoc.v:32176.5-32176.29"
+ attribute \src "libresoc.v:32367.5-32367.29"
switch \initial
- attribute \src "libresoc.v:32176.9-32176.17"
+ attribute \src "libresoc.v:32367.9-32367.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0]
end
- attribute \src "libresoc.v:32194.3-32212.6"
- process $proc$libresoc.v:32194$661
+ attribute \src "libresoc.v:32385.3-32403.6"
+ process $proc$libresoc.v:32385$701
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0]
- attribute \src "libresoc.v:32195.5-32195.29"
+ attribute \src "libresoc.v:32386.5-32386.29"
switch \initial
- attribute \src "libresoc.v:32195.9-32195.17"
+ attribute \src "libresoc.v:32386.9-32386.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0]
end
- attribute \src "libresoc.v:32213.3-32231.6"
- process $proc$libresoc.v:32213$662
+ attribute \src "libresoc.v:32404.3-32422.6"
+ process $proc$libresoc.v:32404$702
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0]
- attribute \src "libresoc.v:32214.5-32214.29"
+ attribute \src "libresoc.v:32405.5-32405.29"
switch \initial
- attribute \src "libresoc.v:32214.9-32214.17"
+ attribute \src "libresoc.v:32405.9-32405.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0]
end
- attribute \src "libresoc.v:32232.3-32250.6"
- process $proc$libresoc.v:32232$663
+ attribute \src "libresoc.v:32423.3-32441.6"
+ process $proc$libresoc.v:32423$703
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0]
- attribute \src "libresoc.v:32233.5-32233.29"
+ attribute \src "libresoc.v:32424.5-32424.29"
switch \initial
- attribute \src "libresoc.v:32233.9-32233.17"
+ attribute \src "libresoc.v:32424.9-32424.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0]
end
- attribute \src "libresoc.v:32251.3-32269.6"
- process $proc$libresoc.v:32251$664
+ attribute \src "libresoc.v:32442.3-32460.6"
+ process $proc$libresoc.v:32442$704
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0]
- attribute \src "libresoc.v:32252.5-32252.29"
+ attribute \src "libresoc.v:32443.5-32443.29"
switch \initial
- attribute \src "libresoc.v:32252.9-32252.17"
+ attribute \src "libresoc.v:32443.9-32443.17"
case 1'1
case
end
sync always
update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0]
end
- attribute \src "libresoc.v:32270.3-32288.6"
- process $proc$libresoc.v:32270$665
+ attribute \src "libresoc.v:32461.3-32479.6"
+ process $proc$libresoc.v:32461$705
assign { } { }
assign { } { }
assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0]
- attribute \src "libresoc.v:32271.5-32271.29"
+ attribute \src "libresoc.v:32462.5-32462.29"
switch \initial
- attribute \src "libresoc.v:32271.9-32271.17"
+ attribute \src "libresoc.v:32462.9-32462.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:32294.1-33801.10"
+attribute \src "libresoc.v:32485.1-33992.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub26"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26"
attribute \generator "nMigen"
module \dec31_dec_sub26
- attribute \src "libresoc.v:32812.3-32863.6"
+ attribute \src "libresoc.v:33003.3-33054.6"
wire width 8 $0\dec31_dec_sub26_asmcode[7:0]
- attribute \src "libresoc.v:33020.3-33071.6"
+ attribute \src "libresoc.v:33211.3-33262.6"
wire $0\dec31_dec_sub26_br[0:0]
- attribute \src "libresoc.v:33696.3-33747.6"
+ attribute \src "libresoc.v:33887.3-33938.6"
wire width 3 $0\dec31_dec_sub26_cr_in[2:0]
- attribute \src "libresoc.v:33748.3-33799.6"
+ attribute \src "libresoc.v:33939.3-33990.6"
wire width 3 $0\dec31_dec_sub26_cr_out[2:0]
- attribute \src "libresoc.v:32760.3-32811.6"
+ attribute \src "libresoc.v:32951.3-33002.6"
wire width 2 $0\dec31_dec_sub26_cry_in[1:0]
- attribute \src "libresoc.v:32968.3-33019.6"
+ attribute \src "libresoc.v:33159.3-33210.6"
wire $0\dec31_dec_sub26_cry_out[0:0]
- attribute \src "libresoc.v:33436.3-33487.6"
+ attribute \src "libresoc.v:33627.3-33678.6"
wire width 5 $0\dec31_dec_sub26_form[4:0]
- attribute \src "libresoc.v:32552.3-32603.6"
+ attribute \src "libresoc.v:32743.3-32794.6"
wire width 12 $0\dec31_dec_sub26_function_unit[11:0]
- attribute \src "libresoc.v:33488.3-33539.6"
+ attribute \src "libresoc.v:33679.3-33730.6"
wire width 3 $0\dec31_dec_sub26_in1_sel[2:0]
- attribute \src "libresoc.v:33540.3-33591.6"
+ attribute \src "libresoc.v:33731.3-33782.6"
wire width 4 $0\dec31_dec_sub26_in2_sel[3:0]
- attribute \src "libresoc.v:33592.3-33643.6"
+ attribute \src "libresoc.v:33783.3-33834.6"
wire width 2 $0\dec31_dec_sub26_in3_sel[1:0]
- attribute \src "libresoc.v:33124.3-33175.6"
+ attribute \src "libresoc.v:33315.3-33366.6"
wire width 7 $0\dec31_dec_sub26_internal_op[6:0]
- attribute \src "libresoc.v:32864.3-32915.6"
+ attribute \src "libresoc.v:33055.3-33106.6"
wire $0\dec31_dec_sub26_inv_a[0:0]
- attribute \src "libresoc.v:32916.3-32967.6"
+ attribute \src "libresoc.v:33107.3-33158.6"
wire $0\dec31_dec_sub26_inv_out[0:0]
- attribute \src "libresoc.v:33228.3-33279.6"
+ attribute \src "libresoc.v:33419.3-33470.6"
wire $0\dec31_dec_sub26_is_32b[0:0]
- attribute \src "libresoc.v:32604.3-32655.6"
+ attribute \src "libresoc.v:32795.3-32846.6"
wire width 4 $0\dec31_dec_sub26_ldst_len[3:0]
- attribute \src "libresoc.v:33332.3-33383.6"
+ attribute \src "libresoc.v:33523.3-33574.6"
wire $0\dec31_dec_sub26_lk[0:0]
- attribute \src "libresoc.v:33644.3-33695.6"
+ attribute \src "libresoc.v:33835.3-33886.6"
wire width 2 $0\dec31_dec_sub26_out_sel[1:0]
- attribute \src "libresoc.v:32708.3-32759.6"
+ attribute \src "libresoc.v:32899.3-32950.6"
wire width 2 $0\dec31_dec_sub26_rc_sel[1:0]
- attribute \src "libresoc.v:33176.3-33227.6"
+ attribute \src "libresoc.v:33367.3-33418.6"
wire $0\dec31_dec_sub26_rsrv[0:0]
- attribute \src "libresoc.v:33384.3-33435.6"
+ attribute \src "libresoc.v:33575.3-33626.6"
wire $0\dec31_dec_sub26_sgl_pipe[0:0]
- attribute \src "libresoc.v:33280.3-33331.6"
+ attribute \src "libresoc.v:33471.3-33522.6"
wire $0\dec31_dec_sub26_sgn[0:0]
- attribute \src "libresoc.v:33072.3-33123.6"
+ attribute \src "libresoc.v:33263.3-33314.6"
wire $0\dec31_dec_sub26_sgn_ext[0:0]
- attribute \src "libresoc.v:32656.3-32707.6"
+ attribute \src "libresoc.v:32847.3-32898.6"
wire width 2 $0\dec31_dec_sub26_upd[1:0]
- attribute \src "libresoc.v:32295.7-32295.20"
+ attribute \src "libresoc.v:32486.7-32486.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:32812.3-32863.6"
+ attribute \src "libresoc.v:33003.3-33054.6"
wire width 8 $1\dec31_dec_sub26_asmcode[7:0]
- attribute \src "libresoc.v:33020.3-33071.6"
+ attribute \src "libresoc.v:33211.3-33262.6"
wire $1\dec31_dec_sub26_br[0:0]
- attribute \src "libresoc.v:33696.3-33747.6"
+ attribute \src "libresoc.v:33887.3-33938.6"
wire width 3 $1\dec31_dec_sub26_cr_in[2:0]
- attribute \src "libresoc.v:33748.3-33799.6"
+ attribute \src "libresoc.v:33939.3-33990.6"
wire width 3 $1\dec31_dec_sub26_cr_out[2:0]
- attribute \src "libresoc.v:32760.3-32811.6"
+ attribute \src "libresoc.v:32951.3-33002.6"
wire width 2 $1\dec31_dec_sub26_cry_in[1:0]
- attribute \src "libresoc.v:32968.3-33019.6"
+ attribute \src "libresoc.v:33159.3-33210.6"
wire $1\dec31_dec_sub26_cry_out[0:0]
- attribute \src "libresoc.v:33436.3-33487.6"
+ attribute \src "libresoc.v:33627.3-33678.6"
wire width 5 $1\dec31_dec_sub26_form[4:0]
- attribute \src "libresoc.v:32552.3-32603.6"
+ attribute \src "libresoc.v:32743.3-32794.6"
wire width 12 $1\dec31_dec_sub26_function_unit[11:0]
- attribute \src "libresoc.v:33488.3-33539.6"
+ attribute \src "libresoc.v:33679.3-33730.6"
wire width 3 $1\dec31_dec_sub26_in1_sel[2:0]
- attribute \src "libresoc.v:33540.3-33591.6"
+ attribute \src "libresoc.v:33731.3-33782.6"
wire width 4 $1\dec31_dec_sub26_in2_sel[3:0]
- attribute \src "libresoc.v:33592.3-33643.6"
+ attribute \src "libresoc.v:33783.3-33834.6"
wire width 2 $1\dec31_dec_sub26_in3_sel[1:0]
- attribute \src "libresoc.v:33124.3-33175.6"
+ attribute \src "libresoc.v:33315.3-33366.6"
wire width 7 $1\dec31_dec_sub26_internal_op[6:0]
- attribute \src "libresoc.v:32864.3-32915.6"
+ attribute \src "libresoc.v:33055.3-33106.6"
wire $1\dec31_dec_sub26_inv_a[0:0]
- attribute \src "libresoc.v:32916.3-32967.6"
+ attribute \src "libresoc.v:33107.3-33158.6"
wire $1\dec31_dec_sub26_inv_out[0:0]
- attribute \src "libresoc.v:33228.3-33279.6"
+ attribute \src "libresoc.v:33419.3-33470.6"
wire $1\dec31_dec_sub26_is_32b[0:0]
- attribute \src "libresoc.v:32604.3-32655.6"
+ attribute \src "libresoc.v:32795.3-32846.6"
wire width 4 $1\dec31_dec_sub26_ldst_len[3:0]
- attribute \src "libresoc.v:33332.3-33383.6"
+ attribute \src "libresoc.v:33523.3-33574.6"
wire $1\dec31_dec_sub26_lk[0:0]
- attribute \src "libresoc.v:33644.3-33695.6"
+ attribute \src "libresoc.v:33835.3-33886.6"
wire width 2 $1\dec31_dec_sub26_out_sel[1:0]
- attribute \src "libresoc.v:32708.3-32759.6"
+ attribute \src "libresoc.v:32899.3-32950.6"
wire width 2 $1\dec31_dec_sub26_rc_sel[1:0]
- attribute \src "libresoc.v:33176.3-33227.6"
+ attribute \src "libresoc.v:33367.3-33418.6"
wire $1\dec31_dec_sub26_rsrv[0:0]
- attribute \src "libresoc.v:33384.3-33435.6"
+ attribute \src "libresoc.v:33575.3-33626.6"
wire $1\dec31_dec_sub26_sgl_pipe[0:0]
- attribute \src "libresoc.v:33280.3-33331.6"
+ attribute \src "libresoc.v:33471.3-33522.6"
wire $1\dec31_dec_sub26_sgn[0:0]
- attribute \src "libresoc.v:33072.3-33123.6"
+ attribute \src "libresoc.v:33263.3-33314.6"
wire $1\dec31_dec_sub26_sgn_ext[0:0]
- attribute \src "libresoc.v:32656.3-32707.6"
+ attribute \src "libresoc.v:32847.3-32898.6"
wire width 2 $1\dec31_dec_sub26_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub26_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub26_upd
- attribute \src "libresoc.v:32295.7-32295.15"
+ attribute \src "libresoc.v:32486.7-32486.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:32295.7-32295.20"
- process $proc$libresoc.v:32295$691
+ attribute \src "libresoc.v:32486.7-32486.20"
+ process $proc$libresoc.v:32486$731
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:32552.3-32603.6"
- process $proc$libresoc.v:32552$667
+ attribute \src "libresoc.v:32743.3-32794.6"
+ process $proc$libresoc.v:32743$707
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0]
- attribute \src "libresoc.v:32553.5-32553.29"
+ attribute \src "libresoc.v:32744.5-32744.29"
switch \initial
- attribute \src "libresoc.v:32553.9-32553.17"
+ attribute \src "libresoc.v:32744.9-32744.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0]
end
- attribute \src "libresoc.v:32604.3-32655.6"
- process $proc$libresoc.v:32604$668
+ attribute \src "libresoc.v:32795.3-32846.6"
+ process $proc$libresoc.v:32795$708
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0]
- attribute \src "libresoc.v:32605.5-32605.29"
+ attribute \src "libresoc.v:32796.5-32796.29"
switch \initial
- attribute \src "libresoc.v:32605.9-32605.17"
+ attribute \src "libresoc.v:32796.9-32796.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0]
end
- attribute \src "libresoc.v:32656.3-32707.6"
- process $proc$libresoc.v:32656$669
+ attribute \src "libresoc.v:32847.3-32898.6"
+ process $proc$libresoc.v:32847$709
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0]
- attribute \src "libresoc.v:32657.5-32657.29"
+ attribute \src "libresoc.v:32848.5-32848.29"
switch \initial
- attribute \src "libresoc.v:32657.9-32657.17"
+ attribute \src "libresoc.v:32848.9-32848.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0]
end
- attribute \src "libresoc.v:32708.3-32759.6"
- process $proc$libresoc.v:32708$670
+ attribute \src "libresoc.v:32899.3-32950.6"
+ process $proc$libresoc.v:32899$710
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0]
- attribute \src "libresoc.v:32709.5-32709.29"
+ attribute \src "libresoc.v:32900.5-32900.29"
switch \initial
- attribute \src "libresoc.v:32709.9-32709.17"
+ attribute \src "libresoc.v:32900.9-32900.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0]
end
- attribute \src "libresoc.v:32760.3-32811.6"
- process $proc$libresoc.v:32760$671
+ attribute \src "libresoc.v:32951.3-33002.6"
+ process $proc$libresoc.v:32951$711
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0]
- attribute \src "libresoc.v:32761.5-32761.29"
+ attribute \src "libresoc.v:32952.5-32952.29"
switch \initial
- attribute \src "libresoc.v:32761.9-32761.17"
+ attribute \src "libresoc.v:32952.9-32952.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0]
end
- attribute \src "libresoc.v:32812.3-32863.6"
- process $proc$libresoc.v:32812$672
+ attribute \src "libresoc.v:33003.3-33054.6"
+ process $proc$libresoc.v:33003$712
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0]
- attribute \src "libresoc.v:32813.5-32813.29"
+ attribute \src "libresoc.v:33004.5-33004.29"
switch \initial
- attribute \src "libresoc.v:32813.9-32813.17"
+ attribute \src "libresoc.v:33004.9-33004.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0]
end
- attribute \src "libresoc.v:32864.3-32915.6"
- process $proc$libresoc.v:32864$673
+ attribute \src "libresoc.v:33055.3-33106.6"
+ process $proc$libresoc.v:33055$713
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0]
- attribute \src "libresoc.v:32865.5-32865.29"
+ attribute \src "libresoc.v:33056.5-33056.29"
switch \initial
- attribute \src "libresoc.v:32865.9-32865.17"
+ attribute \src "libresoc.v:33056.9-33056.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0]
end
- attribute \src "libresoc.v:32916.3-32967.6"
- process $proc$libresoc.v:32916$674
+ attribute \src "libresoc.v:33107.3-33158.6"
+ process $proc$libresoc.v:33107$714
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0]
- attribute \src "libresoc.v:32917.5-32917.29"
+ attribute \src "libresoc.v:33108.5-33108.29"
switch \initial
- attribute \src "libresoc.v:32917.9-32917.17"
+ attribute \src "libresoc.v:33108.9-33108.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0]
end
- attribute \src "libresoc.v:32968.3-33019.6"
- process $proc$libresoc.v:32968$675
+ attribute \src "libresoc.v:33159.3-33210.6"
+ process $proc$libresoc.v:33159$715
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0]
- attribute \src "libresoc.v:32969.5-32969.29"
+ attribute \src "libresoc.v:33160.5-33160.29"
switch \initial
- attribute \src "libresoc.v:32969.9-32969.17"
+ attribute \src "libresoc.v:33160.9-33160.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0]
end
- attribute \src "libresoc.v:33020.3-33071.6"
- process $proc$libresoc.v:33020$676
+ attribute \src "libresoc.v:33211.3-33262.6"
+ process $proc$libresoc.v:33211$716
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0]
- attribute \src "libresoc.v:33021.5-33021.29"
+ attribute \src "libresoc.v:33212.5-33212.29"
switch \initial
- attribute \src "libresoc.v:33021.9-33021.17"
+ attribute \src "libresoc.v:33212.9-33212.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0]
end
- attribute \src "libresoc.v:33072.3-33123.6"
- process $proc$libresoc.v:33072$677
+ attribute \src "libresoc.v:33263.3-33314.6"
+ process $proc$libresoc.v:33263$717
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0]
- attribute \src "libresoc.v:33073.5-33073.29"
+ attribute \src "libresoc.v:33264.5-33264.29"
switch \initial
- attribute \src "libresoc.v:33073.9-33073.17"
+ attribute \src "libresoc.v:33264.9-33264.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0]
end
- attribute \src "libresoc.v:33124.3-33175.6"
- process $proc$libresoc.v:33124$678
+ attribute \src "libresoc.v:33315.3-33366.6"
+ process $proc$libresoc.v:33315$718
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0]
- attribute \src "libresoc.v:33125.5-33125.29"
+ attribute \src "libresoc.v:33316.5-33316.29"
switch \initial
- attribute \src "libresoc.v:33125.9-33125.17"
+ attribute \src "libresoc.v:33316.9-33316.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0]
end
- attribute \src "libresoc.v:33176.3-33227.6"
- process $proc$libresoc.v:33176$679
+ attribute \src "libresoc.v:33367.3-33418.6"
+ process $proc$libresoc.v:33367$719
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0]
- attribute \src "libresoc.v:33177.5-33177.29"
+ attribute \src "libresoc.v:33368.5-33368.29"
switch \initial
- attribute \src "libresoc.v:33177.9-33177.17"
+ attribute \src "libresoc.v:33368.9-33368.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0]
end
- attribute \src "libresoc.v:33228.3-33279.6"
- process $proc$libresoc.v:33228$680
+ attribute \src "libresoc.v:33419.3-33470.6"
+ process $proc$libresoc.v:33419$720
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0]
- attribute \src "libresoc.v:33229.5-33229.29"
+ attribute \src "libresoc.v:33420.5-33420.29"
switch \initial
- attribute \src "libresoc.v:33229.9-33229.17"
+ attribute \src "libresoc.v:33420.9-33420.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0]
end
- attribute \src "libresoc.v:33280.3-33331.6"
- process $proc$libresoc.v:33280$681
+ attribute \src "libresoc.v:33471.3-33522.6"
+ process $proc$libresoc.v:33471$721
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0]
- attribute \src "libresoc.v:33281.5-33281.29"
+ attribute \src "libresoc.v:33472.5-33472.29"
switch \initial
- attribute \src "libresoc.v:33281.9-33281.17"
+ attribute \src "libresoc.v:33472.9-33472.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0]
end
- attribute \src "libresoc.v:33332.3-33383.6"
- process $proc$libresoc.v:33332$682
+ attribute \src "libresoc.v:33523.3-33574.6"
+ process $proc$libresoc.v:33523$722
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0]
- attribute \src "libresoc.v:33333.5-33333.29"
+ attribute \src "libresoc.v:33524.5-33524.29"
switch \initial
- attribute \src "libresoc.v:33333.9-33333.17"
+ attribute \src "libresoc.v:33524.9-33524.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0]
end
- attribute \src "libresoc.v:33384.3-33435.6"
- process $proc$libresoc.v:33384$683
+ attribute \src "libresoc.v:33575.3-33626.6"
+ process $proc$libresoc.v:33575$723
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0]
- attribute \src "libresoc.v:33385.5-33385.29"
+ attribute \src "libresoc.v:33576.5-33576.29"
switch \initial
- attribute \src "libresoc.v:33385.9-33385.17"
+ attribute \src "libresoc.v:33576.9-33576.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:33436.3-33487.6"
- process $proc$libresoc.v:33436$684
+ attribute \src "libresoc.v:33627.3-33678.6"
+ process $proc$libresoc.v:33627$724
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0]
- attribute \src "libresoc.v:33437.5-33437.29"
+ attribute \src "libresoc.v:33628.5-33628.29"
switch \initial
- attribute \src "libresoc.v:33437.9-33437.17"
+ attribute \src "libresoc.v:33628.9-33628.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0]
end
- attribute \src "libresoc.v:33488.3-33539.6"
- process $proc$libresoc.v:33488$685
+ attribute \src "libresoc.v:33679.3-33730.6"
+ process $proc$libresoc.v:33679$725
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0]
- attribute \src "libresoc.v:33489.5-33489.29"
+ attribute \src "libresoc.v:33680.5-33680.29"
switch \initial
- attribute \src "libresoc.v:33489.9-33489.17"
+ attribute \src "libresoc.v:33680.9-33680.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0]
end
- attribute \src "libresoc.v:33540.3-33591.6"
- process $proc$libresoc.v:33540$686
+ attribute \src "libresoc.v:33731.3-33782.6"
+ process $proc$libresoc.v:33731$726
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0]
- attribute \src "libresoc.v:33541.5-33541.29"
+ attribute \src "libresoc.v:33732.5-33732.29"
switch \initial
- attribute \src "libresoc.v:33541.9-33541.17"
+ attribute \src "libresoc.v:33732.9-33732.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0]
end
- attribute \src "libresoc.v:33592.3-33643.6"
- process $proc$libresoc.v:33592$687
+ attribute \src "libresoc.v:33783.3-33834.6"
+ process $proc$libresoc.v:33783$727
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0]
- attribute \src "libresoc.v:33593.5-33593.29"
+ attribute \src "libresoc.v:33784.5-33784.29"
switch \initial
- attribute \src "libresoc.v:33593.9-33593.17"
+ attribute \src "libresoc.v:33784.9-33784.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0]
end
- attribute \src "libresoc.v:33644.3-33695.6"
- process $proc$libresoc.v:33644$688
+ attribute \src "libresoc.v:33835.3-33886.6"
+ process $proc$libresoc.v:33835$728
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0]
- attribute \src "libresoc.v:33645.5-33645.29"
+ attribute \src "libresoc.v:33836.5-33836.29"
switch \initial
- attribute \src "libresoc.v:33645.9-33645.17"
+ attribute \src "libresoc.v:33836.9-33836.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0]
end
- attribute \src "libresoc.v:33696.3-33747.6"
- process $proc$libresoc.v:33696$689
+ attribute \src "libresoc.v:33887.3-33938.6"
+ process $proc$libresoc.v:33887$729
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0]
- attribute \src "libresoc.v:33697.5-33697.29"
+ attribute \src "libresoc.v:33888.5-33888.29"
switch \initial
- attribute \src "libresoc.v:33697.9-33697.17"
+ attribute \src "libresoc.v:33888.9-33888.17"
case 1'1
case
end
sync always
update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0]
end
- attribute \src "libresoc.v:33748.3-33799.6"
- process $proc$libresoc.v:33748$690
+ attribute \src "libresoc.v:33939.3-33990.6"
+ process $proc$libresoc.v:33939$730
assign { } { }
assign { } { }
assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0]
- attribute \src "libresoc.v:33749.5-33749.29"
+ attribute \src "libresoc.v:33940.5-33940.29"
switch \initial
- attribute \src "libresoc.v:33749.9-33749.17"
+ attribute \src "libresoc.v:33940.9-33940.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:33805.1-34520.10"
+attribute \src "libresoc.v:33996.1-34711.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub27"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27"
attribute \generator "nMigen"
module \dec31_dec_sub27
- attribute \src "libresoc.v:34158.3-34176.6"
+ attribute \src "libresoc.v:34349.3-34367.6"
wire width 8 $0\dec31_dec_sub27_asmcode[7:0]
- attribute \src "libresoc.v:34234.3-34252.6"
+ attribute \src "libresoc.v:34425.3-34443.6"
wire $0\dec31_dec_sub27_br[0:0]
- attribute \src "libresoc.v:34481.3-34499.6"
+ attribute \src "libresoc.v:34672.3-34690.6"
wire width 3 $0\dec31_dec_sub27_cr_in[2:0]
- attribute \src "libresoc.v:34500.3-34518.6"
+ attribute \src "libresoc.v:34691.3-34709.6"
wire width 3 $0\dec31_dec_sub27_cr_out[2:0]
- attribute \src "libresoc.v:34139.3-34157.6"
+ attribute \src "libresoc.v:34330.3-34348.6"
wire width 2 $0\dec31_dec_sub27_cry_in[1:0]
- attribute \src "libresoc.v:34215.3-34233.6"
+ attribute \src "libresoc.v:34406.3-34424.6"
wire $0\dec31_dec_sub27_cry_out[0:0]
- attribute \src "libresoc.v:34386.3-34404.6"
+ attribute \src "libresoc.v:34577.3-34595.6"
wire width 5 $0\dec31_dec_sub27_form[4:0]
- attribute \src "libresoc.v:34063.3-34081.6"
+ attribute \src "libresoc.v:34254.3-34272.6"
wire width 12 $0\dec31_dec_sub27_function_unit[11:0]
- attribute \src "libresoc.v:34405.3-34423.6"
+ attribute \src "libresoc.v:34596.3-34614.6"
wire width 3 $0\dec31_dec_sub27_in1_sel[2:0]
- attribute \src "libresoc.v:34424.3-34442.6"
+ attribute \src "libresoc.v:34615.3-34633.6"
wire width 4 $0\dec31_dec_sub27_in2_sel[3:0]
- attribute \src "libresoc.v:34443.3-34461.6"
+ attribute \src "libresoc.v:34634.3-34652.6"
wire width 2 $0\dec31_dec_sub27_in3_sel[1:0]
- attribute \src "libresoc.v:34272.3-34290.6"
+ attribute \src "libresoc.v:34463.3-34481.6"
wire width 7 $0\dec31_dec_sub27_internal_op[6:0]
- attribute \src "libresoc.v:34177.3-34195.6"
+ attribute \src "libresoc.v:34368.3-34386.6"
wire $0\dec31_dec_sub27_inv_a[0:0]
- attribute \src "libresoc.v:34196.3-34214.6"
+ attribute \src "libresoc.v:34387.3-34405.6"
wire $0\dec31_dec_sub27_inv_out[0:0]
- attribute \src "libresoc.v:34310.3-34328.6"
+ attribute \src "libresoc.v:34501.3-34519.6"
wire $0\dec31_dec_sub27_is_32b[0:0]
- attribute \src "libresoc.v:34082.3-34100.6"
+ attribute \src "libresoc.v:34273.3-34291.6"
wire width 4 $0\dec31_dec_sub27_ldst_len[3:0]
- attribute \src "libresoc.v:34348.3-34366.6"
+ attribute \src "libresoc.v:34539.3-34557.6"
wire $0\dec31_dec_sub27_lk[0:0]
- attribute \src "libresoc.v:34462.3-34480.6"
+ attribute \src "libresoc.v:34653.3-34671.6"
wire width 2 $0\dec31_dec_sub27_out_sel[1:0]
- attribute \src "libresoc.v:34120.3-34138.6"
+ attribute \src "libresoc.v:34311.3-34329.6"
wire width 2 $0\dec31_dec_sub27_rc_sel[1:0]
- attribute \src "libresoc.v:34291.3-34309.6"
+ attribute \src "libresoc.v:34482.3-34500.6"
wire $0\dec31_dec_sub27_rsrv[0:0]
- attribute \src "libresoc.v:34367.3-34385.6"
+ attribute \src "libresoc.v:34558.3-34576.6"
wire $0\dec31_dec_sub27_sgl_pipe[0:0]
- attribute \src "libresoc.v:34329.3-34347.6"
+ attribute \src "libresoc.v:34520.3-34538.6"
wire $0\dec31_dec_sub27_sgn[0:0]
- attribute \src "libresoc.v:34253.3-34271.6"
+ attribute \src "libresoc.v:34444.3-34462.6"
wire $0\dec31_dec_sub27_sgn_ext[0:0]
- attribute \src "libresoc.v:34101.3-34119.6"
+ attribute \src "libresoc.v:34292.3-34310.6"
wire width 2 $0\dec31_dec_sub27_upd[1:0]
- attribute \src "libresoc.v:33806.7-33806.20"
+ attribute \src "libresoc.v:33997.7-33997.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:34158.3-34176.6"
+ attribute \src "libresoc.v:34349.3-34367.6"
wire width 8 $1\dec31_dec_sub27_asmcode[7:0]
- attribute \src "libresoc.v:34234.3-34252.6"
+ attribute \src "libresoc.v:34425.3-34443.6"
wire $1\dec31_dec_sub27_br[0:0]
- attribute \src "libresoc.v:34481.3-34499.6"
+ attribute \src "libresoc.v:34672.3-34690.6"
wire width 3 $1\dec31_dec_sub27_cr_in[2:0]
- attribute \src "libresoc.v:34500.3-34518.6"
+ attribute \src "libresoc.v:34691.3-34709.6"
wire width 3 $1\dec31_dec_sub27_cr_out[2:0]
- attribute \src "libresoc.v:34139.3-34157.6"
+ attribute \src "libresoc.v:34330.3-34348.6"
wire width 2 $1\dec31_dec_sub27_cry_in[1:0]
- attribute \src "libresoc.v:34215.3-34233.6"
+ attribute \src "libresoc.v:34406.3-34424.6"
wire $1\dec31_dec_sub27_cry_out[0:0]
- attribute \src "libresoc.v:34386.3-34404.6"
+ attribute \src "libresoc.v:34577.3-34595.6"
wire width 5 $1\dec31_dec_sub27_form[4:0]
- attribute \src "libresoc.v:34063.3-34081.6"
+ attribute \src "libresoc.v:34254.3-34272.6"
wire width 12 $1\dec31_dec_sub27_function_unit[11:0]
- attribute \src "libresoc.v:34405.3-34423.6"
+ attribute \src "libresoc.v:34596.3-34614.6"
wire width 3 $1\dec31_dec_sub27_in1_sel[2:0]
- attribute \src "libresoc.v:34424.3-34442.6"
+ attribute \src "libresoc.v:34615.3-34633.6"
wire width 4 $1\dec31_dec_sub27_in2_sel[3:0]
- attribute \src "libresoc.v:34443.3-34461.6"
+ attribute \src "libresoc.v:34634.3-34652.6"
wire width 2 $1\dec31_dec_sub27_in3_sel[1:0]
- attribute \src "libresoc.v:34272.3-34290.6"
+ attribute \src "libresoc.v:34463.3-34481.6"
wire width 7 $1\dec31_dec_sub27_internal_op[6:0]
- attribute \src "libresoc.v:34177.3-34195.6"
+ attribute \src "libresoc.v:34368.3-34386.6"
wire $1\dec31_dec_sub27_inv_a[0:0]
- attribute \src "libresoc.v:34196.3-34214.6"
+ attribute \src "libresoc.v:34387.3-34405.6"
wire $1\dec31_dec_sub27_inv_out[0:0]
- attribute \src "libresoc.v:34310.3-34328.6"
+ attribute \src "libresoc.v:34501.3-34519.6"
wire $1\dec31_dec_sub27_is_32b[0:0]
- attribute \src "libresoc.v:34082.3-34100.6"
+ attribute \src "libresoc.v:34273.3-34291.6"
wire width 4 $1\dec31_dec_sub27_ldst_len[3:0]
- attribute \src "libresoc.v:34348.3-34366.6"
+ attribute \src "libresoc.v:34539.3-34557.6"
wire $1\dec31_dec_sub27_lk[0:0]
- attribute \src "libresoc.v:34462.3-34480.6"
+ attribute \src "libresoc.v:34653.3-34671.6"
wire width 2 $1\dec31_dec_sub27_out_sel[1:0]
- attribute \src "libresoc.v:34120.3-34138.6"
+ attribute \src "libresoc.v:34311.3-34329.6"
wire width 2 $1\dec31_dec_sub27_rc_sel[1:0]
- attribute \src "libresoc.v:34291.3-34309.6"
+ attribute \src "libresoc.v:34482.3-34500.6"
wire $1\dec31_dec_sub27_rsrv[0:0]
- attribute \src "libresoc.v:34367.3-34385.6"
+ attribute \src "libresoc.v:34558.3-34576.6"
wire $1\dec31_dec_sub27_sgl_pipe[0:0]
- attribute \src "libresoc.v:34329.3-34347.6"
+ attribute \src "libresoc.v:34520.3-34538.6"
wire $1\dec31_dec_sub27_sgn[0:0]
- attribute \src "libresoc.v:34253.3-34271.6"
+ attribute \src "libresoc.v:34444.3-34462.6"
wire $1\dec31_dec_sub27_sgn_ext[0:0]
- attribute \src "libresoc.v:34101.3-34119.6"
+ attribute \src "libresoc.v:34292.3-34310.6"
wire width 2 $1\dec31_dec_sub27_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub27_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub27_upd
- attribute \src "libresoc.v:33806.7-33806.15"
+ attribute \src "libresoc.v:33997.7-33997.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:33806.7-33806.20"
- process $proc$libresoc.v:33806$716
+ attribute \src "libresoc.v:33997.7-33997.20"
+ process $proc$libresoc.v:33997$756
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:34063.3-34081.6"
- process $proc$libresoc.v:34063$692
+ attribute \src "libresoc.v:34254.3-34272.6"
+ process $proc$libresoc.v:34254$732
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0]
- attribute \src "libresoc.v:34064.5-34064.29"
+ attribute \src "libresoc.v:34255.5-34255.29"
switch \initial
- attribute \src "libresoc.v:34064.9-34064.17"
+ attribute \src "libresoc.v:34255.9-34255.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0]
end
- attribute \src "libresoc.v:34082.3-34100.6"
- process $proc$libresoc.v:34082$693
+ attribute \src "libresoc.v:34273.3-34291.6"
+ process $proc$libresoc.v:34273$733
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0]
- attribute \src "libresoc.v:34083.5-34083.29"
+ attribute \src "libresoc.v:34274.5-34274.29"
switch \initial
- attribute \src "libresoc.v:34083.9-34083.17"
+ attribute \src "libresoc.v:34274.9-34274.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0]
end
- attribute \src "libresoc.v:34101.3-34119.6"
- process $proc$libresoc.v:34101$694
+ attribute \src "libresoc.v:34292.3-34310.6"
+ process $proc$libresoc.v:34292$734
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0]
- attribute \src "libresoc.v:34102.5-34102.29"
+ attribute \src "libresoc.v:34293.5-34293.29"
switch \initial
- attribute \src "libresoc.v:34102.9-34102.17"
+ attribute \src "libresoc.v:34293.9-34293.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0]
end
- attribute \src "libresoc.v:34120.3-34138.6"
- process $proc$libresoc.v:34120$695
+ attribute \src "libresoc.v:34311.3-34329.6"
+ process $proc$libresoc.v:34311$735
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0]
- attribute \src "libresoc.v:34121.5-34121.29"
+ attribute \src "libresoc.v:34312.5-34312.29"
switch \initial
- attribute \src "libresoc.v:34121.9-34121.17"
+ attribute \src "libresoc.v:34312.9-34312.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0]
end
- attribute \src "libresoc.v:34139.3-34157.6"
- process $proc$libresoc.v:34139$696
+ attribute \src "libresoc.v:34330.3-34348.6"
+ process $proc$libresoc.v:34330$736
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0]
- attribute \src "libresoc.v:34140.5-34140.29"
+ attribute \src "libresoc.v:34331.5-34331.29"
switch \initial
- attribute \src "libresoc.v:34140.9-34140.17"
+ attribute \src "libresoc.v:34331.9-34331.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0]
end
- attribute \src "libresoc.v:34158.3-34176.6"
- process $proc$libresoc.v:34158$697
+ attribute \src "libresoc.v:34349.3-34367.6"
+ process $proc$libresoc.v:34349$737
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0]
- attribute \src "libresoc.v:34159.5-34159.29"
+ attribute \src "libresoc.v:34350.5-34350.29"
switch \initial
- attribute \src "libresoc.v:34159.9-34159.17"
+ attribute \src "libresoc.v:34350.9-34350.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0]
end
- attribute \src "libresoc.v:34177.3-34195.6"
- process $proc$libresoc.v:34177$698
+ attribute \src "libresoc.v:34368.3-34386.6"
+ process $proc$libresoc.v:34368$738
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0]
- attribute \src "libresoc.v:34178.5-34178.29"
+ attribute \src "libresoc.v:34369.5-34369.29"
switch \initial
- attribute \src "libresoc.v:34178.9-34178.17"
+ attribute \src "libresoc.v:34369.9-34369.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0]
end
- attribute \src "libresoc.v:34196.3-34214.6"
- process $proc$libresoc.v:34196$699
+ attribute \src "libresoc.v:34387.3-34405.6"
+ process $proc$libresoc.v:34387$739
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0]
- attribute \src "libresoc.v:34197.5-34197.29"
+ attribute \src "libresoc.v:34388.5-34388.29"
switch \initial
- attribute \src "libresoc.v:34197.9-34197.17"
+ attribute \src "libresoc.v:34388.9-34388.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0]
end
- attribute \src "libresoc.v:34215.3-34233.6"
- process $proc$libresoc.v:34215$700
+ attribute \src "libresoc.v:34406.3-34424.6"
+ process $proc$libresoc.v:34406$740
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0]
- attribute \src "libresoc.v:34216.5-34216.29"
+ attribute \src "libresoc.v:34407.5-34407.29"
switch \initial
- attribute \src "libresoc.v:34216.9-34216.17"
+ attribute \src "libresoc.v:34407.9-34407.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0]
end
- attribute \src "libresoc.v:34234.3-34252.6"
- process $proc$libresoc.v:34234$701
+ attribute \src "libresoc.v:34425.3-34443.6"
+ process $proc$libresoc.v:34425$741
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0]
- attribute \src "libresoc.v:34235.5-34235.29"
+ attribute \src "libresoc.v:34426.5-34426.29"
switch \initial
- attribute \src "libresoc.v:34235.9-34235.17"
+ attribute \src "libresoc.v:34426.9-34426.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0]
end
- attribute \src "libresoc.v:34253.3-34271.6"
- process $proc$libresoc.v:34253$702
+ attribute \src "libresoc.v:34444.3-34462.6"
+ process $proc$libresoc.v:34444$742
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0]
- attribute \src "libresoc.v:34254.5-34254.29"
+ attribute \src "libresoc.v:34445.5-34445.29"
switch \initial
- attribute \src "libresoc.v:34254.9-34254.17"
+ attribute \src "libresoc.v:34445.9-34445.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0]
end
- attribute \src "libresoc.v:34272.3-34290.6"
- process $proc$libresoc.v:34272$703
+ attribute \src "libresoc.v:34463.3-34481.6"
+ process $proc$libresoc.v:34463$743
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0]
- attribute \src "libresoc.v:34273.5-34273.29"
+ attribute \src "libresoc.v:34464.5-34464.29"
switch \initial
- attribute \src "libresoc.v:34273.9-34273.17"
+ attribute \src "libresoc.v:34464.9-34464.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0]
end
- attribute \src "libresoc.v:34291.3-34309.6"
- process $proc$libresoc.v:34291$704
+ attribute \src "libresoc.v:34482.3-34500.6"
+ process $proc$libresoc.v:34482$744
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0]
- attribute \src "libresoc.v:34292.5-34292.29"
+ attribute \src "libresoc.v:34483.5-34483.29"
switch \initial
- attribute \src "libresoc.v:34292.9-34292.17"
+ attribute \src "libresoc.v:34483.9-34483.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0]
end
- attribute \src "libresoc.v:34310.3-34328.6"
- process $proc$libresoc.v:34310$705
+ attribute \src "libresoc.v:34501.3-34519.6"
+ process $proc$libresoc.v:34501$745
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0]
- attribute \src "libresoc.v:34311.5-34311.29"
+ attribute \src "libresoc.v:34502.5-34502.29"
switch \initial
- attribute \src "libresoc.v:34311.9-34311.17"
+ attribute \src "libresoc.v:34502.9-34502.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0]
end
- attribute \src "libresoc.v:34329.3-34347.6"
- process $proc$libresoc.v:34329$706
+ attribute \src "libresoc.v:34520.3-34538.6"
+ process $proc$libresoc.v:34520$746
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0]
- attribute \src "libresoc.v:34330.5-34330.29"
+ attribute \src "libresoc.v:34521.5-34521.29"
switch \initial
- attribute \src "libresoc.v:34330.9-34330.17"
+ attribute \src "libresoc.v:34521.9-34521.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0]
end
- attribute \src "libresoc.v:34348.3-34366.6"
- process $proc$libresoc.v:34348$707
+ attribute \src "libresoc.v:34539.3-34557.6"
+ process $proc$libresoc.v:34539$747
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0]
- attribute \src "libresoc.v:34349.5-34349.29"
+ attribute \src "libresoc.v:34540.5-34540.29"
switch \initial
- attribute \src "libresoc.v:34349.9-34349.17"
+ attribute \src "libresoc.v:34540.9-34540.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0]
end
- attribute \src "libresoc.v:34367.3-34385.6"
- process $proc$libresoc.v:34367$708
+ attribute \src "libresoc.v:34558.3-34576.6"
+ process $proc$libresoc.v:34558$748
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0]
- attribute \src "libresoc.v:34368.5-34368.29"
+ attribute \src "libresoc.v:34559.5-34559.29"
switch \initial
- attribute \src "libresoc.v:34368.9-34368.17"
+ attribute \src "libresoc.v:34559.9-34559.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:34386.3-34404.6"
- process $proc$libresoc.v:34386$709
+ attribute \src "libresoc.v:34577.3-34595.6"
+ process $proc$libresoc.v:34577$749
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0]
- attribute \src "libresoc.v:34387.5-34387.29"
+ attribute \src "libresoc.v:34578.5-34578.29"
switch \initial
- attribute \src "libresoc.v:34387.9-34387.17"
+ attribute \src "libresoc.v:34578.9-34578.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0]
end
- attribute \src "libresoc.v:34405.3-34423.6"
- process $proc$libresoc.v:34405$710
+ attribute \src "libresoc.v:34596.3-34614.6"
+ process $proc$libresoc.v:34596$750
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0]
- attribute \src "libresoc.v:34406.5-34406.29"
+ attribute \src "libresoc.v:34597.5-34597.29"
switch \initial
- attribute \src "libresoc.v:34406.9-34406.17"
+ attribute \src "libresoc.v:34597.9-34597.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0]
end
- attribute \src "libresoc.v:34424.3-34442.6"
- process $proc$libresoc.v:34424$711
+ attribute \src "libresoc.v:34615.3-34633.6"
+ process $proc$libresoc.v:34615$751
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0]
- attribute \src "libresoc.v:34425.5-34425.29"
+ attribute \src "libresoc.v:34616.5-34616.29"
switch \initial
- attribute \src "libresoc.v:34425.9-34425.17"
+ attribute \src "libresoc.v:34616.9-34616.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0]
end
- attribute \src "libresoc.v:34443.3-34461.6"
- process $proc$libresoc.v:34443$712
+ attribute \src "libresoc.v:34634.3-34652.6"
+ process $proc$libresoc.v:34634$752
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0]
- attribute \src "libresoc.v:34444.5-34444.29"
+ attribute \src "libresoc.v:34635.5-34635.29"
switch \initial
- attribute \src "libresoc.v:34444.9-34444.17"
+ attribute \src "libresoc.v:34635.9-34635.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0]
end
- attribute \src "libresoc.v:34462.3-34480.6"
- process $proc$libresoc.v:34462$713
+ attribute \src "libresoc.v:34653.3-34671.6"
+ process $proc$libresoc.v:34653$753
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0]
- attribute \src "libresoc.v:34463.5-34463.29"
+ attribute \src "libresoc.v:34654.5-34654.29"
switch \initial
- attribute \src "libresoc.v:34463.9-34463.17"
+ attribute \src "libresoc.v:34654.9-34654.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0]
end
- attribute \src "libresoc.v:34481.3-34499.6"
- process $proc$libresoc.v:34481$714
+ attribute \src "libresoc.v:34672.3-34690.6"
+ process $proc$libresoc.v:34672$754
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0]
- attribute \src "libresoc.v:34482.5-34482.29"
+ attribute \src "libresoc.v:34673.5-34673.29"
switch \initial
- attribute \src "libresoc.v:34482.9-34482.17"
+ attribute \src "libresoc.v:34673.9-34673.17"
case 1'1
case
end
sync always
update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0]
end
- attribute \src "libresoc.v:34500.3-34518.6"
- process $proc$libresoc.v:34500$715
+ attribute \src "libresoc.v:34691.3-34709.6"
+ process $proc$libresoc.v:34691$755
assign { } { }
assign { } { }
assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0]
- attribute \src "libresoc.v:34501.5-34501.29"
+ attribute \src "libresoc.v:34692.5-34692.29"
switch \initial
- attribute \src "libresoc.v:34501.9-34501.17"
+ attribute \src "libresoc.v:34692.9-34692.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:34524.1-35671.10"
+attribute \src "libresoc.v:34715.1-35862.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub28"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28"
attribute \generator "nMigen"
module \dec31_dec_sub28
- attribute \src "libresoc.v:34967.3-35003.6"
+ attribute \src "libresoc.v:35158.3-35194.6"
wire width 8 $0\dec31_dec_sub28_asmcode[7:0]
- attribute \src "libresoc.v:35115.3-35151.6"
+ attribute \src "libresoc.v:35306.3-35342.6"
wire $0\dec31_dec_sub28_br[0:0]
- attribute \src "libresoc.v:35596.3-35632.6"
+ attribute \src "libresoc.v:35787.3-35823.6"
wire width 3 $0\dec31_dec_sub28_cr_in[2:0]
- attribute \src "libresoc.v:35633.3-35669.6"
+ attribute \src "libresoc.v:35824.3-35860.6"
wire width 3 $0\dec31_dec_sub28_cr_out[2:0]
- attribute \src "libresoc.v:34930.3-34966.6"
+ attribute \src "libresoc.v:35121.3-35157.6"
wire width 2 $0\dec31_dec_sub28_cry_in[1:0]
- attribute \src "libresoc.v:35078.3-35114.6"
+ attribute \src "libresoc.v:35269.3-35305.6"
wire $0\dec31_dec_sub28_cry_out[0:0]
- attribute \src "libresoc.v:35411.3-35447.6"
+ attribute \src "libresoc.v:35602.3-35638.6"
wire width 5 $0\dec31_dec_sub28_form[4:0]
- attribute \src "libresoc.v:34782.3-34818.6"
+ attribute \src "libresoc.v:34973.3-35009.6"
wire width 12 $0\dec31_dec_sub28_function_unit[11:0]
- attribute \src "libresoc.v:35448.3-35484.6"
+ attribute \src "libresoc.v:35639.3-35675.6"
wire width 3 $0\dec31_dec_sub28_in1_sel[2:0]
- attribute \src "libresoc.v:35485.3-35521.6"
+ attribute \src "libresoc.v:35676.3-35712.6"
wire width 4 $0\dec31_dec_sub28_in2_sel[3:0]
- attribute \src "libresoc.v:35522.3-35558.6"
+ attribute \src "libresoc.v:35713.3-35749.6"
wire width 2 $0\dec31_dec_sub28_in3_sel[1:0]
- attribute \src "libresoc.v:35189.3-35225.6"
+ attribute \src "libresoc.v:35380.3-35416.6"
wire width 7 $0\dec31_dec_sub28_internal_op[6:0]
- attribute \src "libresoc.v:35004.3-35040.6"
+ attribute \src "libresoc.v:35195.3-35231.6"
wire $0\dec31_dec_sub28_inv_a[0:0]
- attribute \src "libresoc.v:35041.3-35077.6"
+ attribute \src "libresoc.v:35232.3-35268.6"
wire $0\dec31_dec_sub28_inv_out[0:0]
- attribute \src "libresoc.v:35263.3-35299.6"
+ attribute \src "libresoc.v:35454.3-35490.6"
wire $0\dec31_dec_sub28_is_32b[0:0]
- attribute \src "libresoc.v:34819.3-34855.6"
+ attribute \src "libresoc.v:35010.3-35046.6"
wire width 4 $0\dec31_dec_sub28_ldst_len[3:0]
- attribute \src "libresoc.v:35337.3-35373.6"
+ attribute \src "libresoc.v:35528.3-35564.6"
wire $0\dec31_dec_sub28_lk[0:0]
- attribute \src "libresoc.v:35559.3-35595.6"
+ attribute \src "libresoc.v:35750.3-35786.6"
wire width 2 $0\dec31_dec_sub28_out_sel[1:0]
- attribute \src "libresoc.v:34893.3-34929.6"
+ attribute \src "libresoc.v:35084.3-35120.6"
wire width 2 $0\dec31_dec_sub28_rc_sel[1:0]
- attribute \src "libresoc.v:35226.3-35262.6"
+ attribute \src "libresoc.v:35417.3-35453.6"
wire $0\dec31_dec_sub28_rsrv[0:0]
- attribute \src "libresoc.v:35374.3-35410.6"
+ attribute \src "libresoc.v:35565.3-35601.6"
wire $0\dec31_dec_sub28_sgl_pipe[0:0]
- attribute \src "libresoc.v:35300.3-35336.6"
+ attribute \src "libresoc.v:35491.3-35527.6"
wire $0\dec31_dec_sub28_sgn[0:0]
- attribute \src "libresoc.v:35152.3-35188.6"
+ attribute \src "libresoc.v:35343.3-35379.6"
wire $0\dec31_dec_sub28_sgn_ext[0:0]
- attribute \src "libresoc.v:34856.3-34892.6"
+ attribute \src "libresoc.v:35047.3-35083.6"
wire width 2 $0\dec31_dec_sub28_upd[1:0]
- attribute \src "libresoc.v:34525.7-34525.20"
+ attribute \src "libresoc.v:34716.7-34716.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:34967.3-35003.6"
+ attribute \src "libresoc.v:35158.3-35194.6"
wire width 8 $1\dec31_dec_sub28_asmcode[7:0]
- attribute \src "libresoc.v:35115.3-35151.6"
+ attribute \src "libresoc.v:35306.3-35342.6"
wire $1\dec31_dec_sub28_br[0:0]
- attribute \src "libresoc.v:35596.3-35632.6"
+ attribute \src "libresoc.v:35787.3-35823.6"
wire width 3 $1\dec31_dec_sub28_cr_in[2:0]
- attribute \src "libresoc.v:35633.3-35669.6"
+ attribute \src "libresoc.v:35824.3-35860.6"
wire width 3 $1\dec31_dec_sub28_cr_out[2:0]
- attribute \src "libresoc.v:34930.3-34966.6"
+ attribute \src "libresoc.v:35121.3-35157.6"
wire width 2 $1\dec31_dec_sub28_cry_in[1:0]
- attribute \src "libresoc.v:35078.3-35114.6"
+ attribute \src "libresoc.v:35269.3-35305.6"
wire $1\dec31_dec_sub28_cry_out[0:0]
- attribute \src "libresoc.v:35411.3-35447.6"
+ attribute \src "libresoc.v:35602.3-35638.6"
wire width 5 $1\dec31_dec_sub28_form[4:0]
- attribute \src "libresoc.v:34782.3-34818.6"
+ attribute \src "libresoc.v:34973.3-35009.6"
wire width 12 $1\dec31_dec_sub28_function_unit[11:0]
- attribute \src "libresoc.v:35448.3-35484.6"
+ attribute \src "libresoc.v:35639.3-35675.6"
wire width 3 $1\dec31_dec_sub28_in1_sel[2:0]
- attribute \src "libresoc.v:35485.3-35521.6"
+ attribute \src "libresoc.v:35676.3-35712.6"
wire width 4 $1\dec31_dec_sub28_in2_sel[3:0]
- attribute \src "libresoc.v:35522.3-35558.6"
+ attribute \src "libresoc.v:35713.3-35749.6"
wire width 2 $1\dec31_dec_sub28_in3_sel[1:0]
- attribute \src "libresoc.v:35189.3-35225.6"
+ attribute \src "libresoc.v:35380.3-35416.6"
wire width 7 $1\dec31_dec_sub28_internal_op[6:0]
- attribute \src "libresoc.v:35004.3-35040.6"
+ attribute \src "libresoc.v:35195.3-35231.6"
wire $1\dec31_dec_sub28_inv_a[0:0]
- attribute \src "libresoc.v:35041.3-35077.6"
+ attribute \src "libresoc.v:35232.3-35268.6"
wire $1\dec31_dec_sub28_inv_out[0:0]
- attribute \src "libresoc.v:35263.3-35299.6"
+ attribute \src "libresoc.v:35454.3-35490.6"
wire $1\dec31_dec_sub28_is_32b[0:0]
- attribute \src "libresoc.v:34819.3-34855.6"
+ attribute \src "libresoc.v:35010.3-35046.6"
wire width 4 $1\dec31_dec_sub28_ldst_len[3:0]
- attribute \src "libresoc.v:35337.3-35373.6"
+ attribute \src "libresoc.v:35528.3-35564.6"
wire $1\dec31_dec_sub28_lk[0:0]
- attribute \src "libresoc.v:35559.3-35595.6"
+ attribute \src "libresoc.v:35750.3-35786.6"
wire width 2 $1\dec31_dec_sub28_out_sel[1:0]
- attribute \src "libresoc.v:34893.3-34929.6"
+ attribute \src "libresoc.v:35084.3-35120.6"
wire width 2 $1\dec31_dec_sub28_rc_sel[1:0]
- attribute \src "libresoc.v:35226.3-35262.6"
+ attribute \src "libresoc.v:35417.3-35453.6"
wire $1\dec31_dec_sub28_rsrv[0:0]
- attribute \src "libresoc.v:35374.3-35410.6"
+ attribute \src "libresoc.v:35565.3-35601.6"
wire $1\dec31_dec_sub28_sgl_pipe[0:0]
- attribute \src "libresoc.v:35300.3-35336.6"
+ attribute \src "libresoc.v:35491.3-35527.6"
wire $1\dec31_dec_sub28_sgn[0:0]
- attribute \src "libresoc.v:35152.3-35188.6"
+ attribute \src "libresoc.v:35343.3-35379.6"
wire $1\dec31_dec_sub28_sgn_ext[0:0]
- attribute \src "libresoc.v:34856.3-34892.6"
+ attribute \src "libresoc.v:35047.3-35083.6"
wire width 2 $1\dec31_dec_sub28_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub28_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub28_upd
- attribute \src "libresoc.v:34525.7-34525.15"
+ attribute \src "libresoc.v:34716.7-34716.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:34525.7-34525.20"
- process $proc$libresoc.v:34525$741
+ attribute \src "libresoc.v:34716.7-34716.20"
+ process $proc$libresoc.v:34716$781
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:34782.3-34818.6"
- process $proc$libresoc.v:34782$717
+ attribute \src "libresoc.v:34973.3-35009.6"
+ process $proc$libresoc.v:34973$757
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0]
- attribute \src "libresoc.v:34783.5-34783.29"
+ attribute \src "libresoc.v:34974.5-34974.29"
switch \initial
- attribute \src "libresoc.v:34783.9-34783.17"
+ attribute \src "libresoc.v:34974.9-34974.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0]
end
- attribute \src "libresoc.v:34819.3-34855.6"
- process $proc$libresoc.v:34819$718
+ attribute \src "libresoc.v:35010.3-35046.6"
+ process $proc$libresoc.v:35010$758
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0]
- attribute \src "libresoc.v:34820.5-34820.29"
+ attribute \src "libresoc.v:35011.5-35011.29"
switch \initial
- attribute \src "libresoc.v:34820.9-34820.17"
+ attribute \src "libresoc.v:35011.9-35011.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0]
end
- attribute \src "libresoc.v:34856.3-34892.6"
- process $proc$libresoc.v:34856$719
+ attribute \src "libresoc.v:35047.3-35083.6"
+ process $proc$libresoc.v:35047$759
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0]
- attribute \src "libresoc.v:34857.5-34857.29"
+ attribute \src "libresoc.v:35048.5-35048.29"
switch \initial
- attribute \src "libresoc.v:34857.9-34857.17"
+ attribute \src "libresoc.v:35048.9-35048.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0]
end
- attribute \src "libresoc.v:34893.3-34929.6"
- process $proc$libresoc.v:34893$720
+ attribute \src "libresoc.v:35084.3-35120.6"
+ process $proc$libresoc.v:35084$760
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0]
- attribute \src "libresoc.v:34894.5-34894.29"
+ attribute \src "libresoc.v:35085.5-35085.29"
switch \initial
- attribute \src "libresoc.v:34894.9-34894.17"
+ attribute \src "libresoc.v:35085.9-35085.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0]
end
- attribute \src "libresoc.v:34930.3-34966.6"
- process $proc$libresoc.v:34930$721
+ attribute \src "libresoc.v:35121.3-35157.6"
+ process $proc$libresoc.v:35121$761
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0]
- attribute \src "libresoc.v:34931.5-34931.29"
+ attribute \src "libresoc.v:35122.5-35122.29"
switch \initial
- attribute \src "libresoc.v:34931.9-34931.17"
+ attribute \src "libresoc.v:35122.9-35122.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0]
end
- attribute \src "libresoc.v:34967.3-35003.6"
- process $proc$libresoc.v:34967$722
+ attribute \src "libresoc.v:35158.3-35194.6"
+ process $proc$libresoc.v:35158$762
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0]
- attribute \src "libresoc.v:34968.5-34968.29"
+ attribute \src "libresoc.v:35159.5-35159.29"
switch \initial
- attribute \src "libresoc.v:34968.9-34968.17"
+ attribute \src "libresoc.v:35159.9-35159.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0]
end
- attribute \src "libresoc.v:35004.3-35040.6"
- process $proc$libresoc.v:35004$723
+ attribute \src "libresoc.v:35195.3-35231.6"
+ process $proc$libresoc.v:35195$763
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0]
- attribute \src "libresoc.v:35005.5-35005.29"
+ attribute \src "libresoc.v:35196.5-35196.29"
switch \initial
- attribute \src "libresoc.v:35005.9-35005.17"
+ attribute \src "libresoc.v:35196.9-35196.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0]
end
- attribute \src "libresoc.v:35041.3-35077.6"
- process $proc$libresoc.v:35041$724
+ attribute \src "libresoc.v:35232.3-35268.6"
+ process $proc$libresoc.v:35232$764
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0]
- attribute \src "libresoc.v:35042.5-35042.29"
+ attribute \src "libresoc.v:35233.5-35233.29"
switch \initial
- attribute \src "libresoc.v:35042.9-35042.17"
+ attribute \src "libresoc.v:35233.9-35233.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0]
end
- attribute \src "libresoc.v:35078.3-35114.6"
- process $proc$libresoc.v:35078$725
+ attribute \src "libresoc.v:35269.3-35305.6"
+ process $proc$libresoc.v:35269$765
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0]
- attribute \src "libresoc.v:35079.5-35079.29"
+ attribute \src "libresoc.v:35270.5-35270.29"
switch \initial
- attribute \src "libresoc.v:35079.9-35079.17"
+ attribute \src "libresoc.v:35270.9-35270.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0]
end
- attribute \src "libresoc.v:35115.3-35151.6"
- process $proc$libresoc.v:35115$726
+ attribute \src "libresoc.v:35306.3-35342.6"
+ process $proc$libresoc.v:35306$766
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0]
- attribute \src "libresoc.v:35116.5-35116.29"
+ attribute \src "libresoc.v:35307.5-35307.29"
switch \initial
- attribute \src "libresoc.v:35116.9-35116.17"
+ attribute \src "libresoc.v:35307.9-35307.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0]
end
- attribute \src "libresoc.v:35152.3-35188.6"
- process $proc$libresoc.v:35152$727
+ attribute \src "libresoc.v:35343.3-35379.6"
+ process $proc$libresoc.v:35343$767
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0]
- attribute \src "libresoc.v:35153.5-35153.29"
+ attribute \src "libresoc.v:35344.5-35344.29"
switch \initial
- attribute \src "libresoc.v:35153.9-35153.17"
+ attribute \src "libresoc.v:35344.9-35344.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0]
end
- attribute \src "libresoc.v:35189.3-35225.6"
- process $proc$libresoc.v:35189$728
+ attribute \src "libresoc.v:35380.3-35416.6"
+ process $proc$libresoc.v:35380$768
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0]
- attribute \src "libresoc.v:35190.5-35190.29"
+ attribute \src "libresoc.v:35381.5-35381.29"
switch \initial
- attribute \src "libresoc.v:35190.9-35190.17"
+ attribute \src "libresoc.v:35381.9-35381.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0]
end
- attribute \src "libresoc.v:35226.3-35262.6"
- process $proc$libresoc.v:35226$729
+ attribute \src "libresoc.v:35417.3-35453.6"
+ process $proc$libresoc.v:35417$769
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0]
- attribute \src "libresoc.v:35227.5-35227.29"
+ attribute \src "libresoc.v:35418.5-35418.29"
switch \initial
- attribute \src "libresoc.v:35227.9-35227.17"
+ attribute \src "libresoc.v:35418.9-35418.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0]
end
- attribute \src "libresoc.v:35263.3-35299.6"
- process $proc$libresoc.v:35263$730
+ attribute \src "libresoc.v:35454.3-35490.6"
+ process $proc$libresoc.v:35454$770
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0]
- attribute \src "libresoc.v:35264.5-35264.29"
+ attribute \src "libresoc.v:35455.5-35455.29"
switch \initial
- attribute \src "libresoc.v:35264.9-35264.17"
+ attribute \src "libresoc.v:35455.9-35455.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0]
end
- attribute \src "libresoc.v:35300.3-35336.6"
- process $proc$libresoc.v:35300$731
+ attribute \src "libresoc.v:35491.3-35527.6"
+ process $proc$libresoc.v:35491$771
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0]
- attribute \src "libresoc.v:35301.5-35301.29"
+ attribute \src "libresoc.v:35492.5-35492.29"
switch \initial
- attribute \src "libresoc.v:35301.9-35301.17"
+ attribute \src "libresoc.v:35492.9-35492.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0]
end
- attribute \src "libresoc.v:35337.3-35373.6"
- process $proc$libresoc.v:35337$732
+ attribute \src "libresoc.v:35528.3-35564.6"
+ process $proc$libresoc.v:35528$772
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0]
- attribute \src "libresoc.v:35338.5-35338.29"
+ attribute \src "libresoc.v:35529.5-35529.29"
switch \initial
- attribute \src "libresoc.v:35338.9-35338.17"
+ attribute \src "libresoc.v:35529.9-35529.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0]
end
- attribute \src "libresoc.v:35374.3-35410.6"
- process $proc$libresoc.v:35374$733
+ attribute \src "libresoc.v:35565.3-35601.6"
+ process $proc$libresoc.v:35565$773
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0]
- attribute \src "libresoc.v:35375.5-35375.29"
+ attribute \src "libresoc.v:35566.5-35566.29"
switch \initial
- attribute \src "libresoc.v:35375.9-35375.17"
+ attribute \src "libresoc.v:35566.9-35566.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:35411.3-35447.6"
- process $proc$libresoc.v:35411$734
+ attribute \src "libresoc.v:35602.3-35638.6"
+ process $proc$libresoc.v:35602$774
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0]
- attribute \src "libresoc.v:35412.5-35412.29"
+ attribute \src "libresoc.v:35603.5-35603.29"
switch \initial
- attribute \src "libresoc.v:35412.9-35412.17"
+ attribute \src "libresoc.v:35603.9-35603.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0]
end
- attribute \src "libresoc.v:35448.3-35484.6"
- process $proc$libresoc.v:35448$735
+ attribute \src "libresoc.v:35639.3-35675.6"
+ process $proc$libresoc.v:35639$775
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0]
- attribute \src "libresoc.v:35449.5-35449.29"
+ attribute \src "libresoc.v:35640.5-35640.29"
switch \initial
- attribute \src "libresoc.v:35449.9-35449.17"
+ attribute \src "libresoc.v:35640.9-35640.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0]
end
- attribute \src "libresoc.v:35485.3-35521.6"
- process $proc$libresoc.v:35485$736
+ attribute \src "libresoc.v:35676.3-35712.6"
+ process $proc$libresoc.v:35676$776
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0]
- attribute \src "libresoc.v:35486.5-35486.29"
+ attribute \src "libresoc.v:35677.5-35677.29"
switch \initial
- attribute \src "libresoc.v:35486.9-35486.17"
+ attribute \src "libresoc.v:35677.9-35677.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0]
end
- attribute \src "libresoc.v:35522.3-35558.6"
- process $proc$libresoc.v:35522$737
+ attribute \src "libresoc.v:35713.3-35749.6"
+ process $proc$libresoc.v:35713$777
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0]
- attribute \src "libresoc.v:35523.5-35523.29"
+ attribute \src "libresoc.v:35714.5-35714.29"
switch \initial
- attribute \src "libresoc.v:35523.9-35523.17"
+ attribute \src "libresoc.v:35714.9-35714.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0]
end
- attribute \src "libresoc.v:35559.3-35595.6"
- process $proc$libresoc.v:35559$738
+ attribute \src "libresoc.v:35750.3-35786.6"
+ process $proc$libresoc.v:35750$778
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0]
- attribute \src "libresoc.v:35560.5-35560.29"
+ attribute \src "libresoc.v:35751.5-35751.29"
switch \initial
- attribute \src "libresoc.v:35560.9-35560.17"
+ attribute \src "libresoc.v:35751.9-35751.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0]
end
- attribute \src "libresoc.v:35596.3-35632.6"
- process $proc$libresoc.v:35596$739
+ attribute \src "libresoc.v:35787.3-35823.6"
+ process $proc$libresoc.v:35787$779
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0]
- attribute \src "libresoc.v:35597.5-35597.29"
+ attribute \src "libresoc.v:35788.5-35788.29"
switch \initial
- attribute \src "libresoc.v:35597.9-35597.17"
+ attribute \src "libresoc.v:35788.9-35788.17"
case 1'1
case
end
sync always
update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0]
end
- attribute \src "libresoc.v:35633.3-35669.6"
- process $proc$libresoc.v:35633$740
+ attribute \src "libresoc.v:35824.3-35860.6"
+ process $proc$libresoc.v:35824$780
assign { } { }
assign { } { }
assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0]
- attribute \src "libresoc.v:35634.5-35634.29"
+ attribute \src "libresoc.v:35825.5-35825.29"
switch \initial
- attribute \src "libresoc.v:35634.9-35634.17"
+ attribute \src "libresoc.v:35825.9-35825.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:35675.1-36246.10"
+attribute \src "libresoc.v:35866.1-36437.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub4"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4"
attribute \generator "nMigen"
module \dec31_dec_sub4
- attribute \src "libresoc.v:35998.3-36010.6"
+ attribute \src "libresoc.v:36189.3-36201.6"
wire width 8 $0\dec31_dec_sub4_asmcode[7:0]
- attribute \src "libresoc.v:36050.3-36062.6"
+ attribute \src "libresoc.v:36241.3-36253.6"
wire $0\dec31_dec_sub4_br[0:0]
- attribute \src "libresoc.v:36219.3-36231.6"
+ attribute \src "libresoc.v:36410.3-36422.6"
wire width 3 $0\dec31_dec_sub4_cr_in[2:0]
- attribute \src "libresoc.v:36232.3-36244.6"
+ attribute \src "libresoc.v:36423.3-36435.6"
wire width 3 $0\dec31_dec_sub4_cr_out[2:0]
- attribute \src "libresoc.v:35985.3-35997.6"
+ attribute \src "libresoc.v:36176.3-36188.6"
wire width 2 $0\dec31_dec_sub4_cry_in[1:0]
- attribute \src "libresoc.v:36037.3-36049.6"
+ attribute \src "libresoc.v:36228.3-36240.6"
wire $0\dec31_dec_sub4_cry_out[0:0]
- attribute \src "libresoc.v:36154.3-36166.6"
+ attribute \src "libresoc.v:36345.3-36357.6"
wire width 5 $0\dec31_dec_sub4_form[4:0]
- attribute \src "libresoc.v:35933.3-35945.6"
+ attribute \src "libresoc.v:36124.3-36136.6"
wire width 12 $0\dec31_dec_sub4_function_unit[11:0]
- attribute \src "libresoc.v:36167.3-36179.6"
+ attribute \src "libresoc.v:36358.3-36370.6"
wire width 3 $0\dec31_dec_sub4_in1_sel[2:0]
- attribute \src "libresoc.v:36180.3-36192.6"
+ attribute \src "libresoc.v:36371.3-36383.6"
wire width 4 $0\dec31_dec_sub4_in2_sel[3:0]
- attribute \src "libresoc.v:36193.3-36205.6"
+ attribute \src "libresoc.v:36384.3-36396.6"
wire width 2 $0\dec31_dec_sub4_in3_sel[1:0]
- attribute \src "libresoc.v:36076.3-36088.6"
+ attribute \src "libresoc.v:36267.3-36279.6"
wire width 7 $0\dec31_dec_sub4_internal_op[6:0]
- attribute \src "libresoc.v:36011.3-36023.6"
+ attribute \src "libresoc.v:36202.3-36214.6"
wire $0\dec31_dec_sub4_inv_a[0:0]
- attribute \src "libresoc.v:36024.3-36036.6"
+ attribute \src "libresoc.v:36215.3-36227.6"
wire $0\dec31_dec_sub4_inv_out[0:0]
- attribute \src "libresoc.v:36102.3-36114.6"
+ attribute \src "libresoc.v:36293.3-36305.6"
wire $0\dec31_dec_sub4_is_32b[0:0]
- attribute \src "libresoc.v:35946.3-35958.6"
+ attribute \src "libresoc.v:36137.3-36149.6"
wire width 4 $0\dec31_dec_sub4_ldst_len[3:0]
- attribute \src "libresoc.v:36128.3-36140.6"
+ attribute \src "libresoc.v:36319.3-36331.6"
wire $0\dec31_dec_sub4_lk[0:0]
- attribute \src "libresoc.v:36206.3-36218.6"
+ attribute \src "libresoc.v:36397.3-36409.6"
wire width 2 $0\dec31_dec_sub4_out_sel[1:0]
- attribute \src "libresoc.v:35972.3-35984.6"
+ attribute \src "libresoc.v:36163.3-36175.6"
wire width 2 $0\dec31_dec_sub4_rc_sel[1:0]
- attribute \src "libresoc.v:36089.3-36101.6"
+ attribute \src "libresoc.v:36280.3-36292.6"
wire $0\dec31_dec_sub4_rsrv[0:0]
- attribute \src "libresoc.v:36141.3-36153.6"
+ attribute \src "libresoc.v:36332.3-36344.6"
wire $0\dec31_dec_sub4_sgl_pipe[0:0]
- attribute \src "libresoc.v:36115.3-36127.6"
+ attribute \src "libresoc.v:36306.3-36318.6"
wire $0\dec31_dec_sub4_sgn[0:0]
- attribute \src "libresoc.v:36063.3-36075.6"
+ attribute \src "libresoc.v:36254.3-36266.6"
wire $0\dec31_dec_sub4_sgn_ext[0:0]
- attribute \src "libresoc.v:35959.3-35971.6"
+ attribute \src "libresoc.v:36150.3-36162.6"
wire width 2 $0\dec31_dec_sub4_upd[1:0]
- attribute \src "libresoc.v:35676.7-35676.20"
+ attribute \src "libresoc.v:35867.7-35867.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:35998.3-36010.6"
+ attribute \src "libresoc.v:36189.3-36201.6"
wire width 8 $1\dec31_dec_sub4_asmcode[7:0]
- attribute \src "libresoc.v:36050.3-36062.6"
+ attribute \src "libresoc.v:36241.3-36253.6"
wire $1\dec31_dec_sub4_br[0:0]
- attribute \src "libresoc.v:36219.3-36231.6"
+ attribute \src "libresoc.v:36410.3-36422.6"
wire width 3 $1\dec31_dec_sub4_cr_in[2:0]
- attribute \src "libresoc.v:36232.3-36244.6"
+ attribute \src "libresoc.v:36423.3-36435.6"
wire width 3 $1\dec31_dec_sub4_cr_out[2:0]
- attribute \src "libresoc.v:35985.3-35997.6"
+ attribute \src "libresoc.v:36176.3-36188.6"
wire width 2 $1\dec31_dec_sub4_cry_in[1:0]
- attribute \src "libresoc.v:36037.3-36049.6"
+ attribute \src "libresoc.v:36228.3-36240.6"
wire $1\dec31_dec_sub4_cry_out[0:0]
- attribute \src "libresoc.v:36154.3-36166.6"
+ attribute \src "libresoc.v:36345.3-36357.6"
wire width 5 $1\dec31_dec_sub4_form[4:0]
- attribute \src "libresoc.v:35933.3-35945.6"
+ attribute \src "libresoc.v:36124.3-36136.6"
wire width 12 $1\dec31_dec_sub4_function_unit[11:0]
- attribute \src "libresoc.v:36167.3-36179.6"
+ attribute \src "libresoc.v:36358.3-36370.6"
wire width 3 $1\dec31_dec_sub4_in1_sel[2:0]
- attribute \src "libresoc.v:36180.3-36192.6"
+ attribute \src "libresoc.v:36371.3-36383.6"
wire width 4 $1\dec31_dec_sub4_in2_sel[3:0]
- attribute \src "libresoc.v:36193.3-36205.6"
+ attribute \src "libresoc.v:36384.3-36396.6"
wire width 2 $1\dec31_dec_sub4_in3_sel[1:0]
- attribute \src "libresoc.v:36076.3-36088.6"
+ attribute \src "libresoc.v:36267.3-36279.6"
wire width 7 $1\dec31_dec_sub4_internal_op[6:0]
- attribute \src "libresoc.v:36011.3-36023.6"
+ attribute \src "libresoc.v:36202.3-36214.6"
wire $1\dec31_dec_sub4_inv_a[0:0]
- attribute \src "libresoc.v:36024.3-36036.6"
+ attribute \src "libresoc.v:36215.3-36227.6"
wire $1\dec31_dec_sub4_inv_out[0:0]
- attribute \src "libresoc.v:36102.3-36114.6"
+ attribute \src "libresoc.v:36293.3-36305.6"
wire $1\dec31_dec_sub4_is_32b[0:0]
- attribute \src "libresoc.v:35946.3-35958.6"
+ attribute \src "libresoc.v:36137.3-36149.6"
wire width 4 $1\dec31_dec_sub4_ldst_len[3:0]
- attribute \src "libresoc.v:36128.3-36140.6"
+ attribute \src "libresoc.v:36319.3-36331.6"
wire $1\dec31_dec_sub4_lk[0:0]
- attribute \src "libresoc.v:36206.3-36218.6"
+ attribute \src "libresoc.v:36397.3-36409.6"
wire width 2 $1\dec31_dec_sub4_out_sel[1:0]
- attribute \src "libresoc.v:35972.3-35984.6"
+ attribute \src "libresoc.v:36163.3-36175.6"
wire width 2 $1\dec31_dec_sub4_rc_sel[1:0]
- attribute \src "libresoc.v:36089.3-36101.6"
+ attribute \src "libresoc.v:36280.3-36292.6"
wire $1\dec31_dec_sub4_rsrv[0:0]
- attribute \src "libresoc.v:36141.3-36153.6"
+ attribute \src "libresoc.v:36332.3-36344.6"
wire $1\dec31_dec_sub4_sgl_pipe[0:0]
- attribute \src "libresoc.v:36115.3-36127.6"
+ attribute \src "libresoc.v:36306.3-36318.6"
wire $1\dec31_dec_sub4_sgn[0:0]
- attribute \src "libresoc.v:36063.3-36075.6"
+ attribute \src "libresoc.v:36254.3-36266.6"
wire $1\dec31_dec_sub4_sgn_ext[0:0]
- attribute \src "libresoc.v:35959.3-35971.6"
+ attribute \src "libresoc.v:36150.3-36162.6"
wire width 2 $1\dec31_dec_sub4_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub4_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub4_upd
- attribute \src "libresoc.v:35676.7-35676.15"
+ attribute \src "libresoc.v:35867.7-35867.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:35676.7-35676.20"
- process $proc$libresoc.v:35676$766
+ attribute \src "libresoc.v:35867.7-35867.20"
+ process $proc$libresoc.v:35867$806
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:35933.3-35945.6"
- process $proc$libresoc.v:35933$742
+ attribute \src "libresoc.v:36124.3-36136.6"
+ process $proc$libresoc.v:36124$782
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0]
- attribute \src "libresoc.v:35934.5-35934.29"
+ attribute \src "libresoc.v:36125.5-36125.29"
switch \initial
- attribute \src "libresoc.v:35934.9-35934.17"
+ attribute \src "libresoc.v:36125.9-36125.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0]
end
- attribute \src "libresoc.v:35946.3-35958.6"
- process $proc$libresoc.v:35946$743
+ attribute \src "libresoc.v:36137.3-36149.6"
+ process $proc$libresoc.v:36137$783
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0]
- attribute \src "libresoc.v:35947.5-35947.29"
+ attribute \src "libresoc.v:36138.5-36138.29"
switch \initial
- attribute \src "libresoc.v:35947.9-35947.17"
+ attribute \src "libresoc.v:36138.9-36138.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0]
end
- attribute \src "libresoc.v:35959.3-35971.6"
- process $proc$libresoc.v:35959$744
+ attribute \src "libresoc.v:36150.3-36162.6"
+ process $proc$libresoc.v:36150$784
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0]
- attribute \src "libresoc.v:35960.5-35960.29"
+ attribute \src "libresoc.v:36151.5-36151.29"
switch \initial
- attribute \src "libresoc.v:35960.9-35960.17"
+ attribute \src "libresoc.v:36151.9-36151.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0]
end
- attribute \src "libresoc.v:35972.3-35984.6"
- process $proc$libresoc.v:35972$745
+ attribute \src "libresoc.v:36163.3-36175.6"
+ process $proc$libresoc.v:36163$785
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0]
- attribute \src "libresoc.v:35973.5-35973.29"
+ attribute \src "libresoc.v:36164.5-36164.29"
switch \initial
- attribute \src "libresoc.v:35973.9-35973.17"
+ attribute \src "libresoc.v:36164.9-36164.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0]
end
- attribute \src "libresoc.v:35985.3-35997.6"
- process $proc$libresoc.v:35985$746
+ attribute \src "libresoc.v:36176.3-36188.6"
+ process $proc$libresoc.v:36176$786
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0]
- attribute \src "libresoc.v:35986.5-35986.29"
+ attribute \src "libresoc.v:36177.5-36177.29"
switch \initial
- attribute \src "libresoc.v:35986.9-35986.17"
+ attribute \src "libresoc.v:36177.9-36177.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0]
end
- attribute \src "libresoc.v:35998.3-36010.6"
- process $proc$libresoc.v:35998$747
+ attribute \src "libresoc.v:36189.3-36201.6"
+ process $proc$libresoc.v:36189$787
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0]
- attribute \src "libresoc.v:35999.5-35999.29"
+ attribute \src "libresoc.v:36190.5-36190.29"
switch \initial
- attribute \src "libresoc.v:35999.9-35999.17"
+ attribute \src "libresoc.v:36190.9-36190.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0]
end
- attribute \src "libresoc.v:36011.3-36023.6"
- process $proc$libresoc.v:36011$748
+ attribute \src "libresoc.v:36202.3-36214.6"
+ process $proc$libresoc.v:36202$788
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0]
- attribute \src "libresoc.v:36012.5-36012.29"
+ attribute \src "libresoc.v:36203.5-36203.29"
switch \initial
- attribute \src "libresoc.v:36012.9-36012.17"
+ attribute \src "libresoc.v:36203.9-36203.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0]
end
- attribute \src "libresoc.v:36024.3-36036.6"
- process $proc$libresoc.v:36024$749
+ attribute \src "libresoc.v:36215.3-36227.6"
+ process $proc$libresoc.v:36215$789
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0]
- attribute \src "libresoc.v:36025.5-36025.29"
+ attribute \src "libresoc.v:36216.5-36216.29"
switch \initial
- attribute \src "libresoc.v:36025.9-36025.17"
+ attribute \src "libresoc.v:36216.9-36216.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0]
end
- attribute \src "libresoc.v:36037.3-36049.6"
- process $proc$libresoc.v:36037$750
+ attribute \src "libresoc.v:36228.3-36240.6"
+ process $proc$libresoc.v:36228$790
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0]
- attribute \src "libresoc.v:36038.5-36038.29"
+ attribute \src "libresoc.v:36229.5-36229.29"
switch \initial
- attribute \src "libresoc.v:36038.9-36038.17"
+ attribute \src "libresoc.v:36229.9-36229.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0]
end
- attribute \src "libresoc.v:36050.3-36062.6"
- process $proc$libresoc.v:36050$751
+ attribute \src "libresoc.v:36241.3-36253.6"
+ process $proc$libresoc.v:36241$791
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0]
- attribute \src "libresoc.v:36051.5-36051.29"
+ attribute \src "libresoc.v:36242.5-36242.29"
switch \initial
- attribute \src "libresoc.v:36051.9-36051.17"
+ attribute \src "libresoc.v:36242.9-36242.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0]
end
- attribute \src "libresoc.v:36063.3-36075.6"
- process $proc$libresoc.v:36063$752
+ attribute \src "libresoc.v:36254.3-36266.6"
+ process $proc$libresoc.v:36254$792
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0]
- attribute \src "libresoc.v:36064.5-36064.29"
+ attribute \src "libresoc.v:36255.5-36255.29"
switch \initial
- attribute \src "libresoc.v:36064.9-36064.17"
+ attribute \src "libresoc.v:36255.9-36255.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0]
end
- attribute \src "libresoc.v:36076.3-36088.6"
- process $proc$libresoc.v:36076$753
+ attribute \src "libresoc.v:36267.3-36279.6"
+ process $proc$libresoc.v:36267$793
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0]
- attribute \src "libresoc.v:36077.5-36077.29"
+ attribute \src "libresoc.v:36268.5-36268.29"
switch \initial
- attribute \src "libresoc.v:36077.9-36077.17"
+ attribute \src "libresoc.v:36268.9-36268.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0]
end
- attribute \src "libresoc.v:36089.3-36101.6"
- process $proc$libresoc.v:36089$754
+ attribute \src "libresoc.v:36280.3-36292.6"
+ process $proc$libresoc.v:36280$794
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0]
- attribute \src "libresoc.v:36090.5-36090.29"
+ attribute \src "libresoc.v:36281.5-36281.29"
switch \initial
- attribute \src "libresoc.v:36090.9-36090.17"
+ attribute \src "libresoc.v:36281.9-36281.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0]
end
- attribute \src "libresoc.v:36102.3-36114.6"
- process $proc$libresoc.v:36102$755
+ attribute \src "libresoc.v:36293.3-36305.6"
+ process $proc$libresoc.v:36293$795
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0]
- attribute \src "libresoc.v:36103.5-36103.29"
+ attribute \src "libresoc.v:36294.5-36294.29"
switch \initial
- attribute \src "libresoc.v:36103.9-36103.17"
+ attribute \src "libresoc.v:36294.9-36294.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0]
end
- attribute \src "libresoc.v:36115.3-36127.6"
- process $proc$libresoc.v:36115$756
+ attribute \src "libresoc.v:36306.3-36318.6"
+ process $proc$libresoc.v:36306$796
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0]
- attribute \src "libresoc.v:36116.5-36116.29"
+ attribute \src "libresoc.v:36307.5-36307.29"
switch \initial
- attribute \src "libresoc.v:36116.9-36116.17"
+ attribute \src "libresoc.v:36307.9-36307.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0]
end
- attribute \src "libresoc.v:36128.3-36140.6"
- process $proc$libresoc.v:36128$757
+ attribute \src "libresoc.v:36319.3-36331.6"
+ process $proc$libresoc.v:36319$797
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0]
- attribute \src "libresoc.v:36129.5-36129.29"
+ attribute \src "libresoc.v:36320.5-36320.29"
switch \initial
- attribute \src "libresoc.v:36129.9-36129.17"
+ attribute \src "libresoc.v:36320.9-36320.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0]
end
- attribute \src "libresoc.v:36141.3-36153.6"
- process $proc$libresoc.v:36141$758
+ attribute \src "libresoc.v:36332.3-36344.6"
+ process $proc$libresoc.v:36332$798
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0]
- attribute \src "libresoc.v:36142.5-36142.29"
+ attribute \src "libresoc.v:36333.5-36333.29"
switch \initial
- attribute \src "libresoc.v:36142.9-36142.17"
+ attribute \src "libresoc.v:36333.9-36333.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:36154.3-36166.6"
- process $proc$libresoc.v:36154$759
+ attribute \src "libresoc.v:36345.3-36357.6"
+ process $proc$libresoc.v:36345$799
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0]
- attribute \src "libresoc.v:36155.5-36155.29"
+ attribute \src "libresoc.v:36346.5-36346.29"
switch \initial
- attribute \src "libresoc.v:36155.9-36155.17"
+ attribute \src "libresoc.v:36346.9-36346.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0]
end
- attribute \src "libresoc.v:36167.3-36179.6"
- process $proc$libresoc.v:36167$760
+ attribute \src "libresoc.v:36358.3-36370.6"
+ process $proc$libresoc.v:36358$800
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0]
- attribute \src "libresoc.v:36168.5-36168.29"
+ attribute \src "libresoc.v:36359.5-36359.29"
switch \initial
- attribute \src "libresoc.v:36168.9-36168.17"
+ attribute \src "libresoc.v:36359.9-36359.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0]
end
- attribute \src "libresoc.v:36180.3-36192.6"
- process $proc$libresoc.v:36180$761
+ attribute \src "libresoc.v:36371.3-36383.6"
+ process $proc$libresoc.v:36371$801
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0]
- attribute \src "libresoc.v:36181.5-36181.29"
+ attribute \src "libresoc.v:36372.5-36372.29"
switch \initial
- attribute \src "libresoc.v:36181.9-36181.17"
+ attribute \src "libresoc.v:36372.9-36372.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0]
end
- attribute \src "libresoc.v:36193.3-36205.6"
- process $proc$libresoc.v:36193$762
+ attribute \src "libresoc.v:36384.3-36396.6"
+ process $proc$libresoc.v:36384$802
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0]
- attribute \src "libresoc.v:36194.5-36194.29"
+ attribute \src "libresoc.v:36385.5-36385.29"
switch \initial
- attribute \src "libresoc.v:36194.9-36194.17"
+ attribute \src "libresoc.v:36385.9-36385.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0]
end
- attribute \src "libresoc.v:36206.3-36218.6"
- process $proc$libresoc.v:36206$763
+ attribute \src "libresoc.v:36397.3-36409.6"
+ process $proc$libresoc.v:36397$803
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0]
- attribute \src "libresoc.v:36207.5-36207.29"
+ attribute \src "libresoc.v:36398.5-36398.29"
switch \initial
- attribute \src "libresoc.v:36207.9-36207.17"
+ attribute \src "libresoc.v:36398.9-36398.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0]
end
- attribute \src "libresoc.v:36219.3-36231.6"
- process $proc$libresoc.v:36219$764
+ attribute \src "libresoc.v:36410.3-36422.6"
+ process $proc$libresoc.v:36410$804
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0]
- attribute \src "libresoc.v:36220.5-36220.29"
+ attribute \src "libresoc.v:36411.5-36411.29"
switch \initial
- attribute \src "libresoc.v:36220.9-36220.17"
+ attribute \src "libresoc.v:36411.9-36411.17"
case 1'1
case
end
sync always
update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0]
end
- attribute \src "libresoc.v:36232.3-36244.6"
- process $proc$libresoc.v:36232$765
+ attribute \src "libresoc.v:36423.3-36435.6"
+ process $proc$libresoc.v:36423$805
assign { } { }
assign { } { }
assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0]
- attribute \src "libresoc.v:36233.5-36233.29"
+ attribute \src "libresoc.v:36424.5-36424.29"
switch \initial
- attribute \src "libresoc.v:36233.9-36233.17"
+ attribute \src "libresoc.v:36424.9-36424.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:36250.1-37541.10"
+attribute \src "libresoc.v:36441.1-37732.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub8"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8"
attribute \generator "nMigen"
module \dec31_dec_sub8
- attribute \src "libresoc.v:36723.3-36765.6"
+ attribute \src "libresoc.v:36914.3-36956.6"
wire width 8 $0\dec31_dec_sub8_asmcode[7:0]
- attribute \src "libresoc.v:36895.3-36937.6"
+ attribute \src "libresoc.v:37086.3-37128.6"
wire $0\dec31_dec_sub8_br[0:0]
- attribute \src "libresoc.v:37454.3-37496.6"
+ attribute \src "libresoc.v:37645.3-37687.6"
wire width 3 $0\dec31_dec_sub8_cr_in[2:0]
- attribute \src "libresoc.v:37497.3-37539.6"
+ attribute \src "libresoc.v:37688.3-37730.6"
wire width 3 $0\dec31_dec_sub8_cr_out[2:0]
- attribute \src "libresoc.v:36680.3-36722.6"
+ attribute \src "libresoc.v:36871.3-36913.6"
wire width 2 $0\dec31_dec_sub8_cry_in[1:0]
- attribute \src "libresoc.v:36852.3-36894.6"
+ attribute \src "libresoc.v:37043.3-37085.6"
wire $0\dec31_dec_sub8_cry_out[0:0]
- attribute \src "libresoc.v:37239.3-37281.6"
+ attribute \src "libresoc.v:37430.3-37472.6"
wire width 5 $0\dec31_dec_sub8_form[4:0]
- attribute \src "libresoc.v:36508.3-36550.6"
+ attribute \src "libresoc.v:36699.3-36741.6"
wire width 12 $0\dec31_dec_sub8_function_unit[11:0]
- attribute \src "libresoc.v:37282.3-37324.6"
+ attribute \src "libresoc.v:37473.3-37515.6"
wire width 3 $0\dec31_dec_sub8_in1_sel[2:0]
- attribute \src "libresoc.v:37325.3-37367.6"
+ attribute \src "libresoc.v:37516.3-37558.6"
wire width 4 $0\dec31_dec_sub8_in2_sel[3:0]
- attribute \src "libresoc.v:37368.3-37410.6"
+ attribute \src "libresoc.v:37559.3-37601.6"
wire width 2 $0\dec31_dec_sub8_in3_sel[1:0]
- attribute \src "libresoc.v:36981.3-37023.6"
+ attribute \src "libresoc.v:37172.3-37214.6"
wire width 7 $0\dec31_dec_sub8_internal_op[6:0]
- attribute \src "libresoc.v:36766.3-36808.6"
+ attribute \src "libresoc.v:36957.3-36999.6"
wire $0\dec31_dec_sub8_inv_a[0:0]
- attribute \src "libresoc.v:36809.3-36851.6"
+ attribute \src "libresoc.v:37000.3-37042.6"
wire $0\dec31_dec_sub8_inv_out[0:0]
- attribute \src "libresoc.v:37067.3-37109.6"
+ attribute \src "libresoc.v:37258.3-37300.6"
wire $0\dec31_dec_sub8_is_32b[0:0]
- attribute \src "libresoc.v:36551.3-36593.6"
+ attribute \src "libresoc.v:36742.3-36784.6"
wire width 4 $0\dec31_dec_sub8_ldst_len[3:0]
- attribute \src "libresoc.v:37153.3-37195.6"
+ attribute \src "libresoc.v:37344.3-37386.6"
wire $0\dec31_dec_sub8_lk[0:0]
- attribute \src "libresoc.v:37411.3-37453.6"
+ attribute \src "libresoc.v:37602.3-37644.6"
wire width 2 $0\dec31_dec_sub8_out_sel[1:0]
- attribute \src "libresoc.v:36637.3-36679.6"
+ attribute \src "libresoc.v:36828.3-36870.6"
wire width 2 $0\dec31_dec_sub8_rc_sel[1:0]
- attribute \src "libresoc.v:37024.3-37066.6"
+ attribute \src "libresoc.v:37215.3-37257.6"
wire $0\dec31_dec_sub8_rsrv[0:0]
- attribute \src "libresoc.v:37196.3-37238.6"
+ attribute \src "libresoc.v:37387.3-37429.6"
wire $0\dec31_dec_sub8_sgl_pipe[0:0]
- attribute \src "libresoc.v:37110.3-37152.6"
+ attribute \src "libresoc.v:37301.3-37343.6"
wire $0\dec31_dec_sub8_sgn[0:0]
- attribute \src "libresoc.v:36938.3-36980.6"
+ attribute \src "libresoc.v:37129.3-37171.6"
wire $0\dec31_dec_sub8_sgn_ext[0:0]
- attribute \src "libresoc.v:36594.3-36636.6"
+ attribute \src "libresoc.v:36785.3-36827.6"
wire width 2 $0\dec31_dec_sub8_upd[1:0]
- attribute \src "libresoc.v:36251.7-36251.20"
+ attribute \src "libresoc.v:36442.7-36442.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:36723.3-36765.6"
+ attribute \src "libresoc.v:36914.3-36956.6"
wire width 8 $1\dec31_dec_sub8_asmcode[7:0]
- attribute \src "libresoc.v:36895.3-36937.6"
+ attribute \src "libresoc.v:37086.3-37128.6"
wire $1\dec31_dec_sub8_br[0:0]
- attribute \src "libresoc.v:37454.3-37496.6"
+ attribute \src "libresoc.v:37645.3-37687.6"
wire width 3 $1\dec31_dec_sub8_cr_in[2:0]
- attribute \src "libresoc.v:37497.3-37539.6"
+ attribute \src "libresoc.v:37688.3-37730.6"
wire width 3 $1\dec31_dec_sub8_cr_out[2:0]
- attribute \src "libresoc.v:36680.3-36722.6"
+ attribute \src "libresoc.v:36871.3-36913.6"
wire width 2 $1\dec31_dec_sub8_cry_in[1:0]
- attribute \src "libresoc.v:36852.3-36894.6"
+ attribute \src "libresoc.v:37043.3-37085.6"
wire $1\dec31_dec_sub8_cry_out[0:0]
- attribute \src "libresoc.v:37239.3-37281.6"
+ attribute \src "libresoc.v:37430.3-37472.6"
wire width 5 $1\dec31_dec_sub8_form[4:0]
- attribute \src "libresoc.v:36508.3-36550.6"
+ attribute \src "libresoc.v:36699.3-36741.6"
wire width 12 $1\dec31_dec_sub8_function_unit[11:0]
- attribute \src "libresoc.v:37282.3-37324.6"
+ attribute \src "libresoc.v:37473.3-37515.6"
wire width 3 $1\dec31_dec_sub8_in1_sel[2:0]
- attribute \src "libresoc.v:37325.3-37367.6"
+ attribute \src "libresoc.v:37516.3-37558.6"
wire width 4 $1\dec31_dec_sub8_in2_sel[3:0]
- attribute \src "libresoc.v:37368.3-37410.6"
+ attribute \src "libresoc.v:37559.3-37601.6"
wire width 2 $1\dec31_dec_sub8_in3_sel[1:0]
- attribute \src "libresoc.v:36981.3-37023.6"
+ attribute \src "libresoc.v:37172.3-37214.6"
wire width 7 $1\dec31_dec_sub8_internal_op[6:0]
- attribute \src "libresoc.v:36766.3-36808.6"
+ attribute \src "libresoc.v:36957.3-36999.6"
wire $1\dec31_dec_sub8_inv_a[0:0]
- attribute \src "libresoc.v:36809.3-36851.6"
+ attribute \src "libresoc.v:37000.3-37042.6"
wire $1\dec31_dec_sub8_inv_out[0:0]
- attribute \src "libresoc.v:37067.3-37109.6"
+ attribute \src "libresoc.v:37258.3-37300.6"
wire $1\dec31_dec_sub8_is_32b[0:0]
- attribute \src "libresoc.v:36551.3-36593.6"
+ attribute \src "libresoc.v:36742.3-36784.6"
wire width 4 $1\dec31_dec_sub8_ldst_len[3:0]
- attribute \src "libresoc.v:37153.3-37195.6"
+ attribute \src "libresoc.v:37344.3-37386.6"
wire $1\dec31_dec_sub8_lk[0:0]
- attribute \src "libresoc.v:37411.3-37453.6"
+ attribute \src "libresoc.v:37602.3-37644.6"
wire width 2 $1\dec31_dec_sub8_out_sel[1:0]
- attribute \src "libresoc.v:36637.3-36679.6"
+ attribute \src "libresoc.v:36828.3-36870.6"
wire width 2 $1\dec31_dec_sub8_rc_sel[1:0]
- attribute \src "libresoc.v:37024.3-37066.6"
+ attribute \src "libresoc.v:37215.3-37257.6"
wire $1\dec31_dec_sub8_rsrv[0:0]
- attribute \src "libresoc.v:37196.3-37238.6"
+ attribute \src "libresoc.v:37387.3-37429.6"
wire $1\dec31_dec_sub8_sgl_pipe[0:0]
- attribute \src "libresoc.v:37110.3-37152.6"
+ attribute \src "libresoc.v:37301.3-37343.6"
wire $1\dec31_dec_sub8_sgn[0:0]
- attribute \src "libresoc.v:36938.3-36980.6"
+ attribute \src "libresoc.v:37129.3-37171.6"
wire $1\dec31_dec_sub8_sgn_ext[0:0]
- attribute \src "libresoc.v:36594.3-36636.6"
+ attribute \src "libresoc.v:36785.3-36827.6"
wire width 2 $1\dec31_dec_sub8_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub8_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub8_upd
- attribute \src "libresoc.v:36251.7-36251.15"
+ attribute \src "libresoc.v:36442.7-36442.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:36251.7-36251.20"
- process $proc$libresoc.v:36251$791
+ attribute \src "libresoc.v:36442.7-36442.20"
+ process $proc$libresoc.v:36442$831
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:36508.3-36550.6"
- process $proc$libresoc.v:36508$767
+ attribute \src "libresoc.v:36699.3-36741.6"
+ process $proc$libresoc.v:36699$807
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0]
- attribute \src "libresoc.v:36509.5-36509.29"
+ attribute \src "libresoc.v:36700.5-36700.29"
switch \initial
- attribute \src "libresoc.v:36509.9-36509.17"
+ attribute \src "libresoc.v:36700.9-36700.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0]
end
- attribute \src "libresoc.v:36551.3-36593.6"
- process $proc$libresoc.v:36551$768
+ attribute \src "libresoc.v:36742.3-36784.6"
+ process $proc$libresoc.v:36742$808
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0]
- attribute \src "libresoc.v:36552.5-36552.29"
+ attribute \src "libresoc.v:36743.5-36743.29"
switch \initial
- attribute \src "libresoc.v:36552.9-36552.17"
+ attribute \src "libresoc.v:36743.9-36743.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0]
end
- attribute \src "libresoc.v:36594.3-36636.6"
- process $proc$libresoc.v:36594$769
+ attribute \src "libresoc.v:36785.3-36827.6"
+ process $proc$libresoc.v:36785$809
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0]
- attribute \src "libresoc.v:36595.5-36595.29"
+ attribute \src "libresoc.v:36786.5-36786.29"
switch \initial
- attribute \src "libresoc.v:36595.9-36595.17"
+ attribute \src "libresoc.v:36786.9-36786.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0]
end
- attribute \src "libresoc.v:36637.3-36679.6"
- process $proc$libresoc.v:36637$770
+ attribute \src "libresoc.v:36828.3-36870.6"
+ process $proc$libresoc.v:36828$810
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0]
- attribute \src "libresoc.v:36638.5-36638.29"
+ attribute \src "libresoc.v:36829.5-36829.29"
switch \initial
- attribute \src "libresoc.v:36638.9-36638.17"
+ attribute \src "libresoc.v:36829.9-36829.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0]
end
- attribute \src "libresoc.v:36680.3-36722.6"
- process $proc$libresoc.v:36680$771
+ attribute \src "libresoc.v:36871.3-36913.6"
+ process $proc$libresoc.v:36871$811
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0]
- attribute \src "libresoc.v:36681.5-36681.29"
+ attribute \src "libresoc.v:36872.5-36872.29"
switch \initial
- attribute \src "libresoc.v:36681.9-36681.17"
+ attribute \src "libresoc.v:36872.9-36872.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0]
end
- attribute \src "libresoc.v:36723.3-36765.6"
- process $proc$libresoc.v:36723$772
+ attribute \src "libresoc.v:36914.3-36956.6"
+ process $proc$libresoc.v:36914$812
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0]
- attribute \src "libresoc.v:36724.5-36724.29"
+ attribute \src "libresoc.v:36915.5-36915.29"
switch \initial
- attribute \src "libresoc.v:36724.9-36724.17"
+ attribute \src "libresoc.v:36915.9-36915.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0]
end
- attribute \src "libresoc.v:36766.3-36808.6"
- process $proc$libresoc.v:36766$773
+ attribute \src "libresoc.v:36957.3-36999.6"
+ process $proc$libresoc.v:36957$813
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0]
- attribute \src "libresoc.v:36767.5-36767.29"
+ attribute \src "libresoc.v:36958.5-36958.29"
switch \initial
- attribute \src "libresoc.v:36767.9-36767.17"
+ attribute \src "libresoc.v:36958.9-36958.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0]
end
- attribute \src "libresoc.v:36809.3-36851.6"
- process $proc$libresoc.v:36809$774
+ attribute \src "libresoc.v:37000.3-37042.6"
+ process $proc$libresoc.v:37000$814
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0]
- attribute \src "libresoc.v:36810.5-36810.29"
+ attribute \src "libresoc.v:37001.5-37001.29"
switch \initial
- attribute \src "libresoc.v:36810.9-36810.17"
+ attribute \src "libresoc.v:37001.9-37001.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0]
end
- attribute \src "libresoc.v:36852.3-36894.6"
- process $proc$libresoc.v:36852$775
+ attribute \src "libresoc.v:37043.3-37085.6"
+ process $proc$libresoc.v:37043$815
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0]
- attribute \src "libresoc.v:36853.5-36853.29"
+ attribute \src "libresoc.v:37044.5-37044.29"
switch \initial
- attribute \src "libresoc.v:36853.9-36853.17"
+ attribute \src "libresoc.v:37044.9-37044.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0]
end
- attribute \src "libresoc.v:36895.3-36937.6"
- process $proc$libresoc.v:36895$776
+ attribute \src "libresoc.v:37086.3-37128.6"
+ process $proc$libresoc.v:37086$816
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0]
- attribute \src "libresoc.v:36896.5-36896.29"
+ attribute \src "libresoc.v:37087.5-37087.29"
switch \initial
- attribute \src "libresoc.v:36896.9-36896.17"
+ attribute \src "libresoc.v:37087.9-37087.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0]
end
- attribute \src "libresoc.v:36938.3-36980.6"
- process $proc$libresoc.v:36938$777
+ attribute \src "libresoc.v:37129.3-37171.6"
+ process $proc$libresoc.v:37129$817
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0]
- attribute \src "libresoc.v:36939.5-36939.29"
+ attribute \src "libresoc.v:37130.5-37130.29"
switch \initial
- attribute \src "libresoc.v:36939.9-36939.17"
+ attribute \src "libresoc.v:37130.9-37130.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0]
end
- attribute \src "libresoc.v:36981.3-37023.6"
- process $proc$libresoc.v:36981$778
+ attribute \src "libresoc.v:37172.3-37214.6"
+ process $proc$libresoc.v:37172$818
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0]
- attribute \src "libresoc.v:36982.5-36982.29"
+ attribute \src "libresoc.v:37173.5-37173.29"
switch \initial
- attribute \src "libresoc.v:36982.9-36982.17"
+ attribute \src "libresoc.v:37173.9-37173.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0]
end
- attribute \src "libresoc.v:37024.3-37066.6"
- process $proc$libresoc.v:37024$779
+ attribute \src "libresoc.v:37215.3-37257.6"
+ process $proc$libresoc.v:37215$819
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0]
- attribute \src "libresoc.v:37025.5-37025.29"
+ attribute \src "libresoc.v:37216.5-37216.29"
switch \initial
- attribute \src "libresoc.v:37025.9-37025.17"
+ attribute \src "libresoc.v:37216.9-37216.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0]
end
- attribute \src "libresoc.v:37067.3-37109.6"
- process $proc$libresoc.v:37067$780
+ attribute \src "libresoc.v:37258.3-37300.6"
+ process $proc$libresoc.v:37258$820
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0]
- attribute \src "libresoc.v:37068.5-37068.29"
+ attribute \src "libresoc.v:37259.5-37259.29"
switch \initial
- attribute \src "libresoc.v:37068.9-37068.17"
+ attribute \src "libresoc.v:37259.9-37259.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0]
end
- attribute \src "libresoc.v:37110.3-37152.6"
- process $proc$libresoc.v:37110$781
+ attribute \src "libresoc.v:37301.3-37343.6"
+ process $proc$libresoc.v:37301$821
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0]
- attribute \src "libresoc.v:37111.5-37111.29"
+ attribute \src "libresoc.v:37302.5-37302.29"
switch \initial
- attribute \src "libresoc.v:37111.9-37111.17"
+ attribute \src "libresoc.v:37302.9-37302.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0]
end
- attribute \src "libresoc.v:37153.3-37195.6"
- process $proc$libresoc.v:37153$782
+ attribute \src "libresoc.v:37344.3-37386.6"
+ process $proc$libresoc.v:37344$822
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0]
- attribute \src "libresoc.v:37154.5-37154.29"
+ attribute \src "libresoc.v:37345.5-37345.29"
switch \initial
- attribute \src "libresoc.v:37154.9-37154.17"
+ attribute \src "libresoc.v:37345.9-37345.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0]
end
- attribute \src "libresoc.v:37196.3-37238.6"
- process $proc$libresoc.v:37196$783
+ attribute \src "libresoc.v:37387.3-37429.6"
+ process $proc$libresoc.v:37387$823
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0]
- attribute \src "libresoc.v:37197.5-37197.29"
+ attribute \src "libresoc.v:37388.5-37388.29"
switch \initial
- attribute \src "libresoc.v:37197.9-37197.17"
+ attribute \src "libresoc.v:37388.9-37388.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:37239.3-37281.6"
- process $proc$libresoc.v:37239$784
+ attribute \src "libresoc.v:37430.3-37472.6"
+ process $proc$libresoc.v:37430$824
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0]
- attribute \src "libresoc.v:37240.5-37240.29"
+ attribute \src "libresoc.v:37431.5-37431.29"
switch \initial
- attribute \src "libresoc.v:37240.9-37240.17"
+ attribute \src "libresoc.v:37431.9-37431.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0]
end
- attribute \src "libresoc.v:37282.3-37324.6"
- process $proc$libresoc.v:37282$785
+ attribute \src "libresoc.v:37473.3-37515.6"
+ process $proc$libresoc.v:37473$825
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0]
- attribute \src "libresoc.v:37283.5-37283.29"
+ attribute \src "libresoc.v:37474.5-37474.29"
switch \initial
- attribute \src "libresoc.v:37283.9-37283.17"
+ attribute \src "libresoc.v:37474.9-37474.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0]
end
- attribute \src "libresoc.v:37325.3-37367.6"
- process $proc$libresoc.v:37325$786
+ attribute \src "libresoc.v:37516.3-37558.6"
+ process $proc$libresoc.v:37516$826
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0]
- attribute \src "libresoc.v:37326.5-37326.29"
+ attribute \src "libresoc.v:37517.5-37517.29"
switch \initial
- attribute \src "libresoc.v:37326.9-37326.17"
+ attribute \src "libresoc.v:37517.9-37517.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0]
end
- attribute \src "libresoc.v:37368.3-37410.6"
- process $proc$libresoc.v:37368$787
+ attribute \src "libresoc.v:37559.3-37601.6"
+ process $proc$libresoc.v:37559$827
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0]
- attribute \src "libresoc.v:37369.5-37369.29"
+ attribute \src "libresoc.v:37560.5-37560.29"
switch \initial
- attribute \src "libresoc.v:37369.9-37369.17"
+ attribute \src "libresoc.v:37560.9-37560.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0]
end
- attribute \src "libresoc.v:37411.3-37453.6"
- process $proc$libresoc.v:37411$788
+ attribute \src "libresoc.v:37602.3-37644.6"
+ process $proc$libresoc.v:37602$828
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0]
- attribute \src "libresoc.v:37412.5-37412.29"
+ attribute \src "libresoc.v:37603.5-37603.29"
switch \initial
- attribute \src "libresoc.v:37412.9-37412.17"
+ attribute \src "libresoc.v:37603.9-37603.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0]
end
- attribute \src "libresoc.v:37454.3-37496.6"
- process $proc$libresoc.v:37454$789
+ attribute \src "libresoc.v:37645.3-37687.6"
+ process $proc$libresoc.v:37645$829
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0]
- attribute \src "libresoc.v:37455.5-37455.29"
+ attribute \src "libresoc.v:37646.5-37646.29"
switch \initial
- attribute \src "libresoc.v:37455.9-37455.17"
+ attribute \src "libresoc.v:37646.9-37646.17"
case 1'1
case
end
sync always
update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0]
end
- attribute \src "libresoc.v:37497.3-37539.6"
- process $proc$libresoc.v:37497$790
+ attribute \src "libresoc.v:37688.3-37730.6"
+ process $proc$libresoc.v:37688$830
assign { } { }
assign { } { }
assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0]
- attribute \src "libresoc.v:37498.5-37498.29"
+ attribute \src "libresoc.v:37689.5-37689.29"
switch \initial
- attribute \src "libresoc.v:37498.9-37498.17"
+ attribute \src "libresoc.v:37689.9-37689.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:37545.1-39124.10"
+attribute \src "libresoc.v:37736.1-39315.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub9"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9"
attribute \generator "nMigen"
module \dec31_dec_sub9
- attribute \src "libresoc.v:38078.3-38132.6"
+ attribute \src "libresoc.v:38269.3-38323.6"
wire width 8 $0\dec31_dec_sub9_asmcode[7:0]
- attribute \src "libresoc.v:38298.3-38352.6"
+ attribute \src "libresoc.v:38489.3-38543.6"
wire $0\dec31_dec_sub9_br[0:0]
- attribute \src "libresoc.v:39013.3-39067.6"
+ attribute \src "libresoc.v:39204.3-39258.6"
wire width 3 $0\dec31_dec_sub9_cr_in[2:0]
- attribute \src "libresoc.v:39068.3-39122.6"
+ attribute \src "libresoc.v:39259.3-39313.6"
wire width 3 $0\dec31_dec_sub9_cr_out[2:0]
- attribute \src "libresoc.v:38023.3-38077.6"
+ attribute \src "libresoc.v:38214.3-38268.6"
wire width 2 $0\dec31_dec_sub9_cry_in[1:0]
- attribute \src "libresoc.v:38243.3-38297.6"
+ attribute \src "libresoc.v:38434.3-38488.6"
wire $0\dec31_dec_sub9_cry_out[0:0]
- attribute \src "libresoc.v:38738.3-38792.6"
+ attribute \src "libresoc.v:38929.3-38983.6"
wire width 5 $0\dec31_dec_sub9_form[4:0]
- attribute \src "libresoc.v:37803.3-37857.6"
+ attribute \src "libresoc.v:37994.3-38048.6"
wire width 12 $0\dec31_dec_sub9_function_unit[11:0]
- attribute \src "libresoc.v:38793.3-38847.6"
+ attribute \src "libresoc.v:38984.3-39038.6"
wire width 3 $0\dec31_dec_sub9_in1_sel[2:0]
- attribute \src "libresoc.v:38848.3-38902.6"
+ attribute \src "libresoc.v:39039.3-39093.6"
wire width 4 $0\dec31_dec_sub9_in2_sel[3:0]
- attribute \src "libresoc.v:38903.3-38957.6"
+ attribute \src "libresoc.v:39094.3-39148.6"
wire width 2 $0\dec31_dec_sub9_in3_sel[1:0]
- attribute \src "libresoc.v:38408.3-38462.6"
+ attribute \src "libresoc.v:38599.3-38653.6"
wire width 7 $0\dec31_dec_sub9_internal_op[6:0]
- attribute \src "libresoc.v:38133.3-38187.6"
+ attribute \src "libresoc.v:38324.3-38378.6"
wire $0\dec31_dec_sub9_inv_a[0:0]
- attribute \src "libresoc.v:38188.3-38242.6"
+ attribute \src "libresoc.v:38379.3-38433.6"
wire $0\dec31_dec_sub9_inv_out[0:0]
- attribute \src "libresoc.v:38518.3-38572.6"
+ attribute \src "libresoc.v:38709.3-38763.6"
wire $0\dec31_dec_sub9_is_32b[0:0]
- attribute \src "libresoc.v:37858.3-37912.6"
+ attribute \src "libresoc.v:38049.3-38103.6"
wire width 4 $0\dec31_dec_sub9_ldst_len[3:0]
- attribute \src "libresoc.v:38628.3-38682.6"
+ attribute \src "libresoc.v:38819.3-38873.6"
wire $0\dec31_dec_sub9_lk[0:0]
- attribute \src "libresoc.v:38958.3-39012.6"
+ attribute \src "libresoc.v:39149.3-39203.6"
wire width 2 $0\dec31_dec_sub9_out_sel[1:0]
- attribute \src "libresoc.v:37968.3-38022.6"
+ attribute \src "libresoc.v:38159.3-38213.6"
wire width 2 $0\dec31_dec_sub9_rc_sel[1:0]
- attribute \src "libresoc.v:38463.3-38517.6"
+ attribute \src "libresoc.v:38654.3-38708.6"
wire $0\dec31_dec_sub9_rsrv[0:0]
- attribute \src "libresoc.v:38683.3-38737.6"
+ attribute \src "libresoc.v:38874.3-38928.6"
wire $0\dec31_dec_sub9_sgl_pipe[0:0]
- attribute \src "libresoc.v:38573.3-38627.6"
+ attribute \src "libresoc.v:38764.3-38818.6"
wire $0\dec31_dec_sub9_sgn[0:0]
- attribute \src "libresoc.v:38353.3-38407.6"
+ attribute \src "libresoc.v:38544.3-38598.6"
wire $0\dec31_dec_sub9_sgn_ext[0:0]
- attribute \src "libresoc.v:37913.3-37967.6"
+ attribute \src "libresoc.v:38104.3-38158.6"
wire width 2 $0\dec31_dec_sub9_upd[1:0]
- attribute \src "libresoc.v:37546.7-37546.20"
+ attribute \src "libresoc.v:37737.7-37737.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:38078.3-38132.6"
+ attribute \src "libresoc.v:38269.3-38323.6"
wire width 8 $1\dec31_dec_sub9_asmcode[7:0]
- attribute \src "libresoc.v:38298.3-38352.6"
+ attribute \src "libresoc.v:38489.3-38543.6"
wire $1\dec31_dec_sub9_br[0:0]
- attribute \src "libresoc.v:39013.3-39067.6"
+ attribute \src "libresoc.v:39204.3-39258.6"
wire width 3 $1\dec31_dec_sub9_cr_in[2:0]
- attribute \src "libresoc.v:39068.3-39122.6"
+ attribute \src "libresoc.v:39259.3-39313.6"
wire width 3 $1\dec31_dec_sub9_cr_out[2:0]
- attribute \src "libresoc.v:38023.3-38077.6"
+ attribute \src "libresoc.v:38214.3-38268.6"
wire width 2 $1\dec31_dec_sub9_cry_in[1:0]
- attribute \src "libresoc.v:38243.3-38297.6"
+ attribute \src "libresoc.v:38434.3-38488.6"
wire $1\dec31_dec_sub9_cry_out[0:0]
- attribute \src "libresoc.v:38738.3-38792.6"
+ attribute \src "libresoc.v:38929.3-38983.6"
wire width 5 $1\dec31_dec_sub9_form[4:0]
- attribute \src "libresoc.v:37803.3-37857.6"
+ attribute \src "libresoc.v:37994.3-38048.6"
wire width 12 $1\dec31_dec_sub9_function_unit[11:0]
- attribute \src "libresoc.v:38793.3-38847.6"
+ attribute \src "libresoc.v:38984.3-39038.6"
wire width 3 $1\dec31_dec_sub9_in1_sel[2:0]
- attribute \src "libresoc.v:38848.3-38902.6"
+ attribute \src "libresoc.v:39039.3-39093.6"
wire width 4 $1\dec31_dec_sub9_in2_sel[3:0]
- attribute \src "libresoc.v:38903.3-38957.6"
+ attribute \src "libresoc.v:39094.3-39148.6"
wire width 2 $1\dec31_dec_sub9_in3_sel[1:0]
- attribute \src "libresoc.v:38408.3-38462.6"
+ attribute \src "libresoc.v:38599.3-38653.6"
wire width 7 $1\dec31_dec_sub9_internal_op[6:0]
- attribute \src "libresoc.v:38133.3-38187.6"
+ attribute \src "libresoc.v:38324.3-38378.6"
wire $1\dec31_dec_sub9_inv_a[0:0]
- attribute \src "libresoc.v:38188.3-38242.6"
+ attribute \src "libresoc.v:38379.3-38433.6"
wire $1\dec31_dec_sub9_inv_out[0:0]
- attribute \src "libresoc.v:38518.3-38572.6"
+ attribute \src "libresoc.v:38709.3-38763.6"
wire $1\dec31_dec_sub9_is_32b[0:0]
- attribute \src "libresoc.v:37858.3-37912.6"
+ attribute \src "libresoc.v:38049.3-38103.6"
wire width 4 $1\dec31_dec_sub9_ldst_len[3:0]
- attribute \src "libresoc.v:38628.3-38682.6"
+ attribute \src "libresoc.v:38819.3-38873.6"
wire $1\dec31_dec_sub9_lk[0:0]
- attribute \src "libresoc.v:38958.3-39012.6"
+ attribute \src "libresoc.v:39149.3-39203.6"
wire width 2 $1\dec31_dec_sub9_out_sel[1:0]
- attribute \src "libresoc.v:37968.3-38022.6"
+ attribute \src "libresoc.v:38159.3-38213.6"
wire width 2 $1\dec31_dec_sub9_rc_sel[1:0]
- attribute \src "libresoc.v:38463.3-38517.6"
+ attribute \src "libresoc.v:38654.3-38708.6"
wire $1\dec31_dec_sub9_rsrv[0:0]
- attribute \src "libresoc.v:38683.3-38737.6"
+ attribute \src "libresoc.v:38874.3-38928.6"
wire $1\dec31_dec_sub9_sgl_pipe[0:0]
- attribute \src "libresoc.v:38573.3-38627.6"
+ attribute \src "libresoc.v:38764.3-38818.6"
wire $1\dec31_dec_sub9_sgn[0:0]
- attribute \src "libresoc.v:38353.3-38407.6"
+ attribute \src "libresoc.v:38544.3-38598.6"
wire $1\dec31_dec_sub9_sgn_ext[0:0]
- attribute \src "libresoc.v:37913.3-37967.6"
+ attribute \src "libresoc.v:38104.3-38158.6"
wire width 2 $1\dec31_dec_sub9_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec31_dec_sub9_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec31_dec_sub9_upd
- attribute \src "libresoc.v:37546.7-37546.15"
+ attribute \src "libresoc.v:37737.7-37737.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 5 \opcode_switch
- attribute \src "libresoc.v:37546.7-37546.20"
- process $proc$libresoc.v:37546$816
+ attribute \src "libresoc.v:37737.7-37737.20"
+ process $proc$libresoc.v:37737$856
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:37803.3-37857.6"
- process $proc$libresoc.v:37803$792
+ attribute \src "libresoc.v:37994.3-38048.6"
+ process $proc$libresoc.v:37994$832
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0]
- attribute \src "libresoc.v:37804.5-37804.29"
+ attribute \src "libresoc.v:37995.5-37995.29"
switch \initial
- attribute \src "libresoc.v:37804.9-37804.17"
+ attribute \src "libresoc.v:37995.9-37995.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0]
end
- attribute \src "libresoc.v:37858.3-37912.6"
- process $proc$libresoc.v:37858$793
+ attribute \src "libresoc.v:38049.3-38103.6"
+ process $proc$libresoc.v:38049$833
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0]
- attribute \src "libresoc.v:37859.5-37859.29"
+ attribute \src "libresoc.v:38050.5-38050.29"
switch \initial
- attribute \src "libresoc.v:37859.9-37859.17"
+ attribute \src "libresoc.v:38050.9-38050.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0]
end
- attribute \src "libresoc.v:37913.3-37967.6"
- process $proc$libresoc.v:37913$794
+ attribute \src "libresoc.v:38104.3-38158.6"
+ process $proc$libresoc.v:38104$834
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0]
- attribute \src "libresoc.v:37914.5-37914.29"
+ attribute \src "libresoc.v:38105.5-38105.29"
switch \initial
- attribute \src "libresoc.v:37914.9-37914.17"
+ attribute \src "libresoc.v:38105.9-38105.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0]
end
- attribute \src "libresoc.v:37968.3-38022.6"
- process $proc$libresoc.v:37968$795
+ attribute \src "libresoc.v:38159.3-38213.6"
+ process $proc$libresoc.v:38159$835
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0]
- attribute \src "libresoc.v:37969.5-37969.29"
+ attribute \src "libresoc.v:38160.5-38160.29"
switch \initial
- attribute \src "libresoc.v:37969.9-37969.17"
+ attribute \src "libresoc.v:38160.9-38160.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0]
end
- attribute \src "libresoc.v:38023.3-38077.6"
- process $proc$libresoc.v:38023$796
+ attribute \src "libresoc.v:38214.3-38268.6"
+ process $proc$libresoc.v:38214$836
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0]
- attribute \src "libresoc.v:38024.5-38024.29"
+ attribute \src "libresoc.v:38215.5-38215.29"
switch \initial
- attribute \src "libresoc.v:38024.9-38024.17"
+ attribute \src "libresoc.v:38215.9-38215.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0]
end
- attribute \src "libresoc.v:38078.3-38132.6"
- process $proc$libresoc.v:38078$797
+ attribute \src "libresoc.v:38269.3-38323.6"
+ process $proc$libresoc.v:38269$837
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0]
- attribute \src "libresoc.v:38079.5-38079.29"
+ attribute \src "libresoc.v:38270.5-38270.29"
switch \initial
- attribute \src "libresoc.v:38079.9-38079.17"
+ attribute \src "libresoc.v:38270.9-38270.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0]
end
- attribute \src "libresoc.v:38133.3-38187.6"
- process $proc$libresoc.v:38133$798
+ attribute \src "libresoc.v:38324.3-38378.6"
+ process $proc$libresoc.v:38324$838
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0]
- attribute \src "libresoc.v:38134.5-38134.29"
+ attribute \src "libresoc.v:38325.5-38325.29"
switch \initial
- attribute \src "libresoc.v:38134.9-38134.17"
+ attribute \src "libresoc.v:38325.9-38325.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0]
end
- attribute \src "libresoc.v:38188.3-38242.6"
- process $proc$libresoc.v:38188$799
+ attribute \src "libresoc.v:38379.3-38433.6"
+ process $proc$libresoc.v:38379$839
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0]
- attribute \src "libresoc.v:38189.5-38189.29"
+ attribute \src "libresoc.v:38380.5-38380.29"
switch \initial
- attribute \src "libresoc.v:38189.9-38189.17"
+ attribute \src "libresoc.v:38380.9-38380.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0]
end
- attribute \src "libresoc.v:38243.3-38297.6"
- process $proc$libresoc.v:38243$800
+ attribute \src "libresoc.v:38434.3-38488.6"
+ process $proc$libresoc.v:38434$840
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0]
- attribute \src "libresoc.v:38244.5-38244.29"
+ attribute \src "libresoc.v:38435.5-38435.29"
switch \initial
- attribute \src "libresoc.v:38244.9-38244.17"
+ attribute \src "libresoc.v:38435.9-38435.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0]
end
- attribute \src "libresoc.v:38298.3-38352.6"
- process $proc$libresoc.v:38298$801
+ attribute \src "libresoc.v:38489.3-38543.6"
+ process $proc$libresoc.v:38489$841
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0]
- attribute \src "libresoc.v:38299.5-38299.29"
+ attribute \src "libresoc.v:38490.5-38490.29"
switch \initial
- attribute \src "libresoc.v:38299.9-38299.17"
+ attribute \src "libresoc.v:38490.9-38490.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0]
end
- attribute \src "libresoc.v:38353.3-38407.6"
- process $proc$libresoc.v:38353$802
+ attribute \src "libresoc.v:38544.3-38598.6"
+ process $proc$libresoc.v:38544$842
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0]
- attribute \src "libresoc.v:38354.5-38354.29"
+ attribute \src "libresoc.v:38545.5-38545.29"
switch \initial
- attribute \src "libresoc.v:38354.9-38354.17"
+ attribute \src "libresoc.v:38545.9-38545.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0]
end
- attribute \src "libresoc.v:38408.3-38462.6"
- process $proc$libresoc.v:38408$803
+ attribute \src "libresoc.v:38599.3-38653.6"
+ process $proc$libresoc.v:38599$843
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0]
- attribute \src "libresoc.v:38409.5-38409.29"
+ attribute \src "libresoc.v:38600.5-38600.29"
switch \initial
- attribute \src "libresoc.v:38409.9-38409.17"
+ attribute \src "libresoc.v:38600.9-38600.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0]
end
- attribute \src "libresoc.v:38463.3-38517.6"
- process $proc$libresoc.v:38463$804
+ attribute \src "libresoc.v:38654.3-38708.6"
+ process $proc$libresoc.v:38654$844
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0]
- attribute \src "libresoc.v:38464.5-38464.29"
+ attribute \src "libresoc.v:38655.5-38655.29"
switch \initial
- attribute \src "libresoc.v:38464.9-38464.17"
+ attribute \src "libresoc.v:38655.9-38655.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0]
end
- attribute \src "libresoc.v:38518.3-38572.6"
- process $proc$libresoc.v:38518$805
+ attribute \src "libresoc.v:38709.3-38763.6"
+ process $proc$libresoc.v:38709$845
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0]
- attribute \src "libresoc.v:38519.5-38519.29"
+ attribute \src "libresoc.v:38710.5-38710.29"
switch \initial
- attribute \src "libresoc.v:38519.9-38519.17"
+ attribute \src "libresoc.v:38710.9-38710.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0]
end
- attribute \src "libresoc.v:38573.3-38627.6"
- process $proc$libresoc.v:38573$806
+ attribute \src "libresoc.v:38764.3-38818.6"
+ process $proc$libresoc.v:38764$846
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0]
- attribute \src "libresoc.v:38574.5-38574.29"
+ attribute \src "libresoc.v:38765.5-38765.29"
switch \initial
- attribute \src "libresoc.v:38574.9-38574.17"
+ attribute \src "libresoc.v:38765.9-38765.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0]
end
- attribute \src "libresoc.v:38628.3-38682.6"
- process $proc$libresoc.v:38628$807
+ attribute \src "libresoc.v:38819.3-38873.6"
+ process $proc$libresoc.v:38819$847
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0]
- attribute \src "libresoc.v:38629.5-38629.29"
+ attribute \src "libresoc.v:38820.5-38820.29"
switch \initial
- attribute \src "libresoc.v:38629.9-38629.17"
+ attribute \src "libresoc.v:38820.9-38820.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0]
end
- attribute \src "libresoc.v:38683.3-38737.6"
- process $proc$libresoc.v:38683$808
+ attribute \src "libresoc.v:38874.3-38928.6"
+ process $proc$libresoc.v:38874$848
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0]
- attribute \src "libresoc.v:38684.5-38684.29"
+ attribute \src "libresoc.v:38875.5-38875.29"
switch \initial
- attribute \src "libresoc.v:38684.9-38684.17"
+ attribute \src "libresoc.v:38875.9-38875.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:38738.3-38792.6"
- process $proc$libresoc.v:38738$809
+ attribute \src "libresoc.v:38929.3-38983.6"
+ process $proc$libresoc.v:38929$849
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0]
- attribute \src "libresoc.v:38739.5-38739.29"
+ attribute \src "libresoc.v:38930.5-38930.29"
switch \initial
- attribute \src "libresoc.v:38739.9-38739.17"
+ attribute \src "libresoc.v:38930.9-38930.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0]
end
- attribute \src "libresoc.v:38793.3-38847.6"
- process $proc$libresoc.v:38793$810
+ attribute \src "libresoc.v:38984.3-39038.6"
+ process $proc$libresoc.v:38984$850
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0]
- attribute \src "libresoc.v:38794.5-38794.29"
+ attribute \src "libresoc.v:38985.5-38985.29"
switch \initial
- attribute \src "libresoc.v:38794.9-38794.17"
+ attribute \src "libresoc.v:38985.9-38985.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0]
end
- attribute \src "libresoc.v:38848.3-38902.6"
- process $proc$libresoc.v:38848$811
+ attribute \src "libresoc.v:39039.3-39093.6"
+ process $proc$libresoc.v:39039$851
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0]
- attribute \src "libresoc.v:38849.5-38849.29"
+ attribute \src "libresoc.v:39040.5-39040.29"
switch \initial
- attribute \src "libresoc.v:38849.9-38849.17"
+ attribute \src "libresoc.v:39040.9-39040.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0]
end
- attribute \src "libresoc.v:38903.3-38957.6"
- process $proc$libresoc.v:38903$812
+ attribute \src "libresoc.v:39094.3-39148.6"
+ process $proc$libresoc.v:39094$852
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0]
- attribute \src "libresoc.v:38904.5-38904.29"
+ attribute \src "libresoc.v:39095.5-39095.29"
switch \initial
- attribute \src "libresoc.v:38904.9-38904.17"
+ attribute \src "libresoc.v:39095.9-39095.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0]
end
- attribute \src "libresoc.v:38958.3-39012.6"
- process $proc$libresoc.v:38958$813
+ attribute \src "libresoc.v:39149.3-39203.6"
+ process $proc$libresoc.v:39149$853
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0]
- attribute \src "libresoc.v:38959.5-38959.29"
+ attribute \src "libresoc.v:39150.5-39150.29"
switch \initial
- attribute \src "libresoc.v:38959.9-38959.17"
+ attribute \src "libresoc.v:39150.9-39150.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0]
end
- attribute \src "libresoc.v:39013.3-39067.6"
- process $proc$libresoc.v:39013$814
+ attribute \src "libresoc.v:39204.3-39258.6"
+ process $proc$libresoc.v:39204$854
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0]
- attribute \src "libresoc.v:39014.5-39014.29"
+ attribute \src "libresoc.v:39205.5-39205.29"
switch \initial
- attribute \src "libresoc.v:39014.9-39014.17"
+ attribute \src "libresoc.v:39205.9-39205.17"
case 1'1
case
end
sync always
update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0]
end
- attribute \src "libresoc.v:39068.3-39122.6"
- process $proc$libresoc.v:39068$815
+ attribute \src "libresoc.v:39259.3-39313.6"
+ process $proc$libresoc.v:39259$855
assign { } { }
assign { } { }
assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0]
- attribute \src "libresoc.v:39069.5-39069.29"
+ attribute \src "libresoc.v:39260.5-39260.29"
switch \initial
- attribute \src "libresoc.v:39069.9-39069.17"
+ attribute \src "libresoc.v:39260.9-39260.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [10:6]
end
-attribute \src "libresoc.v:39128.1-39771.10"
+attribute \src "libresoc.v:39319.1-39962.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec58"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58"
attribute \generator "nMigen"
module \dec58
- attribute \src "libresoc.v:39466.3-39481.6"
+ attribute \src "libresoc.v:39657.3-39672.6"
wire width 8 $0\dec58_asmcode[7:0]
- attribute \src "libresoc.v:39530.3-39545.6"
+ attribute \src "libresoc.v:39721.3-39736.6"
wire $0\dec58_br[0:0]
- attribute \src "libresoc.v:39738.3-39753.6"
+ attribute \src "libresoc.v:39929.3-39944.6"
wire width 3 $0\dec58_cr_in[2:0]
- attribute \src "libresoc.v:39754.3-39769.6"
+ attribute \src "libresoc.v:39945.3-39960.6"
wire width 3 $0\dec58_cr_out[2:0]
- attribute \src "libresoc.v:39450.3-39465.6"
+ attribute \src "libresoc.v:39641.3-39656.6"
wire width 2 $0\dec58_cry_in[1:0]
- attribute \src "libresoc.v:39514.3-39529.6"
+ attribute \src "libresoc.v:39705.3-39720.6"
wire $0\dec58_cry_out[0:0]
- attribute \src "libresoc.v:39658.3-39673.6"
+ attribute \src "libresoc.v:39849.3-39864.6"
wire width 5 $0\dec58_form[4:0]
- attribute \src "libresoc.v:39386.3-39401.6"
+ attribute \src "libresoc.v:39577.3-39592.6"
wire width 12 $0\dec58_function_unit[11:0]
- attribute \src "libresoc.v:39674.3-39689.6"
+ attribute \src "libresoc.v:39865.3-39880.6"
wire width 3 $0\dec58_in1_sel[2:0]
- attribute \src "libresoc.v:39690.3-39705.6"
+ attribute \src "libresoc.v:39881.3-39896.6"
wire width 4 $0\dec58_in2_sel[3:0]
- attribute \src "libresoc.v:39706.3-39721.6"
+ attribute \src "libresoc.v:39897.3-39912.6"
wire width 2 $0\dec58_in3_sel[1:0]
- attribute \src "libresoc.v:39562.3-39577.6"
+ attribute \src "libresoc.v:39753.3-39768.6"
wire width 7 $0\dec58_internal_op[6:0]
- attribute \src "libresoc.v:39482.3-39497.6"
+ attribute \src "libresoc.v:39673.3-39688.6"
wire $0\dec58_inv_a[0:0]
- attribute \src "libresoc.v:39498.3-39513.6"
+ attribute \src "libresoc.v:39689.3-39704.6"
wire $0\dec58_inv_out[0:0]
- attribute \src "libresoc.v:39594.3-39609.6"
+ attribute \src "libresoc.v:39785.3-39800.6"
wire $0\dec58_is_32b[0:0]
- attribute \src "libresoc.v:39402.3-39417.6"
+ attribute \src "libresoc.v:39593.3-39608.6"
wire width 4 $0\dec58_ldst_len[3:0]
- attribute \src "libresoc.v:39626.3-39641.6"
+ attribute \src "libresoc.v:39817.3-39832.6"
wire $0\dec58_lk[0:0]
- attribute \src "libresoc.v:39722.3-39737.6"
+ attribute \src "libresoc.v:39913.3-39928.6"
wire width 2 $0\dec58_out_sel[1:0]
- attribute \src "libresoc.v:39434.3-39449.6"
+ attribute \src "libresoc.v:39625.3-39640.6"
wire width 2 $0\dec58_rc_sel[1:0]
- attribute \src "libresoc.v:39578.3-39593.6"
+ attribute \src "libresoc.v:39769.3-39784.6"
wire $0\dec58_rsrv[0:0]
- attribute \src "libresoc.v:39642.3-39657.6"
+ attribute \src "libresoc.v:39833.3-39848.6"
wire $0\dec58_sgl_pipe[0:0]
- attribute \src "libresoc.v:39610.3-39625.6"
+ attribute \src "libresoc.v:39801.3-39816.6"
wire $0\dec58_sgn[0:0]
- attribute \src "libresoc.v:39546.3-39561.6"
+ attribute \src "libresoc.v:39737.3-39752.6"
wire $0\dec58_sgn_ext[0:0]
- attribute \src "libresoc.v:39418.3-39433.6"
+ attribute \src "libresoc.v:39609.3-39624.6"
wire width 2 $0\dec58_upd[1:0]
- attribute \src "libresoc.v:39129.7-39129.20"
+ attribute \src "libresoc.v:39320.7-39320.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:39466.3-39481.6"
+ attribute \src "libresoc.v:39657.3-39672.6"
wire width 8 $1\dec58_asmcode[7:0]
- attribute \src "libresoc.v:39530.3-39545.6"
+ attribute \src "libresoc.v:39721.3-39736.6"
wire $1\dec58_br[0:0]
- attribute \src "libresoc.v:39738.3-39753.6"
+ attribute \src "libresoc.v:39929.3-39944.6"
wire width 3 $1\dec58_cr_in[2:0]
- attribute \src "libresoc.v:39754.3-39769.6"
+ attribute \src "libresoc.v:39945.3-39960.6"
wire width 3 $1\dec58_cr_out[2:0]
- attribute \src "libresoc.v:39450.3-39465.6"
+ attribute \src "libresoc.v:39641.3-39656.6"
wire width 2 $1\dec58_cry_in[1:0]
- attribute \src "libresoc.v:39514.3-39529.6"
+ attribute \src "libresoc.v:39705.3-39720.6"
wire $1\dec58_cry_out[0:0]
- attribute \src "libresoc.v:39658.3-39673.6"
+ attribute \src "libresoc.v:39849.3-39864.6"
wire width 5 $1\dec58_form[4:0]
- attribute \src "libresoc.v:39386.3-39401.6"
+ attribute \src "libresoc.v:39577.3-39592.6"
wire width 12 $1\dec58_function_unit[11:0]
- attribute \src "libresoc.v:39674.3-39689.6"
+ attribute \src "libresoc.v:39865.3-39880.6"
wire width 3 $1\dec58_in1_sel[2:0]
- attribute \src "libresoc.v:39690.3-39705.6"
+ attribute \src "libresoc.v:39881.3-39896.6"
wire width 4 $1\dec58_in2_sel[3:0]
- attribute \src "libresoc.v:39706.3-39721.6"
+ attribute \src "libresoc.v:39897.3-39912.6"
wire width 2 $1\dec58_in3_sel[1:0]
- attribute \src "libresoc.v:39562.3-39577.6"
+ attribute \src "libresoc.v:39753.3-39768.6"
wire width 7 $1\dec58_internal_op[6:0]
- attribute \src "libresoc.v:39482.3-39497.6"
+ attribute \src "libresoc.v:39673.3-39688.6"
wire $1\dec58_inv_a[0:0]
- attribute \src "libresoc.v:39498.3-39513.6"
+ attribute \src "libresoc.v:39689.3-39704.6"
wire $1\dec58_inv_out[0:0]
- attribute \src "libresoc.v:39594.3-39609.6"
+ attribute \src "libresoc.v:39785.3-39800.6"
wire $1\dec58_is_32b[0:0]
- attribute \src "libresoc.v:39402.3-39417.6"
+ attribute \src "libresoc.v:39593.3-39608.6"
wire width 4 $1\dec58_ldst_len[3:0]
- attribute \src "libresoc.v:39626.3-39641.6"
+ attribute \src "libresoc.v:39817.3-39832.6"
wire $1\dec58_lk[0:0]
- attribute \src "libresoc.v:39722.3-39737.6"
+ attribute \src "libresoc.v:39913.3-39928.6"
wire width 2 $1\dec58_out_sel[1:0]
- attribute \src "libresoc.v:39434.3-39449.6"
+ attribute \src "libresoc.v:39625.3-39640.6"
wire width 2 $1\dec58_rc_sel[1:0]
- attribute \src "libresoc.v:39578.3-39593.6"
+ attribute \src "libresoc.v:39769.3-39784.6"
wire $1\dec58_rsrv[0:0]
- attribute \src "libresoc.v:39642.3-39657.6"
+ attribute \src "libresoc.v:39833.3-39848.6"
wire $1\dec58_sgl_pipe[0:0]
- attribute \src "libresoc.v:39610.3-39625.6"
+ attribute \src "libresoc.v:39801.3-39816.6"
wire $1\dec58_sgn[0:0]
- attribute \src "libresoc.v:39546.3-39561.6"
+ attribute \src "libresoc.v:39737.3-39752.6"
wire $1\dec58_sgn_ext[0:0]
- attribute \src "libresoc.v:39418.3-39433.6"
+ attribute \src "libresoc.v:39609.3-39624.6"
wire width 2 $1\dec58_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec58_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec58_upd
- attribute \src "libresoc.v:39129.7-39129.15"
+ attribute \src "libresoc.v:39320.7-39320.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 2 \opcode_switch
- attribute \src "libresoc.v:39129.7-39129.20"
- process $proc$libresoc.v:39129$841
+ attribute \src "libresoc.v:39320.7-39320.20"
+ process $proc$libresoc.v:39320$881
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:39386.3-39401.6"
- process $proc$libresoc.v:39386$817
+ attribute \src "libresoc.v:39577.3-39592.6"
+ process $proc$libresoc.v:39577$857
assign { } { }
assign { } { }
assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0]
- attribute \src "libresoc.v:39387.5-39387.29"
+ attribute \src "libresoc.v:39578.5-39578.29"
switch \initial
- attribute \src "libresoc.v:39387.9-39387.17"
+ attribute \src "libresoc.v:39578.9-39578.17"
case 1'1
case
end
sync always
update \dec58_function_unit $0\dec58_function_unit[11:0]
end
- attribute \src "libresoc.v:39402.3-39417.6"
- process $proc$libresoc.v:39402$818
+ attribute \src "libresoc.v:39593.3-39608.6"
+ process $proc$libresoc.v:39593$858
assign { } { }
assign { } { }
assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0]
- attribute \src "libresoc.v:39403.5-39403.29"
+ attribute \src "libresoc.v:39594.5-39594.29"
switch \initial
- attribute \src "libresoc.v:39403.9-39403.17"
+ attribute \src "libresoc.v:39594.9-39594.17"
case 1'1
case
end
sync always
update \dec58_ldst_len $0\dec58_ldst_len[3:0]
end
- attribute \src "libresoc.v:39418.3-39433.6"
- process $proc$libresoc.v:39418$819
+ attribute \src "libresoc.v:39609.3-39624.6"
+ process $proc$libresoc.v:39609$859
assign { } { }
assign { } { }
assign $0\dec58_upd[1:0] $1\dec58_upd[1:0]
- attribute \src "libresoc.v:39419.5-39419.29"
+ attribute \src "libresoc.v:39610.5-39610.29"
switch \initial
- attribute \src "libresoc.v:39419.9-39419.17"
+ attribute \src "libresoc.v:39610.9-39610.17"
case 1'1
case
end
sync always
update \dec58_upd $0\dec58_upd[1:0]
end
- attribute \src "libresoc.v:39434.3-39449.6"
- process $proc$libresoc.v:39434$820
+ attribute \src "libresoc.v:39625.3-39640.6"
+ process $proc$libresoc.v:39625$860
assign { } { }
assign { } { }
assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0]
- attribute \src "libresoc.v:39435.5-39435.29"
+ attribute \src "libresoc.v:39626.5-39626.29"
switch \initial
- attribute \src "libresoc.v:39435.9-39435.17"
+ attribute \src "libresoc.v:39626.9-39626.17"
case 1'1
case
end
sync always
update \dec58_rc_sel $0\dec58_rc_sel[1:0]
end
- attribute \src "libresoc.v:39450.3-39465.6"
- process $proc$libresoc.v:39450$821
+ attribute \src "libresoc.v:39641.3-39656.6"
+ process $proc$libresoc.v:39641$861
assign { } { }
assign { } { }
assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0]
- attribute \src "libresoc.v:39451.5-39451.29"
+ attribute \src "libresoc.v:39642.5-39642.29"
switch \initial
- attribute \src "libresoc.v:39451.9-39451.17"
+ attribute \src "libresoc.v:39642.9-39642.17"
case 1'1
case
end
sync always
update \dec58_cry_in $0\dec58_cry_in[1:0]
end
- attribute \src "libresoc.v:39466.3-39481.6"
- process $proc$libresoc.v:39466$822
+ attribute \src "libresoc.v:39657.3-39672.6"
+ process $proc$libresoc.v:39657$862
assign { } { }
assign { } { }
assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0]
- attribute \src "libresoc.v:39467.5-39467.29"
+ attribute \src "libresoc.v:39658.5-39658.29"
switch \initial
- attribute \src "libresoc.v:39467.9-39467.17"
+ attribute \src "libresoc.v:39658.9-39658.17"
case 1'1
case
end
sync always
update \dec58_asmcode $0\dec58_asmcode[7:0]
end
- attribute \src "libresoc.v:39482.3-39497.6"
- process $proc$libresoc.v:39482$823
+ attribute \src "libresoc.v:39673.3-39688.6"
+ process $proc$libresoc.v:39673$863
assign { } { }
assign { } { }
assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0]
- attribute \src "libresoc.v:39483.5-39483.29"
+ attribute \src "libresoc.v:39674.5-39674.29"
switch \initial
- attribute \src "libresoc.v:39483.9-39483.17"
+ attribute \src "libresoc.v:39674.9-39674.17"
case 1'1
case
end
sync always
update \dec58_inv_a $0\dec58_inv_a[0:0]
end
- attribute \src "libresoc.v:39498.3-39513.6"
- process $proc$libresoc.v:39498$824
+ attribute \src "libresoc.v:39689.3-39704.6"
+ process $proc$libresoc.v:39689$864
assign { } { }
assign { } { }
assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0]
- attribute \src "libresoc.v:39499.5-39499.29"
+ attribute \src "libresoc.v:39690.5-39690.29"
switch \initial
- attribute \src "libresoc.v:39499.9-39499.17"
+ attribute \src "libresoc.v:39690.9-39690.17"
case 1'1
case
end
sync always
update \dec58_inv_out $0\dec58_inv_out[0:0]
end
- attribute \src "libresoc.v:39514.3-39529.6"
- process $proc$libresoc.v:39514$825
+ attribute \src "libresoc.v:39705.3-39720.6"
+ process $proc$libresoc.v:39705$865
assign { } { }
assign { } { }
assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0]
- attribute \src "libresoc.v:39515.5-39515.29"
+ attribute \src "libresoc.v:39706.5-39706.29"
switch \initial
- attribute \src "libresoc.v:39515.9-39515.17"
+ attribute \src "libresoc.v:39706.9-39706.17"
case 1'1
case
end
sync always
update \dec58_cry_out $0\dec58_cry_out[0:0]
end
- attribute \src "libresoc.v:39530.3-39545.6"
- process $proc$libresoc.v:39530$826
+ attribute \src "libresoc.v:39721.3-39736.6"
+ process $proc$libresoc.v:39721$866
assign { } { }
assign { } { }
assign $0\dec58_br[0:0] $1\dec58_br[0:0]
- attribute \src "libresoc.v:39531.5-39531.29"
+ attribute \src "libresoc.v:39722.5-39722.29"
switch \initial
- attribute \src "libresoc.v:39531.9-39531.17"
+ attribute \src "libresoc.v:39722.9-39722.17"
case 1'1
case
end
sync always
update \dec58_br $0\dec58_br[0:0]
end
- attribute \src "libresoc.v:39546.3-39561.6"
- process $proc$libresoc.v:39546$827
+ attribute \src "libresoc.v:39737.3-39752.6"
+ process $proc$libresoc.v:39737$867
assign { } { }
assign { } { }
assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0]
- attribute \src "libresoc.v:39547.5-39547.29"
+ attribute \src "libresoc.v:39738.5-39738.29"
switch \initial
- attribute \src "libresoc.v:39547.9-39547.17"
+ attribute \src "libresoc.v:39738.9-39738.17"
case 1'1
case
end
sync always
update \dec58_sgn_ext $0\dec58_sgn_ext[0:0]
end
- attribute \src "libresoc.v:39562.3-39577.6"
- process $proc$libresoc.v:39562$828
+ attribute \src "libresoc.v:39753.3-39768.6"
+ process $proc$libresoc.v:39753$868
assign { } { }
assign { } { }
assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0]
- attribute \src "libresoc.v:39563.5-39563.29"
+ attribute \src "libresoc.v:39754.5-39754.29"
switch \initial
- attribute \src "libresoc.v:39563.9-39563.17"
+ attribute \src "libresoc.v:39754.9-39754.17"
case 1'1
case
end
sync always
update \dec58_internal_op $0\dec58_internal_op[6:0]
end
- attribute \src "libresoc.v:39578.3-39593.6"
- process $proc$libresoc.v:39578$829
+ attribute \src "libresoc.v:39769.3-39784.6"
+ process $proc$libresoc.v:39769$869
assign { } { }
assign { } { }
assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0]
- attribute \src "libresoc.v:39579.5-39579.29"
+ attribute \src "libresoc.v:39770.5-39770.29"
switch \initial
- attribute \src "libresoc.v:39579.9-39579.17"
+ attribute \src "libresoc.v:39770.9-39770.17"
case 1'1
case
end
sync always
update \dec58_rsrv $0\dec58_rsrv[0:0]
end
- attribute \src "libresoc.v:39594.3-39609.6"
- process $proc$libresoc.v:39594$830
+ attribute \src "libresoc.v:39785.3-39800.6"
+ process $proc$libresoc.v:39785$870
assign { } { }
assign { } { }
assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0]
- attribute \src "libresoc.v:39595.5-39595.29"
+ attribute \src "libresoc.v:39786.5-39786.29"
switch \initial
- attribute \src "libresoc.v:39595.9-39595.17"
+ attribute \src "libresoc.v:39786.9-39786.17"
case 1'1
case
end
sync always
update \dec58_is_32b $0\dec58_is_32b[0:0]
end
- attribute \src "libresoc.v:39610.3-39625.6"
- process $proc$libresoc.v:39610$831
+ attribute \src "libresoc.v:39801.3-39816.6"
+ process $proc$libresoc.v:39801$871
assign { } { }
assign { } { }
assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0]
- attribute \src "libresoc.v:39611.5-39611.29"
+ attribute \src "libresoc.v:39802.5-39802.29"
switch \initial
- attribute \src "libresoc.v:39611.9-39611.17"
+ attribute \src "libresoc.v:39802.9-39802.17"
case 1'1
case
end
sync always
update \dec58_sgn $0\dec58_sgn[0:0]
end
- attribute \src "libresoc.v:39626.3-39641.6"
- process $proc$libresoc.v:39626$832
+ attribute \src "libresoc.v:39817.3-39832.6"
+ process $proc$libresoc.v:39817$872
assign { } { }
assign { } { }
assign $0\dec58_lk[0:0] $1\dec58_lk[0:0]
- attribute \src "libresoc.v:39627.5-39627.29"
+ attribute \src "libresoc.v:39818.5-39818.29"
switch \initial
- attribute \src "libresoc.v:39627.9-39627.17"
+ attribute \src "libresoc.v:39818.9-39818.17"
case 1'1
case
end
sync always
update \dec58_lk $0\dec58_lk[0:0]
end
- attribute \src "libresoc.v:39642.3-39657.6"
- process $proc$libresoc.v:39642$833
+ attribute \src "libresoc.v:39833.3-39848.6"
+ process $proc$libresoc.v:39833$873
assign { } { }
assign { } { }
assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0]
- attribute \src "libresoc.v:39643.5-39643.29"
+ attribute \src "libresoc.v:39834.5-39834.29"
switch \initial
- attribute \src "libresoc.v:39643.9-39643.17"
+ attribute \src "libresoc.v:39834.9-39834.17"
case 1'1
case
end
sync always
update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:39658.3-39673.6"
- process $proc$libresoc.v:39658$834
+ attribute \src "libresoc.v:39849.3-39864.6"
+ process $proc$libresoc.v:39849$874
assign { } { }
assign { } { }
assign $0\dec58_form[4:0] $1\dec58_form[4:0]
- attribute \src "libresoc.v:39659.5-39659.29"
+ attribute \src "libresoc.v:39850.5-39850.29"
switch \initial
- attribute \src "libresoc.v:39659.9-39659.17"
+ attribute \src "libresoc.v:39850.9-39850.17"
case 1'1
case
end
sync always
update \dec58_form $0\dec58_form[4:0]
end
- attribute \src "libresoc.v:39674.3-39689.6"
- process $proc$libresoc.v:39674$835
+ attribute \src "libresoc.v:39865.3-39880.6"
+ process $proc$libresoc.v:39865$875
assign { } { }
assign { } { }
assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0]
- attribute \src "libresoc.v:39675.5-39675.29"
+ attribute \src "libresoc.v:39866.5-39866.29"
switch \initial
- attribute \src "libresoc.v:39675.9-39675.17"
+ attribute \src "libresoc.v:39866.9-39866.17"
case 1'1
case
end
sync always
update \dec58_in1_sel $0\dec58_in1_sel[2:0]
end
- attribute \src "libresoc.v:39690.3-39705.6"
- process $proc$libresoc.v:39690$836
+ attribute \src "libresoc.v:39881.3-39896.6"
+ process $proc$libresoc.v:39881$876
assign { } { }
assign { } { }
assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0]
- attribute \src "libresoc.v:39691.5-39691.29"
+ attribute \src "libresoc.v:39882.5-39882.29"
switch \initial
- attribute \src "libresoc.v:39691.9-39691.17"
+ attribute \src "libresoc.v:39882.9-39882.17"
case 1'1
case
end
sync always
update \dec58_in2_sel $0\dec58_in2_sel[3:0]
end
- attribute \src "libresoc.v:39706.3-39721.6"
- process $proc$libresoc.v:39706$837
+ attribute \src "libresoc.v:39897.3-39912.6"
+ process $proc$libresoc.v:39897$877
assign { } { }
assign { } { }
assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0]
- attribute \src "libresoc.v:39707.5-39707.29"
+ attribute \src "libresoc.v:39898.5-39898.29"
switch \initial
- attribute \src "libresoc.v:39707.9-39707.17"
+ attribute \src "libresoc.v:39898.9-39898.17"
case 1'1
case
end
sync always
update \dec58_in3_sel $0\dec58_in3_sel[1:0]
end
- attribute \src "libresoc.v:39722.3-39737.6"
- process $proc$libresoc.v:39722$838
+ attribute \src "libresoc.v:39913.3-39928.6"
+ process $proc$libresoc.v:39913$878
assign { } { }
assign { } { }
assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0]
- attribute \src "libresoc.v:39723.5-39723.29"
+ attribute \src "libresoc.v:39914.5-39914.29"
switch \initial
- attribute \src "libresoc.v:39723.9-39723.17"
+ attribute \src "libresoc.v:39914.9-39914.17"
case 1'1
case
end
sync always
update \dec58_out_sel $0\dec58_out_sel[1:0]
end
- attribute \src "libresoc.v:39738.3-39753.6"
- process $proc$libresoc.v:39738$839
+ attribute \src "libresoc.v:39929.3-39944.6"
+ process $proc$libresoc.v:39929$879
assign { } { }
assign { } { }
assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0]
- attribute \src "libresoc.v:39739.5-39739.29"
+ attribute \src "libresoc.v:39930.5-39930.29"
switch \initial
- attribute \src "libresoc.v:39739.9-39739.17"
+ attribute \src "libresoc.v:39930.9-39930.17"
case 1'1
case
end
sync always
update \dec58_cr_in $0\dec58_cr_in[2:0]
end
- attribute \src "libresoc.v:39754.3-39769.6"
- process $proc$libresoc.v:39754$840
+ attribute \src "libresoc.v:39945.3-39960.6"
+ process $proc$libresoc.v:39945$880
assign { } { }
assign { } { }
assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0]
- attribute \src "libresoc.v:39755.5-39755.29"
+ attribute \src "libresoc.v:39946.5-39946.29"
switch \initial
- attribute \src "libresoc.v:39755.9-39755.17"
+ attribute \src "libresoc.v:39946.9-39946.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [1:0]
end
-attribute \src "libresoc.v:39775.1-40346.10"
+attribute \src "libresoc.v:39966.1-40537.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec62"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62"
attribute \generator "nMigen"
module \dec62
- attribute \src "libresoc.v:40098.3-40110.6"
+ attribute \src "libresoc.v:40289.3-40301.6"
wire width 8 $0\dec62_asmcode[7:0]
- attribute \src "libresoc.v:40150.3-40162.6"
+ attribute \src "libresoc.v:40341.3-40353.6"
wire $0\dec62_br[0:0]
- attribute \src "libresoc.v:40319.3-40331.6"
+ attribute \src "libresoc.v:40510.3-40522.6"
wire width 3 $0\dec62_cr_in[2:0]
- attribute \src "libresoc.v:40332.3-40344.6"
+ attribute \src "libresoc.v:40523.3-40535.6"
wire width 3 $0\dec62_cr_out[2:0]
- attribute \src "libresoc.v:40085.3-40097.6"
+ attribute \src "libresoc.v:40276.3-40288.6"
wire width 2 $0\dec62_cry_in[1:0]
- attribute \src "libresoc.v:40137.3-40149.6"
+ attribute \src "libresoc.v:40328.3-40340.6"
wire $0\dec62_cry_out[0:0]
- attribute \src "libresoc.v:40254.3-40266.6"
+ attribute \src "libresoc.v:40445.3-40457.6"
wire width 5 $0\dec62_form[4:0]
- attribute \src "libresoc.v:40033.3-40045.6"
+ attribute \src "libresoc.v:40224.3-40236.6"
wire width 12 $0\dec62_function_unit[11:0]
- attribute \src "libresoc.v:40267.3-40279.6"
+ attribute \src "libresoc.v:40458.3-40470.6"
wire width 3 $0\dec62_in1_sel[2:0]
- attribute \src "libresoc.v:40280.3-40292.6"
+ attribute \src "libresoc.v:40471.3-40483.6"
wire width 4 $0\dec62_in2_sel[3:0]
- attribute \src "libresoc.v:40293.3-40305.6"
+ attribute \src "libresoc.v:40484.3-40496.6"
wire width 2 $0\dec62_in3_sel[1:0]
- attribute \src "libresoc.v:40176.3-40188.6"
+ attribute \src "libresoc.v:40367.3-40379.6"
wire width 7 $0\dec62_internal_op[6:0]
- attribute \src "libresoc.v:40111.3-40123.6"
+ attribute \src "libresoc.v:40302.3-40314.6"
wire $0\dec62_inv_a[0:0]
- attribute \src "libresoc.v:40124.3-40136.6"
+ attribute \src "libresoc.v:40315.3-40327.6"
wire $0\dec62_inv_out[0:0]
- attribute \src "libresoc.v:40202.3-40214.6"
+ attribute \src "libresoc.v:40393.3-40405.6"
wire $0\dec62_is_32b[0:0]
- attribute \src "libresoc.v:40046.3-40058.6"
+ attribute \src "libresoc.v:40237.3-40249.6"
wire width 4 $0\dec62_ldst_len[3:0]
- attribute \src "libresoc.v:40228.3-40240.6"
+ attribute \src "libresoc.v:40419.3-40431.6"
wire $0\dec62_lk[0:0]
- attribute \src "libresoc.v:40306.3-40318.6"
+ attribute \src "libresoc.v:40497.3-40509.6"
wire width 2 $0\dec62_out_sel[1:0]
- attribute \src "libresoc.v:40072.3-40084.6"
+ attribute \src "libresoc.v:40263.3-40275.6"
wire width 2 $0\dec62_rc_sel[1:0]
- attribute \src "libresoc.v:40189.3-40201.6"
+ attribute \src "libresoc.v:40380.3-40392.6"
wire $0\dec62_rsrv[0:0]
- attribute \src "libresoc.v:40241.3-40253.6"
+ attribute \src "libresoc.v:40432.3-40444.6"
wire $0\dec62_sgl_pipe[0:0]
- attribute \src "libresoc.v:40215.3-40227.6"
+ attribute \src "libresoc.v:40406.3-40418.6"
wire $0\dec62_sgn[0:0]
- attribute \src "libresoc.v:40163.3-40175.6"
+ attribute \src "libresoc.v:40354.3-40366.6"
wire $0\dec62_sgn_ext[0:0]
- attribute \src "libresoc.v:40059.3-40071.6"
+ attribute \src "libresoc.v:40250.3-40262.6"
wire width 2 $0\dec62_upd[1:0]
- attribute \src "libresoc.v:39776.7-39776.20"
+ attribute \src "libresoc.v:39967.7-39967.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:40098.3-40110.6"
+ attribute \src "libresoc.v:40289.3-40301.6"
wire width 8 $1\dec62_asmcode[7:0]
- attribute \src "libresoc.v:40150.3-40162.6"
+ attribute \src "libresoc.v:40341.3-40353.6"
wire $1\dec62_br[0:0]
- attribute \src "libresoc.v:40319.3-40331.6"
+ attribute \src "libresoc.v:40510.3-40522.6"
wire width 3 $1\dec62_cr_in[2:0]
- attribute \src "libresoc.v:40332.3-40344.6"
+ attribute \src "libresoc.v:40523.3-40535.6"
wire width 3 $1\dec62_cr_out[2:0]
- attribute \src "libresoc.v:40085.3-40097.6"
+ attribute \src "libresoc.v:40276.3-40288.6"
wire width 2 $1\dec62_cry_in[1:0]
- attribute \src "libresoc.v:40137.3-40149.6"
+ attribute \src "libresoc.v:40328.3-40340.6"
wire $1\dec62_cry_out[0:0]
- attribute \src "libresoc.v:40254.3-40266.6"
+ attribute \src "libresoc.v:40445.3-40457.6"
wire width 5 $1\dec62_form[4:0]
- attribute \src "libresoc.v:40033.3-40045.6"
+ attribute \src "libresoc.v:40224.3-40236.6"
wire width 12 $1\dec62_function_unit[11:0]
- attribute \src "libresoc.v:40267.3-40279.6"
+ attribute \src "libresoc.v:40458.3-40470.6"
wire width 3 $1\dec62_in1_sel[2:0]
- attribute \src "libresoc.v:40280.3-40292.6"
+ attribute \src "libresoc.v:40471.3-40483.6"
wire width 4 $1\dec62_in2_sel[3:0]
- attribute \src "libresoc.v:40293.3-40305.6"
+ attribute \src "libresoc.v:40484.3-40496.6"
wire width 2 $1\dec62_in3_sel[1:0]
- attribute \src "libresoc.v:40176.3-40188.6"
+ attribute \src "libresoc.v:40367.3-40379.6"
wire width 7 $1\dec62_internal_op[6:0]
- attribute \src "libresoc.v:40111.3-40123.6"
+ attribute \src "libresoc.v:40302.3-40314.6"
wire $1\dec62_inv_a[0:0]
- attribute \src "libresoc.v:40124.3-40136.6"
+ attribute \src "libresoc.v:40315.3-40327.6"
wire $1\dec62_inv_out[0:0]
- attribute \src "libresoc.v:40202.3-40214.6"
+ attribute \src "libresoc.v:40393.3-40405.6"
wire $1\dec62_is_32b[0:0]
- attribute \src "libresoc.v:40046.3-40058.6"
+ attribute \src "libresoc.v:40237.3-40249.6"
wire width 4 $1\dec62_ldst_len[3:0]
- attribute \src "libresoc.v:40228.3-40240.6"
+ attribute \src "libresoc.v:40419.3-40431.6"
wire $1\dec62_lk[0:0]
- attribute \src "libresoc.v:40306.3-40318.6"
+ attribute \src "libresoc.v:40497.3-40509.6"
wire width 2 $1\dec62_out_sel[1:0]
- attribute \src "libresoc.v:40072.3-40084.6"
+ attribute \src "libresoc.v:40263.3-40275.6"
wire width 2 $1\dec62_rc_sel[1:0]
- attribute \src "libresoc.v:40189.3-40201.6"
+ attribute \src "libresoc.v:40380.3-40392.6"
wire $1\dec62_rsrv[0:0]
- attribute \src "libresoc.v:40241.3-40253.6"
+ attribute \src "libresoc.v:40432.3-40444.6"
wire $1\dec62_sgl_pipe[0:0]
- attribute \src "libresoc.v:40215.3-40227.6"
+ attribute \src "libresoc.v:40406.3-40418.6"
wire $1\dec62_sgn[0:0]
- attribute \src "libresoc.v:40163.3-40175.6"
+ attribute \src "libresoc.v:40354.3-40366.6"
wire $1\dec62_sgn_ext[0:0]
- attribute \src "libresoc.v:40059.3-40071.6"
+ attribute \src "libresoc.v:40250.3-40262.6"
wire width 2 $1\dec62_upd[1:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 8 output 4 \dec62_asmcode
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 output 12 \dec62_upd
- attribute \src "libresoc.v:39776.7-39776.15"
+ attribute \src "libresoc.v:39967.7-39967.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283"
wire width 32 input 25 \opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320"
wire width 2 \opcode_switch
- attribute \src "libresoc.v:39776.7-39776.20"
- process $proc$libresoc.v:39776$866
+ attribute \src "libresoc.v:39967.7-39967.20"
+ process $proc$libresoc.v:39967$906
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:40033.3-40045.6"
- process $proc$libresoc.v:40033$842
+ attribute \src "libresoc.v:40224.3-40236.6"
+ process $proc$libresoc.v:40224$882
assign { } { }
assign { } { }
assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0]
- attribute \src "libresoc.v:40034.5-40034.29"
+ attribute \src "libresoc.v:40225.5-40225.29"
switch \initial
- attribute \src "libresoc.v:40034.9-40034.17"
+ attribute \src "libresoc.v:40225.9-40225.17"
case 1'1
case
end
sync always
update \dec62_function_unit $0\dec62_function_unit[11:0]
end
- attribute \src "libresoc.v:40046.3-40058.6"
- process $proc$libresoc.v:40046$843
+ attribute \src "libresoc.v:40237.3-40249.6"
+ process $proc$libresoc.v:40237$883
assign { } { }
assign { } { }
assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0]
- attribute \src "libresoc.v:40047.5-40047.29"
+ attribute \src "libresoc.v:40238.5-40238.29"
switch \initial
- attribute \src "libresoc.v:40047.9-40047.17"
+ attribute \src "libresoc.v:40238.9-40238.17"
case 1'1
case
end
sync always
update \dec62_ldst_len $0\dec62_ldst_len[3:0]
end
- attribute \src "libresoc.v:40059.3-40071.6"
- process $proc$libresoc.v:40059$844
+ attribute \src "libresoc.v:40250.3-40262.6"
+ process $proc$libresoc.v:40250$884
assign { } { }
assign { } { }
assign $0\dec62_upd[1:0] $1\dec62_upd[1:0]
- attribute \src "libresoc.v:40060.5-40060.29"
+ attribute \src "libresoc.v:40251.5-40251.29"
switch \initial
- attribute \src "libresoc.v:40060.9-40060.17"
+ attribute \src "libresoc.v:40251.9-40251.17"
case 1'1
case
end
sync always
update \dec62_upd $0\dec62_upd[1:0]
end
- attribute \src "libresoc.v:40072.3-40084.6"
- process $proc$libresoc.v:40072$845
+ attribute \src "libresoc.v:40263.3-40275.6"
+ process $proc$libresoc.v:40263$885
assign { } { }
assign { } { }
assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0]
- attribute \src "libresoc.v:40073.5-40073.29"
+ attribute \src "libresoc.v:40264.5-40264.29"
switch \initial
- attribute \src "libresoc.v:40073.9-40073.17"
+ attribute \src "libresoc.v:40264.9-40264.17"
case 1'1
case
end
sync always
update \dec62_rc_sel $0\dec62_rc_sel[1:0]
end
- attribute \src "libresoc.v:40085.3-40097.6"
- process $proc$libresoc.v:40085$846
+ attribute \src "libresoc.v:40276.3-40288.6"
+ process $proc$libresoc.v:40276$886
assign { } { }
assign { } { }
assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0]
- attribute \src "libresoc.v:40086.5-40086.29"
+ attribute \src "libresoc.v:40277.5-40277.29"
switch \initial
- attribute \src "libresoc.v:40086.9-40086.17"
+ attribute \src "libresoc.v:40277.9-40277.17"
case 1'1
case
end
sync always
update \dec62_cry_in $0\dec62_cry_in[1:0]
end
- attribute \src "libresoc.v:40098.3-40110.6"
- process $proc$libresoc.v:40098$847
+ attribute \src "libresoc.v:40289.3-40301.6"
+ process $proc$libresoc.v:40289$887
assign { } { }
assign { } { }
assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0]
- attribute \src "libresoc.v:40099.5-40099.29"
+ attribute \src "libresoc.v:40290.5-40290.29"
switch \initial
- attribute \src "libresoc.v:40099.9-40099.17"
+ attribute \src "libresoc.v:40290.9-40290.17"
case 1'1
case
end
sync always
update \dec62_asmcode $0\dec62_asmcode[7:0]
end
- attribute \src "libresoc.v:40111.3-40123.6"
- process $proc$libresoc.v:40111$848
+ attribute \src "libresoc.v:40302.3-40314.6"
+ process $proc$libresoc.v:40302$888
assign { } { }
assign { } { }
assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0]
- attribute \src "libresoc.v:40112.5-40112.29"
+ attribute \src "libresoc.v:40303.5-40303.29"
switch \initial
- attribute \src "libresoc.v:40112.9-40112.17"
+ attribute \src "libresoc.v:40303.9-40303.17"
case 1'1
case
end
sync always
update \dec62_inv_a $0\dec62_inv_a[0:0]
end
- attribute \src "libresoc.v:40124.3-40136.6"
- process $proc$libresoc.v:40124$849
+ attribute \src "libresoc.v:40315.3-40327.6"
+ process $proc$libresoc.v:40315$889
assign { } { }
assign { } { }
assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0]
- attribute \src "libresoc.v:40125.5-40125.29"
+ attribute \src "libresoc.v:40316.5-40316.29"
switch \initial
- attribute \src "libresoc.v:40125.9-40125.17"
+ attribute \src "libresoc.v:40316.9-40316.17"
case 1'1
case
end
sync always
update \dec62_inv_out $0\dec62_inv_out[0:0]
end
- attribute \src "libresoc.v:40137.3-40149.6"
- process $proc$libresoc.v:40137$850
+ attribute \src "libresoc.v:40328.3-40340.6"
+ process $proc$libresoc.v:40328$890
assign { } { }
assign { } { }
assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0]
- attribute \src "libresoc.v:40138.5-40138.29"
+ attribute \src "libresoc.v:40329.5-40329.29"
switch \initial
- attribute \src "libresoc.v:40138.9-40138.17"
+ attribute \src "libresoc.v:40329.9-40329.17"
case 1'1
case
end
sync always
update \dec62_cry_out $0\dec62_cry_out[0:0]
end
- attribute \src "libresoc.v:40150.3-40162.6"
- process $proc$libresoc.v:40150$851
+ attribute \src "libresoc.v:40341.3-40353.6"
+ process $proc$libresoc.v:40341$891
assign { } { }
assign { } { }
assign $0\dec62_br[0:0] $1\dec62_br[0:0]
- attribute \src "libresoc.v:40151.5-40151.29"
+ attribute \src "libresoc.v:40342.5-40342.29"
switch \initial
- attribute \src "libresoc.v:40151.9-40151.17"
+ attribute \src "libresoc.v:40342.9-40342.17"
case 1'1
case
end
sync always
update \dec62_br $0\dec62_br[0:0]
end
- attribute \src "libresoc.v:40163.3-40175.6"
- process $proc$libresoc.v:40163$852
+ attribute \src "libresoc.v:40354.3-40366.6"
+ process $proc$libresoc.v:40354$892
assign { } { }
assign { } { }
assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0]
- attribute \src "libresoc.v:40164.5-40164.29"
+ attribute \src "libresoc.v:40355.5-40355.29"
switch \initial
- attribute \src "libresoc.v:40164.9-40164.17"
+ attribute \src "libresoc.v:40355.9-40355.17"
case 1'1
case
end
sync always
update \dec62_sgn_ext $0\dec62_sgn_ext[0:0]
end
- attribute \src "libresoc.v:40176.3-40188.6"
- process $proc$libresoc.v:40176$853
+ attribute \src "libresoc.v:40367.3-40379.6"
+ process $proc$libresoc.v:40367$893
assign { } { }
assign { } { }
assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0]
- attribute \src "libresoc.v:40177.5-40177.29"
+ attribute \src "libresoc.v:40368.5-40368.29"
switch \initial
- attribute \src "libresoc.v:40177.9-40177.17"
+ attribute \src "libresoc.v:40368.9-40368.17"
case 1'1
case
end
sync always
update \dec62_internal_op $0\dec62_internal_op[6:0]
end
- attribute \src "libresoc.v:40189.3-40201.6"
- process $proc$libresoc.v:40189$854
+ attribute \src "libresoc.v:40380.3-40392.6"
+ process $proc$libresoc.v:40380$894
assign { } { }
assign { } { }
assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0]
- attribute \src "libresoc.v:40190.5-40190.29"
+ attribute \src "libresoc.v:40381.5-40381.29"
switch \initial
- attribute \src "libresoc.v:40190.9-40190.17"
+ attribute \src "libresoc.v:40381.9-40381.17"
case 1'1
case
end
sync always
update \dec62_rsrv $0\dec62_rsrv[0:0]
end
- attribute \src "libresoc.v:40202.3-40214.6"
- process $proc$libresoc.v:40202$855
+ attribute \src "libresoc.v:40393.3-40405.6"
+ process $proc$libresoc.v:40393$895
assign { } { }
assign { } { }
assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0]
- attribute \src "libresoc.v:40203.5-40203.29"
+ attribute \src "libresoc.v:40394.5-40394.29"
switch \initial
- attribute \src "libresoc.v:40203.9-40203.17"
+ attribute \src "libresoc.v:40394.9-40394.17"
case 1'1
case
end
sync always
update \dec62_is_32b $0\dec62_is_32b[0:0]
end
- attribute \src "libresoc.v:40215.3-40227.6"
- process $proc$libresoc.v:40215$856
+ attribute \src "libresoc.v:40406.3-40418.6"
+ process $proc$libresoc.v:40406$896
assign { } { }
assign { } { }
assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0]
- attribute \src "libresoc.v:40216.5-40216.29"
+ attribute \src "libresoc.v:40407.5-40407.29"
switch \initial
- attribute \src "libresoc.v:40216.9-40216.17"
+ attribute \src "libresoc.v:40407.9-40407.17"
case 1'1
case
end
sync always
update \dec62_sgn $0\dec62_sgn[0:0]
end
- attribute \src "libresoc.v:40228.3-40240.6"
- process $proc$libresoc.v:40228$857
+ attribute \src "libresoc.v:40419.3-40431.6"
+ process $proc$libresoc.v:40419$897
assign { } { }
assign { } { }
assign $0\dec62_lk[0:0] $1\dec62_lk[0:0]
- attribute \src "libresoc.v:40229.5-40229.29"
+ attribute \src "libresoc.v:40420.5-40420.29"
switch \initial
- attribute \src "libresoc.v:40229.9-40229.17"
+ attribute \src "libresoc.v:40420.9-40420.17"
case 1'1
case
end
sync always
update \dec62_lk $0\dec62_lk[0:0]
end
- attribute \src "libresoc.v:40241.3-40253.6"
- process $proc$libresoc.v:40241$858
+ attribute \src "libresoc.v:40432.3-40444.6"
+ process $proc$libresoc.v:40432$898
assign { } { }
assign { } { }
assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0]
- attribute \src "libresoc.v:40242.5-40242.29"
+ attribute \src "libresoc.v:40433.5-40433.29"
switch \initial
- attribute \src "libresoc.v:40242.9-40242.17"
+ attribute \src "libresoc.v:40433.9-40433.17"
case 1'1
case
end
sync always
update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0]
end
- attribute \src "libresoc.v:40254.3-40266.6"
- process $proc$libresoc.v:40254$859
+ attribute \src "libresoc.v:40445.3-40457.6"
+ process $proc$libresoc.v:40445$899
assign { } { }
assign { } { }
assign $0\dec62_form[4:0] $1\dec62_form[4:0]
- attribute \src "libresoc.v:40255.5-40255.29"
+ attribute \src "libresoc.v:40446.5-40446.29"
switch \initial
- attribute \src "libresoc.v:40255.9-40255.17"
+ attribute \src "libresoc.v:40446.9-40446.17"
case 1'1
case
end
sync always
update \dec62_form $0\dec62_form[4:0]
end
- attribute \src "libresoc.v:40267.3-40279.6"
- process $proc$libresoc.v:40267$860
+ attribute \src "libresoc.v:40458.3-40470.6"
+ process $proc$libresoc.v:40458$900
assign { } { }
assign { } { }
assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0]
- attribute \src "libresoc.v:40268.5-40268.29"
+ attribute \src "libresoc.v:40459.5-40459.29"
switch \initial
- attribute \src "libresoc.v:40268.9-40268.17"
+ attribute \src "libresoc.v:40459.9-40459.17"
case 1'1
case
end
sync always
update \dec62_in1_sel $0\dec62_in1_sel[2:0]
end
- attribute \src "libresoc.v:40280.3-40292.6"
- process $proc$libresoc.v:40280$861
+ attribute \src "libresoc.v:40471.3-40483.6"
+ process $proc$libresoc.v:40471$901
assign { } { }
assign { } { }
assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0]
- attribute \src "libresoc.v:40281.5-40281.29"
+ attribute \src "libresoc.v:40472.5-40472.29"
switch \initial
- attribute \src "libresoc.v:40281.9-40281.17"
+ attribute \src "libresoc.v:40472.9-40472.17"
case 1'1
case
end
sync always
update \dec62_in2_sel $0\dec62_in2_sel[3:0]
end
- attribute \src "libresoc.v:40293.3-40305.6"
- process $proc$libresoc.v:40293$862
+ attribute \src "libresoc.v:40484.3-40496.6"
+ process $proc$libresoc.v:40484$902
assign { } { }
assign { } { }
assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0]
- attribute \src "libresoc.v:40294.5-40294.29"
+ attribute \src "libresoc.v:40485.5-40485.29"
switch \initial
- attribute \src "libresoc.v:40294.9-40294.17"
+ attribute \src "libresoc.v:40485.9-40485.17"
case 1'1
case
end
sync always
update \dec62_in3_sel $0\dec62_in3_sel[1:0]
end
- attribute \src "libresoc.v:40306.3-40318.6"
- process $proc$libresoc.v:40306$863
+ attribute \src "libresoc.v:40497.3-40509.6"
+ process $proc$libresoc.v:40497$903
assign { } { }
assign { } { }
assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0]
- attribute \src "libresoc.v:40307.5-40307.29"
+ attribute \src "libresoc.v:40498.5-40498.29"
switch \initial
- attribute \src "libresoc.v:40307.9-40307.17"
+ attribute \src "libresoc.v:40498.9-40498.17"
case 1'1
case
end
sync always
update \dec62_out_sel $0\dec62_out_sel[1:0]
end
- attribute \src "libresoc.v:40319.3-40331.6"
- process $proc$libresoc.v:40319$864
+ attribute \src "libresoc.v:40510.3-40522.6"
+ process $proc$libresoc.v:40510$904
assign { } { }
assign { } { }
assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0]
- attribute \src "libresoc.v:40320.5-40320.29"
+ attribute \src "libresoc.v:40511.5-40511.29"
switch \initial
- attribute \src "libresoc.v:40320.9-40320.17"
+ attribute \src "libresoc.v:40511.9-40511.17"
case 1'1
case
end
sync always
update \dec62_cr_in $0\dec62_cr_in[2:0]
end
- attribute \src "libresoc.v:40332.3-40344.6"
- process $proc$libresoc.v:40332$865
+ attribute \src "libresoc.v:40523.3-40535.6"
+ process $proc$libresoc.v:40523$905
assign { } { }
assign { } { }
assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0]
- attribute \src "libresoc.v:40333.5-40333.29"
+ attribute \src "libresoc.v:40524.5-40524.29"
switch \initial
- attribute \src "libresoc.v:40333.9-40333.17"
+ attribute \src "libresoc.v:40524.9-40524.17"
case 1'1
case
end
end
connect \opcode_switch \opcode_in [1:0]
end
-attribute \src "libresoc.v:40350.1-40855.10"
+attribute \src "libresoc.v:40541.1-41046.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec_a"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a"
attribute \generator "nMigen"
module \dec_a
- attribute \src "libresoc.v:40784.3-40819.6"
+ attribute \src "libresoc.v:40975.3-41010.6"
wire width 3 $0\fast_a[2:0]
- attribute \src "libresoc.v:40784.3-40819.6"
+ attribute \src "libresoc.v:40975.3-41010.6"
wire $0\fast_a_ok[0:0]
- attribute \src "libresoc.v:40351.7-40351.20"
+ attribute \src "libresoc.v:40542.7-40542.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:40752.3-40767.6"
+ attribute \src "libresoc.v:40943.3-40958.6"
wire width 5 $0\reg_a[4:0]
- attribute \src "libresoc.v:40768.3-40783.6"
+ attribute \src "libresoc.v:40959.3-40974.6"
wire $0\reg_a_ok[0:0]
- attribute \src "libresoc.v:40820.3-40830.6"
+ attribute \src "libresoc.v:41011.3-41021.6"
wire width 10 $0\spr[9:0]
- attribute \src "libresoc.v:40842.3-40853.6"
+ attribute \src "libresoc.v:41033.3-41044.6"
wire width 10 $0\spr_a[9:0]
- attribute \src "libresoc.v:40842.3-40853.6"
+ attribute \src "libresoc.v:41033.3-41044.6"
wire $0\spr_a_ok[0:0]
- attribute \src "libresoc.v:40831.3-40841.6"
+ attribute \src "libresoc.v:41022.3-41032.6"
wire width 10 $0\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:40784.3-40819.6"
+ attribute \src "libresoc.v:40975.3-41010.6"
wire width 3 $1\fast_a[2:0]
- attribute \src "libresoc.v:40784.3-40819.6"
+ attribute \src "libresoc.v:40975.3-41010.6"
wire $1\fast_a_ok[0:0]
- attribute \src "libresoc.v:40752.3-40767.6"
+ attribute \src "libresoc.v:40943.3-40958.6"
wire width 5 $1\reg_a[4:0]
- attribute \src "libresoc.v:40768.3-40783.6"
+ attribute \src "libresoc.v:40959.3-40974.6"
wire $1\reg_a_ok[0:0]
- attribute \src "libresoc.v:40820.3-40830.6"
+ attribute \src "libresoc.v:41011.3-41021.6"
wire width 10 $1\spr[9:0]
- attribute \src "libresoc.v:40842.3-40853.6"
+ attribute \src "libresoc.v:41033.3-41044.6"
wire width 10 $1\spr_a[9:0]
- attribute \src "libresoc.v:40842.3-40853.6"
+ attribute \src "libresoc.v:41033.3-41044.6"
wire $1\spr_a_ok[0:0]
- attribute \src "libresoc.v:40831.3-40841.6"
+ attribute \src "libresoc.v:41022.3-41032.6"
wire width 10 $1\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:40784.3-40819.6"
+ attribute \src "libresoc.v:40975.3-41010.6"
wire width 3 $2\fast_a[2:0]
- attribute \src "libresoc.v:40784.3-40819.6"
+ attribute \src "libresoc.v:40975.3-41010.6"
wire $2\fast_a_ok[0:0]
- attribute \src "libresoc.v:40752.3-40767.6"
+ attribute \src "libresoc.v:40943.3-40958.6"
wire width 5 $2\reg_a[4:0]
- attribute \src "libresoc.v:40768.3-40783.6"
+ attribute \src "libresoc.v:40959.3-40974.6"
wire $2\reg_a_ok[0:0]
- attribute \src "libresoc.v:40784.3-40819.6"
+ attribute \src "libresoc.v:40975.3-41010.6"
wire width 3 $3\fast_a[2:0]
- attribute \src "libresoc.v:40784.3-40819.6"
+ attribute \src "libresoc.v:40975.3-41010.6"
wire $3\fast_a_ok[0:0]
- attribute \src "libresoc.v:40736.18-40736.110"
- wire $and$libresoc.v:40736$873_Y
- attribute \src "libresoc.v:40741.18-40741.113"
- wire $and$libresoc.v:40741$878_Y
- attribute \src "libresoc.v:40744.17-40744.107"
- wire $and$libresoc.v:40744$881_Y
- attribute \src "libresoc.v:40731.18-40731.112"
- wire $eq$libresoc.v:40731$868_Y
- attribute \src "libresoc.v:40732.18-40732.111"
- wire $eq$libresoc.v:40732$869_Y
- attribute \src "libresoc.v:40733.18-40733.112"
- wire $eq$libresoc.v:40733$870_Y
- attribute \src "libresoc.v:40735.17-40735.110"
- wire $eq$libresoc.v:40735$872_Y
- attribute \src "libresoc.v:40738.18-40738.112"
- wire $eq$libresoc.v:40738$875_Y
- attribute \src "libresoc.v:40742.17-40742.111"
- wire $eq$libresoc.v:40742$879_Y
- attribute \src "libresoc.v:40734.18-40734.109"
- wire $ne$libresoc.v:40734$871_Y
- attribute \src "libresoc.v:40743.17-40743.108"
- wire $ne$libresoc.v:40743$880_Y
- attribute \src "libresoc.v:40739.18-40739.105"
- wire $not$libresoc.v:40739$876_Y
- attribute \src "libresoc.v:40740.18-40740.108"
- wire $not$libresoc.v:40740$877_Y
- attribute \src "libresoc.v:40730.17-40730.107"
- wire $or$libresoc.v:40730$867_Y
- attribute \src "libresoc.v:40737.18-40737.110"
- wire $or$libresoc.v:40737$874_Y
+ attribute \src "libresoc.v:40927.18-40927.110"
+ wire $and$libresoc.v:40927$913_Y
+ attribute \src "libresoc.v:40932.18-40932.113"
+ wire $and$libresoc.v:40932$918_Y
+ attribute \src "libresoc.v:40935.17-40935.107"
+ wire $and$libresoc.v:40935$921_Y
+ attribute \src "libresoc.v:40922.18-40922.112"
+ wire $eq$libresoc.v:40922$908_Y
+ attribute \src "libresoc.v:40923.18-40923.111"
+ wire $eq$libresoc.v:40923$909_Y
+ attribute \src "libresoc.v:40924.18-40924.112"
+ wire $eq$libresoc.v:40924$910_Y
+ attribute \src "libresoc.v:40926.17-40926.110"
+ wire $eq$libresoc.v:40926$912_Y
+ attribute \src "libresoc.v:40929.18-40929.112"
+ wire $eq$libresoc.v:40929$915_Y
+ attribute \src "libresoc.v:40933.17-40933.111"
+ wire $eq$libresoc.v:40933$919_Y
+ attribute \src "libresoc.v:40925.18-40925.109"
+ wire $ne$libresoc.v:40925$911_Y
+ attribute \src "libresoc.v:40934.17-40934.108"
+ wire $ne$libresoc.v:40934$920_Y
+ attribute \src "libresoc.v:40930.18-40930.105"
+ wire $not$libresoc.v:40930$916_Y
+ attribute \src "libresoc.v:40931.18-40931.108"
+ wire $not$libresoc.v:40931$917_Y
+ attribute \src "libresoc.v:40921.17-40921.107"
+ wire $or$libresoc.v:40921$907_Y
+ attribute \src "libresoc.v:40928.18-40928.110"
+ wire $or$libresoc.v:40928$914_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106"
wire width 3 output 6 \fast_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire output 7 \fast_a_ok
- attribute \src "libresoc.v:40351.7-40351.15"
+ attribute \src "libresoc.v:40542.7-40542.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire \sprmap_spr_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101"
- cell $and $and$libresoc.v:40736$873
+ cell $and $and$libresoc.v:40927$913
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$15
connect \B \$17
- connect \Y $and$libresoc.v:40736$873_Y
+ connect \Y $and$libresoc.v:40927$913_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
- cell $and $and$libresoc.v:40741$878
+ cell $and $and$libresoc.v:40932$918
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \XL_XO [9]
connect \B \$27
- connect \Y $and$libresoc.v:40741$878_Y
+ connect \Y $and$libresoc.v:40932$918_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101"
- cell $and $and$libresoc.v:40744$881
+ cell $and $and$libresoc.v:40935$921
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \$5
- connect \Y $and$libresoc.v:40744$881_Y
+ connect \Y $and$libresoc.v:40935$921_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106"
- cell $eq $eq$libresoc.v:40731$868
+ cell $eq $eq$libresoc.v:40922$908
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'100
- connect \Y $eq$libresoc.v:40731$868_Y
+ connect \Y $eq$libresoc.v:40922$908_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
- cell $eq $eq$libresoc.v:40732$869
+ cell $eq $eq$libresoc.v:40923$909
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'001
- connect \Y $eq$libresoc.v:40732$869_Y
+ connect \Y $eq$libresoc.v:40923$909_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100"
- cell $eq $eq$libresoc.v:40733$870
+ cell $eq $eq$libresoc.v:40924$910
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:40733$870_Y
+ connect \Y $eq$libresoc.v:40924$910_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
- cell $eq $eq$libresoc.v:40735$872
+ cell $eq $eq$libresoc.v:40926$912
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'001
- connect \Y $eq$libresoc.v:40735$872_Y
+ connect \Y $eq$libresoc.v:40926$912_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106"
- cell $eq $eq$libresoc.v:40738$875
+ cell $eq $eq$libresoc.v:40929$915
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'100
- connect \Y $eq$libresoc.v:40738$875_Y
+ connect \Y $eq$libresoc.v:40929$915_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100"
- cell $eq $eq$libresoc.v:40742$879
+ cell $eq $eq$libresoc.v:40933$919
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sel_in
connect \B 3'010
- connect \Y $eq$libresoc.v:40742$879_Y
+ connect \Y $eq$libresoc.v:40933$919_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101"
- cell $ne $ne$libresoc.v:40734$871
+ cell $ne $ne$libresoc.v:40925$911
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $ne$libresoc.v:40734$871_Y
+ connect \Y $ne$libresoc.v:40925$911_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101"
- cell $ne $ne$libresoc.v:40743$880
+ cell $ne $ne$libresoc.v:40934$920
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra
connect \B 5'00000
- connect \Y $ne$libresoc.v:40743$880_Y
+ connect \Y $ne$libresoc.v:40934$920_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116"
- cell $not $not$libresoc.v:40739$876
+ cell $not $not$libresoc.v:40930$916
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \BO [2]
- connect \Y $not$libresoc.v:40739$876_Y
+ connect \Y $not$libresoc.v:40930$916_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
- cell $not $not$libresoc.v:40740$877
+ cell $not $not$libresoc.v:40931$917
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \XL_XO [5]
- connect \Y $not$libresoc.v:40740$877_Y
+ connect \Y $not$libresoc.v:40931$917_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101"
- cell $or $or$libresoc.v:40730$867
+ cell $or $or$libresoc.v:40921$907
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$7
- connect \Y $or$libresoc.v:40730$867_Y
+ connect \Y $or$libresoc.v:40921$907_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101"
- cell $or $or$libresoc.v:40737$874
+ cell $or $or$libresoc.v:40928$914
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$13
connect \B \$19
- connect \Y $or$libresoc.v:40737$874_Y
+ connect \Y $or$libresoc.v:40928$914_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:40745.10-40751.4"
+ attribute \src "libresoc.v:40936.10-40942.4"
cell \sprmap \sprmap
connect \fast_o \sprmap_fast_o
connect \fast_o_ok \sprmap_fast_o_ok
connect \spr_o \sprmap_spr_o
connect \spr_o_ok \sprmap_spr_o_ok
end
- attribute \src "libresoc.v:40351.7-40351.20"
- process $proc$libresoc.v:40351$888
+ attribute \src "libresoc.v:40542.7-40542.20"
+ process $proc$libresoc.v:40542$928
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:40752.3-40767.6"
- process $proc$libresoc.v:40752$882
+ attribute \src "libresoc.v:40943.3-40958.6"
+ process $proc$libresoc.v:40943$922
assign { } { }
assign { } { }
assign { } { }
assign $0\reg_a[4:0] $2\reg_a[4:0]
- attribute \src "libresoc.v:40753.5-40753.29"
+ attribute \src "libresoc.v:40944.5-40944.29"
switch \initial
- attribute \src "libresoc.v:40753.9-40753.17"
+ attribute \src "libresoc.v:40944.9-40944.17"
case 1'1
case
end
sync always
update \reg_a $0\reg_a[4:0]
end
- attribute \src "libresoc.v:40768.3-40783.6"
- process $proc$libresoc.v:40768$883
+ attribute \src "libresoc.v:40959.3-40974.6"
+ process $proc$libresoc.v:40959$923
assign { } { }
assign { } { }
assign { } { }
assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0]
- attribute \src "libresoc.v:40769.5-40769.29"
+ attribute \src "libresoc.v:40960.5-40960.29"
switch \initial
- attribute \src "libresoc.v:40769.9-40769.17"
+ attribute \src "libresoc.v:40960.9-40960.17"
case 1'1
case
end
sync always
update \reg_a_ok $0\reg_a_ok[0:0]
end
- attribute \src "libresoc.v:40784.3-40819.6"
- process $proc$libresoc.v:40784$884
+ attribute \src "libresoc.v:40975.3-41010.6"
+ process $proc$libresoc.v:40975$924
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fast_a[2:0] $1\fast_a[2:0]
assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0]
- attribute \src "libresoc.v:40785.5-40785.29"
+ attribute \src "libresoc.v:40976.5-40976.29"
switch \initial
- attribute \src "libresoc.v:40785.9-40785.17"
+ attribute \src "libresoc.v:40976.9-40976.17"
case 1'1
case
end
update \fast_a $0\fast_a[2:0]
update \fast_a_ok $0\fast_a_ok[0:0]
end
- attribute \src "libresoc.v:40820.3-40830.6"
- process $proc$libresoc.v:40820$885
+ attribute \src "libresoc.v:41011.3-41021.6"
+ process $proc$libresoc.v:41011$925
assign { } { }
assign { } { }
assign $0\spr[9:0] $1\spr[9:0]
- attribute \src "libresoc.v:40821.5-40821.29"
+ attribute \src "libresoc.v:41012.5-41012.29"
switch \initial
- attribute \src "libresoc.v:40821.9-40821.17"
+ attribute \src "libresoc.v:41012.9-41012.17"
case 1'1
case
end
sync always
update \spr $0\spr[9:0]
end
- attribute \src "libresoc.v:40831.3-40841.6"
- process $proc$libresoc.v:40831$886
+ attribute \src "libresoc.v:41022.3-41032.6"
+ process $proc$libresoc.v:41022$926
assign { } { }
assign { } { }
assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:40832.5-40832.29"
+ attribute \src "libresoc.v:41023.5-41023.29"
switch \initial
- attribute \src "libresoc.v:40832.9-40832.17"
+ attribute \src "libresoc.v:41023.9-41023.17"
case 1'1
case
end
sync always
update \sprmap_spr_i $0\sprmap_spr_i[9:0]
end
- attribute \src "libresoc.v:40842.3-40853.6"
- process $proc$libresoc.v:40842$887
+ attribute \src "libresoc.v:41033.3-41044.6"
+ process $proc$libresoc.v:41033$927
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\spr_a[9:0] $1\spr_a[9:0]
assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0]
- attribute \src "libresoc.v:40843.5-40843.29"
+ attribute \src "libresoc.v:41034.5-41034.29"
switch \initial
- attribute \src "libresoc.v:40843.9-40843.17"
+ attribute \src "libresoc.v:41034.9-41034.17"
case 1'1
case
end
update \spr_a $0\spr_a[9:0]
update \spr_a_ok $0\spr_a_ok[0:0]
end
- connect \$9 $or$libresoc.v:40730$867_Y
- connect \$11 $eq$libresoc.v:40731$868_Y
- connect \$13 $eq$libresoc.v:40732$869_Y
- connect \$15 $eq$libresoc.v:40733$870_Y
- connect \$17 $ne$libresoc.v:40734$871_Y
- connect \$1 $eq$libresoc.v:40735$872_Y
- connect \$19 $and$libresoc.v:40736$873_Y
- connect \$21 $or$libresoc.v:40737$874_Y
- connect \$23 $eq$libresoc.v:40738$875_Y
- connect \$25 $not$libresoc.v:40739$876_Y
- connect \$27 $not$libresoc.v:40740$877_Y
- connect \$29 $and$libresoc.v:40741$878_Y
- connect \$3 $eq$libresoc.v:40742$879_Y
- connect \$5 $ne$libresoc.v:40743$880_Y
- connect \$7 $and$libresoc.v:40744$881_Y
+ connect \$9 $or$libresoc.v:40921$907_Y
+ connect \$11 $eq$libresoc.v:40922$908_Y
+ connect \$13 $eq$libresoc.v:40923$909_Y
+ connect \$15 $eq$libresoc.v:40924$910_Y
+ connect \$17 $ne$libresoc.v:40925$911_Y
+ connect \$1 $eq$libresoc.v:40926$912_Y
+ connect \$19 $and$libresoc.v:40927$913_Y
+ connect \$21 $or$libresoc.v:40928$914_Y
+ connect \$23 $eq$libresoc.v:40929$915_Y
+ connect \$25 $not$libresoc.v:40930$916_Y
+ connect \$27 $not$libresoc.v:40931$917_Y
+ connect \$29 $and$libresoc.v:40932$918_Y
+ connect \$3 $eq$libresoc.v:40933$919_Y
+ connect \$5 $ne$libresoc.v:40934$920_Y
+ connect \$7 $and$libresoc.v:40935$921_Y
connect \ra \RA
end
-attribute \src "libresoc.v:40859.1-41050.10"
+attribute \src "libresoc.v:41050.1-41241.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec_b"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b"
attribute \generator "nMigen"
module \dec_b
- attribute \src "libresoc.v:41014.3-41031.6"
+ attribute \src "libresoc.v:41205.3-41222.6"
wire width 3 $0\fast_b[2:0]
- attribute \src "libresoc.v:41032.3-41049.6"
+ attribute \src "libresoc.v:41223.3-41240.6"
wire $0\fast_b_ok[0:0]
- attribute \src "libresoc.v:40860.7-40860.20"
+ attribute \src "libresoc.v:41051.7-41051.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:40984.3-40998.6"
+ attribute \src "libresoc.v:41175.3-41189.6"
wire width 5 $0\reg_b[4:0]
- attribute \src "libresoc.v:40999.3-41013.6"
+ attribute \src "libresoc.v:41190.3-41204.6"
wire $0\reg_b_ok[0:0]
- attribute \src "libresoc.v:41014.3-41031.6"
+ attribute \src "libresoc.v:41205.3-41222.6"
wire width 3 $1\fast_b[2:0]
- attribute \src "libresoc.v:41032.3-41049.6"
+ attribute \src "libresoc.v:41223.3-41240.6"
wire $1\fast_b_ok[0:0]
- attribute \src "libresoc.v:40984.3-40998.6"
+ attribute \src "libresoc.v:41175.3-41189.6"
wire width 5 $1\reg_b[4:0]
- attribute \src "libresoc.v:40999.3-41013.6"
+ attribute \src "libresoc.v:41190.3-41204.6"
wire $1\reg_b_ok[0:0]
- attribute \src "libresoc.v:41014.3-41031.6"
+ attribute \src "libresoc.v:41205.3-41222.6"
wire width 3 $2\fast_b[2:0]
- attribute \src "libresoc.v:41032.3-41049.6"
+ attribute \src "libresoc.v:41223.3-41240.6"
wire $2\fast_b_ok[0:0]
- attribute \src "libresoc.v:40980.17-40980.117"
- wire $eq$libresoc.v:40980$889_Y
- attribute \src "libresoc.v:40982.17-40982.117"
- wire $eq$libresoc.v:40982$891_Y
- attribute \src "libresoc.v:40981.17-40981.107"
- wire $not$libresoc.v:40981$890_Y
- attribute \src "libresoc.v:40983.17-40983.107"
- wire $not$libresoc.v:40983$892_Y
+ attribute \src "libresoc.v:41171.17-41171.117"
+ wire $eq$libresoc.v:41171$929_Y
+ attribute \src "libresoc.v:41173.17-41173.117"
+ wire $eq$libresoc.v:41173$931_Y
+ attribute \src "libresoc.v:41172.17-41172.107"
+ wire $not$libresoc.v:41172$930_Y
+ attribute \src "libresoc.v:41174.17-41174.107"
+ wire $not$libresoc.v:41174$932_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
wire width 3 output 4 \fast_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire output 5 \fast_b_ok
- attribute \src "libresoc.v:40860.7-40860.15"
+ attribute \src "libresoc.v:41051.7-41051.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
wire width 4 input 1 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
- cell $eq $eq$libresoc.v:40980$889
+ cell $eq $eq$libresoc.v:41171$929
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0001000
- connect \Y $eq$libresoc.v:40980$889_Y
+ connect \Y $eq$libresoc.v:41171$929_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
- cell $eq $eq$libresoc.v:40982$891
+ cell $eq $eq$libresoc.v:41173$931
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0001000
- connect \Y $eq$libresoc.v:40982$891_Y
+ connect \Y $eq$libresoc.v:41173$931_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
- cell $not $not$libresoc.v:40981$890
+ cell $not $not$libresoc.v:41172$930
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \XL_XO [9]
- connect \Y $not$libresoc.v:40981$890_Y
+ connect \Y $not$libresoc.v:41172$930_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
- cell $not $not$libresoc.v:40983$892
+ cell $not $not$libresoc.v:41174$932
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \XL_XO [9]
- connect \Y $not$libresoc.v:40983$892_Y
+ connect \Y $not$libresoc.v:41174$932_Y
end
- attribute \src "libresoc.v:40860.7-40860.20"
- process $proc$libresoc.v:40860$897
+ attribute \src "libresoc.v:41051.7-41051.20"
+ process $proc$libresoc.v:41051$937
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:40984.3-40998.6"
- process $proc$libresoc.v:40984$893
+ attribute \src "libresoc.v:41175.3-41189.6"
+ process $proc$libresoc.v:41175$933
assign { } { }
assign { } { }
assign $0\reg_b[4:0] $1\reg_b[4:0]
- attribute \src "libresoc.v:40985.5-40985.29"
+ attribute \src "libresoc.v:41176.5-41176.29"
switch \initial
- attribute \src "libresoc.v:40985.9-40985.17"
+ attribute \src "libresoc.v:41176.9-41176.17"
case 1'1
case
end
sync always
update \reg_b $0\reg_b[4:0]
end
- attribute \src "libresoc.v:40999.3-41013.6"
- process $proc$libresoc.v:40999$894
+ attribute \src "libresoc.v:41190.3-41204.6"
+ process $proc$libresoc.v:41190$934
assign { } { }
assign { } { }
assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0]
- attribute \src "libresoc.v:41000.5-41000.29"
+ attribute \src "libresoc.v:41191.5-41191.29"
switch \initial
- attribute \src "libresoc.v:41000.9-41000.17"
+ attribute \src "libresoc.v:41191.9-41191.17"
case 1'1
case
end
sync always
update \reg_b_ok $0\reg_b_ok[0:0]
end
- attribute \src "libresoc.v:41014.3-41031.6"
- process $proc$libresoc.v:41014$895
+ attribute \src "libresoc.v:41205.3-41222.6"
+ process $proc$libresoc.v:41205$935
assign { } { }
assign { } { }
assign $0\fast_b[2:0] $1\fast_b[2:0]
- attribute \src "libresoc.v:41015.5-41015.29"
+ attribute \src "libresoc.v:41206.5-41206.29"
switch \initial
- attribute \src "libresoc.v:41015.9-41015.17"
+ attribute \src "libresoc.v:41206.9-41206.17"
case 1'1
case
end
sync always
update \fast_b $0\fast_b[2:0]
end
- attribute \src "libresoc.v:41032.3-41049.6"
- process $proc$libresoc.v:41032$896
+ attribute \src "libresoc.v:41223.3-41240.6"
+ process $proc$libresoc.v:41223$936
assign { } { }
assign { } { }
assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0]
- attribute \src "libresoc.v:41033.5-41033.29"
+ attribute \src "libresoc.v:41224.5-41224.29"
switch \initial
- attribute \src "libresoc.v:41033.9-41033.17"
+ attribute \src "libresoc.v:41224.9-41224.17"
case 1'1
case
end
sync always
update \fast_b_ok $0\fast_b_ok[0:0]
end
- connect \$1 $eq$libresoc.v:40980$889_Y
- connect \$3 $not$libresoc.v:40981$890_Y
- connect \$5 $eq$libresoc.v:40982$891_Y
- connect \$7 $not$libresoc.v:40983$892_Y
+ connect \$1 $eq$libresoc.v:41171$929_Y
+ connect \$3 $not$libresoc.v:41172$930_Y
+ connect \$5 $eq$libresoc.v:41173$931_Y
+ connect \$7 $not$libresoc.v:41174$932_Y
end
-attribute \src "libresoc.v:41054.1-41102.10"
+attribute \src "libresoc.v:41245.1-41293.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec_c"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c"
attribute \generator "nMigen"
module \dec_c
- attribute \src "libresoc.v:41055.7-41055.20"
+ attribute \src "libresoc.v:41246.7-41246.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:41072.3-41086.6"
+ attribute \src "libresoc.v:41263.3-41277.6"
wire width 5 $0\reg_c[4:0]
- attribute \src "libresoc.v:41087.3-41101.6"
+ attribute \src "libresoc.v:41278.3-41292.6"
wire $0\reg_c_ok[0:0]
- attribute \src "libresoc.v:41072.3-41086.6"
+ attribute \src "libresoc.v:41263.3-41277.6"
wire width 5 $1\reg_c[4:0]
- attribute \src "libresoc.v:41087.3-41101.6"
+ attribute \src "libresoc.v:41278.3-41292.6"
wire $1\reg_c_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447"
wire width 5 input 4 \RB
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447"
wire width 5 input 3 \RS
- attribute \src "libresoc.v:41055.7-41055.15"
+ attribute \src "libresoc.v:41246.7-41246.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire width 5 output 1 \reg_c
attribute \enum_value_10 "RB"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:41055.7-41055.20"
- process $proc$libresoc.v:41055$900
+ attribute \src "libresoc.v:41246.7-41246.20"
+ process $proc$libresoc.v:41246$940
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:41072.3-41086.6"
- process $proc$libresoc.v:41072$898
+ attribute \src "libresoc.v:41263.3-41277.6"
+ process $proc$libresoc.v:41263$938
assign { } { }
assign { } { }
assign $0\reg_c[4:0] $1\reg_c[4:0]
- attribute \src "libresoc.v:41073.5-41073.29"
+ attribute \src "libresoc.v:41264.5-41264.29"
switch \initial
- attribute \src "libresoc.v:41073.9-41073.17"
+ attribute \src "libresoc.v:41264.9-41264.17"
case 1'1
case
end
sync always
update \reg_c $0\reg_c[4:0]
end
- attribute \src "libresoc.v:41087.3-41101.6"
- process $proc$libresoc.v:41087$899
+ attribute \src "libresoc.v:41278.3-41292.6"
+ process $proc$libresoc.v:41278$939
assign { } { }
assign { } { }
assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0]
- attribute \src "libresoc.v:41088.5-41088.29"
+ attribute \src "libresoc.v:41279.5-41279.29"
switch \initial
- attribute \src "libresoc.v:41088.9-41088.17"
+ attribute \src "libresoc.v:41279.9-41279.17"
case 1'1
case
end
update \reg_c_ok $0\reg_c_ok[0:0]
end
end
-attribute \src "libresoc.v:41106.1-41411.10"
+attribute \src "libresoc.v:41297.1-41602.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in"
attribute \generator "nMigen"
module \dec_cr_in
- attribute \src "libresoc.v:41305.3-41331.6"
+ attribute \src "libresoc.v:41496.3-41522.6"
wire width 3 $0\cr_bitfield[2:0]
- attribute \src "libresoc.v:41332.3-41342.6"
+ attribute \src "libresoc.v:41523.3-41533.6"
wire width 3 $0\cr_bitfield_b[2:0]
- attribute \src "libresoc.v:41283.3-41293.6"
+ attribute \src "libresoc.v:41474.3-41484.6"
wire $0\cr_bitfield_b_ok[0:0]
- attribute \src "libresoc.v:41343.3-41353.6"
+ attribute \src "libresoc.v:41534.3-41544.6"
wire width 3 $0\cr_bitfield_o[2:0]
- attribute \src "libresoc.v:41354.3-41364.6"
+ attribute \src "libresoc.v:41545.3-41555.6"
wire $0\cr_bitfield_o_ok[0:0]
- attribute \src "libresoc.v:41256.3-41282.6"
+ attribute \src "libresoc.v:41447.3-41473.6"
wire $0\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:41392.3-41410.6"
+ attribute \src "libresoc.v:41583.3-41601.6"
wire width 8 $0\cr_fxm[7:0]
- attribute \src "libresoc.v:41294.3-41304.6"
+ attribute \src "libresoc.v:41485.3-41495.6"
wire $0\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:41107.7-41107.20"
+ attribute \src "libresoc.v:41298.7-41298.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:41365.3-41375.6"
+ attribute \src "libresoc.v:41556.3-41566.6"
wire $0\move_one[0:0]
- attribute \src "libresoc.v:41376.3-41391.6"
+ attribute \src "libresoc.v:41567.3-41582.6"
wire width 8 $0\ppick_i[7:0]
- attribute \src "libresoc.v:41305.3-41331.6"
+ attribute \src "libresoc.v:41496.3-41522.6"
wire width 3 $1\cr_bitfield[2:0]
- attribute \src "libresoc.v:41332.3-41342.6"
+ attribute \src "libresoc.v:41523.3-41533.6"
wire width 3 $1\cr_bitfield_b[2:0]
- attribute \src "libresoc.v:41283.3-41293.6"
+ attribute \src "libresoc.v:41474.3-41484.6"
wire $1\cr_bitfield_b_ok[0:0]
- attribute \src "libresoc.v:41343.3-41353.6"
+ attribute \src "libresoc.v:41534.3-41544.6"
wire width 3 $1\cr_bitfield_o[2:0]
- attribute \src "libresoc.v:41354.3-41364.6"
+ attribute \src "libresoc.v:41545.3-41555.6"
wire $1\cr_bitfield_o_ok[0:0]
- attribute \src "libresoc.v:41256.3-41282.6"
+ attribute \src "libresoc.v:41447.3-41473.6"
wire $1\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:41392.3-41410.6"
+ attribute \src "libresoc.v:41583.3-41601.6"
wire width 8 $1\cr_fxm[7:0]
- attribute \src "libresoc.v:41294.3-41304.6"
+ attribute \src "libresoc.v:41485.3-41495.6"
wire $1\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:41365.3-41375.6"
+ attribute \src "libresoc.v:41556.3-41566.6"
wire $1\move_one[0:0]
- attribute \src "libresoc.v:41376.3-41391.6"
+ attribute \src "libresoc.v:41567.3-41582.6"
wire width 8 $1\ppick_i[7:0]
- attribute \src "libresoc.v:41392.3-41410.6"
+ attribute \src "libresoc.v:41583.3-41601.6"
wire width 8 $2\cr_fxm[7:0]
- attribute \src "libresoc.v:41376.3-41391.6"
+ attribute \src "libresoc.v:41567.3-41582.6"
wire width 8 $2\ppick_i[7:0]
- attribute \src "libresoc.v:41249.17-41249.112"
- wire $and$libresoc.v:41249$902_Y
- attribute \src "libresoc.v:41251.17-41251.112"
- wire $and$libresoc.v:41251$904_Y
- attribute \src "libresoc.v:41248.17-41248.117"
- wire $eq$libresoc.v:41248$901_Y
- attribute \src "libresoc.v:41250.17-41250.117"
- wire $eq$libresoc.v:41250$903_Y
+ attribute \src "libresoc.v:41440.17-41440.112"
+ wire $and$libresoc.v:41440$942_Y
+ attribute \src "libresoc.v:41442.17-41442.112"
+ wire $and$libresoc.v:41442$944_Y
+ attribute \src "libresoc.v:41439.17-41439.117"
+ wire $eq$libresoc.v:41439$941_Y
+ attribute \src "libresoc.v:41441.17-41441.117"
+ wire $eq$libresoc.v:41441$943_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
wire width 8 output 3 \cr_fxm
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire output 4 \cr_fxm_ok
- attribute \src "libresoc.v:41107.7-41107.15"
+ attribute \src "libresoc.v:41298.7-41298.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
wire width 32 input 18 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485"
wire width 3 input 1 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
- cell $and $and$libresoc.v:41249$902
+ cell $and $and$libresoc.v:41440$942
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \move_one
- connect \Y $and$libresoc.v:41249$902_Y
+ connect \Y $and$libresoc.v:41440$942_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
- cell $and $and$libresoc.v:41251$904
+ cell $and $and$libresoc.v:41442$944
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$5
connect \B \move_one
- connect \Y $and$libresoc.v:41251$904_Y
+ connect \Y $and$libresoc.v:41442$944_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
- cell $eq $eq$libresoc.v:41248$901
+ cell $eq $eq$libresoc.v:41439$941
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0101101
- connect \Y $eq$libresoc.v:41248$901_Y
+ connect \Y $eq$libresoc.v:41439$941_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
- cell $eq $eq$libresoc.v:41250$903
+ cell $eq $eq$libresoc.v:41441$943
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0101101
- connect \Y $eq$libresoc.v:41250$903_Y
+ connect \Y $eq$libresoc.v:41441$943_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:41252.9-41255.4"
+ attribute \src "libresoc.v:41443.9-41446.4"
cell \ppick \ppick
connect \i \ppick_i
connect \o \ppick_o
end
- attribute \src "libresoc.v:41107.7-41107.20"
- process $proc$libresoc.v:41107$915
+ attribute \src "libresoc.v:41298.7-41298.20"
+ process $proc$libresoc.v:41298$955
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:41256.3-41282.6"
- process $proc$libresoc.v:41256$905
+ attribute \src "libresoc.v:41447.3-41473.6"
+ process $proc$libresoc.v:41447$945
assign { } { }
assign { } { }
assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:41257.5-41257.29"
+ attribute \src "libresoc.v:41448.5-41448.29"
switch \initial
- attribute \src "libresoc.v:41257.9-41257.17"
+ attribute \src "libresoc.v:41448.9-41448.17"
case 1'1
case
end
sync always
update \cr_bitfield_ok $0\cr_bitfield_ok[0:0]
end
- attribute \src "libresoc.v:41283.3-41293.6"
- process $proc$libresoc.v:41283$906
+ attribute \src "libresoc.v:41474.3-41484.6"
+ process $proc$libresoc.v:41474$946
assign { } { }
assign { } { }
assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0]
- attribute \src "libresoc.v:41284.5-41284.29"
+ attribute \src "libresoc.v:41475.5-41475.29"
switch \initial
- attribute \src "libresoc.v:41284.9-41284.17"
+ attribute \src "libresoc.v:41475.9-41475.17"
case 1'1
case
end
sync always
update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0]
end
- attribute \src "libresoc.v:41294.3-41304.6"
- process $proc$libresoc.v:41294$907
+ attribute \src "libresoc.v:41485.3-41495.6"
+ process $proc$libresoc.v:41485$947
assign { } { }
assign { } { }
assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:41295.5-41295.29"
+ attribute \src "libresoc.v:41486.5-41486.29"
switch \initial
- attribute \src "libresoc.v:41295.9-41295.17"
+ attribute \src "libresoc.v:41486.9-41486.17"
case 1'1
case
end
sync always
update \cr_fxm_ok $0\cr_fxm_ok[0:0]
end
- attribute \src "libresoc.v:41305.3-41331.6"
- process $proc$libresoc.v:41305$908
+ attribute \src "libresoc.v:41496.3-41522.6"
+ process $proc$libresoc.v:41496$948
assign { } { }
assign { } { }
assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0]
- attribute \src "libresoc.v:41306.5-41306.29"
+ attribute \src "libresoc.v:41497.5-41497.29"
switch \initial
- attribute \src "libresoc.v:41306.9-41306.17"
+ attribute \src "libresoc.v:41497.9-41497.17"
case 1'1
case
end
sync always
update \cr_bitfield $0\cr_bitfield[2:0]
end
- attribute \src "libresoc.v:41332.3-41342.6"
- process $proc$libresoc.v:41332$909
+ attribute \src "libresoc.v:41523.3-41533.6"
+ process $proc$libresoc.v:41523$949
assign { } { }
assign { } { }
assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0]
- attribute \src "libresoc.v:41333.5-41333.29"
+ attribute \src "libresoc.v:41524.5-41524.29"
switch \initial
- attribute \src "libresoc.v:41333.9-41333.17"
+ attribute \src "libresoc.v:41524.9-41524.17"
case 1'1
case
end
sync always
update \cr_bitfield_b $0\cr_bitfield_b[2:0]
end
- attribute \src "libresoc.v:41343.3-41353.6"
- process $proc$libresoc.v:41343$910
+ attribute \src "libresoc.v:41534.3-41544.6"
+ process $proc$libresoc.v:41534$950
assign { } { }
assign { } { }
assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0]
- attribute \src "libresoc.v:41344.5-41344.29"
+ attribute \src "libresoc.v:41535.5-41535.29"
switch \initial
- attribute \src "libresoc.v:41344.9-41344.17"
+ attribute \src "libresoc.v:41535.9-41535.17"
case 1'1
case
end
sync always
update \cr_bitfield_o $0\cr_bitfield_o[2:0]
end
- attribute \src "libresoc.v:41354.3-41364.6"
- process $proc$libresoc.v:41354$911
+ attribute \src "libresoc.v:41545.3-41555.6"
+ process $proc$libresoc.v:41545$951
assign { } { }
assign { } { }
assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0]
- attribute \src "libresoc.v:41355.5-41355.29"
+ attribute \src "libresoc.v:41546.5-41546.29"
switch \initial
- attribute \src "libresoc.v:41355.9-41355.17"
+ attribute \src "libresoc.v:41546.9-41546.17"
case 1'1
case
end
sync always
update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0]
end
- attribute \src "libresoc.v:41365.3-41375.6"
- process $proc$libresoc.v:41365$912
+ attribute \src "libresoc.v:41556.3-41566.6"
+ process $proc$libresoc.v:41556$952
assign { } { }
assign { } { }
assign $0\move_one[0:0] $1\move_one[0:0]
- attribute \src "libresoc.v:41366.5-41366.29"
+ attribute \src "libresoc.v:41557.5-41557.29"
switch \initial
- attribute \src "libresoc.v:41366.9-41366.17"
+ attribute \src "libresoc.v:41557.9-41557.17"
case 1'1
case
end
sync always
update \move_one $0\move_one[0:0]
end
- attribute \src "libresoc.v:41376.3-41391.6"
- process $proc$libresoc.v:41376$913
+ attribute \src "libresoc.v:41567.3-41582.6"
+ process $proc$libresoc.v:41567$953
assign { } { }
assign { } { }
assign $0\ppick_i[7:0] $1\ppick_i[7:0]
- attribute \src "libresoc.v:41377.5-41377.29"
+ attribute \src "libresoc.v:41568.5-41568.29"
switch \initial
- attribute \src "libresoc.v:41377.9-41377.17"
+ attribute \src "libresoc.v:41568.9-41568.17"
case 1'1
case
end
sync always
update \ppick_i $0\ppick_i[7:0]
end
- attribute \src "libresoc.v:41392.3-41410.6"
- process $proc$libresoc.v:41392$914
+ attribute \src "libresoc.v:41583.3-41601.6"
+ process $proc$libresoc.v:41583$954
assign { } { }
assign { } { }
assign $0\cr_fxm[7:0] $1\cr_fxm[7:0]
- attribute \src "libresoc.v:41393.5-41393.29"
+ attribute \src "libresoc.v:41584.5-41584.29"
switch \initial
- attribute \src "libresoc.v:41393.9-41393.17"
+ attribute \src "libresoc.v:41584.9-41584.17"
case 1'1
case
end
sync always
update \cr_fxm $0\cr_fxm[7:0]
end
- connect \$1 $eq$libresoc.v:41248$901_Y
- connect \$3 $and$libresoc.v:41249$902_Y
- connect \$5 $eq$libresoc.v:41250$903_Y
- connect \$7 $and$libresoc.v:41251$904_Y
+ connect \$1 $eq$libresoc.v:41439$941_Y
+ connect \$3 $and$libresoc.v:41440$942_Y
+ connect \$5 $eq$libresoc.v:41441$943_Y
+ connect \$7 $and$libresoc.v:41442$944_Y
end
-attribute \src "libresoc.v:41415.1-41658.10"
+attribute \src "libresoc.v:41606.1-41849.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out"
attribute \generator "nMigen"
module \dec_cr_out
- attribute \src "libresoc.v:41572.3-41590.6"
+ attribute \src "libresoc.v:41763.3-41781.6"
wire width 3 $0\cr_bitfield[2:0]
- attribute \src "libresoc.v:41542.3-41560.6"
+ attribute \src "libresoc.v:41733.3-41751.6"
wire $0\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:41623.3-41657.6"
+ attribute \src "libresoc.v:41814.3-41848.6"
wire width 8 $0\cr_fxm[7:0]
- attribute \src "libresoc.v:41561.3-41571.6"
+ attribute \src "libresoc.v:41752.3-41762.6"
wire $0\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:41416.7-41416.20"
+ attribute \src "libresoc.v:41607.7-41607.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:41591.3-41601.6"
+ attribute \src "libresoc.v:41782.3-41792.6"
wire $0\move_one[0:0]
- attribute \src "libresoc.v:41602.3-41622.6"
+ attribute \src "libresoc.v:41793.3-41813.6"
wire width 8 $0\ppick_i[7:0]
- attribute \src "libresoc.v:41572.3-41590.6"
+ attribute \src "libresoc.v:41763.3-41781.6"
wire width 3 $1\cr_bitfield[2:0]
- attribute \src "libresoc.v:41542.3-41560.6"
+ attribute \src "libresoc.v:41733.3-41751.6"
wire $1\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:41623.3-41657.6"
+ attribute \src "libresoc.v:41814.3-41848.6"
wire width 8 $1\cr_fxm[7:0]
- attribute \src "libresoc.v:41561.3-41571.6"
+ attribute \src "libresoc.v:41752.3-41762.6"
wire $1\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:41591.3-41601.6"
+ attribute \src "libresoc.v:41782.3-41792.6"
wire $1\move_one[0:0]
- attribute \src "libresoc.v:41602.3-41622.6"
+ attribute \src "libresoc.v:41793.3-41813.6"
wire width 8 $1\ppick_i[7:0]
- attribute \src "libresoc.v:41623.3-41657.6"
+ attribute \src "libresoc.v:41814.3-41848.6"
wire width 8 $2\cr_fxm[7:0]
- attribute \src "libresoc.v:41602.3-41622.6"
+ attribute \src "libresoc.v:41793.3-41813.6"
wire width 8 $2\ppick_i[7:0]
- attribute \src "libresoc.v:41623.3-41657.6"
+ attribute \src "libresoc.v:41814.3-41848.6"
wire width 8 $3\cr_fxm[7:0]
- attribute \src "libresoc.v:41602.3-41622.6"
+ attribute \src "libresoc.v:41793.3-41813.6"
wire width 8 $3\ppick_i[7:0]
- attribute \src "libresoc.v:41623.3-41657.6"
+ attribute \src "libresoc.v:41814.3-41848.6"
wire width 8 $4\cr_fxm[7:0]
- attribute \src "libresoc.v:41535.17-41535.117"
- wire $eq$libresoc.v:41535$916_Y
- attribute \src "libresoc.v:41536.17-41536.117"
- wire $eq$libresoc.v:41536$917_Y
+ attribute \src "libresoc.v:41726.17-41726.117"
+ wire $eq$libresoc.v:41726$956_Y
+ attribute \src "libresoc.v:41727.17-41727.117"
+ wire $eq$libresoc.v:41727$957_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580"
wire width 8 output 4 \cr_fxm
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire output 5 \cr_fxm_ok
- attribute \src "libresoc.v:41416.7-41416.15"
+ attribute \src "libresoc.v:41607.7-41607.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551"
wire width 32 input 11 \insn_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550"
wire width 3 input 1 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580"
- cell $eq $eq$libresoc.v:41535$916
+ cell $eq $eq$libresoc.v:41726$956
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110000
- connect \Y $eq$libresoc.v:41535$916_Y
+ connect \Y $eq$libresoc.v:41726$956_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580"
- cell $eq $eq$libresoc.v:41536$917
+ cell $eq $eq$libresoc.v:41727$957
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110000
- connect \Y $eq$libresoc.v:41536$917_Y
+ connect \Y $eq$libresoc.v:41727$957_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:41537.13-41541.4"
+ attribute \src "libresoc.v:41728.13-41732.4"
cell \ppick$1 \ppick
connect \en_o \ppick_en_o
connect \i \ppick_i
connect \o \ppick_o
end
- attribute \src "libresoc.v:41416.7-41416.20"
- process $proc$libresoc.v:41416$924
+ attribute \src "libresoc.v:41607.7-41607.20"
+ process $proc$libresoc.v:41607$964
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:41542.3-41560.6"
- process $proc$libresoc.v:41542$918
+ attribute \src "libresoc.v:41733.3-41751.6"
+ process $proc$libresoc.v:41733$958
assign { } { }
assign { } { }
assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0]
- attribute \src "libresoc.v:41543.5-41543.29"
+ attribute \src "libresoc.v:41734.5-41734.29"
switch \initial
- attribute \src "libresoc.v:41543.9-41543.17"
+ attribute \src "libresoc.v:41734.9-41734.17"
case 1'1
case
end
sync always
update \cr_bitfield_ok $0\cr_bitfield_ok[0:0]
end
- attribute \src "libresoc.v:41561.3-41571.6"
- process $proc$libresoc.v:41561$919
+ attribute \src "libresoc.v:41752.3-41762.6"
+ process $proc$libresoc.v:41752$959
assign { } { }
assign { } { }
assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0]
- attribute \src "libresoc.v:41562.5-41562.29"
+ attribute \src "libresoc.v:41753.5-41753.29"
switch \initial
- attribute \src "libresoc.v:41562.9-41562.17"
+ attribute \src "libresoc.v:41753.9-41753.17"
case 1'1
case
end
sync always
update \cr_fxm_ok $0\cr_fxm_ok[0:0]
end
- attribute \src "libresoc.v:41572.3-41590.6"
- process $proc$libresoc.v:41572$920
+ attribute \src "libresoc.v:41763.3-41781.6"
+ process $proc$libresoc.v:41763$960
assign { } { }
assign { } { }
assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0]
- attribute \src "libresoc.v:41573.5-41573.29"
+ attribute \src "libresoc.v:41764.5-41764.29"
switch \initial
- attribute \src "libresoc.v:41573.9-41573.17"
+ attribute \src "libresoc.v:41764.9-41764.17"
case 1'1
case
end
sync always
update \cr_bitfield $0\cr_bitfield[2:0]
end
- attribute \src "libresoc.v:41591.3-41601.6"
- process $proc$libresoc.v:41591$921
+ attribute \src "libresoc.v:41782.3-41792.6"
+ process $proc$libresoc.v:41782$961
assign { } { }
assign { } { }
assign $0\move_one[0:0] $1\move_one[0:0]
- attribute \src "libresoc.v:41592.5-41592.29"
+ attribute \src "libresoc.v:41783.5-41783.29"
switch \initial
- attribute \src "libresoc.v:41592.9-41592.17"
+ attribute \src "libresoc.v:41783.9-41783.17"
case 1'1
case
end
sync always
update \move_one $0\move_one[0:0]
end
- attribute \src "libresoc.v:41602.3-41622.6"
- process $proc$libresoc.v:41602$922
+ attribute \src "libresoc.v:41793.3-41813.6"
+ process $proc$libresoc.v:41793$962
assign { } { }
assign { } { }
assign $0\ppick_i[7:0] $1\ppick_i[7:0]
- attribute \src "libresoc.v:41603.5-41603.29"
+ attribute \src "libresoc.v:41794.5-41794.29"
switch \initial
- attribute \src "libresoc.v:41603.9-41603.17"
+ attribute \src "libresoc.v:41794.9-41794.17"
case 1'1
case
end
sync always
update \ppick_i $0\ppick_i[7:0]
end
- attribute \src "libresoc.v:41623.3-41657.6"
- process $proc$libresoc.v:41623$923
+ attribute \src "libresoc.v:41814.3-41848.6"
+ process $proc$libresoc.v:41814$963
assign { } { }
assign { } { }
assign $0\cr_fxm[7:0] $1\cr_fxm[7:0]
- attribute \src "libresoc.v:41624.5-41624.29"
+ attribute \src "libresoc.v:41815.5-41815.29"
switch \initial
- attribute \src "libresoc.v:41624.9-41624.17"
+ attribute \src "libresoc.v:41815.9-41815.17"
case 1'1
case
end
sync always
update \cr_fxm $0\cr_fxm[7:0]
end
- connect \$1 $eq$libresoc.v:41535$916_Y
- connect \$3 $eq$libresoc.v:41536$917_Y
+ connect \$1 $eq$libresoc.v:41726$956_Y
+ connect \$3 $eq$libresoc.v:41727$957_Y
end
-attribute \src "libresoc.v:41662.1-42139.10"
+attribute \src "libresoc.v:41853.1-42330.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec_o"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o"
attribute \generator "nMigen"
module \dec_o
- attribute \src "libresoc.v:42100.3-42138.6"
+ attribute \src "libresoc.v:42291.3-42329.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:42100.3-42138.6"
+ attribute \src "libresoc.v:42291.3-42329.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:41663.7-41663.20"
+ attribute \src "libresoc.v:41854.7-41854.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:42026.3-42040.6"
+ attribute \src "libresoc.v:42217.3-42231.6"
wire width 5 $0\reg_o[4:0]
- attribute \src "libresoc.v:42041.3-42055.6"
+ attribute \src "libresoc.v:42232.3-42246.6"
wire $0\reg_o_ok[0:0]
- attribute \src "libresoc.v:42056.3-42066.6"
+ attribute \src "libresoc.v:42247.3-42257.6"
wire width 10 $0\spr[9:0]
- attribute \src "libresoc.v:42083.3-42099.6"
+ attribute \src "libresoc.v:42274.3-42290.6"
wire width 10 $0\spr_o[9:0]
- attribute \src "libresoc.v:42083.3-42099.6"
+ attribute \src "libresoc.v:42274.3-42290.6"
wire $0\spr_o_ok[0:0]
- attribute \src "libresoc.v:42067.3-42082.6"
+ attribute \src "libresoc.v:42258.3-42273.6"
wire width 10 $0\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:42100.3-42138.6"
+ attribute \src "libresoc.v:42291.3-42329.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:42100.3-42138.6"
+ attribute \src "libresoc.v:42291.3-42329.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:42026.3-42040.6"
+ attribute \src "libresoc.v:42217.3-42231.6"
wire width 5 $1\reg_o[4:0]
- attribute \src "libresoc.v:42041.3-42055.6"
+ attribute \src "libresoc.v:42232.3-42246.6"
wire $1\reg_o_ok[0:0]
- attribute \src "libresoc.v:42056.3-42066.6"
+ attribute \src "libresoc.v:42247.3-42257.6"
wire width 10 $1\spr[9:0]
- attribute \src "libresoc.v:42083.3-42099.6"
+ attribute \src "libresoc.v:42274.3-42290.6"
wire width 10 $1\spr_o[9:0]
- attribute \src "libresoc.v:42083.3-42099.6"
+ attribute \src "libresoc.v:42274.3-42290.6"
wire $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:42067.3-42082.6"
+ attribute \src "libresoc.v:42258.3-42273.6"
wire width 10 $1\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:42100.3-42138.6"
+ attribute \src "libresoc.v:42291.3-42329.6"
wire width 3 $2\fast_o[2:0]
- attribute \src "libresoc.v:42100.3-42138.6"
+ attribute \src "libresoc.v:42291.3-42329.6"
wire $2\fast_o_ok[0:0]
- attribute \src "libresoc.v:42083.3-42099.6"
+ attribute \src "libresoc.v:42274.3-42290.6"
wire width 10 $2\spr_o[9:0]
- attribute \src "libresoc.v:42083.3-42099.6"
+ attribute \src "libresoc.v:42274.3-42290.6"
wire $2\spr_o_ok[0:0]
- attribute \src "libresoc.v:42067.3-42082.6"
+ attribute \src "libresoc.v:42258.3-42273.6"
wire width 10 $2\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:42100.3-42138.6"
+ attribute \src "libresoc.v:42291.3-42329.6"
wire width 3 $3\fast_o[2:0]
- attribute \src "libresoc.v:42100.3-42138.6"
+ attribute \src "libresoc.v:42291.3-42329.6"
wire $3\fast_o_ok[0:0]
- attribute \src "libresoc.v:42100.3-42138.6"
+ attribute \src "libresoc.v:42291.3-42329.6"
wire width 3 $4\fast_o[2:0]
- attribute \src "libresoc.v:42100.3-42138.6"
+ attribute \src "libresoc.v:42291.3-42329.6"
wire $4\fast_o_ok[0:0]
- attribute \src "libresoc.v:42015.17-42015.117"
- wire $eq$libresoc.v:42015$925_Y
- attribute \src "libresoc.v:42016.17-42016.117"
- wire $eq$libresoc.v:42016$926_Y
- attribute \src "libresoc.v:42017.17-42017.117"
- wire $eq$libresoc.v:42017$927_Y
- attribute \src "libresoc.v:42018.17-42018.104"
- wire $not$libresoc.v:42018$928_Y
+ attribute \src "libresoc.v:42206.17-42206.117"
+ wire $eq$libresoc.v:42206$965_Y
+ attribute \src "libresoc.v:42207.17-42207.117"
+ wire $eq$libresoc.v:42207$966_Y
+ attribute \src "libresoc.v:42208.17-42208.117"
+ wire $eq$libresoc.v:42208$967_Y
+ attribute \src "libresoc.v:42209.17-42209.104"
+ wire $not$libresoc.v:42209$968_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332"
wire width 3 output 6 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire output 7 \fast_o_ok
- attribute \src "libresoc.v:41663.7-41663.15"
+ attribute \src "libresoc.v:41854.7-41854.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire \sprmap_spr_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332"
- cell $eq $eq$libresoc.v:42015$925
+ cell $eq $eq$libresoc.v:42206$965
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:42015$925_Y
+ connect \Y $eq$libresoc.v:42206$965_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332"
- cell $eq $eq$libresoc.v:42016$926
+ cell $eq $eq$libresoc.v:42207$966
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:42016$926_Y
+ connect \Y $eq$libresoc.v:42207$966_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332"
- cell $eq $eq$libresoc.v:42017$927
+ cell $eq $eq$libresoc.v:42208$967
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110001
- connect \Y $eq$libresoc.v:42017$927_Y
+ connect \Y $eq$libresoc.v:42208$967_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341"
- cell $not $not$libresoc.v:42018$928
+ cell $not $not$libresoc.v:42209$968
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \BO [2]
- connect \Y $not$libresoc.v:42018$928_Y
+ connect \Y $not$libresoc.v:42209$968_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:42019.14-42025.4"
+ attribute \src "libresoc.v:42210.14-42216.4"
cell \sprmap$2 \sprmap
connect \fast_o \sprmap_fast_o
connect \fast_o_ok \sprmap_fast_o_ok
connect \spr_o \sprmap_spr_o
connect \spr_o_ok \sprmap_spr_o_ok
end
- attribute \src "libresoc.v:41663.7-41663.20"
- process $proc$libresoc.v:41663$935
+ attribute \src "libresoc.v:41854.7-41854.20"
+ process $proc$libresoc.v:41854$975
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:42026.3-42040.6"
- process $proc$libresoc.v:42026$929
+ attribute \src "libresoc.v:42217.3-42231.6"
+ process $proc$libresoc.v:42217$969
assign { } { }
assign { } { }
assign $0\reg_o[4:0] $1\reg_o[4:0]
- attribute \src "libresoc.v:42027.5-42027.29"
+ attribute \src "libresoc.v:42218.5-42218.29"
switch \initial
- attribute \src "libresoc.v:42027.9-42027.17"
+ attribute \src "libresoc.v:42218.9-42218.17"
case 1'1
case
end
sync always
update \reg_o $0\reg_o[4:0]
end
- attribute \src "libresoc.v:42041.3-42055.6"
- process $proc$libresoc.v:42041$930
+ attribute \src "libresoc.v:42232.3-42246.6"
+ process $proc$libresoc.v:42232$970
assign { } { }
assign { } { }
assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0]
- attribute \src "libresoc.v:42042.5-42042.29"
+ attribute \src "libresoc.v:42233.5-42233.29"
switch \initial
- attribute \src "libresoc.v:42042.9-42042.17"
+ attribute \src "libresoc.v:42233.9-42233.17"
case 1'1
case
end
sync always
update \reg_o_ok $0\reg_o_ok[0:0]
end
- attribute \src "libresoc.v:42056.3-42066.6"
- process $proc$libresoc.v:42056$931
+ attribute \src "libresoc.v:42247.3-42257.6"
+ process $proc$libresoc.v:42247$971
assign { } { }
assign { } { }
assign $0\spr[9:0] $1\spr[9:0]
- attribute \src "libresoc.v:42057.5-42057.29"
+ attribute \src "libresoc.v:42248.5-42248.29"
switch \initial
- attribute \src "libresoc.v:42057.9-42057.17"
+ attribute \src "libresoc.v:42248.9-42248.17"
case 1'1
case
end
sync always
update \spr $0\spr[9:0]
end
- attribute \src "libresoc.v:42067.3-42082.6"
- process $proc$libresoc.v:42067$932
+ attribute \src "libresoc.v:42258.3-42273.6"
+ process $proc$libresoc.v:42258$972
assign { } { }
assign { } { }
assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0]
- attribute \src "libresoc.v:42068.5-42068.29"
+ attribute \src "libresoc.v:42259.5-42259.29"
switch \initial
- attribute \src "libresoc.v:42068.9-42068.17"
+ attribute \src "libresoc.v:42259.9-42259.17"
case 1'1
case
end
sync always
update \sprmap_spr_i $0\sprmap_spr_i[9:0]
end
- attribute \src "libresoc.v:42083.3-42099.6"
- process $proc$libresoc.v:42083$933
+ attribute \src "libresoc.v:42274.3-42290.6"
+ process $proc$libresoc.v:42274$973
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\spr_o[9:0] $1\spr_o[9:0]
assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:42084.5-42084.29"
+ attribute \src "libresoc.v:42275.5-42275.29"
switch \initial
- attribute \src "libresoc.v:42084.9-42084.17"
+ attribute \src "libresoc.v:42275.9-42275.17"
case 1'1
case
end
update \spr_o $0\spr_o[9:0]
update \spr_o_ok $0\spr_o_ok[0:0]
end
- attribute \src "libresoc.v:42100.3-42138.6"
- process $proc$libresoc.v:42100$934
+ attribute \src "libresoc.v:42291.3-42329.6"
+ process $proc$libresoc.v:42291$974
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $3\fast_o[2:0]
assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0]
- attribute \src "libresoc.v:42101.5-42101.29"
+ attribute \src "libresoc.v:42292.5-42292.29"
switch \initial
- attribute \src "libresoc.v:42101.9-42101.17"
+ attribute \src "libresoc.v:42292.9-42292.17"
case 1'1
case
end
update \fast_o $0\fast_o[2:0]
update \fast_o_ok $0\fast_o_ok[0:0]
end
- connect \$1 $eq$libresoc.v:42015$925_Y
- connect \$3 $eq$libresoc.v:42016$926_Y
- connect \$5 $eq$libresoc.v:42017$927_Y
- connect \$7 $not$libresoc.v:42018$928_Y
+ connect \$1 $eq$libresoc.v:42206$965_Y
+ connect \$3 $eq$libresoc.v:42207$966_Y
+ connect \$5 $eq$libresoc.v:42208$967_Y
+ connect \$7 $not$libresoc.v:42209$968_Y
end
-attribute \src "libresoc.v:42143.1-42304.10"
+attribute \src "libresoc.v:42334.1-42495.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec_o2"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2"
attribute \generator "nMigen"
module \dec_o2
- attribute \src "libresoc.v:42264.3-42283.6"
+ attribute \src "libresoc.v:42455.3-42474.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:42284.3-42303.6"
+ attribute \src "libresoc.v:42475.3-42494.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:42144.7-42144.20"
+ attribute \src "libresoc.v:42335.7-42335.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:42250.3-42263.6"
+ attribute \src "libresoc.v:42441.3-42454.6"
wire width 5 $0\reg_o[4:0]
- attribute \src "libresoc.v:42250.3-42263.6"
+ attribute \src "libresoc.v:42441.3-42454.6"
wire $0\reg_o_ok[0:0]
- attribute \src "libresoc.v:42264.3-42283.6"
+ attribute \src "libresoc.v:42455.3-42474.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:42284.3-42303.6"
+ attribute \src "libresoc.v:42475.3-42494.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:42250.3-42263.6"
+ attribute \src "libresoc.v:42441.3-42454.6"
wire width 5 $1\reg_o[4:0]
- attribute \src "libresoc.v:42250.3-42263.6"
+ attribute \src "libresoc.v:42441.3-42454.6"
wire $1\reg_o_ok[0:0]
- attribute \src "libresoc.v:42264.3-42283.6"
+ attribute \src "libresoc.v:42455.3-42474.6"
wire width 3 $2\fast_o[2:0]
- attribute \src "libresoc.v:42284.3-42303.6"
+ attribute \src "libresoc.v:42475.3-42494.6"
wire $2\fast_o_ok[0:0]
- attribute \src "libresoc.v:42248.17-42248.108"
- wire $eq$libresoc.v:42248$936_Y
- attribute \src "libresoc.v:42249.17-42249.100"
- wire width 6 $extend$libresoc.v:42249$937_Y
- attribute \src "libresoc.v:42249.17-42249.100"
- wire width 6 $pos$libresoc.v:42249$938_Y
+ attribute \src "libresoc.v:42439.17-42439.108"
+ wire $eq$libresoc.v:42439$976_Y
+ attribute \src "libresoc.v:42440.17-42440.100"
+ wire width 6 $extend$libresoc.v:42440$977_Y
+ attribute \src "libresoc.v:42440.17-42440.100"
+ wire width 6 $pos$libresoc.v:42440$978_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447"
wire width 3 output 4 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire output 5 \fast_o_ok
- attribute \src "libresoc.v:42144.7-42144.15"
+ attribute \src "libresoc.v:42335.7-42335.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168"
wire width 2 input 6 \upd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
- cell $eq $eq$libresoc.v:42248$936
+ cell $eq $eq$libresoc.v:42439$976
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \upd
connect \B 2'01
- connect \Y $eq$libresoc.v:42248$936_Y
+ connect \Y $eq$libresoc.v:42439$976_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447"
- cell $pos $extend$libresoc.v:42249$937
+ cell $pos $extend$libresoc.v:42440$977
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 6
connect \A \RA
- connect \Y $extend$libresoc.v:42249$937_Y
+ connect \Y $extend$libresoc.v:42440$977_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447"
- cell $pos $pos$libresoc.v:42249$938
+ cell $pos $pos$libresoc.v:42440$978
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
- connect \A $extend$libresoc.v:42249$937_Y
- connect \Y $pos$libresoc.v:42249$938_Y
+ connect \A $extend$libresoc.v:42440$977_Y
+ connect \Y $pos$libresoc.v:42440$978_Y
end
- attribute \src "libresoc.v:42144.7-42144.20"
- process $proc$libresoc.v:42144$942
+ attribute \src "libresoc.v:42335.7-42335.20"
+ process $proc$libresoc.v:42335$982
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:42250.3-42263.6"
- process $proc$libresoc.v:42250$939
+ attribute \src "libresoc.v:42441.3-42454.6"
+ process $proc$libresoc.v:42441$979
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\reg_o[4:0] $1\reg_o[4:0]
assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0]
- attribute \src "libresoc.v:42251.5-42251.29"
+ attribute \src "libresoc.v:42442.5-42442.29"
switch \initial
- attribute \src "libresoc.v:42251.9-42251.17"
+ attribute \src "libresoc.v:42442.9-42442.17"
case 1'1
case
end
update \reg_o $0\reg_o[4:0]
update \reg_o_ok $0\reg_o_ok[0:0]
end
- attribute \src "libresoc.v:42264.3-42283.6"
- process $proc$libresoc.v:42264$940
+ attribute \src "libresoc.v:42455.3-42474.6"
+ process $proc$libresoc.v:42455$980
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $1\fast_o[2:0]
- attribute \src "libresoc.v:42265.5-42265.29"
+ attribute \src "libresoc.v:42456.5-42456.29"
switch \initial
- attribute \src "libresoc.v:42265.9-42265.17"
+ attribute \src "libresoc.v:42456.9-42456.17"
case 1'1
case
end
sync always
update \fast_o $0\fast_o[2:0]
end
- attribute \src "libresoc.v:42284.3-42303.6"
- process $proc$libresoc.v:42284$941
+ attribute \src "libresoc.v:42475.3-42494.6"
+ process $proc$libresoc.v:42475$981
assign { } { }
assign { } { }
assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:42285.5-42285.29"
+ attribute \src "libresoc.v:42476.5-42476.29"
switch \initial
- attribute \src "libresoc.v:42285.9-42285.17"
+ attribute \src "libresoc.v:42476.9-42476.17"
case 1'1
case
end
sync always
update \fast_o_ok $0\fast_o_ok[0:0]
end
- connect \$1 $eq$libresoc.v:42248$936_Y
- connect \$3 $pos$libresoc.v:42249$938_Y
+ connect \$1 $eq$libresoc.v:42439$976_Y
+ connect \$3 $pos$libresoc.v:42440$978_Y
end
-attribute \src "libresoc.v:42308.1-42442.10"
+attribute \src "libresoc.v:42499.1-42633.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec_oe"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe"
attribute \generator "nMigen"
module \dec_oe
- attribute \src "libresoc.v:42309.7-42309.20"
+ attribute \src "libresoc.v:42500.7-42500.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:42400.3-42420.6"
+ attribute \src "libresoc.v:42591.3-42611.6"
wire $0\oe[0:0]
- attribute \src "libresoc.v:42421.3-42441.6"
+ attribute \src "libresoc.v:42612.3-42632.6"
wire $0\oe_ok[0:0]
- attribute \src "libresoc.v:42400.3-42420.6"
+ attribute \src "libresoc.v:42591.3-42611.6"
wire $1\oe[0:0]
- attribute \src "libresoc.v:42421.3-42441.6"
+ attribute \src "libresoc.v:42612.3-42632.6"
wire $1\oe_ok[0:0]
- attribute \src "libresoc.v:42400.3-42420.6"
+ attribute \src "libresoc.v:42591.3-42611.6"
wire $2\oe[0:0]
- attribute \src "libresoc.v:42421.3-42441.6"
+ attribute \src "libresoc.v:42612.3-42632.6"
wire $2\oe_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447"
wire input 4 \OE
- attribute \src "libresoc.v:42309.7-42309.15"
+ attribute \src "libresoc.v:42500.7-42500.15"
wire \initial
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
wire width 2 input 5 \sel_in
- attribute \src "libresoc.v:42309.7-42309.20"
- process $proc$libresoc.v:42309$945
+ attribute \src "libresoc.v:42500.7-42500.20"
+ process $proc$libresoc.v:42500$985
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:42400.3-42420.6"
- process $proc$libresoc.v:42400$943
+ attribute \src "libresoc.v:42591.3-42611.6"
+ process $proc$libresoc.v:42591$983
assign { } { }
assign { } { }
assign $0\oe[0:0] $1\oe[0:0]
- attribute \src "libresoc.v:42401.5-42401.29"
+ attribute \src "libresoc.v:42592.5-42592.29"
switch \initial
- attribute \src "libresoc.v:42401.9-42401.17"
+ attribute \src "libresoc.v:42592.9-42592.17"
case 1'1
case
end
sync always
update \oe $0\oe[0:0]
end
- attribute \src "libresoc.v:42421.3-42441.6"
- process $proc$libresoc.v:42421$944
+ attribute \src "libresoc.v:42612.3-42632.6"
+ process $proc$libresoc.v:42612$984
assign { } { }
assign { } { }
assign $0\oe_ok[0:0] $1\oe_ok[0:0]
- attribute \src "libresoc.v:42422.5-42422.29"
+ attribute \src "libresoc.v:42613.5-42613.29"
switch \initial
- attribute \src "libresoc.v:42422.9-42422.17"
+ attribute \src "libresoc.v:42613.9-42613.17"
case 1'1
case
end
update \oe_ok $0\oe_ok[0:0]
end
end
-attribute \src "libresoc.v:42446.1-42500.10"
+attribute \src "libresoc.v:42637.1-42691.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec_rc"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc"
attribute \generator "nMigen"
module \dec_rc
- attribute \src "libresoc.v:42447.7-42447.20"
+ attribute \src "libresoc.v:42638.7-42638.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:42462.3-42480.6"
+ attribute \src "libresoc.v:42653.3-42671.6"
wire $0\rc[0:0]
- attribute \src "libresoc.v:42481.3-42499.6"
+ attribute \src "libresoc.v:42672.3-42690.6"
wire $0\rc_ok[0:0]
- attribute \src "libresoc.v:42462.3-42480.6"
+ attribute \src "libresoc.v:42653.3-42671.6"
wire $1\rc[0:0]
- attribute \src "libresoc.v:42481.3-42499.6"
+ attribute \src "libresoc.v:42672.3-42690.6"
wire $1\rc_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447"
wire input 3 \Rc
- attribute \src "libresoc.v:42447.7-42447.15"
+ attribute \src "libresoc.v:42638.7-42638.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire output 1 \rc
attribute \enum_value_10 "RC"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405"
wire width 2 input 4 \sel_in
- attribute \src "libresoc.v:42447.7-42447.20"
- process $proc$libresoc.v:42447$948
+ attribute \src "libresoc.v:42638.7-42638.20"
+ process $proc$libresoc.v:42638$988
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:42462.3-42480.6"
- process $proc$libresoc.v:42462$946
+ attribute \src "libresoc.v:42653.3-42671.6"
+ process $proc$libresoc.v:42653$986
assign { } { }
assign { } { }
assign $0\rc[0:0] $1\rc[0:0]
- attribute \src "libresoc.v:42463.5-42463.29"
+ attribute \src "libresoc.v:42654.5-42654.29"
switch \initial
- attribute \src "libresoc.v:42463.9-42463.17"
+ attribute \src "libresoc.v:42654.9-42654.17"
case 1'1
case
end
sync always
update \rc $0\rc[0:0]
end
- attribute \src "libresoc.v:42481.3-42499.6"
- process $proc$libresoc.v:42481$947
+ attribute \src "libresoc.v:42672.3-42690.6"
+ process $proc$libresoc.v:42672$987
assign { } { }
assign { } { }
assign $0\rc_ok[0:0] $1\rc_ok[0:0]
- attribute \src "libresoc.v:42482.5-42482.29"
+ attribute \src "libresoc.v:42673.5-42673.29"
switch \initial
- attribute \src "libresoc.v:42482.9-42482.17"
+ attribute \src "libresoc.v:42673.9-42673.17"
case 1'1
case
end
update \rc_ok $0\rc_ok[0:0]
end
end
-attribute \src "libresoc.v:42504.1-42826.10"
+attribute \src "libresoc.v:42695.1-43017.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.imem"
+attribute \nmigen.hierarchy "test_issuer.ti.imem"
attribute \generator "nMigen"
module \imem
- attribute \src "libresoc.v:42783.3-42797.6"
- wire width 45 $0\f_badaddr_o$next[44:0]$1011
- attribute \src "libresoc.v:42644.3-42645.39"
+ attribute \src "libresoc.v:42974.3-42988.6"
+ wire width 45 $0\f_badaddr_o$next[44:0]$1051
+ attribute \src "libresoc.v:42835.3-42836.39"
wire width 45 $0\f_badaddr_o[44:0]
- attribute \src "libresoc.v:42798.3-42809.6"
+ attribute \src "libresoc.v:42989.3-43000.6"
wire $0\f_busy_o[0:0]
- attribute \src "libresoc.v:42765.3-42782.6"
- wire $0\f_fetch_err_o$next[0:0]$1007
- attribute \src "libresoc.v:42646.3-42647.43"
+ attribute \src "libresoc.v:42956.3-42973.6"
+ wire $0\f_fetch_err_o$next[0:0]$1047
+ attribute \src "libresoc.v:42837.3-42838.43"
wire $0\f_fetch_err_o[0:0]
- attribute \src "libresoc.v:42810.3-42822.6"
+ attribute \src "libresoc.v:43001.3-43013.6"
wire width 64 $0\f_instr_o[63:0]
- attribute \src "libresoc.v:42747.3-42764.6"
- wire width 45 $0\ibus__adr$next[44:0]$1003
- attribute \src "libresoc.v:42648.3-42649.35"
+ attribute \src "libresoc.v:42938.3-42955.6"
+ wire width 45 $0\ibus__adr$next[44:0]$1043
+ attribute \src "libresoc.v:42839.3-42840.35"
wire width 45 $0\ibus__adr[44:0]
- attribute \src "libresoc.v:42658.3-42680.6"
- wire $0\ibus__cyc$next[0:0]$983
- attribute \src "libresoc.v:42656.3-42657.35"
+ attribute \src "libresoc.v:42849.3-42871.6"
+ wire $0\ibus__cyc$next[0:0]$1023
+ attribute \src "libresoc.v:42847.3-42848.35"
wire $0\ibus__cyc[0:0]
- attribute \src "libresoc.v:42704.3-42726.6"
- wire width 8 $0\ibus__sel$next[7:0]$993
- attribute \src "libresoc.v:42652.3-42653.35"
+ attribute \src "libresoc.v:42895.3-42917.6"
+ wire width 8 $0\ibus__sel$next[7:0]$1033
+ attribute \src "libresoc.v:42843.3-42844.35"
wire width 8 $0\ibus__sel[7:0]
- attribute \src "libresoc.v:42681.3-42703.6"
- wire $0\ibus__stb$next[0:0]$988
- attribute \src "libresoc.v:42654.3-42655.35"
+ attribute \src "libresoc.v:42872.3-42894.6"
+ wire $0\ibus__stb$next[0:0]$1028
+ attribute \src "libresoc.v:42845.3-42846.35"
wire $0\ibus__stb[0:0]
- attribute \src "libresoc.v:42727.3-42746.6"
- wire width 64 $0\ibus_rdata$next[63:0]$998
- attribute \src "libresoc.v:42650.3-42651.37"
+ attribute \src "libresoc.v:42918.3-42937.6"
+ wire width 64 $0\ibus_rdata$next[63:0]$1038
+ attribute \src "libresoc.v:42841.3-42842.37"
wire width 64 $0\ibus_rdata[63:0]
- attribute \src "libresoc.v:42505.7-42505.20"
+ attribute \src "libresoc.v:42696.7-42696.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:42783.3-42797.6"
- wire width 45 $1\f_badaddr_o$next[44:0]$1012
- attribute \src "libresoc.v:42569.14-42569.44"
+ attribute \src "libresoc.v:42974.3-42988.6"
+ wire width 45 $1\f_badaddr_o$next[44:0]$1052
+ attribute \src "libresoc.v:42758.14-42758.44"
wire width 45 $1\f_badaddr_o[44:0]
- attribute \src "libresoc.v:42798.3-42809.6"
+ attribute \src "libresoc.v:42989.3-43000.6"
wire $1\f_busy_o[0:0]
- attribute \src "libresoc.v:42765.3-42782.6"
- wire $1\f_fetch_err_o$next[0:0]$1008
- attribute \src "libresoc.v:42576.7-42576.27"
+ attribute \src "libresoc.v:42956.3-42973.6"
+ wire $1\f_fetch_err_o$next[0:0]$1048
+ attribute \src "libresoc.v:42765.7-42765.27"
wire $1\f_fetch_err_o[0:0]
- attribute \src "libresoc.v:42810.3-42822.6"
+ attribute \src "libresoc.v:43001.3-43013.6"
wire width 64 $1\f_instr_o[63:0]
- attribute \src "libresoc.v:42747.3-42764.6"
- wire width 45 $1\ibus__adr$next[44:0]$1004
- attribute \src "libresoc.v:42590.14-42590.42"
+ attribute \src "libresoc.v:42938.3-42955.6"
+ wire width 45 $1\ibus__adr$next[44:0]$1044
+ attribute \src "libresoc.v:42779.14-42779.42"
wire width 45 $1\ibus__adr[44:0]
- attribute \src "libresoc.v:42658.3-42680.6"
- wire $1\ibus__cyc$next[0:0]$984
- attribute \src "libresoc.v:42595.7-42595.23"
+ attribute \src "libresoc.v:42849.3-42871.6"
+ wire $1\ibus__cyc$next[0:0]$1024
+ attribute \src "libresoc.v:42784.7-42784.23"
wire $1\ibus__cyc[0:0]
- attribute \src "libresoc.v:42704.3-42726.6"
- wire width 8 $1\ibus__sel$next[7:0]$994
- attribute \src "libresoc.v:42604.13-42604.30"
+ attribute \src "libresoc.v:42895.3-42917.6"
+ wire width 8 $1\ibus__sel$next[7:0]$1034
+ attribute \src "libresoc.v:42793.13-42793.30"
wire width 8 $1\ibus__sel[7:0]
- attribute \src "libresoc.v:42681.3-42703.6"
- wire $1\ibus__stb$next[0:0]$989
- attribute \src "libresoc.v:42609.7-42609.23"
+ attribute \src "libresoc.v:42872.3-42894.6"
+ wire $1\ibus__stb$next[0:0]$1029
+ attribute \src "libresoc.v:42798.7-42798.23"
wire $1\ibus__stb[0:0]
- attribute \src "libresoc.v:42727.3-42746.6"
- wire width 64 $1\ibus_rdata$next[63:0]$999
- attribute \src "libresoc.v:42613.14-42613.47"
+ attribute \src "libresoc.v:42918.3-42937.6"
+ wire width 64 $1\ibus_rdata$next[63:0]$1039
+ attribute \src "libresoc.v:42802.14-42802.47"
wire width 64 $1\ibus_rdata[63:0]
- attribute \src "libresoc.v:42783.3-42797.6"
- wire width 45 $2\f_badaddr_o$next[44:0]$1013
- attribute \src "libresoc.v:42765.3-42782.6"
- wire $2\f_fetch_err_o$next[0:0]$1009
- attribute \src "libresoc.v:42747.3-42764.6"
- wire width 45 $2\ibus__adr$next[44:0]$1005
- attribute \src "libresoc.v:42658.3-42680.6"
- wire $2\ibus__cyc$next[0:0]$985
- attribute \src "libresoc.v:42704.3-42726.6"
- wire width 8 $2\ibus__sel$next[7:0]$995
- attribute \src "libresoc.v:42681.3-42703.6"
- wire $2\ibus__stb$next[0:0]$990
- attribute \src "libresoc.v:42727.3-42746.6"
- wire width 64 $2\ibus_rdata$next[63:0]$1000
- attribute \src "libresoc.v:42658.3-42680.6"
- wire $3\ibus__cyc$next[0:0]$986
- attribute \src "libresoc.v:42704.3-42726.6"
- wire width 8 $3\ibus__sel$next[7:0]$996
- attribute \src "libresoc.v:42681.3-42703.6"
- wire $3\ibus__stb$next[0:0]$991
- attribute \src "libresoc.v:42727.3-42746.6"
- wire width 64 $3\ibus_rdata$next[63:0]$1001
- attribute \src "libresoc.v:42620.18-42620.110"
- wire $and$libresoc.v:42620$951_Y
- attribute \src "libresoc.v:42626.18-42626.110"
- wire $and$libresoc.v:42626$957_Y
- attribute \src "libresoc.v:42631.18-42631.110"
- wire $and$libresoc.v:42631$962_Y
- attribute \src "libresoc.v:42634.17-42634.108"
- wire $and$libresoc.v:42634$965_Y
- attribute \src "libresoc.v:42637.18-42637.110"
- wire $and$libresoc.v:42637$968_Y
- attribute \src "libresoc.v:42638.18-42638.115"
- wire $and$libresoc.v:42638$969_Y
- attribute \src "libresoc.v:42640.18-42640.115"
- wire $and$libresoc.v:42640$971_Y
- attribute \src "libresoc.v:42619.18-42619.105"
- wire $not$libresoc.v:42619$950_Y
- attribute \src "libresoc.v:42622.18-42622.105"
- wire $not$libresoc.v:42622$953_Y
- attribute \src "libresoc.v:42623.17-42623.104"
- wire $not$libresoc.v:42623$954_Y
- attribute \src "libresoc.v:42625.18-42625.105"
- wire $not$libresoc.v:42625$956_Y
- attribute \src "libresoc.v:42628.18-42628.105"
- wire $not$libresoc.v:42628$959_Y
- attribute \src "libresoc.v:42630.18-42630.105"
- wire $not$libresoc.v:42630$961_Y
- attribute \src "libresoc.v:42633.18-42633.105"
- wire $not$libresoc.v:42633$964_Y
- attribute \src "libresoc.v:42636.18-42636.105"
- wire $not$libresoc.v:42636$967_Y
- attribute \src "libresoc.v:42639.18-42639.105"
- wire $not$libresoc.v:42639$970_Y
- attribute \src "libresoc.v:42641.18-42641.105"
- wire $not$libresoc.v:42641$972_Y
- attribute \src "libresoc.v:42643.17-42643.104"
- wire $not$libresoc.v:42643$974_Y
- attribute \src "libresoc.v:42618.17-42618.103"
- wire $or$libresoc.v:42618$949_Y
- attribute \src "libresoc.v:42621.18-42621.115"
- wire $or$libresoc.v:42621$952_Y
- attribute \src "libresoc.v:42624.18-42624.106"
- wire $or$libresoc.v:42624$955_Y
- attribute \src "libresoc.v:42627.18-42627.115"
- wire $or$libresoc.v:42627$958_Y
- attribute \src "libresoc.v:42629.18-42629.106"
- wire $or$libresoc.v:42629$960_Y
- attribute \src "libresoc.v:42632.18-42632.115"
- wire $or$libresoc.v:42632$963_Y
- attribute \src "libresoc.v:42635.18-42635.106"
- wire $or$libresoc.v:42635$966_Y
- attribute \src "libresoc.v:42642.17-42642.114"
- wire $or$libresoc.v:42642$973_Y
+ attribute \src "libresoc.v:42974.3-42988.6"
+ wire width 45 $2\f_badaddr_o$next[44:0]$1053
+ attribute \src "libresoc.v:42956.3-42973.6"
+ wire $2\f_fetch_err_o$next[0:0]$1049
+ attribute \src "libresoc.v:42938.3-42955.6"
+ wire width 45 $2\ibus__adr$next[44:0]$1045
+ attribute \src "libresoc.v:42849.3-42871.6"
+ wire $2\ibus__cyc$next[0:0]$1025
+ attribute \src "libresoc.v:42895.3-42917.6"
+ wire width 8 $2\ibus__sel$next[7:0]$1035
+ attribute \src "libresoc.v:42872.3-42894.6"
+ wire $2\ibus__stb$next[0:0]$1030
+ attribute \src "libresoc.v:42918.3-42937.6"
+ wire width 64 $2\ibus_rdata$next[63:0]$1040
+ attribute \src "libresoc.v:42849.3-42871.6"
+ wire $3\ibus__cyc$next[0:0]$1026
+ attribute \src "libresoc.v:42895.3-42917.6"
+ wire width 8 $3\ibus__sel$next[7:0]$1036
+ attribute \src "libresoc.v:42872.3-42894.6"
+ wire $3\ibus__stb$next[0:0]$1031
+ attribute \src "libresoc.v:42918.3-42937.6"
+ wire width 64 $3\ibus_rdata$next[63:0]$1041
+ attribute \src "libresoc.v:42811.18-42811.110"
+ wire $and$libresoc.v:42811$991_Y
+ attribute \src "libresoc.v:42817.18-42817.110"
+ wire $and$libresoc.v:42817$997_Y
+ attribute \src "libresoc.v:42822.18-42822.110"
+ wire $and$libresoc.v:42822$1002_Y
+ attribute \src "libresoc.v:42825.17-42825.108"
+ wire $and$libresoc.v:42825$1005_Y
+ attribute \src "libresoc.v:42828.18-42828.110"
+ wire $and$libresoc.v:42828$1008_Y
+ attribute \src "libresoc.v:42829.18-42829.115"
+ wire $and$libresoc.v:42829$1009_Y
+ attribute \src "libresoc.v:42831.18-42831.115"
+ wire $and$libresoc.v:42831$1011_Y
+ attribute \src "libresoc.v:42810.18-42810.105"
+ wire $not$libresoc.v:42810$990_Y
+ attribute \src "libresoc.v:42813.18-42813.105"
+ wire $not$libresoc.v:42813$993_Y
+ attribute \src "libresoc.v:42814.17-42814.104"
+ wire $not$libresoc.v:42814$994_Y
+ attribute \src "libresoc.v:42816.18-42816.105"
+ wire $not$libresoc.v:42816$996_Y
+ attribute \src "libresoc.v:42819.18-42819.105"
+ wire $not$libresoc.v:42819$999_Y
+ attribute \src "libresoc.v:42821.18-42821.105"
+ wire $not$libresoc.v:42821$1001_Y
+ attribute \src "libresoc.v:42824.18-42824.105"
+ wire $not$libresoc.v:42824$1004_Y
+ attribute \src "libresoc.v:42827.18-42827.105"
+ wire $not$libresoc.v:42827$1007_Y
+ attribute \src "libresoc.v:42830.18-42830.105"
+ wire $not$libresoc.v:42830$1010_Y
+ attribute \src "libresoc.v:42832.18-42832.105"
+ wire $not$libresoc.v:42832$1012_Y
+ attribute \src "libresoc.v:42834.17-42834.104"
+ wire $not$libresoc.v:42834$1014_Y
+ attribute \src "libresoc.v:42809.17-42809.103"
+ wire $or$libresoc.v:42809$989_Y
+ attribute \src "libresoc.v:42812.18-42812.115"
+ wire $or$libresoc.v:42812$992_Y
+ attribute \src "libresoc.v:42815.18-42815.106"
+ wire $or$libresoc.v:42815$995_Y
+ attribute \src "libresoc.v:42818.18-42818.115"
+ wire $or$libresoc.v:42818$998_Y
+ attribute \src "libresoc.v:42820.18-42820.106"
+ wire $or$libresoc.v:42820$1000_Y
+ attribute \src "libresoc.v:42823.18-42823.115"
+ wire $or$libresoc.v:42823$1003_Y
+ attribute \src "libresoc.v:42826.18-42826.106"
+ wire $or$libresoc.v:42826$1006_Y
+ attribute \src "libresoc.v:42833.17-42833.114"
+ wire $or$libresoc.v:42833$1013_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
wire \a_stall_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
wire input 2 \a_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151"
- wire input 14 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
wire width 45 \f_badaddr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
wire width 64 \ibus_rdata
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59"
wire width 64 \ibus_rdata$next
- attribute \src "libresoc.v:42505.7-42505.15"
+ attribute \src "libresoc.v:42696.7-42696.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151"
- wire input 6 \rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153"
+ wire input 14 \intclk_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153"
+ wire input 6 \intclk_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
- cell $and $and$libresoc.v:42620$951
+ cell $and $and$libresoc.v:42811$991
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$11
- connect \Y $and$libresoc.v:42620$951_Y
+ connect \Y $and$libresoc.v:42811$991_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
- cell $and $and$libresoc.v:42626$957
+ cell $and $and$libresoc.v:42817$997
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$21
- connect \Y $and$libresoc.v:42626$957_Y
+ connect \Y $and$libresoc.v:42817$997_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
- cell $and $and$libresoc.v:42631$962
+ cell $and $and$libresoc.v:42822$1002
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$31
- connect \Y $and$libresoc.v:42631$962_Y
+ connect \Y $and$libresoc.v:42822$1002_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
- cell $and $and$libresoc.v:42634$965
+ cell $and $and$libresoc.v:42825$1005
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$1
- connect \Y $and$libresoc.v:42634$965_Y
+ connect \Y $and$libresoc.v:42825$1005_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
- cell $and $and$libresoc.v:42637$968
+ cell $and $and$libresoc.v:42828$1008
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a_valid_i
connect \B \$41
- connect \Y $and$libresoc.v:42637$968_Y
+ connect \Y $and$libresoc.v:42828$1008_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
- cell $and $and$libresoc.v:42638$969
+ cell $and $and$libresoc.v:42829$1009
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__cyc
connect \B \ibus__err
- connect \Y $and$libresoc.v:42638$969_Y
+ connect \Y $and$libresoc.v:42829$1009_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
- cell $and $and$libresoc.v:42640$971
+ cell $and $and$libresoc.v:42831$1011
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__cyc
connect \B \ibus__err
- connect \Y $and$libresoc.v:42640$971_Y
+ connect \Y $and$libresoc.v:42831$1011_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
- cell $not $not$libresoc.v:42619$950
+ cell $not $not$libresoc.v:42810$990
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:42619$950_Y
+ connect \Y $not$libresoc.v:42810$990_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
- cell $not $not$libresoc.v:42622$953
+ cell $not $not$libresoc.v:42813$993
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_valid_i
- connect \Y $not$libresoc.v:42622$953_Y
+ connect \Y $not$libresoc.v:42813$993_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
- cell $not $not$libresoc.v:42623$954
+ cell $not $not$libresoc.v:42814$994
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:42623$954_Y
+ connect \Y $not$libresoc.v:42814$994_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
- cell $not $not$libresoc.v:42625$956
+ cell $not $not$libresoc.v:42816$996
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:42625$956_Y
+ connect \Y $not$libresoc.v:42816$996_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
- cell $not $not$libresoc.v:42628$959
+ cell $not $not$libresoc.v:42819$999
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_valid_i
- connect \Y $not$libresoc.v:42628$959_Y
+ connect \Y $not$libresoc.v:42819$999_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
- cell $not $not$libresoc.v:42630$961
+ cell $not $not$libresoc.v:42821$1001
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:42630$961_Y
+ connect \Y $not$libresoc.v:42821$1001_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
- cell $not $not$libresoc.v:42633$964
+ cell $not $not$libresoc.v:42824$1004
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_valid_i
- connect \Y $not$libresoc.v:42633$964_Y
+ connect \Y $not$libresoc.v:42824$1004_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
- cell $not $not$libresoc.v:42636$967
+ cell $not $not$libresoc.v:42827$1007
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a_stall_i
- connect \Y $not$libresoc.v:42636$967_Y
+ connect \Y $not$libresoc.v:42827$1007_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
- cell $not $not$libresoc.v:42639$970
+ cell $not $not$libresoc.v:42830$1010
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_stall_i
- connect \Y $not$libresoc.v:42639$970_Y
+ connect \Y $not$libresoc.v:42830$1010_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
- cell $not $not$libresoc.v:42641$972
+ cell $not $not$libresoc.v:42832$1012
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_stall_i
- connect \Y $not$libresoc.v:42641$972_Y
+ connect \Y $not$libresoc.v:42832$1012_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
- cell $not $not$libresoc.v:42643$974
+ cell $not $not$libresoc.v:42834$1014
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \f_valid_i
- connect \Y $not$libresoc.v:42643$974_Y
+ connect \Y $not$libresoc.v:42834$1014_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
- cell $or $or$libresoc.v:42618$949
+ cell $or $or$libresoc.v:42809$989
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$5
connect \B \$7
- connect \Y $or$libresoc.v:42618$949_Y
+ connect \Y $or$libresoc.v:42809$989_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
- cell $or $or$libresoc.v:42621$952
+ cell $or $or$libresoc.v:42812$992
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__ack
connect \B \ibus__err
- connect \Y $or$libresoc.v:42621$952_Y
+ connect \Y $or$libresoc.v:42812$992_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
- cell $or $or$libresoc.v:42624$955
+ cell $or $or$libresoc.v:42815$995
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$15
connect \B \$17
- connect \Y $or$libresoc.v:42624$955_Y
+ connect \Y $or$libresoc.v:42815$995_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
- cell $or $or$libresoc.v:42627$958
+ cell $or $or$libresoc.v:42818$998
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__ack
connect \B \ibus__err
- connect \Y $or$libresoc.v:42627$958_Y
+ connect \Y $or$libresoc.v:42818$998_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
- cell $or $or$libresoc.v:42629$960
+ cell $or $or$libresoc.v:42820$1000
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$25
connect \B \$27
- connect \Y $or$libresoc.v:42629$960_Y
+ connect \Y $or$libresoc.v:42820$1000_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
- cell $or $or$libresoc.v:42632$963
+ cell $or $or$libresoc.v:42823$1003
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__ack
connect \B \ibus__err
- connect \Y $or$libresoc.v:42632$963_Y
+ connect \Y $or$libresoc.v:42823$1003_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
- cell $or $or$libresoc.v:42635$966
+ cell $or $or$libresoc.v:42826$1006
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$35
connect \B \$37
- connect \Y $or$libresoc.v:42635$966_Y
+ connect \Y $or$libresoc.v:42826$1006_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
- cell $or $or$libresoc.v:42642$973
+ cell $or $or$libresoc.v:42833$1013
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ibus__ack
connect \B \ibus__err
- connect \Y $or$libresoc.v:42642$973_Y
+ connect \Y $or$libresoc.v:42833$1013_Y
end
- attribute \src "libresoc.v:42505.7-42505.20"
- process $proc$libresoc.v:42505$1016
+ attribute \src "libresoc.v:42696.7-42696.20"
+ process $proc$libresoc.v:42696$1056
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:42569.14-42569.44"
- process $proc$libresoc.v:42569$1017
+ attribute \src "libresoc.v:42758.14-42758.44"
+ process $proc$libresoc.v:42758$1057
assign { } { }
assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000
sync always
sync init
update \f_badaddr_o $1\f_badaddr_o[44:0]
end
- attribute \src "libresoc.v:42576.7-42576.27"
- process $proc$libresoc.v:42576$1018
+ attribute \src "libresoc.v:42765.7-42765.27"
+ process $proc$libresoc.v:42765$1058
assign { } { }
assign $1\f_fetch_err_o[0:0] 1'0
sync always
sync init
update \f_fetch_err_o $1\f_fetch_err_o[0:0]
end
- attribute \src "libresoc.v:42590.14-42590.42"
- process $proc$libresoc.v:42590$1019
+ attribute \src "libresoc.v:42779.14-42779.42"
+ process $proc$libresoc.v:42779$1059
assign { } { }
assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000
sync always
sync init
update \ibus__adr $1\ibus__adr[44:0]
end
- attribute \src "libresoc.v:42595.7-42595.23"
- process $proc$libresoc.v:42595$1020
+ attribute \src "libresoc.v:42784.7-42784.23"
+ process $proc$libresoc.v:42784$1060
assign { } { }
assign $1\ibus__cyc[0:0] 1'0
sync always
sync init
update \ibus__cyc $1\ibus__cyc[0:0]
end
- attribute \src "libresoc.v:42604.13-42604.30"
- process $proc$libresoc.v:42604$1021
+ attribute \src "libresoc.v:42793.13-42793.30"
+ process $proc$libresoc.v:42793$1061
assign { } { }
assign $1\ibus__sel[7:0] 8'00000000
sync always
sync init
update \ibus__sel $1\ibus__sel[7:0]
end
- attribute \src "libresoc.v:42609.7-42609.23"
- process $proc$libresoc.v:42609$1022
+ attribute \src "libresoc.v:42798.7-42798.23"
+ process $proc$libresoc.v:42798$1062
assign { } { }
assign $1\ibus__stb[0:0] 1'0
sync always
sync init
update \ibus__stb $1\ibus__stb[0:0]
end
- attribute \src "libresoc.v:42613.14-42613.47"
- process $proc$libresoc.v:42613$1023
+ attribute \src "libresoc.v:42802.14-42802.47"
+ process $proc$libresoc.v:42802$1063
assign { } { }
assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \ibus_rdata $1\ibus_rdata[63:0]
end
- attribute \src "libresoc.v:42644.3-42645.39"
- process $proc$libresoc.v:42644$975
+ attribute \src "libresoc.v:42835.3-42836.39"
+ process $proc$libresoc.v:42835$1015
assign { } { }
assign $0\f_badaddr_o[44:0] \f_badaddr_o$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \f_badaddr_o $0\f_badaddr_o[44:0]
end
- attribute \src "libresoc.v:42646.3-42647.43"
- process $proc$libresoc.v:42646$976
+ attribute \src "libresoc.v:42837.3-42838.43"
+ process $proc$libresoc.v:42837$1016
assign { } { }
assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \f_fetch_err_o $0\f_fetch_err_o[0:0]
end
- attribute \src "libresoc.v:42648.3-42649.35"
- process $proc$libresoc.v:42648$977
+ attribute \src "libresoc.v:42839.3-42840.35"
+ process $proc$libresoc.v:42839$1017
assign { } { }
assign $0\ibus__adr[44:0] \ibus__adr$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \ibus__adr $0\ibus__adr[44:0]
end
- attribute \src "libresoc.v:42650.3-42651.37"
- process $proc$libresoc.v:42650$978
+ attribute \src "libresoc.v:42841.3-42842.37"
+ process $proc$libresoc.v:42841$1018
assign { } { }
assign $0\ibus_rdata[63:0] \ibus_rdata$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \ibus_rdata $0\ibus_rdata[63:0]
end
- attribute \src "libresoc.v:42652.3-42653.35"
- process $proc$libresoc.v:42652$979
+ attribute \src "libresoc.v:42843.3-42844.35"
+ process $proc$libresoc.v:42843$1019
assign { } { }
assign $0\ibus__sel[7:0] \ibus__sel$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \ibus__sel $0\ibus__sel[7:0]
end
- attribute \src "libresoc.v:42654.3-42655.35"
- process $proc$libresoc.v:42654$980
+ attribute \src "libresoc.v:42845.3-42846.35"
+ process $proc$libresoc.v:42845$1020
assign { } { }
assign $0\ibus__stb[0:0] \ibus__stb$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \ibus__stb $0\ibus__stb[0:0]
end
- attribute \src "libresoc.v:42656.3-42657.35"
- process $proc$libresoc.v:42656$981
+ attribute \src "libresoc.v:42847.3-42848.35"
+ process $proc$libresoc.v:42847$1021
assign { } { }
assign $0\ibus__cyc[0:0] \ibus__cyc$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \ibus__cyc $0\ibus__cyc[0:0]
end
- attribute \src "libresoc.v:42658.3-42680.6"
- process $proc$libresoc.v:42658$982
+ attribute \src "libresoc.v:42849.3-42871.6"
+ process $proc$libresoc.v:42849$1022
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus__cyc$next[0:0]$983 $3\ibus__cyc$next[0:0]$986
- attribute \src "libresoc.v:42659.5-42659.29"
+ assign $0\ibus__cyc$next[0:0]$1023 $3\ibus__cyc$next[0:0]$1026
+ attribute \src "libresoc.v:42850.5-42850.29"
switch \initial
- attribute \src "libresoc.v:42659.9-42659.17"
+ attribute \src "libresoc.v:42850.9-42850.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\ibus__cyc$next[0:0]$984 $2\ibus__cyc$next[0:0]$985
+ assign $1\ibus__cyc$next[0:0]$1024 $2\ibus__cyc$next[0:0]$1025
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\ibus__cyc$next[0:0]$985 1'0
+ assign $2\ibus__cyc$next[0:0]$1025 1'0
case
- assign $2\ibus__cyc$next[0:0]$985 \ibus__cyc
+ assign $2\ibus__cyc$next[0:0]$1025 \ibus__cyc
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\ibus__cyc$next[0:0]$984 1'1
+ assign $1\ibus__cyc$next[0:0]$1024 1'1
case
- assign $1\ibus__cyc$next[0:0]$984 \ibus__cyc
+ assign $1\ibus__cyc$next[0:0]$1024 \ibus__cyc
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus__cyc$next[0:0]$986 1'0
+ assign $3\ibus__cyc$next[0:0]$1026 1'0
case
- assign $3\ibus__cyc$next[0:0]$986 $1\ibus__cyc$next[0:0]$984
+ assign $3\ibus__cyc$next[0:0]$1026 $1\ibus__cyc$next[0:0]$1024
end
sync always
- update \ibus__cyc$next $0\ibus__cyc$next[0:0]$983
+ update \ibus__cyc$next $0\ibus__cyc$next[0:0]$1023
end
- attribute \src "libresoc.v:42681.3-42703.6"
- process $proc$libresoc.v:42681$987
+ attribute \src "libresoc.v:42872.3-42894.6"
+ process $proc$libresoc.v:42872$1027
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus__stb$next[0:0]$988 $3\ibus__stb$next[0:0]$991
- attribute \src "libresoc.v:42682.5-42682.29"
+ assign $0\ibus__stb$next[0:0]$1028 $3\ibus__stb$next[0:0]$1031
+ attribute \src "libresoc.v:42873.5-42873.29"
switch \initial
- attribute \src "libresoc.v:42682.9-42682.17"
+ attribute \src "libresoc.v:42873.9-42873.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\ibus__stb$next[0:0]$989 $2\ibus__stb$next[0:0]$990
+ assign $1\ibus__stb$next[0:0]$1029 $2\ibus__stb$next[0:0]$1030
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
switch \$19
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\ibus__stb$next[0:0]$990 1'0
+ assign $2\ibus__stb$next[0:0]$1030 1'0
case
- assign $2\ibus__stb$next[0:0]$990 \ibus__stb
+ assign $2\ibus__stb$next[0:0]$1030 \ibus__stb
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\ibus__stb$next[0:0]$989 1'1
+ assign $1\ibus__stb$next[0:0]$1029 1'1
case
- assign $1\ibus__stb$next[0:0]$989 \ibus__stb
+ assign $1\ibus__stb$next[0:0]$1029 \ibus__stb
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus__stb$next[0:0]$991 1'0
+ assign $3\ibus__stb$next[0:0]$1031 1'0
case
- assign $3\ibus__stb$next[0:0]$991 $1\ibus__stb$next[0:0]$989
+ assign $3\ibus__stb$next[0:0]$1031 $1\ibus__stb$next[0:0]$1029
end
sync always
- update \ibus__stb$next $0\ibus__stb$next[0:0]$988
+ update \ibus__stb$next $0\ibus__stb$next[0:0]$1028
end
- attribute \src "libresoc.v:42704.3-42726.6"
- process $proc$libresoc.v:42704$992
+ attribute \src "libresoc.v:42895.3-42917.6"
+ process $proc$libresoc.v:42895$1032
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus__sel$next[7:0]$993 $3\ibus__sel$next[7:0]$996
- attribute \src "libresoc.v:42705.5-42705.29"
+ assign $0\ibus__sel$next[7:0]$1033 $3\ibus__sel$next[7:0]$1036
+ attribute \src "libresoc.v:42896.5-42896.29"
switch \initial
- attribute \src "libresoc.v:42705.9-42705.17"
+ attribute \src "libresoc.v:42896.9-42896.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\ibus__sel$next[7:0]$994 $2\ibus__sel$next[7:0]$995
+ assign $1\ibus__sel$next[7:0]$1034 $2\ibus__sel$next[7:0]$1035
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
switch \$29
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\ibus__sel$next[7:0]$995 8'00000000
+ assign $2\ibus__sel$next[7:0]$1035 8'00000000
case
- assign $2\ibus__sel$next[7:0]$995 \ibus__sel
+ assign $2\ibus__sel$next[7:0]$1035 \ibus__sel
end
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\ibus__sel$next[7:0]$994 8'11111111
+ assign $1\ibus__sel$next[7:0]$1034 8'11111111
case
- assign $1\ibus__sel$next[7:0]$994 \ibus__sel
+ assign $1\ibus__sel$next[7:0]$1034 \ibus__sel
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus__sel$next[7:0]$996 8'00000000
+ assign $3\ibus__sel$next[7:0]$1036 8'00000000
case
- assign $3\ibus__sel$next[7:0]$996 $1\ibus__sel$next[7:0]$994
+ assign $3\ibus__sel$next[7:0]$1036 $1\ibus__sel$next[7:0]$1034
end
sync always
- update \ibus__sel$next $0\ibus__sel$next[7:0]$993
+ update \ibus__sel$next $0\ibus__sel$next[7:0]$1033
end
- attribute \src "libresoc.v:42727.3-42746.6"
- process $proc$libresoc.v:42727$997
+ attribute \src "libresoc.v:42918.3-42937.6"
+ process $proc$libresoc.v:42918$1037
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus_rdata$next[63:0]$998 $3\ibus_rdata$next[63:0]$1001
- attribute \src "libresoc.v:42728.5-42728.29"
+ assign $0\ibus_rdata$next[63:0]$1038 $3\ibus_rdata$next[63:0]$1041
+ attribute \src "libresoc.v:42919.5-42919.29"
switch \initial
- attribute \src "libresoc.v:42728.9-42728.17"
+ attribute \src "libresoc.v:42919.9-42919.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\ibus_rdata$next[63:0]$999 $2\ibus_rdata$next[63:0]$1000
+ assign $1\ibus_rdata$next[63:0]$1039 $2\ibus_rdata$next[63:0]$1040
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
switch \$39
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\ibus_rdata$next[63:0]$1000 \ibus__dat_r
+ assign $2\ibus_rdata$next[63:0]$1040 \ibus__dat_r
case
- assign $2\ibus_rdata$next[63:0]$1000 \ibus_rdata
+ assign $2\ibus_rdata$next[63:0]$1040 \ibus_rdata
end
case
- assign $1\ibus_rdata$next[63:0]$999 \ibus_rdata
+ assign $1\ibus_rdata$next[63:0]$1039 \ibus_rdata
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ibus_rdata$next[63:0]$1001 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\ibus_rdata$next[63:0]$1041 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\ibus_rdata$next[63:0]$1001 $1\ibus_rdata$next[63:0]$999
+ assign $3\ibus_rdata$next[63:0]$1041 $1\ibus_rdata$next[63:0]$1039
end
sync always
- update \ibus_rdata$next $0\ibus_rdata$next[63:0]$998
+ update \ibus_rdata$next $0\ibus_rdata$next[63:0]$1038
end
- attribute \src "libresoc.v:42747.3-42764.6"
- process $proc$libresoc.v:42747$1002
+ attribute \src "libresoc.v:42938.3-42955.6"
+ process $proc$libresoc.v:42938$1042
assign { } { }
assign { } { }
assign { } { }
- assign $0\ibus__adr$next[44:0]$1003 $2\ibus__adr$next[44:0]$1005
- attribute \src "libresoc.v:42748.5-42748.29"
+ assign $0\ibus__adr$next[44:0]$1043 $2\ibus__adr$next[44:0]$1045
+ attribute \src "libresoc.v:42939.5-42939.29"
switch \initial
- attribute \src "libresoc.v:42748.9-42748.17"
+ attribute \src "libresoc.v:42939.9-42939.17"
case 1'1
case
end
switch { \$43 \ibus__cyc }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
- assign $1\ibus__adr$next[44:0]$1004 \ibus__adr
+ assign $1\ibus__adr$next[44:0]$1044 \ibus__adr
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\ibus__adr$next[44:0]$1004 \a_pc_i [47:3]
+ assign $1\ibus__adr$next[44:0]$1044 \a_pc_i [47:3]
case
- assign $1\ibus__adr$next[44:0]$1004 \ibus__adr
+ assign $1\ibus__adr$next[44:0]$1044 \ibus__adr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\ibus__adr$next[44:0]$1005 45'000000000000000000000000000000000000000000000
+ assign $2\ibus__adr$next[44:0]$1045 45'000000000000000000000000000000000000000000000
case
- assign $2\ibus__adr$next[44:0]$1005 $1\ibus__adr$next[44:0]$1004
+ assign $2\ibus__adr$next[44:0]$1045 $1\ibus__adr$next[44:0]$1044
end
sync always
- update \ibus__adr$next $0\ibus__adr$next[44:0]$1003
+ update \ibus__adr$next $0\ibus__adr$next[44:0]$1043
end
- attribute \src "libresoc.v:42765.3-42782.6"
- process $proc$libresoc.v:42765$1006
+ attribute \src "libresoc.v:42956.3-42973.6"
+ process $proc$libresoc.v:42956$1046
assign { } { }
assign { } { }
assign { } { }
- assign $0\f_fetch_err_o$next[0:0]$1007 $2\f_fetch_err_o$next[0:0]$1009
- attribute \src "libresoc.v:42766.5-42766.29"
+ assign $0\f_fetch_err_o$next[0:0]$1047 $2\f_fetch_err_o$next[0:0]$1049
+ attribute \src "libresoc.v:42957.5-42957.29"
switch \initial
- attribute \src "libresoc.v:42766.9-42766.17"
+ attribute \src "libresoc.v:42957.9-42957.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\f_fetch_err_o$next[0:0]$1008 1'1
+ assign $1\f_fetch_err_o$next[0:0]$1048 1'1
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $1\f_fetch_err_o$next[0:0]$1008 1'0
+ assign $1\f_fetch_err_o$next[0:0]$1048 1'0
case
- assign $1\f_fetch_err_o$next[0:0]$1008 \f_fetch_err_o
+ assign $1\f_fetch_err_o$next[0:0]$1048 \f_fetch_err_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\f_fetch_err_o$next[0:0]$1009 1'0
+ assign $2\f_fetch_err_o$next[0:0]$1049 1'0
case
- assign $2\f_fetch_err_o$next[0:0]$1009 $1\f_fetch_err_o$next[0:0]$1008
+ assign $2\f_fetch_err_o$next[0:0]$1049 $1\f_fetch_err_o$next[0:0]$1048
end
sync always
- update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$1007
+ update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$1047
end
- attribute \src "libresoc.v:42783.3-42797.6"
- process $proc$libresoc.v:42783$1010
+ attribute \src "libresoc.v:42974.3-42988.6"
+ process $proc$libresoc.v:42974$1050
assign { } { }
assign { } { }
assign { } { }
- assign $0\f_badaddr_o$next[44:0]$1011 $2\f_badaddr_o$next[44:0]$1013
- attribute \src "libresoc.v:42784.5-42784.29"
+ assign $0\f_badaddr_o$next[44:0]$1051 $2\f_badaddr_o$next[44:0]$1053
+ attribute \src "libresoc.v:42975.5-42975.29"
switch \initial
- attribute \src "libresoc.v:42784.9-42784.17"
+ attribute \src "libresoc.v:42975.9-42975.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\f_badaddr_o$next[44:0]$1012 \ibus__adr
+ assign $1\f_badaddr_o$next[44:0]$1052 \ibus__adr
case
- assign $1\f_badaddr_o$next[44:0]$1012 \f_badaddr_o
+ assign $1\f_badaddr_o$next[44:0]$1052 \f_badaddr_o
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\f_badaddr_o$next[44:0]$1013 45'000000000000000000000000000000000000000000000
+ assign $2\f_badaddr_o$next[44:0]$1053 45'000000000000000000000000000000000000000000000
case
- assign $2\f_badaddr_o$next[44:0]$1013 $1\f_badaddr_o$next[44:0]$1012
+ assign $2\f_badaddr_o$next[44:0]$1053 $1\f_badaddr_o$next[44:0]$1052
end
sync always
- update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$1011
+ update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$1051
end
- attribute \src "libresoc.v:42798.3-42809.6"
- process $proc$libresoc.v:42798$1014
+ attribute \src "libresoc.v:42989.3-43000.6"
+ process $proc$libresoc.v:42989$1054
assign { } { }
assign $0\f_busy_o[0:0] $1\f_busy_o[0:0]
- attribute \src "libresoc.v:42799.5-42799.29"
+ attribute \src "libresoc.v:42990.5-42990.29"
switch \initial
- attribute \src "libresoc.v:42799.9-42799.17"
+ attribute \src "libresoc.v:42990.9-42990.17"
case 1'1
case
end
sync always
update \f_busy_o $0\f_busy_o[0:0]
end
- attribute \src "libresoc.v:42810.3-42822.6"
- process $proc$libresoc.v:42810$1015
+ attribute \src "libresoc.v:43001.3-43013.6"
+ process $proc$libresoc.v:43001$1055
assign { } { }
assign { } { }
assign $0\f_instr_o[63:0] $1\f_instr_o[63:0]
- attribute \src "libresoc.v:42811.5-42811.29"
+ attribute \src "libresoc.v:43002.5-43002.29"
switch \initial
- attribute \src "libresoc.v:42811.9-42811.17"
+ attribute \src "libresoc.v:43002.9-43002.17"
case 1'1
case
end
sync always
update \f_instr_o $0\f_instr_o[63:0]
end
- connect \$9 $or$libresoc.v:42618$949_Y
- connect \$11 $not$libresoc.v:42619$950_Y
- connect \$13 $and$libresoc.v:42620$951_Y
- connect \$15 $or$libresoc.v:42621$952_Y
- connect \$17 $not$libresoc.v:42622$953_Y
- connect \$1 $not$libresoc.v:42623$954_Y
- connect \$19 $or$libresoc.v:42624$955_Y
- connect \$21 $not$libresoc.v:42625$956_Y
- connect \$23 $and$libresoc.v:42626$957_Y
- connect \$25 $or$libresoc.v:42627$958_Y
- connect \$27 $not$libresoc.v:42628$959_Y
- connect \$29 $or$libresoc.v:42629$960_Y
- connect \$31 $not$libresoc.v:42630$961_Y
- connect \$33 $and$libresoc.v:42631$962_Y
- connect \$35 $or$libresoc.v:42632$963_Y
- connect \$37 $not$libresoc.v:42633$964_Y
- connect \$3 $and$libresoc.v:42634$965_Y
- connect \$39 $or$libresoc.v:42635$966_Y
- connect \$41 $not$libresoc.v:42636$967_Y
- connect \$43 $and$libresoc.v:42637$968_Y
- connect \$45 $and$libresoc.v:42638$969_Y
- connect \$47 $not$libresoc.v:42639$970_Y
- connect \$49 $and$libresoc.v:42640$971_Y
- connect \$51 $not$libresoc.v:42641$972_Y
- connect \$5 $or$libresoc.v:42642$973_Y
- connect \$7 $not$libresoc.v:42643$974_Y
+ connect \$9 $or$libresoc.v:42809$989_Y
+ connect \$11 $not$libresoc.v:42810$990_Y
+ connect \$13 $and$libresoc.v:42811$991_Y
+ connect \$15 $or$libresoc.v:42812$992_Y
+ connect \$17 $not$libresoc.v:42813$993_Y
+ connect \$1 $not$libresoc.v:42814$994_Y
+ connect \$19 $or$libresoc.v:42815$995_Y
+ connect \$21 $not$libresoc.v:42816$996_Y
+ connect \$23 $and$libresoc.v:42817$997_Y
+ connect \$25 $or$libresoc.v:42818$998_Y
+ connect \$27 $not$libresoc.v:42819$999_Y
+ connect \$29 $or$libresoc.v:42820$1000_Y
+ connect \$31 $not$libresoc.v:42821$1001_Y
+ connect \$33 $and$libresoc.v:42822$1002_Y
+ connect \$35 $or$libresoc.v:42823$1003_Y
+ connect \$37 $not$libresoc.v:42824$1004_Y
+ connect \$3 $and$libresoc.v:42825$1005_Y
+ connect \$39 $or$libresoc.v:42826$1006_Y
+ connect \$41 $not$libresoc.v:42827$1007_Y
+ connect \$43 $and$libresoc.v:42828$1008_Y
+ connect \$45 $and$libresoc.v:42829$1009_Y
+ connect \$47 $not$libresoc.v:42830$1010_Y
+ connect \$49 $and$libresoc.v:42831$1011_Y
+ connect \$51 $not$libresoc.v:42832$1012_Y
+ connect \$5 $or$libresoc.v:42833$1013_Y
+ connect \$7 $not$libresoc.v:42834$1014_Y
connect \a_stall_i 1'0
connect \f_stall_i 1'0
connect \a_busy_o \ibus__cyc
end
-attribute \src "libresoc.v:42830.1-44581.10"
+attribute \src "libresoc.v:43021.1-44772.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.jtag"
+attribute \nmigen.hierarchy "test_issuer.ti.jtag"
attribute \generator "nMigen"
module \jtag
- attribute \src "libresoc.v:43857.3-43880.6"
+ attribute \src "libresoc.v:44048.3-44071.6"
wire $0\TAP_bus__tdo[0:0]
- attribute \src "libresoc.v:44218.3-44233.6"
+ attribute \src "libresoc.v:44409.3-44424.6"
wire $0\TAP_tdo[0:0]
- attribute \src "libresoc.v:44015.3-44047.6"
- wire width 4 $0\dmi0_addr_i$next[3:0]$1235
- attribute \src "libresoc.v:43721.3-43722.39"
+ attribute \src "libresoc.v:44206.3-44238.6"
+ wire width 4 $0\dmi0_addr_i$next[3:0]$1275
+ attribute \src "libresoc.v:43912.3-43913.39"
wire width 4 $0\dmi0_addr_i[3:0]
- attribute \src "libresoc.v:44441.3-44457.6"
- wire $0\dmi0_addrsr__oe$next[0:0]$1318
- attribute \src "libresoc.v:43741.3-43742.47"
+ attribute \src "libresoc.v:44632.3-44648.6"
+ wire $0\dmi0_addrsr__oe$next[0:0]$1358
+ attribute \src "libresoc.v:43932.3-43933.47"
wire $0\dmi0_addrsr__oe[0:0]
- attribute \src "libresoc.v:44458.3-44478.6"
- wire width 8 $0\dmi0_addrsr_reg$next[7:0]$1322
- attribute \src "libresoc.v:43739.3-43740.47"
+ attribute \src "libresoc.v:44649.3-44669.6"
+ wire width 8 $0\dmi0_addrsr_reg$next[7:0]$1362
+ attribute \src "libresoc.v:43930.3-43931.47"
wire width 8 $0\dmi0_addrsr_reg[7:0]
- attribute \src "libresoc.v:44423.3-44431.6"
- wire $0\dmi0_addrsr_update_core$next[0:0]$1312
- attribute \src "libresoc.v:43745.3-43746.63"
+ attribute \src "libresoc.v:44614.3-44622.6"
+ wire $0\dmi0_addrsr_update_core$next[0:0]$1352
+ attribute \src "libresoc.v:43936.3-43937.63"
wire $0\dmi0_addrsr_update_core[0:0]
- attribute \src "libresoc.v:44432.3-44440.6"
- wire $0\dmi0_addrsr_update_core_prev$next[0:0]$1315
- attribute \src "libresoc.v:43743.3-43744.73"
+ attribute \src "libresoc.v:44623.3-44631.6"
+ wire $0\dmi0_addrsr_update_core_prev$next[0:0]$1355
+ attribute \src "libresoc.v:43934.3-43935.73"
wire $0\dmi0_addrsr_update_core_prev[0:0]
- attribute \src "libresoc.v:44128.3-44148.6"
- wire width 64 $0\dmi0_datasr__i$next[63:0]$1253
- attribute \src "libresoc.v:43715.3-43716.45"
+ attribute \src "libresoc.v:44319.3-44339.6"
+ wire width 64 $0\dmi0_datasr__i$next[63:0]$1293
+ attribute \src "libresoc.v:43906.3-43907.45"
wire width 64 $0\dmi0_datasr__i[63:0]
- attribute \src "libresoc.v:43819.3-43835.6"
- wire width 2 $0\dmi0_datasr__oe$next[1:0]$1202
- attribute \src "libresoc.v:43733.3-43734.47"
+ attribute \src "libresoc.v:44010.3-44026.6"
+ wire width 2 $0\dmi0_datasr__oe$next[1:0]$1242
+ attribute \src "libresoc.v:43924.3-43925.47"
wire width 2 $0\dmi0_datasr__oe[1:0]
- attribute \src "libresoc.v:43836.3-43856.6"
- wire width 64 $0\dmi0_datasr_reg$next[63:0]$1206
- attribute \src "libresoc.v:43731.3-43732.47"
+ attribute \src "libresoc.v:44027.3-44047.6"
+ wire width 64 $0\dmi0_datasr_reg$next[63:0]$1246
+ attribute \src "libresoc.v:43922.3-43923.47"
wire width 64 $0\dmi0_datasr_reg[63:0]
- attribute \src "libresoc.v:44479.3-44487.6"
- wire $0\dmi0_datasr_update_core$next[0:0]$1327
- attribute \src "libresoc.v:43737.3-43738.63"
+ attribute \src "libresoc.v:44670.3-44678.6"
+ wire $0\dmi0_datasr_update_core$next[0:0]$1367
+ attribute \src "libresoc.v:43928.3-43929.63"
wire $0\dmi0_datasr_update_core[0:0]
- attribute \src "libresoc.v:43810.3-43818.6"
- wire $0\dmi0_datasr_update_core_prev$next[0:0]$1199
- attribute \src "libresoc.v:43735.3-43736.73"
+ attribute \src "libresoc.v:44001.3-44009.6"
+ wire $0\dmi0_datasr_update_core_prev$next[0:0]$1239
+ attribute \src "libresoc.v:43926.3-43927.73"
wire $0\dmi0_datasr_update_core_prev[0:0]
- attribute \src "libresoc.v:44101.3-44127.6"
- wire width 64 $0\dmi0_din$next[63:0]$1248
- attribute \src "libresoc.v:43717.3-43718.33"
+ attribute \src "libresoc.v:44292.3-44318.6"
+ wire width 64 $0\dmi0_din$next[63:0]$1288
+ attribute \src "libresoc.v:43908.3-43909.33"
wire width 64 $0\dmi0_din[63:0]
- attribute \src "libresoc.v:44048.3-44100.6"
- wire width 3 $0\fsm_state$275$next[2:0]$1241
- attribute \src "libresoc.v:43719.3-43720.45"
- wire width 3 $0\fsm_state$275[2:0]$1170
- attribute \src "libresoc.v:43232.13-43232.35"
- wire width 3 $0\fsm_state$275[2:0]$1343
- attribute \src "libresoc.v:43914.3-43966.6"
- wire width 3 $0\fsm_state$next[2:0]$1218
- attribute \src "libresoc.v:43727.3-43728.35"
+ attribute \src "libresoc.v:44239.3-44291.6"
+ wire width 3 $0\fsm_state$275$next[2:0]$1281
+ attribute \src "libresoc.v:43910.3-43911.45"
+ wire width 3 $0\fsm_state$275[2:0]$1210
+ attribute \src "libresoc.v:43421.13-43421.35"
+ wire width 3 $0\fsm_state$275[2:0]$1383
+ attribute \src "libresoc.v:44105.3-44157.6"
+ wire width 3 $0\fsm_state$next[2:0]$1258
+ attribute \src "libresoc.v:43918.3-43919.35"
wire width 3 $0\fsm_state[2:0]
- attribute \src "libresoc.v:42831.7-42831.20"
+ attribute \src "libresoc.v:43022.7-43022.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:44234.3-44254.6"
- wire width 50 $0\io_bd$next[49:0]$1263
- attribute \src "libresoc.v:43771.3-43772.27"
+ attribute \src "libresoc.v:44425.3-44445.6"
+ wire width 50 $0\io_bd$next[49:0]$1303
+ attribute \src "libresoc.v:43962.3-43963.27"
wire width 50 $0\io_bd[49:0]
- attribute \src "libresoc.v:44149.3-44217.6"
- wire width 50 $0\io_sr$next[49:0]$1258
- attribute \src "libresoc.v:43773.3-43774.27"
+ attribute \src "libresoc.v:44340.3-44408.6"
+ wire width 50 $0\io_sr$next[49:0]$1298
+ attribute \src "libresoc.v:43964.3-43965.27"
wire width 50 $0\io_sr[49:0]
- attribute \src "libresoc.v:43881.3-43913.6"
- wire width 29 $0\jtag_wb__adr$next[28:0]$1212
- attribute \src "libresoc.v:43729.3-43730.41"
+ attribute \src "libresoc.v:44072.3-44104.6"
+ wire width 29 $0\jtag_wb__adr$next[28:0]$1252
+ attribute \src "libresoc.v:43920.3-43921.41"
wire width 29 $0\jtag_wb__adr[28:0]
- attribute \src "libresoc.v:43967.3-43993.6"
- wire width 64 $0\jtag_wb__dat_w$next[63:0]$1225
- attribute \src "libresoc.v:43725.3-43726.45"
+ attribute \src "libresoc.v:44158.3-44184.6"
+ wire width 64 $0\jtag_wb__dat_w$next[63:0]$1265
+ attribute \src "libresoc.v:43916.3-43917.45"
wire width 64 $0\jtag_wb__dat_w[63:0]
- attribute \src "libresoc.v:44329.3-44345.6"
- wire $0\jtag_wb_addrsr__oe$next[0:0]$1288
- attribute \src "libresoc.v:43757.3-43758.53"
+ attribute \src "libresoc.v:44520.3-44536.6"
+ wire $0\jtag_wb_addrsr__oe$next[0:0]$1328
+ attribute \src "libresoc.v:43948.3-43949.53"
wire $0\jtag_wb_addrsr__oe[0:0]
- attribute \src "libresoc.v:44346.3-44366.6"
- wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$1292
- attribute \src "libresoc.v:43755.3-43756.53"
+ attribute \src "libresoc.v:44537.3-44557.6"
+ wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$1332
+ attribute \src "libresoc.v:43946.3-43947.53"
wire width 29 $0\jtag_wb_addrsr_reg[28:0]
- attribute \src "libresoc.v:44311.3-44319.6"
- wire $0\jtag_wb_addrsr_update_core$next[0:0]$1282
- attribute \src "libresoc.v:43761.3-43762.69"
+ attribute \src "libresoc.v:44502.3-44510.6"
+ wire $0\jtag_wb_addrsr_update_core$next[0:0]$1322
+ attribute \src "libresoc.v:43952.3-43953.69"
wire $0\jtag_wb_addrsr_update_core[0:0]
- attribute \src "libresoc.v:44320.3-44328.6"
- wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1285
- attribute \src "libresoc.v:43759.3-43760.79"
+ attribute \src "libresoc.v:44511.3-44519.6"
+ wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1325
+ attribute \src "libresoc.v:43950.3-43951.79"
wire $0\jtag_wb_addrsr_update_core_prev[0:0]
- attribute \src "libresoc.v:43994.3-44014.6"
- wire width 64 $0\jtag_wb_datasr__i$next[63:0]$1230
- attribute \src "libresoc.v:43723.3-43724.51"
+ attribute \src "libresoc.v:44185.3-44205.6"
+ wire width 64 $0\jtag_wb_datasr__i$next[63:0]$1270
+ attribute \src "libresoc.v:43914.3-43915.51"
wire width 64 $0\jtag_wb_datasr__i[63:0]
- attribute \src "libresoc.v:44385.3-44401.6"
- wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$1303
- attribute \src "libresoc.v:43749.3-43750.53"
+ attribute \src "libresoc.v:44576.3-44592.6"
+ wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$1343
+ attribute \src "libresoc.v:43940.3-43941.53"
wire width 2 $0\jtag_wb_datasr__oe[1:0]
- attribute \src "libresoc.v:44402.3-44422.6"
- wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$1307
- attribute \src "libresoc.v:43747.3-43748.53"
+ attribute \src "libresoc.v:44593.3-44613.6"
+ wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$1347
+ attribute \src "libresoc.v:43938.3-43939.53"
wire width 64 $0\jtag_wb_datasr_reg[63:0]
- attribute \src "libresoc.v:44367.3-44375.6"
- wire $0\jtag_wb_datasr_update_core$next[0:0]$1297
- attribute \src "libresoc.v:43753.3-43754.69"
+ attribute \src "libresoc.v:44558.3-44566.6"
+ wire $0\jtag_wb_datasr_update_core$next[0:0]$1337
+ attribute \src "libresoc.v:43944.3-43945.69"
wire $0\jtag_wb_datasr_update_core[0:0]
- attribute \src "libresoc.v:44376.3-44384.6"
- wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$1300
- attribute \src "libresoc.v:43751.3-43752.79"
+ attribute \src "libresoc.v:44567.3-44575.6"
+ wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$1340
+ attribute \src "libresoc.v:43942.3-43943.79"
wire $0\jtag_wb_datasr_update_core_prev[0:0]
- attribute \src "libresoc.v:44273.3-44289.6"
- wire $0\sr0__oe$next[0:0]$1273
- attribute \src "libresoc.v:43765.3-43766.31"
+ attribute \src "libresoc.v:44464.3-44480.6"
+ wire $0\sr0__oe$next[0:0]$1313
+ attribute \src "libresoc.v:43956.3-43957.31"
wire $0\sr0__oe[0:0]
- attribute \src "libresoc.v:44290.3-44310.6"
- wire width 3 $0\sr0_reg$next[2:0]$1277
- attribute \src "libresoc.v:43763.3-43764.31"
+ attribute \src "libresoc.v:44481.3-44501.6"
+ wire width 3 $0\sr0_reg$next[2:0]$1317
+ attribute \src "libresoc.v:43954.3-43955.31"
wire width 3 $0\sr0_reg[2:0]
- attribute \src "libresoc.v:44255.3-44263.6"
- wire $0\sr0_update_core$next[0:0]$1267
- attribute \src "libresoc.v:43769.3-43770.47"
+ attribute \src "libresoc.v:44446.3-44454.6"
+ wire $0\sr0_update_core$next[0:0]$1307
+ attribute \src "libresoc.v:43960.3-43961.47"
wire $0\sr0_update_core[0:0]
- attribute \src "libresoc.v:44264.3-44272.6"
- wire $0\sr0_update_core_prev$next[0:0]$1270
- attribute \src "libresoc.v:43767.3-43768.57"
+ attribute \src "libresoc.v:44455.3-44463.6"
+ wire $0\sr0_update_core_prev$next[0:0]$1310
+ attribute \src "libresoc.v:43958.3-43959.57"
wire $0\sr0_update_core_prev[0:0]
- attribute \src "libresoc.v:43857.3-43880.6"
+ attribute \src "libresoc.v:44048.3-44071.6"
wire $1\TAP_bus__tdo[0:0]
- attribute \src "libresoc.v:44218.3-44233.6"
+ attribute \src "libresoc.v:44409.3-44424.6"
wire $1\TAP_tdo[0:0]
- attribute \src "libresoc.v:44015.3-44047.6"
- wire width 4 $1\dmi0_addr_i$next[3:0]$1236
- attribute \src "libresoc.v:43157.13-43157.31"
+ attribute \src "libresoc.v:44206.3-44238.6"
+ wire width 4 $1\dmi0_addr_i$next[3:0]$1276
+ attribute \src "libresoc.v:43346.13-43346.31"
wire width 4 $1\dmi0_addr_i[3:0]
- attribute \src "libresoc.v:44441.3-44457.6"
- wire $1\dmi0_addrsr__oe$next[0:0]$1319
- attribute \src "libresoc.v:43165.7-43165.29"
+ attribute \src "libresoc.v:44632.3-44648.6"
+ wire $1\dmi0_addrsr__oe$next[0:0]$1359
+ attribute \src "libresoc.v:43354.7-43354.29"
wire $1\dmi0_addrsr__oe[0:0]
- attribute \src "libresoc.v:44458.3-44478.6"
- wire width 8 $1\dmi0_addrsr_reg$next[7:0]$1323
- attribute \src "libresoc.v:43173.13-43173.36"
+ attribute \src "libresoc.v:44649.3-44669.6"
+ wire width 8 $1\dmi0_addrsr_reg$next[7:0]$1363
+ attribute \src "libresoc.v:43362.13-43362.36"
wire width 8 $1\dmi0_addrsr_reg[7:0]
- attribute \src "libresoc.v:44423.3-44431.6"
- wire $1\dmi0_addrsr_update_core$next[0:0]$1313
- attribute \src "libresoc.v:43181.7-43181.37"
+ attribute \src "libresoc.v:44614.3-44622.6"
+ wire $1\dmi0_addrsr_update_core$next[0:0]$1353
+ attribute \src "libresoc.v:43370.7-43370.37"
wire $1\dmi0_addrsr_update_core[0:0]
- attribute \src "libresoc.v:44432.3-44440.6"
- wire $1\dmi0_addrsr_update_core_prev$next[0:0]$1316
- attribute \src "libresoc.v:43185.7-43185.42"
+ attribute \src "libresoc.v:44623.3-44631.6"
+ wire $1\dmi0_addrsr_update_core_prev$next[0:0]$1356
+ attribute \src "libresoc.v:43374.7-43374.42"
wire $1\dmi0_addrsr_update_core_prev[0:0]
- attribute \src "libresoc.v:44128.3-44148.6"
- wire width 64 $1\dmi0_datasr__i$next[63:0]$1254
- attribute \src "libresoc.v:43189.14-43189.51"
+ attribute \src "libresoc.v:44319.3-44339.6"
+ wire width 64 $1\dmi0_datasr__i$next[63:0]$1294
+ attribute \src "libresoc.v:43378.14-43378.51"
wire width 64 $1\dmi0_datasr__i[63:0]
- attribute \src "libresoc.v:43819.3-43835.6"
- wire width 2 $1\dmi0_datasr__oe$next[1:0]$1203
- attribute \src "libresoc.v:43195.13-43195.35"
+ attribute \src "libresoc.v:44010.3-44026.6"
+ wire width 2 $1\dmi0_datasr__oe$next[1:0]$1243
+ attribute \src "libresoc.v:43384.13-43384.35"
wire width 2 $1\dmi0_datasr__oe[1:0]
- attribute \src "libresoc.v:43836.3-43856.6"
- wire width 64 $1\dmi0_datasr_reg$next[63:0]$1207
- attribute \src "libresoc.v:43203.14-43203.52"
+ attribute \src "libresoc.v:44027.3-44047.6"
+ wire width 64 $1\dmi0_datasr_reg$next[63:0]$1247
+ attribute \src "libresoc.v:43392.14-43392.52"
wire width 64 $1\dmi0_datasr_reg[63:0]
- attribute \src "libresoc.v:44479.3-44487.6"
- wire $1\dmi0_datasr_update_core$next[0:0]$1328
- attribute \src "libresoc.v:43211.7-43211.37"
+ attribute \src "libresoc.v:44670.3-44678.6"
+ wire $1\dmi0_datasr_update_core$next[0:0]$1368
+ attribute \src "libresoc.v:43400.7-43400.37"
wire $1\dmi0_datasr_update_core[0:0]
- attribute \src "libresoc.v:43810.3-43818.6"
- wire $1\dmi0_datasr_update_core_prev$next[0:0]$1200
- attribute \src "libresoc.v:43215.7-43215.42"
+ attribute \src "libresoc.v:44001.3-44009.6"
+ wire $1\dmi0_datasr_update_core_prev$next[0:0]$1240
+ attribute \src "libresoc.v:43404.7-43404.42"
wire $1\dmi0_datasr_update_core_prev[0:0]
- attribute \src "libresoc.v:44101.3-44127.6"
- wire width 64 $1\dmi0_din$next[63:0]$1249
- attribute \src "libresoc.v:43220.14-43220.45"
+ attribute \src "libresoc.v:44292.3-44318.6"
+ wire width 64 $1\dmi0_din$next[63:0]$1289
+ attribute \src "libresoc.v:43409.14-43409.45"
wire width 64 $1\dmi0_din[63:0]
- attribute \src "libresoc.v:44048.3-44100.6"
- wire width 3 $1\fsm_state$275$next[2:0]$1242
- attribute \src "libresoc.v:43914.3-43966.6"
- wire width 3 $1\fsm_state$next[2:0]$1219
- attribute \src "libresoc.v:43230.13-43230.29"
+ attribute \src "libresoc.v:44239.3-44291.6"
+ wire width 3 $1\fsm_state$275$next[2:0]$1282
+ attribute \src "libresoc.v:44105.3-44157.6"
+ wire width 3 $1\fsm_state$next[2:0]$1259
+ attribute \src "libresoc.v:43419.13-43419.29"
wire width 3 $1\fsm_state[2:0]
- attribute \src "libresoc.v:44234.3-44254.6"
- wire width 50 $1\io_bd$next[49:0]$1264
- attribute \src "libresoc.v:43430.14-43430.39"
+ attribute \src "libresoc.v:44425.3-44445.6"
+ wire width 50 $1\io_bd$next[49:0]$1304
+ attribute \src "libresoc.v:43623.14-43623.39"
wire width 50 $1\io_bd[49:0]
- attribute \src "libresoc.v:44149.3-44217.6"
- wire width 50 $1\io_sr$next[49:0]$1259
- attribute \src "libresoc.v:43442.14-43442.39"
+ attribute \src "libresoc.v:44340.3-44408.6"
+ wire width 50 $1\io_sr$next[49:0]$1299
+ attribute \src "libresoc.v:43635.14-43635.39"
wire width 50 $1\io_sr[49:0]
- attribute \src "libresoc.v:43881.3-43913.6"
- wire width 29 $1\jtag_wb__adr$next[28:0]$1213
- attribute \src "libresoc.v:43451.14-43451.41"
+ attribute \src "libresoc.v:44072.3-44104.6"
+ wire width 29 $1\jtag_wb__adr$next[28:0]$1253
+ attribute \src "libresoc.v:43644.14-43644.41"
wire width 29 $1\jtag_wb__adr[28:0]
- attribute \src "libresoc.v:43967.3-43993.6"
- wire width 64 $1\jtag_wb__dat_w$next[63:0]$1226
- attribute \src "libresoc.v:43460.14-43460.51"
+ attribute \src "libresoc.v:44158.3-44184.6"
+ wire width 64 $1\jtag_wb__dat_w$next[63:0]$1266
+ attribute \src "libresoc.v:43653.14-43653.51"
wire width 64 $1\jtag_wb__dat_w[63:0]
- attribute \src "libresoc.v:44329.3-44345.6"
- wire $1\jtag_wb_addrsr__oe$next[0:0]$1289
- attribute \src "libresoc.v:43474.7-43474.32"
+ attribute \src "libresoc.v:44520.3-44536.6"
+ wire $1\jtag_wb_addrsr__oe$next[0:0]$1329
+ attribute \src "libresoc.v:43667.7-43667.32"
wire $1\jtag_wb_addrsr__oe[0:0]
- attribute \src "libresoc.v:44346.3-44366.6"
- wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$1293
- attribute \src "libresoc.v:43482.14-43482.47"
+ attribute \src "libresoc.v:44537.3-44557.6"
+ wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$1333
+ attribute \src "libresoc.v:43675.14-43675.47"
wire width 29 $1\jtag_wb_addrsr_reg[28:0]
- attribute \src "libresoc.v:44311.3-44319.6"
- wire $1\jtag_wb_addrsr_update_core$next[0:0]$1283
- attribute \src "libresoc.v:43490.7-43490.40"
+ attribute \src "libresoc.v:44502.3-44510.6"
+ wire $1\jtag_wb_addrsr_update_core$next[0:0]$1323
+ attribute \src "libresoc.v:43683.7-43683.40"
wire $1\jtag_wb_addrsr_update_core[0:0]
- attribute \src "libresoc.v:44320.3-44328.6"
- wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1286
- attribute \src "libresoc.v:43494.7-43494.45"
+ attribute \src "libresoc.v:44511.3-44519.6"
+ wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1326
+ attribute \src "libresoc.v:43687.7-43687.45"
wire $1\jtag_wb_addrsr_update_core_prev[0:0]
- attribute \src "libresoc.v:43994.3-44014.6"
- wire width 64 $1\jtag_wb_datasr__i$next[63:0]$1231
- attribute \src "libresoc.v:43498.14-43498.54"
+ attribute \src "libresoc.v:44185.3-44205.6"
+ wire width 64 $1\jtag_wb_datasr__i$next[63:0]$1271
+ attribute \src "libresoc.v:43691.14-43691.54"
wire width 64 $1\jtag_wb_datasr__i[63:0]
- attribute \src "libresoc.v:44385.3-44401.6"
- wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$1304
- attribute \src "libresoc.v:43504.13-43504.38"
+ attribute \src "libresoc.v:44576.3-44592.6"
+ wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$1344
+ attribute \src "libresoc.v:43697.13-43697.38"
wire width 2 $1\jtag_wb_datasr__oe[1:0]
- attribute \src "libresoc.v:44402.3-44422.6"
- wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$1308
- attribute \src "libresoc.v:43512.14-43512.55"
+ attribute \src "libresoc.v:44593.3-44613.6"
+ wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$1348
+ attribute \src "libresoc.v:43705.14-43705.55"
wire width 64 $1\jtag_wb_datasr_reg[63:0]
- attribute \src "libresoc.v:44367.3-44375.6"
- wire $1\jtag_wb_datasr_update_core$next[0:0]$1298
- attribute \src "libresoc.v:43520.7-43520.40"
+ attribute \src "libresoc.v:44558.3-44566.6"
+ wire $1\jtag_wb_datasr_update_core$next[0:0]$1338
+ attribute \src "libresoc.v:43713.7-43713.40"
wire $1\jtag_wb_datasr_update_core[0:0]
- attribute \src "libresoc.v:44376.3-44384.6"
- wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$1301
- attribute \src "libresoc.v:43524.7-43524.45"
+ attribute \src "libresoc.v:44567.3-44575.6"
+ wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$1341
+ attribute \src "libresoc.v:43717.7-43717.45"
wire $1\jtag_wb_datasr_update_core_prev[0:0]
- attribute \src "libresoc.v:44273.3-44289.6"
- wire $1\sr0__oe$next[0:0]$1274
- attribute \src "libresoc.v:43542.7-43542.21"
+ attribute \src "libresoc.v:44464.3-44480.6"
+ wire $1\sr0__oe$next[0:0]$1314
+ attribute \src "libresoc.v:43733.7-43733.21"
wire $1\sr0__oe[0:0]
- attribute \src "libresoc.v:44290.3-44310.6"
- wire width 3 $1\sr0_reg$next[2:0]$1278
- attribute \src "libresoc.v:43550.13-43550.27"
+ attribute \src "libresoc.v:44481.3-44501.6"
+ wire width 3 $1\sr0_reg$next[2:0]$1318
+ attribute \src "libresoc.v:43741.13-43741.27"
wire width 3 $1\sr0_reg[2:0]
- attribute \src "libresoc.v:44255.3-44263.6"
- wire $1\sr0_update_core$next[0:0]$1268
- attribute \src "libresoc.v:43558.7-43558.29"
+ attribute \src "libresoc.v:44446.3-44454.6"
+ wire $1\sr0_update_core$next[0:0]$1308
+ attribute \src "libresoc.v:43749.7-43749.29"
wire $1\sr0_update_core[0:0]
- attribute \src "libresoc.v:44264.3-44272.6"
- wire $1\sr0_update_core_prev$next[0:0]$1271
- attribute \src "libresoc.v:43562.7-43562.34"
+ attribute \src "libresoc.v:44455.3-44463.6"
+ wire $1\sr0_update_core_prev$next[0:0]$1311
+ attribute \src "libresoc.v:43753.7-43753.34"
wire $1\sr0_update_core_prev[0:0]
- attribute \src "libresoc.v:44015.3-44047.6"
- wire width 4 $2\dmi0_addr_i$next[3:0]$1237
- attribute \src "libresoc.v:44441.3-44457.6"
- wire $2\dmi0_addrsr__oe$next[0:0]$1320
- attribute \src "libresoc.v:44458.3-44478.6"
- wire width 8 $2\dmi0_addrsr_reg$next[7:0]$1324
- attribute \src "libresoc.v:44128.3-44148.6"
- wire width 64 $2\dmi0_datasr__i$next[63:0]$1255
- attribute \src "libresoc.v:43819.3-43835.6"
- wire width 2 $2\dmi0_datasr__oe$next[1:0]$1204
- attribute \src "libresoc.v:43836.3-43856.6"
- wire width 64 $2\dmi0_datasr_reg$next[63:0]$1208
- attribute \src "libresoc.v:44101.3-44127.6"
- wire width 64 $2\dmi0_din$next[63:0]$1250
- attribute \src "libresoc.v:44048.3-44100.6"
- wire width 3 $2\fsm_state$275$next[2:0]$1243
- attribute \src "libresoc.v:43914.3-43966.6"
- wire width 3 $2\fsm_state$next[2:0]$1220
- attribute \src "libresoc.v:44234.3-44254.6"
- wire width 50 $2\io_bd$next[49:0]$1265
- attribute \src "libresoc.v:44149.3-44217.6"
- wire width 50 $2\io_sr$next[49:0]$1260
- attribute \src "libresoc.v:43881.3-43913.6"
- wire width 29 $2\jtag_wb__adr$next[28:0]$1214
- attribute \src "libresoc.v:43967.3-43993.6"
- wire width 64 $2\jtag_wb__dat_w$next[63:0]$1227
- attribute \src "libresoc.v:44329.3-44345.6"
- wire $2\jtag_wb_addrsr__oe$next[0:0]$1290
- attribute \src "libresoc.v:44346.3-44366.6"
- wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$1294
- attribute \src "libresoc.v:43994.3-44014.6"
- wire width 64 $2\jtag_wb_datasr__i$next[63:0]$1232
- attribute \src "libresoc.v:44385.3-44401.6"
- wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$1305
- attribute \src "libresoc.v:44402.3-44422.6"
- wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$1309
- attribute \src "libresoc.v:44273.3-44289.6"
- wire $2\sr0__oe$next[0:0]$1275
- attribute \src "libresoc.v:44290.3-44310.6"
- wire width 3 $2\sr0_reg$next[2:0]$1279
- attribute \src "libresoc.v:44015.3-44047.6"
- wire width 4 $3\dmi0_addr_i$next[3:0]$1238
- attribute \src "libresoc.v:44458.3-44478.6"
- wire width 8 $3\dmi0_addrsr_reg$next[7:0]$1325
- attribute \src "libresoc.v:44128.3-44148.6"
- wire width 64 $3\dmi0_datasr__i$next[63:0]$1256
- attribute \src "libresoc.v:43836.3-43856.6"
- wire width 64 $3\dmi0_datasr_reg$next[63:0]$1209
- attribute \src "libresoc.v:44101.3-44127.6"
- wire width 64 $3\dmi0_din$next[63:0]$1251
- attribute \src "libresoc.v:44048.3-44100.6"
- wire width 3 $3\fsm_state$275$next[2:0]$1244
- attribute \src "libresoc.v:43914.3-43966.6"
- wire width 3 $3\fsm_state$next[2:0]$1221
- attribute \src "libresoc.v:43881.3-43913.6"
- wire width 29 $3\jtag_wb__adr$next[28:0]$1215
- attribute \src "libresoc.v:43967.3-43993.6"
- wire width 64 $3\jtag_wb__dat_w$next[63:0]$1228
- attribute \src "libresoc.v:44346.3-44366.6"
- wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$1295
- attribute \src "libresoc.v:43994.3-44014.6"
- wire width 64 $3\jtag_wb_datasr__i$next[63:0]$1233
- attribute \src "libresoc.v:44402.3-44422.6"
- wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$1310
- attribute \src "libresoc.v:44290.3-44310.6"
- wire width 3 $3\sr0_reg$next[2:0]$1280
- attribute \src "libresoc.v:44015.3-44047.6"
- wire width 4 $4\dmi0_addr_i$next[3:0]$1239
- attribute \src "libresoc.v:44048.3-44100.6"
- wire width 3 $4\fsm_state$275$next[2:0]$1245
- attribute \src "libresoc.v:43914.3-43966.6"
- wire width 3 $4\fsm_state$next[2:0]$1222
- attribute \src "libresoc.v:43881.3-43913.6"
- wire width 29 $4\jtag_wb__adr$next[28:0]$1216
- attribute \src "libresoc.v:44048.3-44100.6"
- wire width 3 $5\fsm_state$275$next[2:0]$1246
- attribute \src "libresoc.v:43914.3-43966.6"
- wire width 3 $5\fsm_state$next[2:0]$1223
- attribute \src "libresoc.v:43667.19-43667.110"
- wire width 30 $add$libresoc.v:43667$1118_Y
- attribute \src "libresoc.v:43668.19-43668.110"
- wire width 30 $add$libresoc.v:43668$1119_Y
- attribute \src "libresoc.v:43675.19-43675.109"
- wire width 5 $add$libresoc.v:43675$1127_Y
- attribute \src "libresoc.v:43676.19-43676.109"
- wire width 5 $add$libresoc.v:43676$1128_Y
- attribute \src "libresoc.v:43600.19-43600.110"
- wire $and$libresoc.v:43600$1051_Y
- attribute \src "libresoc.v:43607.19-43607.110"
- wire $and$libresoc.v:43607$1058_Y
- attribute \src "libresoc.v:43610.19-43610.114"
- wire $and$libresoc.v:43610$1061_Y
- attribute \src "libresoc.v:43612.19-43612.112"
- wire $and$libresoc.v:43612$1063_Y
- attribute \src "libresoc.v:43614.19-43614.113"
- wire $and$libresoc.v:43614$1065_Y
- attribute \src "libresoc.v:43616.19-43616.121"
- wire $and$libresoc.v:43616$1067_Y
- attribute \src "libresoc.v:43620.19-43620.114"
- wire $and$libresoc.v:43620$1071_Y
- attribute \src "libresoc.v:43622.19-43622.112"
- wire $and$libresoc.v:43622$1073_Y
- attribute \src "libresoc.v:43624.19-43624.113"
- wire $and$libresoc.v:43624$1075_Y
- attribute \src "libresoc.v:43626.19-43626.132"
- wire $and$libresoc.v:43626$1077_Y
- attribute \src "libresoc.v:43629.18-43629.108"
- wire $and$libresoc.v:43629$1080_Y
- attribute \src "libresoc.v:43632.19-43632.114"
- wire $and$libresoc.v:43632$1083_Y
- attribute \src "libresoc.v:43634.19-43634.112"
- wire $and$libresoc.v:43634$1085_Y
- attribute \src "libresoc.v:43636.19-43636.113"
- wire $and$libresoc.v:43636$1087_Y
- attribute \src "libresoc.v:43638.19-43638.132"
- wire $and$libresoc.v:43638$1089_Y
- attribute \src "libresoc.v:43640.18-43640.110"
- wire $and$libresoc.v:43640$1091_Y
- attribute \src "libresoc.v:43642.19-43642.114"
- wire $and$libresoc.v:43642$1093_Y
- attribute \src "libresoc.v:43644.19-43644.112"
- wire $and$libresoc.v:43644$1095_Y
- attribute \src "libresoc.v:43646.19-43646.113"
- wire $and$libresoc.v:43646$1097_Y
- attribute \src "libresoc.v:43648.19-43648.129"
- wire $and$libresoc.v:43648$1099_Y
- attribute \src "libresoc.v:43653.19-43653.114"
- wire $and$libresoc.v:43653$1104_Y
- attribute \src "libresoc.v:43655.19-43655.112"
- wire $and$libresoc.v:43655$1106_Y
- attribute \src "libresoc.v:43657.19-43657.113"
- wire $and$libresoc.v:43657$1108_Y
- attribute \src "libresoc.v:43659.19-43659.129"
- wire $and$libresoc.v:43659$1110_Y
- attribute \src "libresoc.v:43679.18-43679.108"
- wire $and$libresoc.v:43679$1131_Y
- attribute \src "libresoc.v:43680.18-43680.111"
- wire $and$libresoc.v:43680$1132_Y
- attribute \src "libresoc.v:43704.17-43704.110"
- wire $and$libresoc.v:43704$1156_Y
- attribute \src "libresoc.v:43573.17-43573.110"
- wire $eq$libresoc.v:43573$1024_Y
- attribute \src "libresoc.v:43584.18-43584.111"
- wire $eq$libresoc.v:43584$1035_Y
- attribute \src "libresoc.v:43597.19-43597.112"
- wire $eq$libresoc.v:43597$1048_Y
- attribute \src "libresoc.v:43598.19-43598.112"
- wire $eq$libresoc.v:43598$1049_Y
- attribute \src "libresoc.v:43601.19-43601.112"
- wire $eq$libresoc.v:43601$1052_Y
- attribute \src "libresoc.v:43602.19-43602.112"
- wire $eq$libresoc.v:43602$1053_Y
- attribute \src "libresoc.v:43604.19-43604.112"
- wire $eq$libresoc.v:43604$1055_Y
- attribute \src "libresoc.v:43606.18-43606.111"
- wire $eq$libresoc.v:43606$1057_Y
- attribute \src "libresoc.v:43608.19-43608.112"
- wire $eq$libresoc.v:43608$1059_Y
- attribute \src "libresoc.v:43618.19-43618.112"
- wire $eq$libresoc.v:43618$1069_Y
- attribute \src "libresoc.v:43627.19-43627.112"
- wire $eq$libresoc.v:43627$1078_Y
- attribute \src "libresoc.v:43628.17-43628.110"
- wire $eq$libresoc.v:43628$1079_Y
- attribute \src "libresoc.v:43630.19-43630.112"
- wire $eq$libresoc.v:43630$1081_Y
- attribute \src "libresoc.v:43639.19-43639.112"
- wire $eq$libresoc.v:43639$1090_Y
- attribute \src "libresoc.v:43649.19-43649.112"
- wire $eq$libresoc.v:43649$1100_Y
- attribute \src "libresoc.v:43650.19-43650.112"
- wire $eq$libresoc.v:43650$1101_Y
- attribute \src "libresoc.v:43651.18-43651.111"
- wire $eq$libresoc.v:43651$1102_Y
- attribute \src "libresoc.v:43660.19-43660.108"
- wire $eq$libresoc.v:43660$1111_Y
- attribute \src "libresoc.v:43662.18-43662.111"
- wire $eq$libresoc.v:43662$1113_Y
- attribute \src "libresoc.v:43663.19-43663.108"
- wire $eq$libresoc.v:43663$1114_Y
- attribute \src "libresoc.v:43664.19-43664.108"
- wire $eq$libresoc.v:43664$1115_Y
- attribute \src "libresoc.v:43666.19-43666.108"
- wire $eq$libresoc.v:43666$1117_Y
- attribute \src "libresoc.v:43670.19-43670.114"
- wire $eq$libresoc.v:43670$1122_Y
- attribute \src "libresoc.v:43671.19-43671.114"
- wire $eq$libresoc.v:43671$1123_Y
- attribute \src "libresoc.v:43674.19-43674.114"
- wire $eq$libresoc.v:43674$1126_Y
- attribute \src "libresoc.v:43677.18-43677.111"
- wire $eq$libresoc.v:43677$1129_Y
- attribute \src "libresoc.v:43681.18-43681.111"
- wire $eq$libresoc.v:43681$1133_Y
- attribute \src "libresoc.v:43682.17-43682.110"
- wire $eq$libresoc.v:43682$1134_Y
- attribute \src "libresoc.v:43683.18-43683.111"
- wire $eq$libresoc.v:43683$1135_Y
- attribute \src "libresoc.v:43669.19-43669.98"
- wire width 8 $extend$libresoc.v:43669$1120_Y
- attribute \src "libresoc.v:43609.19-43609.109"
- wire $ne$libresoc.v:43609$1060_Y
- attribute \src "libresoc.v:43611.19-43611.109"
- wire $ne$libresoc.v:43611$1062_Y
- attribute \src "libresoc.v:43613.19-43613.109"
- wire $ne$libresoc.v:43613$1064_Y
- attribute \src "libresoc.v:43619.19-43619.120"
- wire $ne$libresoc.v:43619$1070_Y
- attribute \src "libresoc.v:43621.19-43621.120"
- wire $ne$libresoc.v:43621$1072_Y
- attribute \src "libresoc.v:43623.19-43623.120"
- wire $ne$libresoc.v:43623$1074_Y
- attribute \src "libresoc.v:43631.19-43631.120"
- wire $ne$libresoc.v:43631$1082_Y
- attribute \src "libresoc.v:43633.19-43633.120"
- wire $ne$libresoc.v:43633$1084_Y
- attribute \src "libresoc.v:43635.19-43635.120"
- wire $ne$libresoc.v:43635$1086_Y
- attribute \src "libresoc.v:43641.19-43641.117"
- wire $ne$libresoc.v:43641$1092_Y
- attribute \src "libresoc.v:43643.19-43643.117"
- wire $ne$libresoc.v:43643$1094_Y
- attribute \src "libresoc.v:43645.19-43645.117"
- wire $ne$libresoc.v:43645$1096_Y
- attribute \src "libresoc.v:43652.19-43652.117"
- wire $ne$libresoc.v:43652$1103_Y
- attribute \src "libresoc.v:43654.19-43654.117"
- wire $ne$libresoc.v:43654$1105_Y
- attribute \src "libresoc.v:43656.19-43656.117"
- wire $ne$libresoc.v:43656$1107_Y
- attribute \src "libresoc.v:43615.19-43615.110"
- wire $not$libresoc.v:43615$1066_Y
- attribute \src "libresoc.v:43625.19-43625.121"
- wire $not$libresoc.v:43625$1076_Y
- attribute \src "libresoc.v:43637.19-43637.121"
- wire $not$libresoc.v:43637$1088_Y
- attribute \src "libresoc.v:43647.19-43647.118"
- wire $not$libresoc.v:43647$1098_Y
- attribute \src "libresoc.v:43658.19-43658.118"
- wire $not$libresoc.v:43658$1109_Y
- attribute \src "libresoc.v:43661.19-43661.98"
- wire $not$libresoc.v:43661$1112_Y
- attribute \src "libresoc.v:43595.18-43595.103"
- wire $or$libresoc.v:43595$1046_Y
- attribute \src "libresoc.v:43599.19-43599.107"
- wire $or$libresoc.v:43599$1050_Y
- attribute \src "libresoc.v:43603.19-43603.107"
- wire $or$libresoc.v:43603$1054_Y
- attribute \src "libresoc.v:43605.19-43605.107"
- wire $or$libresoc.v:43605$1056_Y
- attribute \src "libresoc.v:43617.18-43617.104"
- wire $or$libresoc.v:43617$1068_Y
- attribute \src "libresoc.v:43665.19-43665.105"
- wire $or$libresoc.v:43665$1116_Y
- attribute \src "libresoc.v:43672.18-43672.104"
- wire $or$libresoc.v:43672$1124_Y
- attribute \src "libresoc.v:43673.19-43673.105"
- wire $or$libresoc.v:43673$1125_Y
- attribute \src "libresoc.v:43678.18-43678.104"
- wire $or$libresoc.v:43678$1130_Y
- attribute \src "libresoc.v:43693.17-43693.101"
- wire $or$libresoc.v:43693$1145_Y
- attribute \src "libresoc.v:43669.19-43669.98"
- wire width 8 $pos$libresoc.v:43669$1121_Y
- attribute \src "libresoc.v:43574.18-43574.135"
- wire $ternary$libresoc.v:43574$1025_Y
- attribute \src "libresoc.v:43575.19-43575.135"
- wire $ternary$libresoc.v:43575$1026_Y
- attribute \src "libresoc.v:43576.19-43576.136"
- wire $ternary$libresoc.v:43576$1027_Y
- attribute \src "libresoc.v:43577.19-43577.137"
- wire $ternary$libresoc.v:43577$1028_Y
- attribute \src "libresoc.v:43578.19-43578.136"
- wire $ternary$libresoc.v:43578$1029_Y
- attribute \src "libresoc.v:43579.19-43579.137"
- wire $ternary$libresoc.v:43579$1030_Y
- attribute \src "libresoc.v:43580.19-43580.137"
- wire $ternary$libresoc.v:43580$1031_Y
- attribute \src "libresoc.v:43581.19-43581.136"
- wire $ternary$libresoc.v:43581$1032_Y
- attribute \src "libresoc.v:43582.19-43582.137"
- wire $ternary$libresoc.v:43582$1033_Y
- attribute \src "libresoc.v:43583.19-43583.137"
- wire $ternary$libresoc.v:43583$1034_Y
- attribute \src "libresoc.v:43585.19-43585.136"
- wire $ternary$libresoc.v:43585$1036_Y
- attribute \src "libresoc.v:43586.19-43586.137"
- wire $ternary$libresoc.v:43586$1037_Y
- attribute \src "libresoc.v:43587.19-43587.137"
- wire $ternary$libresoc.v:43587$1038_Y
- attribute \src "libresoc.v:43588.19-43588.136"
- wire $ternary$libresoc.v:43588$1039_Y
- attribute \src "libresoc.v:43589.19-43589.137"
- wire $ternary$libresoc.v:43589$1040_Y
- attribute \src "libresoc.v:43590.19-43590.137"
- wire $ternary$libresoc.v:43590$1041_Y
- attribute \src "libresoc.v:43591.19-43591.136"
- wire $ternary$libresoc.v:43591$1042_Y
- attribute \src "libresoc.v:43592.19-43592.137"
- wire $ternary$libresoc.v:43592$1043_Y
- attribute \src "libresoc.v:43593.19-43593.137"
- wire $ternary$libresoc.v:43593$1044_Y
- attribute \src "libresoc.v:43594.19-43594.136"
- wire $ternary$libresoc.v:43594$1045_Y
- attribute \src "libresoc.v:43596.19-43596.137"
- wire $ternary$libresoc.v:43596$1047_Y
- attribute \src "libresoc.v:43684.18-43684.130"
- wire $ternary$libresoc.v:43684$1136_Y
- attribute \src "libresoc.v:43685.18-43685.131"
- wire $ternary$libresoc.v:43685$1137_Y
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- wire $ternary$libresoc.v:43686$1138_Y
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- wire $ternary$libresoc.v:43687$1139_Y
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- wire $ternary$libresoc.v:43688$1140_Y
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- wire $ternary$libresoc.v:43689$1141_Y
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- wire $ternary$libresoc.v:43690$1142_Y
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- wire $ternary$libresoc.v:43692$1144_Y
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- wire $ternary$libresoc.v:43694$1146_Y
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- wire $ternary$libresoc.v:43697$1149_Y
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- wire $ternary$libresoc.v:43698$1150_Y
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- wire $ternary$libresoc.v:43714$1166_Y
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+ wire $eq$libresoc.v:43788$1088_Y
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+ wire $eq$libresoc.v:43789$1089_Y
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+ wire $eq$libresoc.v:43795$1095_Y
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+ wire $eq$libresoc.v:43797$1097_Y
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+ wire $eq$libresoc.v:43799$1099_Y
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+ wire $eq$libresoc.v:43821$1121_Y
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+ wire $eq$libresoc.v:43855$1155_Y
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+ wire $eq$libresoc.v:43857$1157_Y
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+ wire $eq$libresoc.v:43861$1162_Y
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+ wire $eq$libresoc.v:43862$1163_Y
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+ wire $eq$libresoc.v:43865$1166_Y
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+ wire $eq$libresoc.v:43868$1169_Y
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+ wire $eq$libresoc.v:43872$1173_Y
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+ wire $ne$libresoc.v:43824$1124_Y
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+ wire $ne$libresoc.v:43834$1134_Y
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+ wire $not$libresoc.v:43816$1116_Y
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+ wire $not$libresoc.v:43828$1128_Y
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+ wire $or$libresoc.v:43864$1165_Y
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+ wire $or$libresoc.v:43869$1170_Y
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+ wire $ternary$libresoc.v:43766$1066_Y
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+ wire $ternary$libresoc.v:43767$1067_Y
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+ wire $ternary$libresoc.v:43768$1068_Y
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+ wire $ternary$libresoc.v:43769$1069_Y
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+ wire $ternary$libresoc.v:43770$1070_Y
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+ wire $ternary$libresoc.v:43772$1072_Y
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+ wire $ternary$libresoc.v:43773$1073_Y
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+ wire $ternary$libresoc.v:43776$1076_Y
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+ wire $ternary$libresoc.v:43777$1077_Y
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+ wire $ternary$libresoc.v:43778$1078_Y
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+ wire $ternary$libresoc.v:43779$1079_Y
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+ wire $ternary$libresoc.v:43780$1080_Y
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+ wire $ternary$libresoc.v:43781$1081_Y
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+ wire $ternary$libresoc.v:43782$1082_Y
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+ wire $ternary$libresoc.v:43783$1083_Y
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+ wire $ternary$libresoc.v:43784$1084_Y
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+ wire $ternary$libresoc.v:43785$1085_Y
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+ wire $ternary$libresoc.v:43787$1087_Y
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+ wire $ternary$libresoc.v:43875$1176_Y
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+ wire $ternary$libresoc.v:43876$1177_Y
+ attribute \src "libresoc.v:43877.18-43877.134"
+ wire $ternary$libresoc.v:43877$1178_Y
+ attribute \src "libresoc.v:43878.18-43878.133"
+ wire $ternary$libresoc.v:43878$1179_Y
+ attribute \src "libresoc.v:43879.18-43879.134"
+ wire $ternary$libresoc.v:43879$1180_Y
+ attribute \src "libresoc.v:43880.18-43880.134"
+ wire $ternary$libresoc.v:43880$1181_Y
+ attribute \src "libresoc.v:43881.18-43881.133"
+ wire $ternary$libresoc.v:43881$1182_Y
+ attribute \src "libresoc.v:43882.18-43882.134"
+ wire $ternary$libresoc.v:43882$1183_Y
+ attribute \src "libresoc.v:43883.18-43883.134"
+ wire $ternary$libresoc.v:43883$1184_Y
+ attribute \src "libresoc.v:43885.18-43885.133"
+ wire $ternary$libresoc.v:43885$1186_Y
+ attribute \src "libresoc.v:43886.18-43886.135"
+ wire $ternary$libresoc.v:43886$1187_Y
+ attribute \src "libresoc.v:43887.18-43887.135"
+ wire $ternary$libresoc.v:43887$1188_Y
+ attribute \src "libresoc.v:43888.18-43888.134"
+ wire $ternary$libresoc.v:43888$1189_Y
+ attribute \src "libresoc.v:43889.18-43889.135"
+ wire $ternary$libresoc.v:43889$1190_Y
+ attribute \src "libresoc.v:43890.18-43890.135"
+ wire $ternary$libresoc.v:43890$1191_Y
+ attribute \src "libresoc.v:43891.18-43891.134"
+ wire $ternary$libresoc.v:43891$1192_Y
+ attribute \src "libresoc.v:43892.18-43892.135"
+ wire $ternary$libresoc.v:43892$1193_Y
+ attribute \src "libresoc.v:43893.18-43893.135"
+ wire $ternary$libresoc.v:43893$1194_Y
+ attribute \src "libresoc.v:43894.18-43894.134"
+ wire $ternary$libresoc.v:43894$1195_Y
+ attribute \src "libresoc.v:43896.18-43896.135"
+ wire $ternary$libresoc.v:43896$1197_Y
+ attribute \src "libresoc.v:43897.18-43897.135"
+ wire $ternary$libresoc.v:43897$1198_Y
+ attribute \src "libresoc.v:43898.18-43898.134"
+ wire $ternary$libresoc.v:43898$1199_Y
+ attribute \src "libresoc.v:43899.18-43899.135"
+ wire $ternary$libresoc.v:43899$1200_Y
+ attribute \src "libresoc.v:43900.18-43900.135"
+ wire $ternary$libresoc.v:43900$1201_Y
+ attribute \src "libresoc.v:43901.18-43901.134"
+ wire $ternary$libresoc.v:43901$1202_Y
+ attribute \src "libresoc.v:43902.18-43902.135"
+ wire $ternary$libresoc.v:43902$1203_Y
+ attribute \src "libresoc.v:43903.18-43903.135"
+ wire $ternary$libresoc.v:43903$1204_Y
+ attribute \src "libresoc.v:43904.18-43904.134"
+ wire $ternary$libresoc.v:43904$1205_Y
+ attribute \src "libresoc.v:43905.18-43905.135"
+ wire $ternary$libresoc.v:43905$1206_Y
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
wire \$1
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
wire width 4 \_irblock_ir
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129"
wire \_irblock_tdo
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151"
- wire input 6 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62"
wire input 4 \dmi0_ack_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57"
wire output 89 \gpio_gpio9__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
wire output 90 \gpio_gpio9__pad__oe
- attribute \src "libresoc.v:42831.7-42831.15"
+ attribute \src "libresoc.v:43022.7-43022.15"
wire \initial
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153"
+ wire input 6 \intclk_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153"
+ wire input 7 \intclk_rst
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:437"
wire width 50 \io_bd
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:437"
wire \posjtag_clk
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29"
wire \posjtag_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151"
- wire input 7 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52"
wire width 3 \sr0__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
wire output 59 \uart_tx__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201"
- cell $add $add$libresoc.v:43667$1118
+ cell $add $add$libresoc.v:43858$1158
parameter \A_SIGNED 0
parameter \A_WIDTH 29
parameter \B_SIGNED 0
parameter \Y_WIDTH 30
connect \A \jtag_wb__adr
connect \B 1'1
- connect \Y $add$libresoc.v:43667$1118_Y
+ connect \Y $add$libresoc.v:43858$1158_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225"
- cell $add $add$libresoc.v:43668$1119
+ cell $add $add$libresoc.v:43859$1159
parameter \A_SIGNED 0
parameter \A_WIDTH 29
parameter \B_SIGNED 0
parameter \Y_WIDTH 30
connect \A \jtag_wb__adr
connect \B 1'1
- connect \Y $add$libresoc.v:43668$1119_Y
+ connect \Y $add$libresoc.v:43859$1159_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153"
- cell $add $add$libresoc.v:43675$1127
+ cell $add $add$libresoc.v:43866$1167
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \dmi0_addr_i
connect \B 1'1
- connect \Y $add$libresoc.v:43675$1127_Y
+ connect \Y $add$libresoc.v:43866$1167_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177"
- cell $add $add$libresoc.v:43676$1128
+ cell $add $add$libresoc.v:43867$1168
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \dmi0_addr_i
connect \B 1'1
- connect \Y $add$libresoc.v:43676$1128_Y
+ connect \Y $add$libresoc.v:43867$1168_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362"
- cell $and $and$libresoc.v:43600$1051
+ cell $and $and$libresoc.v:43791$1091
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_fsm_isdr
connect \B \$145
- connect \Y $and$libresoc.v:43600$1051_Y
+ connect \Y $and$libresoc.v:43791$1091_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380"
- cell $and $and$libresoc.v:43607$1058
+ cell $and $and$libresoc.v:43798$1098
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_fsm_isdr
connect \B \$157
- connect \Y $and$libresoc.v:43607$1058_Y
+ connect \Y $and$libresoc.v:43798$1098_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539"
- cell $and $and$libresoc.v:43610$1061
+ cell $and $and$libresoc.v:43801$1101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$163
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:43610$1061_Y
+ connect \Y $and$libresoc.v:43801$1101_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540"
- cell $and $and$libresoc.v:43612$1063
+ cell $and $and$libresoc.v:43803$1103
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$167
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:43612$1063_Y
+ connect \Y $and$libresoc.v:43803$1103_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541"
- cell $and $and$libresoc.v:43614$1065
+ cell $and $and$libresoc.v:43805$1105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$171
connect \B \_fsm_update
- connect \Y $and$libresoc.v:43614$1065_Y
+ connect \Y $and$libresoc.v:43805$1105_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553"
- cell $and $and$libresoc.v:43616$1067
+ cell $and $and$libresoc.v:43807$1107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr0_update_core_prev
connect \B \$175
- connect \Y $and$libresoc.v:43616$1067_Y
+ connect \Y $and$libresoc.v:43807$1107_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539"
- cell $and $and$libresoc.v:43620$1071
+ cell $and $and$libresoc.v:43811$1111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$181
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:43620$1071_Y
+ connect \Y $and$libresoc.v:43811$1111_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540"
- cell $and $and$libresoc.v:43622$1073
+ cell $and $and$libresoc.v:43813$1113
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$185
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:43622$1073_Y
+ connect \Y $and$libresoc.v:43813$1113_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541"
- cell $and $and$libresoc.v:43624$1075
+ cell $and $and$libresoc.v:43815$1115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$189
connect \B \_fsm_update
- connect \Y $and$libresoc.v:43624$1075_Y
+ connect \Y $and$libresoc.v:43815$1115_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553"
- cell $and $and$libresoc.v:43626$1077
+ cell $and $and$libresoc.v:43817$1117
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_update_core_prev
connect \B \$193
- connect \Y $and$libresoc.v:43626$1077_Y
+ connect \Y $and$libresoc.v:43817$1117_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380"
- cell $and $and$libresoc.v:43629$1080
+ cell $and $and$libresoc.v:43820$1120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_fsm_isdr
connect \B \$17
- connect \Y $and$libresoc.v:43629$1080_Y
+ connect \Y $and$libresoc.v:43820$1120_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539"
- cell $and $and$libresoc.v:43632$1083
+ cell $and $and$libresoc.v:43823$1123
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$201
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:43632$1083_Y
+ connect \Y $and$libresoc.v:43823$1123_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540"
- cell $and $and$libresoc.v:43634$1085
+ cell $and $and$libresoc.v:43825$1125
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$205
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:43634$1085_Y
+ connect \Y $and$libresoc.v:43825$1125_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541"
- cell $and $and$libresoc.v:43636$1087
+ cell $and $and$libresoc.v:43827$1127
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$209
connect \B \_fsm_update
- connect \Y $and$libresoc.v:43636$1087_Y
+ connect \Y $and$libresoc.v:43827$1127_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553"
- cell $and $and$libresoc.v:43638$1089
+ cell $and $and$libresoc.v:43829$1129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_update_core_prev
connect \B \$213
- connect \Y $and$libresoc.v:43638$1089_Y
+ connect \Y $and$libresoc.v:43829$1129_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383"
- cell $and $and$libresoc.v:43640$1091
+ cell $and $and$libresoc.v:43831$1131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$19
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:43640$1091_Y
+ connect \Y $and$libresoc.v:43831$1131_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539"
- cell $and $and$libresoc.v:43642$1093
+ cell $and $and$libresoc.v:43833$1133
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$219
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:43642$1093_Y
+ connect \Y $and$libresoc.v:43833$1133_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540"
- cell $and $and$libresoc.v:43644$1095
+ cell $and $and$libresoc.v:43835$1135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$223
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:43644$1095_Y
+ connect \Y $and$libresoc.v:43835$1135_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541"
- cell $and $and$libresoc.v:43646$1097
+ cell $and $and$libresoc.v:43837$1137
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$227
connect \B \_fsm_update
- connect \Y $and$libresoc.v:43646$1097_Y
+ connect \Y $and$libresoc.v:43837$1137_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553"
- cell $and $and$libresoc.v:43648$1099
+ cell $and $and$libresoc.v:43839$1139
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_update_core_prev
connect \B \$231
- connect \Y $and$libresoc.v:43648$1099_Y
+ connect \Y $and$libresoc.v:43839$1139_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539"
- cell $and $and$libresoc.v:43653$1104
+ cell $and $and$libresoc.v:43844$1144
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$239
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:43653$1104_Y
+ connect \Y $and$libresoc.v:43844$1144_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540"
- cell $and $and$libresoc.v:43655$1106
+ cell $and $and$libresoc.v:43846$1146
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$243
connect \B \_fsm_shift
- connect \Y $and$libresoc.v:43655$1106_Y
+ connect \Y $and$libresoc.v:43846$1146_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541"
- cell $and $and$libresoc.v:43657$1108
+ cell $and $and$libresoc.v:43848$1148
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$247
connect \B \_fsm_update
- connect \Y $and$libresoc.v:43657$1108_Y
+ connect \Y $and$libresoc.v:43848$1148_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553"
- cell $and $and$libresoc.v:43659$1110
+ cell $and $and$libresoc.v:43850$1150
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_update_core_prev
connect \B \$251
- connect \Y $and$libresoc.v:43659$1110_Y
+ connect \Y $and$libresoc.v:43850$1150_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380"
- cell $and $and$libresoc.v:43679$1131
+ cell $and $and$libresoc.v:43870$1171
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_fsm_isdr
connect \B \$31
- connect \Y $and$libresoc.v:43679$1131_Y
+ connect \Y $and$libresoc.v:43870$1171_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384"
- cell $and $and$libresoc.v:43680$1132
+ cell $and $and$libresoc.v:43871$1172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$33
connect \B \_fsm_update
- connect \Y $and$libresoc.v:43680$1132_Y
+ connect \Y $and$libresoc.v:43871$1172_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:382"
- cell $and $and$libresoc.v:43704$1156
+ cell $and $and$libresoc.v:43895$1196
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$5
connect \B \_fsm_capture
- connect \Y $and$libresoc.v:43704$1156_Y
+ connect \Y $and$libresoc.v:43895$1196_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $eq $eq$libresoc.v:43573$1024
+ cell $eq $eq$libresoc.v:43764$1064
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:43573$1024_Y
+ connect \Y $eq$libresoc.v:43764$1064_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $eq $eq$libresoc.v:43584$1035
+ cell $eq $eq$libresoc.v:43775$1075
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:43584$1035_Y
+ connect \Y $eq$libresoc.v:43775$1075_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362"
- cell $eq $eq$libresoc.v:43597$1048
+ cell $eq $eq$libresoc.v:43788$1088
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'1
- connect \Y $eq$libresoc.v:43597$1048_Y
+ connect \Y $eq$libresoc.v:43788$1088_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362"
- cell $eq $eq$libresoc.v:43598$1049
+ cell $eq $eq$libresoc.v:43789$1089
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1111
- connect \Y $eq$libresoc.v:43598$1049_Y
+ connect \Y $eq$libresoc.v:43789$1089_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $eq $eq$libresoc.v:43601$1052
+ cell $eq $eq$libresoc.v:43792$1092
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:43601$1052_Y
+ connect \Y $eq$libresoc.v:43792$1092_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $eq $eq$libresoc.v:43602$1053
+ cell $eq $eq$libresoc.v:43793$1093
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:43602$1053_Y
+ connect \Y $eq$libresoc.v:43793$1093_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379"
- cell $eq $eq$libresoc.v:43604$1055
+ cell $eq $eq$libresoc.v:43795$1095
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:43604$1055_Y
+ connect \Y $eq$libresoc.v:43795$1095_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379"
- cell $eq $eq$libresoc.v:43606$1057
+ cell $eq $eq$libresoc.v:43797$1097
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:43606$1057_Y
+ connect \Y $eq$libresoc.v:43797$1097_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538"
- cell $eq $eq$libresoc.v:43608$1059
+ cell $eq $eq$libresoc.v:43799$1099
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 3'100
- connect \Y $eq$libresoc.v:43608$1059_Y
+ connect \Y $eq$libresoc.v:43799$1099_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538"
- cell $eq $eq$libresoc.v:43618$1069
+ cell $eq $eq$libresoc.v:43809$1109
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 3'101
- connect \Y $eq$libresoc.v:43618$1069_Y
+ connect \Y $eq$libresoc.v:43809$1109_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538"
- cell $eq $eq$libresoc.v:43627$1078
+ cell $eq $eq$libresoc.v:43818$1118
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 3'110
- connect \Y $eq$libresoc.v:43627$1078_Y
+ connect \Y $eq$libresoc.v:43818$1118_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $eq $eq$libresoc.v:43628$1079
+ cell $eq $eq$libresoc.v:43819$1119
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:43628$1079_Y
+ connect \Y $eq$libresoc.v:43819$1119_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538"
- cell $eq $eq$libresoc.v:43630$1081
+ cell $eq $eq$libresoc.v:43821$1121
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 3'111
- connect \Y $eq$libresoc.v:43630$1081_Y
+ connect \Y $eq$libresoc.v:43821$1121_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538"
- cell $eq $eq$libresoc.v:43639$1090
+ cell $eq $eq$libresoc.v:43830$1130
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1000
- connect \Y $eq$libresoc.v:43639$1090_Y
+ connect \Y $eq$libresoc.v:43830$1130_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538"
- cell $eq $eq$libresoc.v:43649$1100
+ cell $eq $eq$libresoc.v:43840$1140
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1001
- connect \Y $eq$libresoc.v:43649$1100_Y
+ connect \Y $eq$libresoc.v:43840$1140_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538"
- cell $eq $eq$libresoc.v:43650$1101
+ cell $eq $eq$libresoc.v:43841$1141
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 4'1010
- connect \Y $eq$libresoc.v:43650$1101_Y
+ connect \Y $eq$libresoc.v:43841$1141_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $eq $eq$libresoc.v:43651$1102
+ cell $eq $eq$libresoc.v:43842$1142
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:43651$1102_Y
+ connect \Y $eq$libresoc.v:43842$1142_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229"
- cell $eq $eq$libresoc.v:43660$1111
+ cell $eq $eq$libresoc.v:43851$1151
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state
connect \B 1'0
- connect \Y $eq$libresoc.v:43660$1111_Y
+ connect \Y $eq$libresoc.v:43851$1151_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $eq $eq$libresoc.v:43662$1113
+ cell $eq $eq$libresoc.v:43853$1153
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:43662$1113_Y
+ connect \Y $eq$libresoc.v:43853$1153_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230"
- cell $eq $eq$libresoc.v:43663$1114
+ cell $eq $eq$libresoc.v:43854$1154
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state
connect \B 1'1
- connect \Y $eq$libresoc.v:43663$1114_Y
+ connect \Y $eq$libresoc.v:43854$1154_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230"
- cell $eq $eq$libresoc.v:43664$1115
+ cell $eq $eq$libresoc.v:43855$1155
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state
connect \B 2'10
- connect \Y $eq$libresoc.v:43664$1115_Y
+ connect \Y $eq$libresoc.v:43855$1155_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:231"
- cell $eq $eq$libresoc.v:43666$1117
+ cell $eq $eq$libresoc.v:43857$1157
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state
connect \B 2'10
- connect \Y $eq$libresoc.v:43666$1117_Y
+ connect \Y $eq$libresoc.v:43857$1157_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182"
- cell $eq $eq$libresoc.v:43670$1122
+ cell $eq $eq$libresoc.v:43861$1162
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state$275
connect \B 1'1
- connect \Y $eq$libresoc.v:43670$1122_Y
+ connect \Y $eq$libresoc.v:43861$1162_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182"
- cell $eq $eq$libresoc.v:43671$1123
+ cell $eq $eq$libresoc.v:43862$1163
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state$275
connect \B 2'10
- connect \Y $eq$libresoc.v:43671$1123_Y
+ connect \Y $eq$libresoc.v:43862$1163_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:183"
- cell $eq $eq$libresoc.v:43674$1126
+ cell $eq $eq$libresoc.v:43865$1166
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fsm_state$275
connect \B 2'10
- connect \Y $eq$libresoc.v:43674$1126_Y
+ connect \Y $eq$libresoc.v:43865$1166_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379"
- cell $eq $eq$libresoc.v:43677$1129
+ cell $eq $eq$libresoc.v:43868$1169
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:43677$1129_Y
+ connect \Y $eq$libresoc.v:43868$1169_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385"
- cell $eq $eq$libresoc.v:43681$1133
+ cell $eq $eq$libresoc.v:43872$1173
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:43681$1133_Y
+ connect \Y $eq$libresoc.v:43872$1173_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $eq $eq$libresoc.v:43682$1134
+ cell $eq $eq$libresoc.v:43873$1174
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 2'10
- connect \Y $eq$libresoc.v:43682$1134_Y
+ connect \Y $eq$libresoc.v:43873$1174_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:386"
- cell $eq $eq$libresoc.v:43683$1135
+ cell $eq $eq$libresoc.v:43874$1175
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \_irblock_ir
connect \B 1'0
- connect \Y $eq$libresoc.v:43683$1135_Y
+ connect \Y $eq$libresoc.v:43874$1175_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57"
- cell $pos $extend$libresoc.v:43669$1120
+ cell $pos $extend$libresoc.v:43860$1160
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 8
connect \A \dmi0_addr_i
- connect \Y $extend$libresoc.v:43669$1120_Y
+ connect \Y $extend$libresoc.v:43860$1160_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539"
- cell $ne $ne$libresoc.v:43609$1060
+ cell $ne $ne$libresoc.v:43800$1100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr0_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43609$1060_Y
+ connect \Y $ne$libresoc.v:43800$1100_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540"
- cell $ne $ne$libresoc.v:43611$1062
+ cell $ne $ne$libresoc.v:43802$1102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr0_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43611$1062_Y
+ connect \Y $ne$libresoc.v:43802$1102_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541"
- cell $ne $ne$libresoc.v:43613$1064
+ cell $ne $ne$libresoc.v:43804$1104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sr0_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43613$1064_Y
+ connect \Y $ne$libresoc.v:43804$1104_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539"
- cell $ne $ne$libresoc.v:43619$1070
+ cell $ne $ne$libresoc.v:43810$1110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43619$1070_Y
+ connect \Y $ne$libresoc.v:43810$1110_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540"
- cell $ne $ne$libresoc.v:43621$1072
+ cell $ne $ne$libresoc.v:43812$1112
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43621$1072_Y
+ connect \Y $ne$libresoc.v:43812$1112_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541"
- cell $ne $ne$libresoc.v:43623$1074
+ cell $ne $ne$libresoc.v:43814$1114
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43623$1074_Y
+ connect \Y $ne$libresoc.v:43814$1114_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539"
- cell $ne $ne$libresoc.v:43631$1082
+ cell $ne $ne$libresoc.v:43822$1122
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43631$1082_Y
+ connect \Y $ne$libresoc.v:43822$1122_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540"
- cell $ne $ne$libresoc.v:43633$1084
+ cell $ne $ne$libresoc.v:43824$1124
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43633$1084_Y
+ connect \Y $ne$libresoc.v:43824$1124_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541"
- cell $ne $ne$libresoc.v:43635$1086
+ cell $ne $ne$libresoc.v:43826$1126
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43635$1086_Y
+ connect \Y $ne$libresoc.v:43826$1126_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539"
- cell $ne $ne$libresoc.v:43641$1092
+ cell $ne $ne$libresoc.v:43832$1132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43641$1092_Y
+ connect \Y $ne$libresoc.v:43832$1132_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540"
- cell $ne $ne$libresoc.v:43643$1094
+ cell $ne $ne$libresoc.v:43834$1134
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43643$1094_Y
+ connect \Y $ne$libresoc.v:43834$1134_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541"
- cell $ne $ne$libresoc.v:43645$1096
+ cell $ne $ne$libresoc.v:43836$1136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43645$1096_Y
+ connect \Y $ne$libresoc.v:43836$1136_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539"
- cell $ne $ne$libresoc.v:43652$1103
+ cell $ne $ne$libresoc.v:43843$1143
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43652$1103_Y
+ connect \Y $ne$libresoc.v:43843$1143_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540"
- cell $ne $ne$libresoc.v:43654$1105
+ cell $ne $ne$libresoc.v:43845$1145
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43654$1105_Y
+ connect \Y $ne$libresoc.v:43845$1145_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541"
- cell $ne $ne$libresoc.v:43656$1107
+ cell $ne $ne$libresoc.v:43847$1147
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_isir
connect \B 1'0
- connect \Y $ne$libresoc.v:43656$1107_Y
+ connect \Y $ne$libresoc.v:43847$1147_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553"
- cell $not $not$libresoc.v:43615$1066
+ cell $not $not$libresoc.v:43806$1106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sr0_update_core
- connect \Y $not$libresoc.v:43615$1066_Y
+ connect \Y $not$libresoc.v:43806$1106_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553"
- cell $not $not$libresoc.v:43625$1076
+ cell $not $not$libresoc.v:43816$1116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \jtag_wb_addrsr_update_core
- connect \Y $not$libresoc.v:43625$1076_Y
+ connect \Y $not$libresoc.v:43816$1116_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553"
- cell $not $not$libresoc.v:43637$1088
+ cell $not $not$libresoc.v:43828$1128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \jtag_wb_datasr_update_core
- connect \Y $not$libresoc.v:43637$1088_Y
+ connect \Y $not$libresoc.v:43828$1128_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553"
- cell $not $not$libresoc.v:43647$1098
+ cell $not $not$libresoc.v:43838$1138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi0_addrsr_update_core
- connect \Y $not$libresoc.v:43647$1098_Y
+ connect \Y $not$libresoc.v:43838$1138_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553"
- cell $not $not$libresoc.v:43658$1109
+ cell $not $not$libresoc.v:43849$1149
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dmi0_datasr_update_core
- connect \Y $not$libresoc.v:43658$1109_Y
+ connect \Y $not$libresoc.v:43849$1149_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229"
- cell $not $not$libresoc.v:43661$1112
+ cell $not $not$libresoc.v:43852$1152
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$256
- connect \Y $not$libresoc.v:43661$1112_Y
+ connect \Y $not$libresoc.v:43852$1152_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $or $or$libresoc.v:43595$1046
+ cell $or $or$libresoc.v:43786$1086
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \$11
- connect \Y $or$libresoc.v:43595$1046_Y
+ connect \Y $or$libresoc.v:43786$1086_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362"
- cell $or $or$libresoc.v:43599$1050
+ cell $or $or$libresoc.v:43790$1090
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$141
connect \B \$143
- connect \Y $or$libresoc.v:43599$1050_Y
+ connect \Y $or$libresoc.v:43790$1090_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $or $or$libresoc.v:43603$1054
+ cell $or $or$libresoc.v:43794$1094
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$149
connect \B \$151
- connect \Y $or$libresoc.v:43603$1054_Y
+ connect \Y $or$libresoc.v:43794$1094_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380"
- cell $or $or$libresoc.v:43605$1056
+ cell $or $or$libresoc.v:43796$1096
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$153
connect \B \$155
- connect \Y $or$libresoc.v:43605$1056_Y
+ connect \Y $or$libresoc.v:43796$1096_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380"
- cell $or $or$libresoc.v:43617$1068
+ cell $or $or$libresoc.v:43808$1108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$13
connect \B \$15
- connect \Y $or$libresoc.v:43617$1068_Y
+ connect \Y $or$libresoc.v:43808$1108_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230"
- cell $or $or$libresoc.v:43665$1116
+ cell $or $or$libresoc.v:43856$1156
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$259
connect \B \$261
- connect \Y $or$libresoc.v:43665$1116_Y
+ connect \Y $or$libresoc.v:43856$1156_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $or $or$libresoc.v:43672$1124
+ cell $or $or$libresoc.v:43863$1164
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$23
connect \B \$25
- connect \Y $or$libresoc.v:43672$1124_Y
+ connect \Y $or$libresoc.v:43863$1164_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182"
- cell $or $or$libresoc.v:43673$1125
+ cell $or $or$libresoc.v:43864$1165
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$276
connect \B \$278
- connect \Y $or$libresoc.v:43673$1125_Y
+ connect \Y $or$libresoc.v:43864$1165_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380"
- cell $or $or$libresoc.v:43678$1130
+ cell $or $or$libresoc.v:43869$1170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$27
connect \B \$29
- connect \Y $or$libresoc.v:43678$1130_Y
+ connect \Y $or$libresoc.v:43869$1170_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
- cell $or $or$libresoc.v:43693$1145
+ cell $or $or$libresoc.v:43884$1185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$1
connect \B \$3
- connect \Y $or$libresoc.v:43693$1145_Y
+ connect \Y $or$libresoc.v:43884$1185_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57"
- cell $pos $pos$libresoc.v:43669$1121
+ cell $pos $pos$libresoc.v:43860$1161
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $extend$libresoc.v:43669$1120_Y
- connect \Y $pos$libresoc.v:43669$1121_Y
+ connect \A $extend$libresoc.v:43860$1160_Y
+ connect \Y $pos$libresoc.v:43860$1161_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43574$1025
+ cell $mux $ternary$libresoc.v:43765$1065
parameter \WIDTH 1
connect \A \gpio_gpio9__pad__i
connect \B \io_bd [29]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43574$1025_Y
+ connect \Y $ternary$libresoc.v:43765$1065_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43575$1026
+ cell $mux $ternary$libresoc.v:43766$1066
parameter \WIDTH 1
connect \A \gpio_gpio9__core__o
connect \B \io_bd [30]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43575$1026_Y
+ connect \Y $ternary$libresoc.v:43766$1066_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43576$1027
+ cell $mux $ternary$libresoc.v:43767$1067
parameter \WIDTH 1
connect \A \gpio_gpio9__core__oe
connect \B \io_bd [31]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43576$1027_Y
+ connect \Y $ternary$libresoc.v:43767$1067_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43577$1028
+ cell $mux $ternary$libresoc.v:43768$1068
parameter \WIDTH 1
connect \A \gpio_gpio10__pad__i
connect \B \io_bd [32]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43577$1028_Y
+ connect \Y $ternary$libresoc.v:43768$1068_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43578$1029
+ cell $mux $ternary$libresoc.v:43769$1069
parameter \WIDTH 1
connect \A \gpio_gpio10__core__o
connect \B \io_bd [33]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43578$1029_Y
+ connect \Y $ternary$libresoc.v:43769$1069_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43579$1030
+ cell $mux $ternary$libresoc.v:43770$1070
parameter \WIDTH 1
connect \A \gpio_gpio10__core__oe
connect \B \io_bd [34]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43579$1030_Y
+ connect \Y $ternary$libresoc.v:43770$1070_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43580$1031
+ cell $mux $ternary$libresoc.v:43771$1071
parameter \WIDTH 1
connect \A \gpio_gpio11__pad__i
connect \B \io_bd [35]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43580$1031_Y
+ connect \Y $ternary$libresoc.v:43771$1071_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43581$1032
+ cell $mux $ternary$libresoc.v:43772$1072
parameter \WIDTH 1
connect \A \gpio_gpio11__core__o
connect \B \io_bd [36]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43581$1032_Y
+ connect \Y $ternary$libresoc.v:43772$1072_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43582$1033
+ cell $mux $ternary$libresoc.v:43773$1073
parameter \WIDTH 1
connect \A \gpio_gpio11__core__oe
connect \B \io_bd [37]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43582$1033_Y
+ connect \Y $ternary$libresoc.v:43773$1073_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43583$1034
+ cell $mux $ternary$libresoc.v:43774$1074
parameter \WIDTH 1
connect \A \gpio_gpio12__pad__i
connect \B \io_bd [38]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43583$1034_Y
+ connect \Y $ternary$libresoc.v:43774$1074_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43585$1036
+ cell $mux $ternary$libresoc.v:43776$1076
parameter \WIDTH 1
connect \A \gpio_gpio12__core__o
connect \B \io_bd [39]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43585$1036_Y
+ connect \Y $ternary$libresoc.v:43776$1076_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43586$1037
+ cell $mux $ternary$libresoc.v:43777$1077
parameter \WIDTH 1
connect \A \gpio_gpio12__core__oe
connect \B \io_bd [40]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43586$1037_Y
+ connect \Y $ternary$libresoc.v:43777$1077_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43587$1038
+ cell $mux $ternary$libresoc.v:43778$1078
parameter \WIDTH 1
connect \A \gpio_gpio13__pad__i
connect \B \io_bd [41]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43587$1038_Y
+ connect \Y $ternary$libresoc.v:43778$1078_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43588$1039
+ cell $mux $ternary$libresoc.v:43779$1079
parameter \WIDTH 1
connect \A \gpio_gpio13__core__o
connect \B \io_bd [42]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43588$1039_Y
+ connect \Y $ternary$libresoc.v:43779$1079_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43589$1040
+ cell $mux $ternary$libresoc.v:43780$1080
parameter \WIDTH 1
connect \A \gpio_gpio13__core__oe
connect \B \io_bd [43]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43589$1040_Y
+ connect \Y $ternary$libresoc.v:43780$1080_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43590$1041
+ cell $mux $ternary$libresoc.v:43781$1081
parameter \WIDTH 1
connect \A \gpio_gpio14__pad__i
connect \B \io_bd [44]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43590$1041_Y
+ connect \Y $ternary$libresoc.v:43781$1081_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43591$1042
+ cell $mux $ternary$libresoc.v:43782$1082
parameter \WIDTH 1
connect \A \gpio_gpio14__core__o
connect \B \io_bd [45]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43591$1042_Y
+ connect \Y $ternary$libresoc.v:43782$1082_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43592$1043
+ cell $mux $ternary$libresoc.v:43783$1083
parameter \WIDTH 1
connect \A \gpio_gpio14__core__oe
connect \B \io_bd [46]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43592$1043_Y
+ connect \Y $ternary$libresoc.v:43783$1083_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43593$1044
+ cell $mux $ternary$libresoc.v:43784$1084
parameter \WIDTH 1
connect \A \gpio_gpio15__pad__i
connect \B \io_bd [47]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43593$1044_Y
+ connect \Y $ternary$libresoc.v:43784$1084_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43594$1045
+ cell $mux $ternary$libresoc.v:43785$1085
parameter \WIDTH 1
connect \A \gpio_gpio15__core__o
connect \B \io_bd [48]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43594$1045_Y
+ connect \Y $ternary$libresoc.v:43785$1085_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43596$1047
+ cell $mux $ternary$libresoc.v:43787$1087
parameter \WIDTH 1
connect \A \gpio_gpio15__core__oe
connect \B \io_bd [49]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43596$1047_Y
+ connect \Y $ternary$libresoc.v:43787$1087_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:475"
- cell $mux $ternary$libresoc.v:43684$1136
+ cell $mux $ternary$libresoc.v:43875$1176
parameter \WIDTH 1
connect \A \uart_tx__core__o
connect \B \io_bd [0]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43684$1136_Y
+ connect \Y $ternary$libresoc.v:43875$1176_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:472"
- cell $mux $ternary$libresoc.v:43685$1137
+ cell $mux $ternary$libresoc.v:43876$1177
parameter \WIDTH 1
connect \A \uart_rx__pad__i
connect \B \io_bd [1]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43685$1137_Y
+ connect \Y $ternary$libresoc.v:43876$1177_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43686$1138
+ cell $mux $ternary$libresoc.v:43877$1178
parameter \WIDTH 1
connect \A \gpio_gpio0__pad__i
connect \B \io_bd [2]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43686$1138_Y
+ connect \Y $ternary$libresoc.v:43877$1178_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43687$1139
+ cell $mux $ternary$libresoc.v:43878$1179
parameter \WIDTH 1
connect \A \gpio_gpio0__core__o
connect \B \io_bd [3]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43687$1139_Y
+ connect \Y $ternary$libresoc.v:43878$1179_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43688$1140
+ cell $mux $ternary$libresoc.v:43879$1180
parameter \WIDTH 1
connect \A \gpio_gpio0__core__oe
connect \B \io_bd [4]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43688$1140_Y
+ connect \Y $ternary$libresoc.v:43879$1180_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43689$1141
+ cell $mux $ternary$libresoc.v:43880$1181
parameter \WIDTH 1
connect \A \gpio_gpio1__pad__i
connect \B \io_bd [5]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43689$1141_Y
+ connect \Y $ternary$libresoc.v:43880$1181_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43690$1142
+ cell $mux $ternary$libresoc.v:43881$1182
parameter \WIDTH 1
connect \A \gpio_gpio1__core__o
connect \B \io_bd [6]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43690$1142_Y
+ connect \Y $ternary$libresoc.v:43881$1182_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43691$1143
+ cell $mux $ternary$libresoc.v:43882$1183
parameter \WIDTH 1
connect \A \gpio_gpio1__core__oe
connect \B \io_bd [7]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43691$1143_Y
+ connect \Y $ternary$libresoc.v:43882$1183_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43692$1144
+ cell $mux $ternary$libresoc.v:43883$1184
parameter \WIDTH 1
connect \A \gpio_gpio2__pad__i
connect \B \io_bd [8]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43692$1144_Y
+ connect \Y $ternary$libresoc.v:43883$1184_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43694$1146
+ cell $mux $ternary$libresoc.v:43885$1186
parameter \WIDTH 1
connect \A \gpio_gpio2__core__o
connect \B \io_bd [9]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43694$1146_Y
+ connect \Y $ternary$libresoc.v:43885$1186_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43695$1147
+ cell $mux $ternary$libresoc.v:43886$1187
parameter \WIDTH 1
connect \A \gpio_gpio2__core__oe
connect \B \io_bd [10]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43695$1147_Y
+ connect \Y $ternary$libresoc.v:43886$1187_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43696$1148
+ cell $mux $ternary$libresoc.v:43887$1188
parameter \WIDTH 1
connect \A \gpio_gpio3__pad__i
connect \B \io_bd [11]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43696$1148_Y
+ connect \Y $ternary$libresoc.v:43887$1188_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43697$1149
+ cell $mux $ternary$libresoc.v:43888$1189
parameter \WIDTH 1
connect \A \gpio_gpio3__core__o
connect \B \io_bd [12]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43697$1149_Y
+ connect \Y $ternary$libresoc.v:43888$1189_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43698$1150
+ cell $mux $ternary$libresoc.v:43889$1190
parameter \WIDTH 1
connect \A \gpio_gpio3__core__oe
connect \B \io_bd [13]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43698$1150_Y
+ connect \Y $ternary$libresoc.v:43889$1190_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43699$1151
+ cell $mux $ternary$libresoc.v:43890$1191
parameter \WIDTH 1
connect \A \gpio_gpio4__pad__i
connect \B \io_bd [14]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43699$1151_Y
+ connect \Y $ternary$libresoc.v:43890$1191_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43700$1152
+ cell $mux $ternary$libresoc.v:43891$1192
parameter \WIDTH 1
connect \A \gpio_gpio4__core__o
connect \B \io_bd [15]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43700$1152_Y
+ connect \Y $ternary$libresoc.v:43891$1192_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43701$1153
+ cell $mux $ternary$libresoc.v:43892$1193
parameter \WIDTH 1
connect \A \gpio_gpio4__core__oe
connect \B \io_bd [16]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43701$1153_Y
+ connect \Y $ternary$libresoc.v:43892$1193_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43702$1154
+ cell $mux $ternary$libresoc.v:43893$1194
parameter \WIDTH 1
connect \A \gpio_gpio5__pad__i
connect \B \io_bd [17]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43702$1154_Y
+ connect \Y $ternary$libresoc.v:43893$1194_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43703$1155
+ cell $mux $ternary$libresoc.v:43894$1195
parameter \WIDTH 1
connect \A \gpio_gpio5__core__o
connect \B \io_bd [18]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43703$1155_Y
+ connect \Y $ternary$libresoc.v:43894$1195_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43705$1157
+ cell $mux $ternary$libresoc.v:43896$1197
parameter \WIDTH 1
connect \A \gpio_gpio5__core__oe
connect \B \io_bd [19]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43705$1157_Y
+ connect \Y $ternary$libresoc.v:43896$1197_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43706$1158
+ cell $mux $ternary$libresoc.v:43897$1198
parameter \WIDTH 1
connect \A \gpio_gpio6__pad__i
connect \B \io_bd [20]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43706$1158_Y
+ connect \Y $ternary$libresoc.v:43897$1198_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43707$1159
+ cell $mux $ternary$libresoc.v:43898$1199
parameter \WIDTH 1
connect \A \gpio_gpio6__core__o
connect \B \io_bd [21]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43707$1159_Y
+ connect \Y $ternary$libresoc.v:43898$1199_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43708$1160
+ cell $mux $ternary$libresoc.v:43899$1200
parameter \WIDTH 1
connect \A \gpio_gpio6__core__oe
connect \B \io_bd [22]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43708$1160_Y
+ connect \Y $ternary$libresoc.v:43899$1200_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43709$1161
+ cell $mux $ternary$libresoc.v:43900$1201
parameter \WIDTH 1
connect \A \gpio_gpio7__pad__i
connect \B \io_bd [23]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43709$1161_Y
+ connect \Y $ternary$libresoc.v:43900$1201_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43710$1162
+ cell $mux $ternary$libresoc.v:43901$1202
parameter \WIDTH 1
connect \A \gpio_gpio7__core__o
connect \B \io_bd [24]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43710$1162_Y
+ connect \Y $ternary$libresoc.v:43901$1202_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43711$1163
+ cell $mux $ternary$libresoc.v:43902$1203
parameter \WIDTH 1
connect \A \gpio_gpio7__core__oe
connect \B \io_bd [25]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43711$1163_Y
+ connect \Y $ternary$libresoc.v:43902$1203_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
- cell $mux $ternary$libresoc.v:43712$1164
+ cell $mux $ternary$libresoc.v:43903$1204
parameter \WIDTH 1
connect \A \gpio_gpio8__pad__i
connect \B \io_bd [26]
connect \S \io_bd2core
- connect \Y $ternary$libresoc.v:43712$1164_Y
+ connect \Y $ternary$libresoc.v:43903$1204_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486"
- cell $mux $ternary$libresoc.v:43713$1165
+ cell $mux $ternary$libresoc.v:43904$1205
parameter \WIDTH 1
connect \A \gpio_gpio8__core__o
connect \B \io_bd [27]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43713$1165_Y
+ connect \Y $ternary$libresoc.v:43904$1205_Y
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487"
- cell $mux $ternary$libresoc.v:43714$1166
+ cell $mux $ternary$libresoc.v:43905$1206
parameter \WIDTH 1
connect \A \gpio_gpio8__core__oe
connect \B \io_bd [28]
connect \S \io_bd2io
- connect \Y $ternary$libresoc.v:43714$1166_Y
+ connect \Y $ternary$libresoc.v:43905$1206_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43775.8-43787.4"
+ attribute \src "libresoc.v:43966.8-43978.4"
cell \_fsm \_fsm
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tms \TAP_bus__tms
connect \update \_fsm_update
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43788.12-43798.4"
+ attribute \src "libresoc.v:43979.12-43989.4"
cell \_idblock \_idblock
connect \TAP_bus__tdi \TAP_bus__tdi
connect \TAP_id_tdo \_idblock_TAP_id_tdo
connect \update \_fsm_update
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:43799.12-43809.4"
+ attribute \src "libresoc.v:43990.12-44000.4"
cell \_irblock \_irblock
connect \TAP_bus__tdi \TAP_bus__tdi
connect \capture \_fsm_capture
connect \tdo \_irblock_tdo
connect \update \_fsm_update
end
- attribute \src "libresoc.v:42831.7-42831.20"
- process $proc$libresoc.v:42831$1329
+ attribute \src "libresoc.v:43022.7-43022.20"
+ process $proc$libresoc.v:43022$1369
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:43157.13-43157.31"
- process $proc$libresoc.v:43157$1330
+ attribute \src "libresoc.v:43346.13-43346.31"
+ process $proc$libresoc.v:43346$1370
assign { } { }
assign $1\dmi0_addr_i[3:0] 4'0000
sync always
sync init
update \dmi0_addr_i $1\dmi0_addr_i[3:0]
end
- attribute \src "libresoc.v:43165.7-43165.29"
- process $proc$libresoc.v:43165$1331
+ attribute \src "libresoc.v:43354.7-43354.29"
+ process $proc$libresoc.v:43354$1371
assign { } { }
assign $1\dmi0_addrsr__oe[0:0] 1'0
sync always
sync init
update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0]
end
- attribute \src "libresoc.v:43173.13-43173.36"
- process $proc$libresoc.v:43173$1332
+ attribute \src "libresoc.v:43362.13-43362.36"
+ process $proc$libresoc.v:43362$1372
assign { } { }
assign $1\dmi0_addrsr_reg[7:0] 8'00000000
sync always
sync init
update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0]
end
- attribute \src "libresoc.v:43181.7-43181.37"
- process $proc$libresoc.v:43181$1333
+ attribute \src "libresoc.v:43370.7-43370.37"
+ process $proc$libresoc.v:43370$1373
assign { } { }
assign $1\dmi0_addrsr_update_core[0:0] 1'0
sync always
sync init
update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0]
end
- attribute \src "libresoc.v:43185.7-43185.42"
- process $proc$libresoc.v:43185$1334
+ attribute \src "libresoc.v:43374.7-43374.42"
+ process $proc$libresoc.v:43374$1374
assign { } { }
assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0
sync always
sync init
update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:43189.14-43189.51"
- process $proc$libresoc.v:43189$1335
+ attribute \src "libresoc.v:43378.14-43378.51"
+ process $proc$libresoc.v:43378$1375
assign { } { }
assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dmi0_datasr__i $1\dmi0_datasr__i[63:0]
end
- attribute \src "libresoc.v:43195.13-43195.35"
- process $proc$libresoc.v:43195$1336
+ attribute \src "libresoc.v:43384.13-43384.35"
+ process $proc$libresoc.v:43384$1376
assign { } { }
assign $1\dmi0_datasr__oe[1:0] 2'00
sync always
sync init
update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0]
end
- attribute \src "libresoc.v:43203.14-43203.52"
- process $proc$libresoc.v:43203$1337
+ attribute \src "libresoc.v:43392.14-43392.52"
+ process $proc$libresoc.v:43392$1377
assign { } { }
assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0]
end
- attribute \src "libresoc.v:43211.7-43211.37"
- process $proc$libresoc.v:43211$1338
+ attribute \src "libresoc.v:43400.7-43400.37"
+ process $proc$libresoc.v:43400$1378
assign { } { }
assign $1\dmi0_datasr_update_core[0:0] 1'0
sync always
sync init
update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0]
end
- attribute \src "libresoc.v:43215.7-43215.42"
- process $proc$libresoc.v:43215$1339
+ attribute \src "libresoc.v:43404.7-43404.42"
+ process $proc$libresoc.v:43404$1379
assign { } { }
assign $1\dmi0_datasr_update_core_prev[0:0] 1'0
sync always
sync init
update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:43220.14-43220.45"
- process $proc$libresoc.v:43220$1340
+ attribute \src "libresoc.v:43409.14-43409.45"
+ process $proc$libresoc.v:43409$1380
assign { } { }
assign $1\dmi0_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dmi0_din $1\dmi0_din[63:0]
end
- attribute \src "libresoc.v:43230.13-43230.29"
- process $proc$libresoc.v:43230$1341
+ attribute \src "libresoc.v:43419.13-43419.29"
+ process $proc$libresoc.v:43419$1381
assign { } { }
assign $1\fsm_state[2:0] 3'000
sync always
sync init
update \fsm_state $1\fsm_state[2:0]
end
- attribute \src "libresoc.v:43232.13-43232.35"
- process $proc$libresoc.v:43232$1342
+ attribute \src "libresoc.v:43421.13-43421.35"
+ process $proc$libresoc.v:43421$1382
assign { } { }
- assign $0\fsm_state$275[2:0]$1343 3'000
+ assign $0\fsm_state$275[2:0]$1383 3'000
sync always
sync init
- update \fsm_state$275 $0\fsm_state$275[2:0]$1343
+ update \fsm_state$275 $0\fsm_state$275[2:0]$1383
end
- attribute \src "libresoc.v:43430.14-43430.39"
- process $proc$libresoc.v:43430$1344
+ attribute \src "libresoc.v:43623.14-43623.39"
+ process $proc$libresoc.v:43623$1384
assign { } { }
assign $1\io_bd[49:0] 50'00000000000000000000000000000000000000000000000000
sync always
sync init
update \io_bd $1\io_bd[49:0]
end
- attribute \src "libresoc.v:43442.14-43442.39"
- process $proc$libresoc.v:43442$1345
+ attribute \src "libresoc.v:43635.14-43635.39"
+ process $proc$libresoc.v:43635$1385
assign { } { }
assign $1\io_sr[49:0] 50'00000000000000000000000000000000000000000000000000
sync always
sync init
update \io_sr $1\io_sr[49:0]
end
- attribute \src "libresoc.v:43451.14-43451.41"
- process $proc$libresoc.v:43451$1346
+ attribute \src "libresoc.v:43644.14-43644.41"
+ process $proc$libresoc.v:43644$1386
assign { } { }
assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000
sync always
sync init
update \jtag_wb__adr $1\jtag_wb__adr[28:0]
end
- attribute \src "libresoc.v:43460.14-43460.51"
- process $proc$libresoc.v:43460$1347
+ attribute \src "libresoc.v:43653.14-43653.51"
+ process $proc$libresoc.v:43653$1387
assign { } { }
assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0]
end
- attribute \src "libresoc.v:43474.7-43474.32"
- process $proc$libresoc.v:43474$1348
+ attribute \src "libresoc.v:43667.7-43667.32"
+ process $proc$libresoc.v:43667$1388
assign { } { }
assign $1\jtag_wb_addrsr__oe[0:0] 1'0
sync always
sync init
update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0]
end
- attribute \src "libresoc.v:43482.14-43482.47"
- process $proc$libresoc.v:43482$1349
+ attribute \src "libresoc.v:43675.14-43675.47"
+ process $proc$libresoc.v:43675$1389
assign { } { }
assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000
sync always
sync init
update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0]
end
- attribute \src "libresoc.v:43490.7-43490.40"
- process $proc$libresoc.v:43490$1350
+ attribute \src "libresoc.v:43683.7-43683.40"
+ process $proc$libresoc.v:43683$1390
assign { } { }
assign $1\jtag_wb_addrsr_update_core[0:0] 1'0
sync always
sync init
update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0]
end
- attribute \src "libresoc.v:43494.7-43494.45"
- process $proc$libresoc.v:43494$1351
+ attribute \src "libresoc.v:43687.7-43687.45"
+ process $proc$libresoc.v:43687$1391
assign { } { }
assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0
sync always
sync init
update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:43498.14-43498.54"
- process $proc$libresoc.v:43498$1352
+ attribute \src "libresoc.v:43691.14-43691.54"
+ process $proc$libresoc.v:43691$1392
assign { } { }
assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0]
end
- attribute \src "libresoc.v:43504.13-43504.38"
- process $proc$libresoc.v:43504$1353
+ attribute \src "libresoc.v:43697.13-43697.38"
+ process $proc$libresoc.v:43697$1393
assign { } { }
assign $1\jtag_wb_datasr__oe[1:0] 2'00
sync always
sync init
update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0]
end
- attribute \src "libresoc.v:43512.14-43512.55"
- process $proc$libresoc.v:43512$1354
+ attribute \src "libresoc.v:43705.14-43705.55"
+ process $proc$libresoc.v:43705$1394
assign { } { }
assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0]
end
- attribute \src "libresoc.v:43520.7-43520.40"
- process $proc$libresoc.v:43520$1355
+ attribute \src "libresoc.v:43713.7-43713.40"
+ process $proc$libresoc.v:43713$1395
assign { } { }
assign $1\jtag_wb_datasr_update_core[0:0] 1'0
sync always
sync init
update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0]
end
- attribute \src "libresoc.v:43524.7-43524.45"
- process $proc$libresoc.v:43524$1356
+ attribute \src "libresoc.v:43717.7-43717.45"
+ process $proc$libresoc.v:43717$1396
assign { } { }
assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0
sync always
sync init
update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:43542.7-43542.21"
- process $proc$libresoc.v:43542$1357
+ attribute \src "libresoc.v:43733.7-43733.21"
+ process $proc$libresoc.v:43733$1397
assign { } { }
assign $1\sr0__oe[0:0] 1'0
sync always
sync init
update \sr0__oe $1\sr0__oe[0:0]
end
- attribute \src "libresoc.v:43550.13-43550.27"
- process $proc$libresoc.v:43550$1358
+ attribute \src "libresoc.v:43741.13-43741.27"
+ process $proc$libresoc.v:43741$1398
assign { } { }
assign $1\sr0_reg[2:0] 3'000
sync always
sync init
update \sr0_reg $1\sr0_reg[2:0]
end
- attribute \src "libresoc.v:43558.7-43558.29"
- process $proc$libresoc.v:43558$1359
+ attribute \src "libresoc.v:43749.7-43749.29"
+ process $proc$libresoc.v:43749$1399
assign { } { }
assign $1\sr0_update_core[0:0] 1'0
sync always
sync init
update \sr0_update_core $1\sr0_update_core[0:0]
end
- attribute \src "libresoc.v:43562.7-43562.34"
- process $proc$libresoc.v:43562$1360
+ attribute \src "libresoc.v:43753.7-43753.34"
+ process $proc$libresoc.v:43753$1400
assign { } { }
assign $1\sr0_update_core_prev[0:0] 1'0
sync always
sync init
update \sr0_update_core_prev $1\sr0_update_core_prev[0:0]
end
- attribute \src "libresoc.v:43715.3-43716.45"
- process $proc$libresoc.v:43715$1167
+ attribute \src "libresoc.v:43906.3-43907.45"
+ process $proc$libresoc.v:43906$1207
assign { } { }
assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dmi0_datasr__i $0\dmi0_datasr__i[63:0]
end
- attribute \src "libresoc.v:43717.3-43718.33"
- process $proc$libresoc.v:43717$1168
+ attribute \src "libresoc.v:43908.3-43909.33"
+ process $proc$libresoc.v:43908$1208
assign { } { }
assign $0\dmi0_din[63:0] \dmi0_din$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dmi0_din $0\dmi0_din[63:0]
end
- attribute \src "libresoc.v:43719.3-43720.45"
- process $proc$libresoc.v:43719$1169
+ attribute \src "libresoc.v:43910.3-43911.45"
+ process $proc$libresoc.v:43910$1209
assign { } { }
- assign $0\fsm_state$275[2:0]$1170 \fsm_state$275$next
- sync posedge \clk
- update \fsm_state$275 $0\fsm_state$275[2:0]$1170
+ assign $0\fsm_state$275[2:0]$1210 \fsm_state$275$next
+ sync posedge \intclk_clk
+ update \fsm_state$275 $0\fsm_state$275[2:0]$1210
end
- attribute \src "libresoc.v:43721.3-43722.39"
- process $proc$libresoc.v:43721$1171
+ attribute \src "libresoc.v:43912.3-43913.39"
+ process $proc$libresoc.v:43912$1211
assign { } { }
assign $0\dmi0_addr_i[3:0] \dmi0_addr_i$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dmi0_addr_i $0\dmi0_addr_i[3:0]
end
- attribute \src "libresoc.v:43723.3-43724.51"
- process $proc$libresoc.v:43723$1172
+ attribute \src "libresoc.v:43914.3-43915.51"
+ process $proc$libresoc.v:43914$1212
assign { } { }
assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0]
end
- attribute \src "libresoc.v:43725.3-43726.45"
- process $proc$libresoc.v:43725$1173
+ attribute \src "libresoc.v:43916.3-43917.45"
+ process $proc$libresoc.v:43916$1213
assign { } { }
assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0]
end
- attribute \src "libresoc.v:43727.3-43728.35"
- process $proc$libresoc.v:43727$1174
+ attribute \src "libresoc.v:43918.3-43919.35"
+ process $proc$libresoc.v:43918$1214
assign { } { }
assign $0\fsm_state[2:0] \fsm_state$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \fsm_state $0\fsm_state[2:0]
end
- attribute \src "libresoc.v:43729.3-43730.41"
- process $proc$libresoc.v:43729$1175
+ attribute \src "libresoc.v:43920.3-43921.41"
+ process $proc$libresoc.v:43920$1215
assign { } { }
assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \jtag_wb__adr $0\jtag_wb__adr[28:0]
end
- attribute \src "libresoc.v:43731.3-43732.47"
- process $proc$libresoc.v:43731$1176
+ attribute \src "libresoc.v:43922.3-43923.47"
+ process $proc$libresoc.v:43922$1216
assign { } { }
assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next
sync posedge \posjtag_clk
update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0]
end
- attribute \src "libresoc.v:43733.3-43734.47"
- process $proc$libresoc.v:43733$1177
+ attribute \src "libresoc.v:43924.3-43925.47"
+ process $proc$libresoc.v:43924$1217
assign { } { }
assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0]
end
- attribute \src "libresoc.v:43735.3-43736.73"
- process $proc$libresoc.v:43735$1178
+ attribute \src "libresoc.v:43926.3-43927.73"
+ process $proc$libresoc.v:43926$1218
assign { } { }
assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:43737.3-43738.63"
- process $proc$libresoc.v:43737$1179
+ attribute \src "libresoc.v:43928.3-43929.63"
+ process $proc$libresoc.v:43928$1219
assign { } { }
assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0]
end
- attribute \src "libresoc.v:43739.3-43740.47"
- process $proc$libresoc.v:43739$1180
+ attribute \src "libresoc.v:43930.3-43931.47"
+ process $proc$libresoc.v:43930$1220
assign { } { }
assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next
sync posedge \posjtag_clk
update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0]
end
- attribute \src "libresoc.v:43741.3-43742.47"
- process $proc$libresoc.v:43741$1181
+ attribute \src "libresoc.v:43932.3-43933.47"
+ process $proc$libresoc.v:43932$1221
assign { } { }
assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0]
end
- attribute \src "libresoc.v:43743.3-43744.73"
- process $proc$libresoc.v:43743$1182
+ attribute \src "libresoc.v:43934.3-43935.73"
+ process $proc$libresoc.v:43934$1222
assign { } { }
assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:43745.3-43746.63"
- process $proc$libresoc.v:43745$1183
+ attribute \src "libresoc.v:43936.3-43937.63"
+ process $proc$libresoc.v:43936$1223
assign { } { }
assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0]
end
- attribute \src "libresoc.v:43747.3-43748.53"
- process $proc$libresoc.v:43747$1184
+ attribute \src "libresoc.v:43938.3-43939.53"
+ process $proc$libresoc.v:43938$1224
assign { } { }
assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next
sync posedge \posjtag_clk
update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0]
end
- attribute \src "libresoc.v:43749.3-43750.53"
- process $proc$libresoc.v:43749$1185
+ attribute \src "libresoc.v:43940.3-43941.53"
+ process $proc$libresoc.v:43940$1225
assign { } { }
assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0]
end
- attribute \src "libresoc.v:43751.3-43752.79"
- process $proc$libresoc.v:43751$1186
+ attribute \src "libresoc.v:43942.3-43943.79"
+ process $proc$libresoc.v:43942$1226
assign { } { }
assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:43753.3-43754.69"
- process $proc$libresoc.v:43753$1187
+ attribute \src "libresoc.v:43944.3-43945.69"
+ process $proc$libresoc.v:43944$1227
assign { } { }
assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0]
end
- attribute \src "libresoc.v:43755.3-43756.53"
- process $proc$libresoc.v:43755$1188
+ attribute \src "libresoc.v:43946.3-43947.53"
+ process $proc$libresoc.v:43946$1228
assign { } { }
assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next
sync posedge \posjtag_clk
update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0]
end
- attribute \src "libresoc.v:43757.3-43758.53"
- process $proc$libresoc.v:43757$1189
+ attribute \src "libresoc.v:43948.3-43949.53"
+ process $proc$libresoc.v:43948$1229
assign { } { }
assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0]
end
- attribute \src "libresoc.v:43759.3-43760.79"
- process $proc$libresoc.v:43759$1190
+ attribute \src "libresoc.v:43950.3-43951.79"
+ process $proc$libresoc.v:43950$1230
assign { } { }
assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0]
end
- attribute \src "libresoc.v:43761.3-43762.69"
- process $proc$libresoc.v:43761$1191
+ attribute \src "libresoc.v:43952.3-43953.69"
+ process $proc$libresoc.v:43952$1231
assign { } { }
assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0]
end
- attribute \src "libresoc.v:43763.3-43764.31"
- process $proc$libresoc.v:43763$1192
+ attribute \src "libresoc.v:43954.3-43955.31"
+ process $proc$libresoc.v:43954$1232
assign { } { }
assign $0\sr0_reg[2:0] \sr0_reg$next
sync posedge \posjtag_clk
update \sr0_reg $0\sr0_reg[2:0]
end
- attribute \src "libresoc.v:43765.3-43766.31"
- process $proc$libresoc.v:43765$1193
+ attribute \src "libresoc.v:43956.3-43957.31"
+ process $proc$libresoc.v:43956$1233
assign { } { }
assign $0\sr0__oe[0:0] \sr0__oe$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \sr0__oe $0\sr0__oe[0:0]
end
- attribute \src "libresoc.v:43767.3-43768.57"
- process $proc$libresoc.v:43767$1194
+ attribute \src "libresoc.v:43958.3-43959.57"
+ process $proc$libresoc.v:43958$1234
assign { } { }
assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \sr0_update_core_prev $0\sr0_update_core_prev[0:0]
end
- attribute \src "libresoc.v:43769.3-43770.47"
- process $proc$libresoc.v:43769$1195
+ attribute \src "libresoc.v:43960.3-43961.47"
+ process $proc$libresoc.v:43960$1235
assign { } { }
assign $0\sr0_update_core[0:0] \sr0_update_core$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \sr0_update_core $0\sr0_update_core[0:0]
end
- attribute \src "libresoc.v:43771.3-43772.27"
- process $proc$libresoc.v:43771$1196
+ attribute \src "libresoc.v:43962.3-43963.27"
+ process $proc$libresoc.v:43962$1236
assign { } { }
assign $0\io_bd[49:0] \io_bd$next
sync negedge \negjtag_clk
update \io_bd $0\io_bd[49:0]
end
- attribute \src "libresoc.v:43773.3-43774.27"
- process $proc$libresoc.v:43773$1197
+ attribute \src "libresoc.v:43964.3-43965.27"
+ process $proc$libresoc.v:43964$1237
assign { } { }
assign $0\io_sr[49:0] \io_sr$next
sync posedge \posjtag_clk
update \io_sr $0\io_sr[49:0]
end
- attribute \src "libresoc.v:43810.3-43818.6"
- process $proc$libresoc.v:43810$1198
+ attribute \src "libresoc.v:44001.3-44009.6"
+ process $proc$libresoc.v:44001$1238
assign { } { }
assign { } { }
- assign $0\dmi0_datasr_update_core_prev$next[0:0]$1199 $1\dmi0_datasr_update_core_prev$next[0:0]$1200
- attribute \src "libresoc.v:43811.5-43811.29"
+ assign $0\dmi0_datasr_update_core_prev$next[0:0]$1239 $1\dmi0_datasr_update_core_prev$next[0:0]$1240
+ attribute \src "libresoc.v:44002.5-44002.29"
switch \initial
- attribute \src "libresoc.v:43811.9-43811.17"
+ attribute \src "libresoc.v:44002.9-44002.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_datasr_update_core_prev$next[0:0]$1200 1'0
+ assign $1\dmi0_datasr_update_core_prev$next[0:0]$1240 1'0
case
- assign $1\dmi0_datasr_update_core_prev$next[0:0]$1200 \dmi0_datasr_update_core
+ assign $1\dmi0_datasr_update_core_prev$next[0:0]$1240 \dmi0_datasr_update_core
end
sync always
- update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$1199
+ update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$1239
end
- attribute \src "libresoc.v:43819.3-43835.6"
- process $proc$libresoc.v:43819$1201
+ attribute \src "libresoc.v:44010.3-44026.6"
+ process $proc$libresoc.v:44010$1241
assign { } { }
assign { } { }
- assign $0\dmi0_datasr__oe$next[1:0]$1202 $2\dmi0_datasr__oe$next[1:0]$1204
- attribute \src "libresoc.v:43820.5-43820.29"
+ assign $0\dmi0_datasr__oe$next[1:0]$1242 $2\dmi0_datasr__oe$next[1:0]$1244
+ attribute \src "libresoc.v:44011.5-44011.29"
switch \initial
- attribute \src "libresoc.v:43820.9-43820.17"
+ attribute \src "libresoc.v:44011.9-44011.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_datasr__oe$next[1:0]$1203 \dmi0_datasr_isir
+ assign $1\dmi0_datasr__oe$next[1:0]$1243 \dmi0_datasr_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\dmi0_datasr__oe$next[1:0]$1203 2'00
+ assign $1\dmi0_datasr__oe$next[1:0]$1243 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_datasr__oe$next[1:0]$1204 2'00
+ assign $2\dmi0_datasr__oe$next[1:0]$1244 2'00
case
- assign $2\dmi0_datasr__oe$next[1:0]$1204 $1\dmi0_datasr__oe$next[1:0]$1203
+ assign $2\dmi0_datasr__oe$next[1:0]$1244 $1\dmi0_datasr__oe$next[1:0]$1243
end
sync always
- update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$1202
+ update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$1242
end
- attribute \src "libresoc.v:43836.3-43856.6"
- process $proc$libresoc.v:43836$1205
+ attribute \src "libresoc.v:44027.3-44047.6"
+ process $proc$libresoc.v:44027$1245
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0_datasr_reg$next[63:0]$1206 $3\dmi0_datasr_reg$next[63:0]$1209
- attribute \src "libresoc.v:43837.5-43837.29"
+ assign $0\dmi0_datasr_reg$next[63:0]$1246 $3\dmi0_datasr_reg$next[63:0]$1249
+ attribute \src "libresoc.v:44028.5-44028.29"
switch \initial
- attribute \src "libresoc.v:43837.9-43837.17"
+ attribute \src "libresoc.v:44028.9-44028.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_datasr_reg$next[63:0]$1207 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] }
+ assign $1\dmi0_datasr_reg$next[63:0]$1247 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] }
case
- assign $1\dmi0_datasr_reg$next[63:0]$1207 \dmi0_datasr_reg
+ assign $1\dmi0_datasr_reg$next[63:0]$1247 \dmi0_datasr_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561"
switch \dmi0_datasr_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_datasr_reg$next[63:0]$1208 \dmi0_datasr__i
+ assign $2\dmi0_datasr_reg$next[63:0]$1248 \dmi0_datasr__i
case
- assign $2\dmi0_datasr_reg$next[63:0]$1208 $1\dmi0_datasr_reg$next[63:0]$1207
+ assign $2\dmi0_datasr_reg$next[63:0]$1248 $1\dmi0_datasr_reg$next[63:0]$1247
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0_datasr_reg$next[63:0]$1209 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dmi0_datasr_reg$next[63:0]$1249 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dmi0_datasr_reg$next[63:0]$1209 $2\dmi0_datasr_reg$next[63:0]$1208
+ assign $3\dmi0_datasr_reg$next[63:0]$1249 $2\dmi0_datasr_reg$next[63:0]$1248
end
sync always
- update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$1206
+ update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$1246
end
- attribute \src "libresoc.v:43857.3-43880.6"
- process $proc$libresoc.v:43857$1210
+ attribute \src "libresoc.v:44048.3-44071.6"
+ process $proc$libresoc.v:44048$1250
assign { } { }
assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0]
- attribute \src "libresoc.v:43858.5-43858.29"
+ attribute \src "libresoc.v:44049.5-44049.29"
switch \initial
- attribute \src "libresoc.v:43858.9-43858.17"
+ attribute \src "libresoc.v:44049.9-44049.17"
case 1'1
case
end
sync always
update \TAP_bus__tdo $0\TAP_bus__tdo[0:0]
end
- attribute \src "libresoc.v:43881.3-43913.6"
- process $proc$libresoc.v:43881$1211
+ attribute \src "libresoc.v:44072.3-44104.6"
+ process $proc$libresoc.v:44072$1251
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb__adr$next[28:0]$1212 $4\jtag_wb__adr$next[28:0]$1216
- attribute \src "libresoc.v:43882.5-43882.29"
+ assign $0\jtag_wb__adr$next[28:0]$1252 $4\jtag_wb__adr$next[28:0]$1256
+ attribute \src "libresoc.v:44073.5-44073.29"
switch \initial
- attribute \src "libresoc.v:43882.9-43882.17"
+ attribute \src "libresoc.v:44073.9-44073.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\jtag_wb__adr$next[28:0]$1213 $2\jtag_wb__adr$next[28:0]$1214
+ assign $1\jtag_wb__adr$next[28:0]$1253 $2\jtag_wb__adr$next[28:0]$1254
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196"
switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $2\jtag_wb__adr$next[28:0]$1214 \jtag_wb_addrsr__o
+ assign $2\jtag_wb__adr$next[28:0]$1254 \jtag_wb_addrsr__o
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $2\jtag_wb__adr$next[28:0]$1214 \$267 [28:0]
+ assign $2\jtag_wb__adr$next[28:0]$1254 \$267 [28:0]
case
- assign $2\jtag_wb__adr$next[28:0]$1214 \jtag_wb__adr
+ assign $2\jtag_wb__adr$next[28:0]$1254 \jtag_wb__adr
end
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\jtag_wb__adr$next[28:0]$1213 $3\jtag_wb__adr$next[28:0]$1215
+ assign $1\jtag_wb__adr$next[28:0]$1253 $3\jtag_wb__adr$next[28:0]$1255
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:224"
switch \jtag_wb__ack
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb__adr$next[28:0]$1215 \$270 [28:0]
+ assign $3\jtag_wb__adr$next[28:0]$1255 \$270 [28:0]
case
- assign $3\jtag_wb__adr$next[28:0]$1215 \jtag_wb__adr
+ assign $3\jtag_wb__adr$next[28:0]$1255 \jtag_wb__adr
end
case
- assign $1\jtag_wb__adr$next[28:0]$1213 \jtag_wb__adr
+ assign $1\jtag_wb__adr$next[28:0]$1253 \jtag_wb__adr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\jtag_wb__adr$next[28:0]$1216 29'00000000000000000000000000000
+ assign $4\jtag_wb__adr$next[28:0]$1256 29'00000000000000000000000000000
case
- assign $4\jtag_wb__adr$next[28:0]$1216 $1\jtag_wb__adr$next[28:0]$1213
+ assign $4\jtag_wb__adr$next[28:0]$1256 $1\jtag_wb__adr$next[28:0]$1253
end
sync always
- update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$1212
+ update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$1252
end
- attribute \src "libresoc.v:43914.3-43966.6"
- process $proc$libresoc.v:43914$1217
+ attribute \src "libresoc.v:44105.3-44157.6"
+ process $proc$libresoc.v:44105$1257
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$next[2:0]$1218 $5\fsm_state$next[2:0]$1223
- attribute \src "libresoc.v:43915.5-43915.29"
+ assign $0\fsm_state$next[2:0]$1258 $5\fsm_state$next[2:0]$1263
+ attribute \src "libresoc.v:44106.5-44106.29"
switch \initial
- attribute \src "libresoc.v:43915.9-43915.17"
+ attribute \src "libresoc.v:44106.9-44106.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\fsm_state$next[2:0]$1219 $2\fsm_state$next[2:0]$1220
+ assign $1\fsm_state$next[2:0]$1259 $2\fsm_state$next[2:0]$1260
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196"
switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $2\fsm_state$next[2:0]$1220 3'001
+ assign $2\fsm_state$next[2:0]$1260 3'001
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $2\fsm_state$next[2:0]$1220 3'001
+ assign $2\fsm_state$next[2:0]$1260 3'001
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $2\fsm_state$next[2:0]$1220 3'010
+ assign $2\fsm_state$next[2:0]$1260 3'010
case
- assign $2\fsm_state$next[2:0]$1220 \fsm_state
+ assign $2\fsm_state$next[2:0]$1260 \fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\fsm_state$next[2:0]$1219 3'011
+ assign $1\fsm_state$next[2:0]$1259 3'011
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\fsm_state$next[2:0]$1219 $3\fsm_state$next[2:0]$1221
+ assign $1\fsm_state$next[2:0]$1259 $3\fsm_state$next[2:0]$1261
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:213"
switch \jtag_wb__ack
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\fsm_state$next[2:0]$1221 3'000
+ assign $3\fsm_state$next[2:0]$1261 3'000
case
- assign $3\fsm_state$next[2:0]$1221 \fsm_state
+ assign $3\fsm_state$next[2:0]$1261 \fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'010
assign { } { }
- assign $1\fsm_state$next[2:0]$1219 3'100
+ assign $1\fsm_state$next[2:0]$1259 3'100
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\fsm_state$next[2:0]$1219 $4\fsm_state$next[2:0]$1222
+ assign $1\fsm_state$next[2:0]$1259 $4\fsm_state$next[2:0]$1262
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:224"
switch \jtag_wb__ack
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\fsm_state$next[2:0]$1222 3'001
+ assign $4\fsm_state$next[2:0]$1262 3'001
case
- assign $4\fsm_state$next[2:0]$1222 \fsm_state
+ assign $4\fsm_state$next[2:0]$1262 \fsm_state
end
case
- assign $1\fsm_state$next[2:0]$1219 \fsm_state
+ assign $1\fsm_state$next[2:0]$1259 \fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fsm_state$next[2:0]$1223 3'000
+ assign $5\fsm_state$next[2:0]$1263 3'000
case
- assign $5\fsm_state$next[2:0]$1223 $1\fsm_state$next[2:0]$1219
+ assign $5\fsm_state$next[2:0]$1263 $1\fsm_state$next[2:0]$1259
end
sync always
- update \fsm_state$next $0\fsm_state$next[2:0]$1218
+ update \fsm_state$next $0\fsm_state$next[2:0]$1258
end
- attribute \src "libresoc.v:43967.3-43993.6"
- process $proc$libresoc.v:43967$1224
+ attribute \src "libresoc.v:44158.3-44184.6"
+ process $proc$libresoc.v:44158$1264
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb__dat_w$next[63:0]$1225 $3\jtag_wb__dat_w$next[63:0]$1228
- attribute \src "libresoc.v:43968.5-43968.29"
+ assign $0\jtag_wb__dat_w$next[63:0]$1265 $3\jtag_wb__dat_w$next[63:0]$1268
+ attribute \src "libresoc.v:44159.5-44159.29"
switch \initial
- attribute \src "libresoc.v:43968.9-43968.17"
+ attribute \src "libresoc.v:44159.9-44159.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\jtag_wb__dat_w$next[63:0]$1226 $2\jtag_wb__dat_w$next[63:0]$1227
+ assign $1\jtag_wb__dat_w$next[63:0]$1266 $2\jtag_wb__dat_w$next[63:0]$1267
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196"
switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $2\jtag_wb__dat_w$next[63:0]$1227 \jtag_wb__dat_w
+ assign $2\jtag_wb__dat_w$next[63:0]$1267 \jtag_wb__dat_w
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $2\jtag_wb__dat_w$next[63:0]$1227 \jtag_wb__dat_w
+ assign $2\jtag_wb__dat_w$next[63:0]$1267 \jtag_wb__dat_w
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $2\jtag_wb__dat_w$next[63:0]$1227 \jtag_wb_datasr__o
+ assign $2\jtag_wb__dat_w$next[63:0]$1267 \jtag_wb_datasr__o
case
- assign $2\jtag_wb__dat_w$next[63:0]$1227 \jtag_wb__dat_w
+ assign $2\jtag_wb__dat_w$next[63:0]$1267 \jtag_wb__dat_w
end
case
- assign $1\jtag_wb__dat_w$next[63:0]$1226 \jtag_wb__dat_w
+ assign $1\jtag_wb__dat_w$next[63:0]$1266 \jtag_wb__dat_w
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb__dat_w$next[63:0]$1228 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\jtag_wb__dat_w$next[63:0]$1268 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\jtag_wb__dat_w$next[63:0]$1228 $1\jtag_wb__dat_w$next[63:0]$1226
+ assign $3\jtag_wb__dat_w$next[63:0]$1268 $1\jtag_wb__dat_w$next[63:0]$1266
end
sync always
- update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$1225
+ update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$1265
end
- attribute \src "libresoc.v:43994.3-44014.6"
- process $proc$libresoc.v:43994$1229
+ attribute \src "libresoc.v:44185.3-44205.6"
+ process $proc$libresoc.v:44185$1269
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr__i$next[63:0]$1230 $3\jtag_wb_datasr__i$next[63:0]$1233
- attribute \src "libresoc.v:43995.5-43995.29"
+ assign $0\jtag_wb_datasr__i$next[63:0]$1270 $3\jtag_wb_datasr__i$next[63:0]$1273
+ attribute \src "libresoc.v:44186.5-44186.29"
switch \initial
- attribute \src "libresoc.v:43995.9-43995.17"
+ attribute \src "libresoc.v:44186.9-44186.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\jtag_wb_datasr__i$next[63:0]$1231 $2\jtag_wb_datasr__i$next[63:0]$1232
+ assign $1\jtag_wb_datasr__i$next[63:0]$1271 $2\jtag_wb_datasr__i$next[63:0]$1272
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:213"
switch \jtag_wb__ack
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_datasr__i$next[63:0]$1232 \jtag_wb__dat_r
+ assign $2\jtag_wb_datasr__i$next[63:0]$1272 \jtag_wb__dat_r
case
- assign $2\jtag_wb_datasr__i$next[63:0]$1232 \jtag_wb_datasr__i
+ assign $2\jtag_wb_datasr__i$next[63:0]$1272 \jtag_wb_datasr__i
end
case
- assign $1\jtag_wb_datasr__i$next[63:0]$1231 \jtag_wb_datasr__i
+ assign $1\jtag_wb_datasr__i$next[63:0]$1271 \jtag_wb_datasr__i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb_datasr__i$next[63:0]$1233 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\jtag_wb_datasr__i$next[63:0]$1273 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\jtag_wb_datasr__i$next[63:0]$1233 $1\jtag_wb_datasr__i$next[63:0]$1231
+ assign $3\jtag_wb_datasr__i$next[63:0]$1273 $1\jtag_wb_datasr__i$next[63:0]$1271
end
sync always
- update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$1230
+ update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$1270
end
- attribute \src "libresoc.v:44015.3-44047.6"
- process $proc$libresoc.v:44015$1234
+ attribute \src "libresoc.v:44206.3-44238.6"
+ process $proc$libresoc.v:44206$1274
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0_addr_i$next[3:0]$1235 $4\dmi0_addr_i$next[3:0]$1239
- attribute \src "libresoc.v:44016.5-44016.29"
+ assign $0\dmi0_addr_i$next[3:0]$1275 $4\dmi0_addr_i$next[3:0]$1279
+ attribute \src "libresoc.v:44207.5-44207.29"
switch \initial
- attribute \src "libresoc.v:44016.9-44016.17"
+ attribute \src "libresoc.v:44207.9-44207.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\dmi0_addr_i$next[3:0]$1236 $2\dmi0_addr_i$next[3:0]$1237
+ assign $1\dmi0_addr_i$next[3:0]$1276 $2\dmi0_addr_i$next[3:0]$1277
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148"
switch { \dmi0_datasr__oe \dmi0_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $2\dmi0_addr_i$next[3:0]$1237 \dmi0_addrsr__o [3:0]
+ assign $2\dmi0_addr_i$next[3:0]$1277 \dmi0_addrsr__o [3:0]
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $2\dmi0_addr_i$next[3:0]$1237 \$284 [3:0]
+ assign $2\dmi0_addr_i$next[3:0]$1277 \$284 [3:0]
case
- assign $2\dmi0_addr_i$next[3:0]$1237 \dmi0_addr_i
+ assign $2\dmi0_addr_i$next[3:0]$1277 \dmi0_addr_i
end
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\dmi0_addr_i$next[3:0]$1236 $3\dmi0_addr_i$next[3:0]$1238
+ assign $1\dmi0_addr_i$next[3:0]$1276 $3\dmi0_addr_i$next[3:0]$1278
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:176"
switch \dmi0_ack_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0_addr_i$next[3:0]$1238 \$287 [3:0]
+ assign $3\dmi0_addr_i$next[3:0]$1278 \$287 [3:0]
case
- assign $3\dmi0_addr_i$next[3:0]$1238 \dmi0_addr_i
+ assign $3\dmi0_addr_i$next[3:0]$1278 \dmi0_addr_i
end
case
- assign $1\dmi0_addr_i$next[3:0]$1236 \dmi0_addr_i
+ assign $1\dmi0_addr_i$next[3:0]$1276 \dmi0_addr_i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\dmi0_addr_i$next[3:0]$1239 4'0000
+ assign $4\dmi0_addr_i$next[3:0]$1279 4'0000
case
- assign $4\dmi0_addr_i$next[3:0]$1239 $1\dmi0_addr_i$next[3:0]$1236
+ assign $4\dmi0_addr_i$next[3:0]$1279 $1\dmi0_addr_i$next[3:0]$1276
end
sync always
- update \dmi0_addr_i$next $0\dmi0_addr_i$next[3:0]$1235
+ update \dmi0_addr_i$next $0\dmi0_addr_i$next[3:0]$1275
end
- attribute \src "libresoc.v:44048.3-44100.6"
- process $proc$libresoc.v:44048$1240
+ attribute \src "libresoc.v:44239.3-44291.6"
+ process $proc$libresoc.v:44239$1280
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$275$next[2:0]$1241 $5\fsm_state$275$next[2:0]$1246
- attribute \src "libresoc.v:44049.5-44049.29"
+ assign $0\fsm_state$275$next[2:0]$1281 $5\fsm_state$275$next[2:0]$1286
+ attribute \src "libresoc.v:44240.5-44240.29"
switch \initial
- attribute \src "libresoc.v:44049.9-44049.17"
+ attribute \src "libresoc.v:44240.9-44240.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\fsm_state$275$next[2:0]$1242 $2\fsm_state$275$next[2:0]$1243
+ assign $1\fsm_state$275$next[2:0]$1282 $2\fsm_state$275$next[2:0]$1283
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148"
switch { \dmi0_datasr__oe \dmi0_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $2\fsm_state$275$next[2:0]$1243 3'001
+ assign $2\fsm_state$275$next[2:0]$1283 3'001
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $2\fsm_state$275$next[2:0]$1243 3'001
+ assign $2\fsm_state$275$next[2:0]$1283 3'001
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $2\fsm_state$275$next[2:0]$1243 3'010
+ assign $2\fsm_state$275$next[2:0]$1283 3'010
case
- assign $2\fsm_state$275$next[2:0]$1243 \fsm_state$275
+ assign $2\fsm_state$275$next[2:0]$1283 \fsm_state$275
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\fsm_state$275$next[2:0]$1242 3'011
+ assign $1\fsm_state$275$next[2:0]$1282 3'011
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\fsm_state$275$next[2:0]$1242 $3\fsm_state$275$next[2:0]$1244
+ assign $1\fsm_state$275$next[2:0]$1282 $3\fsm_state$275$next[2:0]$1284
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:165"
switch \dmi0_ack_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\fsm_state$275$next[2:0]$1244 3'000
+ assign $3\fsm_state$275$next[2:0]$1284 3'000
case
- assign $3\fsm_state$275$next[2:0]$1244 \fsm_state$275
+ assign $3\fsm_state$275$next[2:0]$1284 \fsm_state$275
end
attribute \src "libresoc.v:0.0-0.0"
case 3'010
assign { } { }
- assign $1\fsm_state$275$next[2:0]$1242 3'100
+ assign $1\fsm_state$275$next[2:0]$1282 3'100
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\fsm_state$275$next[2:0]$1242 $4\fsm_state$275$next[2:0]$1245
+ assign $1\fsm_state$275$next[2:0]$1282 $4\fsm_state$275$next[2:0]$1285
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:176"
switch \dmi0_ack_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\fsm_state$275$next[2:0]$1245 3'001
+ assign $4\fsm_state$275$next[2:0]$1285 3'001
case
- assign $4\fsm_state$275$next[2:0]$1245 \fsm_state$275
+ assign $4\fsm_state$275$next[2:0]$1285 \fsm_state$275
end
case
- assign $1\fsm_state$275$next[2:0]$1242 \fsm_state$275
+ assign $1\fsm_state$275$next[2:0]$1282 \fsm_state$275
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fsm_state$275$next[2:0]$1246 3'000
+ assign $5\fsm_state$275$next[2:0]$1286 3'000
case
- assign $5\fsm_state$275$next[2:0]$1246 $1\fsm_state$275$next[2:0]$1242
+ assign $5\fsm_state$275$next[2:0]$1286 $1\fsm_state$275$next[2:0]$1282
end
sync always
- update \fsm_state$275$next $0\fsm_state$275$next[2:0]$1241
+ update \fsm_state$275$next $0\fsm_state$275$next[2:0]$1281
end
- attribute \src "libresoc.v:44101.3-44127.6"
- process $proc$libresoc.v:44101$1247
+ attribute \src "libresoc.v:44292.3-44318.6"
+ process $proc$libresoc.v:44292$1287
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0_din$next[63:0]$1248 $3\dmi0_din$next[63:0]$1251
- attribute \src "libresoc.v:44102.5-44102.29"
+ assign $0\dmi0_din$next[63:0]$1288 $3\dmi0_din$next[63:0]$1291
+ attribute \src "libresoc.v:44293.5-44293.29"
switch \initial
- attribute \src "libresoc.v:44102.9-44102.17"
+ attribute \src "libresoc.v:44293.9-44293.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\dmi0_din$next[63:0]$1249 $2\dmi0_din$next[63:0]$1250
+ assign $1\dmi0_din$next[63:0]$1289 $2\dmi0_din$next[63:0]$1290
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148"
switch { \dmi0_datasr__oe \dmi0_addrsr__oe }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $2\dmi0_din$next[63:0]$1250 \dmi0_din
+ assign $2\dmi0_din$next[63:0]$1290 \dmi0_din
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $2\dmi0_din$next[63:0]$1250 \dmi0_din
+ assign $2\dmi0_din$next[63:0]$1290 \dmi0_din
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $2\dmi0_din$next[63:0]$1250 \dmi0_datasr__o
+ assign $2\dmi0_din$next[63:0]$1290 \dmi0_datasr__o
case
- assign $2\dmi0_din$next[63:0]$1250 \dmi0_din
+ assign $2\dmi0_din$next[63:0]$1290 \dmi0_din
end
case
- assign $1\dmi0_din$next[63:0]$1249 \dmi0_din
+ assign $1\dmi0_din$next[63:0]$1289 \dmi0_din
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0_din$next[63:0]$1251 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dmi0_din$next[63:0]$1291 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dmi0_din$next[63:0]$1251 $1\dmi0_din$next[63:0]$1249
+ assign $3\dmi0_din$next[63:0]$1291 $1\dmi0_din$next[63:0]$1289
end
sync always
- update \dmi0_din$next $0\dmi0_din$next[63:0]$1248
+ update \dmi0_din$next $0\dmi0_din$next[63:0]$1288
end
- attribute \src "libresoc.v:44128.3-44148.6"
- process $proc$libresoc.v:44128$1252
+ attribute \src "libresoc.v:44319.3-44339.6"
+ process $proc$libresoc.v:44319$1292
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0_datasr__i$next[63:0]$1253 $3\dmi0_datasr__i$next[63:0]$1256
- attribute \src "libresoc.v:44129.5-44129.29"
+ assign $0\dmi0_datasr__i$next[63:0]$1293 $3\dmi0_datasr__i$next[63:0]$1296
+ attribute \src "libresoc.v:44320.5-44320.29"
switch \initial
- attribute \src "libresoc.v:44129.9-44129.17"
+ attribute \src "libresoc.v:44320.9-44320.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\dmi0_datasr__i$next[63:0]$1254 $2\dmi0_datasr__i$next[63:0]$1255
+ assign $1\dmi0_datasr__i$next[63:0]$1294 $2\dmi0_datasr__i$next[63:0]$1295
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:165"
switch \dmi0_ack_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_datasr__i$next[63:0]$1255 \dmi0_dout
+ assign $2\dmi0_datasr__i$next[63:0]$1295 \dmi0_dout
case
- assign $2\dmi0_datasr__i$next[63:0]$1255 \dmi0_datasr__i
+ assign $2\dmi0_datasr__i$next[63:0]$1295 \dmi0_datasr__i
end
case
- assign $1\dmi0_datasr__i$next[63:0]$1254 \dmi0_datasr__i
+ assign $1\dmi0_datasr__i$next[63:0]$1294 \dmi0_datasr__i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0_datasr__i$next[63:0]$1256 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dmi0_datasr__i$next[63:0]$1296 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dmi0_datasr__i$next[63:0]$1256 $1\dmi0_datasr__i$next[63:0]$1254
+ assign $3\dmi0_datasr__i$next[63:0]$1296 $1\dmi0_datasr__i$next[63:0]$1294
end
sync always
- update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$1253
+ update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$1293
end
- attribute \src "libresoc.v:44149.3-44217.6"
- process $proc$libresoc.v:44149$1257
+ attribute \src "libresoc.v:44340.3-44408.6"
+ process $proc$libresoc.v:44340$1297
assign { } { }
assign { } { }
assign { } { }
- assign $0\io_sr$next[49:0]$1258 $2\io_sr$next[49:0]$1260
- attribute \src "libresoc.v:44150.5-44150.29"
+ assign $0\io_sr$next[49:0]$1298 $2\io_sr$next[49:0]$1300
+ attribute \src "libresoc.v:44341.5-44341.29"
switch \initial
- attribute \src "libresoc.v:44150.9-44150.17"
+ attribute \src "libresoc.v:44341.9-44341.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
assign { } { }
- assign $1\io_sr$next[49:0]$1259 [0] \uart_tx__core__o
- assign $1\io_sr$next[49:0]$1259 [1] \uart_rx__pad__i
- assign $1\io_sr$next[49:0]$1259 [2] \gpio_gpio0__pad__i
- assign $1\io_sr$next[49:0]$1259 [3] \gpio_gpio0__core__o
- assign $1\io_sr$next[49:0]$1259 [4] \gpio_gpio0__core__oe
- assign $1\io_sr$next[49:0]$1259 [5] \gpio_gpio1__pad__i
- assign $1\io_sr$next[49:0]$1259 [6] \gpio_gpio1__core__o
- assign $1\io_sr$next[49:0]$1259 [7] \gpio_gpio1__core__oe
- assign $1\io_sr$next[49:0]$1259 [8] \gpio_gpio2__pad__i
- assign $1\io_sr$next[49:0]$1259 [9] \gpio_gpio2__core__o
- assign $1\io_sr$next[49:0]$1259 [10] \gpio_gpio2__core__oe
- assign $1\io_sr$next[49:0]$1259 [11] \gpio_gpio3__pad__i
- assign $1\io_sr$next[49:0]$1259 [12] \gpio_gpio3__core__o
- assign $1\io_sr$next[49:0]$1259 [13] \gpio_gpio3__core__oe
- assign $1\io_sr$next[49:0]$1259 [14] \gpio_gpio4__pad__i
- assign $1\io_sr$next[49:0]$1259 [15] \gpio_gpio4__core__o
- assign $1\io_sr$next[49:0]$1259 [16] \gpio_gpio4__core__oe
- assign $1\io_sr$next[49:0]$1259 [17] \gpio_gpio5__pad__i
- assign $1\io_sr$next[49:0]$1259 [18] \gpio_gpio5__core__o
- assign $1\io_sr$next[49:0]$1259 [19] \gpio_gpio5__core__oe
- assign $1\io_sr$next[49:0]$1259 [20] \gpio_gpio6__pad__i
- assign $1\io_sr$next[49:0]$1259 [21] \gpio_gpio6__core__o
- assign $1\io_sr$next[49:0]$1259 [22] \gpio_gpio6__core__oe
- assign $1\io_sr$next[49:0]$1259 [23] \gpio_gpio7__pad__i
- assign $1\io_sr$next[49:0]$1259 [24] \gpio_gpio7__core__o
- assign $1\io_sr$next[49:0]$1259 [25] \gpio_gpio7__core__oe
- assign $1\io_sr$next[49:0]$1259 [26] \gpio_gpio8__pad__i
- assign $1\io_sr$next[49:0]$1259 [27] \gpio_gpio8__core__o
- assign $1\io_sr$next[49:0]$1259 [28] \gpio_gpio8__core__oe
- assign $1\io_sr$next[49:0]$1259 [29] \gpio_gpio9__pad__i
- assign $1\io_sr$next[49:0]$1259 [30] \gpio_gpio9__core__o
- assign $1\io_sr$next[49:0]$1259 [31] \gpio_gpio9__core__oe
- assign $1\io_sr$next[49:0]$1259 [32] \gpio_gpio10__pad__i
- assign $1\io_sr$next[49:0]$1259 [33] \gpio_gpio10__core__o
- assign $1\io_sr$next[49:0]$1259 [34] \gpio_gpio10__core__oe
- assign $1\io_sr$next[49:0]$1259 [35] \gpio_gpio11__pad__i
- assign $1\io_sr$next[49:0]$1259 [36] \gpio_gpio11__core__o
- assign $1\io_sr$next[49:0]$1259 [37] \gpio_gpio11__core__oe
- assign $1\io_sr$next[49:0]$1259 [38] \gpio_gpio12__pad__i
- assign $1\io_sr$next[49:0]$1259 [39] \gpio_gpio12__core__o
- assign $1\io_sr$next[49:0]$1259 [40] \gpio_gpio12__core__oe
- assign $1\io_sr$next[49:0]$1259 [41] \gpio_gpio13__pad__i
- assign $1\io_sr$next[49:0]$1259 [42] \gpio_gpio13__core__o
- assign $1\io_sr$next[49:0]$1259 [43] \gpio_gpio13__core__oe
- assign $1\io_sr$next[49:0]$1259 [44] \gpio_gpio14__pad__i
- assign $1\io_sr$next[49:0]$1259 [45] \gpio_gpio14__core__o
- assign $1\io_sr$next[49:0]$1259 [46] \gpio_gpio14__core__oe
- assign $1\io_sr$next[49:0]$1259 [47] \gpio_gpio15__pad__i
- assign $1\io_sr$next[49:0]$1259 [48] \gpio_gpio15__core__o
- assign $1\io_sr$next[49:0]$1259 [49] \gpio_gpio15__core__oe
+ assign $1\io_sr$next[49:0]$1299 [0] \uart_tx__core__o
+ assign $1\io_sr$next[49:0]$1299 [1] \uart_rx__pad__i
+ assign $1\io_sr$next[49:0]$1299 [2] \gpio_gpio0__pad__i
+ assign $1\io_sr$next[49:0]$1299 [3] \gpio_gpio0__core__o
+ assign $1\io_sr$next[49:0]$1299 [4] \gpio_gpio0__core__oe
+ assign $1\io_sr$next[49:0]$1299 [5] \gpio_gpio1__pad__i
+ assign $1\io_sr$next[49:0]$1299 [6] \gpio_gpio1__core__o
+ assign $1\io_sr$next[49:0]$1299 [7] \gpio_gpio1__core__oe
+ assign $1\io_sr$next[49:0]$1299 [8] \gpio_gpio2__pad__i
+ assign $1\io_sr$next[49:0]$1299 [9] \gpio_gpio2__core__o
+ assign $1\io_sr$next[49:0]$1299 [10] \gpio_gpio2__core__oe
+ assign $1\io_sr$next[49:0]$1299 [11] \gpio_gpio3__pad__i
+ assign $1\io_sr$next[49:0]$1299 [12] \gpio_gpio3__core__o
+ assign $1\io_sr$next[49:0]$1299 [13] \gpio_gpio3__core__oe
+ assign $1\io_sr$next[49:0]$1299 [14] \gpio_gpio4__pad__i
+ assign $1\io_sr$next[49:0]$1299 [15] \gpio_gpio4__core__o
+ assign $1\io_sr$next[49:0]$1299 [16] \gpio_gpio4__core__oe
+ assign $1\io_sr$next[49:0]$1299 [17] \gpio_gpio5__pad__i
+ assign $1\io_sr$next[49:0]$1299 [18] \gpio_gpio5__core__o
+ assign $1\io_sr$next[49:0]$1299 [19] \gpio_gpio5__core__oe
+ assign $1\io_sr$next[49:0]$1299 [20] \gpio_gpio6__pad__i
+ assign $1\io_sr$next[49:0]$1299 [21] \gpio_gpio6__core__o
+ assign $1\io_sr$next[49:0]$1299 [22] \gpio_gpio6__core__oe
+ assign $1\io_sr$next[49:0]$1299 [23] \gpio_gpio7__pad__i
+ assign $1\io_sr$next[49:0]$1299 [24] \gpio_gpio7__core__o
+ assign $1\io_sr$next[49:0]$1299 [25] \gpio_gpio7__core__oe
+ assign $1\io_sr$next[49:0]$1299 [26] \gpio_gpio8__pad__i
+ assign $1\io_sr$next[49:0]$1299 [27] \gpio_gpio8__core__o
+ assign $1\io_sr$next[49:0]$1299 [28] \gpio_gpio8__core__oe
+ assign $1\io_sr$next[49:0]$1299 [29] \gpio_gpio9__pad__i
+ assign $1\io_sr$next[49:0]$1299 [30] \gpio_gpio9__core__o
+ assign $1\io_sr$next[49:0]$1299 [31] \gpio_gpio9__core__oe
+ assign $1\io_sr$next[49:0]$1299 [32] \gpio_gpio10__pad__i
+ assign $1\io_sr$next[49:0]$1299 [33] \gpio_gpio10__core__o
+ assign $1\io_sr$next[49:0]$1299 [34] \gpio_gpio10__core__oe
+ assign $1\io_sr$next[49:0]$1299 [35] \gpio_gpio11__pad__i
+ assign $1\io_sr$next[49:0]$1299 [36] \gpio_gpio11__core__o
+ assign $1\io_sr$next[49:0]$1299 [37] \gpio_gpio11__core__oe
+ assign $1\io_sr$next[49:0]$1299 [38] \gpio_gpio12__pad__i
+ assign $1\io_sr$next[49:0]$1299 [39] \gpio_gpio12__core__o
+ assign $1\io_sr$next[49:0]$1299 [40] \gpio_gpio12__core__oe
+ assign $1\io_sr$next[49:0]$1299 [41] \gpio_gpio13__pad__i
+ assign $1\io_sr$next[49:0]$1299 [42] \gpio_gpio13__core__o
+ assign $1\io_sr$next[49:0]$1299 [43] \gpio_gpio13__core__oe
+ assign $1\io_sr$next[49:0]$1299 [44] \gpio_gpio14__pad__i
+ assign $1\io_sr$next[49:0]$1299 [45] \gpio_gpio14__core__o
+ assign $1\io_sr$next[49:0]$1299 [46] \gpio_gpio14__core__oe
+ assign $1\io_sr$next[49:0]$1299 [47] \gpio_gpio15__pad__i
+ assign $1\io_sr$next[49:0]$1299 [48] \gpio_gpio15__core__o
+ assign $1\io_sr$next[49:0]$1299 [49] \gpio_gpio15__core__oe
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
assign { } { }
- assign $1\io_sr$next[49:0]$1259 { \io_sr [48:0] \TAP_bus__tdi }
+ assign $1\io_sr$next[49:0]$1299 { \io_sr [48:0] \TAP_bus__tdi }
case
- assign $1\io_sr$next[49:0]$1259 \io_sr
+ assign $1\io_sr$next[49:0]$1299 \io_sr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\io_sr$next[49:0]$1260 50'00000000000000000000000000000000000000000000000000
+ assign $2\io_sr$next[49:0]$1300 50'00000000000000000000000000000000000000000000000000
case
- assign $2\io_sr$next[49:0]$1260 $1\io_sr$next[49:0]$1259
+ assign $2\io_sr$next[49:0]$1300 $1\io_sr$next[49:0]$1299
end
sync always
- update \io_sr$next $0\io_sr$next[49:0]$1258
+ update \io_sr$next $0\io_sr$next[49:0]$1298
end
- attribute \src "libresoc.v:44218.3-44233.6"
- process $proc$libresoc.v:44218$1261
+ attribute \src "libresoc.v:44409.3-44424.6"
+ process $proc$libresoc.v:44409$1301
assign { } { }
assign { } { }
assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0]
- attribute \src "libresoc.v:44219.5-44219.29"
+ attribute \src "libresoc.v:44410.5-44410.29"
switch \initial
- attribute \src "libresoc.v:44219.9-44219.17"
+ attribute \src "libresoc.v:44410.9-44410.17"
case 1'1
case
end
sync always
update \TAP_tdo $0\TAP_tdo[0:0]
end
- attribute \src "libresoc.v:44234.3-44254.6"
- process $proc$libresoc.v:44234$1262
+ attribute \src "libresoc.v:44425.3-44445.6"
+ process $proc$libresoc.v:44425$1302
assign { } { }
assign { } { }
assign { } { }
- assign $0\io_bd$next[49:0]$1263 $2\io_bd$next[49:0]$1265
- attribute \src "libresoc.v:44235.5-44235.29"
+ assign $0\io_bd$next[49:0]$1303 $2\io_bd$next[49:0]$1305
+ attribute \src "libresoc.v:44426.5-44426.29"
switch \initial
- attribute \src "libresoc.v:44235.9-44235.17"
+ attribute \src "libresoc.v:44426.9-44426.17"
case 1'1
case
end
switch { \io_update \io_shift \io_capture }
attribute \src "libresoc.v:0.0-0.0"
case 3'--1
- assign $1\io_bd$next[49:0]$1264 \io_bd
+ assign $1\io_bd$next[49:0]$1304 \io_bd
attribute \src "libresoc.v:0.0-0.0"
case 3'-1-
- assign $1\io_bd$next[49:0]$1264 \io_bd
+ assign $1\io_bd$next[49:0]$1304 \io_bd
attribute \src "libresoc.v:0.0-0.0"
case 3'1--
assign { } { }
- assign $1\io_bd$next[49:0]$1264 \io_sr
+ assign $1\io_bd$next[49:0]$1304 \io_sr
case
- assign $1\io_bd$next[49:0]$1264 \io_bd
+ assign $1\io_bd$next[49:0]$1304 \io_bd
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \negjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\io_bd$next[49:0]$1265 50'00000000000000000000000000000000000000000000000000
+ assign $2\io_bd$next[49:0]$1305 50'00000000000000000000000000000000000000000000000000
case
- assign $2\io_bd$next[49:0]$1265 $1\io_bd$next[49:0]$1264
+ assign $2\io_bd$next[49:0]$1305 $1\io_bd$next[49:0]$1304
end
sync always
- update \io_bd$next $0\io_bd$next[49:0]$1263
+ update \io_bd$next $0\io_bd$next[49:0]$1303
end
- attribute \src "libresoc.v:44255.3-44263.6"
- process $proc$libresoc.v:44255$1266
+ attribute \src "libresoc.v:44446.3-44454.6"
+ process $proc$libresoc.v:44446$1306
assign { } { }
assign { } { }
- assign $0\sr0_update_core$next[0:0]$1267 $1\sr0_update_core$next[0:0]$1268
- attribute \src "libresoc.v:44256.5-44256.29"
+ assign $0\sr0_update_core$next[0:0]$1307 $1\sr0_update_core$next[0:0]$1308
+ attribute \src "libresoc.v:44447.5-44447.29"
switch \initial
- attribute \src "libresoc.v:44256.9-44256.17"
+ attribute \src "libresoc.v:44447.9-44447.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr0_update_core$next[0:0]$1268 1'0
+ assign $1\sr0_update_core$next[0:0]$1308 1'0
case
- assign $1\sr0_update_core$next[0:0]$1268 \sr0_update
+ assign $1\sr0_update_core$next[0:0]$1308 \sr0_update
end
sync always
- update \sr0_update_core$next $0\sr0_update_core$next[0:0]$1267
+ update \sr0_update_core$next $0\sr0_update_core$next[0:0]$1307
end
- attribute \src "libresoc.v:44264.3-44272.6"
- process $proc$libresoc.v:44264$1269
+ attribute \src "libresoc.v:44455.3-44463.6"
+ process $proc$libresoc.v:44455$1309
assign { } { }
assign { } { }
- assign $0\sr0_update_core_prev$next[0:0]$1270 $1\sr0_update_core_prev$next[0:0]$1271
- attribute \src "libresoc.v:44265.5-44265.29"
+ assign $0\sr0_update_core_prev$next[0:0]$1310 $1\sr0_update_core_prev$next[0:0]$1311
+ attribute \src "libresoc.v:44456.5-44456.29"
switch \initial
- attribute \src "libresoc.v:44265.9-44265.17"
+ attribute \src "libresoc.v:44456.9-44456.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr0_update_core_prev$next[0:0]$1271 1'0
+ assign $1\sr0_update_core_prev$next[0:0]$1311 1'0
case
- assign $1\sr0_update_core_prev$next[0:0]$1271 \sr0_update_core
+ assign $1\sr0_update_core_prev$next[0:0]$1311 \sr0_update_core
end
sync always
- update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$1270
+ update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$1310
end
- attribute \src "libresoc.v:44273.3-44289.6"
- process $proc$libresoc.v:44273$1272
+ attribute \src "libresoc.v:44464.3-44480.6"
+ process $proc$libresoc.v:44464$1312
assign { } { }
assign { } { }
- assign $0\sr0__oe$next[0:0]$1273 $2\sr0__oe$next[0:0]$1275
- attribute \src "libresoc.v:44274.5-44274.29"
+ assign $0\sr0__oe$next[0:0]$1313 $2\sr0__oe$next[0:0]$1315
+ attribute \src "libresoc.v:44465.5-44465.29"
switch \initial
- attribute \src "libresoc.v:44274.9-44274.17"
+ attribute \src "libresoc.v:44465.9-44465.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr0__oe$next[0:0]$1274 \sr0_isir
+ assign $1\sr0__oe$next[0:0]$1314 \sr0_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\sr0__oe$next[0:0]$1274 1'0
+ assign $1\sr0__oe$next[0:0]$1314 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sr0__oe$next[0:0]$1275 1'0
+ assign $2\sr0__oe$next[0:0]$1315 1'0
case
- assign $2\sr0__oe$next[0:0]$1275 $1\sr0__oe$next[0:0]$1274
+ assign $2\sr0__oe$next[0:0]$1315 $1\sr0__oe$next[0:0]$1314
end
sync always
- update \sr0__oe$next $0\sr0__oe$next[0:0]$1273
+ update \sr0__oe$next $0\sr0__oe$next[0:0]$1313
end
- attribute \src "libresoc.v:44290.3-44310.6"
- process $proc$libresoc.v:44290$1276
+ attribute \src "libresoc.v:44481.3-44501.6"
+ process $proc$libresoc.v:44481$1316
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\sr0_reg$next[2:0]$1277 $3\sr0_reg$next[2:0]$1280
- attribute \src "libresoc.v:44291.5-44291.29"
+ assign $0\sr0_reg$next[2:0]$1317 $3\sr0_reg$next[2:0]$1320
+ attribute \src "libresoc.v:44482.5-44482.29"
switch \initial
- attribute \src "libresoc.v:44291.9-44291.17"
+ attribute \src "libresoc.v:44482.9-44482.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\sr0_reg$next[2:0]$1278 { \TAP_bus__tdi \sr0_reg [2:1] }
+ assign $1\sr0_reg$next[2:0]$1318 { \TAP_bus__tdi \sr0_reg [2:1] }
case
- assign $1\sr0_reg$next[2:0]$1278 \sr0_reg
+ assign $1\sr0_reg$next[2:0]$1318 \sr0_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561"
switch \sr0_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\sr0_reg$next[2:0]$1279 \sr0__i
+ assign $2\sr0_reg$next[2:0]$1319 \sr0__i
case
- assign $2\sr0_reg$next[2:0]$1279 $1\sr0_reg$next[2:0]$1278
+ assign $2\sr0_reg$next[2:0]$1319 $1\sr0_reg$next[2:0]$1318
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\sr0_reg$next[2:0]$1280 3'000
+ assign $3\sr0_reg$next[2:0]$1320 3'000
case
- assign $3\sr0_reg$next[2:0]$1280 $2\sr0_reg$next[2:0]$1279
+ assign $3\sr0_reg$next[2:0]$1320 $2\sr0_reg$next[2:0]$1319
end
sync always
- update \sr0_reg$next $0\sr0_reg$next[2:0]$1277
+ update \sr0_reg$next $0\sr0_reg$next[2:0]$1317
end
- attribute \src "libresoc.v:44311.3-44319.6"
- process $proc$libresoc.v:44311$1281
+ attribute \src "libresoc.v:44502.3-44510.6"
+ process $proc$libresoc.v:44502$1321
assign { } { }
assign { } { }
- assign $0\jtag_wb_addrsr_update_core$next[0:0]$1282 $1\jtag_wb_addrsr_update_core$next[0:0]$1283
- attribute \src "libresoc.v:44312.5-44312.29"
+ assign $0\jtag_wb_addrsr_update_core$next[0:0]$1322 $1\jtag_wb_addrsr_update_core$next[0:0]$1323
+ attribute \src "libresoc.v:44503.5-44503.29"
switch \initial
- attribute \src "libresoc.v:44312.9-44312.17"
+ attribute \src "libresoc.v:44503.9-44503.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_addrsr_update_core$next[0:0]$1283 1'0
+ assign $1\jtag_wb_addrsr_update_core$next[0:0]$1323 1'0
case
- assign $1\jtag_wb_addrsr_update_core$next[0:0]$1283 \jtag_wb_addrsr_update
+ assign $1\jtag_wb_addrsr_update_core$next[0:0]$1323 \jtag_wb_addrsr_update
end
sync always
- update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$1282
+ update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$1322
end
- attribute \src "libresoc.v:44320.3-44328.6"
- process $proc$libresoc.v:44320$1284
+ attribute \src "libresoc.v:44511.3-44519.6"
+ process $proc$libresoc.v:44511$1324
assign { } { }
assign { } { }
- assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1285 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1286
- attribute \src "libresoc.v:44321.5-44321.29"
+ assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1325 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1326
+ attribute \src "libresoc.v:44512.5-44512.29"
switch \initial
- attribute \src "libresoc.v:44321.9-44321.17"
+ attribute \src "libresoc.v:44512.9-44512.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1286 1'0
+ assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1326 1'0
case
- assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1286 \jtag_wb_addrsr_update_core
+ assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1326 \jtag_wb_addrsr_update_core
end
sync always
- update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1285
+ update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1325
end
- attribute \src "libresoc.v:44329.3-44345.6"
- process $proc$libresoc.v:44329$1287
+ attribute \src "libresoc.v:44520.3-44536.6"
+ process $proc$libresoc.v:44520$1327
assign { } { }
assign { } { }
- assign $0\jtag_wb_addrsr__oe$next[0:0]$1288 $2\jtag_wb_addrsr__oe$next[0:0]$1290
- attribute \src "libresoc.v:44330.5-44330.29"
+ assign $0\jtag_wb_addrsr__oe$next[0:0]$1328 $2\jtag_wb_addrsr__oe$next[0:0]$1330
+ attribute \src "libresoc.v:44521.5-44521.29"
switch \initial
- attribute \src "libresoc.v:44330.9-44330.17"
+ attribute \src "libresoc.v:44521.9-44521.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_addrsr__oe$next[0:0]$1289 \jtag_wb_addrsr_isir
+ assign $1\jtag_wb_addrsr__oe$next[0:0]$1329 \jtag_wb_addrsr_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\jtag_wb_addrsr__oe$next[0:0]$1289 1'0
+ assign $1\jtag_wb_addrsr__oe$next[0:0]$1329 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_addrsr__oe$next[0:0]$1290 1'0
+ assign $2\jtag_wb_addrsr__oe$next[0:0]$1330 1'0
case
- assign $2\jtag_wb_addrsr__oe$next[0:0]$1290 $1\jtag_wb_addrsr__oe$next[0:0]$1289
+ assign $2\jtag_wb_addrsr__oe$next[0:0]$1330 $1\jtag_wb_addrsr__oe$next[0:0]$1329
end
sync always
- update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$1288
+ update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$1328
end
- attribute \src "libresoc.v:44346.3-44366.6"
- process $proc$libresoc.v:44346$1291
+ attribute \src "libresoc.v:44537.3-44557.6"
+ process $proc$libresoc.v:44537$1331
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb_addrsr_reg$next[28:0]$1292 $3\jtag_wb_addrsr_reg$next[28:0]$1295
- attribute \src "libresoc.v:44347.5-44347.29"
+ assign $0\jtag_wb_addrsr_reg$next[28:0]$1332 $3\jtag_wb_addrsr_reg$next[28:0]$1335
+ attribute \src "libresoc.v:44538.5-44538.29"
switch \initial
- attribute \src "libresoc.v:44347.9-44347.17"
+ attribute \src "libresoc.v:44538.9-44538.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_addrsr_reg$next[28:0]$1293 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] }
+ assign $1\jtag_wb_addrsr_reg$next[28:0]$1333 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] }
case
- assign $1\jtag_wb_addrsr_reg$next[28:0]$1293 \jtag_wb_addrsr_reg
+ assign $1\jtag_wb_addrsr_reg$next[28:0]$1333 \jtag_wb_addrsr_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561"
switch \jtag_wb_addrsr_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_addrsr_reg$next[28:0]$1294 \jtag_wb_addrsr__i
+ assign $2\jtag_wb_addrsr_reg$next[28:0]$1334 \jtag_wb_addrsr__i
case
- assign $2\jtag_wb_addrsr_reg$next[28:0]$1294 $1\jtag_wb_addrsr_reg$next[28:0]$1293
+ assign $2\jtag_wb_addrsr_reg$next[28:0]$1334 $1\jtag_wb_addrsr_reg$next[28:0]$1333
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb_addrsr_reg$next[28:0]$1295 29'00000000000000000000000000000
+ assign $3\jtag_wb_addrsr_reg$next[28:0]$1335 29'00000000000000000000000000000
case
- assign $3\jtag_wb_addrsr_reg$next[28:0]$1295 $2\jtag_wb_addrsr_reg$next[28:0]$1294
+ assign $3\jtag_wb_addrsr_reg$next[28:0]$1335 $2\jtag_wb_addrsr_reg$next[28:0]$1334
end
sync always
- update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$1292
+ update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$1332
end
- attribute \src "libresoc.v:44367.3-44375.6"
- process $proc$libresoc.v:44367$1296
+ attribute \src "libresoc.v:44558.3-44566.6"
+ process $proc$libresoc.v:44558$1336
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr_update_core$next[0:0]$1297 $1\jtag_wb_datasr_update_core$next[0:0]$1298
- attribute \src "libresoc.v:44368.5-44368.29"
+ assign $0\jtag_wb_datasr_update_core$next[0:0]$1337 $1\jtag_wb_datasr_update_core$next[0:0]$1338
+ attribute \src "libresoc.v:44559.5-44559.29"
switch \initial
- attribute \src "libresoc.v:44368.9-44368.17"
+ attribute \src "libresoc.v:44559.9-44559.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_datasr_update_core$next[0:0]$1298 1'0
+ assign $1\jtag_wb_datasr_update_core$next[0:0]$1338 1'0
case
- assign $1\jtag_wb_datasr_update_core$next[0:0]$1298 \jtag_wb_datasr_update
+ assign $1\jtag_wb_datasr_update_core$next[0:0]$1338 \jtag_wb_datasr_update
end
sync always
- update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$1297
+ update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$1337
end
- attribute \src "libresoc.v:44376.3-44384.6"
- process $proc$libresoc.v:44376$1299
+ attribute \src "libresoc.v:44567.3-44575.6"
+ process $proc$libresoc.v:44567$1339
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$1300 $1\jtag_wb_datasr_update_core_prev$next[0:0]$1301
- attribute \src "libresoc.v:44377.5-44377.29"
+ assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$1340 $1\jtag_wb_datasr_update_core_prev$next[0:0]$1341
+ attribute \src "libresoc.v:44568.5-44568.29"
switch \initial
- attribute \src "libresoc.v:44377.9-44377.17"
+ attribute \src "libresoc.v:44568.9-44568.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1301 1'0
+ assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1341 1'0
case
- assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1301 \jtag_wb_datasr_update_core
+ assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1341 \jtag_wb_datasr_update_core
end
sync always
- update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$1300
+ update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$1340
end
- attribute \src "libresoc.v:44385.3-44401.6"
- process $proc$libresoc.v:44385$1302
+ attribute \src "libresoc.v:44576.3-44592.6"
+ process $proc$libresoc.v:44576$1342
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr__oe$next[1:0]$1303 $2\jtag_wb_datasr__oe$next[1:0]$1305
- attribute \src "libresoc.v:44386.5-44386.29"
+ assign $0\jtag_wb_datasr__oe$next[1:0]$1343 $2\jtag_wb_datasr__oe$next[1:0]$1345
+ attribute \src "libresoc.v:44577.5-44577.29"
switch \initial
- attribute \src "libresoc.v:44386.9-44386.17"
+ attribute \src "libresoc.v:44577.9-44577.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_datasr__oe$next[1:0]$1304 \jtag_wb_datasr_isir
+ assign $1\jtag_wb_datasr__oe$next[1:0]$1344 \jtag_wb_datasr_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\jtag_wb_datasr__oe$next[1:0]$1304 2'00
+ assign $1\jtag_wb_datasr__oe$next[1:0]$1344 2'00
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_datasr__oe$next[1:0]$1305 2'00
+ assign $2\jtag_wb_datasr__oe$next[1:0]$1345 2'00
case
- assign $2\jtag_wb_datasr__oe$next[1:0]$1305 $1\jtag_wb_datasr__oe$next[1:0]$1304
+ assign $2\jtag_wb_datasr__oe$next[1:0]$1345 $1\jtag_wb_datasr__oe$next[1:0]$1344
end
sync always
- update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$1303
+ update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$1343
end
- attribute \src "libresoc.v:44402.3-44422.6"
- process $proc$libresoc.v:44402$1306
+ attribute \src "libresoc.v:44593.3-44613.6"
+ process $proc$libresoc.v:44593$1346
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\jtag_wb_datasr_reg$next[63:0]$1307 $3\jtag_wb_datasr_reg$next[63:0]$1310
- attribute \src "libresoc.v:44403.5-44403.29"
+ assign $0\jtag_wb_datasr_reg$next[63:0]$1347 $3\jtag_wb_datasr_reg$next[63:0]$1350
+ attribute \src "libresoc.v:44594.5-44594.29"
switch \initial
- attribute \src "libresoc.v:44403.9-44403.17"
+ attribute \src "libresoc.v:44594.9-44594.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_wb_datasr_reg$next[63:0]$1308 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] }
+ assign $1\jtag_wb_datasr_reg$next[63:0]$1348 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] }
case
- assign $1\jtag_wb_datasr_reg$next[63:0]$1308 \jtag_wb_datasr_reg
+ assign $1\jtag_wb_datasr_reg$next[63:0]$1348 \jtag_wb_datasr_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561"
switch \jtag_wb_datasr_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\jtag_wb_datasr_reg$next[63:0]$1309 \jtag_wb_datasr__i
+ assign $2\jtag_wb_datasr_reg$next[63:0]$1349 \jtag_wb_datasr__i
case
- assign $2\jtag_wb_datasr_reg$next[63:0]$1309 $1\jtag_wb_datasr_reg$next[63:0]$1308
+ assign $2\jtag_wb_datasr_reg$next[63:0]$1349 $1\jtag_wb_datasr_reg$next[63:0]$1348
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\jtag_wb_datasr_reg$next[63:0]$1310 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\jtag_wb_datasr_reg$next[63:0]$1350 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\jtag_wb_datasr_reg$next[63:0]$1310 $2\jtag_wb_datasr_reg$next[63:0]$1309
+ assign $3\jtag_wb_datasr_reg$next[63:0]$1350 $2\jtag_wb_datasr_reg$next[63:0]$1349
end
sync always
- update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$1307
+ update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$1347
end
- attribute \src "libresoc.v:44423.3-44431.6"
- process $proc$libresoc.v:44423$1311
+ attribute \src "libresoc.v:44614.3-44622.6"
+ process $proc$libresoc.v:44614$1351
assign { } { }
assign { } { }
- assign $0\dmi0_addrsr_update_core$next[0:0]$1312 $1\dmi0_addrsr_update_core$next[0:0]$1313
- attribute \src "libresoc.v:44424.5-44424.29"
+ assign $0\dmi0_addrsr_update_core$next[0:0]$1352 $1\dmi0_addrsr_update_core$next[0:0]$1353
+ attribute \src "libresoc.v:44615.5-44615.29"
switch \initial
- attribute \src "libresoc.v:44424.9-44424.17"
+ attribute \src "libresoc.v:44615.9-44615.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_addrsr_update_core$next[0:0]$1313 1'0
+ assign $1\dmi0_addrsr_update_core$next[0:0]$1353 1'0
case
- assign $1\dmi0_addrsr_update_core$next[0:0]$1313 \dmi0_addrsr_update
+ assign $1\dmi0_addrsr_update_core$next[0:0]$1353 \dmi0_addrsr_update
end
sync always
- update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$1312
+ update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$1352
end
- attribute \src "libresoc.v:44432.3-44440.6"
- process $proc$libresoc.v:44432$1314
+ attribute \src "libresoc.v:44623.3-44631.6"
+ process $proc$libresoc.v:44623$1354
assign { } { }
assign { } { }
- assign $0\dmi0_addrsr_update_core_prev$next[0:0]$1315 $1\dmi0_addrsr_update_core_prev$next[0:0]$1316
- attribute \src "libresoc.v:44433.5-44433.29"
+ assign $0\dmi0_addrsr_update_core_prev$next[0:0]$1355 $1\dmi0_addrsr_update_core_prev$next[0:0]$1356
+ attribute \src "libresoc.v:44624.5-44624.29"
switch \initial
- attribute \src "libresoc.v:44433.9-44433.17"
+ attribute \src "libresoc.v:44624.9-44624.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1316 1'0
+ assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1356 1'0
case
- assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1316 \dmi0_addrsr_update_core
+ assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1356 \dmi0_addrsr_update_core
end
sync always
- update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$1315
+ update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$1355
end
- attribute \src "libresoc.v:44441.3-44457.6"
- process $proc$libresoc.v:44441$1317
+ attribute \src "libresoc.v:44632.3-44648.6"
+ process $proc$libresoc.v:44632$1357
assign { } { }
assign { } { }
- assign $0\dmi0_addrsr__oe$next[0:0]$1318 $2\dmi0_addrsr__oe$next[0:0]$1320
- attribute \src "libresoc.v:44442.5-44442.29"
+ assign $0\dmi0_addrsr__oe$next[0:0]$1358 $2\dmi0_addrsr__oe$next[0:0]$1360
+ attribute \src "libresoc.v:44633.5-44633.29"
switch \initial
- attribute \src "libresoc.v:44442.9-44442.17"
+ attribute \src "libresoc.v:44633.9-44633.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_addrsr__oe$next[0:0]$1319 \dmi0_addrsr_isir
+ assign $1\dmi0_addrsr__oe$next[0:0]$1359 \dmi0_addrsr_isir
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $1\dmi0_addrsr__oe$next[0:0]$1319 1'0
+ assign $1\dmi0_addrsr__oe$next[0:0]$1359 1'0
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_addrsr__oe$next[0:0]$1320 1'0
+ assign $2\dmi0_addrsr__oe$next[0:0]$1360 1'0
case
- assign $2\dmi0_addrsr__oe$next[0:0]$1320 $1\dmi0_addrsr__oe$next[0:0]$1319
+ assign $2\dmi0_addrsr__oe$next[0:0]$1360 $1\dmi0_addrsr__oe$next[0:0]$1359
end
sync always
- update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$1318
+ update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$1358
end
- attribute \src "libresoc.v:44458.3-44478.6"
- process $proc$libresoc.v:44458$1321
+ attribute \src "libresoc.v:44649.3-44669.6"
+ process $proc$libresoc.v:44649$1361
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\dmi0_addrsr_reg$next[7:0]$1322 $3\dmi0_addrsr_reg$next[7:0]$1325
- attribute \src "libresoc.v:44459.5-44459.29"
+ assign $0\dmi0_addrsr_reg$next[7:0]$1362 $3\dmi0_addrsr_reg$next[7:0]$1365
+ attribute \src "libresoc.v:44650.5-44650.29"
switch \initial
- attribute \src "libresoc.v:44459.9-44459.17"
+ attribute \src "libresoc.v:44650.9-44650.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dmi0_addrsr_reg$next[7:0]$1323 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] }
+ assign $1\dmi0_addrsr_reg$next[7:0]$1363 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] }
case
- assign $1\dmi0_addrsr_reg$next[7:0]$1323 \dmi0_addrsr_reg
+ assign $1\dmi0_addrsr_reg$next[7:0]$1363 \dmi0_addrsr_reg
end
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561"
switch \dmi0_addrsr_capture
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dmi0_addrsr_reg$next[7:0]$1324 \dmi0_addrsr__i
+ assign $2\dmi0_addrsr_reg$next[7:0]$1364 \dmi0_addrsr__i
case
- assign $2\dmi0_addrsr_reg$next[7:0]$1324 $1\dmi0_addrsr_reg$next[7:0]$1323
+ assign $2\dmi0_addrsr_reg$next[7:0]$1364 $1\dmi0_addrsr_reg$next[7:0]$1363
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \posjtag_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dmi0_addrsr_reg$next[7:0]$1325 8'00000000
+ assign $3\dmi0_addrsr_reg$next[7:0]$1365 8'00000000
case
- assign $3\dmi0_addrsr_reg$next[7:0]$1325 $2\dmi0_addrsr_reg$next[7:0]$1324
+ assign $3\dmi0_addrsr_reg$next[7:0]$1365 $2\dmi0_addrsr_reg$next[7:0]$1364
end
sync always
- update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$1322
+ update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$1362
end
- attribute \src "libresoc.v:44479.3-44487.6"
- process $proc$libresoc.v:44479$1326
+ attribute \src "libresoc.v:44670.3-44678.6"
+ process $proc$libresoc.v:44670$1366
assign { } { }
assign { } { }
- assign $0\dmi0_datasr_update_core$next[0:0]$1327 $1\dmi0_datasr_update_core$next[0:0]$1328
- attribute \src "libresoc.v:44480.5-44480.29"
+ assign $0\dmi0_datasr_update_core$next[0:0]$1367 $1\dmi0_datasr_update_core$next[0:0]$1368
+ attribute \src "libresoc.v:44671.5-44671.29"
switch \initial
- attribute \src "libresoc.v:44480.9-44480.17"
+ attribute \src "libresoc.v:44671.9-44671.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\dmi0_datasr_update_core$next[0:0]$1328 1'0
- case
- assign $1\dmi0_datasr_update_core$next[0:0]$1328 \dmi0_datasr_update
- end
- sync always
- update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$1327
- end
- connect \$9 $eq$libresoc.v:43573$1024_Y
- connect \$99 $ternary$libresoc.v:43574$1025_Y
- connect \$101 $ternary$libresoc.v:43575$1026_Y
- connect \$103 $ternary$libresoc.v:43576$1027_Y
- connect \$105 $ternary$libresoc.v:43577$1028_Y
- connect \$107 $ternary$libresoc.v:43578$1029_Y
- connect \$109 $ternary$libresoc.v:43579$1030_Y
- connect \$111 $ternary$libresoc.v:43580$1031_Y
- connect \$113 $ternary$libresoc.v:43581$1032_Y
- connect \$115 $ternary$libresoc.v:43582$1033_Y
- connect \$117 $ternary$libresoc.v:43583$1034_Y
- connect \$11 $eq$libresoc.v:43584$1035_Y
- connect \$119 $ternary$libresoc.v:43585$1036_Y
- connect \$121 $ternary$libresoc.v:43586$1037_Y
- connect \$123 $ternary$libresoc.v:43587$1038_Y
- connect \$125 $ternary$libresoc.v:43588$1039_Y
- connect \$127 $ternary$libresoc.v:43589$1040_Y
- connect \$129 $ternary$libresoc.v:43590$1041_Y
- connect \$131 $ternary$libresoc.v:43591$1042_Y
- connect \$133 $ternary$libresoc.v:43592$1043_Y
- connect \$135 $ternary$libresoc.v:43593$1044_Y
- connect \$137 $ternary$libresoc.v:43594$1045_Y
- connect \$13 $or$libresoc.v:43595$1046_Y
- connect \$139 $ternary$libresoc.v:43596$1047_Y
- connect \$141 $eq$libresoc.v:43597$1048_Y
- connect \$143 $eq$libresoc.v:43598$1049_Y
- connect \$145 $or$libresoc.v:43599$1050_Y
- connect \$147 $and$libresoc.v:43600$1051_Y
- connect \$149 $eq$libresoc.v:43601$1052_Y
- connect \$151 $eq$libresoc.v:43602$1053_Y
- connect \$153 $or$libresoc.v:43603$1054_Y
- connect \$155 $eq$libresoc.v:43604$1055_Y
- connect \$157 $or$libresoc.v:43605$1056_Y
- connect \$15 $eq$libresoc.v:43606$1057_Y
- connect \$159 $and$libresoc.v:43607$1058_Y
- connect \$161 $eq$libresoc.v:43608$1059_Y
- connect \$163 $ne$libresoc.v:43609$1060_Y
- connect \$165 $and$libresoc.v:43610$1061_Y
- connect \$167 $ne$libresoc.v:43611$1062_Y
- connect \$169 $and$libresoc.v:43612$1063_Y
- connect \$171 $ne$libresoc.v:43613$1064_Y
- connect \$173 $and$libresoc.v:43614$1065_Y
- connect \$175 $not$libresoc.v:43615$1066_Y
- connect \$177 $and$libresoc.v:43616$1067_Y
- connect \$17 $or$libresoc.v:43617$1068_Y
- connect \$179 $eq$libresoc.v:43618$1069_Y
- connect \$181 $ne$libresoc.v:43619$1070_Y
- connect \$183 $and$libresoc.v:43620$1071_Y
- connect \$185 $ne$libresoc.v:43621$1072_Y
- connect \$187 $and$libresoc.v:43622$1073_Y
- connect \$189 $ne$libresoc.v:43623$1074_Y
- connect \$191 $and$libresoc.v:43624$1075_Y
- connect \$193 $not$libresoc.v:43625$1076_Y
- connect \$195 $and$libresoc.v:43626$1077_Y
- connect \$197 $eq$libresoc.v:43627$1078_Y
- connect \$1 $eq$libresoc.v:43628$1079_Y
- connect \$19 $and$libresoc.v:43629$1080_Y
- connect \$199 $eq$libresoc.v:43630$1081_Y
- connect \$201 $ne$libresoc.v:43631$1082_Y
- connect \$203 $and$libresoc.v:43632$1083_Y
- connect \$205 $ne$libresoc.v:43633$1084_Y
- connect \$207 $and$libresoc.v:43634$1085_Y
- connect \$209 $ne$libresoc.v:43635$1086_Y
- connect \$211 $and$libresoc.v:43636$1087_Y
- connect \$213 $not$libresoc.v:43637$1088_Y
- connect \$215 $and$libresoc.v:43638$1089_Y
- connect \$217 $eq$libresoc.v:43639$1090_Y
- connect \$21 $and$libresoc.v:43640$1091_Y
- connect \$219 $ne$libresoc.v:43641$1092_Y
- connect \$221 $and$libresoc.v:43642$1093_Y
- connect \$223 $ne$libresoc.v:43643$1094_Y
- connect \$225 $and$libresoc.v:43644$1095_Y
- connect \$227 $ne$libresoc.v:43645$1096_Y
- connect \$229 $and$libresoc.v:43646$1097_Y
- connect \$231 $not$libresoc.v:43647$1098_Y
- connect \$233 $and$libresoc.v:43648$1099_Y
- connect \$235 $eq$libresoc.v:43649$1100_Y
- connect \$237 $eq$libresoc.v:43650$1101_Y
- connect \$23 $eq$libresoc.v:43651$1102_Y
- connect \$239 $ne$libresoc.v:43652$1103_Y
- connect \$241 $and$libresoc.v:43653$1104_Y
- connect \$243 $ne$libresoc.v:43654$1105_Y
- connect \$245 $and$libresoc.v:43655$1106_Y
- connect \$247 $ne$libresoc.v:43656$1107_Y
- connect \$249 $and$libresoc.v:43657$1108_Y
- connect \$251 $not$libresoc.v:43658$1109_Y
- connect \$253 $and$libresoc.v:43659$1110_Y
- connect \$256 $eq$libresoc.v:43660$1111_Y
- connect \$255 $not$libresoc.v:43661$1112_Y
- connect \$25 $eq$libresoc.v:43662$1113_Y
- connect \$259 $eq$libresoc.v:43663$1114_Y
- connect \$261 $eq$libresoc.v:43664$1115_Y
- connect \$263 $or$libresoc.v:43665$1116_Y
- connect \$265 $eq$libresoc.v:43666$1117_Y
- connect \$268 $add$libresoc.v:43667$1118_Y
- connect \$271 $add$libresoc.v:43668$1119_Y
- connect \$273 $pos$libresoc.v:43669$1121_Y
- connect \$276 $eq$libresoc.v:43670$1122_Y
- connect \$278 $eq$libresoc.v:43671$1123_Y
- connect \$27 $or$libresoc.v:43672$1124_Y
- connect \$280 $or$libresoc.v:43673$1125_Y
- connect \$282 $eq$libresoc.v:43674$1126_Y
- connect \$285 $add$libresoc.v:43675$1127_Y
- connect \$288 $add$libresoc.v:43676$1128_Y
- connect \$29 $eq$libresoc.v:43677$1129_Y
- connect \$31 $or$libresoc.v:43678$1130_Y
- connect \$33 $and$libresoc.v:43679$1131_Y
- connect \$35 $and$libresoc.v:43680$1132_Y
- connect \$37 $eq$libresoc.v:43681$1133_Y
- connect \$3 $eq$libresoc.v:43682$1134_Y
- connect \$39 $eq$libresoc.v:43683$1135_Y
- connect \$41 $ternary$libresoc.v:43684$1136_Y
- connect \$43 $ternary$libresoc.v:43685$1137_Y
- connect \$45 $ternary$libresoc.v:43686$1138_Y
- connect \$47 $ternary$libresoc.v:43687$1139_Y
- connect \$49 $ternary$libresoc.v:43688$1140_Y
- connect \$51 $ternary$libresoc.v:43689$1141_Y
- connect \$53 $ternary$libresoc.v:43690$1142_Y
- connect \$55 $ternary$libresoc.v:43691$1143_Y
- connect \$57 $ternary$libresoc.v:43692$1144_Y
- connect \$5 $or$libresoc.v:43693$1145_Y
- connect \$59 $ternary$libresoc.v:43694$1146_Y
- connect \$61 $ternary$libresoc.v:43695$1147_Y
- connect \$63 $ternary$libresoc.v:43696$1148_Y
- connect \$65 $ternary$libresoc.v:43697$1149_Y
- connect \$67 $ternary$libresoc.v:43698$1150_Y
- connect \$69 $ternary$libresoc.v:43699$1151_Y
- connect \$71 $ternary$libresoc.v:43700$1152_Y
- connect \$73 $ternary$libresoc.v:43701$1153_Y
- connect \$75 $ternary$libresoc.v:43702$1154_Y
- connect \$77 $ternary$libresoc.v:43703$1155_Y
- connect \$7 $and$libresoc.v:43704$1156_Y
- connect \$79 $ternary$libresoc.v:43705$1157_Y
- connect \$81 $ternary$libresoc.v:43706$1158_Y
- connect \$83 $ternary$libresoc.v:43707$1159_Y
- connect \$85 $ternary$libresoc.v:43708$1160_Y
- connect \$87 $ternary$libresoc.v:43709$1161_Y
- connect \$89 $ternary$libresoc.v:43710$1162_Y
- connect \$91 $ternary$libresoc.v:43711$1163_Y
- connect \$93 $ternary$libresoc.v:43712$1164_Y
- connect \$95 $ternary$libresoc.v:43713$1165_Y
- connect \$97 $ternary$libresoc.v:43714$1166_Y
+ switch \intclk_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\dmi0_datasr_update_core$next[0:0]$1368 1'0
+ case
+ assign $1\dmi0_datasr_update_core$next[0:0]$1368 \dmi0_datasr_update
+ end
+ sync always
+ update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$1367
+ end
+ connect \$9 $eq$libresoc.v:43764$1064_Y
+ connect \$99 $ternary$libresoc.v:43765$1065_Y
+ connect \$101 $ternary$libresoc.v:43766$1066_Y
+ connect \$103 $ternary$libresoc.v:43767$1067_Y
+ connect \$105 $ternary$libresoc.v:43768$1068_Y
+ connect \$107 $ternary$libresoc.v:43769$1069_Y
+ connect \$109 $ternary$libresoc.v:43770$1070_Y
+ connect \$111 $ternary$libresoc.v:43771$1071_Y
+ connect \$113 $ternary$libresoc.v:43772$1072_Y
+ connect \$115 $ternary$libresoc.v:43773$1073_Y
+ connect \$117 $ternary$libresoc.v:43774$1074_Y
+ connect \$11 $eq$libresoc.v:43775$1075_Y
+ connect \$119 $ternary$libresoc.v:43776$1076_Y
+ connect \$121 $ternary$libresoc.v:43777$1077_Y
+ connect \$123 $ternary$libresoc.v:43778$1078_Y
+ connect \$125 $ternary$libresoc.v:43779$1079_Y
+ connect \$127 $ternary$libresoc.v:43780$1080_Y
+ connect \$129 $ternary$libresoc.v:43781$1081_Y
+ connect \$131 $ternary$libresoc.v:43782$1082_Y
+ connect \$133 $ternary$libresoc.v:43783$1083_Y
+ connect \$135 $ternary$libresoc.v:43784$1084_Y
+ connect \$137 $ternary$libresoc.v:43785$1085_Y
+ connect \$13 $or$libresoc.v:43786$1086_Y
+ connect \$139 $ternary$libresoc.v:43787$1087_Y
+ connect \$141 $eq$libresoc.v:43788$1088_Y
+ connect \$143 $eq$libresoc.v:43789$1089_Y
+ connect \$145 $or$libresoc.v:43790$1090_Y
+ connect \$147 $and$libresoc.v:43791$1091_Y
+ connect \$149 $eq$libresoc.v:43792$1092_Y
+ connect \$151 $eq$libresoc.v:43793$1093_Y
+ connect \$153 $or$libresoc.v:43794$1094_Y
+ connect \$155 $eq$libresoc.v:43795$1095_Y
+ connect \$157 $or$libresoc.v:43796$1096_Y
+ connect \$15 $eq$libresoc.v:43797$1097_Y
+ connect \$159 $and$libresoc.v:43798$1098_Y
+ connect \$161 $eq$libresoc.v:43799$1099_Y
+ connect \$163 $ne$libresoc.v:43800$1100_Y
+ connect \$165 $and$libresoc.v:43801$1101_Y
+ connect \$167 $ne$libresoc.v:43802$1102_Y
+ connect \$169 $and$libresoc.v:43803$1103_Y
+ connect \$171 $ne$libresoc.v:43804$1104_Y
+ connect \$173 $and$libresoc.v:43805$1105_Y
+ connect \$175 $not$libresoc.v:43806$1106_Y
+ connect \$177 $and$libresoc.v:43807$1107_Y
+ connect \$17 $or$libresoc.v:43808$1108_Y
+ connect \$179 $eq$libresoc.v:43809$1109_Y
+ connect \$181 $ne$libresoc.v:43810$1110_Y
+ connect \$183 $and$libresoc.v:43811$1111_Y
+ connect \$185 $ne$libresoc.v:43812$1112_Y
+ connect \$187 $and$libresoc.v:43813$1113_Y
+ connect \$189 $ne$libresoc.v:43814$1114_Y
+ connect \$191 $and$libresoc.v:43815$1115_Y
+ connect \$193 $not$libresoc.v:43816$1116_Y
+ connect \$195 $and$libresoc.v:43817$1117_Y
+ connect \$197 $eq$libresoc.v:43818$1118_Y
+ connect \$1 $eq$libresoc.v:43819$1119_Y
+ connect \$19 $and$libresoc.v:43820$1120_Y
+ connect \$199 $eq$libresoc.v:43821$1121_Y
+ connect \$201 $ne$libresoc.v:43822$1122_Y
+ connect \$203 $and$libresoc.v:43823$1123_Y
+ connect \$205 $ne$libresoc.v:43824$1124_Y
+ connect \$207 $and$libresoc.v:43825$1125_Y
+ connect \$209 $ne$libresoc.v:43826$1126_Y
+ connect \$211 $and$libresoc.v:43827$1127_Y
+ connect \$213 $not$libresoc.v:43828$1128_Y
+ connect \$215 $and$libresoc.v:43829$1129_Y
+ connect \$217 $eq$libresoc.v:43830$1130_Y
+ connect \$21 $and$libresoc.v:43831$1131_Y
+ connect \$219 $ne$libresoc.v:43832$1132_Y
+ connect \$221 $and$libresoc.v:43833$1133_Y
+ connect \$223 $ne$libresoc.v:43834$1134_Y
+ connect \$225 $and$libresoc.v:43835$1135_Y
+ connect \$227 $ne$libresoc.v:43836$1136_Y
+ connect \$229 $and$libresoc.v:43837$1137_Y
+ connect \$231 $not$libresoc.v:43838$1138_Y
+ connect \$233 $and$libresoc.v:43839$1139_Y
+ connect \$235 $eq$libresoc.v:43840$1140_Y
+ connect \$237 $eq$libresoc.v:43841$1141_Y
+ connect \$23 $eq$libresoc.v:43842$1142_Y
+ connect \$239 $ne$libresoc.v:43843$1143_Y
+ connect \$241 $and$libresoc.v:43844$1144_Y
+ connect \$243 $ne$libresoc.v:43845$1145_Y
+ connect \$245 $and$libresoc.v:43846$1146_Y
+ connect \$247 $ne$libresoc.v:43847$1147_Y
+ connect \$249 $and$libresoc.v:43848$1148_Y
+ connect \$251 $not$libresoc.v:43849$1149_Y
+ connect \$253 $and$libresoc.v:43850$1150_Y
+ connect \$256 $eq$libresoc.v:43851$1151_Y
+ connect \$255 $not$libresoc.v:43852$1152_Y
+ connect \$25 $eq$libresoc.v:43853$1153_Y
+ connect \$259 $eq$libresoc.v:43854$1154_Y
+ connect \$261 $eq$libresoc.v:43855$1155_Y
+ connect \$263 $or$libresoc.v:43856$1156_Y
+ connect \$265 $eq$libresoc.v:43857$1157_Y
+ connect \$268 $add$libresoc.v:43858$1158_Y
+ connect \$271 $add$libresoc.v:43859$1159_Y
+ connect \$273 $pos$libresoc.v:43860$1161_Y
+ connect \$276 $eq$libresoc.v:43861$1162_Y
+ connect \$278 $eq$libresoc.v:43862$1163_Y
+ connect \$27 $or$libresoc.v:43863$1164_Y
+ connect \$280 $or$libresoc.v:43864$1165_Y
+ connect \$282 $eq$libresoc.v:43865$1166_Y
+ connect \$285 $add$libresoc.v:43866$1167_Y
+ connect \$288 $add$libresoc.v:43867$1168_Y
+ connect \$29 $eq$libresoc.v:43868$1169_Y
+ connect \$31 $or$libresoc.v:43869$1170_Y
+ connect \$33 $and$libresoc.v:43870$1171_Y
+ connect \$35 $and$libresoc.v:43871$1172_Y
+ connect \$37 $eq$libresoc.v:43872$1173_Y
+ connect \$3 $eq$libresoc.v:43873$1174_Y
+ connect \$39 $eq$libresoc.v:43874$1175_Y
+ connect \$41 $ternary$libresoc.v:43875$1176_Y
+ connect \$43 $ternary$libresoc.v:43876$1177_Y
+ connect \$45 $ternary$libresoc.v:43877$1178_Y
+ connect \$47 $ternary$libresoc.v:43878$1179_Y
+ connect \$49 $ternary$libresoc.v:43879$1180_Y
+ connect \$51 $ternary$libresoc.v:43880$1181_Y
+ connect \$53 $ternary$libresoc.v:43881$1182_Y
+ connect \$55 $ternary$libresoc.v:43882$1183_Y
+ connect \$57 $ternary$libresoc.v:43883$1184_Y
+ connect \$5 $or$libresoc.v:43884$1185_Y
+ connect \$59 $ternary$libresoc.v:43885$1186_Y
+ connect \$61 $ternary$libresoc.v:43886$1187_Y
+ connect \$63 $ternary$libresoc.v:43887$1188_Y
+ connect \$65 $ternary$libresoc.v:43888$1189_Y
+ connect \$67 $ternary$libresoc.v:43889$1190_Y
+ connect \$69 $ternary$libresoc.v:43890$1191_Y
+ connect \$71 $ternary$libresoc.v:43891$1192_Y
+ connect \$73 $ternary$libresoc.v:43892$1193_Y
+ connect \$75 $ternary$libresoc.v:43893$1194_Y
+ connect \$77 $ternary$libresoc.v:43894$1195_Y
+ connect \$7 $and$libresoc.v:43895$1196_Y
+ connect \$79 $ternary$libresoc.v:43896$1197_Y
+ connect \$81 $ternary$libresoc.v:43897$1198_Y
+ connect \$83 $ternary$libresoc.v:43898$1199_Y
+ connect \$85 $ternary$libresoc.v:43899$1200_Y
+ connect \$87 $ternary$libresoc.v:43900$1201_Y
+ connect \$89 $ternary$libresoc.v:43901$1202_Y
+ connect \$91 $ternary$libresoc.v:43902$1203_Y
+ connect \$93 $ternary$libresoc.v:43903$1204_Y
+ connect \$95 $ternary$libresoc.v:43904$1205_Y
+ connect \$97 $ternary$libresoc.v:43905$1206_Y
connect \$267 \$268
connect \$270 \$271
connect \$284 \$285
connect \io_shift \$21
connect \io_capture \$7
end
-attribute \src "ls180.v:4.1-10282.10"
+attribute \src "ls180.v:4.1-10347.10"
attribute \cells_not_processed 1
module \ls180
- attribute \src "ls180.v:9977.1-9987.4"
- wire width 7 $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683
- attribute \src "ls180.v:9977.1-9987.4"
- wire width 32 $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684
- attribute \src "ls180.v:9977.1-9987.4"
- wire width 32 $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685
- attribute \src "ls180.v:9977.1-9987.4"
- wire width 7 $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686
- attribute \src "ls180.v:9977.1-9987.4"
- wire width 32 $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687
- attribute \src "ls180.v:9977.1-9987.4"
- wire width 32 $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688
- attribute \src "ls180.v:9977.1-9987.4"
- wire width 7 $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689
- attribute \src "ls180.v:9977.1-9987.4"
- wire width 32 $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690
- attribute \src "ls180.v:9977.1-9987.4"
- wire width 32 $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691
- attribute \src "ls180.v:9977.1-9987.4"
- wire width 7 $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692
- attribute \src "ls180.v:9977.1-9987.4"
- wire width 32 $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693
- attribute \src "ls180.v:9977.1-9987.4"
- wire width 32 $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694
- attribute \src "ls180.v:9997.1-10001.4"
- wire width 3 $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697
- attribute \src "ls180.v:9997.1-10001.4"
- wire width 25 $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698
- attribute \src "ls180.v:9997.1-10001.4"
- wire width 25 $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699
- attribute \src "ls180.v:10011.1-10015.4"
- wire width 3 $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704
- attribute \src "ls180.v:10011.1-10015.4"
- wire width 25 $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705
- attribute \src "ls180.v:10011.1-10015.4"
- wire width 25 $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706
- attribute \src "ls180.v:10025.1-10029.4"
- wire width 3 $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711
- attribute \src "ls180.v:10025.1-10029.4"
- wire width 25 $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712
- attribute \src "ls180.v:10025.1-10029.4"
- wire width 25 $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713
- attribute \src "ls180.v:10039.1-10043.4"
- wire width 3 $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718
- attribute \src "ls180.v:10039.1-10043.4"
- wire width 25 $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719
- attribute \src "ls180.v:10039.1-10043.4"
- wire width 25 $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720
- attribute \src "ls180.v:10054.1-10058.4"
- wire width 4 $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725
- attribute \src "ls180.v:10054.1-10058.4"
- wire width 10 $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726
- attribute \src "ls180.v:10054.1-10058.4"
- wire width 10 $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727
- attribute \src "ls180.v:10071.1-10075.4"
- wire width 4 $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732
- attribute \src "ls180.v:10071.1-10075.4"
- wire width 10 $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733
- attribute \src "ls180.v:10071.1-10075.4"
- wire width 10 $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734
- attribute \src "ls180.v:10087.1-10091.4"
- wire width 5 $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739
- attribute \src "ls180.v:10087.1-10091.4"
- wire width 10 $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740
- attribute \src "ls180.v:10087.1-10091.4"
- wire width 10 $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741
- attribute \src "ls180.v:10101.1-10105.4"
- wire width 5 $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746
- attribute \src "ls180.v:10101.1-10105.4"
- wire width 10 $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747
- attribute \src "ls180.v:10101.1-10105.4"
- wire width 10 $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:10040.1-10050.4"
+ wire width 7 $0$memwr$\mem$ls180.v:10042$1_ADDR[6:0]$2693
+ attribute \src "ls180.v:10040.1-10050.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10042$1_DATA[31:0]$2694
+ attribute \src "ls180.v:10040.1-10050.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10042$1_EN[31:0]$2695
+ attribute \src "ls180.v:10040.1-10050.4"
+ wire width 7 $0$memwr$\mem$ls180.v:10044$2_ADDR[6:0]$2696
+ attribute \src "ls180.v:10040.1-10050.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10044$2_DATA[31:0]$2697
+ attribute \src "ls180.v:10040.1-10050.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10044$2_EN[31:0]$2698
+ attribute \src "ls180.v:10040.1-10050.4"
+ wire width 7 $0$memwr$\mem$ls180.v:10046$3_ADDR[6:0]$2699
+ attribute \src "ls180.v:10040.1-10050.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10046$3_DATA[31:0]$2700
+ attribute \src "ls180.v:10040.1-10050.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10046$3_EN[31:0]$2701
+ attribute \src "ls180.v:10040.1-10050.4"
+ wire width 7 $0$memwr$\mem$ls180.v:10048$4_ADDR[6:0]$2702
+ attribute \src "ls180.v:10040.1-10050.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10048$4_DATA[31:0]$2703
+ attribute \src "ls180.v:10040.1-10050.4"
+ wire width 32 $0$memwr$\mem$ls180.v:10048$4_EN[31:0]$2704
+ attribute \src "ls180.v:10060.1-10064.4"
+ wire width 3 $0$memwr$\storage$ls180.v:10062$5_ADDR[2:0]$2707
+ attribute \src "ls180.v:10060.1-10064.4"
+ wire width 25 $0$memwr$\storage$ls180.v:10062$5_DATA[24:0]$2708
+ attribute \src "ls180.v:10060.1-10064.4"
+ wire width 25 $0$memwr$\storage$ls180.v:10062$5_EN[24:0]$2709
+ attribute \src "ls180.v:10074.1-10078.4"
+ wire width 3 $0$memwr$\storage_1$ls180.v:10076$6_ADDR[2:0]$2714
+ attribute \src "ls180.v:10074.1-10078.4"
+ wire width 25 $0$memwr$\storage_1$ls180.v:10076$6_DATA[24:0]$2715
+ attribute \src "ls180.v:10074.1-10078.4"
+ wire width 25 $0$memwr$\storage_1$ls180.v:10076$6_EN[24:0]$2716
+ attribute \src "ls180.v:10088.1-10092.4"
+ wire width 3 $0$memwr$\storage_2$ls180.v:10090$7_ADDR[2:0]$2721
+ attribute \src "ls180.v:10088.1-10092.4"
+ wire width 25 $0$memwr$\storage_2$ls180.v:10090$7_DATA[24:0]$2722
+ attribute \src "ls180.v:10088.1-10092.4"
+ wire width 25 $0$memwr$\storage_2$ls180.v:10090$7_EN[24:0]$2723
+ attribute \src "ls180.v:10102.1-10106.4"
+ wire width 3 $0$memwr$\storage_3$ls180.v:10104$8_ADDR[2:0]$2728
+ attribute \src "ls180.v:10102.1-10106.4"
+ wire width 25 $0$memwr$\storage_3$ls180.v:10104$8_DATA[24:0]$2729
+ attribute \src "ls180.v:10102.1-10106.4"
+ wire width 25 $0$memwr$\storage_3$ls180.v:10104$8_EN[24:0]$2730
+ attribute \src "ls180.v:10117.1-10121.4"
+ wire width 4 $0$memwr$\storage_4$ls180.v:10119$9_ADDR[3:0]$2735
+ attribute \src "ls180.v:10117.1-10121.4"
+ wire width 10 $0$memwr$\storage_4$ls180.v:10119$9_DATA[9:0]$2736
+ attribute \src "ls180.v:10117.1-10121.4"
+ wire width 10 $0$memwr$\storage_4$ls180.v:10119$9_EN[9:0]$2737
+ attribute \src "ls180.v:10134.1-10138.4"
+ wire width 4 $0$memwr$\storage_5$ls180.v:10136$10_ADDR[3:0]$2742
+ attribute \src "ls180.v:10134.1-10138.4"
+ wire width 10 $0$memwr$\storage_5$ls180.v:10136$10_DATA[9:0]$2743
+ attribute \src "ls180.v:10134.1-10138.4"
+ wire width 10 $0$memwr$\storage_5$ls180.v:10136$10_EN[9:0]$2744
+ attribute \src "ls180.v:10150.1-10154.4"
+ wire width 5 $0$memwr$\storage_6$ls180.v:10152$11_ADDR[4:0]$2749
+ attribute \src "ls180.v:10150.1-10154.4"
+ wire width 10 $0$memwr$\storage_6$ls180.v:10152$11_DATA[9:0]$2750
+ attribute \src "ls180.v:10150.1-10154.4"
+ wire width 10 $0$memwr$\storage_6$ls180.v:10152$11_EN[9:0]$2751
+ attribute \src "ls180.v:10164.1-10168.4"
+ wire width 5 $0$memwr$\storage_7$ls180.v:10166$12_ADDR[4:0]$2756
+ attribute \src "ls180.v:10164.1-10168.4"
+ wire width 10 $0$memwr$\storage_7$ls180.v:10166$12_DATA[9:0]$2757
+ attribute \src "ls180.v:10164.1-10168.4"
+ wire width 10 $0$memwr$\storage_7$ls180.v:10166$12_EN[9:0]$2758
+ attribute \src "ls180.v:3206.1-3299.4"
wire width 3 $0\builder_bankmachine0_next_state[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\builder_bankmachine0_state[2:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire width 3 $0\builder_bankmachine1_next_state[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\builder_bankmachine1_state[2:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire width 3 $0\builder_bankmachine2_next_state[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\builder_bankmachine2_state[2:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire width 3 $0\builder_bankmachine3_next_state[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\builder_bankmachine3_state[2:0]
- attribute \src "ls180.v:6448.1-6464.4"
+ attribute \src "ls180.v:6500.1-6516.4"
wire $0\builder_comb_rhs_array_muxed0[0:0]
- attribute \src "ls180.v:6669.1-6685.4"
+ attribute \src "ls180.v:6721.1-6737.4"
wire $0\builder_comb_rhs_array_muxed10[0:0]
- attribute \src "ls180.v:6686.1-6702.4"
+ attribute \src "ls180.v:6738.1-6754.4"
wire $0\builder_comb_rhs_array_muxed11[0:0]
- attribute \src "ls180.v:6754.1-6761.4"
+ attribute \src "ls180.v:6806.1-6813.4"
wire width 22 $0\builder_comb_rhs_array_muxed12[21:0]
- attribute \src "ls180.v:6762.1-6769.4"
+ attribute \src "ls180.v:6814.1-6821.4"
wire $0\builder_comb_rhs_array_muxed13[0:0]
- attribute \src "ls180.v:6770.1-6777.4"
+ attribute \src "ls180.v:6822.1-6829.4"
wire $0\builder_comb_rhs_array_muxed14[0:0]
- attribute \src "ls180.v:6778.1-6785.4"
+ attribute \src "ls180.v:6830.1-6837.4"
wire width 22 $0\builder_comb_rhs_array_muxed15[21:0]
- attribute \src "ls180.v:6786.1-6793.4"
+ attribute \src "ls180.v:6838.1-6845.4"
wire $0\builder_comb_rhs_array_muxed16[0:0]
- attribute \src "ls180.v:6794.1-6801.4"
+ attribute \src "ls180.v:6846.1-6853.4"
wire $0\builder_comb_rhs_array_muxed17[0:0]
- attribute \src "ls180.v:6802.1-6809.4"
+ attribute \src "ls180.v:6854.1-6861.4"
wire width 22 $0\builder_comb_rhs_array_muxed18[21:0]
- attribute \src "ls180.v:6810.1-6817.4"
+ attribute \src "ls180.v:6862.1-6869.4"
wire $0\builder_comb_rhs_array_muxed19[0:0]
- attribute \src "ls180.v:6465.1-6481.4"
+ attribute \src "ls180.v:6517.1-6533.4"
wire width 13 $0\builder_comb_rhs_array_muxed1[12:0]
- attribute \src "ls180.v:6818.1-6825.4"
+ attribute \src "ls180.v:6870.1-6877.4"
wire $0\builder_comb_rhs_array_muxed20[0:0]
- attribute \src "ls180.v:6826.1-6833.4"
+ attribute \src "ls180.v:6878.1-6885.4"
wire width 22 $0\builder_comb_rhs_array_muxed21[21:0]
- attribute \src "ls180.v:6834.1-6841.4"
+ attribute \src "ls180.v:6886.1-6893.4"
wire $0\builder_comb_rhs_array_muxed22[0:0]
- attribute \src "ls180.v:6842.1-6849.4"
+ attribute \src "ls180.v:6894.1-6901.4"
wire $0\builder_comb_rhs_array_muxed23[0:0]
- attribute \src "ls180.v:6850.1-6869.4"
+ attribute \src "ls180.v:6902.1-6921.4"
wire width 32 $0\builder_comb_rhs_array_muxed24[31:0]
- attribute \src "ls180.v:6870.1-6889.4"
+ attribute \src "ls180.v:6922.1-6941.4"
wire width 32 $0\builder_comb_rhs_array_muxed25[31:0]
- attribute \src "ls180.v:6890.1-6909.4"
+ attribute \src "ls180.v:6942.1-6961.4"
wire width 4 $0\builder_comb_rhs_array_muxed26[3:0]
- attribute \src "ls180.v:6910.1-6929.4"
+ attribute \src "ls180.v:6962.1-6981.4"
wire $0\builder_comb_rhs_array_muxed27[0:0]
- attribute \src "ls180.v:6930.1-6949.4"
+ attribute \src "ls180.v:6982.1-7001.4"
wire $0\builder_comb_rhs_array_muxed28[0:0]
- attribute \src "ls180.v:6950.1-6969.4"
+ attribute \src "ls180.v:7002.1-7021.4"
wire $0\builder_comb_rhs_array_muxed29[0:0]
- attribute \src "ls180.v:6482.1-6498.4"
+ attribute \src "ls180.v:6534.1-6550.4"
wire width 2 $0\builder_comb_rhs_array_muxed2[1:0]
- attribute \src "ls180.v:6970.1-6989.4"
+ attribute \src "ls180.v:7022.1-7041.4"
wire width 3 $0\builder_comb_rhs_array_muxed30[2:0]
- attribute \src "ls180.v:6990.1-7009.4"
+ attribute \src "ls180.v:7042.1-7061.4"
wire width 2 $0\builder_comb_rhs_array_muxed31[1:0]
- attribute \src "ls180.v:6499.1-6515.4"
+ attribute \src "ls180.v:6551.1-6567.4"
wire $0\builder_comb_rhs_array_muxed3[0:0]
- attribute \src "ls180.v:6516.1-6532.4"
+ attribute \src "ls180.v:6568.1-6584.4"
wire $0\builder_comb_rhs_array_muxed4[0:0]
- attribute \src "ls180.v:6533.1-6549.4"
+ attribute \src "ls180.v:6585.1-6601.4"
wire $0\builder_comb_rhs_array_muxed5[0:0]
- attribute \src "ls180.v:6601.1-6617.4"
+ attribute \src "ls180.v:6653.1-6669.4"
wire $0\builder_comb_rhs_array_muxed6[0:0]
- attribute \src "ls180.v:6618.1-6634.4"
+ attribute \src "ls180.v:6670.1-6686.4"
wire width 13 $0\builder_comb_rhs_array_muxed7[12:0]
- attribute \src "ls180.v:6635.1-6651.4"
+ attribute \src "ls180.v:6687.1-6703.4"
wire width 2 $0\builder_comb_rhs_array_muxed8[1:0]
- attribute \src "ls180.v:6652.1-6668.4"
+ attribute \src "ls180.v:6704.1-6720.4"
wire $0\builder_comb_rhs_array_muxed9[0:0]
- attribute \src "ls180.v:6550.1-6566.4"
+ attribute \src "ls180.v:6602.1-6618.4"
wire $0\builder_comb_t_array_muxed0[0:0]
- attribute \src "ls180.v:6567.1-6583.4"
+ attribute \src "ls180.v:6619.1-6635.4"
wire $0\builder_comb_t_array_muxed1[0:0]
- attribute \src "ls180.v:6584.1-6600.4"
+ attribute \src "ls180.v:6636.1-6652.4"
wire $0\builder_comb_t_array_muxed2[0:0]
- attribute \src "ls180.v:6703.1-6719.4"
+ attribute \src "ls180.v:6755.1-6771.4"
wire $0\builder_comb_t_array_muxed3[0:0]
- attribute \src "ls180.v:6720.1-6736.4"
+ attribute \src "ls180.v:6772.1-6788.4"
wire $0\builder_comb_t_array_muxed4[0:0]
- attribute \src "ls180.v:6737.1-6753.4"
+ attribute \src "ls180.v:6789.1-6805.4"
wire $0\builder_comb_t_array_muxed5[0:0]
- attribute \src "ls180.v:2739.1-2785.4"
+ attribute \src "ls180.v:2770.1-2816.4"
wire $0\builder_converter0_next_state[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_converter0_state[0:0]
- attribute \src "ls180.v:2799.1-2845.4"
+ attribute \src "ls180.v:2830.1-2876.4"
wire $0\builder_converter1_next_state[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_converter1_state[0:0]
- attribute \src "ls180.v:2859.1-2905.4"
+ attribute \src "ls180.v:2890.1-2936.4"
wire $0\builder_converter2_next_state[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_converter2_state[0:0]
- attribute \src "ls180.v:3992.1-4038.4"
+ attribute \src "ls180.v:4023.1-4069.4"
wire $0\builder_converter_next_state[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_converter_state[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 20 $0\builder_count[19:0]
- attribute \src "ls180.v:5705.1-5716.4"
+ attribute \src "ls180.v:5740.1-5751.4"
wire $0\builder_error[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\builder_grant[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0]
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 14 $0\builder_libresocsim_adr[13:0]
- attribute \src "ls180.v:5594.1-5630.4"
+ attribute \src "ls180.v:5629.1-5665.4"
wire width 14 $0\builder_libresocsim_adr_next_value1[13:0]
- attribute \src "ls180.v:5594.1-5630.4"
+ attribute \src "ls180.v:5629.1-5665.4"
wire $0\builder_libresocsim_adr_next_value_ce1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\builder_libresocsim_dat_w[7:0]
- attribute \src "ls180.v:5594.1-5630.4"
+ attribute \src "ls180.v:5629.1-5665.4"
wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0]
- attribute \src "ls180.v:5594.1-5630.4"
+ attribute \src "ls180.v:5629.1-5665.4"
wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_libresocsim_we[0:0]
- attribute \src "ls180.v:5594.1-5630.4"
+ attribute \src "ls180.v:5629.1-5665.4"
wire $0\builder_libresocsim_we_next_value2[0:0]
- attribute \src "ls180.v:5594.1-5630.4"
+ attribute \src "ls180.v:5629.1-5665.4"
wire $0\builder_libresocsim_we_next_value_ce2[0:0]
- attribute \src "ls180.v:5594.1-5630.4"
+ attribute \src "ls180.v:5629.1-5665.4"
wire $0\builder_libresocsim_wishbone_ack[0:0]
- attribute \src "ls180.v:5594.1-5630.4"
+ attribute \src "ls180.v:5629.1-5665.4"
wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0]
- attribute \src "ls180.v:1841.5-1841.44"
+ attribute \src "ls180.v:1857.5-1857.44"
wire $0\builder_libresocsim_wishbone_err[0:0]
- attribute \src "ls180.v:1730.5-1730.27"
+ attribute \src "ls180.v:1746.5-1746.27"
wire $0\builder_locked0[0:0]
- attribute \src "ls180.v:1731.5-1731.27"
+ attribute \src "ls180.v:1747.5-1747.27"
wire $0\builder_locked1[0:0]
- attribute \src "ls180.v:1732.5-1732.27"
+ attribute \src "ls180.v:1748.5-1748.27"
wire $0\builder_locked2[0:0]
- attribute \src "ls180.v:1733.5-1733.27"
+ attribute \src "ls180.v:1749.5-1749.27"
wire $0\builder_locked3[0:0]
- attribute \src "ls180.v:3864.1-3936.4"
+ attribute \src "ls180.v:3895.1-3967.4"
wire width 3 $0\builder_multiplexer_next_state[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\builder_multiplexer_state[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl0_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl0_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl10_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl10_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl11_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl11_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl12_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl12_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl13_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl13_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl14_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl14_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl15_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl15_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl16_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl16_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl1_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl1_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl2_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl2_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl3_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl3_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl4_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl4_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl5_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl5_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl6_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl6_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl7_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl7_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl8_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl8_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl9_regs0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_multiregimpl9_regs1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_new_master_rdata_valid0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_new_master_rdata_valid1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_new_master_rdata_valid2[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_new_master_rdata_valid3[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_new_master_wdata_ready[0:0]
- attribute \src "ls180.v:5594.1-5630.4"
+ attribute \src "ls180.v:5629.1-5665.4"
wire width 2 $0\builder_next_state[1:0]
- attribute \src "ls180.v:3081.1-3111.4"
+ attribute \src "ls180.v:3112.1-3142.4"
wire width 2 $0\builder_refresher_next_state[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\builder_refresher_state[1:0]
- attribute \src "ls180.v:5345.1-5384.4"
+ attribute \src "ls180.v:5380.1-5419.4"
wire width 2 $0\builder_sdblock2memdma_next_state[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\builder_sdblock2memdma_state[1:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_sdcore_crcupstreaminserter_state[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire width 3 $0\builder_sdcore_fsm_next_state[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\builder_sdcore_fsm_state[2:0]
- attribute \src "ls180.v:5404.1-5441.4"
+ attribute \src "ls180.v:5439.1-5476.4"
wire $0\builder_sdmem2blockdma_fsm_next_state[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_sdmem2blockdma_fsm_state[0:0]
- attribute \src "ls180.v:5442.1-5478.4"
+ attribute \src "ls180.v:5477.1-5513.4"
wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0]
- attribute \src "ls180.v:4587.1-4659.4"
+ attribute \src "ls180.v:4622.1-4694.4"
wire width 3 $0\builder_sdphy_fsm_next_state[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\builder_sdphy_fsm_state[2:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0]
- attribute \src "ls180.v:4322.1-4398.4"
+ attribute \src "ls180.v:4357.1-4433.4"
wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0]
- attribute \src "ls180.v:4559.1-4586.4"
+ attribute \src "ls180.v:4594.1-4621.4"
wire $0\builder_sdphy_sdphycrcr_next_state[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_sdphy_sdphycrcr_state[0:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\builder_sdphy_sdphydatar_state[2:0]
- attribute \src "ls180.v:4288.1-4321.4"
+ attribute \src "ls180.v:4323.1-4356.4"
wire $0\builder_sdphy_sdphyinit_next_state[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\builder_sdphy_sdphyinit_state[0:0]
- attribute \src "ls180.v:5705.1-5716.4"
+ attribute \src "ls180.v:5740.1-5751.4"
wire $0\builder_shared_ack[0:0]
- attribute \src "ls180.v:5705.1-5716.4"
+ attribute \src "ls180.v:5740.1-5751.4"
wire width 32 $0\builder_shared_dat_r[31:0]
- attribute \src "ls180.v:5655.1-5662.4"
+ attribute \src "ls180.v:5690.1-5697.4"
wire width 5 $0\builder_slave_sel[4:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 5 $0\builder_slave_sel_r[4:0]
- attribute \src "ls180.v:4182.1-4230.4"
+ attribute \src "ls180.v:4213.1-4261.4"
wire width 2 $0\builder_spimaster0_next_state[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\builder_spimaster0_state[1:0]
- attribute \src "ls180.v:5545.1-5593.4"
+ attribute \src "ls180.v:5580.1-5628.4"
wire width 2 $0\builder_spimaster1_next_state[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\builder_spimaster1_state[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\builder_state[1:0]
- attribute \src "ls180.v:7129.1-7157.4"
+ attribute \src "ls180.v:7181.1-7209.4"
wire $0\builder_sync_f_array_muxed0[0:0]
- attribute \src "ls180.v:7158.1-7186.4"
+ attribute \src "ls180.v:7210.1-7238.4"
wire $0\builder_sync_f_array_muxed1[0:0]
- attribute \src "ls180.v:7010.1-7026.4"
+ attribute \src "ls180.v:7062.1-7078.4"
wire width 2 $0\builder_sync_rhs_array_muxed0[1:0]
- attribute \src "ls180.v:7027.1-7043.4"
+ attribute \src "ls180.v:7079.1-7095.4"
wire width 13 $0\builder_sync_rhs_array_muxed1[12:0]
- attribute \src "ls180.v:7044.1-7060.4"
+ attribute \src "ls180.v:7096.1-7112.4"
wire $0\builder_sync_rhs_array_muxed2[0:0]
- attribute \src "ls180.v:7061.1-7077.4"
+ attribute \src "ls180.v:7113.1-7129.4"
wire $0\builder_sync_rhs_array_muxed3[0:0]
- attribute \src "ls180.v:7078.1-7094.4"
+ attribute \src "ls180.v:7130.1-7146.4"
wire $0\builder_sync_rhs_array_muxed4[0:0]
- attribute \src "ls180.v:7095.1-7111.4"
+ attribute \src "ls180.v:7147.1-7163.4"
wire $0\builder_sync_rhs_array_muxed5[0:0]
- attribute \src "ls180.v:7112.1-7128.4"
+ attribute \src "ls180.v:7164.1-7180.4"
wire $0\builder_sync_rhs_array_muxed6[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\libresocsim_clk_divider1[15:0]
- attribute \src "ls180.v:5545.1-5593.4"
+ attribute \src "ls180.v:5580.1-5628.4"
wire $0\libresocsim_clk_enable[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\libresocsim_control_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\libresocsim_control_storage[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\libresocsim_count[2:0]
- attribute \src "ls180.v:5545.1-5593.4"
+ attribute \src "ls180.v:5580.1-5628.4"
wire width 3 $0\libresocsim_count_spimaster1_next_value[2:0]
- attribute \src "ls180.v:5545.1-5593.4"
+ attribute \src "ls180.v:5580.1-5628.4"
wire $0\libresocsim_count_spimaster1_next_value_ce[0:0]
- attribute \src "ls180.v:5545.1-5593.4"
+ attribute \src "ls180.v:5580.1-5628.4"
wire $0\libresocsim_cs_enable[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\libresocsim_cs_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\libresocsim_cs_storage[0:0]
- attribute \src "ls180.v:5545.1-5593.4"
+ attribute \src "ls180.v:5580.1-5628.4"
wire $0\libresocsim_done0[0:0]
- attribute \src "ls180.v:5545.1-5593.4"
+ attribute \src "ls180.v:5580.1-5628.4"
wire $0\libresocsim_irq[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\libresocsim_loopback_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\libresocsim_loopback_storage[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\libresocsim_miso[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\libresocsim_miso_data[7:0]
- attribute \src "ls180.v:5545.1-5593.4"
+ attribute \src "ls180.v:5580.1-5628.4"
wire $0\libresocsim_miso_latch[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\libresocsim_mosi_data[7:0]
- attribute \src "ls180.v:5545.1-5593.4"
+ attribute \src "ls180.v:5580.1-5628.4"
wire $0\libresocsim_mosi_latch[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\libresocsim_mosi_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\libresocsim_mosi_sel[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\libresocsim_mosi_storage[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\libresocsim_re[0:0]
- attribute \src "ls180.v:6262.1-6267.4"
+ attribute \src "ls180.v:6311.1-6316.4"
wire $0\libresocsim_start1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\libresocsim_storage[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_cmd_consumed[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_converter_counter[0:0]
- attribute \src "ls180.v:3992.1-4038.4"
+ attribute \src "ls180.v:4023.1-4069.4"
wire $0\main_converter_counter_converter_next_value[0:0]
- attribute \src "ls180.v:3992.1-4038.4"
+ attribute \src "ls180.v:4023.1-4069.4"
wire $0\main_converter_counter_converter_next_value_ce[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_converter_dat_r[31:0]
- attribute \src "ls180.v:3992.1-4038.4"
+ attribute \src "ls180.v:4023.1-4069.4"
wire $0\main_converter_skip[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire width 16 $0\main_dfi_p0_rddata[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_dfi_p0_rddata_valid[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire width 42 $0\main_dummy[41:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire width 36 $0\main_dummy[35:0]
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_gpio_oe_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_gpio_oe_storage[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_gpio_out_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_gpio_out_storage[15:0]
- attribute \src "ls180.v:7244.1-7262.4"
+ attribute \src "ls180.v:7296.1-7314.4"
wire width 16 $0\main_gpio_status[15:0]
- attribute \src "ls180.v:7283.1-7285.4"
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire $0\main_i2c_re[0:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire width 3 $0\main_i2c_storage[2:0]
+ attribute \src "ls180.v:7335.1-7337.4"
wire $0\main_int_rst[0:0]
- attribute \src "ls180.v:1480.11-1480.41"
+ attribute \src "ls180.v:1496.11-1496.41"
wire width 2 $0\main_interface0_bus_bte[1:0]
- attribute \src "ls180.v:1479.11-1479.41"
+ attribute \src "ls180.v:1495.11-1495.41"
wire width 3 $0\main_interface0_bus_cti[2:0]
- attribute \src "ls180.v:5404.1-5441.4"
+ attribute \src "ls180.v:5439.1-5476.4"
wire width 32 $0\main_interface1_bus_adr[31:0]
- attribute \src "ls180.v:1571.11-1571.41"
+ attribute \src "ls180.v:1587.11-1587.41"
wire width 2 $0\main_interface1_bus_bte[1:0]
- attribute \src "ls180.v:1570.11-1570.41"
+ attribute \src "ls180.v:1586.11-1586.41"
wire width 3 $0\main_interface1_bus_cti[2:0]
- attribute \src "ls180.v:5404.1-5441.4"
+ attribute \src "ls180.v:5439.1-5476.4"
wire $0\main_interface1_bus_cyc[0:0]
- attribute \src "ls180.v:1563.12-1563.45"
+ attribute \src "ls180.v:1579.12-1579.45"
wire width 32 $0\main_interface1_bus_dat_w[31:0]
- attribute \src "ls180.v:5404.1-5441.4"
+ attribute \src "ls180.v:5439.1-5476.4"
wire width 4 $0\main_interface1_bus_sel[3:0]
- attribute \src "ls180.v:5404.1-5441.4"
+ attribute \src "ls180.v:5439.1-5476.4"
wire $0\main_interface1_bus_stb[0:0]
- attribute \src "ls180.v:5404.1-5441.4"
+ attribute \src "ls180.v:5439.1-5476.4"
wire $0\main_interface1_bus_we[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_libresocsim_bus_errors[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_converter0_counter[0:0]
- attribute \src "ls180.v:2739.1-2785.4"
+ attribute \src "ls180.v:2770.1-2816.4"
wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0]
- attribute \src "ls180.v:2739.1-2785.4"
+ attribute \src "ls180.v:2770.1-2816.4"
wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 64 $0\main_libresocsim_converter0_dat_r[63:0]
- attribute \src "ls180.v:2739.1-2785.4"
+ attribute \src "ls180.v:2770.1-2816.4"
wire $0\main_libresocsim_converter0_skip[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_converter1_counter[0:0]
- attribute \src "ls180.v:2799.1-2845.4"
+ attribute \src "ls180.v:2830.1-2876.4"
wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0]
- attribute \src "ls180.v:2799.1-2845.4"
+ attribute \src "ls180.v:2830.1-2876.4"
wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 64 $0\main_libresocsim_converter1_dat_r[63:0]
- attribute \src "ls180.v:2799.1-2845.4"
+ attribute \src "ls180.v:2830.1-2876.4"
wire $0\main_libresocsim_converter1_skip[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_converter2_counter[0:0]
- attribute \src "ls180.v:2859.1-2905.4"
+ attribute \src "ls180.v:2890.1-2936.4"
wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0]
- attribute \src "ls180.v:2859.1-2905.4"
+ attribute \src "ls180.v:2890.1-2936.4"
wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 64 $0\main_libresocsim_converter2_dat_r[63:0]
- attribute \src "ls180.v:2859.1-2905.4"
+ attribute \src "ls180.v:2890.1-2936.4"
wire $0\main_libresocsim_converter2_skip[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_en_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_en_storage[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_eventmanager_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_eventmanager_storage[0:0]
- attribute \src "ls180.v:2739.1-2785.4"
+ attribute \src "ls180.v:2770.1-2816.4"
wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0]
- attribute \src "ls180.v:139.11-139.69"
+ attribute \src "ls180.v:147.11-147.69"
wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0]
- attribute \src "ls180.v:138.11-138.69"
+ attribute \src "ls180.v:146.11-146.69"
wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0]
- attribute \src "ls180.v:2739.1-2785.4"
+ attribute \src "ls180.v:2770.1-2816.4"
wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0]
- attribute \src "ls180.v:2727.1-2737.4"
+ attribute \src "ls180.v:2758.1-2768.4"
wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0]
- attribute \src "ls180.v:2739.1-2785.4"
+ attribute \src "ls180.v:2770.1-2816.4"
wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0]
- attribute \src "ls180.v:2739.1-2785.4"
+ attribute \src "ls180.v:2770.1-2816.4"
wire $0\main_libresocsim_interface0_converted_interface_stb[0:0]
- attribute \src "ls180.v:2739.1-2785.4"
+ attribute \src "ls180.v:2770.1-2816.4"
wire $0\main_libresocsim_interface0_converted_interface_we[0:0]
- attribute \src "ls180.v:2799.1-2845.4"
+ attribute \src "ls180.v:2830.1-2876.4"
wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0]
- attribute \src "ls180.v:154.11-154.69"
+ attribute \src "ls180.v:162.11-162.69"
wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0]
- attribute \src "ls180.v:153.11-153.69"
+ attribute \src "ls180.v:161.11-161.69"
wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0]
- attribute \src "ls180.v:2799.1-2845.4"
+ attribute \src "ls180.v:2830.1-2876.4"
wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0]
- attribute \src "ls180.v:2787.1-2797.4"
+ attribute \src "ls180.v:2818.1-2828.4"
wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0]
- attribute \src "ls180.v:2799.1-2845.4"
+ attribute \src "ls180.v:2830.1-2876.4"
wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0]
- attribute \src "ls180.v:2799.1-2845.4"
+ attribute \src "ls180.v:2830.1-2876.4"
wire $0\main_libresocsim_interface1_converted_interface_stb[0:0]
- attribute \src "ls180.v:2799.1-2845.4"
+ attribute \src "ls180.v:2830.1-2876.4"
wire $0\main_libresocsim_interface1_converted_interface_we[0:0]
- attribute \src "ls180.v:2859.1-2905.4"
+ attribute \src "ls180.v:2890.1-2936.4"
wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0]
- attribute \src "ls180.v:169.11-169.69"
+ attribute \src "ls180.v:177.11-177.69"
wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0]
- attribute \src "ls180.v:168.11-168.69"
+ attribute \src "ls180.v:176.11-176.69"
wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0]
- attribute \src "ls180.v:2859.1-2905.4"
+ attribute \src "ls180.v:2890.1-2936.4"
wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0]
- attribute \src "ls180.v:2847.1-2857.4"
+ attribute \src "ls180.v:2878.1-2888.4"
wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0]
- attribute \src "ls180.v:2859.1-2905.4"
+ attribute \src "ls180.v:2890.1-2936.4"
wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0]
- attribute \src "ls180.v:2859.1-2905.4"
+ attribute \src "ls180.v:2890.1-2936.4"
wire $0\main_libresocsim_interface2_converted_interface_stb[0:0]
- attribute \src "ls180.v:2859.1-2905.4"
+ attribute \src "ls180.v:2890.1-2936.4"
wire $0\main_libresocsim_interface2_converted_interface_we[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0]
- attribute \src "ls180.v:2799.1-2845.4"
+ attribute \src "ls180.v:2830.1-2876.4"
wire $0\main_libresocsim_libresoc_dbus_ack[0:0]
- attribute \src "ls180.v:70.5-70.46"
+ attribute \src "ls180.v:76.5-76.46"
wire $0\main_libresocsim_libresoc_dbus_err[0:0]
- attribute \src "ls180.v:2739.1-2785.4"
+ attribute \src "ls180.v:2770.1-2816.4"
wire $0\main_libresocsim_libresoc_ibus_ack[0:0]
- attribute \src "ls180.v:81.5-81.46"
+ attribute \src "ls180.v:87.5-87.46"
wire $0\main_libresocsim_libresoc_ibus_err[0:0]
- attribute \src "ls180.v:2720.1-2725.4"
+ attribute \src "ls180.v:2751.1-2756.4"
wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0]
- attribute \src "ls180.v:2859.1-2905.4"
+ attribute \src "ls180.v:2890.1-2936.4"
wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0]
- attribute \src "ls180.v:112.5-112.49"
+ attribute \src "ls180.v:118.5-118.49"
wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_load_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_libresocsim_load_storage[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_ram_bus_ack[0:0]
- attribute \src "ls180.v:185.5-185.40"
+ attribute \src "ls180.v:193.5-193.40"
wire $0\main_libresocsim_ram_bus_err[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_reload_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_libresocsim_reload_storage[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_reset_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_reset_storage[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_scratch_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_libresocsim_scratch_storage[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_update_value_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_update_value_storage[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_libresocsim_value[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_libresocsim_value_status[31:0]
- attribute \src "ls180.v:2908.1-2914.4"
+ attribute \src "ls180.v:2939.1-2945.4"
wire width 4 $0\main_libresocsim_we[3:0]
- attribute \src "ls180.v:2920.1-2925.4"
+ attribute \src "ls180.v:2951.1-2956.4"
wire $0\main_libresocsim_zero_clear[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_zero_old_trigger[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_libresocsim_zero_pending[0:0]
- attribute \src "ls180.v:3992.1-4038.4"
+ attribute \src "ls180.v:4023.1-4069.4"
wire width 30 $0\main_litedram_wb_adr[29:0]
- attribute \src "ls180.v:3992.1-4038.4"
+ attribute \src "ls180.v:4023.1-4069.4"
wire $0\main_litedram_wb_cyc[0:0]
- attribute \src "ls180.v:3980.1-3990.4"
+ attribute \src "ls180.v:4011.1-4021.4"
wire width 16 $0\main_litedram_wb_dat_w[15:0]
- attribute \src "ls180.v:3992.1-4038.4"
+ attribute \src "ls180.v:4023.1-4069.4"
wire width 2 $0\main_litedram_wb_sel[1:0]
- attribute \src "ls180.v:3992.1-4038.4"
+ attribute \src "ls180.v:4023.1-4069.4"
wire $0\main_litedram_wb_stb[0:0]
- attribute \src "ls180.v:3992.1-4038.4"
+ attribute \src "ls180.v:4023.1-4069.4"
wire $0\main_litedram_wb_we[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire width 32 $0\main_phase_accumulator_rx[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire width 32 $0\main_phase_accumulator_tx[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_pwm0_counter[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_pwm0_enable_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_pwm0_enable_storage[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_pwm0_period_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_pwm0_period_storage[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_pwm0_width_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_pwm0_width_storage[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_pwm1_counter[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_pwm1_enable_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_pwm1_enable_storage[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_pwm1_period_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_pwm1_period_storage[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_pwm1_width_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_pwm1_width_storage[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_rddata_en[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire $0\main_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire width 4 $0\main_rx_bitcount[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire $0\main_rx_busy[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire $0\main_rx_r[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire width 8 $0\main_rx_reg[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\main_sdblock2mem_converter_demux[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdblock2mem_converter_source_first[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdblock2mem_converter_source_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdblock2mem_converter_strobe_all[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 5 $0\main_sdblock2mem_fifo_consume[4:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 6 $0\main_sdblock2mem_fifo_level[5:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 5 $0\main_sdblock2mem_fifo_produce[4:0]
- attribute \src "ls180.v:1504.5-1504.41"
+ attribute \src "ls180.v:1520.5-1520.41"
wire $0\main_sdblock2mem_fifo_replace[0:0]
- attribute \src "ls180.v:5312.1-5319.4"
+ attribute \src "ls180.v:5347.1-5354.4"
wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0]
- attribute \src "ls180.v:5345.1-5384.4"
+ attribute \src "ls180.v:5380.1-5419.4"
wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0]
- attribute \src "ls180.v:5345.1-5384.4"
+ attribute \src "ls180.v:5380.1-5419.4"
wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0]
- attribute \src "ls180.v:5345.1-5384.4"
+ attribute \src "ls180.v:5380.1-5419.4"
wire $0\main_sdblock2mem_sink_sink_valid1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0]
- attribute \src "ls180.v:5345.1-5384.4"
+ attribute \src "ls180.v:5380.1-5419.4"
wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
- attribute \src "ls180.v:5345.1-5384.4"
+ attribute \src "ls180.v:5380.1-5419.4"
wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
- attribute \src "ls180.v:5345.1-5384.4"
+ attribute \src "ls180.v:5380.1-5419.4"
wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
- attribute \src "ls180.v:5345.1-5384.4"
+ attribute \src "ls180.v:5380.1-5419.4"
wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdcore_block_count_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_sdcore_block_count_storage[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdcore_block_length_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 10 $0\main_sdcore_block_length_storage[9:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdcore_cmd_argument_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_sdcore_cmd_argument_storage[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdcore_cmd_command_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_sdcore_cmd_command_storage[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdcore_cmd_count[2:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdcore_cmd_done[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdcore_cmd_error[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 128 $0\main_sdcore_cmd_response_status[127:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
- attribute \src "ls180.v:1313.5-1313.34"
+ attribute \src "ls180.v:1329.5-1329.34"
wire $0\main_sdcore_cmd_send_w[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdcore_cmd_timeout[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0]
- attribute \src "ls180.v:5000.1-5007.4"
+ attribute \src "ls180.v:5035.1-5042.4"
wire $0\main_sdcore_crc16_checker_crc0_clr[0:0]
- attribute \src "ls180.v:5056.1-5063.4"
+ attribute \src "ls180.v:5091.1-5098.4"
wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
- attribute \src "ls180.v:5010.1-5017.4"
+ attribute \src "ls180.v:5045.1-5052.4"
wire $0\main_sdcore_crc16_checker_crc1_clr[0:0]
- attribute \src "ls180.v:5066.1-5073.4"
+ attribute \src "ls180.v:5101.1-5108.4"
wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
- attribute \src "ls180.v:5020.1-5027.4"
+ attribute \src "ls180.v:5055.1-5062.4"
wire $0\main_sdcore_crc16_checker_crc2_clr[0:0]
- attribute \src "ls180.v:5076.1-5083.4"
+ attribute \src "ls180.v:5111.1-5118.4"
wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
- attribute \src "ls180.v:5030.1-5037.4"
+ attribute \src "ls180.v:5065.1-5072.4"
wire $0\main_sdcore_crc16_checker_crc3_clr[0:0]
- attribute \src "ls180.v:5086.1-5093.4"
+ attribute \src "ls180.v:5121.1-5128.4"
wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_crc16_checker_sink_first[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_crc16_checker_sink_last[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0]
- attribute \src "ls180.v:5045.1-5052.4"
+ attribute \src "ls180.v:5080.1-5087.4"
wire $0\main_sdcore_crc16_checker_sink_ready[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_crc16_checker_sink_valid[0:0]
- attribute \src "ls180.v:1419.5-1419.50"
+ attribute \src "ls180.v:1435.5-1435.50"
wire $0\main_sdcore_crc16_checker_source_first[0:0]
- attribute \src "ls180.v:5039.1-5044.4"
+ attribute \src "ls180.v:5074.1-5079.4"
wire $0\main_sdcore_crc16_checker_source_valid[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_sdcore_crc16_checker_val[7:0]
- attribute \src "ls180.v:4992.1-4997.4"
+ attribute \src "ls180.v:5027.1-5032.4"
wire $0\main_sdcore_crc16_checker_valid[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
- attribute \src "ls180.v:4874.1-4881.4"
+ attribute \src "ls180.v:4909.1-4916.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
- attribute \src "ls180.v:4884.1-4891.4"
+ attribute \src "ls180.v:4919.1-4926.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
- attribute \src "ls180.v:4894.1-4901.4"
+ attribute \src "ls180.v:4929.1-4936.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
- attribute \src "ls180.v:4904.1-4911.4"
+ attribute \src "ls180.v:4939.1-4946.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire $0\main_sdcore_crc16_inserter_sink_ready[0:0]
- attribute \src "ls180.v:1376.5-1376.51"
+ attribute \src "ls180.v:1392.5-1392.51"
wire $0\main_sdcore_crc16_inserter_source_first[0:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire $0\main_sdcore_crc16_inserter_source_last[0:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_crc16_inserter_source_ready[0:0]
- attribute \src "ls180.v:4912.1-4991.4"
+ attribute \src "ls180.v:4947.1-5026.4"
wire $0\main_sdcore_crc16_inserter_source_valid[0:0]
- attribute \src "ls180.v:4852.1-4859.4"
+ attribute \src "ls180.v:4887.1-4894.4"
wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_sdcore_data_count[31:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdcore_data_done[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdcore_data_error[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdcore_data_timeout[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\main_sdmem2block_converter_mux[1:0]
- attribute \src "ls180.v:5490.1-5506.4"
+ attribute \src "ls180.v:5525.1-5541.4"
wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdmem2block_dma_base_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 64 $0\main_sdmem2block_dma_base_storage[63:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_sdmem2block_dma_data[31:0]
- attribute \src "ls180.v:5404.1-5441.4"
+ attribute \src "ls180.v:5439.1-5476.4"
wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
- attribute \src "ls180.v:5404.1-5441.4"
+ attribute \src "ls180.v:5439.1-5476.4"
wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
- attribute \src "ls180.v:5442.1-5478.4"
+ attribute \src "ls180.v:5477.1-5513.4"
wire $0\main_sdmem2block_dma_done_status[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdmem2block_dma_enable_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdmem2block_dma_enable_storage[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdmem2block_dma_length_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_sdmem2block_dma_length_storage[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdmem2block_dma_loop_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdmem2block_dma_loop_storage[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_sdmem2block_dma_offset[31:0]
- attribute \src "ls180.v:5442.1-5478.4"
+ attribute \src "ls180.v:5477.1-5513.4"
wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
- attribute \src "ls180.v:5442.1-5478.4"
+ attribute \src "ls180.v:5477.1-5513.4"
wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
- attribute \src "ls180.v:5442.1-5478.4"
+ attribute \src "ls180.v:5477.1-5513.4"
wire $0\main_sdmem2block_dma_sink_last[0:0]
- attribute \src "ls180.v:5442.1-5478.4"
+ attribute \src "ls180.v:5477.1-5513.4"
wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0]
- attribute \src "ls180.v:5404.1-5441.4"
+ attribute \src "ls180.v:5439.1-5476.4"
wire $0\main_sdmem2block_dma_sink_ready[0:0]
- attribute \src "ls180.v:5442.1-5478.4"
+ attribute \src "ls180.v:5477.1-5513.4"
wire $0\main_sdmem2block_dma_sink_valid[0:0]
- attribute \src "ls180.v:1584.5-1584.45"
+ attribute \src "ls180.v:1600.5-1600.45"
wire $0\main_sdmem2block_dma_source_first[0:0]
- attribute \src "ls180.v:5404.1-5441.4"
+ attribute \src "ls180.v:5439.1-5476.4"
wire $0\main_sdmem2block_dma_source_last[0:0]
- attribute \src "ls180.v:5404.1-5441.4"
+ attribute \src "ls180.v:5439.1-5476.4"
wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0]
- attribute \src "ls180.v:5404.1-5441.4"
+ attribute \src "ls180.v:5439.1-5476.4"
wire $0\main_sdmem2block_dma_source_valid[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 5 $0\main_sdmem2block_fifo_consume[4:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 6 $0\main_sdmem2block_fifo_level[5:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 5 $0\main_sdmem2block_fifo_produce[4:0]
- attribute \src "ls180.v:1640.5-1640.41"
+ attribute \src "ls180.v:1656.5-1656.41"
wire $0\main_sdmem2block_fifo_replace[0:0]
- attribute \src "ls180.v:5520.1-5527.4"
+ attribute \src "ls180.v:5555.1-5562.4"
wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_clocker_clk0[0:0]
- attribute \src "ls180.v:4258.1-4286.4"
+ attribute \src "ls180.v:4293.1-4321.4"
wire $0\main_sdphy_clocker_clk1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_clocker_clk_d[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 9 $0\main_sdphy_clocker_clks[8:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_clocker_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 9 $0\main_sdphy_clocker_storage[8:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0]
- attribute \src "ls180.v:1105.5-1105.53"
+ attribute \src "ls180.v:1121.5-1121.53"
wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0]
- attribute \src "ls180.v:1106.5-1106.52"
+ attribute \src "ls180.v:1122.5-1122.52"
wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
- attribute \src "ls180.v:1086.5-1086.46"
+ attribute \src "ls180.v:1102.5-1102.46"
wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_cmdr_cmdr_reset[0:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_cmdr_cmdr_run[0:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_sdphy_cmdr_count[7:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
- attribute \src "ls180.v:1059.5-1059.49"
+ attribute \src "ls180.v:1075.5-1075.49"
wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0]
- attribute \src "ls180.v:1060.5-1060.48"
+ attribute \src "ls180.v:1076.5-1076.48"
wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0]
- attribute \src "ls180.v:1061.5-1061.55"
+ attribute \src "ls180.v:1077.5-1077.55"
wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0]
- attribute \src "ls180.v:1063.5-1063.57"
+ attribute \src "ls180.v:1079.5-1079.57"
wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0]
- attribute \src "ls180.v:1064.5-1064.58"
+ attribute \src "ls180.v:1080.5-1080.58"
wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1066.11-1066.64"
+ attribute \src "ls180.v:1082.11-1082.64"
wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0]
- attribute \src "ls180.v:1067.5-1067.59"
+ attribute \src "ls180.v:1083.5-1083.59"
wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1072.11-1072.57"
+ attribute \src "ls180.v:1088.11-1088.57"
wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:1073.5-1073.52"
+ attribute \src "ls180.v:1089.5-1089.52"
wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdphy_cmdr_sink_last[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire $0\main_sdphy_cmdr_sink_ready[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdphy_cmdr_sink_valid[0:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire $0\main_sdphy_cmdr_source_last[0:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdphy_cmdr_source_ready[0:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire $0\main_sdphy_cmdr_source_valid[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_sdphy_cmdr_timeout[31:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
- attribute \src "ls180.v:4432.1-4525.4"
+ attribute \src "ls180.v:4467.1-4560.4"
wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_sdphy_cmdw_count[7:0]
- attribute \src "ls180.v:4322.1-4398.4"
+ attribute \src "ls180.v:4357.1-4433.4"
wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
- attribute \src "ls180.v:4322.1-4398.4"
+ attribute \src "ls180.v:4357.1-4433.4"
wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
- attribute \src "ls180.v:4322.1-4398.4"
+ attribute \src "ls180.v:4357.1-4433.4"
wire $0\main_sdphy_cmdw_done[0:0]
- attribute \src "ls180.v:4322.1-4398.4"
+ attribute \src "ls180.v:4357.1-4433.4"
wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:4322.1-4398.4"
+ attribute \src "ls180.v:4357.1-4433.4"
wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:4322.1-4398.4"
+ attribute \src "ls180.v:4357.1-4433.4"
wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1049.11-1049.57"
+ attribute \src "ls180.v:1065.11-1065.57"
wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:1050.5-1050.52"
+ attribute \src "ls180.v:1066.5-1066.52"
wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdphy_cmdw_sink_last[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0]
- attribute \src "ls180.v:4322.1-4398.4"
+ attribute \src "ls180.v:4357.1-4433.4"
wire $0\main_sdphy_cmdw_sink_ready[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdphy_cmdw_sink_valid[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 10 $0\main_sdphy_datar_count[9:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_datar_datar_buf_source_first[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_datar_datar_buf_source_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_datar_datar_buf_source_valid[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_datar_datar_converter_demux[0:0]
- attribute \src "ls180.v:1261.5-1261.55"
+ attribute \src "ls180.v:1277.5-1277.55"
wire $0\main_sdphy_datar_datar_converter_sink_first[0:0]
- attribute \src "ls180.v:1262.5-1262.54"
+ attribute \src "ls180.v:1278.5-1278.54"
wire $0\main_sdphy_datar_datar_converter_sink_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_datar_datar_converter_source_first[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_datar_datar_converter_source_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0]
- attribute \src "ls180.v:1242.5-1242.48"
+ attribute \src "ls180.v:1258.5-1258.48"
wire $0\main_sdphy_datar_datar_pads_in_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_datar_datar_reset[0:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_datar_datar_run[0:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire $0\main_sdphy_datar_datar_source_source_ready0[0:0]
- attribute \src "ls180.v:1213.5-1213.50"
+ attribute \src "ls180.v:1229.5-1229.50"
wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0]
- attribute \src "ls180.v:1214.5-1214.49"
+ attribute \src "ls180.v:1230.5-1230.49"
wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0]
- attribute \src "ls180.v:1215.5-1215.56"
+ attribute \src "ls180.v:1231.5-1231.56"
wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0]
- attribute \src "ls180.v:1217.5-1217.58"
+ attribute \src "ls180.v:1233.5-1233.58"
wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0]
- attribute \src "ls180.v:1218.5-1218.59"
+ attribute \src "ls180.v:1234.5-1234.59"
wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1220.11-1220.65"
+ attribute \src "ls180.v:1236.11-1236.65"
wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0]
- attribute \src "ls180.v:1221.5-1221.60"
+ attribute \src "ls180.v:1237.5-1237.60"
wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire $0\main_sdphy_datar_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1224.5-1224.51"
+ attribute \src "ls180.v:1240.5-1240.51"
wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:1225.5-1225.52"
+ attribute \src "ls180.v:1241.5-1241.52"
wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1226.11-1226.58"
+ attribute \src "ls180.v:1242.11-1242.58"
wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:1227.5-1227.53"
+ attribute \src "ls180.v:1243.5-1243.53"
wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdphy_datar_sink_last[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire $0\main_sdphy_datar_sink_ready[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdphy_datar_sink_valid[0:0]
- attribute \src "ls180.v:1234.5-1234.41"
+ attribute \src "ls180.v:1250.5-1250.41"
wire $0\main_sdphy_datar_source_first[0:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire $0\main_sdphy_datar_source_last[0:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire width 8 $0\main_sdphy_datar_source_payload_data[7:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire width 3 $0\main_sdphy_datar_source_payload_status[2:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdphy_datar_source_ready[0:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire $0\main_sdphy_datar_source_valid[0:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire $0\main_sdphy_datar_stop[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 32 $0\main_sdphy_datar_timeout[31:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
- attribute \src "ls180.v:4693.1-4794.4"
+ attribute \src "ls180.v:4728.1-4829.4"
wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_sdphy_dataw_count[7:0]
- attribute \src "ls180.v:4587.1-4659.4"
+ attribute \src "ls180.v:4622.1-4694.4"
wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
- attribute \src "ls180.v:4587.1-4659.4"
+ attribute \src "ls180.v:4622.1-4694.4"
wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0]
- attribute \src "ls180.v:1183.5-1183.54"
+ attribute \src "ls180.v:1199.5-1199.54"
wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0]
- attribute \src "ls180.v:1184.5-1184.53"
+ attribute \src "ls180.v:1200.5-1200.53"
wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
- attribute \src "ls180.v:1164.5-1164.47"
+ attribute \src "ls180.v:1180.5-1180.47"
wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_dataw_crcr_reset[0:0]
- attribute \src "ls180.v:4559.1-4586.4"
+ attribute \src "ls180.v:4594.1-4621.4"
wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
- attribute \src "ls180.v:4559.1-4586.4"
+ attribute \src "ls180.v:4594.1-4621.4"
wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdphy_dataw_crcr_run[0:0]
- attribute \src "ls180.v:4559.1-4586.4"
+ attribute \src "ls180.v:4594.1-4621.4"
wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0]
- attribute \src "ls180.v:4559.1-4586.4"
+ attribute \src "ls180.v:4594.1-4621.4"
wire $0\main_sdphy_dataw_error[0:0]
- attribute \src "ls180.v:1151.5-1151.50"
+ attribute \src "ls180.v:1167.5-1167.50"
wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0]
- attribute \src "ls180.v:1152.5-1152.49"
+ attribute \src "ls180.v:1168.5-1168.49"
wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0]
- attribute \src "ls180.v:1153.5-1153.56"
+ attribute \src "ls180.v:1169.5-1169.56"
wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0]
- attribute \src "ls180.v:1154.5-1154.58"
+ attribute \src "ls180.v:1170.5-1170.58"
wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0]
- attribute \src "ls180.v:1155.5-1155.58"
+ attribute \src "ls180.v:1171.5-1171.58"
wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0]
- attribute \src "ls180.v:1156.5-1156.59"
+ attribute \src "ls180.v:1172.5-1172.59"
wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1157.11-1157.65"
+ attribute \src "ls180.v:1173.11-1173.65"
wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0]
- attribute \src "ls180.v:1158.11-1158.65"
+ attribute \src "ls180.v:1174.11-1174.65"
wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0]
- attribute \src "ls180.v:1159.5-1159.60"
+ attribute \src "ls180.v:1175.5-1175.60"
wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0]
- attribute \src "ls180.v:1149.5-1149.50"
+ attribute \src "ls180.v:1165.5-1165.50"
wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0]
- attribute \src "ls180.v:4587.1-4659.4"
+ attribute \src "ls180.v:4622.1-4694.4"
wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1138.5-1138.51"
+ attribute \src "ls180.v:1154.5-1154.51"
wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:1139.5-1139.52"
+ attribute \src "ls180.v:1155.5-1155.52"
wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:4587.1-4659.4"
+ attribute \src "ls180.v:4622.1-4694.4"
wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:4587.1-4659.4"
+ attribute \src "ls180.v:4622.1-4694.4"
wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdphy_dataw_sink_first[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdphy_dataw_sink_last[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0]
- attribute \src "ls180.v:4587.1-4659.4"
+ attribute \src "ls180.v:4622.1-4694.4"
wire $0\main_sdphy_dataw_sink_ready[0:0]
- attribute \src "ls180.v:5094.1-5284.4"
+ attribute \src "ls180.v:5129.1-5319.4"
wire $0\main_sdphy_dataw_sink_valid[0:0]
- attribute \src "ls180.v:4587.1-4659.4"
+ attribute \src "ls180.v:4622.1-4694.4"
wire $0\main_sdphy_dataw_start[0:0]
- attribute \src "ls180.v:4587.1-4659.4"
+ attribute \src "ls180.v:4622.1-4694.4"
wire $0\main_sdphy_dataw_stop[0:0]
- attribute \src "ls180.v:4559.1-4586.4"
+ attribute \src "ls180.v:4594.1-4621.4"
wire $0\main_sdphy_dataw_valid[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_sdphy_init_count[7:0]
- attribute \src "ls180.v:4288.1-4321.4"
+ attribute \src "ls180.v:4323.1-4356.4"
wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
- attribute \src "ls180.v:4288.1-4321.4"
+ attribute \src "ls180.v:4323.1-4356.4"
wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
- attribute \src "ls180.v:1031.5-1031.40"
+ attribute \src "ls180.v:1047.5-1047.40"
wire $0\main_sdphy_init_initialize_w[0:0]
- attribute \src "ls180.v:4288.1-4321.4"
+ attribute \src "ls180.v:4323.1-4356.4"
wire $0\main_sdphy_init_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:4288.1-4321.4"
+ attribute \src "ls180.v:4323.1-4356.4"
wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:4288.1-4321.4"
+ attribute \src "ls180.v:4323.1-4356.4"
wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:4288.1-4321.4"
+ attribute \src "ls180.v:4323.1-4356.4"
wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:4288.1-4321.4"
+ attribute \src "ls180.v:4323.1-4356.4"
wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire $0\main_sdphy_sdpads_cmd_i[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire width 4 $0\main_sdphy_sdpads_data_i[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_address_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 13 $0\main_sdram_address_storage[12:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_baddress_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\main_sdram_baddress_storage[1:0]
- attribute \src "ls180.v:3137.1-3144.4"
+ attribute \src "ls180.v:3168.1-3175.4"
wire $0\main_sdram_bankmachine0_auto_precharge[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:417.5-417.64"
+ attribute \src "ls180.v:425.5-425.64"
wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
- attribute \src "ls180.v:400.5-400.67"
+ attribute \src "ls180.v:408.5-408.67"
wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
- attribute \src "ls180.v:401.5-401.66"
+ attribute \src "ls180.v:409.5-409.66"
wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
- attribute \src "ls180.v:3159.1-3166.4"
+ attribute \src "ls180.v:3190.1-3197.4"
wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:3126.1-3133.4"
+ attribute \src "ls180.v:3157.1-3164.4"
wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0]
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:3206.1-3299.4"
wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0]
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:3206.1-3299.4"
wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:3206.1-3299.4"
wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:3206.1-3299.4"
wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:3206.1-3299.4"
wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0]
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:3206.1-3299.4"
wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0]
- attribute \src "ls180.v:3824.1-3832.4"
+ attribute \src "ls180.v:3855.1-3863.4"
wire $0\main_sdram_bankmachine0_cmd_ready[0:0]
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:3206.1-3299.4"
wire $0\main_sdram_bankmachine0_cmd_valid[0:0]
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:3206.1-3299.4"
wire $0\main_sdram_bankmachine0_refresh_gnt[0:0]
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:3206.1-3299.4"
wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0]
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:3206.1-3299.4"
wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 13 $0\main_sdram_bankmachine0_row[12:0]
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:3206.1-3299.4"
wire $0\main_sdram_bankmachine0_row_close[0:0]
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:3206.1-3299.4"
wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:3175.1-3268.4"
+ attribute \src "ls180.v:3206.1-3299.4"
wire $0\main_sdram_bankmachine0_row_open[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine0_row_opened[0:0]
- attribute \src "ls180.v:459.32-459.76"
+ attribute \src "ls180.v:467.32-467.76"
wire $0\main_sdram_bankmachine0_trascon_ready[0:0]
- attribute \src "ls180.v:457.32-457.75"
+ attribute \src "ls180.v:465.32-465.75"
wire $0\main_sdram_bankmachine0_trccon_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0]
- attribute \src "ls180.v:3294.1-3301.4"
+ attribute \src "ls180.v:3325.1-3332.4"
wire $0\main_sdram_bankmachine1_auto_precharge[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:499.5-499.64"
+ attribute \src "ls180.v:507.5-507.64"
wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
- attribute \src "ls180.v:482.5-482.67"
+ attribute \src "ls180.v:490.5-490.67"
wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
- attribute \src "ls180.v:483.5-483.66"
+ attribute \src "ls180.v:491.5-491.66"
wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
- attribute \src "ls180.v:3316.1-3323.4"
+ attribute \src "ls180.v:3347.1-3354.4"
wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:3283.1-3290.4"
+ attribute \src "ls180.v:3314.1-3321.4"
wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0]
- attribute \src "ls180.v:3833.1-3841.4"
+ attribute \src "ls180.v:3864.1-3872.4"
wire $0\main_sdram_bankmachine1_cmd_ready[0:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire $0\main_sdram_bankmachine1_cmd_valid[0:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire $0\main_sdram_bankmachine1_refresh_gnt[0:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 13 $0\main_sdram_bankmachine1_row[12:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire $0\main_sdram_bankmachine1_row_close[0:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:3332.1-3425.4"
+ attribute \src "ls180.v:3363.1-3456.4"
wire $0\main_sdram_bankmachine1_row_open[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine1_row_opened[0:0]
- attribute \src "ls180.v:541.32-541.76"
+ attribute \src "ls180.v:549.32-549.76"
wire $0\main_sdram_bankmachine1_trascon_ready[0:0]
- attribute \src "ls180.v:539.32-539.75"
+ attribute \src "ls180.v:547.32-547.75"
wire $0\main_sdram_bankmachine1_trccon_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0]
- attribute \src "ls180.v:3451.1-3458.4"
+ attribute \src "ls180.v:3482.1-3489.4"
wire $0\main_sdram_bankmachine2_auto_precharge[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:581.5-581.64"
+ attribute \src "ls180.v:589.5-589.64"
wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
- attribute \src "ls180.v:564.5-564.67"
+ attribute \src "ls180.v:572.5-572.67"
wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0]
- attribute \src "ls180.v:565.5-565.66"
+ attribute \src "ls180.v:573.5-573.66"
wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
- attribute \src "ls180.v:3473.1-3480.4"
+ attribute \src "ls180.v:3504.1-3511.4"
wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:3440.1-3447.4"
+ attribute \src "ls180.v:3471.1-3478.4"
wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0]
- attribute \src "ls180.v:3842.1-3850.4"
+ attribute \src "ls180.v:3873.1-3881.4"
wire $0\main_sdram_bankmachine2_cmd_ready[0:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire $0\main_sdram_bankmachine2_cmd_valid[0:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire $0\main_sdram_bankmachine2_refresh_gnt[0:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 13 $0\main_sdram_bankmachine2_row[12:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire $0\main_sdram_bankmachine2_row_close[0:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:3489.1-3582.4"
+ attribute \src "ls180.v:3520.1-3613.4"
wire $0\main_sdram_bankmachine2_row_open[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine2_row_opened[0:0]
- attribute \src "ls180.v:623.32-623.76"
+ attribute \src "ls180.v:631.32-631.76"
wire $0\main_sdram_bankmachine2_trascon_ready[0:0]
- attribute \src "ls180.v:621.32-621.75"
+ attribute \src "ls180.v:629.32-629.75"
wire $0\main_sdram_bankmachine2_trccon_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0]
- attribute \src "ls180.v:3608.1-3615.4"
+ attribute \src "ls180.v:3639.1-3646.4"
wire $0\main_sdram_bankmachine3_auto_precharge[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:663.5-663.64"
+ attribute \src "ls180.v:671.5-671.64"
wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
- attribute \src "ls180.v:646.5-646.67"
+ attribute \src "ls180.v:654.5-654.67"
wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
- attribute \src "ls180.v:647.5-647.66"
+ attribute \src "ls180.v:655.5-655.66"
wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
- attribute \src "ls180.v:3630.1-3637.4"
+ attribute \src "ls180.v:3661.1-3668.4"
wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:3597.1-3604.4"
+ attribute \src "ls180.v:3628.1-3635.4"
wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0]
- attribute \src "ls180.v:3851.1-3859.4"
+ attribute \src "ls180.v:3882.1-3890.4"
wire $0\main_sdram_bankmachine3_cmd_ready[0:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire $0\main_sdram_bankmachine3_cmd_valid[0:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire $0\main_sdram_bankmachine3_refresh_gnt[0:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 13 $0\main_sdram_bankmachine3_row[12:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire $0\main_sdram_bankmachine3_row_close[0:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:3646.1-3739.4"
+ attribute \src "ls180.v:3677.1-3770.4"
wire $0\main_sdram_bankmachine3_row_open[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine3_row_opened[0:0]
- attribute \src "ls180.v:705.32-705.76"
+ attribute \src "ls180.v:713.32-713.76"
wire $0\main_sdram_bankmachine3_trascon_ready[0:0]
- attribute \src "ls180.v:703.32-703.75"
+ attribute \src "ls180.v:711.32-711.75"
wire $0\main_sdram_bankmachine3_trccon_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0]
- attribute \src "ls180.v:3773.1-3778.4"
+ attribute \src "ls180.v:3804.1-3809.4"
wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0]
- attribute \src "ls180.v:3779.1-3784.4"
+ attribute \src "ls180.v:3810.1-3815.4"
wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0]
- attribute \src "ls180.v:3785.1-3790.4"
+ attribute \src "ls180.v:3816.1-3821.4"
wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0]
- attribute \src "ls180.v:713.5-713.43"
+ attribute \src "ls180.v:721.5-721.43"
wire $0\main_sdram_choose_cmd_cmd_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\main_sdram_choose_cmd_grant[1:0]
- attribute \src "ls180.v:3759.1-3765.4"
+ attribute \src "ls180.v:3790.1-3796.4"
wire width 4 $0\main_sdram_choose_cmd_valids[3:0]
- attribute \src "ls180.v:711.5-711.48"
+ attribute \src "ls180.v:719.5-719.48"
wire $0\main_sdram_choose_cmd_want_activates[0:0]
- attribute \src "ls180.v:710.5-710.43"
+ attribute \src "ls180.v:718.5-718.43"
wire $0\main_sdram_choose_cmd_want_cmds[0:0]
- attribute \src "ls180.v:708.5-708.44"
+ attribute \src "ls180.v:716.5-716.44"
wire $0\main_sdram_choose_cmd_want_reads[0:0]
- attribute \src "ls180.v:709.5-709.45"
+ attribute \src "ls180.v:717.5-717.45"
wire $0\main_sdram_choose_cmd_want_writes[0:0]
- attribute \src "ls180.v:3806.1-3811.4"
+ attribute \src "ls180.v:3837.1-3842.4"
wire $0\main_sdram_choose_req_cmd_payload_cas[0:0]
- attribute \src "ls180.v:3812.1-3817.4"
+ attribute \src "ls180.v:3843.1-3848.4"
wire $0\main_sdram_choose_req_cmd_payload_ras[0:0]
- attribute \src "ls180.v:3818.1-3823.4"
+ attribute \src "ls180.v:3849.1-3854.4"
wire $0\main_sdram_choose_req_cmd_payload_we[0:0]
- attribute \src "ls180.v:3864.1-3936.4"
+ attribute \src "ls180.v:3895.1-3967.4"
wire $0\main_sdram_choose_req_cmd_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\main_sdram_choose_req_grant[1:0]
- attribute \src "ls180.v:3792.1-3798.4"
+ attribute \src "ls180.v:3823.1-3829.4"
wire width 4 $0\main_sdram_choose_req_valids[3:0]
- attribute \src "ls180.v:3864.1-3936.4"
+ attribute \src "ls180.v:3895.1-3967.4"
wire $0\main_sdram_choose_req_want_activates[0:0]
- attribute \src "ls180.v:3864.1-3936.4"
+ attribute \src "ls180.v:3895.1-3967.4"
wire $0\main_sdram_choose_req_want_reads[0:0]
- attribute \src "ls180.v:3864.1-3936.4"
+ attribute \src "ls180.v:3895.1-3967.4"
wire $0\main_sdram_choose_req_want_writes[0:0]
- attribute \src "ls180.v:3081.1-3111.4"
+ attribute \src "ls180.v:3112.1-3142.4"
wire $0\main_sdram_cmd_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 13 $0\main_sdram_cmd_payload_a[12:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\main_sdram_cmd_payload_ba[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_cmd_payload_cas[0:0]
- attribute \src "ls180.v:361.5-361.42"
+ attribute \src "ls180.v:369.5-369.42"
wire $0\main_sdram_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:362.5-362.43"
+ attribute \src "ls180.v:370.5-370.43"
wire $0\main_sdram_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_cmd_payload_ras[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_cmd_payload_we[0:0]
- attribute \src "ls180.v:3864.1-3936.4"
+ attribute \src "ls180.v:3895.1-3967.4"
wire $0\main_sdram_cmd_ready[0:0]
- attribute \src "ls180.v:3081.1-3111.4"
+ attribute \src "ls180.v:3112.1-3142.4"
wire $0\main_sdram_cmd_valid[0:0]
- attribute \src "ls180.v:297.5-297.38"
+ attribute \src "ls180.v:305.5-305.38"
wire $0\main_sdram_command_issue_w[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_command_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 6 $0\main_sdram_command_storage[5:0]
- attribute \src "ls180.v:346.5-346.35"
+ attribute \src "ls180.v:354.5-354.35"
wire $0\main_sdram_dfi_p0_act_n[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 13 $0\main_sdram_dfi_p0_address[12:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\main_sdram_dfi_p0_bank[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_dfi_p0_cas_n[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_dfi_p0_cs_n[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_dfi_p0_ras_n[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_dfi_p0_rddata_en[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_dfi_p0_we_n[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_dfi_p0_wrdata_en[0:0]
- attribute \src "ls180.v:3864.1-3936.4"
+ attribute \src "ls180.v:3895.1-3967.4"
wire $0\main_sdram_en0[0:0]
- attribute \src "ls180.v:3864.1-3936.4"
+ attribute \src "ls180.v:3895.1-3967.4"
wire $0\main_sdram_en1[0:0]
- attribute \src "ls180.v:3960.1-3973.4"
+ attribute \src "ls180.v:3991.1-4004.4"
wire width 16 $0\main_sdram_interface_wdata[15:0]
- attribute \src "ls180.v:3960.1-3973.4"
+ attribute \src "ls180.v:3991.1-4004.4"
wire width 2 $0\main_sdram_interface_wdata_we[1:0]
- attribute \src "ls180.v:247.5-247.36"
+ attribute \src "ls180.v:255.5-255.36"
wire $0\main_sdram_inti_p0_act_n[0:0]
- attribute \src "ls180.v:3022.1-3038.4"
+ attribute \src "ls180.v:3053.1-3069.4"
wire $0\main_sdram_inti_p0_cas_n[0:0]
- attribute \src "ls180.v:3022.1-3038.4"
+ attribute \src "ls180.v:3053.1-3069.4"
wire $0\main_sdram_inti_p0_cs_n[0:0]
- attribute \src "ls180.v:3022.1-3038.4"
+ attribute \src "ls180.v:3053.1-3069.4"
wire $0\main_sdram_inti_p0_ras_n[0:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire width 16 $0\main_sdram_inti_p0_rddata[15:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire $0\main_sdram_inti_p0_rddata_valid[0:0]
- attribute \src "ls180.v:3022.1-3038.4"
+ attribute \src "ls180.v:3053.1-3069.4"
wire $0\main_sdram_inti_p0_we_n[0:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire $0\main_sdram_master_p0_act_n[0:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire width 13 $0\main_sdram_master_p0_address[12:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire width 2 $0\main_sdram_master_p0_bank[1:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire $0\main_sdram_master_p0_cas_n[0:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire $0\main_sdram_master_p0_cke[0:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire $0\main_sdram_master_p0_cs_n[0:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire $0\main_sdram_master_p0_odt[0:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire $0\main_sdram_master_p0_ras_n[0:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire $0\main_sdram_master_p0_rddata_en[0:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire $0\main_sdram_master_p0_reset_n[0:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire $0\main_sdram_master_p0_we_n[0:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire width 16 $0\main_sdram_master_p0_wrdata[15:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire $0\main_sdram_master_p0_wrdata_en[0:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0]
- attribute \src "ls180.v:744.12-744.36"
+ attribute \src "ls180.v:752.12-752.36"
wire width 13 $0\main_sdram_nop_a[12:0]
- attribute \src "ls180.v:745.11-745.35"
+ attribute \src "ls180.v:753.11-753.35"
wire width 2 $0\main_sdram_nop_ba[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_postponer_count[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_postponer_req_o[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_sequencer_count[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_sdram_sequencer_counter[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_sequencer_done1[0:0]
- attribute \src "ls180.v:3081.1-3111.4"
+ attribute \src "ls180.v:3112.1-3142.4"
wire $0\main_sdram_sequencer_start0[0:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire width 16 $0\main_sdram_slave_p0_rddata[15:0]
- attribute \src "ls180.v:2964.1-3018.4"
+ attribute \src "ls180.v:2995.1-3049.4"
wire $0\main_sdram_slave_p0_rddata_valid[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdram_status[15:0]
- attribute \src "ls180.v:747.5-747.31"
+ attribute \src "ls180.v:755.5-755.31"
wire $0\main_sdram_steerer0[0:0]
- attribute \src "ls180.v:748.5-748.31"
+ attribute \src "ls180.v:756.5-756.31"
wire $0\main_sdram_steerer1[0:0]
- attribute \src "ls180.v:3864.1-3936.4"
+ attribute \src "ls180.v:3895.1-3967.4"
wire width 2 $0\main_sdram_steerer_sel[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_sdram_storage[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_tccdcon_count[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_tccdcon_ready[0:0]
- attribute \src "ls180.v:752.32-752.63"
+ attribute \src "ls180.v:760.32-760.63"
wire $0\main_sdram_tfawcon_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 5 $0\main_sdram_time0[4:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_sdram_time1[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 10 $0\main_sdram_timer_count1[9:0]
- attribute \src "ls180.v:750.32-750.63"
+ attribute \src "ls180.v:758.32-758.63"
wire $0\main_sdram_trrdcon_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_sdram_twtrcon_count[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_twtrcon_ready[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_sdram_wrdata_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_sdram_wrdata_storage[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire $0\main_sink_ready[0:0]
- attribute \src "ls180.v:823.5-823.29"
- wire $0\main_source_first[0:0]
- attribute \src "ls180.v:824.5-824.28"
- wire $0\main_source_last[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire width 8 $0\main_source_payload_data[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire $0\main_source_valid[0:0]
- attribute \src "ls180.v:968.12-968.48"
+ attribute \src "ls180.v:976.12-976.48"
wire width 16 $0\main_spi_master_clk_divider0[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_spi_master_clk_divider1[15:0]
- attribute \src "ls180.v:4182.1-4230.4"
+ attribute \src "ls180.v:4213.1-4261.4"
wire $0\main_spi_master_clk_enable[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_spi_master_control_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 16 $0\main_spi_master_control_storage[15:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_spi_master_count[2:0]
- attribute \src "ls180.v:4182.1-4230.4"
+ attribute \src "ls180.v:4213.1-4261.4"
wire width 3 $0\main_spi_master_count_spimaster0_next_value[2:0]
- attribute \src "ls180.v:4182.1-4230.4"
+ attribute \src "ls180.v:4213.1-4261.4"
wire $0\main_spi_master_count_spimaster0_next_value_ce[0:0]
- attribute \src "ls180.v:4182.1-4230.4"
+ attribute \src "ls180.v:4213.1-4261.4"
wire $0\main_spi_master_cs_enable[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_spi_master_cs_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_spi_master_cs_storage[0:0]
- attribute \src "ls180.v:4182.1-4230.4"
+ attribute \src "ls180.v:4213.1-4261.4"
wire $0\main_spi_master_done0[0:0]
- attribute \src "ls180.v:4182.1-4230.4"
+ attribute \src "ls180.v:4213.1-4261.4"
wire $0\main_spi_master_irq[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_spi_master_loopback_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_spi_master_loopback_storage[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_spi_master_miso[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_spi_master_miso_data[7:0]
- attribute \src "ls180.v:4182.1-4230.4"
+ attribute \src "ls180.v:4213.1-4261.4"
wire $0\main_spi_master_miso_latch[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_spi_master_mosi_data[7:0]
- attribute \src "ls180.v:4182.1-4230.4"
+ attribute \src "ls180.v:4213.1-4261.4"
wire $0\main_spi_master_mosi_latch[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_spi_master_mosi_re[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 3 $0\main_spi_master_mosi_sel[2:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 8 $0\main_spi_master_mosi_storage[7:0]
- attribute \src "ls180.v:6216.1-6221.4"
+ attribute \src "ls180.v:6265.1-6270.4"
wire $0\main_spi_master_start1[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire width 32 $0\main_storage[31:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire width 4 $0\main_tx_bitcount[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire $0\main_tx_busy[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire width 8 $0\main_tx_reg[7:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire $0\main_uart_clk_rxen[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
- wire $0\main_uart_clk_txen[0:0]
- attribute \src "ls180.v:4100.1-4104.4"
+ attribute \src "ls180.v:4131.1-4135.4"
wire width 2 $0\main_uart_eventmanager_pending_w[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_uart_eventmanager_re[0:0]
- attribute \src "ls180.v:4089.1-4093.4"
+ attribute \src "ls180.v:4120.1-4124.4"
wire width 2 $0\main_uart_eventmanager_status_w[1:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 2 $0\main_uart_eventmanager_storage[1:0]
- attribute \src "ls180.v:950.5-950.27"
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire $0\main_uart_phy_re[0:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire width 4 $0\main_uart_phy_rx_bitcount[3:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire $0\main_uart_phy_rx_busy[0:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire $0\main_uart_phy_rx_r[0:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire width 8 $0\main_uart_phy_rx_reg[7:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire $0\main_uart_phy_sink_ready[0:0]
+ attribute \src "ls180.v:831.5-831.38"
+ wire $0\main_uart_phy_source_first[0:0]
+ attribute \src "ls180.v:832.5-832.37"
+ wire $0\main_uart_phy_source_last[0:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire width 8 $0\main_uart_phy_source_payload_data[7:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire $0\main_uart_phy_source_valid[0:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire width 32 $0\main_uart_phy_storage[31:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire width 4 $0\main_uart_phy_tx_bitcount[3:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire $0\main_uart_phy_tx_busy[0:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire width 8 $0\main_uart_phy_tx_reg[7:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire $0\main_uart_phy_uart_clk_rxen[0:0]
+ attribute \src "ls180.v:7411.1-10036.4"
+ wire $0\main_uart_phy_uart_clk_txen[0:0]
+ attribute \src "ls180.v:958.5-958.27"
wire $0\main_uart_reset[0:0]
- attribute \src "ls180.v:4094.1-4099.4"
+ attribute \src "ls180.v:4125.1-4130.4"
wire $0\main_uart_rx_clear[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_uart_rx_fifo_consume[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 5 $0\main_uart_rx_fifo_level0[4:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_uart_rx_fifo_produce[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_uart_rx_fifo_readable[0:0]
- attribute \src "ls180.v:932.5-932.37"
+ attribute \src "ls180.v:940.5-940.37"
wire $0\main_uart_rx_fifo_replace[0:0]
- attribute \src "ls180.v:4152.1-4159.4"
+ attribute \src "ls180.v:4183.1-4190.4"
wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_uart_rx_old_trigger[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_uart_rx_pending[0:0]
- attribute \src "ls180.v:4083.1-4088.4"
+ attribute \src "ls180.v:4114.1-4119.4"
wire $0\main_uart_tx_clear[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_uart_tx_fifo_consume[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 5 $0\main_uart_tx_fifo_level0[4:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire width 4 $0\main_uart_tx_fifo_produce[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_uart_tx_fifo_readable[0:0]
- attribute \src "ls180.v:895.5-895.37"
+ attribute \src "ls180.v:903.5-903.37"
wire $0\main_uart_tx_fifo_replace[0:0]
- attribute \src "ls180.v:878.5-878.40"
+ attribute \src "ls180.v:886.5-886.40"
wire $0\main_uart_tx_fifo_sink_first[0:0]
- attribute \src "ls180.v:879.5-879.39"
+ attribute \src "ls180.v:887.5-887.39"
wire $0\main_uart_tx_fifo_sink_last[0:0]
- attribute \src "ls180.v:4122.1-4129.4"
+ attribute \src "ls180.v:4153.1-4160.4"
wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_uart_tx_old_trigger[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_uart_tx_pending[0:0]
- attribute \src "ls180.v:3992.1-4038.4"
+ attribute \src "ls180.v:4023.1-4069.4"
wire $0\main_wb_sdram_ack[0:0]
- attribute \src "ls180.v:791.5-791.29"
+ attribute \src "ls180.v:799.5-799.29"
wire $0\main_wb_sdram_err[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\main_wdata_consumed[0:0]
- attribute \src "ls180.v:9977.1-9987.4"
+ attribute \src "ls180.v:10040.1-10050.4"
wire width 7 $0\memadr[6:0]
- attribute \src "ls180.v:9997.1-10001.4"
+ attribute \src "ls180.v:10060.1-10064.4"
wire width 25 $0\memdat[24:0]
- attribute \src "ls180.v:10011.1-10015.4"
+ attribute \src "ls180.v:10074.1-10078.4"
wire width 25 $0\memdat_1[24:0]
- attribute \src "ls180.v:10025.1-10029.4"
+ attribute \src "ls180.v:10088.1-10092.4"
wire width 25 $0\memdat_2[24:0]
- attribute \src "ls180.v:10039.1-10043.4"
+ attribute \src "ls180.v:10102.1-10106.4"
wire width 25 $0\memdat_3[24:0]
- attribute \src "ls180.v:10054.1-10058.4"
+ attribute \src "ls180.v:10117.1-10121.4"
wire width 10 $0\memdat_4[9:0]
- attribute \src "ls180.v:10060.1-10063.4"
+ attribute \src "ls180.v:10123.1-10126.4"
wire width 10 $0\memdat_5[9:0]
- attribute \src "ls180.v:10071.1-10075.4"
+ attribute \src "ls180.v:10134.1-10138.4"
wire width 10 $0\memdat_6[9:0]
- attribute \src "ls180.v:10077.1-10080.4"
+ attribute \src "ls180.v:10140.1-10143.4"
wire width 10 $0\memdat_7[9:0]
- attribute \src "ls180.v:10087.1-10091.4"
+ attribute \src "ls180.v:10150.1-10154.4"
wire width 10 $0\memdat_8[9:0]
- attribute \src "ls180.v:10101.1-10105.4"
+ attribute \src "ls180.v:10164.1-10168.4"
wire width 10 $0\memdat_9[9:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\pwm0[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\pwm1[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire $0\sdcard_clk[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire $0\sdcard_cmd_o[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire $0\sdcard_cmd_oe[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire width 4 $0\sdcard_data_o[3:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire $0\sdcard_data_oe[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire width 13 $0\sdram_a[12:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire width 2 $0\sdram_ba[1:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire $0\sdram_cas_n[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire $0\sdram_cke[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire $0\sdram_clock[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire $0\sdram_cs_n[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire width 2 $0\sdram_dm[1:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire width 16 $0\sdram_dq_o[15:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire $0\sdram_dq_oe[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire $0\sdram_ras_n[0:0]
- attribute \src "ls180.v:7287.1-7357.4"
+ attribute \src "ls180.v:7339.1-7409.4"
wire $0\sdram_we_n[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\spi_master_clk[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\spi_master_cs_n[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\spi_master_mosi[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\spisdcard_clk[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\spisdcard_cs_n[0:0]
- attribute \src "ls180.v:7359.1-9973.4"
+ attribute \src "ls180.v:7411.1-10036.4"
wire $0\spisdcard_mosi[0:0]
- attribute \src "ls180.v:1709.11-1709.49"
+ attribute \src "ls180.v:1725.11-1725.49"
wire width 3 $1\builder_bankmachine0_next_state[2:0]
- attribute \src "ls180.v:1708.11-1708.44"
+ attribute \src "ls180.v:1724.11-1724.44"
wire width 3 $1\builder_bankmachine0_state[2:0]
- attribute \src "ls180.v:1711.11-1711.49"
+ attribute \src "ls180.v:1727.11-1727.49"
wire width 3 $1\builder_bankmachine1_next_state[2:0]
- attribute \src "ls180.v:1710.11-1710.44"
+ attribute \src "ls180.v:1726.11-1726.44"
wire width 3 $1\builder_bankmachine1_state[2:0]
- attribute \src "ls180.v:1713.11-1713.49"
+ attribute \src "ls180.v:1729.11-1729.49"
wire width 3 $1\builder_bankmachine2_next_state[2:0]
- attribute \src "ls180.v:1712.11-1712.44"
+ attribute \src "ls180.v:1728.11-1728.44"
wire width 3 $1\builder_bankmachine2_state[2:0]
- attribute \src "ls180.v:1715.11-1715.49"
+ attribute \src "ls180.v:1731.11-1731.49"
wire width 3 $1\builder_bankmachine3_next_state[2:0]
- attribute \src "ls180.v:1714.11-1714.44"
+ attribute \src "ls180.v:1730.11-1730.44"
wire width 3 $1\builder_bankmachine3_state[2:0]
- attribute \src "ls180.v:2547.5-2547.41"
+ attribute \src "ls180.v:2576.5-2576.41"
wire $1\builder_comb_rhs_array_muxed0[0:0]
- attribute \src "ls180.v:2560.5-2560.42"
+ attribute \src "ls180.v:2589.5-2589.42"
wire $1\builder_comb_rhs_array_muxed10[0:0]
- attribute \src "ls180.v:2561.5-2561.42"
+ attribute \src "ls180.v:2590.5-2590.42"
wire $1\builder_comb_rhs_array_muxed11[0:0]
- attribute \src "ls180.v:2565.12-2565.50"
+ attribute \src "ls180.v:2594.12-2594.50"
wire width 22 $1\builder_comb_rhs_array_muxed12[21:0]
- attribute \src "ls180.v:2566.5-2566.42"
+ attribute \src "ls180.v:2595.5-2595.42"
wire $1\builder_comb_rhs_array_muxed13[0:0]
- attribute \src "ls180.v:2567.5-2567.42"
+ attribute \src "ls180.v:2596.5-2596.42"
wire $1\builder_comb_rhs_array_muxed14[0:0]
- attribute \src "ls180.v:2568.12-2568.50"
+ attribute \src "ls180.v:2597.12-2597.50"
wire width 22 $1\builder_comb_rhs_array_muxed15[21:0]
- attribute \src "ls180.v:2569.5-2569.42"
+ attribute \src "ls180.v:2598.5-2598.42"
wire $1\builder_comb_rhs_array_muxed16[0:0]
- attribute \src "ls180.v:2570.5-2570.42"
+ attribute \src "ls180.v:2599.5-2599.42"
wire $1\builder_comb_rhs_array_muxed17[0:0]
- attribute \src "ls180.v:2571.12-2571.50"
+ attribute \src "ls180.v:2600.12-2600.50"
wire width 22 $1\builder_comb_rhs_array_muxed18[21:0]
- attribute \src "ls180.v:2572.5-2572.42"
+ attribute \src "ls180.v:2601.5-2601.42"
wire $1\builder_comb_rhs_array_muxed19[0:0]
- attribute \src "ls180.v:2548.12-2548.49"
+ attribute \src "ls180.v:2577.12-2577.49"
wire width 13 $1\builder_comb_rhs_array_muxed1[12:0]
- attribute \src "ls180.v:2573.5-2573.42"
+ attribute \src "ls180.v:2602.5-2602.42"
wire $1\builder_comb_rhs_array_muxed20[0:0]
- attribute \src "ls180.v:2574.12-2574.50"
+ attribute \src "ls180.v:2603.12-2603.50"
wire width 22 $1\builder_comb_rhs_array_muxed21[21:0]
- attribute \src "ls180.v:2575.5-2575.42"
+ attribute \src "ls180.v:2604.5-2604.42"
wire $1\builder_comb_rhs_array_muxed22[0:0]
- attribute \src "ls180.v:2576.5-2576.42"
+ attribute \src "ls180.v:2605.5-2605.42"
wire $1\builder_comb_rhs_array_muxed23[0:0]
- attribute \src "ls180.v:2577.12-2577.50"
+ attribute \src "ls180.v:2606.12-2606.50"
wire width 32 $1\builder_comb_rhs_array_muxed24[31:0]
- attribute \src "ls180.v:2578.12-2578.50"
+ attribute \src "ls180.v:2607.12-2607.50"
wire width 32 $1\builder_comb_rhs_array_muxed25[31:0]
- attribute \src "ls180.v:2579.11-2579.48"
+ attribute \src "ls180.v:2608.11-2608.48"
wire width 4 $1\builder_comb_rhs_array_muxed26[3:0]
- attribute \src "ls180.v:2580.5-2580.42"
+ attribute \src "ls180.v:2609.5-2609.42"
wire $1\builder_comb_rhs_array_muxed27[0:0]
- attribute \src "ls180.v:2581.5-2581.42"
+ attribute \src "ls180.v:2610.5-2610.42"
wire $1\builder_comb_rhs_array_muxed28[0:0]
- attribute \src "ls180.v:2582.5-2582.42"
+ attribute \src "ls180.v:2611.5-2611.42"
wire $1\builder_comb_rhs_array_muxed29[0:0]
- attribute \src "ls180.v:2549.11-2549.47"
+ attribute \src "ls180.v:2578.11-2578.47"
wire width 2 $1\builder_comb_rhs_array_muxed2[1:0]
- attribute \src "ls180.v:2583.11-2583.48"
+ attribute \src "ls180.v:2612.11-2612.48"
wire width 3 $1\builder_comb_rhs_array_muxed30[2:0]
- attribute \src "ls180.v:2584.11-2584.48"
+ attribute \src "ls180.v:2613.11-2613.48"
wire width 2 $1\builder_comb_rhs_array_muxed31[1:0]
- attribute \src "ls180.v:2550.5-2550.41"
+ attribute \src "ls180.v:2579.5-2579.41"
wire $1\builder_comb_rhs_array_muxed3[0:0]
- attribute \src "ls180.v:2551.5-2551.41"
+ attribute \src "ls180.v:2580.5-2580.41"
wire $1\builder_comb_rhs_array_muxed4[0:0]
- attribute \src "ls180.v:2552.5-2552.41"
+ attribute \src "ls180.v:2581.5-2581.41"
wire $1\builder_comb_rhs_array_muxed5[0:0]
- attribute \src "ls180.v:2556.5-2556.41"
+ attribute \src "ls180.v:2585.5-2585.41"
wire $1\builder_comb_rhs_array_muxed6[0:0]
- attribute \src "ls180.v:2557.12-2557.49"
+ attribute \src "ls180.v:2586.12-2586.49"
wire width 13 $1\builder_comb_rhs_array_muxed7[12:0]
- attribute \src "ls180.v:2558.11-2558.47"
+ attribute \src "ls180.v:2587.11-2587.47"
wire width 2 $1\builder_comb_rhs_array_muxed8[1:0]
- attribute \src "ls180.v:2559.5-2559.41"
+ attribute \src "ls180.v:2588.5-2588.41"
wire $1\builder_comb_rhs_array_muxed9[0:0]
- attribute \src "ls180.v:2553.5-2553.39"
+ attribute \src "ls180.v:2582.5-2582.39"
wire $1\builder_comb_t_array_muxed0[0:0]
- attribute \src "ls180.v:2554.5-2554.39"
+ attribute \src "ls180.v:2583.5-2583.39"
wire $1\builder_comb_t_array_muxed1[0:0]
- attribute \src "ls180.v:2555.5-2555.39"
+ attribute \src "ls180.v:2584.5-2584.39"
wire $1\builder_comb_t_array_muxed2[0:0]
- attribute \src "ls180.v:2562.5-2562.39"
+ attribute \src "ls180.v:2591.5-2591.39"
wire $1\builder_comb_t_array_muxed3[0:0]
- attribute \src "ls180.v:2563.5-2563.39"
+ attribute \src "ls180.v:2592.5-2592.39"
wire $1\builder_comb_t_array_muxed4[0:0]
- attribute \src "ls180.v:2564.5-2564.39"
+ attribute \src "ls180.v:2593.5-2593.39"
wire $1\builder_comb_t_array_muxed5[0:0]
- attribute \src "ls180.v:1695.5-1695.41"
+ attribute \src "ls180.v:1711.5-1711.41"
wire $1\builder_converter0_next_state[0:0]
- attribute \src "ls180.v:1694.5-1694.36"
+ attribute \src "ls180.v:1710.5-1710.36"
wire $1\builder_converter0_state[0:0]
- attribute \src "ls180.v:1699.5-1699.41"
+ attribute \src "ls180.v:1715.5-1715.41"
wire $1\builder_converter1_next_state[0:0]
- attribute \src "ls180.v:1698.5-1698.36"
+ attribute \src "ls180.v:1714.5-1714.36"
wire $1\builder_converter1_state[0:0]
- attribute \src "ls180.v:1703.5-1703.41"
+ attribute \src "ls180.v:1719.5-1719.41"
wire $1\builder_converter2_next_state[0:0]
- attribute \src "ls180.v:1702.5-1702.36"
+ attribute \src "ls180.v:1718.5-1718.36"
wire $1\builder_converter2_state[0:0]
- attribute \src "ls180.v:1740.5-1740.40"
+ attribute \src "ls180.v:1756.5-1756.40"
wire $1\builder_converter_next_state[0:0]
- attribute \src "ls180.v:1739.5-1739.35"
+ attribute \src "ls180.v:1755.5-1755.35"
wire $1\builder_converter_state[0:0]
- attribute \src "ls180.v:1860.12-1860.39"
+ attribute \src "ls180.v:1876.12-1876.39"
wire width 20 $1\builder_count[19:0]
- attribute \src "ls180.v:1857.5-1857.25"
+ attribute \src "ls180.v:1873.5-1873.25"
wire $1\builder_error[0:0]
- attribute \src "ls180.v:1854.11-1854.31"
+ attribute \src "ls180.v:1870.11-1870.31"
wire width 3 $1\builder_grant[2:0]
- attribute \src "ls180.v:1864.11-1864.51"
+ attribute \src "ls180.v:1880.11-1880.51"
wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2386.11-2386.52"
+ attribute \src "ls180.v:2382.11-2382.52"
wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2427.11-2427.52"
+ attribute \src "ls180.v:2415.11-2415.52"
wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2492.11-2492.52"
+ attribute \src "ls180.v:2456.11-2456.52"
wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2517.11-2517.52"
+ attribute \src "ls180.v:2521.11-2521.52"
wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1905.11-1905.51"
+ attribute \src "ls180.v:2546.11-2546.52"
+ wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0]
+ attribute \src "ls180.v:1921.11-1921.51"
wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1934.11-1934.51"
+ attribute \src "ls180.v:1950.11-1950.51"
wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1975.11-1975.51"
+ attribute \src "ls180.v:1963.11-1963.51"
wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2016.11-2016.51"
+ attribute \src "ls180.v:2004.11-2004.51"
wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2081.11-2081.51"
+ attribute \src "ls180.v:2045.11-2045.51"
wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2214.11-2214.51"
+ attribute \src "ls180.v:2110.11-2110.51"
wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2295.11-2295.51"
+ attribute \src "ls180.v:2243.11-2243.51"
wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2312.11-2312.51"
+ attribute \src "ls180.v:2324.11-2324.51"
wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2353.11-2353.51"
+ attribute \src "ls180.v:2341.11-2341.51"
wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1827.12-1827.43"
+ attribute \src "ls180.v:1843.12-1843.43"
wire width 14 $1\builder_libresocsim_adr[13:0]
- attribute \src "ls180.v:2543.12-2543.55"
+ attribute \src "ls180.v:2572.12-2572.55"
wire width 14 $1\builder_libresocsim_adr_next_value1[13:0]
- attribute \src "ls180.v:2544.5-2544.50"
+ attribute \src "ls180.v:2573.5-2573.50"
wire $1\builder_libresocsim_adr_next_value_ce1[0:0]
- attribute \src "ls180.v:1829.11-1829.43"
+ attribute \src "ls180.v:1845.11-1845.43"
wire width 8 $1\builder_libresocsim_dat_w[7:0]
- attribute \src "ls180.v:2541.11-2541.55"
+ attribute \src "ls180.v:2570.11-2570.55"
wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0]
- attribute \src "ls180.v:2542.5-2542.52"
+ attribute \src "ls180.v:2571.5-2571.52"
wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0]
- attribute \src "ls180.v:1828.5-1828.34"
+ attribute \src "ls180.v:1844.5-1844.34"
wire $1\builder_libresocsim_we[0:0]
- attribute \src "ls180.v:2545.5-2545.46"
+ attribute \src "ls180.v:2574.5-2574.46"
wire $1\builder_libresocsim_we_next_value2[0:0]
- attribute \src "ls180.v:2546.5-2546.49"
+ attribute \src "ls180.v:2575.5-2575.49"
wire $1\builder_libresocsim_we_next_value_ce2[0:0]
- attribute \src "ls180.v:1837.5-1837.44"
+ attribute \src "ls180.v:1853.5-1853.44"
wire $1\builder_libresocsim_wishbone_ack[0:0]
- attribute \src "ls180.v:1833.12-1833.54"
+ attribute \src "ls180.v:1849.12-1849.54"
wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0]
- attribute \src "ls180.v:1717.11-1717.48"
+ attribute \src "ls180.v:1733.11-1733.48"
wire width 3 $1\builder_multiplexer_next_state[2:0]
- attribute \src "ls180.v:1716.11-1716.43"
+ attribute \src "ls180.v:1732.11-1732.43"
wire width 3 $1\builder_multiplexer_state[2:0]
- attribute \src "ls180.v:2650.32-2650.66"
+ attribute \src "ls180.v:2679.32-2679.66"
wire $1\builder_multiregimpl0_regs0[0:0]
- attribute \src "ls180.v:2651.32-2651.66"
+ attribute \src "ls180.v:2680.32-2680.66"
wire $1\builder_multiregimpl0_regs1[0:0]
- attribute \src "ls180.v:2670.32-2670.67"
+ attribute \src "ls180.v:2699.32-2699.67"
wire $1\builder_multiregimpl10_regs0[0:0]
- attribute \src "ls180.v:2671.32-2671.67"
+ attribute \src "ls180.v:2700.32-2700.67"
wire $1\builder_multiregimpl10_regs1[0:0]
- attribute \src "ls180.v:2672.32-2672.67"
+ attribute \src "ls180.v:2701.32-2701.67"
wire $1\builder_multiregimpl11_regs0[0:0]
- attribute \src "ls180.v:2673.32-2673.67"
+ attribute \src "ls180.v:2702.32-2702.67"
wire $1\builder_multiregimpl11_regs1[0:0]
- attribute \src "ls180.v:2674.32-2674.67"
+ attribute \src "ls180.v:2703.32-2703.67"
wire $1\builder_multiregimpl12_regs0[0:0]
- attribute \src "ls180.v:2675.32-2675.67"
+ attribute \src "ls180.v:2704.32-2704.67"
wire $1\builder_multiregimpl12_regs1[0:0]
- attribute \src "ls180.v:2676.32-2676.67"
+ attribute \src "ls180.v:2705.32-2705.67"
wire $1\builder_multiregimpl13_regs0[0:0]
- attribute \src "ls180.v:2677.32-2677.67"
+ attribute \src "ls180.v:2706.32-2706.67"
wire $1\builder_multiregimpl13_regs1[0:0]
- attribute \src "ls180.v:2678.32-2678.67"
+ attribute \src "ls180.v:2707.32-2707.67"
wire $1\builder_multiregimpl14_regs0[0:0]
- attribute \src "ls180.v:2679.32-2679.67"
+ attribute \src "ls180.v:2708.32-2708.67"
wire $1\builder_multiregimpl14_regs1[0:0]
- attribute \src "ls180.v:2680.32-2680.67"
+ attribute \src "ls180.v:2709.32-2709.67"
wire $1\builder_multiregimpl15_regs0[0:0]
- attribute \src "ls180.v:2681.32-2681.67"
+ attribute \src "ls180.v:2710.32-2710.67"
wire $1\builder_multiregimpl15_regs1[0:0]
- attribute \src "ls180.v:2682.32-2682.67"
+ attribute \src "ls180.v:2711.32-2711.67"
wire $1\builder_multiregimpl16_regs0[0:0]
- attribute \src "ls180.v:2683.32-2683.67"
+ attribute \src "ls180.v:2712.32-2712.67"
wire $1\builder_multiregimpl16_regs1[0:0]
- attribute \src "ls180.v:2652.32-2652.66"
+ attribute \src "ls180.v:2681.32-2681.66"
wire $1\builder_multiregimpl1_regs0[0:0]
- attribute \src "ls180.v:2653.32-2653.66"
+ attribute \src "ls180.v:2682.32-2682.66"
wire $1\builder_multiregimpl1_regs1[0:0]
- attribute \src "ls180.v:2654.32-2654.66"
+ attribute \src "ls180.v:2683.32-2683.66"
wire $1\builder_multiregimpl2_regs0[0:0]
- attribute \src "ls180.v:2655.32-2655.66"
+ attribute \src "ls180.v:2684.32-2684.66"
wire $1\builder_multiregimpl2_regs1[0:0]
- attribute \src "ls180.v:2656.32-2656.66"
+ attribute \src "ls180.v:2685.32-2685.66"
wire $1\builder_multiregimpl3_regs0[0:0]
- attribute \src "ls180.v:2657.32-2657.66"
+ attribute \src "ls180.v:2686.32-2686.66"
wire $1\builder_multiregimpl3_regs1[0:0]
- attribute \src "ls180.v:2658.32-2658.66"
+ attribute \src "ls180.v:2687.32-2687.66"
wire $1\builder_multiregimpl4_regs0[0:0]
- attribute \src "ls180.v:2659.32-2659.66"
+ attribute \src "ls180.v:2688.32-2688.66"
wire $1\builder_multiregimpl4_regs1[0:0]
- attribute \src "ls180.v:2660.32-2660.66"
+ attribute \src "ls180.v:2689.32-2689.66"
wire $1\builder_multiregimpl5_regs0[0:0]
- attribute \src "ls180.v:2661.32-2661.66"
+ attribute \src "ls180.v:2690.32-2690.66"
wire $1\builder_multiregimpl5_regs1[0:0]
- attribute \src "ls180.v:2662.32-2662.66"
+ attribute \src "ls180.v:2691.32-2691.66"
wire $1\builder_multiregimpl6_regs0[0:0]
- attribute \src "ls180.v:2663.32-2663.66"
+ attribute \src "ls180.v:2692.32-2692.66"
wire $1\builder_multiregimpl6_regs1[0:0]
- attribute \src "ls180.v:2664.32-2664.66"
+ attribute \src "ls180.v:2693.32-2693.66"
wire $1\builder_multiregimpl7_regs0[0:0]
- attribute \src "ls180.v:2665.32-2665.66"
+ attribute \src "ls180.v:2694.32-2694.66"
wire $1\builder_multiregimpl7_regs1[0:0]
- attribute \src "ls180.v:2666.32-2666.66"
+ attribute \src "ls180.v:2695.32-2695.66"
wire $1\builder_multiregimpl8_regs0[0:0]
- attribute \src "ls180.v:2667.32-2667.66"
+ attribute \src "ls180.v:2696.32-2696.66"
wire $1\builder_multiregimpl8_regs1[0:0]
- attribute \src "ls180.v:2668.32-2668.66"
+ attribute \src "ls180.v:2697.32-2697.66"
wire $1\builder_multiregimpl9_regs0[0:0]
- attribute \src "ls180.v:2669.32-2669.66"
+ attribute \src "ls180.v:2698.32-2698.66"
wire $1\builder_multiregimpl9_regs1[0:0]
- attribute \src "ls180.v:1735.5-1735.43"
+ attribute \src "ls180.v:1751.5-1751.43"
wire $1\builder_new_master_rdata_valid0[0:0]
- attribute \src "ls180.v:1736.5-1736.43"
+ attribute \src "ls180.v:1752.5-1752.43"
wire $1\builder_new_master_rdata_valid1[0:0]
- attribute \src "ls180.v:1737.5-1737.43"
+ attribute \src "ls180.v:1753.5-1753.43"
wire $1\builder_new_master_rdata_valid2[0:0]
- attribute \src "ls180.v:1738.5-1738.43"
+ attribute \src "ls180.v:1754.5-1754.43"
wire $1\builder_new_master_rdata_valid3[0:0]
- attribute \src "ls180.v:1734.5-1734.42"
+ attribute \src "ls180.v:1750.5-1750.42"
wire $1\builder_new_master_wdata_ready[0:0]
- attribute \src "ls180.v:2540.11-2540.36"
+ attribute \src "ls180.v:2569.11-2569.36"
wire width 2 $1\builder_next_state[1:0]
- attribute \src "ls180.v:1707.11-1707.46"
+ attribute \src "ls180.v:1723.11-1723.46"
wire width 2 $1\builder_refresher_next_state[1:0]
- attribute \src "ls180.v:1706.11-1706.41"
+ attribute \src "ls180.v:1722.11-1722.41"
wire width 2 $1\builder_refresher_state[1:0]
- attribute \src "ls180.v:1812.11-1812.51"
+ attribute \src "ls180.v:1828.11-1828.51"
wire width 2 $1\builder_sdblock2memdma_next_state[1:0]
- attribute \src "ls180.v:1811.11-1811.46"
+ attribute \src "ls180.v:1827.11-1827.46"
wire width 2 $1\builder_sdblock2memdma_state[1:0]
- attribute \src "ls180.v:1780.5-1780.57"
+ attribute \src "ls180.v:1796.5-1796.57"
wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0]
- attribute \src "ls180.v:1779.5-1779.52"
+ attribute \src "ls180.v:1795.5-1795.52"
wire $1\builder_sdcore_crcupstreaminserter_state[0:0]
- attribute \src "ls180.v:1792.11-1792.47"
+ attribute \src "ls180.v:1808.11-1808.47"
wire width 3 $1\builder_sdcore_fsm_next_state[2:0]
- attribute \src "ls180.v:1791.11-1791.42"
+ attribute \src "ls180.v:1807.11-1807.42"
wire width 3 $1\builder_sdcore_fsm_state[2:0]
- attribute \src "ls180.v:1816.5-1816.49"
+ attribute \src "ls180.v:1832.5-1832.49"
wire $1\builder_sdmem2blockdma_fsm_next_state[0:0]
- attribute \src "ls180.v:1815.5-1815.44"
+ attribute \src "ls180.v:1831.5-1831.44"
wire $1\builder_sdmem2blockdma_fsm_state[0:0]
- attribute \src "ls180.v:1820.11-1820.65"
+ attribute \src "ls180.v:1836.11-1836.65"
wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0]
- attribute \src "ls180.v:1819.11-1819.60"
+ attribute \src "ls180.v:1835.11-1835.60"
wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0]
- attribute \src "ls180.v:1768.11-1768.46"
+ attribute \src "ls180.v:1784.11-1784.46"
wire width 3 $1\builder_sdphy_fsm_next_state[2:0]
- attribute \src "ls180.v:1767.11-1767.41"
+ attribute \src "ls180.v:1783.11-1783.41"
wire width 3 $1\builder_sdphy_fsm_state[2:0]
- attribute \src "ls180.v:1756.11-1756.52"
+ attribute \src "ls180.v:1772.11-1772.52"
wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0]
- attribute \src "ls180.v:1755.11-1755.47"
+ attribute \src "ls180.v:1771.11-1771.47"
wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0]
- attribute \src "ls180.v:1752.11-1752.52"
+ attribute \src "ls180.v:1768.11-1768.52"
wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0]
- attribute \src "ls180.v:1751.11-1751.47"
+ attribute \src "ls180.v:1767.11-1767.47"
wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0]
- attribute \src "ls180.v:1764.5-1764.46"
+ attribute \src "ls180.v:1780.5-1780.46"
wire $1\builder_sdphy_sdphycrcr_next_state[0:0]
- attribute \src "ls180.v:1763.5-1763.41"
+ attribute \src "ls180.v:1779.5-1779.41"
wire $1\builder_sdphy_sdphycrcr_state[0:0]
- attribute \src "ls180.v:1772.11-1772.53"
+ attribute \src "ls180.v:1788.11-1788.53"
wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0]
- attribute \src "ls180.v:1771.11-1771.48"
+ attribute \src "ls180.v:1787.11-1787.48"
wire width 3 $1\builder_sdphy_sdphydatar_state[2:0]
- attribute \src "ls180.v:1748.5-1748.46"
+ attribute \src "ls180.v:1764.5-1764.46"
wire $1\builder_sdphy_sdphyinit_next_state[0:0]
- attribute \src "ls180.v:1747.5-1747.41"
+ attribute \src "ls180.v:1763.5-1763.41"
wire $1\builder_sdphy_sdphyinit_state[0:0]
- attribute \src "ls180.v:1848.5-1848.30"
+ attribute \src "ls180.v:1864.5-1864.30"
wire $1\builder_shared_ack[0:0]
- attribute \src "ls180.v:1844.12-1844.40"
+ attribute \src "ls180.v:1860.12-1860.40"
wire width 32 $1\builder_shared_dat_r[31:0]
- attribute \src "ls180.v:1855.11-1855.35"
+ attribute \src "ls180.v:1871.11-1871.35"
wire width 5 $1\builder_slave_sel[4:0]
- attribute \src "ls180.v:1856.11-1856.37"
+ attribute \src "ls180.v:1872.11-1872.37"
wire width 5 $1\builder_slave_sel_r[4:0]
- attribute \src "ls180.v:1744.11-1744.47"
+ attribute \src "ls180.v:1760.11-1760.47"
wire width 2 $1\builder_spimaster0_next_state[1:0]
- attribute \src "ls180.v:1743.11-1743.42"
+ attribute \src "ls180.v:1759.11-1759.42"
wire width 2 $1\builder_spimaster0_state[1:0]
- attribute \src "ls180.v:1824.11-1824.47"
+ attribute \src "ls180.v:1840.11-1840.47"
wire width 2 $1\builder_spimaster1_next_state[1:0]
- attribute \src "ls180.v:1823.11-1823.42"
+ attribute \src "ls180.v:1839.11-1839.42"
wire width 2 $1\builder_spimaster1_state[1:0]
- attribute \src "ls180.v:2539.11-2539.31"
+ attribute \src "ls180.v:2568.11-2568.31"
wire width 2 $1\builder_state[1:0]
- attribute \src "ls180.v:2592.5-2592.39"
+ attribute \src "ls180.v:2621.5-2621.39"
wire $1\builder_sync_f_array_muxed0[0:0]
- attribute \src "ls180.v:2593.5-2593.39"
+ attribute \src "ls180.v:2622.5-2622.39"
wire $1\builder_sync_f_array_muxed1[0:0]
- attribute \src "ls180.v:2585.11-2585.47"
+ attribute \src "ls180.v:2614.11-2614.47"
wire width 2 $1\builder_sync_rhs_array_muxed0[1:0]
- attribute \src "ls180.v:2586.12-2586.49"
+ attribute \src "ls180.v:2615.12-2615.49"
wire width 13 $1\builder_sync_rhs_array_muxed1[12:0]
- attribute \src "ls180.v:2587.5-2587.41"
+ attribute \src "ls180.v:2616.5-2616.41"
wire $1\builder_sync_rhs_array_muxed2[0:0]
- attribute \src "ls180.v:2588.5-2588.41"
+ attribute \src "ls180.v:2617.5-2617.41"
wire $1\builder_sync_rhs_array_muxed3[0:0]
- attribute \src "ls180.v:2589.5-2589.41"
+ attribute \src "ls180.v:2618.5-2618.41"
wire $1\builder_sync_rhs_array_muxed4[0:0]
- attribute \src "ls180.v:2590.5-2590.41"
+ attribute \src "ls180.v:2619.5-2619.41"
wire $1\builder_sync_rhs_array_muxed5[0:0]
- attribute \src "ls180.v:2591.5-2591.41"
+ attribute \src "ls180.v:2620.5-2620.41"
wire $1\builder_sync_rhs_array_muxed6[0:0]
- attribute \src "ls180.v:1686.12-1686.44"
+ attribute \src "ls180.v:1702.12-1702.44"
wire width 16 $1\libresocsim_clk_divider1[15:0]
- attribute \src "ls180.v:1681.5-1681.34"
+ attribute \src "ls180.v:1697.5-1697.34"
wire $1\libresocsim_clk_enable[0:0]
- attribute \src "ls180.v:1668.5-1668.34"
+ attribute \src "ls180.v:1684.5-1684.34"
wire $1\libresocsim_control_re[0:0]
- attribute \src "ls180.v:1667.12-1667.47"
+ attribute \src "ls180.v:1683.12-1683.47"
wire width 16 $1\libresocsim_control_storage[15:0]
- attribute \src "ls180.v:1683.11-1683.35"
+ attribute \src "ls180.v:1699.11-1699.35"
wire width 3 $1\libresocsim_count[2:0]
- attribute \src "ls180.v:1825.11-1825.57"
+ attribute \src "ls180.v:1841.11-1841.57"
wire width 3 $1\libresocsim_count_spimaster1_next_value[2:0]
- attribute \src "ls180.v:1826.5-1826.54"
+ attribute \src "ls180.v:1842.5-1842.54"
wire $1\libresocsim_count_spimaster1_next_value_ce[0:0]
- attribute \src "ls180.v:1682.5-1682.33"
+ attribute \src "ls180.v:1698.5-1698.33"
wire $1\libresocsim_cs_enable[0:0]
- attribute \src "ls180.v:1678.5-1678.29"
+ attribute \src "ls180.v:1694.5-1694.29"
wire $1\libresocsim_cs_re[0:0]
- attribute \src "ls180.v:1677.5-1677.34"
+ attribute \src "ls180.v:1693.5-1693.34"
wire $1\libresocsim_cs_storage[0:0]
- attribute \src "ls180.v:1658.5-1658.29"
+ attribute \src "ls180.v:1674.5-1674.29"
wire $1\libresocsim_done0[0:0]
- attribute \src "ls180.v:1659.5-1659.27"
+ attribute \src "ls180.v:1675.5-1675.27"
wire $1\libresocsim_irq[0:0]
- attribute \src "ls180.v:1680.5-1680.35"
+ attribute \src "ls180.v:1696.5-1696.35"
wire $1\libresocsim_loopback_re[0:0]
- attribute \src "ls180.v:1679.5-1679.40"
+ attribute \src "ls180.v:1695.5-1695.40"
wire $1\libresocsim_loopback_storage[0:0]
- attribute \src "ls180.v:1661.11-1661.34"
+ attribute \src "ls180.v:1677.11-1677.34"
wire width 8 $1\libresocsim_miso[7:0]
- attribute \src "ls180.v:1691.11-1691.39"
+ attribute \src "ls180.v:1707.11-1707.39"
wire width 8 $1\libresocsim_miso_data[7:0]
- attribute \src "ls180.v:1685.5-1685.34"
+ attribute \src "ls180.v:1701.5-1701.34"
wire $1\libresocsim_miso_latch[0:0]
- attribute \src "ls180.v:1689.11-1689.39"
+ attribute \src "ls180.v:1705.11-1705.39"
wire width 8 $1\libresocsim_mosi_data[7:0]
- attribute \src "ls180.v:1684.5-1684.34"
+ attribute \src "ls180.v:1700.5-1700.34"
wire $1\libresocsim_mosi_latch[0:0]
- attribute \src "ls180.v:1673.5-1673.31"
+ attribute \src "ls180.v:1689.5-1689.31"
wire $1\libresocsim_mosi_re[0:0]
- attribute \src "ls180.v:1690.11-1690.38"
+ attribute \src "ls180.v:1706.11-1706.38"
wire width 3 $1\libresocsim_mosi_sel[2:0]
- attribute \src "ls180.v:1672.11-1672.42"
+ attribute \src "ls180.v:1688.11-1688.42"
wire width 8 $1\libresocsim_mosi_storage[7:0]
- attribute \src "ls180.v:1693.5-1693.26"
+ attribute \src "ls180.v:1709.5-1709.26"
wire $1\libresocsim_re[0:0]
- attribute \src "ls180.v:1665.5-1665.30"
+ attribute \src "ls180.v:1681.5-1681.30"
wire $1\libresocsim_start1[0:0]
- attribute \src "ls180.v:1692.12-1692.41"
+ attribute \src "ls180.v:1708.12-1708.41"
wire width 16 $1\libresocsim_storage[15:0]
- attribute \src "ls180.v:804.5-804.29"
+ attribute \src "ls180.v:812.5-812.29"
wire $1\main_cmd_consumed[0:0]
- attribute \src "ls180.v:801.5-801.34"
+ attribute \src "ls180.v:809.5-809.34"
wire $1\main_converter_counter[0:0]
- attribute \src "ls180.v:1741.5-1741.55"
+ attribute \src "ls180.v:1757.5-1757.55"
wire $1\main_converter_counter_converter_next_value[0:0]
- attribute \src "ls180.v:1742.5-1742.58"
+ attribute \src "ls180.v:1758.5-1758.58"
wire $1\main_converter_counter_converter_next_value_ce[0:0]
- attribute \src "ls180.v:803.12-803.40"
+ attribute \src "ls180.v:811.12-811.40"
wire width 32 $1\main_converter_dat_r[31:0]
- attribute \src "ls180.v:800.5-800.31"
+ attribute \src "ls180.v:808.5-808.31"
wire $1\main_converter_skip[0:0]
- attribute \src "ls180.v:235.12-235.38"
+ attribute \src "ls180.v:243.12-243.38"
wire width 16 $1\main_dfi_p0_rddata[15:0]
- attribute \src "ls180.v:236.5-236.36"
+ attribute \src "ls180.v:244.5-244.36"
wire $1\main_dfi_p0_rddata_valid[0:0]
- attribute \src "ls180.v:997.12-997.30"
- wire width 42 $1\main_dummy[41:0]
- attribute \src "ls180.v:952.5-952.27"
+ attribute \src "ls180.v:1005.12-1005.30"
+ wire width 36 $1\main_dummy[35:0]
+ attribute \src "ls180.v:960.5-960.27"
wire $1\main_gpio_oe_re[0:0]
- attribute \src "ls180.v:951.12-951.40"
+ attribute \src "ls180.v:959.12-959.40"
wire width 16 $1\main_gpio_oe_storage[15:0]
- attribute \src "ls180.v:956.5-956.28"
+ attribute \src "ls180.v:964.5-964.28"
wire $1\main_gpio_out_re[0:0]
- attribute \src "ls180.v:955.12-955.41"
+ attribute \src "ls180.v:963.12-963.41"
wire width 16 $1\main_gpio_out_storage[15:0]
- attribute \src "ls180.v:953.12-953.36"
+ attribute \src "ls180.v:961.12-961.36"
wire width 16 $1\main_gpio_status[15:0]
- attribute \src "ls180.v:220.5-220.24"
+ attribute \src "ls180.v:1030.5-1030.23"
+ wire $1\main_i2c_re[0:0]
+ attribute \src "ls180.v:1029.11-1029.34"
+ wire width 3 $1\main_i2c_storage[2:0]
+ attribute \src "ls180.v:228.5-228.24"
wire $1\main_int_rst[0:0]
- attribute \src "ls180.v:1562.12-1562.43"
+ attribute \src "ls180.v:1578.12-1578.43"
wire width 32 $1\main_interface1_bus_adr[31:0]
- attribute \src "ls180.v:1566.5-1566.35"
+ attribute \src "ls180.v:1582.5-1582.35"
wire $1\main_interface1_bus_cyc[0:0]
- attribute \src "ls180.v:1565.11-1565.41"
+ attribute \src "ls180.v:1581.11-1581.41"
wire width 4 $1\main_interface1_bus_sel[3:0]
- attribute \src "ls180.v:1567.5-1567.35"
+ attribute \src "ls180.v:1583.5-1583.35"
wire $1\main_interface1_bus_stb[0:0]
- attribute \src "ls180.v:1569.5-1569.34"
+ attribute \src "ls180.v:1585.5-1585.34"
wire $1\main_interface1_bus_we[0:0]
- attribute \src "ls180.v:57.12-57.47"
+ attribute \src "ls180.v:63.12-63.47"
wire width 32 $1\main_libresocsim_bus_errors[31:0]
- attribute \src "ls180.v:142.5-142.47"
+ attribute \src "ls180.v:150.5-150.47"
wire $1\main_libresocsim_converter0_counter[0:0]
- attribute \src "ls180.v:1696.5-1696.69"
+ attribute \src "ls180.v:1712.5-1712.69"
wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0]
- attribute \src "ls180.v:1697.5-1697.72"
+ attribute \src "ls180.v:1713.5-1713.72"
wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
- attribute \src "ls180.v:144.12-144.53"
+ attribute \src "ls180.v:152.12-152.53"
wire width 64 $1\main_libresocsim_converter0_dat_r[63:0]
- attribute \src "ls180.v:141.5-141.44"
+ attribute \src "ls180.v:149.5-149.44"
wire $1\main_libresocsim_converter0_skip[0:0]
- attribute \src "ls180.v:157.5-157.47"
+ attribute \src "ls180.v:165.5-165.47"
wire $1\main_libresocsim_converter1_counter[0:0]
- attribute \src "ls180.v:1700.5-1700.69"
+ attribute \src "ls180.v:1716.5-1716.69"
wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0]
- attribute \src "ls180.v:1701.5-1701.72"
+ attribute \src "ls180.v:1717.5-1717.72"
wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
- attribute \src "ls180.v:159.12-159.53"
+ attribute \src "ls180.v:167.12-167.53"
wire width 64 $1\main_libresocsim_converter1_dat_r[63:0]
- attribute \src "ls180.v:156.5-156.44"
+ attribute \src "ls180.v:164.5-164.44"
wire $1\main_libresocsim_converter1_skip[0:0]
- attribute \src "ls180.v:172.5-172.47"
+ attribute \src "ls180.v:180.5-180.47"
wire $1\main_libresocsim_converter2_counter[0:0]
- attribute \src "ls180.v:1704.5-1704.69"
+ attribute \src "ls180.v:1720.5-1720.69"
wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0]
- attribute \src "ls180.v:1705.5-1705.72"
+ attribute \src "ls180.v:1721.5-1721.72"
wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
- attribute \src "ls180.v:174.12-174.53"
+ attribute \src "ls180.v:182.12-182.53"
wire width 64 $1\main_libresocsim_converter2_dat_r[63:0]
- attribute \src "ls180.v:171.5-171.44"
+ attribute \src "ls180.v:179.5-179.44"
wire $1\main_libresocsim_converter2_skip[0:0]
- attribute \src "ls180.v:195.5-195.34"
+ attribute \src "ls180.v:203.5-203.34"
wire $1\main_libresocsim_en_re[0:0]
- attribute \src "ls180.v:194.5-194.39"
+ attribute \src "ls180.v:202.5-202.39"
wire $1\main_libresocsim_en_storage[0:0]
- attribute \src "ls180.v:215.5-215.44"
+ attribute \src "ls180.v:223.5-223.44"
wire $1\main_libresocsim_eventmanager_re[0:0]
- attribute \src "ls180.v:214.5-214.49"
+ attribute \src "ls180.v:222.5-222.49"
wire $1\main_libresocsim_eventmanager_storage[0:0]
- attribute \src "ls180.v:130.12-130.71"
+ attribute \src "ls180.v:138.12-138.71"
wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0]
- attribute \src "ls180.v:134.5-134.63"
+ attribute \src "ls180.v:142.5-142.63"
wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0]
- attribute \src "ls180.v:131.12-131.73"
+ attribute \src "ls180.v:139.12-139.73"
wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0]
- attribute \src "ls180.v:133.11-133.69"
+ attribute \src "ls180.v:141.11-141.69"
wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0]
- attribute \src "ls180.v:135.5-135.63"
+ attribute \src "ls180.v:143.5-143.63"
wire $1\main_libresocsim_interface0_converted_interface_stb[0:0]
- attribute \src "ls180.v:137.5-137.62"
+ attribute \src "ls180.v:145.5-145.62"
wire $1\main_libresocsim_interface0_converted_interface_we[0:0]
- attribute \src "ls180.v:145.12-145.71"
+ attribute \src "ls180.v:153.12-153.71"
wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0]
- attribute \src "ls180.v:149.5-149.63"
+ attribute \src "ls180.v:157.5-157.63"
wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0]
- attribute \src "ls180.v:146.12-146.73"
+ attribute \src "ls180.v:154.12-154.73"
wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0]
- attribute \src "ls180.v:148.11-148.69"
+ attribute \src "ls180.v:156.11-156.69"
wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0]
- attribute \src "ls180.v:150.5-150.63"
+ attribute \src "ls180.v:158.5-158.63"
wire $1\main_libresocsim_interface1_converted_interface_stb[0:0]
- attribute \src "ls180.v:152.5-152.62"
+ attribute \src "ls180.v:160.5-160.62"
wire $1\main_libresocsim_interface1_converted_interface_we[0:0]
- attribute \src "ls180.v:160.12-160.71"
+ attribute \src "ls180.v:168.12-168.71"
wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0]
- attribute \src "ls180.v:164.5-164.63"
+ attribute \src "ls180.v:172.5-172.63"
wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0]
- attribute \src "ls180.v:161.12-161.73"
+ attribute \src "ls180.v:169.12-169.73"
wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0]
- attribute \src "ls180.v:163.11-163.69"
+ attribute \src "ls180.v:171.11-171.69"
wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0]
- attribute \src "ls180.v:165.5-165.63"
+ attribute \src "ls180.v:173.5-173.63"
wire $1\main_libresocsim_interface2_converted_interface_stb[0:0]
- attribute \src "ls180.v:167.5-167.62"
+ attribute \src "ls180.v:175.5-175.62"
wire $1\main_libresocsim_interface2_converted_interface_we[0:0]
- attribute \src "ls180.v:120.5-120.65"
+ attribute \src "ls180.v:128.5-128.65"
wire $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0]
- attribute \src "ls180.v:66.5-66.46"
+ attribute \src "ls180.v:72.5-72.46"
wire $1\main_libresocsim_libresoc_dbus_ack[0:0]
- attribute \src "ls180.v:77.5-77.46"
+ attribute \src "ls180.v:83.5-83.46"
wire $1\main_libresocsim_libresoc_ibus_ack[0:0]
- attribute \src "ls180.v:59.12-59.55"
+ attribute \src "ls180.v:65.12-65.55"
wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0]
- attribute \src "ls180.v:110.5-110.49"
+ attribute \src "ls180.v:116.5-116.49"
wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0]
- attribute \src "ls180.v:191.5-191.36"
+ attribute \src "ls180.v:199.5-199.36"
wire $1\main_libresocsim_load_re[0:0]
- attribute \src "ls180.v:190.12-190.49"
+ attribute \src "ls180.v:198.12-198.49"
wire width 32 $1\main_libresocsim_load_storage[31:0]
- attribute \src "ls180.v:181.5-181.40"
+ attribute \src "ls180.v:189.5-189.40"
wire $1\main_libresocsim_ram_bus_ack[0:0]
- attribute \src "ls180.v:193.5-193.38"
+ attribute \src "ls180.v:201.5-201.38"
wire $1\main_libresocsim_reload_re[0:0]
- attribute \src "ls180.v:192.12-192.51"
+ attribute \src "ls180.v:200.12-200.51"
wire width 32 $1\main_libresocsim_reload_storage[31:0]
- attribute \src "ls180.v:50.5-50.37"
+ attribute \src "ls180.v:56.5-56.37"
wire $1\main_libresocsim_reset_re[0:0]
- attribute \src "ls180.v:49.5-49.42"
+ attribute \src "ls180.v:55.5-55.42"
wire $1\main_libresocsim_reset_storage[0:0]
- attribute \src "ls180.v:52.5-52.39"
+ attribute \src "ls180.v:58.5-58.39"
wire $1\main_libresocsim_scratch_re[0:0]
- attribute \src "ls180.v:51.12-51.60"
+ attribute \src "ls180.v:57.12-57.60"
wire width 32 $1\main_libresocsim_scratch_storage[31:0]
- attribute \src "ls180.v:197.5-197.44"
+ attribute \src "ls180.v:205.5-205.44"
wire $1\main_libresocsim_update_value_re[0:0]
- attribute \src "ls180.v:196.5-196.49"
+ attribute \src "ls180.v:204.5-204.49"
wire $1\main_libresocsim_update_value_storage[0:0]
- attribute \src "ls180.v:216.12-216.42"
+ attribute \src "ls180.v:224.12-224.42"
wire width 32 $1\main_libresocsim_value[31:0]
- attribute \src "ls180.v:198.12-198.49"
+ attribute \src "ls180.v:206.12-206.49"
wire width 32 $1\main_libresocsim_value_status[31:0]
- attribute \src "ls180.v:188.11-188.37"
+ attribute \src "ls180.v:196.11-196.37"
wire width 4 $1\main_libresocsim_we[3:0]
- attribute \src "ls180.v:204.5-204.39"
+ attribute \src "ls180.v:212.5-212.39"
wire $1\main_libresocsim_zero_clear[0:0]
- attribute \src "ls180.v:205.5-205.45"
+ attribute \src "ls180.v:213.5-213.45"
wire $1\main_libresocsim_zero_old_trigger[0:0]
- attribute \src "ls180.v:202.5-202.41"
+ attribute \src "ls180.v:210.5-210.41"
wire $1\main_libresocsim_zero_pending[0:0]
- attribute \src "ls180.v:792.12-792.40"
+ attribute \src "ls180.v:800.12-800.40"
wire width 30 $1\main_litedram_wb_adr[29:0]
- attribute \src "ls180.v:796.5-796.32"
+ attribute \src "ls180.v:804.5-804.32"
wire $1\main_litedram_wb_cyc[0:0]
- attribute \src "ls180.v:793.12-793.42"
+ attribute \src "ls180.v:801.12-801.42"
wire width 16 $1\main_litedram_wb_dat_w[15:0]
- attribute \src "ls180.v:795.11-795.38"
+ attribute \src "ls180.v:803.11-803.38"
wire width 2 $1\main_litedram_wb_sel[1:0]
- attribute \src "ls180.v:797.5-797.32"
+ attribute \src "ls180.v:805.5-805.32"
wire $1\main_litedram_wb_stb[0:0]
- attribute \src "ls180.v:799.5-799.31"
+ attribute \src "ls180.v:807.5-807.31"
wire $1\main_litedram_wb_we[0:0]
- attribute \src "ls180.v:827.12-827.45"
- wire width 32 $1\main_phase_accumulator_rx[31:0]
- attribute \src "ls180.v:817.12-817.45"
- wire width 32 $1\main_phase_accumulator_tx[31:0]
- attribute \src "ls180.v:1001.12-1001.37"
+ attribute \src "ls180.v:1009.12-1009.37"
wire width 32 $1\main_pwm0_counter[31:0]
- attribute \src "ls180.v:1003.5-1003.31"
+ attribute \src "ls180.v:1011.5-1011.31"
wire $1\main_pwm0_enable_re[0:0]
- attribute \src "ls180.v:1002.5-1002.36"
+ attribute \src "ls180.v:1010.5-1010.36"
wire $1\main_pwm0_enable_storage[0:0]
- attribute \src "ls180.v:1007.5-1007.31"
+ attribute \src "ls180.v:1015.5-1015.31"
wire $1\main_pwm0_period_re[0:0]
- attribute \src "ls180.v:1006.12-1006.44"
+ attribute \src "ls180.v:1014.12-1014.44"
wire width 32 $1\main_pwm0_period_storage[31:0]
- attribute \src "ls180.v:1005.5-1005.30"
+ attribute \src "ls180.v:1013.5-1013.30"
wire $1\main_pwm0_width_re[0:0]
- attribute \src "ls180.v:1004.12-1004.43"
+ attribute \src "ls180.v:1012.12-1012.43"
wire width 32 $1\main_pwm0_width_storage[31:0]
- attribute \src "ls180.v:1011.12-1011.37"
+ attribute \src "ls180.v:1019.12-1019.37"
wire width 32 $1\main_pwm1_counter[31:0]
- attribute \src "ls180.v:1013.5-1013.31"
+ attribute \src "ls180.v:1021.5-1021.31"
wire $1\main_pwm1_enable_re[0:0]
- attribute \src "ls180.v:1012.5-1012.36"
+ attribute \src "ls180.v:1020.5-1020.36"
wire $1\main_pwm1_enable_storage[0:0]
- attribute \src "ls180.v:1017.5-1017.31"
+ attribute \src "ls180.v:1025.5-1025.31"
wire $1\main_pwm1_period_re[0:0]
- attribute \src "ls180.v:1016.12-1016.44"
+ attribute \src "ls180.v:1024.12-1024.44"
wire width 32 $1\main_pwm1_period_storage[31:0]
- attribute \src "ls180.v:1015.5-1015.30"
+ attribute \src "ls180.v:1023.5-1023.30"
wire $1\main_pwm1_width_re[0:0]
- attribute \src "ls180.v:1014.12-1014.43"
+ attribute \src "ls180.v:1022.12-1022.43"
wire width 32 $1\main_pwm1_width_storage[31:0]
- attribute \src "ls180.v:237.11-237.32"
+ attribute \src "ls180.v:245.11-245.32"
wire width 3 $1\main_rddata_en[2:0]
- attribute \src "ls180.v:810.5-810.19"
- wire $1\main_re[0:0]
- attribute \src "ls180.v:831.11-831.34"
- wire width 4 $1\main_rx_bitcount[3:0]
- attribute \src "ls180.v:832.5-832.24"
- wire $1\main_rx_busy[0:0]
- attribute \src "ls180.v:829.5-829.21"
- wire $1\main_rx_r[0:0]
- attribute \src "ls180.v:830.11-830.29"
- wire width 8 $1\main_rx_reg[7:0]
- attribute \src "ls180.v:1531.11-1531.50"
+ attribute \src "ls180.v:1547.11-1547.50"
wire width 2 $1\main_sdblock2mem_converter_demux[1:0]
- attribute \src "ls180.v:1527.5-1527.51"
+ attribute \src "ls180.v:1543.5-1543.51"
wire $1\main_sdblock2mem_converter_source_first[0:0]
- attribute \src "ls180.v:1528.5-1528.50"
+ attribute \src "ls180.v:1544.5-1544.50"
wire $1\main_sdblock2mem_converter_source_last[0:0]
- attribute \src "ls180.v:1529.12-1529.66"
+ attribute \src "ls180.v:1545.12-1545.66"
wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0]
- attribute \src "ls180.v:1530.11-1530.77"
+ attribute \src "ls180.v:1546.11-1546.77"
wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
- attribute \src "ls180.v:1533.5-1533.49"
+ attribute \src "ls180.v:1549.5-1549.49"
wire $1\main_sdblock2mem_converter_strobe_all[0:0]
- attribute \src "ls180.v:1506.11-1506.47"
+ attribute \src "ls180.v:1522.11-1522.47"
wire width 5 $1\main_sdblock2mem_fifo_consume[4:0]
- attribute \src "ls180.v:1503.11-1503.45"
+ attribute \src "ls180.v:1519.11-1519.45"
wire width 6 $1\main_sdblock2mem_fifo_level[5:0]
- attribute \src "ls180.v:1505.11-1505.47"
+ attribute \src "ls180.v:1521.11-1521.47"
wire width 5 $1\main_sdblock2mem_fifo_produce[4:0]
- attribute \src "ls180.v:1507.11-1507.50"
+ attribute \src "ls180.v:1523.11-1523.50"
wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0]
- attribute \src "ls180.v:1541.12-1541.62"
+ attribute \src "ls180.v:1557.12-1557.62"
wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0]
- attribute \src "ls180.v:1542.12-1542.60"
+ attribute \src "ls180.v:1558.12-1558.60"
wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0]
- attribute \src "ls180.v:1539.5-1539.45"
+ attribute \src "ls180.v:1555.5-1555.45"
wire $1\main_sdblock2mem_sink_sink_valid1[0:0]
- attribute \src "ls180.v:1549.5-1549.54"
+ attribute \src "ls180.v:1565.5-1565.54"
wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
- attribute \src "ls180.v:1548.12-1548.67"
+ attribute \src "ls180.v:1564.12-1564.67"
wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
- attribute \src "ls180.v:1553.5-1553.56"
+ attribute \src "ls180.v:1569.5-1569.56"
wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
- attribute \src "ls180.v:1552.5-1552.61"
+ attribute \src "ls180.v:1568.5-1568.61"
wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
- attribute \src "ls180.v:1551.5-1551.56"
+ attribute \src "ls180.v:1567.5-1567.56"
wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
- attribute \src "ls180.v:1550.12-1550.69"
+ attribute \src "ls180.v:1566.12-1566.69"
wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
- attribute \src "ls180.v:1557.5-1557.54"
+ attribute \src "ls180.v:1573.5-1573.54"
wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
- attribute \src "ls180.v:1556.5-1556.59"
+ attribute \src "ls180.v:1572.5-1572.59"
wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
- attribute \src "ls180.v:1559.12-1559.61"
+ attribute \src "ls180.v:1575.12-1575.61"
wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0]
- attribute \src "ls180.v:1813.12-1813.87"
+ attribute \src "ls180.v:1829.12-1829.87"
wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
- attribute \src "ls180.v:1814.5-1814.82"
+ attribute \src "ls180.v:1830.5-1830.82"
wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
- attribute \src "ls180.v:1544.5-1544.57"
+ attribute \src "ls180.v:1560.5-1560.57"
wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
- attribute \src "ls180.v:1554.5-1554.53"
+ attribute \src "ls180.v:1570.5-1570.53"
wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0]
- attribute \src "ls180.v:1323.5-1323.38"
+ attribute \src "ls180.v:1339.5-1339.38"
wire $1\main_sdcore_block_count_re[0:0]
- attribute \src "ls180.v:1322.12-1322.51"
+ attribute \src "ls180.v:1338.12-1338.51"
wire width 32 $1\main_sdcore_block_count_storage[31:0]
- attribute \src "ls180.v:1321.5-1321.39"
+ attribute \src "ls180.v:1337.5-1337.39"
wire $1\main_sdcore_block_length_re[0:0]
- attribute \src "ls180.v:1320.11-1320.51"
+ attribute \src "ls180.v:1336.11-1336.51"
wire width 10 $1\main_sdcore_block_length_storage[9:0]
- attribute \src "ls180.v:1307.5-1307.39"
+ attribute \src "ls180.v:1323.5-1323.39"
wire $1\main_sdcore_cmd_argument_re[0:0]
- attribute \src "ls180.v:1306.12-1306.52"
+ attribute \src "ls180.v:1322.12-1322.52"
wire width 32 $1\main_sdcore_cmd_argument_storage[31:0]
- attribute \src "ls180.v:1309.5-1309.38"
+ attribute \src "ls180.v:1325.5-1325.38"
wire $1\main_sdcore_cmd_command_re[0:0]
- attribute \src "ls180.v:1308.12-1308.51"
+ attribute \src "ls180.v:1324.12-1324.51"
wire width 32 $1\main_sdcore_cmd_command_storage[31:0]
- attribute \src "ls180.v:1462.11-1462.39"
+ attribute \src "ls180.v:1478.11-1478.39"
wire width 3 $1\main_sdcore_cmd_count[2:0]
- attribute \src "ls180.v:1797.11-1797.62"
+ attribute \src "ls180.v:1813.11-1813.62"
wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
- attribute \src "ls180.v:1798.5-1798.59"
+ attribute \src "ls180.v:1814.5-1814.59"
wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
- attribute \src "ls180.v:1463.5-1463.32"
+ attribute \src "ls180.v:1479.5-1479.32"
wire $1\main_sdcore_cmd_done[0:0]
- attribute \src "ls180.v:1793.5-1793.55"
+ attribute \src "ls180.v:1809.5-1809.55"
wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
- attribute \src "ls180.v:1794.5-1794.58"
+ attribute \src "ls180.v:1810.5-1810.58"
wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
- attribute \src "ls180.v:1464.5-1464.33"
+ attribute \src "ls180.v:1480.5-1480.33"
wire $1\main_sdcore_cmd_error[0:0]
- attribute \src "ls180.v:1801.5-1801.56"
+ attribute \src "ls180.v:1817.5-1817.56"
wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
- attribute \src "ls180.v:1802.5-1802.59"
+ attribute \src "ls180.v:1818.5-1818.59"
wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
- attribute \src "ls180.v:1314.13-1314.53"
+ attribute \src "ls180.v:1330.13-1330.53"
wire width 128 $1\main_sdcore_cmd_response_status[127:0]
- attribute \src "ls180.v:1809.13-1809.76"
+ attribute \src "ls180.v:1825.13-1825.76"
wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
- attribute \src "ls180.v:1810.5-1810.69"
+ attribute \src "ls180.v:1826.5-1826.69"
wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
- attribute \src "ls180.v:1465.5-1465.35"
+ attribute \src "ls180.v:1481.5-1481.35"
wire $1\main_sdcore_cmd_timeout[0:0]
- attribute \src "ls180.v:1803.5-1803.58"
+ attribute \src "ls180.v:1819.5-1819.58"
wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
- attribute \src "ls180.v:1804.5-1804.61"
+ attribute \src "ls180.v:1820.5-1820.61"
wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
- attribute \src "ls180.v:1423.11-1423.47"
+ attribute \src "ls180.v:1439.11-1439.47"
wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0]
- attribute \src "ls180.v:1429.5-1429.46"
+ attribute \src "ls180.v:1445.5-1445.46"
wire $1\main_sdcore_crc16_checker_crc0_clr[0:0]
- attribute \src "ls180.v:1428.12-1428.54"
+ attribute \src "ls180.v:1444.12-1444.54"
wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0]
- attribute \src "ls180.v:1424.12-1424.58"
+ attribute \src "ls180.v:1440.12-1440.58"
wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
- attribute \src "ls180.v:1436.5-1436.46"
+ attribute \src "ls180.v:1452.5-1452.46"
wire $1\main_sdcore_crc16_checker_crc1_clr[0:0]
- attribute \src "ls180.v:1435.12-1435.54"
+ attribute \src "ls180.v:1451.12-1451.54"
wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0]
- attribute \src "ls180.v:1431.12-1431.58"
+ attribute \src "ls180.v:1447.12-1447.58"
wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
- attribute \src "ls180.v:1443.5-1443.46"
+ attribute \src "ls180.v:1459.5-1459.46"
wire $1\main_sdcore_crc16_checker_crc2_clr[0:0]
- attribute \src "ls180.v:1442.12-1442.54"
+ attribute \src "ls180.v:1458.12-1458.54"
wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0]
- attribute \src "ls180.v:1438.12-1438.58"
+ attribute \src "ls180.v:1454.12-1454.58"
wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
- attribute \src "ls180.v:1450.5-1450.46"
+ attribute \src "ls180.v:1466.5-1466.46"
wire $1\main_sdcore_crc16_checker_crc3_clr[0:0]
- attribute \src "ls180.v:1449.12-1449.54"
+ attribute \src "ls180.v:1465.12-1465.54"
wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0]
- attribute \src "ls180.v:1445.12-1445.58"
+ attribute \src "ls180.v:1461.12-1461.58"
wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
- attribute \src "ls180.v:1452.12-1452.53"
+ attribute \src "ls180.v:1468.12-1468.53"
wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0]
- attribute \src "ls180.v:1453.12-1453.53"
+ attribute \src "ls180.v:1469.12-1469.53"
wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0]
- attribute \src "ls180.v:1454.12-1454.53"
+ attribute \src "ls180.v:1470.12-1470.53"
wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0]
- attribute \src "ls180.v:1455.12-1455.53"
+ attribute \src "ls180.v:1471.12-1471.53"
wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0]
- attribute \src "ls180.v:1457.12-1457.51"
+ attribute \src "ls180.v:1473.12-1473.51"
wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0]
- attribute \src "ls180.v:1458.12-1458.51"
+ attribute \src "ls180.v:1474.12-1474.51"
wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0]
- attribute \src "ls180.v:1459.12-1459.51"
+ attribute \src "ls180.v:1475.12-1475.51"
wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0]
- attribute \src "ls180.v:1460.12-1460.51"
+ attribute \src "ls180.v:1476.12-1476.51"
wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0]
- attribute \src "ls180.v:1414.5-1414.48"
+ attribute \src "ls180.v:1430.5-1430.48"
wire $1\main_sdcore_crc16_checker_sink_first[0:0]
- attribute \src "ls180.v:1415.5-1415.47"
+ attribute \src "ls180.v:1431.5-1431.47"
wire $1\main_sdcore_crc16_checker_sink_last[0:0]
- attribute \src "ls180.v:1416.11-1416.61"
+ attribute \src "ls180.v:1432.11-1432.61"
wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0]
- attribute \src "ls180.v:1413.5-1413.48"
+ attribute \src "ls180.v:1429.5-1429.48"
wire $1\main_sdcore_crc16_checker_sink_ready[0:0]
- attribute \src "ls180.v:1412.5-1412.48"
+ attribute \src "ls180.v:1428.5-1428.48"
wire $1\main_sdcore_crc16_checker_sink_valid[0:0]
- attribute \src "ls180.v:1417.5-1417.50"
+ attribute \src "ls180.v:1433.5-1433.50"
wire $1\main_sdcore_crc16_checker_source_valid[0:0]
- attribute \src "ls180.v:1422.11-1422.47"
+ attribute \src "ls180.v:1438.11-1438.47"
wire width 8 $1\main_sdcore_crc16_checker_val[7:0]
- attribute \src "ls180.v:1456.5-1456.43"
+ attribute \src "ls180.v:1472.5-1472.43"
wire $1\main_sdcore_crc16_checker_valid[0:0]
- attribute \src "ls180.v:1379.11-1379.48"
+ attribute \src "ls180.v:1395.11-1395.48"
wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0]
- attribute \src "ls180.v:1789.11-1789.87"
+ attribute \src "ls180.v:1805.11-1805.87"
wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
- attribute \src "ls180.v:1790.5-1790.84"
+ attribute \src "ls180.v:1806.5-1806.84"
wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
- attribute \src "ls180.v:1384.12-1384.55"
+ attribute \src "ls180.v:1400.12-1400.55"
wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0]
- attribute \src "ls180.v:1380.12-1380.59"
+ attribute \src "ls180.v:1396.12-1396.59"
wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
- attribute \src "ls180.v:1391.12-1391.55"
+ attribute \src "ls180.v:1407.12-1407.55"
wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
- attribute \src "ls180.v:1387.12-1387.59"
+ attribute \src "ls180.v:1403.12-1403.59"
wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
- attribute \src "ls180.v:1398.12-1398.55"
+ attribute \src "ls180.v:1414.12-1414.55"
wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0]
- attribute \src "ls180.v:1394.12-1394.59"
+ attribute \src "ls180.v:1410.12-1410.59"
wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
- attribute \src "ls180.v:1405.12-1405.55"
+ attribute \src "ls180.v:1421.12-1421.55"
wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0]
- attribute \src "ls180.v:1401.12-1401.59"
+ attribute \src "ls180.v:1417.12-1417.59"
wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
- attribute \src "ls180.v:1408.12-1408.54"
+ attribute \src "ls180.v:1424.12-1424.54"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0]
- attribute \src "ls180.v:1781.12-1781.93"
+ attribute \src "ls180.v:1797.12-1797.93"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
- attribute \src "ls180.v:1782.5-1782.88"
+ attribute \src "ls180.v:1798.5-1798.88"
wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
- attribute \src "ls180.v:1409.12-1409.54"
+ attribute \src "ls180.v:1425.12-1425.54"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0]
- attribute \src "ls180.v:1783.12-1783.93"
+ attribute \src "ls180.v:1799.12-1799.93"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
- attribute \src "ls180.v:1784.5-1784.88"
+ attribute \src "ls180.v:1800.5-1800.88"
wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
- attribute \src "ls180.v:1410.12-1410.54"
+ attribute \src "ls180.v:1426.12-1426.54"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0]
- attribute \src "ls180.v:1785.12-1785.93"
+ attribute \src "ls180.v:1801.12-1801.93"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
- attribute \src "ls180.v:1786.5-1786.88"
+ attribute \src "ls180.v:1802.5-1802.88"
wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
- attribute \src "ls180.v:1411.12-1411.54"
+ attribute \src "ls180.v:1427.12-1427.54"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0]
- attribute \src "ls180.v:1787.12-1787.93"
+ attribute \src "ls180.v:1803.12-1803.93"
wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
- attribute \src "ls180.v:1788.5-1788.88"
+ attribute \src "ls180.v:1804.5-1804.88"
wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
- attribute \src "ls180.v:1370.5-1370.49"
+ attribute \src "ls180.v:1386.5-1386.49"
wire $1\main_sdcore_crc16_inserter_sink_ready[0:0]
- attribute \src "ls180.v:1377.5-1377.50"
+ attribute \src "ls180.v:1393.5-1393.50"
wire $1\main_sdcore_crc16_inserter_source_last[0:0]
- attribute \src "ls180.v:1378.11-1378.64"
+ attribute \src "ls180.v:1394.11-1394.64"
wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0]
- attribute \src "ls180.v:1375.5-1375.51"
+ attribute \src "ls180.v:1391.5-1391.51"
wire $1\main_sdcore_crc16_inserter_source_ready[0:0]
- attribute \src "ls180.v:1374.5-1374.51"
+ attribute \src "ls180.v:1390.5-1390.51"
wire $1\main_sdcore_crc16_inserter_source_valid[0:0]
- attribute \src "ls180.v:1366.11-1366.47"
+ attribute \src "ls180.v:1382.11-1382.47"
wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0]
- attribute \src "ls180.v:1324.11-1324.51"
+ attribute \src "ls180.v:1340.11-1340.51"
wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0]
- attribute \src "ls180.v:1467.12-1467.42"
+ attribute \src "ls180.v:1483.12-1483.42"
wire width 32 $1\main_sdcore_data_count[31:0]
- attribute \src "ls180.v:1799.12-1799.65"
+ attribute \src "ls180.v:1815.12-1815.65"
wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
- attribute \src "ls180.v:1800.5-1800.60"
+ attribute \src "ls180.v:1816.5-1816.60"
wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
- attribute \src "ls180.v:1468.5-1468.33"
+ attribute \src "ls180.v:1484.5-1484.33"
wire $1\main_sdcore_data_done[0:0]
- attribute \src "ls180.v:1795.5-1795.56"
+ attribute \src "ls180.v:1811.5-1811.56"
wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
- attribute \src "ls180.v:1796.5-1796.59"
+ attribute \src "ls180.v:1812.5-1812.59"
wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
- attribute \src "ls180.v:1469.5-1469.34"
+ attribute \src "ls180.v:1485.5-1485.34"
wire $1\main_sdcore_data_error[0:0]
- attribute \src "ls180.v:1805.5-1805.57"
+ attribute \src "ls180.v:1821.5-1821.57"
wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
- attribute \src "ls180.v:1806.5-1806.60"
+ attribute \src "ls180.v:1822.5-1822.60"
wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
- attribute \src "ls180.v:1470.5-1470.36"
+ attribute \src "ls180.v:1486.5-1486.36"
wire $1\main_sdcore_data_timeout[0:0]
- attribute \src "ls180.v:1807.5-1807.59"
+ attribute \src "ls180.v:1823.5-1823.59"
wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
- attribute \src "ls180.v:1808.5-1808.62"
+ attribute \src "ls180.v:1824.5-1824.62"
wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
- attribute \src "ls180.v:1615.11-1615.48"
+ attribute \src "ls180.v:1631.11-1631.48"
wire width 2 $1\main_sdmem2block_converter_mux[1:0]
- attribute \src "ls180.v:1613.11-1613.64"
+ attribute \src "ls180.v:1629.11-1629.64"
wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0]
- attribute \src "ls180.v:1589.5-1589.40"
+ attribute \src "ls180.v:1605.5-1605.40"
wire $1\main_sdmem2block_dma_base_re[0:0]
- attribute \src "ls180.v:1588.12-1588.53"
+ attribute \src "ls180.v:1604.12-1604.53"
wire width 64 $1\main_sdmem2block_dma_base_storage[63:0]
- attribute \src "ls180.v:1587.12-1587.45"
+ attribute \src "ls180.v:1603.12-1603.45"
wire width 32 $1\main_sdmem2block_dma_data[31:0]
- attribute \src "ls180.v:1817.12-1817.75"
+ attribute \src "ls180.v:1833.12-1833.75"
wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
- attribute \src "ls180.v:1818.5-1818.70"
+ attribute \src "ls180.v:1834.5-1834.70"
wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
- attribute \src "ls180.v:1594.5-1594.44"
+ attribute \src "ls180.v:1610.5-1610.44"
wire $1\main_sdmem2block_dma_done_status[0:0]
- attribute \src "ls180.v:1593.5-1593.42"
+ attribute \src "ls180.v:1609.5-1609.42"
wire $1\main_sdmem2block_dma_enable_re[0:0]
- attribute \src "ls180.v:1592.5-1592.47"
+ attribute \src "ls180.v:1608.5-1608.47"
wire $1\main_sdmem2block_dma_enable_storage[0:0]
- attribute \src "ls180.v:1591.5-1591.42"
+ attribute \src "ls180.v:1607.5-1607.42"
wire $1\main_sdmem2block_dma_length_re[0:0]
- attribute \src "ls180.v:1590.12-1590.55"
+ attribute \src "ls180.v:1606.12-1606.55"
wire width 32 $1\main_sdmem2block_dma_length_storage[31:0]
- attribute \src "ls180.v:1597.5-1597.40"
+ attribute \src "ls180.v:1613.5-1613.40"
wire $1\main_sdmem2block_dma_loop_re[0:0]
- attribute \src "ls180.v:1596.5-1596.45"
+ attribute \src "ls180.v:1612.5-1612.45"
wire $1\main_sdmem2block_dma_loop_storage[0:0]
- attribute \src "ls180.v:1601.12-1601.47"
+ attribute \src "ls180.v:1617.12-1617.47"
wire width 32 $1\main_sdmem2block_dma_offset[31:0]
- attribute \src "ls180.v:1821.12-1821.87"
+ attribute \src "ls180.v:1837.12-1837.87"
wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
- attribute \src "ls180.v:1822.5-1822.82"
+ attribute \src "ls180.v:1838.5-1838.82"
wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
- attribute \src "ls180.v:1580.5-1580.42"
+ attribute \src "ls180.v:1596.5-1596.42"
wire $1\main_sdmem2block_dma_sink_last[0:0]
- attribute \src "ls180.v:1581.12-1581.61"
+ attribute \src "ls180.v:1597.12-1597.61"
wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0]
- attribute \src "ls180.v:1579.5-1579.43"
+ attribute \src "ls180.v:1595.5-1595.43"
wire $1\main_sdmem2block_dma_sink_ready[0:0]
- attribute \src "ls180.v:1578.5-1578.43"
+ attribute \src "ls180.v:1594.5-1594.43"
wire $1\main_sdmem2block_dma_sink_valid[0:0]
- attribute \src "ls180.v:1585.5-1585.44"
+ attribute \src "ls180.v:1601.5-1601.44"
wire $1\main_sdmem2block_dma_source_last[0:0]
- attribute \src "ls180.v:1586.12-1586.60"
+ attribute \src "ls180.v:1602.12-1602.60"
wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0]
- attribute \src "ls180.v:1582.5-1582.45"
+ attribute \src "ls180.v:1598.5-1598.45"
wire $1\main_sdmem2block_dma_source_valid[0:0]
- attribute \src "ls180.v:1642.11-1642.47"
+ attribute \src "ls180.v:1658.11-1658.47"
wire width 5 $1\main_sdmem2block_fifo_consume[4:0]
- attribute \src "ls180.v:1639.11-1639.45"
+ attribute \src "ls180.v:1655.11-1655.45"
wire width 6 $1\main_sdmem2block_fifo_level[5:0]
- attribute \src "ls180.v:1641.11-1641.47"
+ attribute \src "ls180.v:1657.11-1657.47"
wire width 5 $1\main_sdmem2block_fifo_produce[4:0]
- attribute \src "ls180.v:1643.11-1643.50"
+ attribute \src "ls180.v:1659.11-1659.50"
wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0]
- attribute \src "ls180.v:1023.5-1023.35"
+ attribute \src "ls180.v:1039.5-1039.35"
wire $1\main_sdphy_clocker_clk0[0:0]
- attribute \src "ls180.v:1026.5-1026.35"
+ attribute \src "ls180.v:1042.5-1042.35"
wire $1\main_sdphy_clocker_clk1[0:0]
- attribute \src "ls180.v:1027.5-1027.36"
+ attribute \src "ls180.v:1043.5-1043.36"
wire $1\main_sdphy_clocker_clk_d[0:0]
- attribute \src "ls180.v:1025.11-1025.41"
+ attribute \src "ls180.v:1041.11-1041.41"
wire width 9 $1\main_sdphy_clocker_clks[8:0]
- attribute \src "ls180.v:1021.5-1021.33"
+ attribute \src "ls180.v:1037.5-1037.33"
wire $1\main_sdphy_clocker_re[0:0]
- attribute \src "ls180.v:1020.11-1020.46"
+ attribute \src "ls180.v:1036.11-1036.46"
wire width 9 $1\main_sdphy_clocker_storage[8:0]
- attribute \src "ls180.v:1129.5-1129.49"
+ attribute \src "ls180.v:1145.5-1145.49"
wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
- attribute \src "ls180.v:1130.5-1130.48"
+ attribute \src "ls180.v:1146.5-1146.48"
wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
- attribute \src "ls180.v:1131.11-1131.62"
+ attribute \src "ls180.v:1147.11-1147.62"
wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
- attribute \src "ls180.v:1127.5-1127.49"
+ attribute \src "ls180.v:1143.5-1143.49"
wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
- attribute \src "ls180.v:1114.11-1114.54"
+ attribute \src "ls180.v:1130.11-1130.54"
wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0]
- attribute \src "ls180.v:1110.5-1110.55"
+ attribute \src "ls180.v:1126.5-1126.55"
wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
- attribute \src "ls180.v:1111.5-1111.54"
+ attribute \src "ls180.v:1127.5-1127.54"
wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
- attribute \src "ls180.v:1112.11-1112.68"
+ attribute \src "ls180.v:1128.11-1128.68"
wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
- attribute \src "ls180.v:1113.11-1113.81"
+ attribute \src "ls180.v:1129.11-1129.81"
wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
- attribute \src "ls180.v:1116.5-1116.53"
+ attribute \src "ls180.v:1132.5-1132.53"
wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
- attribute \src "ls180.v:1132.5-1132.38"
+ attribute \src "ls180.v:1148.5-1148.38"
wire $1\main_sdphy_cmdr_cmdr_reset[0:0]
- attribute \src "ls180.v:1761.5-1761.66"
+ attribute \src "ls180.v:1777.5-1777.66"
wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
- attribute \src "ls180.v:1762.5-1762.69"
+ attribute \src "ls180.v:1778.5-1778.69"
wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
- attribute \src "ls180.v:1102.5-1102.36"
+ attribute \src "ls180.v:1118.5-1118.36"
wire $1\main_sdphy_cmdr_cmdr_run[0:0]
- attribute \src "ls180.v:1097.5-1097.53"
+ attribute \src "ls180.v:1113.5-1113.53"
wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
- attribute \src "ls180.v:1084.11-1084.39"
+ attribute \src "ls180.v:1100.11-1100.39"
wire width 8 $1\main_sdphy_cmdr_count[7:0]
- attribute \src "ls180.v:1757.11-1757.67"
+ attribute \src "ls180.v:1773.11-1773.67"
wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
- attribute \src "ls180.v:1758.5-1758.64"
+ attribute \src "ls180.v:1774.5-1774.64"
wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
- attribute \src "ls180.v:1069.5-1069.48"
+ attribute \src "ls180.v:1085.5-1085.48"
wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1070.5-1070.50"
+ attribute \src "ls180.v:1086.5-1086.50"
wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:1071.5-1071.51"
+ attribute \src "ls180.v:1087.5-1087.51"
wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1076.5-1076.37"
+ attribute \src "ls180.v:1092.5-1092.37"
wire $1\main_sdphy_cmdr_sink_last[0:0]
- attribute \src "ls180.v:1077.11-1077.53"
+ attribute \src "ls180.v:1093.11-1093.53"
wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0]
- attribute \src "ls180.v:1075.5-1075.38"
+ attribute \src "ls180.v:1091.5-1091.38"
wire $1\main_sdphy_cmdr_sink_ready[0:0]
- attribute \src "ls180.v:1074.5-1074.38"
+ attribute \src "ls180.v:1090.5-1090.38"
wire $1\main_sdphy_cmdr_sink_valid[0:0]
- attribute \src "ls180.v:1080.5-1080.39"
+ attribute \src "ls180.v:1096.5-1096.39"
wire $1\main_sdphy_cmdr_source_last[0:0]
- attribute \src "ls180.v:1081.11-1081.53"
+ attribute \src "ls180.v:1097.11-1097.53"
wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0]
- attribute \src "ls180.v:1082.11-1082.55"
+ attribute \src "ls180.v:1098.11-1098.55"
wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0]
- attribute \src "ls180.v:1079.5-1079.40"
+ attribute \src "ls180.v:1095.5-1095.40"
wire $1\main_sdphy_cmdr_source_ready[0:0]
- attribute \src "ls180.v:1078.5-1078.40"
+ attribute \src "ls180.v:1094.5-1094.40"
wire $1\main_sdphy_cmdr_source_valid[0:0]
- attribute \src "ls180.v:1083.12-1083.48"
+ attribute \src "ls180.v:1099.12-1099.48"
wire width 32 $1\main_sdphy_cmdr_timeout[31:0]
- attribute \src "ls180.v:1759.12-1759.71"
+ attribute \src "ls180.v:1775.12-1775.71"
wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
- attribute \src "ls180.v:1760.5-1760.66"
+ attribute \src "ls180.v:1776.5-1776.66"
wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
- attribute \src "ls180.v:1056.11-1056.39"
+ attribute \src "ls180.v:1072.11-1072.39"
wire width 8 $1\main_sdphy_cmdw_count[7:0]
- attribute \src "ls180.v:1753.11-1753.66"
+ attribute \src "ls180.v:1769.11-1769.66"
wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
- attribute \src "ls180.v:1754.5-1754.63"
+ attribute \src "ls180.v:1770.5-1770.63"
wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
- attribute \src "ls180.v:1055.5-1055.32"
+ attribute \src "ls180.v:1071.5-1071.32"
wire $1\main_sdphy_cmdw_done[0:0]
- attribute \src "ls180.v:1046.5-1046.48"
+ attribute \src "ls180.v:1062.5-1062.48"
wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1047.5-1047.50"
+ attribute \src "ls180.v:1063.5-1063.50"
wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:1048.5-1048.51"
+ attribute \src "ls180.v:1064.5-1064.51"
wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1053.5-1053.37"
+ attribute \src "ls180.v:1069.5-1069.37"
wire $1\main_sdphy_cmdw_sink_last[0:0]
- attribute \src "ls180.v:1054.11-1054.51"
+ attribute \src "ls180.v:1070.11-1070.51"
wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0]
- attribute \src "ls180.v:1052.5-1052.38"
+ attribute \src "ls180.v:1068.5-1068.38"
wire $1\main_sdphy_cmdw_sink_ready[0:0]
- attribute \src "ls180.v:1051.5-1051.38"
+ attribute \src "ls180.v:1067.5-1067.38"
wire $1\main_sdphy_cmdw_sink_valid[0:0]
- attribute \src "ls180.v:1240.11-1240.41"
+ attribute \src "ls180.v:1256.11-1256.41"
wire width 10 $1\main_sdphy_datar_count[9:0]
- attribute \src "ls180.v:1773.11-1773.70"
+ attribute \src "ls180.v:1789.11-1789.70"
wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
- attribute \src "ls180.v:1774.5-1774.66"
+ attribute \src "ls180.v:1790.5-1790.66"
wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
- attribute \src "ls180.v:1285.5-1285.51"
+ attribute \src "ls180.v:1301.5-1301.51"
wire $1\main_sdphy_datar_datar_buf_source_first[0:0]
- attribute \src "ls180.v:1286.5-1286.50"
+ attribute \src "ls180.v:1302.5-1302.50"
wire $1\main_sdphy_datar_datar_buf_source_last[0:0]
- attribute \src "ls180.v:1287.11-1287.64"
+ attribute \src "ls180.v:1303.11-1303.64"
wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0]
- attribute \src "ls180.v:1283.5-1283.51"
+ attribute \src "ls180.v:1299.5-1299.51"
wire $1\main_sdphy_datar_datar_buf_source_valid[0:0]
- attribute \src "ls180.v:1270.5-1270.50"
+ attribute \src "ls180.v:1286.5-1286.50"
wire $1\main_sdphy_datar_datar_converter_demux[0:0]
- attribute \src "ls180.v:1266.5-1266.57"
+ attribute \src "ls180.v:1282.5-1282.57"
wire $1\main_sdphy_datar_datar_converter_source_first[0:0]
- attribute \src "ls180.v:1267.5-1267.56"
+ attribute \src "ls180.v:1283.5-1283.56"
wire $1\main_sdphy_datar_datar_converter_source_last[0:0]
- attribute \src "ls180.v:1268.11-1268.70"
+ attribute \src "ls180.v:1284.11-1284.70"
wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0]
- attribute \src "ls180.v:1269.11-1269.83"
+ attribute \src "ls180.v:1285.11-1285.83"
wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
- attribute \src "ls180.v:1272.5-1272.55"
+ attribute \src "ls180.v:1288.5-1288.55"
wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0]
- attribute \src "ls180.v:1288.5-1288.40"
+ attribute \src "ls180.v:1304.5-1304.40"
wire $1\main_sdphy_datar_datar_reset[0:0]
- attribute \src "ls180.v:1777.5-1777.69"
+ attribute \src "ls180.v:1793.5-1793.69"
wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
- attribute \src "ls180.v:1778.5-1778.72"
+ attribute \src "ls180.v:1794.5-1794.72"
wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
- attribute \src "ls180.v:1258.5-1258.38"
+ attribute \src "ls180.v:1274.5-1274.38"
wire $1\main_sdphy_datar_datar_run[0:0]
- attribute \src "ls180.v:1253.5-1253.55"
+ attribute \src "ls180.v:1269.5-1269.55"
wire $1\main_sdphy_datar_datar_source_source_ready0[0:0]
- attribute \src "ls180.v:1223.5-1223.49"
+ attribute \src "ls180.v:1239.5-1239.49"
wire $1\main_sdphy_datar_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1230.5-1230.38"
+ attribute \src "ls180.v:1246.5-1246.38"
wire $1\main_sdphy_datar_sink_last[0:0]
- attribute \src "ls180.v:1231.11-1231.61"
+ attribute \src "ls180.v:1247.11-1247.61"
wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0]
- attribute \src "ls180.v:1229.5-1229.39"
+ attribute \src "ls180.v:1245.5-1245.39"
wire $1\main_sdphy_datar_sink_ready[0:0]
- attribute \src "ls180.v:1228.5-1228.39"
+ attribute \src "ls180.v:1244.5-1244.39"
wire $1\main_sdphy_datar_sink_valid[0:0]
- attribute \src "ls180.v:1235.5-1235.40"
+ attribute \src "ls180.v:1251.5-1251.40"
wire $1\main_sdphy_datar_source_last[0:0]
- attribute \src "ls180.v:1236.11-1236.54"
+ attribute \src "ls180.v:1252.11-1252.54"
wire width 8 $1\main_sdphy_datar_source_payload_data[7:0]
- attribute \src "ls180.v:1237.11-1237.56"
+ attribute \src "ls180.v:1253.11-1253.56"
wire width 3 $1\main_sdphy_datar_source_payload_status[2:0]
- attribute \src "ls180.v:1233.5-1233.41"
+ attribute \src "ls180.v:1249.5-1249.41"
wire $1\main_sdphy_datar_source_ready[0:0]
- attribute \src "ls180.v:1232.5-1232.41"
+ attribute \src "ls180.v:1248.5-1248.41"
wire $1\main_sdphy_datar_source_valid[0:0]
- attribute \src "ls180.v:1238.5-1238.33"
+ attribute \src "ls180.v:1254.5-1254.33"
wire $1\main_sdphy_datar_stop[0:0]
- attribute \src "ls180.v:1239.12-1239.49"
+ attribute \src "ls180.v:1255.12-1255.49"
wire width 32 $1\main_sdphy_datar_timeout[31:0]
- attribute \src "ls180.v:1775.12-1775.73"
+ attribute \src "ls180.v:1791.12-1791.73"
wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
- attribute \src "ls180.v:1776.5-1776.68"
+ attribute \src "ls180.v:1792.5-1792.68"
wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
- attribute \src "ls180.v:1148.11-1148.40"
+ attribute \src "ls180.v:1164.11-1164.40"
wire width 8 $1\main_sdphy_dataw_count[7:0]
- attribute \src "ls180.v:1769.11-1769.61"
+ attribute \src "ls180.v:1785.11-1785.61"
wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
- attribute \src "ls180.v:1770.5-1770.58"
+ attribute \src "ls180.v:1786.5-1786.58"
wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
- attribute \src "ls180.v:1207.5-1207.50"
+ attribute \src "ls180.v:1223.5-1223.50"
wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0]
- attribute \src "ls180.v:1208.5-1208.49"
+ attribute \src "ls180.v:1224.5-1224.49"
wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0]
- attribute \src "ls180.v:1209.11-1209.63"
+ attribute \src "ls180.v:1225.11-1225.63"
wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
- attribute \src "ls180.v:1205.5-1205.50"
+ attribute \src "ls180.v:1221.5-1221.50"
wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0]
- attribute \src "ls180.v:1192.11-1192.55"
+ attribute \src "ls180.v:1208.11-1208.55"
wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0]
- attribute \src "ls180.v:1188.5-1188.56"
+ attribute \src "ls180.v:1204.5-1204.56"
wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0]
- attribute \src "ls180.v:1189.5-1189.55"
+ attribute \src "ls180.v:1205.5-1205.55"
wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0]
- attribute \src "ls180.v:1190.11-1190.69"
+ attribute \src "ls180.v:1206.11-1206.69"
wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
- attribute \src "ls180.v:1191.11-1191.82"
+ attribute \src "ls180.v:1207.11-1207.82"
wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
- attribute \src "ls180.v:1194.5-1194.54"
+ attribute \src "ls180.v:1210.5-1210.54"
wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
- attribute \src "ls180.v:1210.5-1210.39"
+ attribute \src "ls180.v:1226.5-1226.39"
wire $1\main_sdphy_dataw_crcr_reset[0:0]
- attribute \src "ls180.v:1765.5-1765.66"
+ attribute \src "ls180.v:1781.5-1781.66"
wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
- attribute \src "ls180.v:1766.5-1766.69"
+ attribute \src "ls180.v:1782.5-1782.69"
wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
- attribute \src "ls180.v:1180.5-1180.37"
+ attribute \src "ls180.v:1196.5-1196.37"
wire $1\main_sdphy_dataw_crcr_run[0:0]
- attribute \src "ls180.v:1175.5-1175.54"
+ attribute \src "ls180.v:1191.5-1191.54"
wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0]
- attribute \src "ls180.v:1162.5-1162.34"
+ attribute \src "ls180.v:1178.5-1178.34"
wire $1\main_sdphy_dataw_error[0:0]
- attribute \src "ls180.v:1137.5-1137.49"
+ attribute \src "ls180.v:1153.5-1153.49"
wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1140.11-1140.58"
+ attribute \src "ls180.v:1156.11-1156.58"
wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:1141.5-1141.53"
+ attribute \src "ls180.v:1157.5-1157.53"
wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:1144.5-1144.39"
+ attribute \src "ls180.v:1160.5-1160.39"
wire $1\main_sdphy_dataw_sink_first[0:0]
- attribute \src "ls180.v:1145.5-1145.38"
+ attribute \src "ls180.v:1161.5-1161.38"
wire $1\main_sdphy_dataw_sink_last[0:0]
- attribute \src "ls180.v:1146.11-1146.52"
+ attribute \src "ls180.v:1162.11-1162.52"
wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0]
- attribute \src "ls180.v:1143.5-1143.39"
+ attribute \src "ls180.v:1159.5-1159.39"
wire $1\main_sdphy_dataw_sink_ready[0:0]
- attribute \src "ls180.v:1142.5-1142.39"
+ attribute \src "ls180.v:1158.5-1158.39"
wire $1\main_sdphy_dataw_sink_valid[0:0]
- attribute \src "ls180.v:1160.5-1160.34"
+ attribute \src "ls180.v:1176.5-1176.34"
wire $1\main_sdphy_dataw_start[0:0]
- attribute \src "ls180.v:1147.5-1147.33"
+ attribute \src "ls180.v:1163.5-1163.33"
wire $1\main_sdphy_dataw_stop[0:0]
- attribute \src "ls180.v:1161.5-1161.34"
+ attribute \src "ls180.v:1177.5-1177.34"
wire $1\main_sdphy_dataw_valid[0:0]
- attribute \src "ls180.v:1041.11-1041.39"
+ attribute \src "ls180.v:1057.11-1057.39"
wire width 8 $1\main_sdphy_init_count[7:0]
- attribute \src "ls180.v:1749.11-1749.66"
+ attribute \src "ls180.v:1765.11-1765.66"
wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
- attribute \src "ls180.v:1750.5-1750.63"
+ attribute \src "ls180.v:1766.5-1766.63"
wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
- attribute \src "ls180.v:1036.5-1036.48"
+ attribute \src "ls180.v:1052.5-1052.48"
wire $1\main_sdphy_init_pads_out_payload_clk[0:0]
- attribute \src "ls180.v:1037.5-1037.50"
+ attribute \src "ls180.v:1053.5-1053.50"
wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0]
- attribute \src "ls180.v:1038.5-1038.51"
+ attribute \src "ls180.v:1054.5-1054.51"
wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
- attribute \src "ls180.v:1039.11-1039.57"
+ attribute \src "ls180.v:1055.11-1055.57"
wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0]
- attribute \src "ls180.v:1040.5-1040.52"
+ attribute \src "ls180.v:1056.5-1056.52"
wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0]
- attribute \src "ls180.v:1290.5-1290.35"
+ attribute \src "ls180.v:1306.5-1306.35"
wire $1\main_sdphy_sdpads_cmd_i[0:0]
- attribute \src "ls180.v:1293.11-1293.42"
+ attribute \src "ls180.v:1309.11-1309.42"
wire width 4 $1\main_sdphy_sdpads_data_i[3:0]
- attribute \src "ls180.v:299.5-299.33"
+ attribute \src "ls180.v:307.5-307.33"
wire $1\main_sdram_address_re[0:0]
- attribute \src "ls180.v:298.12-298.46"
+ attribute \src "ls180.v:306.12-306.46"
wire width 13 $1\main_sdram_address_storage[12:0]
- attribute \src "ls180.v:301.5-301.34"
+ attribute \src "ls180.v:309.5-309.34"
wire $1\main_sdram_baddress_re[0:0]
- attribute \src "ls180.v:300.11-300.45"
+ attribute \src "ls180.v:308.11-308.45"
wire width 2 $1\main_sdram_baddress_storage[1:0]
- attribute \src "ls180.v:397.5-397.50"
+ attribute \src "ls180.v:405.5-405.50"
wire $1\main_sdram_bankmachine0_auto_precharge[0:0]
- attribute \src "ls180.v:419.11-419.70"
+ attribute \src "ls180.v:427.11-427.70"
wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:416.11-416.68"
+ attribute \src "ls180.v:424.11-424.68"
wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:418.11-418.70"
+ attribute \src "ls180.v:426.11-426.70"
wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:420.11-420.73"
+ attribute \src "ls180.v:428.11-428.73"
wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:443.5-443.59"
+ attribute \src "ls180.v:451.5-451.59"
wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:444.5-444.58"
+ attribute \src "ls180.v:452.5-452.58"
wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:446.12-446.74"
+ attribute \src "ls180.v:454.12-454.74"
wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:445.5-445.64"
+ attribute \src "ls180.v:453.5-453.64"
wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:441.5-441.59"
+ attribute \src "ls180.v:449.5-449.59"
wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:389.12-389.57"
+ attribute \src "ls180.v:397.12-397.57"
wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
- attribute \src "ls180.v:391.5-391.51"
+ attribute \src "ls180.v:399.5-399.51"
wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0]
- attribute \src "ls180.v:394.5-394.54"
+ attribute \src "ls180.v:402.5-402.54"
wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:395.5-395.55"
+ attribute \src "ls180.v:403.5-403.55"
wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:396.5-396.56"
+ attribute \src "ls180.v:404.5-404.56"
wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:392.5-392.51"
+ attribute \src "ls180.v:400.5-400.51"
wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
- attribute \src "ls180.v:393.5-393.50"
+ attribute \src "ls180.v:401.5-401.50"
wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
- attribute \src "ls180.v:388.5-388.45"
+ attribute \src "ls180.v:396.5-396.45"
wire $1\main_sdram_bankmachine0_cmd_ready[0:0]
- attribute \src "ls180.v:387.5-387.45"
+ attribute \src "ls180.v:395.5-395.45"
wire $1\main_sdram_bankmachine0_cmd_valid[0:0]
- attribute \src "ls180.v:386.5-386.47"
+ attribute \src "ls180.v:394.5-394.47"
wire $1\main_sdram_bankmachine0_refresh_gnt[0:0]
- attribute \src "ls180.v:384.5-384.51"
+ attribute \src "ls180.v:392.5-392.51"
wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0]
- attribute \src "ls180.v:383.5-383.51"
+ attribute \src "ls180.v:391.5-391.51"
wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0]
- attribute \src "ls180.v:447.12-447.47"
+ attribute \src "ls180.v:455.12-455.47"
wire width 13 $1\main_sdram_bankmachine0_row[12:0]
- attribute \src "ls180.v:451.5-451.45"
+ attribute \src "ls180.v:459.5-459.45"
wire $1\main_sdram_bankmachine0_row_close[0:0]
- attribute \src "ls180.v:452.5-452.54"
+ attribute \src "ls180.v:460.5-460.54"
wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:450.5-450.44"
+ attribute \src "ls180.v:458.5-458.44"
wire $1\main_sdram_bankmachine0_row_open[0:0]
- attribute \src "ls180.v:448.5-448.46"
+ attribute \src "ls180.v:456.5-456.46"
wire $1\main_sdram_bankmachine0_row_opened[0:0]
- attribute \src "ls180.v:455.11-455.55"
+ attribute \src "ls180.v:463.11-463.55"
wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0]
- attribute \src "ls180.v:454.32-454.76"
+ attribute \src "ls180.v:462.32-462.76"
wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
- attribute \src "ls180.v:479.5-479.50"
+ attribute \src "ls180.v:487.5-487.50"
wire $1\main_sdram_bankmachine1_auto_precharge[0:0]
- attribute \src "ls180.v:501.11-501.70"
+ attribute \src "ls180.v:509.11-509.70"
wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:498.11-498.68"
+ attribute \src "ls180.v:506.11-506.68"
wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:500.11-500.70"
+ attribute \src "ls180.v:508.11-508.70"
wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:502.11-502.73"
+ attribute \src "ls180.v:510.11-510.73"
wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:525.5-525.59"
+ attribute \src "ls180.v:533.5-533.59"
wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:526.5-526.58"
+ attribute \src "ls180.v:534.5-534.58"
wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:528.12-528.74"
+ attribute \src "ls180.v:536.12-536.74"
wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:527.5-527.64"
+ attribute \src "ls180.v:535.5-535.64"
wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:523.5-523.59"
+ attribute \src "ls180.v:531.5-531.59"
wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:471.12-471.57"
+ attribute \src "ls180.v:479.12-479.57"
wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0]
- attribute \src "ls180.v:473.5-473.51"
+ attribute \src "ls180.v:481.5-481.51"
wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0]
- attribute \src "ls180.v:476.5-476.54"
+ attribute \src "ls180.v:484.5-484.54"
wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:477.5-477.55"
+ attribute \src "ls180.v:485.5-485.55"
wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:478.5-478.56"
+ attribute \src "ls180.v:486.5-486.56"
wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:474.5-474.51"
+ attribute \src "ls180.v:482.5-482.51"
wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0]
- attribute \src "ls180.v:475.5-475.50"
+ attribute \src "ls180.v:483.5-483.50"
wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0]
- attribute \src "ls180.v:470.5-470.45"
+ attribute \src "ls180.v:478.5-478.45"
wire $1\main_sdram_bankmachine1_cmd_ready[0:0]
- attribute \src "ls180.v:469.5-469.45"
+ attribute \src "ls180.v:477.5-477.45"
wire $1\main_sdram_bankmachine1_cmd_valid[0:0]
- attribute \src "ls180.v:468.5-468.47"
+ attribute \src "ls180.v:476.5-476.47"
wire $1\main_sdram_bankmachine1_refresh_gnt[0:0]
- attribute \src "ls180.v:466.5-466.51"
+ attribute \src "ls180.v:474.5-474.51"
wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0]
- attribute \src "ls180.v:465.5-465.51"
+ attribute \src "ls180.v:473.5-473.51"
wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0]
- attribute \src "ls180.v:529.12-529.47"
+ attribute \src "ls180.v:537.12-537.47"
wire width 13 $1\main_sdram_bankmachine1_row[12:0]
- attribute \src "ls180.v:533.5-533.45"
+ attribute \src "ls180.v:541.5-541.45"
wire $1\main_sdram_bankmachine1_row_close[0:0]
- attribute \src "ls180.v:534.5-534.54"
+ attribute \src "ls180.v:542.5-542.54"
wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:532.5-532.44"
+ attribute \src "ls180.v:540.5-540.44"
wire $1\main_sdram_bankmachine1_row_open[0:0]
- attribute \src "ls180.v:530.5-530.46"
+ attribute \src "ls180.v:538.5-538.46"
wire $1\main_sdram_bankmachine1_row_opened[0:0]
- attribute \src "ls180.v:537.11-537.55"
+ attribute \src "ls180.v:545.11-545.55"
wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0]
- attribute \src "ls180.v:536.32-536.76"
+ attribute \src "ls180.v:544.32-544.76"
wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0]
- attribute \src "ls180.v:561.5-561.50"
+ attribute \src "ls180.v:569.5-569.50"
wire $1\main_sdram_bankmachine2_auto_precharge[0:0]
- attribute \src "ls180.v:583.11-583.70"
+ attribute \src "ls180.v:591.11-591.70"
wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:580.11-580.68"
+ attribute \src "ls180.v:588.11-588.68"
wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:582.11-582.70"
+ attribute \src "ls180.v:590.11-590.70"
wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:584.11-584.73"
+ attribute \src "ls180.v:592.11-592.73"
wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:607.5-607.59"
+ attribute \src "ls180.v:615.5-615.59"
wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:608.5-608.58"
+ attribute \src "ls180.v:616.5-616.58"
wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:610.12-610.74"
+ attribute \src "ls180.v:618.12-618.74"
wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:609.5-609.64"
+ attribute \src "ls180.v:617.5-617.64"
wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:605.5-605.59"
+ attribute \src "ls180.v:613.5-613.59"
wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:553.12-553.57"
+ attribute \src "ls180.v:561.12-561.57"
wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0]
- attribute \src "ls180.v:555.5-555.51"
+ attribute \src "ls180.v:563.5-563.51"
wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0]
- attribute \src "ls180.v:558.5-558.54"
+ attribute \src "ls180.v:566.5-566.54"
wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:559.5-559.55"
+ attribute \src "ls180.v:567.5-567.55"
wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:560.5-560.56"
+ attribute \src "ls180.v:568.5-568.56"
wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:556.5-556.51"
+ attribute \src "ls180.v:564.5-564.51"
wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0]
- attribute \src "ls180.v:557.5-557.50"
+ attribute \src "ls180.v:565.5-565.50"
wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0]
- attribute \src "ls180.v:552.5-552.45"
+ attribute \src "ls180.v:560.5-560.45"
wire $1\main_sdram_bankmachine2_cmd_ready[0:0]
- attribute \src "ls180.v:551.5-551.45"
+ attribute \src "ls180.v:559.5-559.45"
wire $1\main_sdram_bankmachine2_cmd_valid[0:0]
- attribute \src "ls180.v:550.5-550.47"
+ attribute \src "ls180.v:558.5-558.47"
wire $1\main_sdram_bankmachine2_refresh_gnt[0:0]
- attribute \src "ls180.v:548.5-548.51"
+ attribute \src "ls180.v:556.5-556.51"
wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0]
- attribute \src "ls180.v:547.5-547.51"
+ attribute \src "ls180.v:555.5-555.51"
wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0]
- attribute \src "ls180.v:611.12-611.47"
+ attribute \src "ls180.v:619.12-619.47"
wire width 13 $1\main_sdram_bankmachine2_row[12:0]
- attribute \src "ls180.v:615.5-615.45"
+ attribute \src "ls180.v:623.5-623.45"
wire $1\main_sdram_bankmachine2_row_close[0:0]
- attribute \src "ls180.v:616.5-616.54"
+ attribute \src "ls180.v:624.5-624.54"
wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:614.5-614.44"
+ attribute \src "ls180.v:622.5-622.44"
wire $1\main_sdram_bankmachine2_row_open[0:0]
- attribute \src "ls180.v:612.5-612.46"
+ attribute \src "ls180.v:620.5-620.46"
wire $1\main_sdram_bankmachine2_row_opened[0:0]
- attribute \src "ls180.v:619.11-619.55"
+ attribute \src "ls180.v:627.11-627.55"
wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0]
- attribute \src "ls180.v:618.32-618.76"
+ attribute \src "ls180.v:626.32-626.76"
wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0]
- attribute \src "ls180.v:643.5-643.50"
+ attribute \src "ls180.v:651.5-651.50"
wire $1\main_sdram_bankmachine3_auto_precharge[0:0]
- attribute \src "ls180.v:665.11-665.70"
+ attribute \src "ls180.v:673.11-673.70"
wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:662.11-662.68"
+ attribute \src "ls180.v:670.11-670.68"
wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:664.11-664.70"
+ attribute \src "ls180.v:672.11-672.70"
wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:666.11-666.73"
+ attribute \src "ls180.v:674.11-674.73"
wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:689.5-689.59"
+ attribute \src "ls180.v:697.5-697.59"
wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:690.5-690.58"
+ attribute \src "ls180.v:698.5-698.58"
wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:692.12-692.74"
+ attribute \src "ls180.v:700.12-700.74"
wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:691.5-691.64"
+ attribute \src "ls180.v:699.5-699.64"
wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:687.5-687.59"
+ attribute \src "ls180.v:695.5-695.59"
wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:635.12-635.57"
+ attribute \src "ls180.v:643.12-643.57"
wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0]
- attribute \src "ls180.v:637.5-637.51"
+ attribute \src "ls180.v:645.5-645.51"
wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0]
- attribute \src "ls180.v:640.5-640.54"
+ attribute \src "ls180.v:648.5-648.54"
wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:641.5-641.55"
+ attribute \src "ls180.v:649.5-649.55"
wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:642.5-642.56"
+ attribute \src "ls180.v:650.5-650.56"
wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:638.5-638.51"
+ attribute \src "ls180.v:646.5-646.51"
wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0]
- attribute \src "ls180.v:639.5-639.50"
+ attribute \src "ls180.v:647.5-647.50"
wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0]
- attribute \src "ls180.v:634.5-634.45"
+ attribute \src "ls180.v:642.5-642.45"
wire $1\main_sdram_bankmachine3_cmd_ready[0:0]
- attribute \src "ls180.v:633.5-633.45"
+ attribute \src "ls180.v:641.5-641.45"
wire $1\main_sdram_bankmachine3_cmd_valid[0:0]
- attribute \src "ls180.v:632.5-632.47"
+ attribute \src "ls180.v:640.5-640.47"
wire $1\main_sdram_bankmachine3_refresh_gnt[0:0]
- attribute \src "ls180.v:630.5-630.51"
+ attribute \src "ls180.v:638.5-638.51"
wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0]
- attribute \src "ls180.v:629.5-629.51"
+ attribute \src "ls180.v:637.5-637.51"
wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0]
- attribute \src "ls180.v:693.12-693.47"
+ attribute \src "ls180.v:701.12-701.47"
wire width 13 $1\main_sdram_bankmachine3_row[12:0]
- attribute \src "ls180.v:697.5-697.45"
+ attribute \src "ls180.v:705.5-705.45"
wire $1\main_sdram_bankmachine3_row_close[0:0]
- attribute \src "ls180.v:698.5-698.54"
+ attribute \src "ls180.v:706.5-706.54"
wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:696.5-696.44"
+ attribute \src "ls180.v:704.5-704.44"
wire $1\main_sdram_bankmachine3_row_open[0:0]
- attribute \src "ls180.v:694.5-694.46"
+ attribute \src "ls180.v:702.5-702.46"
wire $1\main_sdram_bankmachine3_row_opened[0:0]
- attribute \src "ls180.v:701.11-701.55"
+ attribute \src "ls180.v:709.11-709.55"
wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0]
- attribute \src "ls180.v:700.32-700.76"
+ attribute \src "ls180.v:708.32-708.76"
wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
- attribute \src "ls180.v:716.5-716.49"
+ attribute \src "ls180.v:724.5-724.49"
wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0]
- attribute \src "ls180.v:717.5-717.49"
+ attribute \src "ls180.v:725.5-725.49"
wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0]
- attribute \src "ls180.v:718.5-718.48"
+ attribute \src "ls180.v:726.5-726.48"
wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0]
- attribute \src "ls180.v:724.11-724.45"
+ attribute \src "ls180.v:732.11-732.45"
wire width 2 $1\main_sdram_choose_cmd_grant[1:0]
- attribute \src "ls180.v:722.11-722.46"
+ attribute \src "ls180.v:730.11-730.46"
wire width 4 $1\main_sdram_choose_cmd_valids[3:0]
- attribute \src "ls180.v:734.5-734.49"
+ attribute \src "ls180.v:742.5-742.49"
wire $1\main_sdram_choose_req_cmd_payload_cas[0:0]
- attribute \src "ls180.v:735.5-735.49"
+ attribute \src "ls180.v:743.5-743.49"
wire $1\main_sdram_choose_req_cmd_payload_ras[0:0]
- attribute \src "ls180.v:736.5-736.48"
+ attribute \src "ls180.v:744.5-744.48"
wire $1\main_sdram_choose_req_cmd_payload_we[0:0]
- attribute \src "ls180.v:731.5-731.43"
+ attribute \src "ls180.v:739.5-739.43"
wire $1\main_sdram_choose_req_cmd_ready[0:0]
- attribute \src "ls180.v:742.11-742.45"
+ attribute \src "ls180.v:750.11-750.45"
wire width 2 $1\main_sdram_choose_req_grant[1:0]
- attribute \src "ls180.v:740.11-740.46"
+ attribute \src "ls180.v:748.11-748.46"
wire width 4 $1\main_sdram_choose_req_valids[3:0]
- attribute \src "ls180.v:729.5-729.48"
+ attribute \src "ls180.v:737.5-737.48"
wire $1\main_sdram_choose_req_want_activates[0:0]
- attribute \src "ls180.v:726.5-726.44"
+ attribute \src "ls180.v:734.5-734.44"
wire $1\main_sdram_choose_req_want_reads[0:0]
- attribute \src "ls180.v:727.5-727.45"
+ attribute \src "ls180.v:735.5-735.45"
wire $1\main_sdram_choose_req_want_writes[0:0]
- attribute \src "ls180.v:355.5-355.31"
+ attribute \src "ls180.v:363.5-363.31"
wire $1\main_sdram_cmd_last[0:0]
- attribute \src "ls180.v:356.12-356.44"
+ attribute \src "ls180.v:364.12-364.44"
wire width 13 $1\main_sdram_cmd_payload_a[12:0]
- attribute \src "ls180.v:357.11-357.43"
+ attribute \src "ls180.v:365.11-365.43"
wire width 2 $1\main_sdram_cmd_payload_ba[1:0]
- attribute \src "ls180.v:358.5-358.38"
+ attribute \src "ls180.v:366.5-366.38"
wire $1\main_sdram_cmd_payload_cas[0:0]
- attribute \src "ls180.v:359.5-359.38"
+ attribute \src "ls180.v:367.5-367.38"
wire $1\main_sdram_cmd_payload_ras[0:0]
- attribute \src "ls180.v:360.5-360.37"
+ attribute \src "ls180.v:368.5-368.37"
wire $1\main_sdram_cmd_payload_we[0:0]
- attribute \src "ls180.v:354.5-354.32"
+ attribute \src "ls180.v:362.5-362.32"
wire $1\main_sdram_cmd_ready[0:0]
- attribute \src "ls180.v:353.5-353.32"
+ attribute \src "ls180.v:361.5-361.32"
wire $1\main_sdram_cmd_valid[0:0]
- attribute \src "ls180.v:293.5-293.33"
+ attribute \src "ls180.v:301.5-301.33"
wire $1\main_sdram_command_re[0:0]
- attribute \src "ls180.v:292.11-292.44"
+ attribute \src "ls180.v:300.11-300.44"
wire width 6 $1\main_sdram_command_storage[5:0]
- attribute \src "ls180.v:337.12-337.45"
+ attribute \src "ls180.v:345.12-345.45"
wire width 13 $1\main_sdram_dfi_p0_address[12:0]
- attribute \src "ls180.v:338.11-338.40"
+ attribute \src "ls180.v:346.11-346.40"
wire width 2 $1\main_sdram_dfi_p0_bank[1:0]
- attribute \src "ls180.v:339.5-339.35"
+ attribute \src "ls180.v:347.5-347.35"
wire $1\main_sdram_dfi_p0_cas_n[0:0]
- attribute \src "ls180.v:340.5-340.34"
+ attribute \src "ls180.v:348.5-348.34"
wire $1\main_sdram_dfi_p0_cs_n[0:0]
- attribute \src "ls180.v:341.5-341.35"
+ attribute \src "ls180.v:349.5-349.35"
wire $1\main_sdram_dfi_p0_ras_n[0:0]
- attribute \src "ls180.v:350.5-350.39"
+ attribute \src "ls180.v:358.5-358.39"
wire $1\main_sdram_dfi_p0_rddata_en[0:0]
- attribute \src "ls180.v:342.5-342.34"
+ attribute \src "ls180.v:350.5-350.34"
wire $1\main_sdram_dfi_p0_we_n[0:0]
- attribute \src "ls180.v:348.5-348.39"
+ attribute \src "ls180.v:356.5-356.39"
wire $1\main_sdram_dfi_p0_wrdata_en[0:0]
- attribute \src "ls180.v:761.5-761.26"
+ attribute \src "ls180.v:769.5-769.26"
wire $1\main_sdram_en0[0:0]
- attribute \src "ls180.v:764.5-764.26"
+ attribute \src "ls180.v:772.5-772.26"
wire $1\main_sdram_en1[0:0]
- attribute \src "ls180.v:334.12-334.46"
+ attribute \src "ls180.v:342.12-342.46"
wire width 16 $1\main_sdram_interface_wdata[15:0]
- attribute \src "ls180.v:335.11-335.47"
+ attribute \src "ls180.v:343.11-343.47"
wire width 2 $1\main_sdram_interface_wdata_we[1:0]
- attribute \src "ls180.v:240.5-240.36"
+ attribute \src "ls180.v:248.5-248.36"
wire $1\main_sdram_inti_p0_cas_n[0:0]
- attribute \src "ls180.v:241.5-241.35"
+ attribute \src "ls180.v:249.5-249.35"
wire $1\main_sdram_inti_p0_cs_n[0:0]
- attribute \src "ls180.v:242.5-242.36"
+ attribute \src "ls180.v:250.5-250.36"
wire $1\main_sdram_inti_p0_ras_n[0:0]
- attribute \src "ls180.v:252.12-252.45"
+ attribute \src "ls180.v:260.12-260.45"
wire width 16 $1\main_sdram_inti_p0_rddata[15:0]
- attribute \src "ls180.v:253.5-253.43"
+ attribute \src "ls180.v:261.5-261.43"
wire $1\main_sdram_inti_p0_rddata_valid[0:0]
- attribute \src "ls180.v:243.5-243.35"
+ attribute \src "ls180.v:251.5-251.35"
wire $1\main_sdram_inti_p0_we_n[0:0]
- attribute \src "ls180.v:279.5-279.38"
+ attribute \src "ls180.v:287.5-287.38"
wire $1\main_sdram_master_p0_act_n[0:0]
- attribute \src "ls180.v:270.12-270.48"
+ attribute \src "ls180.v:278.12-278.48"
wire width 13 $1\main_sdram_master_p0_address[12:0]
- attribute \src "ls180.v:271.11-271.43"
+ attribute \src "ls180.v:279.11-279.43"
wire width 2 $1\main_sdram_master_p0_bank[1:0]
- attribute \src "ls180.v:272.5-272.38"
+ attribute \src "ls180.v:280.5-280.38"
wire $1\main_sdram_master_p0_cas_n[0:0]
- attribute \src "ls180.v:276.5-276.36"
+ attribute \src "ls180.v:284.5-284.36"
wire $1\main_sdram_master_p0_cke[0:0]
- attribute \src "ls180.v:273.5-273.37"
+ attribute \src "ls180.v:281.5-281.37"
wire $1\main_sdram_master_p0_cs_n[0:0]
- attribute \src "ls180.v:277.5-277.36"
+ attribute \src "ls180.v:285.5-285.36"
wire $1\main_sdram_master_p0_odt[0:0]
- attribute \src "ls180.v:274.5-274.38"
+ attribute \src "ls180.v:282.5-282.38"
wire $1\main_sdram_master_p0_ras_n[0:0]
- attribute \src "ls180.v:283.5-283.42"
+ attribute \src "ls180.v:291.5-291.42"
wire $1\main_sdram_master_p0_rddata_en[0:0]
- attribute \src "ls180.v:278.5-278.40"
+ attribute \src "ls180.v:286.5-286.40"
wire $1\main_sdram_master_p0_reset_n[0:0]
- attribute \src "ls180.v:275.5-275.37"
+ attribute \src "ls180.v:283.5-283.37"
wire $1\main_sdram_master_p0_we_n[0:0]
- attribute \src "ls180.v:280.12-280.47"
+ attribute \src "ls180.v:288.12-288.47"
wire width 16 $1\main_sdram_master_p0_wrdata[15:0]
- attribute \src "ls180.v:281.5-281.42"
+ attribute \src "ls180.v:289.5-289.42"
wire $1\main_sdram_master_p0_wrdata_en[0:0]
- attribute \src "ls180.v:282.11-282.50"
+ attribute \src "ls180.v:290.11-290.50"
wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0]
- attribute \src "ls180.v:371.5-371.38"
+ attribute \src "ls180.v:379.5-379.38"
wire $1\main_sdram_postponer_count[0:0]
- attribute \src "ls180.v:370.5-370.38"
+ attribute \src "ls180.v:378.5-378.38"
wire $1\main_sdram_postponer_req_o[0:0]
- attribute \src "ls180.v:291.5-291.25"
+ attribute \src "ls180.v:299.5-299.25"
wire $1\main_sdram_re[0:0]
- attribute \src "ls180.v:377.5-377.38"
+ attribute \src "ls180.v:385.5-385.38"
wire $1\main_sdram_sequencer_count[0:0]
- attribute \src "ls180.v:376.11-376.46"
+ attribute \src "ls180.v:384.11-384.46"
wire width 4 $1\main_sdram_sequencer_counter[3:0]
- attribute \src "ls180.v:375.5-375.38"
+ attribute \src "ls180.v:383.5-383.38"
wire $1\main_sdram_sequencer_done1[0:0]
- attribute \src "ls180.v:372.5-372.39"
+ attribute \src "ls180.v:380.5-380.39"
wire $1\main_sdram_sequencer_start0[0:0]
- attribute \src "ls180.v:268.12-268.46"
+ attribute \src "ls180.v:276.12-276.46"
wire width 16 $1\main_sdram_slave_p0_rddata[15:0]
- attribute \src "ls180.v:269.5-269.44"
+ attribute \src "ls180.v:277.5-277.44"
wire $1\main_sdram_slave_p0_rddata_valid[0:0]
- attribute \src "ls180.v:304.12-304.37"
+ attribute \src "ls180.v:312.12-312.37"
wire width 16 $1\main_sdram_status[15:0]
- attribute \src "ls180.v:746.11-746.40"
+ attribute \src "ls180.v:754.11-754.40"
wire width 2 $1\main_sdram_steerer_sel[1:0]
- attribute \src "ls180.v:290.11-290.36"
+ attribute \src "ls180.v:298.11-298.36"
wire width 4 $1\main_sdram_storage[3:0]
- attribute \src "ls180.v:755.5-755.36"
+ attribute \src "ls180.v:763.5-763.36"
wire $1\main_sdram_tccdcon_count[0:0]
- attribute \src "ls180.v:754.32-754.63"
+ attribute \src "ls180.v:762.32-762.63"
wire $1\main_sdram_tccdcon_ready[0:0]
- attribute \src "ls180.v:763.11-763.34"
+ attribute \src "ls180.v:771.11-771.34"
wire width 5 $1\main_sdram_time0[4:0]
- attribute \src "ls180.v:766.11-766.34"
+ attribute \src "ls180.v:774.11-774.34"
wire width 4 $1\main_sdram_time1[3:0]
- attribute \src "ls180.v:368.11-368.44"
+ attribute \src "ls180.v:376.11-376.44"
wire width 10 $1\main_sdram_timer_count1[9:0]
- attribute \src "ls180.v:758.11-758.42"
+ attribute \src "ls180.v:766.11-766.42"
wire width 3 $1\main_sdram_twtrcon_count[2:0]
- attribute \src "ls180.v:757.32-757.63"
+ attribute \src "ls180.v:765.32-765.63"
wire $1\main_sdram_twtrcon_ready[0:0]
- attribute \src "ls180.v:303.5-303.32"
+ attribute \src "ls180.v:311.5-311.32"
wire $1\main_sdram_wrdata_re[0:0]
- attribute \src "ls180.v:302.12-302.45"
+ attribute \src "ls180.v:310.12-310.45"
wire width 16 $1\main_sdram_wrdata_storage[15:0]
- attribute \src "ls180.v:812.5-812.27"
- wire $1\main_sink_ready[0:0]
- attribute \src "ls180.v:825.11-825.42"
- wire width 8 $1\main_source_payload_data[7:0]
- attribute \src "ls180.v:821.5-821.29"
- wire $1\main_source_valid[0:0]
- attribute \src "ls180.v:990.12-990.48"
+ attribute \src "ls180.v:998.12-998.48"
wire width 16 $1\main_spi_master_clk_divider1[15:0]
- attribute \src "ls180.v:985.5-985.38"
+ attribute \src "ls180.v:993.5-993.38"
wire $1\main_spi_master_clk_enable[0:0]
- attribute \src "ls180.v:972.5-972.38"
+ attribute \src "ls180.v:980.5-980.38"
wire $1\main_spi_master_control_re[0:0]
- attribute \src "ls180.v:971.12-971.51"
+ attribute \src "ls180.v:979.12-979.51"
wire width 16 $1\main_spi_master_control_storage[15:0]
- attribute \src "ls180.v:987.11-987.39"
+ attribute \src "ls180.v:995.11-995.39"
wire width 3 $1\main_spi_master_count[2:0]
- attribute \src "ls180.v:1745.11-1745.61"
+ attribute \src "ls180.v:1761.11-1761.61"
wire width 3 $1\main_spi_master_count_spimaster0_next_value[2:0]
- attribute \src "ls180.v:1746.5-1746.58"
+ attribute \src "ls180.v:1762.5-1762.58"
wire $1\main_spi_master_count_spimaster0_next_value_ce[0:0]
- attribute \src "ls180.v:986.5-986.37"
+ attribute \src "ls180.v:994.5-994.37"
wire $1\main_spi_master_cs_enable[0:0]
- attribute \src "ls180.v:982.5-982.33"
+ attribute \src "ls180.v:990.5-990.33"
wire $1\main_spi_master_cs_re[0:0]
- attribute \src "ls180.v:981.5-981.38"
+ attribute \src "ls180.v:989.5-989.38"
wire $1\main_spi_master_cs_storage[0:0]
- attribute \src "ls180.v:962.5-962.33"
+ attribute \src "ls180.v:970.5-970.33"
wire $1\main_spi_master_done0[0:0]
- attribute \src "ls180.v:963.5-963.31"
+ attribute \src "ls180.v:971.5-971.31"
wire $1\main_spi_master_irq[0:0]
- attribute \src "ls180.v:984.5-984.39"
+ attribute \src "ls180.v:992.5-992.39"
wire $1\main_spi_master_loopback_re[0:0]
- attribute \src "ls180.v:983.5-983.44"
+ attribute \src "ls180.v:991.5-991.44"
wire $1\main_spi_master_loopback_storage[0:0]
- attribute \src "ls180.v:965.11-965.38"
+ attribute \src "ls180.v:973.11-973.38"
wire width 8 $1\main_spi_master_miso[7:0]
- attribute \src "ls180.v:995.11-995.43"
+ attribute \src "ls180.v:1003.11-1003.43"
wire width 8 $1\main_spi_master_miso_data[7:0]
- attribute \src "ls180.v:989.5-989.38"
+ attribute \src "ls180.v:997.5-997.38"
wire $1\main_spi_master_miso_latch[0:0]
- attribute \src "ls180.v:993.11-993.43"
+ attribute \src "ls180.v:1001.11-1001.43"
wire width 8 $1\main_spi_master_mosi_data[7:0]
- attribute \src "ls180.v:988.5-988.38"
+ attribute \src "ls180.v:996.5-996.38"
wire $1\main_spi_master_mosi_latch[0:0]
- attribute \src "ls180.v:977.5-977.35"
+ attribute \src "ls180.v:985.5-985.35"
wire $1\main_spi_master_mosi_re[0:0]
- attribute \src "ls180.v:994.11-994.42"
+ attribute \src "ls180.v:1002.11-1002.42"
wire width 3 $1\main_spi_master_mosi_sel[2:0]
- attribute \src "ls180.v:976.11-976.46"
+ attribute \src "ls180.v:984.11-984.46"
wire width 8 $1\main_spi_master_mosi_storage[7:0]
- attribute \src "ls180.v:969.5-969.34"
+ attribute \src "ls180.v:977.5-977.34"
wire $1\main_spi_master_start1[0:0]
- attribute \src "ls180.v:809.12-809.38"
- wire width 32 $1\main_storage[31:0]
- attribute \src "ls180.v:819.11-819.34"
- wire width 4 $1\main_tx_bitcount[3:0]
- attribute \src "ls180.v:820.5-820.24"
- wire $1\main_tx_busy[0:0]
- attribute \src "ls180.v:818.11-818.29"
- wire width 8 $1\main_tx_reg[7:0]
- attribute \src "ls180.v:826.5-826.30"
- wire $1\main_uart_clk_rxen[0:0]
- attribute \src "ls180.v:816.5-816.30"
- wire $1\main_uart_clk_txen[0:0]
- attribute \src "ls180.v:859.11-859.50"
+ attribute \src "ls180.v:867.11-867.50"
wire width 2 $1\main_uart_eventmanager_pending_w[1:0]
- attribute \src "ls180.v:861.5-861.37"
+ attribute \src "ls180.v:869.5-869.37"
wire $1\main_uart_eventmanager_re[0:0]
- attribute \src "ls180.v:855.11-855.49"
+ attribute \src "ls180.v:863.11-863.49"
wire width 2 $1\main_uart_eventmanager_status_w[1:0]
- attribute \src "ls180.v:860.11-860.48"
+ attribute \src "ls180.v:868.11-868.48"
wire width 2 $1\main_uart_eventmanager_storage[1:0]
- attribute \src "ls180.v:850.5-850.30"
+ attribute \src "ls180.v:835.12-835.54"
+ wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0]
+ attribute \src "ls180.v:825.12-825.54"
+ wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0]
+ attribute \src "ls180.v:818.5-818.28"
+ wire $1\main_uart_phy_re[0:0]
+ attribute \src "ls180.v:839.11-839.43"
+ wire width 4 $1\main_uart_phy_rx_bitcount[3:0]
+ attribute \src "ls180.v:840.5-840.33"
+ wire $1\main_uart_phy_rx_busy[0:0]
+ attribute \src "ls180.v:837.5-837.30"
+ wire $1\main_uart_phy_rx_r[0:0]
+ attribute \src "ls180.v:838.11-838.38"
+ wire width 8 $1\main_uart_phy_rx_reg[7:0]
+ attribute \src "ls180.v:820.5-820.36"
+ wire $1\main_uart_phy_sink_ready[0:0]
+ attribute \src "ls180.v:833.11-833.51"
+ wire width 8 $1\main_uart_phy_source_payload_data[7:0]
+ attribute \src "ls180.v:829.5-829.38"
+ wire $1\main_uart_phy_source_valid[0:0]
+ attribute \src "ls180.v:817.12-817.47"
+ wire width 32 $1\main_uart_phy_storage[31:0]
+ attribute \src "ls180.v:827.11-827.43"
+ wire width 4 $1\main_uart_phy_tx_bitcount[3:0]
+ attribute \src "ls180.v:828.5-828.33"
+ wire $1\main_uart_phy_tx_busy[0:0]
+ attribute \src "ls180.v:826.11-826.38"
+ wire width 8 $1\main_uart_phy_tx_reg[7:0]
+ attribute \src "ls180.v:834.5-834.39"
+ wire $1\main_uart_phy_uart_clk_rxen[0:0]
+ attribute \src "ls180.v:824.5-824.39"
+ wire $1\main_uart_phy_uart_clk_txen[0:0]
+ attribute \src "ls180.v:858.5-858.30"
wire $1\main_uart_rx_clear[0:0]
- attribute \src "ls180.v:934.11-934.43"
+ attribute \src "ls180.v:942.11-942.43"
wire width 4 $1\main_uart_rx_fifo_consume[3:0]
- attribute \src "ls180.v:931.11-931.42"
+ attribute \src "ls180.v:939.11-939.42"
wire width 5 $1\main_uart_rx_fifo_level0[4:0]
- attribute \src "ls180.v:933.11-933.43"
+ attribute \src "ls180.v:941.11-941.43"
wire width 4 $1\main_uart_rx_fifo_produce[3:0]
- attribute \src "ls180.v:924.5-924.38"
+ attribute \src "ls180.v:932.5-932.38"
wire $1\main_uart_rx_fifo_readable[0:0]
- attribute \src "ls180.v:935.11-935.46"
+ attribute \src "ls180.v:943.11-943.46"
wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0]
- attribute \src "ls180.v:851.5-851.36"
+ attribute \src "ls180.v:859.5-859.36"
wire $1\main_uart_rx_old_trigger[0:0]
- attribute \src "ls180.v:848.5-848.32"
+ attribute \src "ls180.v:856.5-856.32"
wire $1\main_uart_rx_pending[0:0]
- attribute \src "ls180.v:845.5-845.30"
+ attribute \src "ls180.v:853.5-853.30"
wire $1\main_uart_tx_clear[0:0]
- attribute \src "ls180.v:897.11-897.43"
+ attribute \src "ls180.v:905.11-905.43"
wire width 4 $1\main_uart_tx_fifo_consume[3:0]
- attribute \src "ls180.v:894.11-894.42"
+ attribute \src "ls180.v:902.11-902.42"
wire width 5 $1\main_uart_tx_fifo_level0[4:0]
- attribute \src "ls180.v:896.11-896.43"
+ attribute \src "ls180.v:904.11-904.43"
wire width 4 $1\main_uart_tx_fifo_produce[3:0]
- attribute \src "ls180.v:887.5-887.38"
+ attribute \src "ls180.v:895.5-895.38"
wire $1\main_uart_tx_fifo_readable[0:0]
- attribute \src "ls180.v:898.11-898.46"
+ attribute \src "ls180.v:906.11-906.46"
wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0]
- attribute \src "ls180.v:846.5-846.36"
+ attribute \src "ls180.v:854.5-854.36"
wire $1\main_uart_tx_old_trigger[0:0]
- attribute \src "ls180.v:843.5-843.32"
+ attribute \src "ls180.v:851.5-851.32"
wire $1\main_uart_tx_pending[0:0]
- attribute \src "ls180.v:787.5-787.29"
+ attribute \src "ls180.v:795.5-795.29"
wire $1\main_wb_sdram_ack[0:0]
- attribute \src "ls180.v:805.5-805.31"
+ attribute \src "ls180.v:813.5-813.31"
wire $1\main_wdata_consumed[0:0]
- attribute \src "ls180.v:2768.68-2768.110"
- wire $add$ls180.v:2768$22_Y
- attribute \src "ls180.v:2828.68-2828.110"
- wire $add$ls180.v:2828$33_Y
- attribute \src "ls180.v:2888.68-2888.110"
- wire $add$ls180.v:2888$44_Y
- attribute \src "ls180.v:4021.54-4021.83"
- wire $add$ls180.v:4021$537_Y
- attribute \src "ls180.v:4121.36-4121.89"
- wire width 5 $add$ls180.v:4121$583_Y
- attribute \src "ls180.v:4151.36-4151.89"
- wire width 5 $add$ls180.v:4151$594_Y
- attribute \src "ls180.v:4206.53-4206.81"
- wire width 3 $add$ls180.v:4206$607_Y
- attribute \src "ls180.v:4306.58-4306.86"
- wire width 8 $add$ls180.v:4306$635_Y
- attribute \src "ls180.v:4363.58-4363.86"
- wire width 8 $add$ls180.v:4363$638_Y
- attribute \src "ls180.v:4380.58-4380.86"
- wire width 8 $add$ls180.v:4380$640_Y
- attribute \src "ls180.v:4473.59-4473.87"
- wire width 8 $add$ls180.v:4473$657_Y
- attribute \src "ls180.v:4498.59-4498.87"
- wire width 8 $add$ls180.v:4498$660_Y
- attribute \src "ls180.v:4620.53-4620.82"
- wire width 8 $add$ls180.v:4620$677_Y
- attribute \src "ls180.v:4731.65-4731.114"
- wire width 10 $add$ls180.v:4731$691_Y
- attribute \src "ls180.v:4736.62-4736.91"
- wire width 10 $add$ls180.v:4736$694_Y
- attribute \src "ls180.v:4762.61-4762.90"
- wire width 10 $add$ls180.v:4762$697_Y
- attribute \src "ls180.v:4966.80-4966.117"
- wire width 3 $add$ls180.v:4966$882_Y
- attribute \src "ls180.v:5160.54-5160.82"
- wire width 3 $add$ls180.v:5160$957_Y
- attribute \src "ls180.v:5212.55-5212.84"
- wire width 32 $add$ls180.v:5212$967_Y
- attribute \src "ls180.v:5238.57-5238.86"
- wire width 32 $add$ls180.v:5238$975_Y
- attribute \src "ls180.v:5359.51-5359.134"
- wire width 32 $add$ls180.v:5359$991_Y
- attribute \src "ls180.v:5362.77-5362.125"
- wire width 32 $add$ls180.v:5362$993_Y
- attribute \src "ls180.v:5455.50-5455.105"
- wire width 32 $add$ls180.v:5455$1002_Y
- attribute \src "ls180.v:5457.77-5457.111"
- wire width 32 $add$ls180.v:5457$1003_Y
- attribute \src "ls180.v:5569.49-5569.73"
- wire width 3 $add$ls180.v:5569$1022_Y
- attribute \src "ls180.v:7437.36-7437.70"
- wire width 32 $add$ls180.v:7437$2405_Y
- attribute \src "ls180.v:7522.37-7522.72"
- wire width 4 $add$ls180.v:7522$2426_Y
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+ attribute \src "ls180.v:4876.205-4876.278"
+ wire $xor$ls180.v:4876$790_Y
+ attribute \src "ls180.v:4876.164-4876.279"
+ wire $xor$ls180.v:4876$791_Y
+ attribute \src "ls180.v:4877.360-4877.432"
+ wire $xor$ls180.v:4877$792_Y
+ attribute \src "ls180.v:4877.205-4877.277"
+ wire $xor$ls180.v:4877$793_Y
+ attribute \src "ls180.v:4877.164-4877.278"
+ wire $xor$ls180.v:4877$794_Y
+ attribute \src "ls180.v:4878.360-4878.432"
+ wire $xor$ls180.v:4878$795_Y
+ attribute \src "ls180.v:4878.205-4878.277"
+ wire $xor$ls180.v:4878$796_Y
+ attribute \src "ls180.v:4878.164-4878.278"
+ wire $xor$ls180.v:4878$797_Y
+ attribute \src "ls180.v:4879.360-4879.432"
+ wire $xor$ls180.v:4879$798_Y
+ attribute \src "ls180.v:4879.205-4879.277"
+ wire $xor$ls180.v:4879$799_Y
+ attribute \src "ls180.v:4879.164-4879.278"
+ wire $xor$ls180.v:4879$800_Y
+ attribute \src "ls180.v:4880.360-4880.432"
+ wire $xor$ls180.v:4880$801_Y
+ attribute \src "ls180.v:4880.205-4880.277"
+ wire $xor$ls180.v:4880$802_Y
+ attribute \src "ls180.v:4880.164-4880.278"
+ wire $xor$ls180.v:4880$803_Y
+ attribute \src "ls180.v:4881.360-4881.432"
+ wire $xor$ls180.v:4881$804_Y
+ attribute \src "ls180.v:4881.205-4881.277"
+ wire $xor$ls180.v:4881$805_Y
+ attribute \src "ls180.v:4881.164-4881.278"
+ wire $xor$ls180.v:4881$806_Y
+ attribute \src "ls180.v:4882.360-4882.432"
+ wire $xor$ls180.v:4882$807_Y
+ attribute \src "ls180.v:4882.205-4882.277"
+ wire $xor$ls180.v:4882$808_Y
+ attribute \src "ls180.v:4882.164-4882.278"
+ wire $xor$ls180.v:4882$809_Y
+ attribute \src "ls180.v:4883.360-4883.432"
+ wire $xor$ls180.v:4883$810_Y
+ attribute \src "ls180.v:4883.205-4883.277"
+ wire $xor$ls180.v:4883$811_Y
+ attribute \src "ls180.v:4883.164-4883.278"
+ wire $xor$ls180.v:4883$812_Y
+ attribute \src "ls180.v:4884.360-4884.432"
+ wire $xor$ls180.v:4884$813_Y
+ attribute \src "ls180.v:4884.205-4884.277"
+ wire $xor$ls180.v:4884$814_Y
+ attribute \src "ls180.v:4884.164-4884.278"
+ wire $xor$ls180.v:4884$815_Y
+ attribute \src "ls180.v:4885.360-4885.432"
+ wire $xor$ls180.v:4885$816_Y
+ attribute \src "ls180.v:4885.205-4885.277"
+ wire $xor$ls180.v:4885$817_Y
+ attribute \src "ls180.v:4885.164-4885.278"
+ wire $xor$ls180.v:4885$818_Y
+ attribute \src "ls180.v:4886.360-4886.432"
+ wire $xor$ls180.v:4886$819_Y
+ attribute \src "ls180.v:4886.205-4886.277"
+ wire $xor$ls180.v:4886$820_Y
+ attribute \src "ls180.v:4886.164-4886.278"
+ wire $xor$ls180.v:4886$821_Y
+ attribute \src "ls180.v:4907.899-4907.983"
+ wire $xor$ls180.v:4907$835_Y
+ attribute \src "ls180.v:4907.634-4907.718"
+ wire $xor$ls180.v:4907$836_Y
+ attribute \src "ls180.v:4907.588-4907.719"
+ wire $xor$ls180.v:4907$837_Y
+ attribute \src "ls180.v:4907.234-4907.318"
+ wire $xor$ls180.v:4907$838_Y
+ attribute \src "ls180.v:4907.187-4907.319"
+ wire $xor$ls180.v:4907$839_Y
+ attribute \src "ls180.v:4908.899-4908.983"
+ wire $xor$ls180.v:4908$840_Y
+ attribute \src "ls180.v:4908.634-4908.718"
+ wire $xor$ls180.v:4908$841_Y
+ attribute \src "ls180.v:4908.588-4908.719"
+ wire $xor$ls180.v:4908$842_Y
+ attribute \src "ls180.v:4908.234-4908.318"
+ wire $xor$ls180.v:4908$843_Y
+ attribute \src "ls180.v:4908.187-4908.319"
+ wire $xor$ls180.v:4908$844_Y
+ attribute \src "ls180.v:4917.899-4917.983"
+ wire $xor$ls180.v:4917$846_Y
+ attribute \src "ls180.v:4917.634-4917.718"
+ wire $xor$ls180.v:4917$847_Y
+ attribute \src "ls180.v:4917.588-4917.719"
+ wire $xor$ls180.v:4917$848_Y
+ attribute \src "ls180.v:4917.234-4917.318"
+ wire $xor$ls180.v:4917$849_Y
+ attribute \src "ls180.v:4917.187-4917.319"
+ wire $xor$ls180.v:4917$850_Y
+ attribute \src "ls180.v:4918.899-4918.983"
+ wire $xor$ls180.v:4918$851_Y
+ attribute \src "ls180.v:4918.634-4918.718"
+ wire $xor$ls180.v:4918$852_Y
+ attribute \src "ls180.v:4918.588-4918.719"
+ wire $xor$ls180.v:4918$853_Y
+ attribute \src "ls180.v:4918.234-4918.318"
+ wire $xor$ls180.v:4918$854_Y
+ attribute \src "ls180.v:4918.187-4918.319"
+ wire $xor$ls180.v:4918$855_Y
+ attribute \src "ls180.v:4927.899-4927.983"
+ wire $xor$ls180.v:4927$857_Y
+ attribute \src "ls180.v:4927.634-4927.718"
+ wire $xor$ls180.v:4927$858_Y
+ attribute \src "ls180.v:4927.588-4927.719"
+ wire $xor$ls180.v:4927$859_Y
+ attribute \src "ls180.v:4927.234-4927.318"
+ wire $xor$ls180.v:4927$860_Y
+ attribute \src "ls180.v:4927.187-4927.319"
+ wire $xor$ls180.v:4927$861_Y
+ attribute \src "ls180.v:4928.899-4928.983"
+ wire $xor$ls180.v:4928$862_Y
+ attribute \src "ls180.v:4928.634-4928.718"
+ wire $xor$ls180.v:4928$863_Y
+ attribute \src "ls180.v:4928.588-4928.719"
+ wire $xor$ls180.v:4928$864_Y
+ attribute \src "ls180.v:4928.234-4928.318"
+ wire $xor$ls180.v:4928$865_Y
+ attribute \src "ls180.v:4928.187-4928.319"
+ wire $xor$ls180.v:4928$866_Y
+ attribute \src "ls180.v:4937.899-4937.983"
+ wire $xor$ls180.v:4937$868_Y
+ attribute \src "ls180.v:4937.634-4937.718"
+ wire $xor$ls180.v:4937$869_Y
+ attribute \src "ls180.v:4937.588-4937.719"
+ wire $xor$ls180.v:4937$870_Y
+ attribute \src "ls180.v:4937.234-4937.318"
+ wire $xor$ls180.v:4937$871_Y
+ attribute \src "ls180.v:4937.187-4937.319"
+ wire $xor$ls180.v:4937$872_Y
+ attribute \src "ls180.v:4938.899-4938.983"
+ wire $xor$ls180.v:4938$873_Y
+ attribute \src "ls180.v:4938.634-4938.718"
+ wire $xor$ls180.v:4938$874_Y
+ attribute \src "ls180.v:4938.588-4938.719"
+ wire $xor$ls180.v:4938$875_Y
+ attribute \src "ls180.v:4938.234-4938.318"
+ wire $xor$ls180.v:4938$876_Y
+ attribute \src "ls180.v:4938.187-4938.319"
+ wire $xor$ls180.v:4938$877_Y
+ attribute \src "ls180.v:5089.879-5089.961"
+ wire $xor$ls180.v:5089$910_Y
+ attribute \src "ls180.v:5089.620-5089.702"
+ wire $xor$ls180.v:5089$911_Y
+ attribute \src "ls180.v:5089.575-5089.703"
+ wire $xor$ls180.v:5089$912_Y
+ attribute \src "ls180.v:5089.229-5089.311"
+ wire $xor$ls180.v:5089$913_Y
+ attribute \src "ls180.v:5089.183-5089.312"
+ wire $xor$ls180.v:5089$914_Y
+ attribute \src "ls180.v:5090.879-5090.961"
+ wire $xor$ls180.v:5090$915_Y
+ attribute \src "ls180.v:5090.620-5090.702"
+ wire $xor$ls180.v:5090$916_Y
+ attribute \src "ls180.v:5090.575-5090.703"
+ wire $xor$ls180.v:5090$917_Y
+ attribute \src "ls180.v:5090.229-5090.311"
+ wire $xor$ls180.v:5090$918_Y
+ attribute \src "ls180.v:5090.183-5090.312"
+ wire $xor$ls180.v:5090$919_Y
+ attribute \src "ls180.v:5099.879-5099.961"
+ wire $xor$ls180.v:5099$921_Y
+ attribute \src "ls180.v:5099.620-5099.702"
+ wire $xor$ls180.v:5099$922_Y
+ attribute \src "ls180.v:5099.575-5099.703"
+ wire $xor$ls180.v:5099$923_Y
+ attribute \src "ls180.v:5099.229-5099.311"
+ wire $xor$ls180.v:5099$924_Y
+ attribute \src "ls180.v:5099.183-5099.312"
+ wire $xor$ls180.v:5099$925_Y
+ attribute \src "ls180.v:5100.879-5100.961"
+ wire $xor$ls180.v:5100$926_Y
+ attribute \src "ls180.v:5100.620-5100.702"
+ wire $xor$ls180.v:5100$927_Y
+ attribute \src "ls180.v:5100.575-5100.703"
+ wire $xor$ls180.v:5100$928_Y
+ attribute \src "ls180.v:5100.229-5100.311"
+ wire $xor$ls180.v:5100$929_Y
+ attribute \src "ls180.v:5100.183-5100.312"
+ wire $xor$ls180.v:5100$930_Y
+ attribute \src "ls180.v:5109.879-5109.961"
+ wire $xor$ls180.v:5109$932_Y
+ attribute \src "ls180.v:5109.620-5109.702"
+ wire $xor$ls180.v:5109$933_Y
+ attribute \src "ls180.v:5109.575-5109.703"
+ wire $xor$ls180.v:5109$934_Y
+ attribute \src "ls180.v:5109.229-5109.311"
+ wire $xor$ls180.v:5109$935_Y
+ attribute \src "ls180.v:5109.183-5109.312"
+ wire $xor$ls180.v:5109$936_Y
+ attribute \src "ls180.v:5110.879-5110.961"
+ wire $xor$ls180.v:5110$937_Y
+ attribute \src "ls180.v:5110.620-5110.702"
+ wire $xor$ls180.v:5110$938_Y
+ attribute \src "ls180.v:5110.575-5110.703"
+ wire $xor$ls180.v:5110$939_Y
+ attribute \src "ls180.v:5110.229-5110.311"
+ wire $xor$ls180.v:5110$940_Y
+ attribute \src "ls180.v:5110.183-5110.312"
+ wire $xor$ls180.v:5110$941_Y
+ attribute \src "ls180.v:5119.879-5119.961"
+ wire $xor$ls180.v:5119$943_Y
+ attribute \src "ls180.v:5119.620-5119.702"
+ wire $xor$ls180.v:5119$944_Y
+ attribute \src "ls180.v:5119.575-5119.703"
+ wire $xor$ls180.v:5119$945_Y
+ attribute \src "ls180.v:5119.229-5119.311"
+ wire $xor$ls180.v:5119$946_Y
+ attribute \src "ls180.v:5119.183-5119.312"
+ wire $xor$ls180.v:5119$947_Y
+ attribute \src "ls180.v:5120.879-5120.961"
+ wire $xor$ls180.v:5120$948_Y
+ attribute \src "ls180.v:5120.620-5120.702"
+ wire $xor$ls180.v:5120$949_Y
+ attribute \src "ls180.v:5120.575-5120.703"
+ wire $xor$ls180.v:5120$950_Y
+ attribute \src "ls180.v:5120.229-5120.311"
+ wire $xor$ls180.v:5120$951_Y
+ attribute \src "ls180.v:5120.183-5120.312"
+ wire $xor$ls180.v:5120$952_Y
+ attribute \src "ls180.v:1725.11-1725.42"
wire width 3 \builder_bankmachine0_next_state
- attribute \src "ls180.v:1708.11-1708.37"
+ attribute \src "ls180.v:1724.11-1724.37"
wire width 3 \builder_bankmachine0_state
- attribute \src "ls180.v:1711.11-1711.42"
+ attribute \src "ls180.v:1727.11-1727.42"
wire width 3 \builder_bankmachine1_next_state
- attribute \src "ls180.v:1710.11-1710.37"
+ attribute \src "ls180.v:1726.11-1726.37"
wire width 3 \builder_bankmachine1_state
- attribute \src "ls180.v:1713.11-1713.42"
+ attribute \src "ls180.v:1729.11-1729.42"
wire width 3 \builder_bankmachine2_next_state
- attribute \src "ls180.v:1712.11-1712.37"
+ attribute \src "ls180.v:1728.11-1728.37"
wire width 3 \builder_bankmachine2_state
- attribute \src "ls180.v:1715.11-1715.42"
+ attribute \src "ls180.v:1731.11-1731.42"
wire width 3 \builder_bankmachine3_next_state
- attribute \src "ls180.v:1714.11-1714.37"
+ attribute \src "ls180.v:1730.11-1730.37"
wire width 3 \builder_bankmachine3_state
- attribute \src "ls180.v:2547.5-2547.34"
+ attribute \src "ls180.v:2576.5-2576.34"
wire \builder_comb_rhs_array_muxed0
- attribute \src "ls180.v:2548.12-2548.41"
+ attribute \src "ls180.v:2577.12-2577.41"
wire width 13 \builder_comb_rhs_array_muxed1
- attribute \src "ls180.v:2560.5-2560.35"
+ attribute \src "ls180.v:2589.5-2589.35"
wire \builder_comb_rhs_array_muxed10
- attribute \src "ls180.v:2561.5-2561.35"
+ attribute \src "ls180.v:2590.5-2590.35"
wire \builder_comb_rhs_array_muxed11
- attribute \src "ls180.v:2565.12-2565.42"
+ attribute \src "ls180.v:2594.12-2594.42"
wire width 22 \builder_comb_rhs_array_muxed12
- attribute \src "ls180.v:2566.5-2566.35"
+ attribute \src "ls180.v:2595.5-2595.35"
wire \builder_comb_rhs_array_muxed13
- attribute \src "ls180.v:2567.5-2567.35"
+ attribute \src "ls180.v:2596.5-2596.35"
wire \builder_comb_rhs_array_muxed14
- attribute \src "ls180.v:2568.12-2568.42"
+ attribute \src "ls180.v:2597.12-2597.42"
wire width 22 \builder_comb_rhs_array_muxed15
- attribute \src "ls180.v:2569.5-2569.35"
+ attribute \src "ls180.v:2598.5-2598.35"
wire \builder_comb_rhs_array_muxed16
- attribute \src "ls180.v:2570.5-2570.35"
+ attribute \src "ls180.v:2599.5-2599.35"
wire \builder_comb_rhs_array_muxed17
- attribute \src "ls180.v:2571.12-2571.42"
+ attribute \src "ls180.v:2600.12-2600.42"
wire width 22 \builder_comb_rhs_array_muxed18
- attribute \src "ls180.v:2572.5-2572.35"
+ attribute \src "ls180.v:2601.5-2601.35"
wire \builder_comb_rhs_array_muxed19
- attribute \src "ls180.v:2549.11-2549.40"
+ attribute \src "ls180.v:2578.11-2578.40"
wire width 2 \builder_comb_rhs_array_muxed2
- attribute \src "ls180.v:2573.5-2573.35"
+ attribute \src "ls180.v:2602.5-2602.35"
wire \builder_comb_rhs_array_muxed20
- attribute \src "ls180.v:2574.12-2574.42"
+ attribute \src "ls180.v:2603.12-2603.42"
wire width 22 \builder_comb_rhs_array_muxed21
- attribute \src "ls180.v:2575.5-2575.35"
+ attribute \src "ls180.v:2604.5-2604.35"
wire \builder_comb_rhs_array_muxed22
- attribute \src "ls180.v:2576.5-2576.35"
+ attribute \src "ls180.v:2605.5-2605.35"
wire \builder_comb_rhs_array_muxed23
- attribute \src "ls180.v:2577.12-2577.42"
+ attribute \src "ls180.v:2606.12-2606.42"
wire width 32 \builder_comb_rhs_array_muxed24
- attribute \src "ls180.v:2578.12-2578.42"
+ attribute \src "ls180.v:2607.12-2607.42"
wire width 32 \builder_comb_rhs_array_muxed25
- attribute \src "ls180.v:2579.11-2579.41"
+ attribute \src "ls180.v:2608.11-2608.41"
wire width 4 \builder_comb_rhs_array_muxed26
- attribute \src "ls180.v:2580.5-2580.35"
+ attribute \src "ls180.v:2609.5-2609.35"
wire \builder_comb_rhs_array_muxed27
- attribute \src "ls180.v:2581.5-2581.35"
+ attribute \src "ls180.v:2610.5-2610.35"
wire \builder_comb_rhs_array_muxed28
- attribute \src "ls180.v:2582.5-2582.35"
+ attribute \src "ls180.v:2611.5-2611.35"
wire \builder_comb_rhs_array_muxed29
- attribute \src "ls180.v:2550.5-2550.34"
+ attribute \src "ls180.v:2579.5-2579.34"
wire \builder_comb_rhs_array_muxed3
- attribute \src "ls180.v:2583.11-2583.41"
+ attribute \src "ls180.v:2612.11-2612.41"
wire width 3 \builder_comb_rhs_array_muxed30
- attribute \src "ls180.v:2584.11-2584.41"
+ attribute \src "ls180.v:2613.11-2613.41"
wire width 2 \builder_comb_rhs_array_muxed31
- attribute \src "ls180.v:2551.5-2551.34"
+ attribute \src "ls180.v:2580.5-2580.34"
wire \builder_comb_rhs_array_muxed4
- attribute \src "ls180.v:2552.5-2552.34"
+ attribute \src "ls180.v:2581.5-2581.34"
wire \builder_comb_rhs_array_muxed5
- attribute \src "ls180.v:2556.5-2556.34"
+ attribute \src "ls180.v:2585.5-2585.34"
wire \builder_comb_rhs_array_muxed6
- attribute \src "ls180.v:2557.12-2557.41"
+ attribute \src "ls180.v:2586.12-2586.41"
wire width 13 \builder_comb_rhs_array_muxed7
- attribute \src "ls180.v:2558.11-2558.40"
+ attribute \src "ls180.v:2587.11-2587.40"
wire width 2 \builder_comb_rhs_array_muxed8
- attribute \src "ls180.v:2559.5-2559.34"
+ attribute \src "ls180.v:2588.5-2588.34"
wire \builder_comb_rhs_array_muxed9
- attribute \src "ls180.v:2553.5-2553.32"
+ attribute \src "ls180.v:2582.5-2582.32"
wire \builder_comb_t_array_muxed0
- attribute \src "ls180.v:2554.5-2554.32"
+ attribute \src "ls180.v:2583.5-2583.32"
wire \builder_comb_t_array_muxed1
- attribute \src "ls180.v:2555.5-2555.32"
+ attribute \src "ls180.v:2584.5-2584.32"
wire \builder_comb_t_array_muxed2
- attribute \src "ls180.v:2562.5-2562.32"
+ attribute \src "ls180.v:2591.5-2591.32"
wire \builder_comb_t_array_muxed3
- attribute \src "ls180.v:2563.5-2563.32"
+ attribute \src "ls180.v:2592.5-2592.32"
wire \builder_comb_t_array_muxed4
- attribute \src "ls180.v:2564.5-2564.32"
+ attribute \src "ls180.v:2593.5-2593.32"
wire \builder_comb_t_array_muxed5
- attribute \src "ls180.v:1695.5-1695.34"
+ attribute \src "ls180.v:1711.5-1711.34"
wire \builder_converter0_next_state
- attribute \src "ls180.v:1694.5-1694.29"
+ attribute \src "ls180.v:1710.5-1710.29"
wire \builder_converter0_state
- attribute \src "ls180.v:1699.5-1699.34"
+ attribute \src "ls180.v:1715.5-1715.34"
wire \builder_converter1_next_state
- attribute \src "ls180.v:1698.5-1698.29"
+ attribute \src "ls180.v:1714.5-1714.29"
wire \builder_converter1_state
- attribute \src "ls180.v:1703.5-1703.34"
+ attribute \src "ls180.v:1719.5-1719.34"
wire \builder_converter2_next_state
- attribute \src "ls180.v:1702.5-1702.29"
+ attribute \src "ls180.v:1718.5-1718.29"
wire \builder_converter2_state
- attribute \src "ls180.v:1740.5-1740.33"
+ attribute \src "ls180.v:1756.5-1756.33"
wire \builder_converter_next_state
- attribute \src "ls180.v:1739.5-1739.28"
+ attribute \src "ls180.v:1755.5-1755.28"
wire \builder_converter_state
- attribute \src "ls180.v:1860.12-1860.25"
+ attribute \src "ls180.v:1876.12-1876.25"
wire width 20 \builder_count
- attribute \src "ls180.v:2535.13-2535.41"
+ attribute \src "ls180.v:2564.13-2564.41"
wire width 14 \builder_csr_interconnect_adr
- attribute \src "ls180.v:2538.12-2538.42"
+ attribute \src "ls180.v:2567.12-2567.42"
wire width 8 \builder_csr_interconnect_dat_r
- attribute \src "ls180.v:2537.12-2537.42"
+ attribute \src "ls180.v:2566.12-2566.42"
wire width 8 \builder_csr_interconnect_dat_w
- attribute \src "ls180.v:2536.6-2536.33"
+ attribute \src "ls180.v:2565.6-2565.33"
wire \builder_csr_interconnect_we
- attribute \src "ls180.v:1898.12-1898.42"
+ attribute \src "ls180.v:1914.12-1914.42"
wire width 8 \builder_csrbank0_bus_errors0_r
- attribute \src "ls180.v:1897.6-1897.37"
+ attribute \src "ls180.v:1913.6-1913.37"
wire \builder_csrbank0_bus_errors0_re
- attribute \src "ls180.v:1900.12-1900.42"
+ attribute \src "ls180.v:1916.12-1916.42"
wire width 8 \builder_csrbank0_bus_errors0_w
- attribute \src "ls180.v:1899.6-1899.37"
+ attribute \src "ls180.v:1915.6-1915.37"
wire \builder_csrbank0_bus_errors0_we
- attribute \src "ls180.v:1894.12-1894.42"
+ attribute \src "ls180.v:1910.12-1910.42"
wire width 8 \builder_csrbank0_bus_errors1_r
- attribute \src "ls180.v:1893.6-1893.37"
+ attribute \src "ls180.v:1909.6-1909.37"
wire \builder_csrbank0_bus_errors1_re
- attribute \src "ls180.v:1896.12-1896.42"
+ attribute \src "ls180.v:1912.12-1912.42"
wire width 8 \builder_csrbank0_bus_errors1_w
- attribute \src "ls180.v:1895.6-1895.37"
+ attribute \src "ls180.v:1911.6-1911.37"
wire \builder_csrbank0_bus_errors1_we
- attribute \src "ls180.v:1890.12-1890.42"
+ attribute \src "ls180.v:1906.12-1906.42"
wire width 8 \builder_csrbank0_bus_errors2_r
- attribute \src "ls180.v:1889.6-1889.37"
+ attribute \src "ls180.v:1905.6-1905.37"
wire \builder_csrbank0_bus_errors2_re
- attribute \src "ls180.v:1892.12-1892.42"
+ attribute \src "ls180.v:1908.12-1908.42"
wire width 8 \builder_csrbank0_bus_errors2_w
- attribute \src "ls180.v:1891.6-1891.37"
+ attribute \src "ls180.v:1907.6-1907.37"
wire \builder_csrbank0_bus_errors2_we
- attribute \src "ls180.v:1886.12-1886.42"
+ attribute \src "ls180.v:1902.12-1902.42"
wire width 8 \builder_csrbank0_bus_errors3_r
- attribute \src "ls180.v:1885.6-1885.37"
+ attribute \src "ls180.v:1901.6-1901.37"
wire \builder_csrbank0_bus_errors3_re
- attribute \src "ls180.v:1888.12-1888.42"
+ attribute \src "ls180.v:1904.12-1904.42"
wire width 8 \builder_csrbank0_bus_errors3_w
- attribute \src "ls180.v:1887.6-1887.37"
+ attribute \src "ls180.v:1903.6-1903.37"
wire \builder_csrbank0_bus_errors3_we
- attribute \src "ls180.v:1866.6-1866.31"
+ attribute \src "ls180.v:1882.6-1882.31"
wire \builder_csrbank0_reset0_r
- attribute \src "ls180.v:1865.6-1865.32"
+ attribute \src "ls180.v:1881.6-1881.32"
wire \builder_csrbank0_reset0_re
- attribute \src "ls180.v:1868.6-1868.31"
+ attribute \src "ls180.v:1884.6-1884.31"
wire \builder_csrbank0_reset0_w
- attribute \src "ls180.v:1867.6-1867.32"
+ attribute \src "ls180.v:1883.6-1883.32"
wire \builder_csrbank0_reset0_we
- attribute \src "ls180.v:1882.12-1882.39"
+ attribute \src "ls180.v:1898.12-1898.39"
wire width 8 \builder_csrbank0_scratch0_r
- attribute \src "ls180.v:1881.6-1881.34"
+ attribute \src "ls180.v:1897.6-1897.34"
wire \builder_csrbank0_scratch0_re
- attribute \src "ls180.v:1884.12-1884.39"
+ attribute \src "ls180.v:1900.12-1900.39"
wire width 8 \builder_csrbank0_scratch0_w
- attribute \src "ls180.v:1883.6-1883.34"
+ attribute \src "ls180.v:1899.6-1899.34"
wire \builder_csrbank0_scratch0_we
- attribute \src "ls180.v:1878.12-1878.39"
+ attribute \src "ls180.v:1894.12-1894.39"
wire width 8 \builder_csrbank0_scratch1_r
- attribute \src "ls180.v:1877.6-1877.34"
+ attribute \src "ls180.v:1893.6-1893.34"
wire \builder_csrbank0_scratch1_re
- attribute \src "ls180.v:1880.12-1880.39"
+ attribute \src "ls180.v:1896.12-1896.39"
wire width 8 \builder_csrbank0_scratch1_w
- attribute \src "ls180.v:1879.6-1879.34"
+ attribute \src "ls180.v:1895.6-1895.34"
wire \builder_csrbank0_scratch1_we
- attribute \src "ls180.v:1874.12-1874.39"
+ attribute \src "ls180.v:1890.12-1890.39"
wire width 8 \builder_csrbank0_scratch2_r
- attribute \src "ls180.v:1873.6-1873.34"
+ attribute \src "ls180.v:1889.6-1889.34"
wire \builder_csrbank0_scratch2_re
- attribute \src "ls180.v:1876.12-1876.39"
+ attribute \src "ls180.v:1892.12-1892.39"
wire width 8 \builder_csrbank0_scratch2_w
- attribute \src "ls180.v:1875.6-1875.34"
+ attribute \src "ls180.v:1891.6-1891.34"
wire \builder_csrbank0_scratch2_we
- attribute \src "ls180.v:1870.12-1870.39"
+ attribute \src "ls180.v:1886.12-1886.39"
wire width 8 \builder_csrbank0_scratch3_r
- attribute \src "ls180.v:1869.6-1869.34"
+ attribute \src "ls180.v:1885.6-1885.34"
wire \builder_csrbank0_scratch3_re
- attribute \src "ls180.v:1872.12-1872.39"
+ attribute \src "ls180.v:1888.12-1888.39"
wire width 8 \builder_csrbank0_scratch3_w
- attribute \src "ls180.v:1871.6-1871.34"
+ attribute \src "ls180.v:1887.6-1887.34"
wire \builder_csrbank0_scratch3_we
- attribute \src "ls180.v:1901.6-1901.26"
+ attribute \src "ls180.v:1917.6-1917.26"
wire \builder_csrbank0_sel
- attribute \src "ls180.v:2420.12-2420.44"
- wire width 8 \builder_csrbank10_clk_divider0_r
- attribute \src "ls180.v:2419.6-2419.39"
- wire \builder_csrbank10_clk_divider0_re
- attribute \src "ls180.v:2422.12-2422.44"
- wire width 8 \builder_csrbank10_clk_divider0_w
- attribute \src "ls180.v:2421.6-2421.39"
- wire \builder_csrbank10_clk_divider0_we
- attribute \src "ls180.v:2416.12-2416.44"
- wire width 8 \builder_csrbank10_clk_divider1_r
- attribute \src "ls180.v:2415.6-2415.39"
- wire \builder_csrbank10_clk_divider1_re
- attribute \src "ls180.v:2418.12-2418.44"
- wire width 8 \builder_csrbank10_clk_divider1_w
- attribute \src "ls180.v:2417.6-2417.39"
- wire \builder_csrbank10_clk_divider1_we
- attribute \src "ls180.v:2392.12-2392.40"
+ attribute \src "ls180.v:2388.12-2388.40"
wire width 8 \builder_csrbank10_control0_r
- attribute \src "ls180.v:2391.6-2391.35"
+ attribute \src "ls180.v:2387.6-2387.35"
wire \builder_csrbank10_control0_re
- attribute \src "ls180.v:2394.12-2394.40"
+ attribute \src "ls180.v:2390.12-2390.40"
wire width 8 \builder_csrbank10_control0_w
- attribute \src "ls180.v:2393.6-2393.35"
+ attribute \src "ls180.v:2389.6-2389.35"
wire \builder_csrbank10_control0_we
- attribute \src "ls180.v:2388.12-2388.40"
+ attribute \src "ls180.v:2384.12-2384.40"
wire width 8 \builder_csrbank10_control1_r
- attribute \src "ls180.v:2387.6-2387.35"
+ attribute \src "ls180.v:2383.6-2383.35"
wire \builder_csrbank10_control1_re
- attribute \src "ls180.v:2390.12-2390.40"
+ attribute \src "ls180.v:2386.12-2386.40"
wire width 8 \builder_csrbank10_control1_w
- attribute \src "ls180.v:2389.6-2389.35"
+ attribute \src "ls180.v:2385.6-2385.35"
wire \builder_csrbank10_control1_we
- attribute \src "ls180.v:2408.6-2408.29"
+ attribute \src "ls180.v:2404.6-2404.29"
wire \builder_csrbank10_cs0_r
- attribute \src "ls180.v:2407.6-2407.30"
+ attribute \src "ls180.v:2403.6-2403.30"
wire \builder_csrbank10_cs0_re
- attribute \src "ls180.v:2410.6-2410.29"
+ attribute \src "ls180.v:2406.6-2406.29"
wire \builder_csrbank10_cs0_w
- attribute \src "ls180.v:2409.6-2409.30"
+ attribute \src "ls180.v:2405.6-2405.30"
wire \builder_csrbank10_cs0_we
- attribute \src "ls180.v:2412.6-2412.35"
+ attribute \src "ls180.v:2408.6-2408.35"
wire \builder_csrbank10_loopback0_r
- attribute \src "ls180.v:2411.6-2411.36"
+ attribute \src "ls180.v:2407.6-2407.36"
wire \builder_csrbank10_loopback0_re
- attribute \src "ls180.v:2414.6-2414.35"
+ attribute \src "ls180.v:2410.6-2410.35"
wire \builder_csrbank10_loopback0_w
- attribute \src "ls180.v:2413.6-2413.36"
+ attribute \src "ls180.v:2409.6-2409.36"
wire \builder_csrbank10_loopback0_we
- attribute \src "ls180.v:2404.12-2404.36"
+ attribute \src "ls180.v:2400.12-2400.36"
wire width 8 \builder_csrbank10_miso_r
- attribute \src "ls180.v:2403.6-2403.31"
+ attribute \src "ls180.v:2399.6-2399.31"
wire \builder_csrbank10_miso_re
- attribute \src "ls180.v:2406.12-2406.36"
+ attribute \src "ls180.v:2402.12-2402.36"
wire width 8 \builder_csrbank10_miso_w
- attribute \src "ls180.v:2405.6-2405.31"
+ attribute \src "ls180.v:2401.6-2401.31"
wire \builder_csrbank10_miso_we
- attribute \src "ls180.v:2400.12-2400.37"
+ attribute \src "ls180.v:2396.12-2396.37"
wire width 8 \builder_csrbank10_mosi0_r
- attribute \src "ls180.v:2399.6-2399.32"
+ attribute \src "ls180.v:2395.6-2395.32"
wire \builder_csrbank10_mosi0_re
- attribute \src "ls180.v:2402.12-2402.37"
+ attribute \src "ls180.v:2398.12-2398.37"
wire width 8 \builder_csrbank10_mosi0_w
- attribute \src "ls180.v:2401.6-2401.32"
+ attribute \src "ls180.v:2397.6-2397.32"
wire \builder_csrbank10_mosi0_we
- attribute \src "ls180.v:2423.6-2423.27"
+ attribute \src "ls180.v:2411.6-2411.27"
wire \builder_csrbank10_sel
- attribute \src "ls180.v:2396.6-2396.32"
+ attribute \src "ls180.v:2392.6-2392.32"
wire \builder_csrbank10_status_r
- attribute \src "ls180.v:2395.6-2395.33"
+ attribute \src "ls180.v:2391.6-2391.33"
wire \builder_csrbank10_status_re
- attribute \src "ls180.v:2398.6-2398.32"
+ attribute \src "ls180.v:2394.6-2394.32"
wire \builder_csrbank10_status_w
- attribute \src "ls180.v:2397.6-2397.33"
+ attribute \src "ls180.v:2393.6-2393.33"
wire \builder_csrbank10_status_we
- attribute \src "ls180.v:2461.6-2461.29"
- wire \builder_csrbank11_en0_r
- attribute \src "ls180.v:2460.6-2460.30"
- wire \builder_csrbank11_en0_re
- attribute \src "ls180.v:2463.6-2463.29"
- wire \builder_csrbank11_en0_w
- attribute \src "ls180.v:2462.6-2462.30"
- wire \builder_csrbank11_en0_we
- attribute \src "ls180.v:2485.6-2485.36"
- wire \builder_csrbank11_ev_enable0_r
- attribute \src "ls180.v:2484.6-2484.37"
- wire \builder_csrbank11_ev_enable0_re
- attribute \src "ls180.v:2487.6-2487.36"
- wire \builder_csrbank11_ev_enable0_w
- attribute \src "ls180.v:2486.6-2486.37"
- wire \builder_csrbank11_ev_enable0_we
- attribute \src "ls180.v:2441.12-2441.37"
- wire width 8 \builder_csrbank11_load0_r
- attribute \src "ls180.v:2440.6-2440.32"
- wire \builder_csrbank11_load0_re
- attribute \src "ls180.v:2443.12-2443.37"
- wire width 8 \builder_csrbank11_load0_w
- attribute \src "ls180.v:2442.6-2442.32"
- wire \builder_csrbank11_load0_we
- attribute \src "ls180.v:2437.12-2437.37"
- wire width 8 \builder_csrbank11_load1_r
- attribute \src "ls180.v:2436.6-2436.32"
- wire \builder_csrbank11_load1_re
- attribute \src "ls180.v:2439.12-2439.37"
- wire width 8 \builder_csrbank11_load1_w
- attribute \src "ls180.v:2438.6-2438.32"
- wire \builder_csrbank11_load1_we
- attribute \src "ls180.v:2433.12-2433.37"
- wire width 8 \builder_csrbank11_load2_r
- attribute \src "ls180.v:2432.6-2432.32"
- wire \builder_csrbank11_load2_re
- attribute \src "ls180.v:2435.12-2435.37"
- wire width 8 \builder_csrbank11_load2_w
- attribute \src "ls180.v:2434.6-2434.32"
- wire \builder_csrbank11_load2_we
+ attribute \src "ls180.v:2449.12-2449.44"
+ wire width 8 \builder_csrbank11_clk_divider0_r
+ attribute \src "ls180.v:2448.6-2448.39"
+ wire \builder_csrbank11_clk_divider0_re
+ attribute \src "ls180.v:2451.12-2451.44"
+ wire width 8 \builder_csrbank11_clk_divider0_w
+ attribute \src "ls180.v:2450.6-2450.39"
+ wire \builder_csrbank11_clk_divider0_we
+ attribute \src "ls180.v:2445.12-2445.44"
+ wire width 8 \builder_csrbank11_clk_divider1_r
+ attribute \src "ls180.v:2444.6-2444.39"
+ wire \builder_csrbank11_clk_divider1_re
+ attribute \src "ls180.v:2447.12-2447.44"
+ wire width 8 \builder_csrbank11_clk_divider1_w
+ attribute \src "ls180.v:2446.6-2446.39"
+ wire \builder_csrbank11_clk_divider1_we
+ attribute \src "ls180.v:2421.12-2421.40"
+ wire width 8 \builder_csrbank11_control0_r
+ attribute \src "ls180.v:2420.6-2420.35"
+ wire \builder_csrbank11_control0_re
+ attribute \src "ls180.v:2423.12-2423.40"
+ wire width 8 \builder_csrbank11_control0_w
+ attribute \src "ls180.v:2422.6-2422.35"
+ wire \builder_csrbank11_control0_we
+ attribute \src "ls180.v:2417.12-2417.40"
+ wire width 8 \builder_csrbank11_control1_r
+ attribute \src "ls180.v:2416.6-2416.35"
+ wire \builder_csrbank11_control1_re
+ attribute \src "ls180.v:2419.12-2419.40"
+ wire width 8 \builder_csrbank11_control1_w
+ attribute \src "ls180.v:2418.6-2418.35"
+ wire \builder_csrbank11_control1_we
+ attribute \src "ls180.v:2437.6-2437.29"
+ wire \builder_csrbank11_cs0_r
+ attribute \src "ls180.v:2436.6-2436.30"
+ wire \builder_csrbank11_cs0_re
+ attribute \src "ls180.v:2439.6-2439.29"
+ wire \builder_csrbank11_cs0_w
+ attribute \src "ls180.v:2438.6-2438.30"
+ wire \builder_csrbank11_cs0_we
+ attribute \src "ls180.v:2441.6-2441.35"
+ wire \builder_csrbank11_loopback0_r
+ attribute \src "ls180.v:2440.6-2440.36"
+ wire \builder_csrbank11_loopback0_re
+ attribute \src "ls180.v:2443.6-2443.35"
+ wire \builder_csrbank11_loopback0_w
+ attribute \src "ls180.v:2442.6-2442.36"
+ wire \builder_csrbank11_loopback0_we
+ attribute \src "ls180.v:2433.12-2433.36"
+ wire width 8 \builder_csrbank11_miso_r
+ attribute \src "ls180.v:2432.6-2432.31"
+ wire \builder_csrbank11_miso_re
+ attribute \src "ls180.v:2435.12-2435.36"
+ wire width 8 \builder_csrbank11_miso_w
+ attribute \src "ls180.v:2434.6-2434.31"
+ wire \builder_csrbank11_miso_we
attribute \src "ls180.v:2429.12-2429.37"
- wire width 8 \builder_csrbank11_load3_r
+ wire width 8 \builder_csrbank11_mosi0_r
attribute \src "ls180.v:2428.6-2428.32"
- wire \builder_csrbank11_load3_re
+ wire \builder_csrbank11_mosi0_re
attribute \src "ls180.v:2431.12-2431.37"
- wire width 8 \builder_csrbank11_load3_w
+ wire width 8 \builder_csrbank11_mosi0_w
attribute \src "ls180.v:2430.6-2430.32"
- wire \builder_csrbank11_load3_we
- attribute \src "ls180.v:2457.12-2457.39"
- wire width 8 \builder_csrbank11_reload0_r
- attribute \src "ls180.v:2456.6-2456.34"
- wire \builder_csrbank11_reload0_re
- attribute \src "ls180.v:2459.12-2459.39"
- wire width 8 \builder_csrbank11_reload0_w
- attribute \src "ls180.v:2458.6-2458.34"
- wire \builder_csrbank11_reload0_we
- attribute \src "ls180.v:2453.12-2453.39"
- wire width 8 \builder_csrbank11_reload1_r
- attribute \src "ls180.v:2452.6-2452.34"
- wire \builder_csrbank11_reload1_re
- attribute \src "ls180.v:2455.12-2455.39"
- wire width 8 \builder_csrbank11_reload1_w
- attribute \src "ls180.v:2454.6-2454.34"
- wire \builder_csrbank11_reload1_we
- attribute \src "ls180.v:2449.12-2449.39"
- wire width 8 \builder_csrbank11_reload2_r
- attribute \src "ls180.v:2448.6-2448.34"
- wire \builder_csrbank11_reload2_re
- attribute \src "ls180.v:2451.12-2451.39"
- wire width 8 \builder_csrbank11_reload2_w
- attribute \src "ls180.v:2450.6-2450.34"
- wire \builder_csrbank11_reload2_we
- attribute \src "ls180.v:2445.12-2445.39"
- wire width 8 \builder_csrbank11_reload3_r
- attribute \src "ls180.v:2444.6-2444.34"
- wire \builder_csrbank11_reload3_re
- attribute \src "ls180.v:2447.12-2447.39"
- wire width 8 \builder_csrbank11_reload3_w
- attribute \src "ls180.v:2446.6-2446.34"
- wire \builder_csrbank11_reload3_we
- attribute \src "ls180.v:2488.6-2488.27"
+ wire \builder_csrbank11_mosi0_we
+ attribute \src "ls180.v:2452.6-2452.27"
wire \builder_csrbank11_sel
- attribute \src "ls180.v:2465.6-2465.39"
- wire \builder_csrbank11_update_value0_r
- attribute \src "ls180.v:2464.6-2464.40"
- wire \builder_csrbank11_update_value0_re
- attribute \src "ls180.v:2467.6-2467.39"
- wire \builder_csrbank11_update_value0_w
- attribute \src "ls180.v:2466.6-2466.40"
- wire \builder_csrbank11_update_value0_we
- attribute \src "ls180.v:2481.12-2481.38"
- wire width 8 \builder_csrbank11_value0_r
- attribute \src "ls180.v:2480.6-2480.33"
- wire \builder_csrbank11_value0_re
- attribute \src "ls180.v:2483.12-2483.38"
- wire width 8 \builder_csrbank11_value0_w
- attribute \src "ls180.v:2482.6-2482.33"
- wire \builder_csrbank11_value0_we
- attribute \src "ls180.v:2477.12-2477.38"
- wire width 8 \builder_csrbank11_value1_r
- attribute \src "ls180.v:2476.6-2476.33"
- wire \builder_csrbank11_value1_re
- attribute \src "ls180.v:2479.12-2479.38"
- wire width 8 \builder_csrbank11_value1_w
- attribute \src "ls180.v:2478.6-2478.33"
- wire \builder_csrbank11_value1_we
- attribute \src "ls180.v:2473.12-2473.38"
- wire width 8 \builder_csrbank11_value2_r
- attribute \src "ls180.v:2472.6-2472.33"
- wire \builder_csrbank11_value2_re
- attribute \src "ls180.v:2475.12-2475.38"
- wire width 8 \builder_csrbank11_value2_w
- attribute \src "ls180.v:2474.6-2474.33"
- wire \builder_csrbank11_value2_we
- attribute \src "ls180.v:2469.12-2469.38"
- wire width 8 \builder_csrbank11_value3_r
- attribute \src "ls180.v:2468.6-2468.33"
- wire \builder_csrbank11_value3_re
- attribute \src "ls180.v:2471.12-2471.38"
- wire width 8 \builder_csrbank11_value3_w
- attribute \src "ls180.v:2470.6-2470.33"
- wire \builder_csrbank11_value3_we
- attribute \src "ls180.v:2502.12-2502.42"
- wire width 2 \builder_csrbank12_ev_enable0_r
- attribute \src "ls180.v:2501.6-2501.37"
+ attribute \src "ls180.v:2425.6-2425.32"
+ wire \builder_csrbank11_status_r
+ attribute \src "ls180.v:2424.6-2424.33"
+ wire \builder_csrbank11_status_re
+ attribute \src "ls180.v:2427.6-2427.32"
+ wire \builder_csrbank11_status_w
+ attribute \src "ls180.v:2426.6-2426.33"
+ wire \builder_csrbank11_status_we
+ attribute \src "ls180.v:2490.6-2490.29"
+ wire \builder_csrbank12_en0_r
+ attribute \src "ls180.v:2489.6-2489.30"
+ wire \builder_csrbank12_en0_re
+ attribute \src "ls180.v:2492.6-2492.29"
+ wire \builder_csrbank12_en0_w
+ attribute \src "ls180.v:2491.6-2491.30"
+ wire \builder_csrbank12_en0_we
+ attribute \src "ls180.v:2514.6-2514.36"
+ wire \builder_csrbank12_ev_enable0_r
+ attribute \src "ls180.v:2513.6-2513.37"
wire \builder_csrbank12_ev_enable0_re
- attribute \src "ls180.v:2504.12-2504.42"
- wire width 2 \builder_csrbank12_ev_enable0_w
- attribute \src "ls180.v:2503.6-2503.37"
+ attribute \src "ls180.v:2516.6-2516.36"
+ wire \builder_csrbank12_ev_enable0_w
+ attribute \src "ls180.v:2515.6-2515.37"
wire \builder_csrbank12_ev_enable0_we
- attribute \src "ls180.v:2498.6-2498.33"
- wire \builder_csrbank12_rxempty_r
- attribute \src "ls180.v:2497.6-2497.34"
- wire \builder_csrbank12_rxempty_re
- attribute \src "ls180.v:2500.6-2500.33"
- wire \builder_csrbank12_rxempty_w
- attribute \src "ls180.v:2499.6-2499.34"
- wire \builder_csrbank12_rxempty_we
- attribute \src "ls180.v:2510.6-2510.32"
- wire \builder_csrbank12_rxfull_r
+ attribute \src "ls180.v:2470.12-2470.37"
+ wire width 8 \builder_csrbank12_load0_r
+ attribute \src "ls180.v:2469.6-2469.32"
+ wire \builder_csrbank12_load0_re
+ attribute \src "ls180.v:2472.12-2472.37"
+ wire width 8 \builder_csrbank12_load0_w
+ attribute \src "ls180.v:2471.6-2471.32"
+ wire \builder_csrbank12_load0_we
+ attribute \src "ls180.v:2466.12-2466.37"
+ wire width 8 \builder_csrbank12_load1_r
+ attribute \src "ls180.v:2465.6-2465.32"
+ wire \builder_csrbank12_load1_re
+ attribute \src "ls180.v:2468.12-2468.37"
+ wire width 8 \builder_csrbank12_load1_w
+ attribute \src "ls180.v:2467.6-2467.32"
+ wire \builder_csrbank12_load1_we
+ attribute \src "ls180.v:2462.12-2462.37"
+ wire width 8 \builder_csrbank12_load2_r
+ attribute \src "ls180.v:2461.6-2461.32"
+ wire \builder_csrbank12_load2_re
+ attribute \src "ls180.v:2464.12-2464.37"
+ wire width 8 \builder_csrbank12_load2_w
+ attribute \src "ls180.v:2463.6-2463.32"
+ wire \builder_csrbank12_load2_we
+ attribute \src "ls180.v:2458.12-2458.37"
+ wire width 8 \builder_csrbank12_load3_r
+ attribute \src "ls180.v:2457.6-2457.32"
+ wire \builder_csrbank12_load3_re
+ attribute \src "ls180.v:2460.12-2460.37"
+ wire width 8 \builder_csrbank12_load3_w
+ attribute \src "ls180.v:2459.6-2459.32"
+ wire \builder_csrbank12_load3_we
+ attribute \src "ls180.v:2486.12-2486.39"
+ wire width 8 \builder_csrbank12_reload0_r
+ attribute \src "ls180.v:2485.6-2485.34"
+ wire \builder_csrbank12_reload0_re
+ attribute \src "ls180.v:2488.12-2488.39"
+ wire width 8 \builder_csrbank12_reload0_w
+ attribute \src "ls180.v:2487.6-2487.34"
+ wire \builder_csrbank12_reload0_we
+ attribute \src "ls180.v:2482.12-2482.39"
+ wire width 8 \builder_csrbank12_reload1_r
+ attribute \src "ls180.v:2481.6-2481.34"
+ wire \builder_csrbank12_reload1_re
+ attribute \src "ls180.v:2484.12-2484.39"
+ wire width 8 \builder_csrbank12_reload1_w
+ attribute \src "ls180.v:2483.6-2483.34"
+ wire \builder_csrbank12_reload1_we
+ attribute \src "ls180.v:2478.12-2478.39"
+ wire width 8 \builder_csrbank12_reload2_r
+ attribute \src "ls180.v:2477.6-2477.34"
+ wire \builder_csrbank12_reload2_re
+ attribute \src "ls180.v:2480.12-2480.39"
+ wire width 8 \builder_csrbank12_reload2_w
+ attribute \src "ls180.v:2479.6-2479.34"
+ wire \builder_csrbank12_reload2_we
+ attribute \src "ls180.v:2474.12-2474.39"
+ wire width 8 \builder_csrbank12_reload3_r
+ attribute \src "ls180.v:2473.6-2473.34"
+ wire \builder_csrbank12_reload3_re
+ attribute \src "ls180.v:2476.12-2476.39"
+ wire width 8 \builder_csrbank12_reload3_w
+ attribute \src "ls180.v:2475.6-2475.34"
+ wire \builder_csrbank12_reload3_we
+ attribute \src "ls180.v:2517.6-2517.27"
+ wire \builder_csrbank12_sel
+ attribute \src "ls180.v:2494.6-2494.39"
+ wire \builder_csrbank12_update_value0_r
+ attribute \src "ls180.v:2493.6-2493.40"
+ wire \builder_csrbank12_update_value0_re
+ attribute \src "ls180.v:2496.6-2496.39"
+ wire \builder_csrbank12_update_value0_w
+ attribute \src "ls180.v:2495.6-2495.40"
+ wire \builder_csrbank12_update_value0_we
+ attribute \src "ls180.v:2510.12-2510.38"
+ wire width 8 \builder_csrbank12_value0_r
attribute \src "ls180.v:2509.6-2509.33"
- wire \builder_csrbank12_rxfull_re
- attribute \src "ls180.v:2512.6-2512.32"
- wire \builder_csrbank12_rxfull_w
+ wire \builder_csrbank12_value0_re
+ attribute \src "ls180.v:2512.12-2512.38"
+ wire width 8 \builder_csrbank12_value0_w
attribute \src "ls180.v:2511.6-2511.33"
- wire \builder_csrbank12_rxfull_we
- attribute \src "ls180.v:2513.6-2513.27"
- wire \builder_csrbank12_sel
- attribute \src "ls180.v:2506.6-2506.33"
- wire \builder_csrbank12_txempty_r
- attribute \src "ls180.v:2505.6-2505.34"
- wire \builder_csrbank12_txempty_re
- attribute \src "ls180.v:2508.6-2508.33"
- wire \builder_csrbank12_txempty_w
- attribute \src "ls180.v:2507.6-2507.34"
- wire \builder_csrbank12_txempty_we
- attribute \src "ls180.v:2494.6-2494.32"
- wire \builder_csrbank12_txfull_r
- attribute \src "ls180.v:2493.6-2493.33"
- wire \builder_csrbank12_txfull_re
- attribute \src "ls180.v:2496.6-2496.32"
- wire \builder_csrbank12_txfull_w
- attribute \src "ls180.v:2495.6-2495.33"
- wire \builder_csrbank12_txfull_we
- attribute \src "ls180.v:2534.6-2534.27"
+ wire \builder_csrbank12_value0_we
+ attribute \src "ls180.v:2506.12-2506.38"
+ wire width 8 \builder_csrbank12_value1_r
+ attribute \src "ls180.v:2505.6-2505.33"
+ wire \builder_csrbank12_value1_re
+ attribute \src "ls180.v:2508.12-2508.38"
+ wire width 8 \builder_csrbank12_value1_w
+ attribute \src "ls180.v:2507.6-2507.33"
+ wire \builder_csrbank12_value1_we
+ attribute \src "ls180.v:2502.12-2502.38"
+ wire width 8 \builder_csrbank12_value2_r
+ attribute \src "ls180.v:2501.6-2501.33"
+ wire \builder_csrbank12_value2_re
+ attribute \src "ls180.v:2504.12-2504.38"
+ wire width 8 \builder_csrbank12_value2_w
+ attribute \src "ls180.v:2503.6-2503.33"
+ wire \builder_csrbank12_value2_we
+ attribute \src "ls180.v:2498.12-2498.38"
+ wire width 8 \builder_csrbank12_value3_r
+ attribute \src "ls180.v:2497.6-2497.33"
+ wire \builder_csrbank12_value3_re
+ attribute \src "ls180.v:2500.12-2500.38"
+ wire width 8 \builder_csrbank12_value3_w
+ attribute \src "ls180.v:2499.6-2499.33"
+ wire \builder_csrbank12_value3_we
+ attribute \src "ls180.v:2531.12-2531.42"
+ wire width 2 \builder_csrbank13_ev_enable0_r
+ attribute \src "ls180.v:2530.6-2530.37"
+ wire \builder_csrbank13_ev_enable0_re
+ attribute \src "ls180.v:2533.12-2533.42"
+ wire width 2 \builder_csrbank13_ev_enable0_w
+ attribute \src "ls180.v:2532.6-2532.37"
+ wire \builder_csrbank13_ev_enable0_we
+ attribute \src "ls180.v:2527.6-2527.33"
+ wire \builder_csrbank13_rxempty_r
+ attribute \src "ls180.v:2526.6-2526.34"
+ wire \builder_csrbank13_rxempty_re
+ attribute \src "ls180.v:2529.6-2529.33"
+ wire \builder_csrbank13_rxempty_w
+ attribute \src "ls180.v:2528.6-2528.34"
+ wire \builder_csrbank13_rxempty_we
+ attribute \src "ls180.v:2539.6-2539.32"
+ wire \builder_csrbank13_rxfull_r
+ attribute \src "ls180.v:2538.6-2538.33"
+ wire \builder_csrbank13_rxfull_re
+ attribute \src "ls180.v:2541.6-2541.32"
+ wire \builder_csrbank13_rxfull_w
+ attribute \src "ls180.v:2540.6-2540.33"
+ wire \builder_csrbank13_rxfull_we
+ attribute \src "ls180.v:2542.6-2542.27"
wire \builder_csrbank13_sel
- attribute \src "ls180.v:2531.12-2531.44"
- wire width 8 \builder_csrbank13_tuning_word0_r
- attribute \src "ls180.v:2530.6-2530.39"
- wire \builder_csrbank13_tuning_word0_re
- attribute \src "ls180.v:2533.12-2533.44"
- wire width 8 \builder_csrbank13_tuning_word0_w
- attribute \src "ls180.v:2532.6-2532.39"
- wire \builder_csrbank13_tuning_word0_we
- attribute \src "ls180.v:2527.12-2527.44"
- wire width 8 \builder_csrbank13_tuning_word1_r
- attribute \src "ls180.v:2526.6-2526.39"
- wire \builder_csrbank13_tuning_word1_re
- attribute \src "ls180.v:2529.12-2529.44"
- wire width 8 \builder_csrbank13_tuning_word1_w
- attribute \src "ls180.v:2528.6-2528.39"
- wire \builder_csrbank13_tuning_word1_we
- attribute \src "ls180.v:2523.12-2523.44"
- wire width 8 \builder_csrbank13_tuning_word2_r
- attribute \src "ls180.v:2522.6-2522.39"
- wire \builder_csrbank13_tuning_word2_re
- attribute \src "ls180.v:2525.12-2525.44"
- wire width 8 \builder_csrbank13_tuning_word2_w
- attribute \src "ls180.v:2524.6-2524.39"
- wire \builder_csrbank13_tuning_word2_we
- attribute \src "ls180.v:2519.12-2519.44"
- wire width 8 \builder_csrbank13_tuning_word3_r
- attribute \src "ls180.v:2518.6-2518.39"
- wire \builder_csrbank13_tuning_word3_re
- attribute \src "ls180.v:2521.12-2521.44"
- wire width 8 \builder_csrbank13_tuning_word3_w
- attribute \src "ls180.v:2520.6-2520.39"
- wire \builder_csrbank13_tuning_word3_we
- attribute \src "ls180.v:1919.12-1919.34"
+ attribute \src "ls180.v:2535.6-2535.33"
+ wire \builder_csrbank13_txempty_r
+ attribute \src "ls180.v:2534.6-2534.34"
+ wire \builder_csrbank13_txempty_re
+ attribute \src "ls180.v:2537.6-2537.33"
+ wire \builder_csrbank13_txempty_w
+ attribute \src "ls180.v:2536.6-2536.34"
+ wire \builder_csrbank13_txempty_we
+ attribute \src "ls180.v:2523.6-2523.32"
+ wire \builder_csrbank13_txfull_r
+ attribute \src "ls180.v:2522.6-2522.33"
+ wire \builder_csrbank13_txfull_re
+ attribute \src "ls180.v:2525.6-2525.32"
+ wire \builder_csrbank13_txfull_w
+ attribute \src "ls180.v:2524.6-2524.33"
+ wire \builder_csrbank13_txfull_we
+ attribute \src "ls180.v:2563.6-2563.27"
+ wire \builder_csrbank14_sel
+ attribute \src "ls180.v:2560.12-2560.44"
+ wire width 8 \builder_csrbank14_tuning_word0_r
+ attribute \src "ls180.v:2559.6-2559.39"
+ wire \builder_csrbank14_tuning_word0_re
+ attribute \src "ls180.v:2562.12-2562.44"
+ wire width 8 \builder_csrbank14_tuning_word0_w
+ attribute \src "ls180.v:2561.6-2561.39"
+ wire \builder_csrbank14_tuning_word0_we
+ attribute \src "ls180.v:2556.12-2556.44"
+ wire width 8 \builder_csrbank14_tuning_word1_r
+ attribute \src "ls180.v:2555.6-2555.39"
+ wire \builder_csrbank14_tuning_word1_re
+ attribute \src "ls180.v:2558.12-2558.44"
+ wire width 8 \builder_csrbank14_tuning_word1_w
+ attribute \src "ls180.v:2557.6-2557.39"
+ wire \builder_csrbank14_tuning_word1_we
+ attribute \src "ls180.v:2552.12-2552.44"
+ wire width 8 \builder_csrbank14_tuning_word2_r
+ attribute \src "ls180.v:2551.6-2551.39"
+ wire \builder_csrbank14_tuning_word2_re
+ attribute \src "ls180.v:2554.12-2554.44"
+ wire width 8 \builder_csrbank14_tuning_word2_w
+ attribute \src "ls180.v:2553.6-2553.39"
+ wire \builder_csrbank14_tuning_word2_we
+ attribute \src "ls180.v:2548.12-2548.44"
+ wire width 8 \builder_csrbank14_tuning_word3_r
+ attribute \src "ls180.v:2547.6-2547.39"
+ wire \builder_csrbank14_tuning_word3_re
+ attribute \src "ls180.v:2550.12-2550.44"
+ wire width 8 \builder_csrbank14_tuning_word3_w
+ attribute \src "ls180.v:2549.6-2549.39"
+ wire \builder_csrbank14_tuning_word3_we
+ attribute \src "ls180.v:1935.12-1935.34"
wire width 8 \builder_csrbank1_in0_r
- attribute \src "ls180.v:1918.6-1918.29"
+ attribute \src "ls180.v:1934.6-1934.29"
wire \builder_csrbank1_in0_re
- attribute \src "ls180.v:1921.12-1921.34"
+ attribute \src "ls180.v:1937.12-1937.34"
wire width 8 \builder_csrbank1_in0_w
- attribute \src "ls180.v:1920.6-1920.29"
+ attribute \src "ls180.v:1936.6-1936.29"
wire \builder_csrbank1_in0_we
- attribute \src "ls180.v:1915.12-1915.34"
+ attribute \src "ls180.v:1931.12-1931.34"
wire width 8 \builder_csrbank1_in1_r
- attribute \src "ls180.v:1914.6-1914.29"
+ attribute \src "ls180.v:1930.6-1930.29"
wire \builder_csrbank1_in1_re
- attribute \src "ls180.v:1917.12-1917.34"
+ attribute \src "ls180.v:1933.12-1933.34"
wire width 8 \builder_csrbank1_in1_w
- attribute \src "ls180.v:1916.6-1916.29"
+ attribute \src "ls180.v:1932.6-1932.29"
wire \builder_csrbank1_in1_we
- attribute \src "ls180.v:1911.12-1911.34"
+ attribute \src "ls180.v:1927.12-1927.34"
wire width 8 \builder_csrbank1_oe0_r
- attribute \src "ls180.v:1910.6-1910.29"
+ attribute \src "ls180.v:1926.6-1926.29"
wire \builder_csrbank1_oe0_re
- attribute \src "ls180.v:1913.12-1913.34"
+ attribute \src "ls180.v:1929.12-1929.34"
wire width 8 \builder_csrbank1_oe0_w
- attribute \src "ls180.v:1912.6-1912.29"
+ attribute \src "ls180.v:1928.6-1928.29"
wire \builder_csrbank1_oe0_we
- attribute \src "ls180.v:1907.12-1907.34"
+ attribute \src "ls180.v:1923.12-1923.34"
wire width 8 \builder_csrbank1_oe1_r
- attribute \src "ls180.v:1906.6-1906.29"
+ attribute \src "ls180.v:1922.6-1922.29"
wire \builder_csrbank1_oe1_re
- attribute \src "ls180.v:1909.12-1909.34"
+ attribute \src "ls180.v:1925.12-1925.34"
wire width 8 \builder_csrbank1_oe1_w
- attribute \src "ls180.v:1908.6-1908.29"
+ attribute \src "ls180.v:1924.6-1924.29"
wire \builder_csrbank1_oe1_we
- attribute \src "ls180.v:1927.12-1927.35"
+ attribute \src "ls180.v:1943.12-1943.35"
wire width 8 \builder_csrbank1_out0_r
- attribute \src "ls180.v:1926.6-1926.30"
+ attribute \src "ls180.v:1942.6-1942.30"
wire \builder_csrbank1_out0_re
- attribute \src "ls180.v:1929.12-1929.35"
+ attribute \src "ls180.v:1945.12-1945.35"
wire width 8 \builder_csrbank1_out0_w
- attribute \src "ls180.v:1928.6-1928.30"
+ attribute \src "ls180.v:1944.6-1944.30"
wire \builder_csrbank1_out0_we
- attribute \src "ls180.v:1923.12-1923.35"
+ attribute \src "ls180.v:1939.12-1939.35"
wire width 8 \builder_csrbank1_out1_r
- attribute \src "ls180.v:1922.6-1922.30"
+ attribute \src "ls180.v:1938.6-1938.30"
wire \builder_csrbank1_out1_re
- attribute \src "ls180.v:1925.12-1925.35"
+ attribute \src "ls180.v:1941.12-1941.35"
wire width 8 \builder_csrbank1_out1_w
- attribute \src "ls180.v:1924.6-1924.30"
+ attribute \src "ls180.v:1940.6-1940.30"
wire \builder_csrbank1_out1_we
- attribute \src "ls180.v:1930.6-1930.26"
+ attribute \src "ls180.v:1946.6-1946.26"
wire \builder_csrbank1_sel
- attribute \src "ls180.v:1936.6-1936.32"
- wire \builder_csrbank2_enable0_r
- attribute \src "ls180.v:1935.6-1935.33"
- wire \builder_csrbank2_enable0_re
- attribute \src "ls180.v:1938.6-1938.32"
- wire \builder_csrbank2_enable0_w
- attribute \src "ls180.v:1937.6-1937.33"
- wire \builder_csrbank2_enable0_we
- attribute \src "ls180.v:1968.12-1968.38"
- wire width 8 \builder_csrbank2_period0_r
- attribute \src "ls180.v:1967.6-1967.33"
- wire \builder_csrbank2_period0_re
- attribute \src "ls180.v:1970.12-1970.38"
- wire width 8 \builder_csrbank2_period0_w
- attribute \src "ls180.v:1969.6-1969.33"
- wire \builder_csrbank2_period0_we
- attribute \src "ls180.v:1964.12-1964.38"
- wire width 8 \builder_csrbank2_period1_r
- attribute \src "ls180.v:1963.6-1963.33"
- wire \builder_csrbank2_period1_re
- attribute \src "ls180.v:1966.12-1966.38"
- wire width 8 \builder_csrbank2_period1_w
- attribute \src "ls180.v:1965.6-1965.33"
- wire \builder_csrbank2_period1_we
- attribute \src "ls180.v:1960.12-1960.38"
- wire width 8 \builder_csrbank2_period2_r
- attribute \src "ls180.v:1959.6-1959.33"
- wire \builder_csrbank2_period2_re
- attribute \src "ls180.v:1962.12-1962.38"
- wire width 8 \builder_csrbank2_period2_w
- attribute \src "ls180.v:1961.6-1961.33"
- wire \builder_csrbank2_period2_we
- attribute \src "ls180.v:1956.12-1956.38"
- wire width 8 \builder_csrbank2_period3_r
- attribute \src "ls180.v:1955.6-1955.33"
- wire \builder_csrbank2_period3_re
- attribute \src "ls180.v:1958.12-1958.38"
- wire width 8 \builder_csrbank2_period3_w
- attribute \src "ls180.v:1957.6-1957.33"
- wire \builder_csrbank2_period3_we
- attribute \src "ls180.v:1971.6-1971.26"
+ attribute \src "ls180.v:1956.6-1956.26"
+ wire \builder_csrbank2_r_r
+ attribute \src "ls180.v:1955.6-1955.27"
+ wire \builder_csrbank2_r_re
+ attribute \src "ls180.v:1958.6-1958.26"
+ wire \builder_csrbank2_r_w
+ attribute \src "ls180.v:1957.6-1957.27"
+ wire \builder_csrbank2_r_we
+ attribute \src "ls180.v:1959.6-1959.26"
wire \builder_csrbank2_sel
- attribute \src "ls180.v:1952.12-1952.37"
- wire width 8 \builder_csrbank2_width0_r
- attribute \src "ls180.v:1951.6-1951.32"
- wire \builder_csrbank2_width0_re
- attribute \src "ls180.v:1954.12-1954.37"
- wire width 8 \builder_csrbank2_width0_w
- attribute \src "ls180.v:1953.6-1953.32"
- wire \builder_csrbank2_width0_we
- attribute \src "ls180.v:1948.12-1948.37"
- wire width 8 \builder_csrbank2_width1_r
- attribute \src "ls180.v:1947.6-1947.32"
- wire \builder_csrbank2_width1_re
- attribute \src "ls180.v:1950.12-1950.37"
- wire width 8 \builder_csrbank2_width1_w
- attribute \src "ls180.v:1949.6-1949.32"
- wire \builder_csrbank2_width1_we
- attribute \src "ls180.v:1944.12-1944.37"
- wire width 8 \builder_csrbank2_width2_r
- attribute \src "ls180.v:1943.6-1943.32"
- wire \builder_csrbank2_width2_re
- attribute \src "ls180.v:1946.12-1946.37"
- wire width 8 \builder_csrbank2_width2_w
- attribute \src "ls180.v:1945.6-1945.32"
- wire \builder_csrbank2_width2_we
- attribute \src "ls180.v:1940.12-1940.37"
- wire width 8 \builder_csrbank2_width3_r
- attribute \src "ls180.v:1939.6-1939.32"
- wire \builder_csrbank2_width3_re
- attribute \src "ls180.v:1942.12-1942.37"
- wire width 8 \builder_csrbank2_width3_w
- attribute \src "ls180.v:1941.6-1941.32"
- wire \builder_csrbank2_width3_we
- attribute \src "ls180.v:1977.6-1977.32"
+ attribute \src "ls180.v:1952.12-1952.33"
+ wire width 3 \builder_csrbank2_w0_r
+ attribute \src "ls180.v:1951.6-1951.28"
+ wire \builder_csrbank2_w0_re
+ attribute \src "ls180.v:1954.12-1954.33"
+ wire width 3 \builder_csrbank2_w0_w
+ attribute \src "ls180.v:1953.6-1953.28"
+ wire \builder_csrbank2_w0_we
+ attribute \src "ls180.v:1965.6-1965.32"
wire \builder_csrbank3_enable0_r
- attribute \src "ls180.v:1976.6-1976.33"
+ attribute \src "ls180.v:1964.6-1964.33"
wire \builder_csrbank3_enable0_re
- attribute \src "ls180.v:1979.6-1979.32"
+ attribute \src "ls180.v:1967.6-1967.32"
wire \builder_csrbank3_enable0_w
- attribute \src "ls180.v:1978.6-1978.33"
+ attribute \src "ls180.v:1966.6-1966.33"
wire \builder_csrbank3_enable0_we
- attribute \src "ls180.v:2009.12-2009.38"
+ attribute \src "ls180.v:1997.12-1997.38"
wire width 8 \builder_csrbank3_period0_r
- attribute \src "ls180.v:2008.6-2008.33"
+ attribute \src "ls180.v:1996.6-1996.33"
wire \builder_csrbank3_period0_re
- attribute \src "ls180.v:2011.12-2011.38"
+ attribute \src "ls180.v:1999.12-1999.38"
wire width 8 \builder_csrbank3_period0_w
- attribute \src "ls180.v:2010.6-2010.33"
+ attribute \src "ls180.v:1998.6-1998.33"
wire \builder_csrbank3_period0_we
- attribute \src "ls180.v:2005.12-2005.38"
+ attribute \src "ls180.v:1993.12-1993.38"
wire width 8 \builder_csrbank3_period1_r
- attribute \src "ls180.v:2004.6-2004.33"
+ attribute \src "ls180.v:1992.6-1992.33"
wire \builder_csrbank3_period1_re
- attribute \src "ls180.v:2007.12-2007.38"
+ attribute \src "ls180.v:1995.12-1995.38"
wire width 8 \builder_csrbank3_period1_w
- attribute \src "ls180.v:2006.6-2006.33"
+ attribute \src "ls180.v:1994.6-1994.33"
wire \builder_csrbank3_period1_we
- attribute \src "ls180.v:2001.12-2001.38"
+ attribute \src "ls180.v:1989.12-1989.38"
wire width 8 \builder_csrbank3_period2_r
- attribute \src "ls180.v:2000.6-2000.33"
+ attribute \src "ls180.v:1988.6-1988.33"
wire \builder_csrbank3_period2_re
- attribute \src "ls180.v:2003.12-2003.38"
+ attribute \src "ls180.v:1991.12-1991.38"
wire width 8 \builder_csrbank3_period2_w
- attribute \src "ls180.v:2002.6-2002.33"
+ attribute \src "ls180.v:1990.6-1990.33"
wire \builder_csrbank3_period2_we
- attribute \src "ls180.v:1997.12-1997.38"
+ attribute \src "ls180.v:1985.12-1985.38"
wire width 8 \builder_csrbank3_period3_r
- attribute \src "ls180.v:1996.6-1996.33"
+ attribute \src "ls180.v:1984.6-1984.33"
wire \builder_csrbank3_period3_re
- attribute \src "ls180.v:1999.12-1999.38"
+ attribute \src "ls180.v:1987.12-1987.38"
wire width 8 \builder_csrbank3_period3_w
- attribute \src "ls180.v:1998.6-1998.33"
+ attribute \src "ls180.v:1986.6-1986.33"
wire \builder_csrbank3_period3_we
- attribute \src "ls180.v:2012.6-2012.26"
+ attribute \src "ls180.v:2000.6-2000.26"
wire \builder_csrbank3_sel
- attribute \src "ls180.v:1993.12-1993.37"
+ attribute \src "ls180.v:1981.12-1981.37"
wire width 8 \builder_csrbank3_width0_r
- attribute \src "ls180.v:1992.6-1992.32"
+ attribute \src "ls180.v:1980.6-1980.32"
wire \builder_csrbank3_width0_re
- attribute \src "ls180.v:1995.12-1995.37"
+ attribute \src "ls180.v:1983.12-1983.37"
wire width 8 \builder_csrbank3_width0_w
- attribute \src "ls180.v:1994.6-1994.32"
+ attribute \src "ls180.v:1982.6-1982.32"
wire \builder_csrbank3_width0_we
- attribute \src "ls180.v:1989.12-1989.37"
+ attribute \src "ls180.v:1977.12-1977.37"
wire width 8 \builder_csrbank3_width1_r
- attribute \src "ls180.v:1988.6-1988.32"
+ attribute \src "ls180.v:1976.6-1976.32"
wire \builder_csrbank3_width1_re
- attribute \src "ls180.v:1991.12-1991.37"
+ attribute \src "ls180.v:1979.12-1979.37"
wire width 8 \builder_csrbank3_width1_w
- attribute \src "ls180.v:1990.6-1990.32"
+ attribute \src "ls180.v:1978.6-1978.32"
wire \builder_csrbank3_width1_we
- attribute \src "ls180.v:1985.12-1985.37"
+ attribute \src "ls180.v:1973.12-1973.37"
wire width 8 \builder_csrbank3_width2_r
- attribute \src "ls180.v:1984.6-1984.32"
+ attribute \src "ls180.v:1972.6-1972.32"
wire \builder_csrbank3_width2_re
- attribute \src "ls180.v:1987.12-1987.37"
+ attribute \src "ls180.v:1975.12-1975.37"
wire width 8 \builder_csrbank3_width2_w
- attribute \src "ls180.v:1986.6-1986.32"
+ attribute \src "ls180.v:1974.6-1974.32"
wire \builder_csrbank3_width2_we
- attribute \src "ls180.v:1981.12-1981.37"
+ attribute \src "ls180.v:1969.12-1969.37"
wire width 8 \builder_csrbank3_width3_r
- attribute \src "ls180.v:1980.6-1980.32"
+ attribute \src "ls180.v:1968.6-1968.32"
wire \builder_csrbank3_width3_re
- attribute \src "ls180.v:1983.12-1983.37"
+ attribute \src "ls180.v:1971.12-1971.37"
wire width 8 \builder_csrbank3_width3_w
- attribute \src "ls180.v:1982.6-1982.32"
+ attribute \src "ls180.v:1970.6-1970.32"
wire \builder_csrbank3_width3_we
- attribute \src "ls180.v:2046.12-2046.40"
- wire width 8 \builder_csrbank4_dma_base0_r
- attribute \src "ls180.v:2045.6-2045.35"
- wire \builder_csrbank4_dma_base0_re
- attribute \src "ls180.v:2048.12-2048.40"
- wire width 8 \builder_csrbank4_dma_base0_w
- attribute \src "ls180.v:2047.6-2047.35"
- wire \builder_csrbank4_dma_base0_we
- attribute \src "ls180.v:2042.12-2042.40"
- wire width 8 \builder_csrbank4_dma_base1_r
- attribute \src "ls180.v:2041.6-2041.35"
- wire \builder_csrbank4_dma_base1_re
- attribute \src "ls180.v:2044.12-2044.40"
- wire width 8 \builder_csrbank4_dma_base1_w
- attribute \src "ls180.v:2043.6-2043.35"
- wire \builder_csrbank4_dma_base1_we
- attribute \src "ls180.v:2038.12-2038.40"
- wire width 8 \builder_csrbank4_dma_base2_r
- attribute \src "ls180.v:2037.6-2037.35"
- wire \builder_csrbank4_dma_base2_re
- attribute \src "ls180.v:2040.12-2040.40"
- wire width 8 \builder_csrbank4_dma_base2_w
- attribute \src "ls180.v:2039.6-2039.35"
- wire \builder_csrbank4_dma_base2_we
- attribute \src "ls180.v:2034.12-2034.40"
- wire width 8 \builder_csrbank4_dma_base3_r
- attribute \src "ls180.v:2033.6-2033.35"
- wire \builder_csrbank4_dma_base3_re
- attribute \src "ls180.v:2036.12-2036.40"
- wire width 8 \builder_csrbank4_dma_base3_w
- attribute \src "ls180.v:2035.6-2035.35"
- wire \builder_csrbank4_dma_base3_we
- attribute \src "ls180.v:2030.12-2030.40"
- wire width 8 \builder_csrbank4_dma_base4_r
- attribute \src "ls180.v:2029.6-2029.35"
- wire \builder_csrbank4_dma_base4_re
- attribute \src "ls180.v:2032.12-2032.40"
- wire width 8 \builder_csrbank4_dma_base4_w
- attribute \src "ls180.v:2031.6-2031.35"
- wire \builder_csrbank4_dma_base4_we
- attribute \src "ls180.v:2026.12-2026.40"
- wire width 8 \builder_csrbank4_dma_base5_r
- attribute \src "ls180.v:2025.6-2025.35"
- wire \builder_csrbank4_dma_base5_re
- attribute \src "ls180.v:2028.12-2028.40"
- wire width 8 \builder_csrbank4_dma_base5_w
- attribute \src "ls180.v:2027.6-2027.35"
- wire \builder_csrbank4_dma_base5_we
- attribute \src "ls180.v:2022.12-2022.40"
- wire width 8 \builder_csrbank4_dma_base6_r
- attribute \src "ls180.v:2021.6-2021.35"
- wire \builder_csrbank4_dma_base6_re
- attribute \src "ls180.v:2024.12-2024.40"
- wire width 8 \builder_csrbank4_dma_base6_w
- attribute \src "ls180.v:2023.6-2023.35"
- wire \builder_csrbank4_dma_base6_we
- attribute \src "ls180.v:2018.12-2018.40"
- wire width 8 \builder_csrbank4_dma_base7_r
- attribute \src "ls180.v:2017.6-2017.35"
- wire \builder_csrbank4_dma_base7_re
- attribute \src "ls180.v:2020.12-2020.40"
- wire width 8 \builder_csrbank4_dma_base7_w
- attribute \src "ls180.v:2019.6-2019.35"
- wire \builder_csrbank4_dma_base7_we
- attribute \src "ls180.v:2070.6-2070.33"
- wire \builder_csrbank4_dma_done_r
- attribute \src "ls180.v:2069.6-2069.34"
- wire \builder_csrbank4_dma_done_re
- attribute \src "ls180.v:2072.6-2072.33"
- wire \builder_csrbank4_dma_done_w
- attribute \src "ls180.v:2071.6-2071.34"
- wire \builder_csrbank4_dma_done_we
- attribute \src "ls180.v:2066.6-2066.36"
- wire \builder_csrbank4_dma_enable0_r
- attribute \src "ls180.v:2065.6-2065.37"
- wire \builder_csrbank4_dma_enable0_re
- attribute \src "ls180.v:2068.6-2068.36"
- wire \builder_csrbank4_dma_enable0_w
- attribute \src "ls180.v:2067.6-2067.37"
- wire \builder_csrbank4_dma_enable0_we
- attribute \src "ls180.v:2062.12-2062.42"
- wire width 8 \builder_csrbank4_dma_length0_r
- attribute \src "ls180.v:2061.6-2061.37"
- wire \builder_csrbank4_dma_length0_re
- attribute \src "ls180.v:2064.12-2064.42"
- wire width 8 \builder_csrbank4_dma_length0_w
- attribute \src "ls180.v:2063.6-2063.37"
- wire \builder_csrbank4_dma_length0_we
- attribute \src "ls180.v:2058.12-2058.42"
- wire width 8 \builder_csrbank4_dma_length1_r
- attribute \src "ls180.v:2057.6-2057.37"
- wire \builder_csrbank4_dma_length1_re
- attribute \src "ls180.v:2060.12-2060.42"
- wire width 8 \builder_csrbank4_dma_length1_w
- attribute \src "ls180.v:2059.6-2059.37"
- wire \builder_csrbank4_dma_length1_we
- attribute \src "ls180.v:2054.12-2054.42"
- wire width 8 \builder_csrbank4_dma_length2_r
- attribute \src "ls180.v:2053.6-2053.37"
- wire \builder_csrbank4_dma_length2_re
- attribute \src "ls180.v:2056.12-2056.42"
- wire width 8 \builder_csrbank4_dma_length2_w
- attribute \src "ls180.v:2055.6-2055.37"
- wire \builder_csrbank4_dma_length2_we
- attribute \src "ls180.v:2050.12-2050.42"
- wire width 8 \builder_csrbank4_dma_length3_r
- attribute \src "ls180.v:2049.6-2049.37"
- wire \builder_csrbank4_dma_length3_re
- attribute \src "ls180.v:2052.12-2052.42"
- wire width 8 \builder_csrbank4_dma_length3_w
- attribute \src "ls180.v:2051.6-2051.37"
- wire \builder_csrbank4_dma_length3_we
- attribute \src "ls180.v:2074.6-2074.34"
- wire \builder_csrbank4_dma_loop0_r
- attribute \src "ls180.v:2073.6-2073.35"
- wire \builder_csrbank4_dma_loop0_re
- attribute \src "ls180.v:2076.6-2076.34"
- wire \builder_csrbank4_dma_loop0_w
- attribute \src "ls180.v:2075.6-2075.35"
- wire \builder_csrbank4_dma_loop0_we
- attribute \src "ls180.v:2077.6-2077.26"
+ attribute \src "ls180.v:2006.6-2006.32"
+ wire \builder_csrbank4_enable0_r
+ attribute \src "ls180.v:2005.6-2005.33"
+ wire \builder_csrbank4_enable0_re
+ attribute \src "ls180.v:2008.6-2008.32"
+ wire \builder_csrbank4_enable0_w
+ attribute \src "ls180.v:2007.6-2007.33"
+ wire \builder_csrbank4_enable0_we
+ attribute \src "ls180.v:2038.12-2038.38"
+ wire width 8 \builder_csrbank4_period0_r
+ attribute \src "ls180.v:2037.6-2037.33"
+ wire \builder_csrbank4_period0_re
+ attribute \src "ls180.v:2040.12-2040.38"
+ wire width 8 \builder_csrbank4_period0_w
+ attribute \src "ls180.v:2039.6-2039.33"
+ wire \builder_csrbank4_period0_we
+ attribute \src "ls180.v:2034.12-2034.38"
+ wire width 8 \builder_csrbank4_period1_r
+ attribute \src "ls180.v:2033.6-2033.33"
+ wire \builder_csrbank4_period1_re
+ attribute \src "ls180.v:2036.12-2036.38"
+ wire width 8 \builder_csrbank4_period1_w
+ attribute \src "ls180.v:2035.6-2035.33"
+ wire \builder_csrbank4_period1_we
+ attribute \src "ls180.v:2030.12-2030.38"
+ wire width 8 \builder_csrbank4_period2_r
+ attribute \src "ls180.v:2029.6-2029.33"
+ wire \builder_csrbank4_period2_re
+ attribute \src "ls180.v:2032.12-2032.38"
+ wire width 8 \builder_csrbank4_period2_w
+ attribute \src "ls180.v:2031.6-2031.33"
+ wire \builder_csrbank4_period2_we
+ attribute \src "ls180.v:2026.12-2026.38"
+ wire width 8 \builder_csrbank4_period3_r
+ attribute \src "ls180.v:2025.6-2025.33"
+ wire \builder_csrbank4_period3_re
+ attribute \src "ls180.v:2028.12-2028.38"
+ wire width 8 \builder_csrbank4_period3_w
+ attribute \src "ls180.v:2027.6-2027.33"
+ wire \builder_csrbank4_period3_we
+ attribute \src "ls180.v:2041.6-2041.26"
wire \builder_csrbank4_sel
- attribute \src "ls180.v:2207.12-2207.43"
- wire width 8 \builder_csrbank5_block_count0_r
- attribute \src "ls180.v:2206.6-2206.38"
- wire \builder_csrbank5_block_count0_re
- attribute \src "ls180.v:2209.12-2209.43"
- wire width 8 \builder_csrbank5_block_count0_w
- attribute \src "ls180.v:2208.6-2208.38"
- wire \builder_csrbank5_block_count0_we
- attribute \src "ls180.v:2203.12-2203.43"
- wire width 8 \builder_csrbank5_block_count1_r
- attribute \src "ls180.v:2202.6-2202.38"
- wire \builder_csrbank5_block_count1_re
- attribute \src "ls180.v:2205.12-2205.43"
- wire width 8 \builder_csrbank5_block_count1_w
- attribute \src "ls180.v:2204.6-2204.38"
- wire \builder_csrbank5_block_count1_we
- attribute \src "ls180.v:2199.12-2199.43"
- wire width 8 \builder_csrbank5_block_count2_r
- attribute \src "ls180.v:2198.6-2198.38"
- wire \builder_csrbank5_block_count2_re
- attribute \src "ls180.v:2201.12-2201.43"
- wire width 8 \builder_csrbank5_block_count2_w
- attribute \src "ls180.v:2200.6-2200.38"
- wire \builder_csrbank5_block_count2_we
- attribute \src "ls180.v:2195.12-2195.43"
- wire width 8 \builder_csrbank5_block_count3_r
- attribute \src "ls180.v:2194.6-2194.38"
- wire \builder_csrbank5_block_count3_re
- attribute \src "ls180.v:2197.12-2197.43"
- wire width 8 \builder_csrbank5_block_count3_w
- attribute \src "ls180.v:2196.6-2196.38"
- wire \builder_csrbank5_block_count3_we
- attribute \src "ls180.v:2191.12-2191.44"
- wire width 8 \builder_csrbank5_block_length0_r
- attribute \src "ls180.v:2190.6-2190.39"
- wire \builder_csrbank5_block_length0_re
- attribute \src "ls180.v:2193.12-2193.44"
- wire width 8 \builder_csrbank5_block_length0_w
- attribute \src "ls180.v:2192.6-2192.39"
- wire \builder_csrbank5_block_length0_we
- attribute \src "ls180.v:2187.12-2187.44"
- wire width 2 \builder_csrbank5_block_length1_r
- attribute \src "ls180.v:2186.6-2186.39"
- wire \builder_csrbank5_block_length1_re
- attribute \src "ls180.v:2189.12-2189.44"
- wire width 2 \builder_csrbank5_block_length1_w
- attribute \src "ls180.v:2188.6-2188.39"
- wire \builder_csrbank5_block_length1_we
- attribute \src "ls180.v:2095.12-2095.44"
- wire width 8 \builder_csrbank5_cmd_argument0_r
- attribute \src "ls180.v:2094.6-2094.39"
- wire \builder_csrbank5_cmd_argument0_re
- attribute \src "ls180.v:2097.12-2097.44"
- wire width 8 \builder_csrbank5_cmd_argument0_w
- attribute \src "ls180.v:2096.6-2096.39"
- wire \builder_csrbank5_cmd_argument0_we
- attribute \src "ls180.v:2091.12-2091.44"
- wire width 8 \builder_csrbank5_cmd_argument1_r
- attribute \src "ls180.v:2090.6-2090.39"
- wire \builder_csrbank5_cmd_argument1_re
- attribute \src "ls180.v:2093.12-2093.44"
- wire width 8 \builder_csrbank5_cmd_argument1_w
- attribute \src "ls180.v:2092.6-2092.39"
- wire \builder_csrbank5_cmd_argument1_we
- attribute \src "ls180.v:2087.12-2087.44"
- wire width 8 \builder_csrbank5_cmd_argument2_r
- attribute \src "ls180.v:2086.6-2086.39"
- wire \builder_csrbank5_cmd_argument2_re
- attribute \src "ls180.v:2089.12-2089.44"
- wire width 8 \builder_csrbank5_cmd_argument2_w
- attribute \src "ls180.v:2088.6-2088.39"
- wire \builder_csrbank5_cmd_argument2_we
- attribute \src "ls180.v:2083.12-2083.44"
- wire width 8 \builder_csrbank5_cmd_argument3_r
- attribute \src "ls180.v:2082.6-2082.39"
- wire \builder_csrbank5_cmd_argument3_re
- attribute \src "ls180.v:2085.12-2085.44"
- wire width 8 \builder_csrbank5_cmd_argument3_w
- attribute \src "ls180.v:2084.6-2084.39"
- wire \builder_csrbank5_cmd_argument3_we
- attribute \src "ls180.v:2111.12-2111.43"
- wire width 8 \builder_csrbank5_cmd_command0_r
- attribute \src "ls180.v:2110.6-2110.38"
- wire \builder_csrbank5_cmd_command0_re
- attribute \src "ls180.v:2113.12-2113.43"
- wire width 8 \builder_csrbank5_cmd_command0_w
- attribute \src "ls180.v:2112.6-2112.38"
- wire \builder_csrbank5_cmd_command0_we
- attribute \src "ls180.v:2107.12-2107.43"
- wire width 8 \builder_csrbank5_cmd_command1_r
- attribute \src "ls180.v:2106.6-2106.38"
- wire \builder_csrbank5_cmd_command1_re
- attribute \src "ls180.v:2109.12-2109.43"
- wire width 8 \builder_csrbank5_cmd_command1_w
- attribute \src "ls180.v:2108.6-2108.38"
- wire \builder_csrbank5_cmd_command1_we
- attribute \src "ls180.v:2103.12-2103.43"
- wire width 8 \builder_csrbank5_cmd_command2_r
- attribute \src "ls180.v:2102.6-2102.38"
- wire \builder_csrbank5_cmd_command2_re
- attribute \src "ls180.v:2105.12-2105.43"
- wire width 8 \builder_csrbank5_cmd_command2_w
- attribute \src "ls180.v:2104.6-2104.38"
- wire \builder_csrbank5_cmd_command2_we
- attribute \src "ls180.v:2099.12-2099.43"
- wire width 8 \builder_csrbank5_cmd_command3_r
- attribute \src "ls180.v:2098.6-2098.38"
- wire \builder_csrbank5_cmd_command3_re
- attribute \src "ls180.v:2101.12-2101.43"
- wire width 8 \builder_csrbank5_cmd_command3_w
- attribute \src "ls180.v:2100.6-2100.38"
- wire \builder_csrbank5_cmd_command3_we
- attribute \src "ls180.v:2179.12-2179.40"
- wire width 4 \builder_csrbank5_cmd_event_r
- attribute \src "ls180.v:2178.6-2178.35"
- wire \builder_csrbank5_cmd_event_re
- attribute \src "ls180.v:2181.12-2181.40"
- wire width 4 \builder_csrbank5_cmd_event_w
- attribute \src "ls180.v:2180.6-2180.35"
- wire \builder_csrbank5_cmd_event_we
- attribute \src "ls180.v:2175.12-2175.44"
- wire width 8 \builder_csrbank5_cmd_response0_r
- attribute \src "ls180.v:2174.6-2174.39"
- wire \builder_csrbank5_cmd_response0_re
- attribute \src "ls180.v:2177.12-2177.44"
- wire width 8 \builder_csrbank5_cmd_response0_w
- attribute \src "ls180.v:2176.6-2176.39"
- wire \builder_csrbank5_cmd_response0_we
- attribute \src "ls180.v:2135.12-2135.45"
- wire width 8 \builder_csrbank5_cmd_response10_r
- attribute \src "ls180.v:2134.6-2134.40"
- wire \builder_csrbank5_cmd_response10_re
- attribute \src "ls180.v:2137.12-2137.45"
- wire width 8 \builder_csrbank5_cmd_response10_w
- attribute \src "ls180.v:2136.6-2136.40"
- wire \builder_csrbank5_cmd_response10_we
- attribute \src "ls180.v:2131.12-2131.45"
- wire width 8 \builder_csrbank5_cmd_response11_r
- attribute \src "ls180.v:2130.6-2130.40"
- wire \builder_csrbank5_cmd_response11_re
- attribute \src "ls180.v:2133.12-2133.45"
- wire width 8 \builder_csrbank5_cmd_response11_w
- attribute \src "ls180.v:2132.6-2132.40"
- wire \builder_csrbank5_cmd_response11_we
- attribute \src "ls180.v:2127.12-2127.45"
- wire width 8 \builder_csrbank5_cmd_response12_r
- attribute \src "ls180.v:2126.6-2126.40"
- wire \builder_csrbank5_cmd_response12_re
- attribute \src "ls180.v:2129.12-2129.45"
- wire width 8 \builder_csrbank5_cmd_response12_w
- attribute \src "ls180.v:2128.6-2128.40"
- wire \builder_csrbank5_cmd_response12_we
- attribute \src "ls180.v:2123.12-2123.45"
- wire width 8 \builder_csrbank5_cmd_response13_r
- attribute \src "ls180.v:2122.6-2122.40"
- wire \builder_csrbank5_cmd_response13_re
- attribute \src "ls180.v:2125.12-2125.45"
- wire width 8 \builder_csrbank5_cmd_response13_w
- attribute \src "ls180.v:2124.6-2124.40"
- wire \builder_csrbank5_cmd_response13_we
- attribute \src "ls180.v:2119.12-2119.45"
- wire width 8 \builder_csrbank5_cmd_response14_r
- attribute \src "ls180.v:2118.6-2118.40"
- wire \builder_csrbank5_cmd_response14_re
- attribute \src "ls180.v:2121.12-2121.45"
- wire width 8 \builder_csrbank5_cmd_response14_w
- attribute \src "ls180.v:2120.6-2120.40"
- wire \builder_csrbank5_cmd_response14_we
- attribute \src "ls180.v:2115.12-2115.45"
- wire width 8 \builder_csrbank5_cmd_response15_r
- attribute \src "ls180.v:2114.6-2114.40"
- wire \builder_csrbank5_cmd_response15_re
- attribute \src "ls180.v:2117.12-2117.45"
- wire width 8 \builder_csrbank5_cmd_response15_w
- attribute \src "ls180.v:2116.6-2116.40"
- wire \builder_csrbank5_cmd_response15_we
- attribute \src "ls180.v:2171.12-2171.44"
- wire width 8 \builder_csrbank5_cmd_response1_r
- attribute \src "ls180.v:2170.6-2170.39"
- wire \builder_csrbank5_cmd_response1_re
- attribute \src "ls180.v:2173.12-2173.44"
- wire width 8 \builder_csrbank5_cmd_response1_w
- attribute \src "ls180.v:2172.6-2172.39"
- wire \builder_csrbank5_cmd_response1_we
- attribute \src "ls180.v:2167.12-2167.44"
- wire width 8 \builder_csrbank5_cmd_response2_r
- attribute \src "ls180.v:2166.6-2166.39"
- wire \builder_csrbank5_cmd_response2_re
- attribute \src "ls180.v:2169.12-2169.44"
- wire width 8 \builder_csrbank5_cmd_response2_w
- attribute \src "ls180.v:2168.6-2168.39"
- wire \builder_csrbank5_cmd_response2_we
- attribute \src "ls180.v:2163.12-2163.44"
- wire width 8 \builder_csrbank5_cmd_response3_r
- attribute \src "ls180.v:2162.6-2162.39"
- wire \builder_csrbank5_cmd_response3_re
- attribute \src "ls180.v:2165.12-2165.44"
- wire width 8 \builder_csrbank5_cmd_response3_w
- attribute \src "ls180.v:2164.6-2164.39"
- wire \builder_csrbank5_cmd_response3_we
- attribute \src "ls180.v:2159.12-2159.44"
- wire width 8 \builder_csrbank5_cmd_response4_r
- attribute \src "ls180.v:2158.6-2158.39"
- wire \builder_csrbank5_cmd_response4_re
- attribute \src "ls180.v:2161.12-2161.44"
- wire width 8 \builder_csrbank5_cmd_response4_w
- attribute \src "ls180.v:2160.6-2160.39"
- wire \builder_csrbank5_cmd_response4_we
- attribute \src "ls180.v:2155.12-2155.44"
- wire width 8 \builder_csrbank5_cmd_response5_r
- attribute \src "ls180.v:2154.6-2154.39"
- wire \builder_csrbank5_cmd_response5_re
- attribute \src "ls180.v:2157.12-2157.44"
- wire width 8 \builder_csrbank5_cmd_response5_w
- attribute \src "ls180.v:2156.6-2156.39"
- wire \builder_csrbank5_cmd_response5_we
- attribute \src "ls180.v:2151.12-2151.44"
- wire width 8 \builder_csrbank5_cmd_response6_r
- attribute \src "ls180.v:2150.6-2150.39"
- wire \builder_csrbank5_cmd_response6_re
- attribute \src "ls180.v:2153.12-2153.44"
- wire width 8 \builder_csrbank5_cmd_response6_w
- attribute \src "ls180.v:2152.6-2152.39"
- wire \builder_csrbank5_cmd_response6_we
- attribute \src "ls180.v:2147.12-2147.44"
- wire width 8 \builder_csrbank5_cmd_response7_r
- attribute \src "ls180.v:2146.6-2146.39"
- wire \builder_csrbank5_cmd_response7_re
- attribute \src "ls180.v:2149.12-2149.44"
- wire width 8 \builder_csrbank5_cmd_response7_w
- attribute \src "ls180.v:2148.6-2148.39"
- wire \builder_csrbank5_cmd_response7_we
- attribute \src "ls180.v:2143.12-2143.44"
- wire width 8 \builder_csrbank5_cmd_response8_r
- attribute \src "ls180.v:2142.6-2142.39"
- wire \builder_csrbank5_cmd_response8_re
- attribute \src "ls180.v:2145.12-2145.44"
- wire width 8 \builder_csrbank5_cmd_response8_w
- attribute \src "ls180.v:2144.6-2144.39"
- wire \builder_csrbank5_cmd_response8_we
- attribute \src "ls180.v:2139.12-2139.44"
- wire width 8 \builder_csrbank5_cmd_response9_r
- attribute \src "ls180.v:2138.6-2138.39"
- wire \builder_csrbank5_cmd_response9_re
- attribute \src "ls180.v:2141.12-2141.44"
- wire width 8 \builder_csrbank5_cmd_response9_w
- attribute \src "ls180.v:2140.6-2140.39"
- wire \builder_csrbank5_cmd_response9_we
- attribute \src "ls180.v:2183.12-2183.41"
- wire width 4 \builder_csrbank5_data_event_r
- attribute \src "ls180.v:2182.6-2182.36"
- wire \builder_csrbank5_data_event_re
- attribute \src "ls180.v:2185.12-2185.41"
- wire width 4 \builder_csrbank5_data_event_w
- attribute \src "ls180.v:2184.6-2184.36"
- wire \builder_csrbank5_data_event_we
- attribute \src "ls180.v:2210.6-2210.26"
+ attribute \src "ls180.v:2022.12-2022.37"
+ wire width 8 \builder_csrbank4_width0_r
+ attribute \src "ls180.v:2021.6-2021.32"
+ wire \builder_csrbank4_width0_re
+ attribute \src "ls180.v:2024.12-2024.37"
+ wire width 8 \builder_csrbank4_width0_w
+ attribute \src "ls180.v:2023.6-2023.32"
+ wire \builder_csrbank4_width0_we
+ attribute \src "ls180.v:2018.12-2018.37"
+ wire width 8 \builder_csrbank4_width1_r
+ attribute \src "ls180.v:2017.6-2017.32"
+ wire \builder_csrbank4_width1_re
+ attribute \src "ls180.v:2020.12-2020.37"
+ wire width 8 \builder_csrbank4_width1_w
+ attribute \src "ls180.v:2019.6-2019.32"
+ wire \builder_csrbank4_width1_we
+ attribute \src "ls180.v:2014.12-2014.37"
+ wire width 8 \builder_csrbank4_width2_r
+ attribute \src "ls180.v:2013.6-2013.32"
+ wire \builder_csrbank4_width2_re
+ attribute \src "ls180.v:2016.12-2016.37"
+ wire width 8 \builder_csrbank4_width2_w
+ attribute \src "ls180.v:2015.6-2015.32"
+ wire \builder_csrbank4_width2_we
+ attribute \src "ls180.v:2010.12-2010.37"
+ wire width 8 \builder_csrbank4_width3_r
+ attribute \src "ls180.v:2009.6-2009.32"
+ wire \builder_csrbank4_width3_re
+ attribute \src "ls180.v:2012.12-2012.37"
+ wire width 8 \builder_csrbank4_width3_w
+ attribute \src "ls180.v:2011.6-2011.32"
+ wire \builder_csrbank4_width3_we
+ attribute \src "ls180.v:2075.12-2075.40"
+ wire width 8 \builder_csrbank5_dma_base0_r
+ attribute \src "ls180.v:2074.6-2074.35"
+ wire \builder_csrbank5_dma_base0_re
+ attribute \src "ls180.v:2077.12-2077.40"
+ wire width 8 \builder_csrbank5_dma_base0_w
+ attribute \src "ls180.v:2076.6-2076.35"
+ wire \builder_csrbank5_dma_base0_we
+ attribute \src "ls180.v:2071.12-2071.40"
+ wire width 8 \builder_csrbank5_dma_base1_r
+ attribute \src "ls180.v:2070.6-2070.35"
+ wire \builder_csrbank5_dma_base1_re
+ attribute \src "ls180.v:2073.12-2073.40"
+ wire width 8 \builder_csrbank5_dma_base1_w
+ attribute \src "ls180.v:2072.6-2072.35"
+ wire \builder_csrbank5_dma_base1_we
+ attribute \src "ls180.v:2067.12-2067.40"
+ wire width 8 \builder_csrbank5_dma_base2_r
+ attribute \src "ls180.v:2066.6-2066.35"
+ wire \builder_csrbank5_dma_base2_re
+ attribute \src "ls180.v:2069.12-2069.40"
+ wire width 8 \builder_csrbank5_dma_base2_w
+ attribute \src "ls180.v:2068.6-2068.35"
+ wire \builder_csrbank5_dma_base2_we
+ attribute \src "ls180.v:2063.12-2063.40"
+ wire width 8 \builder_csrbank5_dma_base3_r
+ attribute \src "ls180.v:2062.6-2062.35"
+ wire \builder_csrbank5_dma_base3_re
+ attribute \src "ls180.v:2065.12-2065.40"
+ wire width 8 \builder_csrbank5_dma_base3_w
+ attribute \src "ls180.v:2064.6-2064.35"
+ wire \builder_csrbank5_dma_base3_we
+ attribute \src "ls180.v:2059.12-2059.40"
+ wire width 8 \builder_csrbank5_dma_base4_r
+ attribute \src "ls180.v:2058.6-2058.35"
+ wire \builder_csrbank5_dma_base4_re
+ attribute \src "ls180.v:2061.12-2061.40"
+ wire width 8 \builder_csrbank5_dma_base4_w
+ attribute \src "ls180.v:2060.6-2060.35"
+ wire \builder_csrbank5_dma_base4_we
+ attribute \src "ls180.v:2055.12-2055.40"
+ wire width 8 \builder_csrbank5_dma_base5_r
+ attribute \src "ls180.v:2054.6-2054.35"
+ wire \builder_csrbank5_dma_base5_re
+ attribute \src "ls180.v:2057.12-2057.40"
+ wire width 8 \builder_csrbank5_dma_base5_w
+ attribute \src "ls180.v:2056.6-2056.35"
+ wire \builder_csrbank5_dma_base5_we
+ attribute \src "ls180.v:2051.12-2051.40"
+ wire width 8 \builder_csrbank5_dma_base6_r
+ attribute \src "ls180.v:2050.6-2050.35"
+ wire \builder_csrbank5_dma_base6_re
+ attribute \src "ls180.v:2053.12-2053.40"
+ wire width 8 \builder_csrbank5_dma_base6_w
+ attribute \src "ls180.v:2052.6-2052.35"
+ wire \builder_csrbank5_dma_base6_we
+ attribute \src "ls180.v:2047.12-2047.40"
+ wire width 8 \builder_csrbank5_dma_base7_r
+ attribute \src "ls180.v:2046.6-2046.35"
+ wire \builder_csrbank5_dma_base7_re
+ attribute \src "ls180.v:2049.12-2049.40"
+ wire width 8 \builder_csrbank5_dma_base7_w
+ attribute \src "ls180.v:2048.6-2048.35"
+ wire \builder_csrbank5_dma_base7_we
+ attribute \src "ls180.v:2099.6-2099.33"
+ wire \builder_csrbank5_dma_done_r
+ attribute \src "ls180.v:2098.6-2098.34"
+ wire \builder_csrbank5_dma_done_re
+ attribute \src "ls180.v:2101.6-2101.33"
+ wire \builder_csrbank5_dma_done_w
+ attribute \src "ls180.v:2100.6-2100.34"
+ wire \builder_csrbank5_dma_done_we
+ attribute \src "ls180.v:2095.6-2095.36"
+ wire \builder_csrbank5_dma_enable0_r
+ attribute \src "ls180.v:2094.6-2094.37"
+ wire \builder_csrbank5_dma_enable0_re
+ attribute \src "ls180.v:2097.6-2097.36"
+ wire \builder_csrbank5_dma_enable0_w
+ attribute \src "ls180.v:2096.6-2096.37"
+ wire \builder_csrbank5_dma_enable0_we
+ attribute \src "ls180.v:2091.12-2091.42"
+ wire width 8 \builder_csrbank5_dma_length0_r
+ attribute \src "ls180.v:2090.6-2090.37"
+ wire \builder_csrbank5_dma_length0_re
+ attribute \src "ls180.v:2093.12-2093.42"
+ wire width 8 \builder_csrbank5_dma_length0_w
+ attribute \src "ls180.v:2092.6-2092.37"
+ wire \builder_csrbank5_dma_length0_we
+ attribute \src "ls180.v:2087.12-2087.42"
+ wire width 8 \builder_csrbank5_dma_length1_r
+ attribute \src "ls180.v:2086.6-2086.37"
+ wire \builder_csrbank5_dma_length1_re
+ attribute \src "ls180.v:2089.12-2089.42"
+ wire width 8 \builder_csrbank5_dma_length1_w
+ attribute \src "ls180.v:2088.6-2088.37"
+ wire \builder_csrbank5_dma_length1_we
+ attribute \src "ls180.v:2083.12-2083.42"
+ wire width 8 \builder_csrbank5_dma_length2_r
+ attribute \src "ls180.v:2082.6-2082.37"
+ wire \builder_csrbank5_dma_length2_re
+ attribute \src "ls180.v:2085.12-2085.42"
+ wire width 8 \builder_csrbank5_dma_length2_w
+ attribute \src "ls180.v:2084.6-2084.37"
+ wire \builder_csrbank5_dma_length2_we
+ attribute \src "ls180.v:2079.12-2079.42"
+ wire width 8 \builder_csrbank5_dma_length3_r
+ attribute \src "ls180.v:2078.6-2078.37"
+ wire \builder_csrbank5_dma_length3_re
+ attribute \src "ls180.v:2081.12-2081.42"
+ wire width 8 \builder_csrbank5_dma_length3_w
+ attribute \src "ls180.v:2080.6-2080.37"
+ wire \builder_csrbank5_dma_length3_we
+ attribute \src "ls180.v:2103.6-2103.34"
+ wire \builder_csrbank5_dma_loop0_r
+ attribute \src "ls180.v:2102.6-2102.35"
+ wire \builder_csrbank5_dma_loop0_re
+ attribute \src "ls180.v:2105.6-2105.34"
+ wire \builder_csrbank5_dma_loop0_w
+ attribute \src "ls180.v:2104.6-2104.35"
+ wire \builder_csrbank5_dma_loop0_we
+ attribute \src "ls180.v:2106.6-2106.26"
wire \builder_csrbank5_sel
- attribute \src "ls180.v:2244.12-2244.40"
- wire width 8 \builder_csrbank6_dma_base0_r
- attribute \src "ls180.v:2243.6-2243.35"
- wire \builder_csrbank6_dma_base0_re
- attribute \src "ls180.v:2246.12-2246.40"
- wire width 8 \builder_csrbank6_dma_base0_w
- attribute \src "ls180.v:2245.6-2245.35"
- wire \builder_csrbank6_dma_base0_we
- attribute \src "ls180.v:2240.12-2240.40"
- wire width 8 \builder_csrbank6_dma_base1_r
- attribute \src "ls180.v:2239.6-2239.35"
- wire \builder_csrbank6_dma_base1_re
- attribute \src "ls180.v:2242.12-2242.40"
- wire width 8 \builder_csrbank6_dma_base1_w
- attribute \src "ls180.v:2241.6-2241.35"
- wire \builder_csrbank6_dma_base1_we
- attribute \src "ls180.v:2236.12-2236.40"
- wire width 8 \builder_csrbank6_dma_base2_r
- attribute \src "ls180.v:2235.6-2235.35"
- wire \builder_csrbank6_dma_base2_re
- attribute \src "ls180.v:2238.12-2238.40"
- wire width 8 \builder_csrbank6_dma_base2_w
- attribute \src "ls180.v:2237.6-2237.35"
- wire \builder_csrbank6_dma_base2_we
- attribute \src "ls180.v:2232.12-2232.40"
- wire width 8 \builder_csrbank6_dma_base3_r
- attribute \src "ls180.v:2231.6-2231.35"
- wire \builder_csrbank6_dma_base3_re
- attribute \src "ls180.v:2234.12-2234.40"
- wire width 8 \builder_csrbank6_dma_base3_w
- attribute \src "ls180.v:2233.6-2233.35"
- wire \builder_csrbank6_dma_base3_we
- attribute \src "ls180.v:2228.12-2228.40"
- wire width 8 \builder_csrbank6_dma_base4_r
- attribute \src "ls180.v:2227.6-2227.35"
- wire \builder_csrbank6_dma_base4_re
- attribute \src "ls180.v:2230.12-2230.40"
- wire width 8 \builder_csrbank6_dma_base4_w
- attribute \src "ls180.v:2229.6-2229.35"
- wire \builder_csrbank6_dma_base4_we
- attribute \src "ls180.v:2224.12-2224.40"
- wire width 8 \builder_csrbank6_dma_base5_r
- attribute \src "ls180.v:2223.6-2223.35"
- wire \builder_csrbank6_dma_base5_re
- attribute \src "ls180.v:2226.12-2226.40"
- wire width 8 \builder_csrbank6_dma_base5_w
- attribute \src "ls180.v:2225.6-2225.35"
- wire \builder_csrbank6_dma_base5_we
- attribute \src "ls180.v:2220.12-2220.40"
- wire width 8 \builder_csrbank6_dma_base6_r
- attribute \src "ls180.v:2219.6-2219.35"
- wire \builder_csrbank6_dma_base6_re
- attribute \src "ls180.v:2222.12-2222.40"
- wire width 8 \builder_csrbank6_dma_base6_w
- attribute \src "ls180.v:2221.6-2221.35"
- wire \builder_csrbank6_dma_base6_we
- attribute \src "ls180.v:2216.12-2216.40"
- wire width 8 \builder_csrbank6_dma_base7_r
- attribute \src "ls180.v:2215.6-2215.35"
- wire \builder_csrbank6_dma_base7_re
- attribute \src "ls180.v:2218.12-2218.40"
- wire width 8 \builder_csrbank6_dma_base7_w
- attribute \src "ls180.v:2217.6-2217.35"
- wire \builder_csrbank6_dma_base7_we
- attribute \src "ls180.v:2268.6-2268.33"
- wire \builder_csrbank6_dma_done_r
- attribute \src "ls180.v:2267.6-2267.34"
- wire \builder_csrbank6_dma_done_re
- attribute \src "ls180.v:2270.6-2270.33"
- wire \builder_csrbank6_dma_done_w
- attribute \src "ls180.v:2269.6-2269.34"
- wire \builder_csrbank6_dma_done_we
- attribute \src "ls180.v:2264.6-2264.36"
- wire \builder_csrbank6_dma_enable0_r
- attribute \src "ls180.v:2263.6-2263.37"
- wire \builder_csrbank6_dma_enable0_re
- attribute \src "ls180.v:2266.6-2266.36"
- wire \builder_csrbank6_dma_enable0_w
- attribute \src "ls180.v:2265.6-2265.37"
- wire \builder_csrbank6_dma_enable0_we
- attribute \src "ls180.v:2260.12-2260.42"
- wire width 8 \builder_csrbank6_dma_length0_r
- attribute \src "ls180.v:2259.6-2259.37"
- wire \builder_csrbank6_dma_length0_re
- attribute \src "ls180.v:2262.12-2262.42"
- wire width 8 \builder_csrbank6_dma_length0_w
- attribute \src "ls180.v:2261.6-2261.37"
- wire \builder_csrbank6_dma_length0_we
- attribute \src "ls180.v:2256.12-2256.42"
- wire width 8 \builder_csrbank6_dma_length1_r
- attribute \src "ls180.v:2255.6-2255.37"
- wire \builder_csrbank6_dma_length1_re
- attribute \src "ls180.v:2258.12-2258.42"
- wire width 8 \builder_csrbank6_dma_length1_w
- attribute \src "ls180.v:2257.6-2257.37"
- wire \builder_csrbank6_dma_length1_we
- attribute \src "ls180.v:2252.12-2252.42"
- wire width 8 \builder_csrbank6_dma_length2_r
- attribute \src "ls180.v:2251.6-2251.37"
- wire \builder_csrbank6_dma_length2_re
- attribute \src "ls180.v:2254.12-2254.42"
- wire width 8 \builder_csrbank6_dma_length2_w
- attribute \src "ls180.v:2253.6-2253.37"
- wire \builder_csrbank6_dma_length2_we
- attribute \src "ls180.v:2248.12-2248.42"
- wire width 8 \builder_csrbank6_dma_length3_r
- attribute \src "ls180.v:2247.6-2247.37"
- wire \builder_csrbank6_dma_length3_re
- attribute \src "ls180.v:2250.12-2250.42"
- wire width 8 \builder_csrbank6_dma_length3_w
- attribute \src "ls180.v:2249.6-2249.37"
- wire \builder_csrbank6_dma_length3_we
- attribute \src "ls180.v:2272.6-2272.34"
- wire \builder_csrbank6_dma_loop0_r
- attribute \src "ls180.v:2271.6-2271.35"
- wire \builder_csrbank6_dma_loop0_re
- attribute \src "ls180.v:2274.6-2274.34"
- wire \builder_csrbank6_dma_loop0_w
- attribute \src "ls180.v:2273.6-2273.35"
- wire \builder_csrbank6_dma_loop0_we
- attribute \src "ls180.v:2288.12-2288.42"
- wire width 8 \builder_csrbank6_dma_offset0_r
- attribute \src "ls180.v:2287.6-2287.37"
- wire \builder_csrbank6_dma_offset0_re
- attribute \src "ls180.v:2290.12-2290.42"
- wire width 8 \builder_csrbank6_dma_offset0_w
- attribute \src "ls180.v:2289.6-2289.37"
- wire \builder_csrbank6_dma_offset0_we
- attribute \src "ls180.v:2284.12-2284.42"
- wire width 8 \builder_csrbank6_dma_offset1_r
- attribute \src "ls180.v:2283.6-2283.37"
- wire \builder_csrbank6_dma_offset1_re
- attribute \src "ls180.v:2286.12-2286.42"
- wire width 8 \builder_csrbank6_dma_offset1_w
- attribute \src "ls180.v:2285.6-2285.37"
- wire \builder_csrbank6_dma_offset1_we
- attribute \src "ls180.v:2280.12-2280.42"
- wire width 8 \builder_csrbank6_dma_offset2_r
- attribute \src "ls180.v:2279.6-2279.37"
- wire \builder_csrbank6_dma_offset2_re
- attribute \src "ls180.v:2282.12-2282.42"
- wire width 8 \builder_csrbank6_dma_offset2_w
- attribute \src "ls180.v:2281.6-2281.37"
- wire \builder_csrbank6_dma_offset2_we
- attribute \src "ls180.v:2276.12-2276.42"
- wire width 8 \builder_csrbank6_dma_offset3_r
- attribute \src "ls180.v:2275.6-2275.37"
- wire \builder_csrbank6_dma_offset3_re
- attribute \src "ls180.v:2278.12-2278.42"
- wire width 8 \builder_csrbank6_dma_offset3_w
- attribute \src "ls180.v:2277.6-2277.37"
- wire \builder_csrbank6_dma_offset3_we
- attribute \src "ls180.v:2291.6-2291.26"
+ attribute \src "ls180.v:2236.12-2236.43"
+ wire width 8 \builder_csrbank6_block_count0_r
+ attribute \src "ls180.v:2235.6-2235.38"
+ wire \builder_csrbank6_block_count0_re
+ attribute \src "ls180.v:2238.12-2238.43"
+ wire width 8 \builder_csrbank6_block_count0_w
+ attribute \src "ls180.v:2237.6-2237.38"
+ wire \builder_csrbank6_block_count0_we
+ attribute \src "ls180.v:2232.12-2232.43"
+ wire width 8 \builder_csrbank6_block_count1_r
+ attribute \src "ls180.v:2231.6-2231.38"
+ wire \builder_csrbank6_block_count1_re
+ attribute \src "ls180.v:2234.12-2234.43"
+ wire width 8 \builder_csrbank6_block_count1_w
+ attribute \src "ls180.v:2233.6-2233.38"
+ wire \builder_csrbank6_block_count1_we
+ attribute \src "ls180.v:2228.12-2228.43"
+ wire width 8 \builder_csrbank6_block_count2_r
+ attribute \src "ls180.v:2227.6-2227.38"
+ wire \builder_csrbank6_block_count2_re
+ attribute \src "ls180.v:2230.12-2230.43"
+ wire width 8 \builder_csrbank6_block_count2_w
+ attribute \src "ls180.v:2229.6-2229.38"
+ wire \builder_csrbank6_block_count2_we
+ attribute \src "ls180.v:2224.12-2224.43"
+ wire width 8 \builder_csrbank6_block_count3_r
+ attribute \src "ls180.v:2223.6-2223.38"
+ wire \builder_csrbank6_block_count3_re
+ attribute \src "ls180.v:2226.12-2226.43"
+ wire width 8 \builder_csrbank6_block_count3_w
+ attribute \src "ls180.v:2225.6-2225.38"
+ wire \builder_csrbank6_block_count3_we
+ attribute \src "ls180.v:2220.12-2220.44"
+ wire width 8 \builder_csrbank6_block_length0_r
+ attribute \src "ls180.v:2219.6-2219.39"
+ wire \builder_csrbank6_block_length0_re
+ attribute \src "ls180.v:2222.12-2222.44"
+ wire width 8 \builder_csrbank6_block_length0_w
+ attribute \src "ls180.v:2221.6-2221.39"
+ wire \builder_csrbank6_block_length0_we
+ attribute \src "ls180.v:2216.12-2216.44"
+ wire width 2 \builder_csrbank6_block_length1_r
+ attribute \src "ls180.v:2215.6-2215.39"
+ wire \builder_csrbank6_block_length1_re
+ attribute \src "ls180.v:2218.12-2218.44"
+ wire width 2 \builder_csrbank6_block_length1_w
+ attribute \src "ls180.v:2217.6-2217.39"
+ wire \builder_csrbank6_block_length1_we
+ attribute \src "ls180.v:2124.12-2124.44"
+ wire width 8 \builder_csrbank6_cmd_argument0_r
+ attribute \src "ls180.v:2123.6-2123.39"
+ wire \builder_csrbank6_cmd_argument0_re
+ attribute \src "ls180.v:2126.12-2126.44"
+ wire width 8 \builder_csrbank6_cmd_argument0_w
+ attribute \src "ls180.v:2125.6-2125.39"
+ wire \builder_csrbank6_cmd_argument0_we
+ attribute \src "ls180.v:2120.12-2120.44"
+ wire width 8 \builder_csrbank6_cmd_argument1_r
+ attribute \src "ls180.v:2119.6-2119.39"
+ wire \builder_csrbank6_cmd_argument1_re
+ attribute \src "ls180.v:2122.12-2122.44"
+ wire width 8 \builder_csrbank6_cmd_argument1_w
+ attribute \src "ls180.v:2121.6-2121.39"
+ wire \builder_csrbank6_cmd_argument1_we
+ attribute \src "ls180.v:2116.12-2116.44"
+ wire width 8 \builder_csrbank6_cmd_argument2_r
+ attribute \src "ls180.v:2115.6-2115.39"
+ wire \builder_csrbank6_cmd_argument2_re
+ attribute \src "ls180.v:2118.12-2118.44"
+ wire width 8 \builder_csrbank6_cmd_argument2_w
+ attribute \src "ls180.v:2117.6-2117.39"
+ wire \builder_csrbank6_cmd_argument2_we
+ attribute \src "ls180.v:2112.12-2112.44"
+ wire width 8 \builder_csrbank6_cmd_argument3_r
+ attribute \src "ls180.v:2111.6-2111.39"
+ wire \builder_csrbank6_cmd_argument3_re
+ attribute \src "ls180.v:2114.12-2114.44"
+ wire width 8 \builder_csrbank6_cmd_argument3_w
+ attribute \src "ls180.v:2113.6-2113.39"
+ wire \builder_csrbank6_cmd_argument3_we
+ attribute \src "ls180.v:2140.12-2140.43"
+ wire width 8 \builder_csrbank6_cmd_command0_r
+ attribute \src "ls180.v:2139.6-2139.38"
+ wire \builder_csrbank6_cmd_command0_re
+ attribute \src "ls180.v:2142.12-2142.43"
+ wire width 8 \builder_csrbank6_cmd_command0_w
+ attribute \src "ls180.v:2141.6-2141.38"
+ wire \builder_csrbank6_cmd_command0_we
+ attribute \src "ls180.v:2136.12-2136.43"
+ wire width 8 \builder_csrbank6_cmd_command1_r
+ attribute \src "ls180.v:2135.6-2135.38"
+ wire \builder_csrbank6_cmd_command1_re
+ attribute \src "ls180.v:2138.12-2138.43"
+ wire width 8 \builder_csrbank6_cmd_command1_w
+ attribute \src "ls180.v:2137.6-2137.38"
+ wire \builder_csrbank6_cmd_command1_we
+ attribute \src "ls180.v:2132.12-2132.43"
+ wire width 8 \builder_csrbank6_cmd_command2_r
+ attribute \src "ls180.v:2131.6-2131.38"
+ wire \builder_csrbank6_cmd_command2_re
+ attribute \src "ls180.v:2134.12-2134.43"
+ wire width 8 \builder_csrbank6_cmd_command2_w
+ attribute \src "ls180.v:2133.6-2133.38"
+ wire \builder_csrbank6_cmd_command2_we
+ attribute \src "ls180.v:2128.12-2128.43"
+ wire width 8 \builder_csrbank6_cmd_command3_r
+ attribute \src "ls180.v:2127.6-2127.38"
+ wire \builder_csrbank6_cmd_command3_re
+ attribute \src "ls180.v:2130.12-2130.43"
+ wire width 8 \builder_csrbank6_cmd_command3_w
+ attribute \src "ls180.v:2129.6-2129.38"
+ wire \builder_csrbank6_cmd_command3_we
+ attribute \src "ls180.v:2208.12-2208.40"
+ wire width 4 \builder_csrbank6_cmd_event_r
+ attribute \src "ls180.v:2207.6-2207.35"
+ wire \builder_csrbank6_cmd_event_re
+ attribute \src "ls180.v:2210.12-2210.40"
+ wire width 4 \builder_csrbank6_cmd_event_w
+ attribute \src "ls180.v:2209.6-2209.35"
+ wire \builder_csrbank6_cmd_event_we
+ attribute \src "ls180.v:2204.12-2204.44"
+ wire width 8 \builder_csrbank6_cmd_response0_r
+ attribute \src "ls180.v:2203.6-2203.39"
+ wire \builder_csrbank6_cmd_response0_re
+ attribute \src "ls180.v:2206.12-2206.44"
+ wire width 8 \builder_csrbank6_cmd_response0_w
+ attribute \src "ls180.v:2205.6-2205.39"
+ wire \builder_csrbank6_cmd_response0_we
+ attribute \src "ls180.v:2164.12-2164.45"
+ wire width 8 \builder_csrbank6_cmd_response10_r
+ attribute \src "ls180.v:2163.6-2163.40"
+ wire \builder_csrbank6_cmd_response10_re
+ attribute \src "ls180.v:2166.12-2166.45"
+ wire width 8 \builder_csrbank6_cmd_response10_w
+ attribute \src "ls180.v:2165.6-2165.40"
+ wire \builder_csrbank6_cmd_response10_we
+ attribute \src "ls180.v:2160.12-2160.45"
+ wire width 8 \builder_csrbank6_cmd_response11_r
+ attribute \src "ls180.v:2159.6-2159.40"
+ wire \builder_csrbank6_cmd_response11_re
+ attribute \src "ls180.v:2162.12-2162.45"
+ wire width 8 \builder_csrbank6_cmd_response11_w
+ attribute \src "ls180.v:2161.6-2161.40"
+ wire \builder_csrbank6_cmd_response11_we
+ attribute \src "ls180.v:2156.12-2156.45"
+ wire width 8 \builder_csrbank6_cmd_response12_r
+ attribute \src "ls180.v:2155.6-2155.40"
+ wire \builder_csrbank6_cmd_response12_re
+ attribute \src "ls180.v:2158.12-2158.45"
+ wire width 8 \builder_csrbank6_cmd_response12_w
+ attribute \src "ls180.v:2157.6-2157.40"
+ wire \builder_csrbank6_cmd_response12_we
+ attribute \src "ls180.v:2152.12-2152.45"
+ wire width 8 \builder_csrbank6_cmd_response13_r
+ attribute \src "ls180.v:2151.6-2151.40"
+ wire \builder_csrbank6_cmd_response13_re
+ attribute \src "ls180.v:2154.12-2154.45"
+ wire width 8 \builder_csrbank6_cmd_response13_w
+ attribute \src "ls180.v:2153.6-2153.40"
+ wire \builder_csrbank6_cmd_response13_we
+ attribute \src "ls180.v:2148.12-2148.45"
+ wire width 8 \builder_csrbank6_cmd_response14_r
+ attribute \src "ls180.v:2147.6-2147.40"
+ wire \builder_csrbank6_cmd_response14_re
+ attribute \src "ls180.v:2150.12-2150.45"
+ wire width 8 \builder_csrbank6_cmd_response14_w
+ attribute \src "ls180.v:2149.6-2149.40"
+ wire \builder_csrbank6_cmd_response14_we
+ attribute \src "ls180.v:2144.12-2144.45"
+ wire width 8 \builder_csrbank6_cmd_response15_r
+ attribute \src "ls180.v:2143.6-2143.40"
+ wire \builder_csrbank6_cmd_response15_re
+ attribute \src "ls180.v:2146.12-2146.45"
+ wire width 8 \builder_csrbank6_cmd_response15_w
+ attribute \src "ls180.v:2145.6-2145.40"
+ wire \builder_csrbank6_cmd_response15_we
+ attribute \src "ls180.v:2200.12-2200.44"
+ wire width 8 \builder_csrbank6_cmd_response1_r
+ attribute \src "ls180.v:2199.6-2199.39"
+ wire \builder_csrbank6_cmd_response1_re
+ attribute \src "ls180.v:2202.12-2202.44"
+ wire width 8 \builder_csrbank6_cmd_response1_w
+ attribute \src "ls180.v:2201.6-2201.39"
+ wire \builder_csrbank6_cmd_response1_we
+ attribute \src "ls180.v:2196.12-2196.44"
+ wire width 8 \builder_csrbank6_cmd_response2_r
+ attribute \src "ls180.v:2195.6-2195.39"
+ wire \builder_csrbank6_cmd_response2_re
+ attribute \src "ls180.v:2198.12-2198.44"
+ wire width 8 \builder_csrbank6_cmd_response2_w
+ attribute \src "ls180.v:2197.6-2197.39"
+ wire \builder_csrbank6_cmd_response2_we
+ attribute \src "ls180.v:2192.12-2192.44"
+ wire width 8 \builder_csrbank6_cmd_response3_r
+ attribute \src "ls180.v:2191.6-2191.39"
+ wire \builder_csrbank6_cmd_response3_re
+ attribute \src "ls180.v:2194.12-2194.44"
+ wire width 8 \builder_csrbank6_cmd_response3_w
+ attribute \src "ls180.v:2193.6-2193.39"
+ wire \builder_csrbank6_cmd_response3_we
+ attribute \src "ls180.v:2188.12-2188.44"
+ wire width 8 \builder_csrbank6_cmd_response4_r
+ attribute \src "ls180.v:2187.6-2187.39"
+ wire \builder_csrbank6_cmd_response4_re
+ attribute \src "ls180.v:2190.12-2190.44"
+ wire width 8 \builder_csrbank6_cmd_response4_w
+ attribute \src "ls180.v:2189.6-2189.39"
+ wire \builder_csrbank6_cmd_response4_we
+ attribute \src "ls180.v:2184.12-2184.44"
+ wire width 8 \builder_csrbank6_cmd_response5_r
+ attribute \src "ls180.v:2183.6-2183.39"
+ wire \builder_csrbank6_cmd_response5_re
+ attribute \src "ls180.v:2186.12-2186.44"
+ wire width 8 \builder_csrbank6_cmd_response5_w
+ attribute \src "ls180.v:2185.6-2185.39"
+ wire \builder_csrbank6_cmd_response5_we
+ attribute \src "ls180.v:2180.12-2180.44"
+ wire width 8 \builder_csrbank6_cmd_response6_r
+ attribute \src "ls180.v:2179.6-2179.39"
+ wire \builder_csrbank6_cmd_response6_re
+ attribute \src "ls180.v:2182.12-2182.44"
+ wire width 8 \builder_csrbank6_cmd_response6_w
+ attribute \src "ls180.v:2181.6-2181.39"
+ wire \builder_csrbank6_cmd_response6_we
+ attribute \src "ls180.v:2176.12-2176.44"
+ wire width 8 \builder_csrbank6_cmd_response7_r
+ attribute \src "ls180.v:2175.6-2175.39"
+ wire \builder_csrbank6_cmd_response7_re
+ attribute \src "ls180.v:2178.12-2178.44"
+ wire width 8 \builder_csrbank6_cmd_response7_w
+ attribute \src "ls180.v:2177.6-2177.39"
+ wire \builder_csrbank6_cmd_response7_we
+ attribute \src "ls180.v:2172.12-2172.44"
+ wire width 8 \builder_csrbank6_cmd_response8_r
+ attribute \src "ls180.v:2171.6-2171.39"
+ wire \builder_csrbank6_cmd_response8_re
+ attribute \src "ls180.v:2174.12-2174.44"
+ wire width 8 \builder_csrbank6_cmd_response8_w
+ attribute \src "ls180.v:2173.6-2173.39"
+ wire \builder_csrbank6_cmd_response8_we
+ attribute \src "ls180.v:2168.12-2168.44"
+ wire width 8 \builder_csrbank6_cmd_response9_r
+ attribute \src "ls180.v:2167.6-2167.39"
+ wire \builder_csrbank6_cmd_response9_re
+ attribute \src "ls180.v:2170.12-2170.44"
+ wire width 8 \builder_csrbank6_cmd_response9_w
+ attribute \src "ls180.v:2169.6-2169.39"
+ wire \builder_csrbank6_cmd_response9_we
+ attribute \src "ls180.v:2212.12-2212.41"
+ wire width 4 \builder_csrbank6_data_event_r
+ attribute \src "ls180.v:2211.6-2211.36"
+ wire \builder_csrbank6_data_event_re
+ attribute \src "ls180.v:2214.12-2214.41"
+ wire width 4 \builder_csrbank6_data_event_w
+ attribute \src "ls180.v:2213.6-2213.36"
+ wire \builder_csrbank6_data_event_we
+ attribute \src "ls180.v:2239.6-2239.26"
wire \builder_csrbank6_sel
- attribute \src "ls180.v:2297.6-2297.36"
- wire \builder_csrbank7_card_detect_r
- attribute \src "ls180.v:2296.6-2296.37"
- wire \builder_csrbank7_card_detect_re
- attribute \src "ls180.v:2299.6-2299.36"
- wire \builder_csrbank7_card_detect_w
- attribute \src "ls180.v:2298.6-2298.37"
- wire \builder_csrbank7_card_detect_we
- attribute \src "ls180.v:2305.12-2305.47"
- wire width 8 \builder_csrbank7_clocker_divider0_r
- attribute \src "ls180.v:2304.6-2304.42"
- wire \builder_csrbank7_clocker_divider0_re
- attribute \src "ls180.v:2307.12-2307.47"
- wire width 8 \builder_csrbank7_clocker_divider0_w
- attribute \src "ls180.v:2306.6-2306.42"
- wire \builder_csrbank7_clocker_divider0_we
- attribute \src "ls180.v:2301.6-2301.41"
- wire \builder_csrbank7_clocker_divider1_r
- attribute \src "ls180.v:2300.6-2300.42"
- wire \builder_csrbank7_clocker_divider1_re
- attribute \src "ls180.v:2303.6-2303.41"
- wire \builder_csrbank7_clocker_divider1_w
- attribute \src "ls180.v:2302.6-2302.42"
- wire \builder_csrbank7_clocker_divider1_we
- attribute \src "ls180.v:2308.6-2308.26"
+ attribute \src "ls180.v:2273.12-2273.40"
+ wire width 8 \builder_csrbank7_dma_base0_r
+ attribute \src "ls180.v:2272.6-2272.35"
+ wire \builder_csrbank7_dma_base0_re
+ attribute \src "ls180.v:2275.12-2275.40"
+ wire width 8 \builder_csrbank7_dma_base0_w
+ attribute \src "ls180.v:2274.6-2274.35"
+ wire \builder_csrbank7_dma_base0_we
+ attribute \src "ls180.v:2269.12-2269.40"
+ wire width 8 \builder_csrbank7_dma_base1_r
+ attribute \src "ls180.v:2268.6-2268.35"
+ wire \builder_csrbank7_dma_base1_re
+ attribute \src "ls180.v:2271.12-2271.40"
+ wire width 8 \builder_csrbank7_dma_base1_w
+ attribute \src "ls180.v:2270.6-2270.35"
+ wire \builder_csrbank7_dma_base1_we
+ attribute \src "ls180.v:2265.12-2265.40"
+ wire width 8 \builder_csrbank7_dma_base2_r
+ attribute \src "ls180.v:2264.6-2264.35"
+ wire \builder_csrbank7_dma_base2_re
+ attribute \src "ls180.v:2267.12-2267.40"
+ wire width 8 \builder_csrbank7_dma_base2_w
+ attribute \src "ls180.v:2266.6-2266.35"
+ wire \builder_csrbank7_dma_base2_we
+ attribute \src "ls180.v:2261.12-2261.40"
+ wire width 8 \builder_csrbank7_dma_base3_r
+ attribute \src "ls180.v:2260.6-2260.35"
+ wire \builder_csrbank7_dma_base3_re
+ attribute \src "ls180.v:2263.12-2263.40"
+ wire width 8 \builder_csrbank7_dma_base3_w
+ attribute \src "ls180.v:2262.6-2262.35"
+ wire \builder_csrbank7_dma_base3_we
+ attribute \src "ls180.v:2257.12-2257.40"
+ wire width 8 \builder_csrbank7_dma_base4_r
+ attribute \src "ls180.v:2256.6-2256.35"
+ wire \builder_csrbank7_dma_base4_re
+ attribute \src "ls180.v:2259.12-2259.40"
+ wire width 8 \builder_csrbank7_dma_base4_w
+ attribute \src "ls180.v:2258.6-2258.35"
+ wire \builder_csrbank7_dma_base4_we
+ attribute \src "ls180.v:2253.12-2253.40"
+ wire width 8 \builder_csrbank7_dma_base5_r
+ attribute \src "ls180.v:2252.6-2252.35"
+ wire \builder_csrbank7_dma_base5_re
+ attribute \src "ls180.v:2255.12-2255.40"
+ wire width 8 \builder_csrbank7_dma_base5_w
+ attribute \src "ls180.v:2254.6-2254.35"
+ wire \builder_csrbank7_dma_base5_we
+ attribute \src "ls180.v:2249.12-2249.40"
+ wire width 8 \builder_csrbank7_dma_base6_r
+ attribute \src "ls180.v:2248.6-2248.35"
+ wire \builder_csrbank7_dma_base6_re
+ attribute \src "ls180.v:2251.12-2251.40"
+ wire width 8 \builder_csrbank7_dma_base6_w
+ attribute \src "ls180.v:2250.6-2250.35"
+ wire \builder_csrbank7_dma_base6_we
+ attribute \src "ls180.v:2245.12-2245.40"
+ wire width 8 \builder_csrbank7_dma_base7_r
+ attribute \src "ls180.v:2244.6-2244.35"
+ wire \builder_csrbank7_dma_base7_re
+ attribute \src "ls180.v:2247.12-2247.40"
+ wire width 8 \builder_csrbank7_dma_base7_w
+ attribute \src "ls180.v:2246.6-2246.35"
+ wire \builder_csrbank7_dma_base7_we
+ attribute \src "ls180.v:2297.6-2297.33"
+ wire \builder_csrbank7_dma_done_r
+ attribute \src "ls180.v:2296.6-2296.34"
+ wire \builder_csrbank7_dma_done_re
+ attribute \src "ls180.v:2299.6-2299.33"
+ wire \builder_csrbank7_dma_done_w
+ attribute \src "ls180.v:2298.6-2298.34"
+ wire \builder_csrbank7_dma_done_we
+ attribute \src "ls180.v:2293.6-2293.36"
+ wire \builder_csrbank7_dma_enable0_r
+ attribute \src "ls180.v:2292.6-2292.37"
+ wire \builder_csrbank7_dma_enable0_re
+ attribute \src "ls180.v:2295.6-2295.36"
+ wire \builder_csrbank7_dma_enable0_w
+ attribute \src "ls180.v:2294.6-2294.37"
+ wire \builder_csrbank7_dma_enable0_we
+ attribute \src "ls180.v:2289.12-2289.42"
+ wire width 8 \builder_csrbank7_dma_length0_r
+ attribute \src "ls180.v:2288.6-2288.37"
+ wire \builder_csrbank7_dma_length0_re
+ attribute \src "ls180.v:2291.12-2291.42"
+ wire width 8 \builder_csrbank7_dma_length0_w
+ attribute \src "ls180.v:2290.6-2290.37"
+ wire \builder_csrbank7_dma_length0_we
+ attribute \src "ls180.v:2285.12-2285.42"
+ wire width 8 \builder_csrbank7_dma_length1_r
+ attribute \src "ls180.v:2284.6-2284.37"
+ wire \builder_csrbank7_dma_length1_re
+ attribute \src "ls180.v:2287.12-2287.42"
+ wire width 8 \builder_csrbank7_dma_length1_w
+ attribute \src "ls180.v:2286.6-2286.37"
+ wire \builder_csrbank7_dma_length1_we
+ attribute \src "ls180.v:2281.12-2281.42"
+ wire width 8 \builder_csrbank7_dma_length2_r
+ attribute \src "ls180.v:2280.6-2280.37"
+ wire \builder_csrbank7_dma_length2_re
+ attribute \src "ls180.v:2283.12-2283.42"
+ wire width 8 \builder_csrbank7_dma_length2_w
+ attribute \src "ls180.v:2282.6-2282.37"
+ wire \builder_csrbank7_dma_length2_we
+ attribute \src "ls180.v:2277.12-2277.42"
+ wire width 8 \builder_csrbank7_dma_length3_r
+ attribute \src "ls180.v:2276.6-2276.37"
+ wire \builder_csrbank7_dma_length3_re
+ attribute \src "ls180.v:2279.12-2279.42"
+ wire width 8 \builder_csrbank7_dma_length3_w
+ attribute \src "ls180.v:2278.6-2278.37"
+ wire \builder_csrbank7_dma_length3_we
+ attribute \src "ls180.v:2301.6-2301.34"
+ wire \builder_csrbank7_dma_loop0_r
+ attribute \src "ls180.v:2300.6-2300.35"
+ wire \builder_csrbank7_dma_loop0_re
+ attribute \src "ls180.v:2303.6-2303.34"
+ wire \builder_csrbank7_dma_loop0_w
+ attribute \src "ls180.v:2302.6-2302.35"
+ wire \builder_csrbank7_dma_loop0_we
+ attribute \src "ls180.v:2317.12-2317.42"
+ wire width 8 \builder_csrbank7_dma_offset0_r
+ attribute \src "ls180.v:2316.6-2316.37"
+ wire \builder_csrbank7_dma_offset0_re
+ attribute \src "ls180.v:2319.12-2319.42"
+ wire width 8 \builder_csrbank7_dma_offset0_w
+ attribute \src "ls180.v:2318.6-2318.37"
+ wire \builder_csrbank7_dma_offset0_we
+ attribute \src "ls180.v:2313.12-2313.42"
+ wire width 8 \builder_csrbank7_dma_offset1_r
+ attribute \src "ls180.v:2312.6-2312.37"
+ wire \builder_csrbank7_dma_offset1_re
+ attribute \src "ls180.v:2315.12-2315.42"
+ wire width 8 \builder_csrbank7_dma_offset1_w
+ attribute \src "ls180.v:2314.6-2314.37"
+ wire \builder_csrbank7_dma_offset1_we
+ attribute \src "ls180.v:2309.12-2309.42"
+ wire width 8 \builder_csrbank7_dma_offset2_r
+ attribute \src "ls180.v:2308.6-2308.37"
+ wire \builder_csrbank7_dma_offset2_re
+ attribute \src "ls180.v:2311.12-2311.42"
+ wire width 8 \builder_csrbank7_dma_offset2_w
+ attribute \src "ls180.v:2310.6-2310.37"
+ wire \builder_csrbank7_dma_offset2_we
+ attribute \src "ls180.v:2305.12-2305.42"
+ wire width 8 \builder_csrbank7_dma_offset3_r
+ attribute \src "ls180.v:2304.6-2304.37"
+ wire \builder_csrbank7_dma_offset3_re
+ attribute \src "ls180.v:2307.12-2307.42"
+ wire width 8 \builder_csrbank7_dma_offset3_w
+ attribute \src "ls180.v:2306.6-2306.37"
+ wire \builder_csrbank7_dma_offset3_we
+ attribute \src "ls180.v:2320.6-2320.26"
wire \builder_csrbank7_sel
- attribute \src "ls180.v:2314.12-2314.44"
- wire width 4 \builder_csrbank8_dfii_control0_r
- attribute \src "ls180.v:2313.6-2313.39"
- wire \builder_csrbank8_dfii_control0_re
- attribute \src "ls180.v:2316.12-2316.44"
- wire width 4 \builder_csrbank8_dfii_control0_w
- attribute \src "ls180.v:2315.6-2315.39"
- wire \builder_csrbank8_dfii_control0_we
- attribute \src "ls180.v:2326.12-2326.48"
- wire width 8 \builder_csrbank8_dfii_pi0_address0_r
- attribute \src "ls180.v:2325.6-2325.43"
- wire \builder_csrbank8_dfii_pi0_address0_re
- attribute \src "ls180.v:2328.12-2328.48"
- wire width 8 \builder_csrbank8_dfii_pi0_address0_w
- attribute \src "ls180.v:2327.6-2327.43"
- wire \builder_csrbank8_dfii_pi0_address0_we
- attribute \src "ls180.v:2322.12-2322.48"
- wire width 5 \builder_csrbank8_dfii_pi0_address1_r
- attribute \src "ls180.v:2321.6-2321.43"
- wire \builder_csrbank8_dfii_pi0_address1_re
- attribute \src "ls180.v:2324.12-2324.48"
- wire width 5 \builder_csrbank8_dfii_pi0_address1_w
- attribute \src "ls180.v:2323.6-2323.43"
- wire \builder_csrbank8_dfii_pi0_address1_we
- attribute \src "ls180.v:2330.12-2330.49"
- wire width 2 \builder_csrbank8_dfii_pi0_baddress0_r
- attribute \src "ls180.v:2329.6-2329.44"
- wire \builder_csrbank8_dfii_pi0_baddress0_re
- attribute \src "ls180.v:2332.12-2332.49"
- wire width 2 \builder_csrbank8_dfii_pi0_baddress0_w
- attribute \src "ls180.v:2331.6-2331.44"
- wire \builder_csrbank8_dfii_pi0_baddress0_we
- attribute \src "ls180.v:2318.12-2318.48"
- wire width 6 \builder_csrbank8_dfii_pi0_command0_r
- attribute \src "ls180.v:2317.6-2317.43"
- wire \builder_csrbank8_dfii_pi0_command0_re
- attribute \src "ls180.v:2320.12-2320.48"
- wire width 6 \builder_csrbank8_dfii_pi0_command0_w
- attribute \src "ls180.v:2319.6-2319.43"
- wire \builder_csrbank8_dfii_pi0_command0_we
- attribute \src "ls180.v:2346.12-2346.47"
- wire width 8 \builder_csrbank8_dfii_pi0_rddata0_r
- attribute \src "ls180.v:2345.6-2345.42"
- wire \builder_csrbank8_dfii_pi0_rddata0_re
- attribute \src "ls180.v:2348.12-2348.47"
- wire width 8 \builder_csrbank8_dfii_pi0_rddata0_w
- attribute \src "ls180.v:2347.6-2347.42"
- wire \builder_csrbank8_dfii_pi0_rddata0_we
- attribute \src "ls180.v:2342.12-2342.47"
- wire width 8 \builder_csrbank8_dfii_pi0_rddata1_r
- attribute \src "ls180.v:2341.6-2341.42"
- wire \builder_csrbank8_dfii_pi0_rddata1_re
- attribute \src "ls180.v:2344.12-2344.47"
- wire width 8 \builder_csrbank8_dfii_pi0_rddata1_w
- attribute \src "ls180.v:2343.6-2343.42"
- wire \builder_csrbank8_dfii_pi0_rddata1_we
- attribute \src "ls180.v:2338.12-2338.47"
- wire width 8 \builder_csrbank8_dfii_pi0_wrdata0_r
- attribute \src "ls180.v:2337.6-2337.42"
- wire \builder_csrbank8_dfii_pi0_wrdata0_re
- attribute \src "ls180.v:2340.12-2340.47"
- wire width 8 \builder_csrbank8_dfii_pi0_wrdata0_w
- attribute \src "ls180.v:2339.6-2339.42"
- wire \builder_csrbank8_dfii_pi0_wrdata0_we
+ attribute \src "ls180.v:2326.6-2326.36"
+ wire \builder_csrbank8_card_detect_r
+ attribute \src "ls180.v:2325.6-2325.37"
+ wire \builder_csrbank8_card_detect_re
+ attribute \src "ls180.v:2328.6-2328.36"
+ wire \builder_csrbank8_card_detect_w
+ attribute \src "ls180.v:2327.6-2327.37"
+ wire \builder_csrbank8_card_detect_we
attribute \src "ls180.v:2334.12-2334.47"
- wire width 8 \builder_csrbank8_dfii_pi0_wrdata1_r
+ wire width 8 \builder_csrbank8_clocker_divider0_r
attribute \src "ls180.v:2333.6-2333.42"
- wire \builder_csrbank8_dfii_pi0_wrdata1_re
+ wire \builder_csrbank8_clocker_divider0_re
attribute \src "ls180.v:2336.12-2336.47"
- wire width 8 \builder_csrbank8_dfii_pi0_wrdata1_w
+ wire width 8 \builder_csrbank8_clocker_divider0_w
attribute \src "ls180.v:2335.6-2335.42"
- wire \builder_csrbank8_dfii_pi0_wrdata1_we
- attribute \src "ls180.v:2349.6-2349.26"
+ wire \builder_csrbank8_clocker_divider0_we
+ attribute \src "ls180.v:2330.6-2330.41"
+ wire \builder_csrbank8_clocker_divider1_r
+ attribute \src "ls180.v:2329.6-2329.42"
+ wire \builder_csrbank8_clocker_divider1_re
+ attribute \src "ls180.v:2332.6-2332.41"
+ wire \builder_csrbank8_clocker_divider1_w
+ attribute \src "ls180.v:2331.6-2331.42"
+ wire \builder_csrbank8_clocker_divider1_we
+ attribute \src "ls180.v:2337.6-2337.26"
wire \builder_csrbank8_sel
- attribute \src "ls180.v:2359.12-2359.39"
- wire width 8 \builder_csrbank9_control0_r
- attribute \src "ls180.v:2358.6-2358.34"
- wire \builder_csrbank9_control0_re
- attribute \src "ls180.v:2361.12-2361.39"
- wire width 8 \builder_csrbank9_control0_w
- attribute \src "ls180.v:2360.6-2360.34"
- wire \builder_csrbank9_control0_we
- attribute \src "ls180.v:2355.12-2355.39"
- wire width 8 \builder_csrbank9_control1_r
- attribute \src "ls180.v:2354.6-2354.34"
- wire \builder_csrbank9_control1_re
- attribute \src "ls180.v:2357.12-2357.39"
- wire width 8 \builder_csrbank9_control1_w
- attribute \src "ls180.v:2356.6-2356.34"
- wire \builder_csrbank9_control1_we
- attribute \src "ls180.v:2375.6-2375.28"
- wire \builder_csrbank9_cs0_r
- attribute \src "ls180.v:2374.6-2374.29"
- wire \builder_csrbank9_cs0_re
- attribute \src "ls180.v:2377.6-2377.28"
- wire \builder_csrbank9_cs0_w
- attribute \src "ls180.v:2376.6-2376.29"
- wire \builder_csrbank9_cs0_we
- attribute \src "ls180.v:2379.6-2379.34"
- wire \builder_csrbank9_loopback0_r
- attribute \src "ls180.v:2378.6-2378.35"
- wire \builder_csrbank9_loopback0_re
- attribute \src "ls180.v:2381.6-2381.34"
- wire \builder_csrbank9_loopback0_w
- attribute \src "ls180.v:2380.6-2380.35"
- wire \builder_csrbank9_loopback0_we
- attribute \src "ls180.v:2371.12-2371.35"
- wire width 8 \builder_csrbank9_miso_r
- attribute \src "ls180.v:2370.6-2370.30"
- wire \builder_csrbank9_miso_re
- attribute \src "ls180.v:2373.12-2373.35"
- wire width 8 \builder_csrbank9_miso_w
- attribute \src "ls180.v:2372.6-2372.30"
- wire \builder_csrbank9_miso_we
- attribute \src "ls180.v:2367.12-2367.36"
- wire width 8 \builder_csrbank9_mosi0_r
- attribute \src "ls180.v:2366.6-2366.31"
- wire \builder_csrbank9_mosi0_re
- attribute \src "ls180.v:2369.12-2369.36"
- wire width 8 \builder_csrbank9_mosi0_w
- attribute \src "ls180.v:2368.6-2368.31"
- wire \builder_csrbank9_mosi0_we
- attribute \src "ls180.v:2382.6-2382.26"
+ attribute \src "ls180.v:2343.12-2343.44"
+ wire width 4 \builder_csrbank9_dfii_control0_r
+ attribute \src "ls180.v:2342.6-2342.39"
+ wire \builder_csrbank9_dfii_control0_re
+ attribute \src "ls180.v:2345.12-2345.44"
+ wire width 4 \builder_csrbank9_dfii_control0_w
+ attribute \src "ls180.v:2344.6-2344.39"
+ wire \builder_csrbank9_dfii_control0_we
+ attribute \src "ls180.v:2355.12-2355.48"
+ wire width 8 \builder_csrbank9_dfii_pi0_address0_r
+ attribute \src "ls180.v:2354.6-2354.43"
+ wire \builder_csrbank9_dfii_pi0_address0_re
+ attribute \src "ls180.v:2357.12-2357.48"
+ wire width 8 \builder_csrbank9_dfii_pi0_address0_w
+ attribute \src "ls180.v:2356.6-2356.43"
+ wire \builder_csrbank9_dfii_pi0_address0_we
+ attribute \src "ls180.v:2351.12-2351.48"
+ wire width 5 \builder_csrbank9_dfii_pi0_address1_r
+ attribute \src "ls180.v:2350.6-2350.43"
+ wire \builder_csrbank9_dfii_pi0_address1_re
+ attribute \src "ls180.v:2353.12-2353.48"
+ wire width 5 \builder_csrbank9_dfii_pi0_address1_w
+ attribute \src "ls180.v:2352.6-2352.43"
+ wire \builder_csrbank9_dfii_pi0_address1_we
+ attribute \src "ls180.v:2359.12-2359.49"
+ wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r
+ attribute \src "ls180.v:2358.6-2358.44"
+ wire \builder_csrbank9_dfii_pi0_baddress0_re
+ attribute \src "ls180.v:2361.12-2361.49"
+ wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w
+ attribute \src "ls180.v:2360.6-2360.44"
+ wire \builder_csrbank9_dfii_pi0_baddress0_we
+ attribute \src "ls180.v:2347.12-2347.48"
+ wire width 6 \builder_csrbank9_dfii_pi0_command0_r
+ attribute \src "ls180.v:2346.6-2346.43"
+ wire \builder_csrbank9_dfii_pi0_command0_re
+ attribute \src "ls180.v:2349.12-2349.48"
+ wire width 6 \builder_csrbank9_dfii_pi0_command0_w
+ attribute \src "ls180.v:2348.6-2348.43"
+ wire \builder_csrbank9_dfii_pi0_command0_we
+ attribute \src "ls180.v:2375.12-2375.47"
+ wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r
+ attribute \src "ls180.v:2374.6-2374.42"
+ wire \builder_csrbank9_dfii_pi0_rddata0_re
+ attribute \src "ls180.v:2377.12-2377.47"
+ wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w
+ attribute \src "ls180.v:2376.6-2376.42"
+ wire \builder_csrbank9_dfii_pi0_rddata0_we
+ attribute \src "ls180.v:2371.12-2371.47"
+ wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r
+ attribute \src "ls180.v:2370.6-2370.42"
+ wire \builder_csrbank9_dfii_pi0_rddata1_re
+ attribute \src "ls180.v:2373.12-2373.47"
+ wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w
+ attribute \src "ls180.v:2372.6-2372.42"
+ wire \builder_csrbank9_dfii_pi0_rddata1_we
+ attribute \src "ls180.v:2367.12-2367.47"
+ wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r
+ attribute \src "ls180.v:2366.6-2366.42"
+ wire \builder_csrbank9_dfii_pi0_wrdata0_re
+ attribute \src "ls180.v:2369.12-2369.47"
+ wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w
+ attribute \src "ls180.v:2368.6-2368.42"
+ wire \builder_csrbank9_dfii_pi0_wrdata0_we
+ attribute \src "ls180.v:2363.12-2363.47"
+ wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r
+ attribute \src "ls180.v:2362.6-2362.42"
+ wire \builder_csrbank9_dfii_pi0_wrdata1_re
+ attribute \src "ls180.v:2365.12-2365.47"
+ wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w
+ attribute \src "ls180.v:2364.6-2364.42"
+ wire \builder_csrbank9_dfii_pi0_wrdata1_we
+ attribute \src "ls180.v:2378.6-2378.26"
wire \builder_csrbank9_sel
- attribute \src "ls180.v:2363.6-2363.31"
- wire \builder_csrbank9_status_r
- attribute \src "ls180.v:2362.6-2362.32"
- wire \builder_csrbank9_status_re
- attribute \src "ls180.v:2365.6-2365.31"
- wire \builder_csrbank9_status_w
- attribute \src "ls180.v:2364.6-2364.32"
- wire \builder_csrbank9_status_we
- attribute \src "ls180.v:1859.6-1859.18"
+ attribute \src "ls180.v:1875.6-1875.18"
wire \builder_done
- attribute \src "ls180.v:1857.5-1857.18"
+ attribute \src "ls180.v:1873.5-1873.18"
wire \builder_error
- attribute \src "ls180.v:1854.11-1854.24"
+ attribute \src "ls180.v:1870.11-1870.24"
wire width 3 \builder_grant
- attribute \src "ls180.v:1861.13-1861.44"
+ attribute \src "ls180.v:1877.13-1877.44"
wire width 14 \builder_interface0_bank_bus_adr
- attribute \src "ls180.v:1864.11-1864.44"
+ attribute \src "ls180.v:1880.11-1880.44"
wire width 8 \builder_interface0_bank_bus_dat_r
- attribute \src "ls180.v:1863.12-1863.45"
+ attribute \src "ls180.v:1879.12-1879.45"
wire width 8 \builder_interface0_bank_bus_dat_w
- attribute \src "ls180.v:1862.6-1862.36"
+ attribute \src "ls180.v:1878.6-1878.36"
wire \builder_interface0_bank_bus_we
- attribute \src "ls180.v:2383.13-2383.45"
+ attribute \src "ls180.v:2379.13-2379.45"
wire width 14 \builder_interface10_bank_bus_adr
- attribute \src "ls180.v:2386.11-2386.45"
+ attribute \src "ls180.v:2382.11-2382.45"
wire width 8 \builder_interface10_bank_bus_dat_r
- attribute \src "ls180.v:2385.12-2385.46"
+ attribute \src "ls180.v:2381.12-2381.46"
wire width 8 \builder_interface10_bank_bus_dat_w
- attribute \src "ls180.v:2384.6-2384.37"
+ attribute \src "ls180.v:2380.6-2380.37"
wire \builder_interface10_bank_bus_we
- attribute \src "ls180.v:2424.13-2424.45"
+ attribute \src "ls180.v:2412.13-2412.45"
wire width 14 \builder_interface11_bank_bus_adr
- attribute \src "ls180.v:2427.11-2427.45"
+ attribute \src "ls180.v:2415.11-2415.45"
wire width 8 \builder_interface11_bank_bus_dat_r
- attribute \src "ls180.v:2426.12-2426.46"
+ attribute \src "ls180.v:2414.12-2414.46"
wire width 8 \builder_interface11_bank_bus_dat_w
- attribute \src "ls180.v:2425.6-2425.37"
+ attribute \src "ls180.v:2413.6-2413.37"
wire \builder_interface11_bank_bus_we
- attribute \src "ls180.v:2489.13-2489.45"
+ attribute \src "ls180.v:2453.13-2453.45"
wire width 14 \builder_interface12_bank_bus_adr
- attribute \src "ls180.v:2492.11-2492.45"
+ attribute \src "ls180.v:2456.11-2456.45"
wire width 8 \builder_interface12_bank_bus_dat_r
- attribute \src "ls180.v:2491.12-2491.46"
+ attribute \src "ls180.v:2455.12-2455.46"
wire width 8 \builder_interface12_bank_bus_dat_w
- attribute \src "ls180.v:2490.6-2490.37"
+ attribute \src "ls180.v:2454.6-2454.37"
wire \builder_interface12_bank_bus_we
- attribute \src "ls180.v:2514.13-2514.45"
+ attribute \src "ls180.v:2518.13-2518.45"
wire width 14 \builder_interface13_bank_bus_adr
- attribute \src "ls180.v:2517.11-2517.45"
+ attribute \src "ls180.v:2521.11-2521.45"
wire width 8 \builder_interface13_bank_bus_dat_r
- attribute \src "ls180.v:2516.12-2516.46"
+ attribute \src "ls180.v:2520.12-2520.46"
wire width 8 \builder_interface13_bank_bus_dat_w
- attribute \src "ls180.v:2515.6-2515.37"
+ attribute \src "ls180.v:2519.6-2519.37"
wire \builder_interface13_bank_bus_we
- attribute \src "ls180.v:1902.13-1902.44"
+ attribute \src "ls180.v:2543.13-2543.45"
+ wire width 14 \builder_interface14_bank_bus_adr
+ attribute \src "ls180.v:2546.11-2546.45"
+ wire width 8 \builder_interface14_bank_bus_dat_r
+ attribute \src "ls180.v:2545.12-2545.46"
+ wire width 8 \builder_interface14_bank_bus_dat_w
+ attribute \src "ls180.v:2544.6-2544.37"
+ wire \builder_interface14_bank_bus_we
+ attribute \src "ls180.v:1918.13-1918.44"
wire width 14 \builder_interface1_bank_bus_adr
- attribute \src "ls180.v:1905.11-1905.44"
+ attribute \src "ls180.v:1921.11-1921.44"
wire width 8 \builder_interface1_bank_bus_dat_r
- attribute \src "ls180.v:1904.12-1904.45"
+ attribute \src "ls180.v:1920.12-1920.45"
wire width 8 \builder_interface1_bank_bus_dat_w
- attribute \src "ls180.v:1903.6-1903.36"
+ attribute \src "ls180.v:1919.6-1919.36"
wire \builder_interface1_bank_bus_we
- attribute \src "ls180.v:1931.13-1931.44"
+ attribute \src "ls180.v:1947.13-1947.44"
wire width 14 \builder_interface2_bank_bus_adr
- attribute \src "ls180.v:1934.11-1934.44"
+ attribute \src "ls180.v:1950.11-1950.44"
wire width 8 \builder_interface2_bank_bus_dat_r
- attribute \src "ls180.v:1933.12-1933.45"
+ attribute \src "ls180.v:1949.12-1949.45"
wire width 8 \builder_interface2_bank_bus_dat_w
- attribute \src "ls180.v:1932.6-1932.36"
+ attribute \src "ls180.v:1948.6-1948.36"
wire \builder_interface2_bank_bus_we
- attribute \src "ls180.v:1972.13-1972.44"
+ attribute \src "ls180.v:1960.13-1960.44"
wire width 14 \builder_interface3_bank_bus_adr
- attribute \src "ls180.v:1975.11-1975.44"
+ attribute \src "ls180.v:1963.11-1963.44"
wire width 8 \builder_interface3_bank_bus_dat_r
- attribute \src "ls180.v:1974.12-1974.45"
+ attribute \src "ls180.v:1962.12-1962.45"
wire width 8 \builder_interface3_bank_bus_dat_w
- attribute \src "ls180.v:1973.6-1973.36"
+ attribute \src "ls180.v:1961.6-1961.36"
wire \builder_interface3_bank_bus_we
- attribute \src "ls180.v:2013.13-2013.44"
+ attribute \src "ls180.v:2001.13-2001.44"
wire width 14 \builder_interface4_bank_bus_adr
- attribute \src "ls180.v:2016.11-2016.44"
+ attribute \src "ls180.v:2004.11-2004.44"
wire width 8 \builder_interface4_bank_bus_dat_r
- attribute \src "ls180.v:2015.12-2015.45"
+ attribute \src "ls180.v:2003.12-2003.45"
wire width 8 \builder_interface4_bank_bus_dat_w
- attribute \src "ls180.v:2014.6-2014.36"
+ attribute \src "ls180.v:2002.6-2002.36"
wire \builder_interface4_bank_bus_we
- attribute \src "ls180.v:2078.13-2078.44"
+ attribute \src "ls180.v:2042.13-2042.44"
wire width 14 \builder_interface5_bank_bus_adr
- attribute \src "ls180.v:2081.11-2081.44"
+ attribute \src "ls180.v:2045.11-2045.44"
wire width 8 \builder_interface5_bank_bus_dat_r
- attribute \src "ls180.v:2080.12-2080.45"
+ attribute \src "ls180.v:2044.12-2044.45"
wire width 8 \builder_interface5_bank_bus_dat_w
- attribute \src "ls180.v:2079.6-2079.36"
+ attribute \src "ls180.v:2043.6-2043.36"
wire \builder_interface5_bank_bus_we
- attribute \src "ls180.v:2211.13-2211.44"
+ attribute \src "ls180.v:2107.13-2107.44"
wire width 14 \builder_interface6_bank_bus_adr
- attribute \src "ls180.v:2214.11-2214.44"
+ attribute \src "ls180.v:2110.11-2110.44"
wire width 8 \builder_interface6_bank_bus_dat_r
- attribute \src "ls180.v:2213.12-2213.45"
+ attribute \src "ls180.v:2109.12-2109.45"
wire width 8 \builder_interface6_bank_bus_dat_w
- attribute \src "ls180.v:2212.6-2212.36"
+ attribute \src "ls180.v:2108.6-2108.36"
wire \builder_interface6_bank_bus_we
- attribute \src "ls180.v:2292.13-2292.44"
+ attribute \src "ls180.v:2240.13-2240.44"
wire width 14 \builder_interface7_bank_bus_adr
- attribute \src "ls180.v:2295.11-2295.44"
+ attribute \src "ls180.v:2243.11-2243.44"
wire width 8 \builder_interface7_bank_bus_dat_r
- attribute \src "ls180.v:2294.12-2294.45"
+ attribute \src "ls180.v:2242.12-2242.45"
wire width 8 \builder_interface7_bank_bus_dat_w
- attribute \src "ls180.v:2293.6-2293.36"
+ attribute \src "ls180.v:2241.6-2241.36"
wire \builder_interface7_bank_bus_we
- attribute \src "ls180.v:2309.13-2309.44"
+ attribute \src "ls180.v:2321.13-2321.44"
wire width 14 \builder_interface8_bank_bus_adr
- attribute \src "ls180.v:2312.11-2312.44"
+ attribute \src "ls180.v:2324.11-2324.44"
wire width 8 \builder_interface8_bank_bus_dat_r
- attribute \src "ls180.v:2311.12-2311.45"
+ attribute \src "ls180.v:2323.12-2323.45"
wire width 8 \builder_interface8_bank_bus_dat_w
- attribute \src "ls180.v:2310.6-2310.36"
+ attribute \src "ls180.v:2322.6-2322.36"
wire \builder_interface8_bank_bus_we
- attribute \src "ls180.v:2350.13-2350.44"
+ attribute \src "ls180.v:2338.13-2338.44"
wire width 14 \builder_interface9_bank_bus_adr
- attribute \src "ls180.v:2353.11-2353.44"
+ attribute \src "ls180.v:2341.11-2341.44"
wire width 8 \builder_interface9_bank_bus_dat_r
- attribute \src "ls180.v:2352.12-2352.45"
+ attribute \src "ls180.v:2340.12-2340.45"
wire width 8 \builder_interface9_bank_bus_dat_w
- attribute \src "ls180.v:2351.6-2351.36"
+ attribute \src "ls180.v:2339.6-2339.36"
wire \builder_interface9_bank_bus_we
- attribute \src "ls180.v:1827.12-1827.35"
+ attribute \src "ls180.v:1843.12-1843.35"
wire width 14 \builder_libresocsim_adr
- attribute \src "ls180.v:2543.12-2543.47"
+ attribute \src "ls180.v:2572.12-2572.47"
wire width 14 \builder_libresocsim_adr_next_value1
- attribute \src "ls180.v:2544.5-2544.43"
+ attribute \src "ls180.v:2573.5-2573.43"
wire \builder_libresocsim_adr_next_value_ce1
- attribute \src "ls180.v:1830.12-1830.37"
+ attribute \src "ls180.v:1846.12-1846.37"
wire width 8 \builder_libresocsim_dat_r
- attribute \src "ls180.v:1829.11-1829.36"
+ attribute \src "ls180.v:1845.11-1845.36"
wire width 8 \builder_libresocsim_dat_w
- attribute \src "ls180.v:2541.11-2541.48"
+ attribute \src "ls180.v:2570.11-2570.48"
wire width 8 \builder_libresocsim_dat_w_next_value0
- attribute \src "ls180.v:2542.5-2542.45"
+ attribute \src "ls180.v:2571.5-2571.45"
wire \builder_libresocsim_dat_w_next_value_ce0
- attribute \src "ls180.v:1828.5-1828.27"
+ attribute \src "ls180.v:1844.5-1844.27"
wire \builder_libresocsim_we
- attribute \src "ls180.v:2545.5-2545.39"
+ attribute \src "ls180.v:2574.5-2574.39"
wire \builder_libresocsim_we_next_value2
- attribute \src "ls180.v:2546.5-2546.42"
+ attribute \src "ls180.v:2575.5-2575.42"
wire \builder_libresocsim_we_next_value_ce2
- attribute \src "ls180.v:1837.5-1837.37"
+ attribute \src "ls180.v:1853.5-1853.37"
wire \builder_libresocsim_wishbone_ack
- attribute \src "ls180.v:1831.13-1831.45"
+ attribute \src "ls180.v:1847.13-1847.45"
wire width 30 \builder_libresocsim_wishbone_adr
- attribute \src "ls180.v:1840.12-1840.44"
+ attribute \src "ls180.v:1856.12-1856.44"
wire width 2 \builder_libresocsim_wishbone_bte
- attribute \src "ls180.v:1839.12-1839.44"
+ attribute \src "ls180.v:1855.12-1855.44"
wire width 3 \builder_libresocsim_wishbone_cti
- attribute \src "ls180.v:1835.6-1835.38"
+ attribute \src "ls180.v:1851.6-1851.38"
wire \builder_libresocsim_wishbone_cyc
- attribute \src "ls180.v:1833.12-1833.46"
+ attribute \src "ls180.v:1849.12-1849.46"
wire width 32 \builder_libresocsim_wishbone_dat_r
- attribute \src "ls180.v:1832.13-1832.47"
+ attribute \src "ls180.v:1848.13-1848.47"
wire width 32 \builder_libresocsim_wishbone_dat_w
- attribute \src "ls180.v:1841.5-1841.37"
+ attribute \src "ls180.v:1857.5-1857.37"
wire \builder_libresocsim_wishbone_err
- attribute \src "ls180.v:1834.12-1834.44"
+ attribute \src "ls180.v:1850.12-1850.44"
wire width 4 \builder_libresocsim_wishbone_sel
- attribute \src "ls180.v:1836.6-1836.38"
+ attribute \src "ls180.v:1852.6-1852.38"
wire \builder_libresocsim_wishbone_stb
- attribute \src "ls180.v:1838.6-1838.37"
+ attribute \src "ls180.v:1854.6-1854.37"
wire \builder_libresocsim_wishbone_we
- attribute \src "ls180.v:1730.5-1730.20"
+ attribute \src "ls180.v:1746.5-1746.20"
wire \builder_locked0
- attribute \src "ls180.v:1731.5-1731.20"
+ attribute \src "ls180.v:1747.5-1747.20"
wire \builder_locked1
- attribute \src "ls180.v:1732.5-1732.20"
+ attribute \src "ls180.v:1748.5-1748.20"
wire \builder_locked2
- attribute \src "ls180.v:1733.5-1733.20"
+ attribute \src "ls180.v:1749.5-1749.20"
wire \builder_locked3
- attribute \src "ls180.v:1717.11-1717.41"
+ attribute \src "ls180.v:1733.11-1733.41"
wire width 3 \builder_multiplexer_next_state
- attribute \src "ls180.v:1716.11-1716.36"
+ attribute \src "ls180.v:1732.11-1732.36"
wire width 3 \builder_multiplexer_state
attribute \no_retiming "true"
- attribute \src "ls180.v:2650.32-2650.59"
+ attribute \src "ls180.v:2679.32-2679.59"
wire \builder_multiregimpl0_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2651.32-2651.59"
+ attribute \src "ls180.v:2680.32-2680.59"
wire \builder_multiregimpl0_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2670.32-2670.60"
+ attribute \src "ls180.v:2699.32-2699.60"
wire \builder_multiregimpl10_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2671.32-2671.60"
+ attribute \src "ls180.v:2700.32-2700.60"
wire \builder_multiregimpl10_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2672.32-2672.60"
+ attribute \src "ls180.v:2701.32-2701.60"
wire \builder_multiregimpl11_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2673.32-2673.60"
+ attribute \src "ls180.v:2702.32-2702.60"
wire \builder_multiregimpl11_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2674.32-2674.60"
+ attribute \src "ls180.v:2703.32-2703.60"
wire \builder_multiregimpl12_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2675.32-2675.60"
+ attribute \src "ls180.v:2704.32-2704.60"
wire \builder_multiregimpl12_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2676.32-2676.60"
+ attribute \src "ls180.v:2705.32-2705.60"
wire \builder_multiregimpl13_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2677.32-2677.60"
+ attribute \src "ls180.v:2706.32-2706.60"
wire \builder_multiregimpl13_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2678.32-2678.60"
+ attribute \src "ls180.v:2707.32-2707.60"
wire \builder_multiregimpl14_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2679.32-2679.60"
+ attribute \src "ls180.v:2708.32-2708.60"
wire \builder_multiregimpl14_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2680.32-2680.60"
+ attribute \src "ls180.v:2709.32-2709.60"
wire \builder_multiregimpl15_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2681.32-2681.60"
+ attribute \src "ls180.v:2710.32-2710.60"
wire \builder_multiregimpl15_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2682.32-2682.60"
+ attribute \src "ls180.v:2711.32-2711.60"
wire \builder_multiregimpl16_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2683.32-2683.60"
+ attribute \src "ls180.v:2712.32-2712.60"
wire \builder_multiregimpl16_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2652.32-2652.59"
+ attribute \src "ls180.v:2681.32-2681.59"
wire \builder_multiregimpl1_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2653.32-2653.59"
+ attribute \src "ls180.v:2682.32-2682.59"
wire \builder_multiregimpl1_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2654.32-2654.59"
+ attribute \src "ls180.v:2683.32-2683.59"
wire \builder_multiregimpl2_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2655.32-2655.59"
+ attribute \src "ls180.v:2684.32-2684.59"
wire \builder_multiregimpl2_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2656.32-2656.59"
+ attribute \src "ls180.v:2685.32-2685.59"
wire \builder_multiregimpl3_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2657.32-2657.59"
+ attribute \src "ls180.v:2686.32-2686.59"
wire \builder_multiregimpl3_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2658.32-2658.59"
+ attribute \src "ls180.v:2687.32-2687.59"
wire \builder_multiregimpl4_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2659.32-2659.59"
+ attribute \src "ls180.v:2688.32-2688.59"
wire \builder_multiregimpl4_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2660.32-2660.59"
+ attribute \src "ls180.v:2689.32-2689.59"
wire \builder_multiregimpl5_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2661.32-2661.59"
+ attribute \src "ls180.v:2690.32-2690.59"
wire \builder_multiregimpl5_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2662.32-2662.59"
+ attribute \src "ls180.v:2691.32-2691.59"
wire \builder_multiregimpl6_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2663.32-2663.59"
+ attribute \src "ls180.v:2692.32-2692.59"
wire \builder_multiregimpl6_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2664.32-2664.59"
+ attribute \src "ls180.v:2693.32-2693.59"
wire \builder_multiregimpl7_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2665.32-2665.59"
+ attribute \src "ls180.v:2694.32-2694.59"
wire \builder_multiregimpl7_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2666.32-2666.59"
+ attribute \src "ls180.v:2695.32-2695.59"
wire \builder_multiregimpl8_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2667.32-2667.59"
+ attribute \src "ls180.v:2696.32-2696.59"
wire \builder_multiregimpl8_regs1
attribute \no_retiming "true"
- attribute \src "ls180.v:2668.32-2668.59"
+ attribute \src "ls180.v:2697.32-2697.59"
wire \builder_multiregimpl9_regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:2669.32-2669.59"
+ attribute \src "ls180.v:2698.32-2698.59"
wire \builder_multiregimpl9_regs1
- attribute \src "ls180.v:1735.5-1735.36"
+ attribute \src "ls180.v:1751.5-1751.36"
wire \builder_new_master_rdata_valid0
- attribute \src "ls180.v:1736.5-1736.36"
+ attribute \src "ls180.v:1752.5-1752.36"
wire \builder_new_master_rdata_valid1
- attribute \src "ls180.v:1737.5-1737.36"
+ attribute \src "ls180.v:1753.5-1753.36"
wire \builder_new_master_rdata_valid2
- attribute \src "ls180.v:1738.5-1738.36"
+ attribute \src "ls180.v:1754.5-1754.36"
wire \builder_new_master_rdata_valid3
- attribute \src "ls180.v:1734.5-1734.35"
+ attribute \src "ls180.v:1750.5-1750.35"
wire \builder_new_master_wdata_ready
- attribute \src "ls180.v:2540.11-2540.29"
+ attribute \src "ls180.v:2569.11-2569.29"
wire width 2 \builder_next_state
- attribute \src "ls180.v:1707.11-1707.39"
+ attribute \src "ls180.v:1723.11-1723.39"
wire width 2 \builder_refresher_next_state
- attribute \src "ls180.v:1706.11-1706.34"
+ attribute \src "ls180.v:1722.11-1722.34"
wire width 2 \builder_refresher_state
- attribute \src "ls180.v:1853.12-1853.27"
+ attribute \src "ls180.v:1869.12-1869.27"
wire width 5 \builder_request
- attribute \src "ls180.v:1720.6-1720.28"
+ attribute \src "ls180.v:1736.6-1736.28"
wire \builder_roundrobin0_ce
- attribute \src "ls180.v:1719.6-1719.31"
+ attribute \src "ls180.v:1735.6-1735.31"
wire \builder_roundrobin0_grant
- attribute \src "ls180.v:1718.6-1718.33"
+ attribute \src "ls180.v:1734.6-1734.33"
wire \builder_roundrobin0_request
- attribute \src "ls180.v:1723.6-1723.28"
+ attribute \src "ls180.v:1739.6-1739.28"
wire \builder_roundrobin1_ce
- attribute \src "ls180.v:1722.6-1722.31"
+ attribute \src "ls180.v:1738.6-1738.31"
wire \builder_roundrobin1_grant
- attribute \src "ls180.v:1721.6-1721.33"
+ attribute \src "ls180.v:1737.6-1737.33"
wire \builder_roundrobin1_request
- attribute \src "ls180.v:1726.6-1726.28"
+ attribute \src "ls180.v:1742.6-1742.28"
wire \builder_roundrobin2_ce
- attribute \src "ls180.v:1725.6-1725.31"
+ attribute \src "ls180.v:1741.6-1741.31"
wire \builder_roundrobin2_grant
- attribute \src "ls180.v:1724.6-1724.33"
+ attribute \src "ls180.v:1740.6-1740.33"
wire \builder_roundrobin2_request
- attribute \src "ls180.v:1729.6-1729.28"
+ attribute \src "ls180.v:1745.6-1745.28"
wire \builder_roundrobin3_ce
- attribute \src "ls180.v:1728.6-1728.31"
+ attribute \src "ls180.v:1744.6-1744.31"
wire \builder_roundrobin3_grant
- attribute \src "ls180.v:1727.6-1727.33"
+ attribute \src "ls180.v:1743.6-1743.33"
wire \builder_roundrobin3_request
- attribute \src "ls180.v:1812.11-1812.44"
+ attribute \src "ls180.v:1828.11-1828.44"
wire width 2 \builder_sdblock2memdma_next_state
- attribute \src "ls180.v:1811.11-1811.39"
+ attribute \src "ls180.v:1827.11-1827.39"
wire width 2 \builder_sdblock2memdma_state
- attribute \src "ls180.v:1780.5-1780.50"
+ attribute \src "ls180.v:1796.5-1796.50"
wire \builder_sdcore_crcupstreaminserter_next_state
- attribute \src "ls180.v:1779.5-1779.45"
+ attribute \src "ls180.v:1795.5-1795.45"
wire \builder_sdcore_crcupstreaminserter_state
- attribute \src "ls180.v:1792.11-1792.40"
+ attribute \src "ls180.v:1808.11-1808.40"
wire width 3 \builder_sdcore_fsm_next_state
- attribute \src "ls180.v:1791.11-1791.35"
+ attribute \src "ls180.v:1807.11-1807.35"
wire width 3 \builder_sdcore_fsm_state
- attribute \src "ls180.v:1816.5-1816.42"
+ attribute \src "ls180.v:1832.5-1832.42"
wire \builder_sdmem2blockdma_fsm_next_state
- attribute \src "ls180.v:1815.5-1815.37"
+ attribute \src "ls180.v:1831.5-1831.37"
wire \builder_sdmem2blockdma_fsm_state
- attribute \src "ls180.v:1820.11-1820.58"
+ attribute \src "ls180.v:1836.11-1836.58"
wire width 2 \builder_sdmem2blockdma_resetinserter_next_state
- attribute \src "ls180.v:1819.11-1819.53"
+ attribute \src "ls180.v:1835.11-1835.53"
wire width 2 \builder_sdmem2blockdma_resetinserter_state
- attribute \src "ls180.v:1768.11-1768.39"
+ attribute \src "ls180.v:1784.11-1784.39"
wire width 3 \builder_sdphy_fsm_next_state
- attribute \src "ls180.v:1767.11-1767.34"
+ attribute \src "ls180.v:1783.11-1783.34"
wire width 3 \builder_sdphy_fsm_state
- attribute \src "ls180.v:1756.11-1756.45"
+ attribute \src "ls180.v:1772.11-1772.45"
wire width 3 \builder_sdphy_sdphycmdr_next_state
- attribute \src "ls180.v:1755.11-1755.40"
+ attribute \src "ls180.v:1771.11-1771.40"
wire width 3 \builder_sdphy_sdphycmdr_state
- attribute \src "ls180.v:1752.11-1752.45"
+ attribute \src "ls180.v:1768.11-1768.45"
wire width 2 \builder_sdphy_sdphycmdw_next_state
- attribute \src "ls180.v:1751.11-1751.40"
+ attribute \src "ls180.v:1767.11-1767.40"
wire width 2 \builder_sdphy_sdphycmdw_state
- attribute \src "ls180.v:1764.5-1764.39"
+ attribute \src "ls180.v:1780.5-1780.39"
wire \builder_sdphy_sdphycrcr_next_state
- attribute \src "ls180.v:1763.5-1763.34"
+ attribute \src "ls180.v:1779.5-1779.34"
wire \builder_sdphy_sdphycrcr_state
- attribute \src "ls180.v:1772.11-1772.46"
+ attribute \src "ls180.v:1788.11-1788.46"
wire width 3 \builder_sdphy_sdphydatar_next_state
- attribute \src "ls180.v:1771.11-1771.41"
+ attribute \src "ls180.v:1787.11-1787.41"
wire width 3 \builder_sdphy_sdphydatar_state
- attribute \src "ls180.v:1748.5-1748.39"
+ attribute \src "ls180.v:1764.5-1764.39"
wire \builder_sdphy_sdphyinit_next_state
- attribute \src "ls180.v:1747.5-1747.34"
+ attribute \src "ls180.v:1763.5-1763.34"
wire \builder_sdphy_sdphyinit_state
- attribute \src "ls180.v:1848.5-1848.23"
+ attribute \src "ls180.v:1864.5-1864.23"
wire \builder_shared_ack
- attribute \src "ls180.v:1842.13-1842.31"
+ attribute \src "ls180.v:1858.13-1858.31"
wire width 30 \builder_shared_adr
- attribute \src "ls180.v:1851.12-1851.30"
+ attribute \src "ls180.v:1867.12-1867.30"
wire width 2 \builder_shared_bte
- attribute \src "ls180.v:1850.12-1850.30"
+ attribute \src "ls180.v:1866.12-1866.30"
wire width 3 \builder_shared_cti
- attribute \src "ls180.v:1846.6-1846.24"
+ attribute \src "ls180.v:1862.6-1862.24"
wire \builder_shared_cyc
- attribute \src "ls180.v:1844.12-1844.32"
+ attribute \src "ls180.v:1860.12-1860.32"
wire width 32 \builder_shared_dat_r
- attribute \src "ls180.v:1843.13-1843.33"
+ attribute \src "ls180.v:1859.13-1859.33"
wire width 32 \builder_shared_dat_w
- attribute \src "ls180.v:1852.6-1852.24"
+ attribute \src "ls180.v:1868.6-1868.24"
wire \builder_shared_err
- attribute \src "ls180.v:1845.12-1845.30"
+ attribute \src "ls180.v:1861.12-1861.30"
wire width 4 \builder_shared_sel
- attribute \src "ls180.v:1847.6-1847.24"
+ attribute \src "ls180.v:1863.6-1863.24"
wire \builder_shared_stb
- attribute \src "ls180.v:1849.6-1849.23"
+ attribute \src "ls180.v:1865.6-1865.23"
wire \builder_shared_we
- attribute \src "ls180.v:1855.11-1855.28"
+ attribute \src "ls180.v:1871.11-1871.28"
wire width 5 \builder_slave_sel
- attribute \src "ls180.v:1856.11-1856.30"
+ attribute \src "ls180.v:1872.11-1872.30"
wire width 5 \builder_slave_sel_r
- attribute \src "ls180.v:1744.11-1744.40"
+ attribute \src "ls180.v:1760.11-1760.40"
wire width 2 \builder_spimaster0_next_state
- attribute \src "ls180.v:1743.11-1743.35"
+ attribute \src "ls180.v:1759.11-1759.35"
wire width 2 \builder_spimaster0_state
- attribute \src "ls180.v:1824.11-1824.40"
+ attribute \src "ls180.v:1840.11-1840.40"
wire width 2 \builder_spimaster1_next_state
- attribute \src "ls180.v:1823.11-1823.35"
+ attribute \src "ls180.v:1839.11-1839.35"
wire width 2 \builder_spimaster1_state
- attribute \src "ls180.v:2539.11-2539.24"
+ attribute \src "ls180.v:2568.11-2568.24"
wire width 2 \builder_state
- attribute \src "ls180.v:2592.5-2592.32"
+ attribute \src "ls180.v:2621.5-2621.32"
wire \builder_sync_f_array_muxed0
- attribute \src "ls180.v:2593.5-2593.32"
+ attribute \src "ls180.v:2622.5-2622.32"
wire \builder_sync_f_array_muxed1
- attribute \src "ls180.v:2585.11-2585.40"
+ attribute \src "ls180.v:2614.11-2614.40"
wire width 2 \builder_sync_rhs_array_muxed0
- attribute \src "ls180.v:2586.12-2586.41"
+ attribute \src "ls180.v:2615.12-2615.41"
wire width 13 \builder_sync_rhs_array_muxed1
- attribute \src "ls180.v:2587.5-2587.34"
+ attribute \src "ls180.v:2616.5-2616.34"
wire \builder_sync_rhs_array_muxed2
- attribute \src "ls180.v:2588.5-2588.34"
+ attribute \src "ls180.v:2617.5-2617.34"
wire \builder_sync_rhs_array_muxed3
- attribute \src "ls180.v:2589.5-2589.34"
+ attribute \src "ls180.v:2618.5-2618.34"
wire \builder_sync_rhs_array_muxed4
- attribute \src "ls180.v:2590.5-2590.34"
+ attribute \src "ls180.v:2619.5-2619.34"
wire \builder_sync_rhs_array_muxed5
- attribute \src "ls180.v:2591.5-2591.34"
+ attribute \src "ls180.v:2620.5-2620.34"
wire \builder_sync_rhs_array_muxed6
- attribute \src "ls180.v:1858.6-1858.18"
+ attribute \src "ls180.v:1874.6-1874.18"
wire \builder_wait
- attribute \src "ls180.v:28.19-28.23"
- wire width 3 input 24 \eint
- attribute \src "ls180.v:21.20-21.26"
- wire width 16 input 17 \gpio_i
- attribute \src "ls180.v:22.21-22.27"
- wire width 16 output 18 \gpio_o
- attribute \src "ls180.v:23.21-23.28"
- wire width 16 output 19 \gpio_oe
- attribute \src "ls180.v:30.13-30.21"
- wire input 26 \jtag_tck
+ attribute \src "ls180.v:30.19-30.23"
+ wire width 3 input 26 \eint
+ attribute \src "ls180.v:23.20-23.26"
+ wire width 16 input 19 \gpio_i
+ attribute \src "ls180.v:24.21-24.27"
+ wire width 16 output 20 \gpio_o
+ attribute \src "ls180.v:25.21-25.28"
+ wire width 16 output 21 \gpio_oe
+ attribute \src "ls180.v:38.14-38.21"
+ wire output 34 \i2c_scl
+ attribute \src "ls180.v:39.13-39.22"
+ wire input 35 \i2c_sda_i
+ attribute \src "ls180.v:40.14-40.23"
+ wire output 36 \i2c_sda_o
+ attribute \src "ls180.v:41.14-41.24"
+ wire output 37 \i2c_sda_oe
+ attribute \src "ls180.v:32.13-32.21"
+ wire input 28 \jtag_tck
+ attribute \src "ls180.v:33.13-33.21"
+ wire input 29 \jtag_tdi
+ attribute \src "ls180.v:34.14-34.22"
+ wire output 30 \jtag_tdo
attribute \src "ls180.v:31.13-31.21"
- wire input 27 \jtag_tdi
- attribute \src "ls180.v:32.14-32.22"
- wire output 28 \jtag_tdo
- attribute \src "ls180.v:29.13-29.21"
- wire input 25 \jtag_tms
- attribute \src "ls180.v:1664.13-1664.37"
+ wire input 27 \jtag_tms
+ attribute \src "ls180.v:1680.13-1680.37"
wire width 16 \libresocsim_clk_divider0
- attribute \src "ls180.v:1686.12-1686.36"
+ attribute \src "ls180.v:1702.12-1702.36"
wire width 16 \libresocsim_clk_divider1
- attribute \src "ls180.v:1681.5-1681.27"
+ attribute \src "ls180.v:1697.5-1697.27"
wire \libresocsim_clk_enable
- attribute \src "ls180.v:1688.6-1688.26"
+ attribute \src "ls180.v:1704.6-1704.26"
wire \libresocsim_clk_fall
- attribute \src "ls180.v:1687.6-1687.26"
+ attribute \src "ls180.v:1703.6-1703.26"
wire \libresocsim_clk_rise
- attribute \src "ls180.v:1668.5-1668.27"
+ attribute \src "ls180.v:1684.5-1684.27"
wire \libresocsim_control_re
- attribute \src "ls180.v:1667.12-1667.39"
+ attribute \src "ls180.v:1683.12-1683.39"
wire width 16 \libresocsim_control_storage
- attribute \src "ls180.v:1683.11-1683.28"
+ attribute \src "ls180.v:1699.11-1699.28"
wire width 3 \libresocsim_count
- attribute \src "ls180.v:1825.11-1825.50"
+ attribute \src "ls180.v:1841.11-1841.50"
wire width 3 \libresocsim_count_spimaster1_next_value
- attribute \src "ls180.v:1826.5-1826.47"
+ attribute \src "ls180.v:1842.5-1842.47"
wire \libresocsim_count_spimaster1_next_value_ce
- attribute \src "ls180.v:1662.6-1662.20"
+ attribute \src "ls180.v:1678.6-1678.20"
wire \libresocsim_cs
- attribute \src "ls180.v:1682.5-1682.26"
+ attribute \src "ls180.v:1698.5-1698.26"
wire \libresocsim_cs_enable
- attribute \src "ls180.v:1678.5-1678.22"
+ attribute \src "ls180.v:1694.5-1694.22"
wire \libresocsim_cs_re
- attribute \src "ls180.v:1677.5-1677.27"
+ attribute \src "ls180.v:1693.5-1693.27"
wire \libresocsim_cs_storage
- attribute \src "ls180.v:1658.5-1658.22"
+ attribute \src "ls180.v:1674.5-1674.22"
wire \libresocsim_done0
- attribute \src "ls180.v:1669.6-1669.23"
+ attribute \src "ls180.v:1685.6-1685.23"
wire \libresocsim_done1
- attribute \src "ls180.v:1659.5-1659.20"
+ attribute \src "ls180.v:1675.5-1675.20"
wire \libresocsim_irq
- attribute \src "ls180.v:1657.12-1657.31"
+ attribute \src "ls180.v:1673.12-1673.31"
wire width 8 \libresocsim_length0
- attribute \src "ls180.v:1666.12-1666.31"
+ attribute \src "ls180.v:1682.12-1682.31"
wire width 8 \libresocsim_length1
- attribute \src "ls180.v:1663.6-1663.26"
+ attribute \src "ls180.v:1679.6-1679.26"
wire \libresocsim_loopback
- attribute \src "ls180.v:1680.5-1680.28"
+ attribute \src "ls180.v:1696.5-1696.28"
wire \libresocsim_loopback_re
- attribute \src "ls180.v:1679.5-1679.33"
+ attribute \src "ls180.v:1695.5-1695.33"
wire \libresocsim_loopback_storage
- attribute \src "ls180.v:1661.11-1661.27"
+ attribute \src "ls180.v:1677.11-1677.27"
wire width 8 \libresocsim_miso
- attribute \src "ls180.v:1691.11-1691.32"
+ attribute \src "ls180.v:1707.11-1707.32"
wire width 8 \libresocsim_miso_data
- attribute \src "ls180.v:1685.5-1685.27"
+ attribute \src "ls180.v:1701.5-1701.27"
wire \libresocsim_miso_latch
- attribute \src "ls180.v:1674.12-1674.35"
+ attribute \src "ls180.v:1690.12-1690.35"
wire width 8 \libresocsim_miso_status
- attribute \src "ls180.v:1675.6-1675.25"
+ attribute \src "ls180.v:1691.6-1691.25"
wire \libresocsim_miso_we
- attribute \src "ls180.v:1660.12-1660.28"
+ attribute \src "ls180.v:1676.12-1676.28"
wire width 8 \libresocsim_mosi
- attribute \src "ls180.v:1689.11-1689.32"
+ attribute \src "ls180.v:1705.11-1705.32"
wire width 8 \libresocsim_mosi_data
- attribute \src "ls180.v:1684.5-1684.27"
+ attribute \src "ls180.v:1700.5-1700.27"
wire \libresocsim_mosi_latch
- attribute \src "ls180.v:1673.5-1673.24"
+ attribute \src "ls180.v:1689.5-1689.24"
wire \libresocsim_mosi_re
- attribute \src "ls180.v:1690.11-1690.31"
+ attribute \src "ls180.v:1706.11-1706.31"
wire width 3 \libresocsim_mosi_sel
- attribute \src "ls180.v:1672.11-1672.35"
+ attribute \src "ls180.v:1688.11-1688.35"
wire width 8 \libresocsim_mosi_storage
- attribute \src "ls180.v:1693.5-1693.19"
+ attribute \src "ls180.v:1709.5-1709.19"
wire \libresocsim_re
- attribute \src "ls180.v:1676.6-1676.21"
+ attribute \src "ls180.v:1692.6-1692.21"
wire \libresocsim_sel
- attribute \src "ls180.v:1656.6-1656.24"
+ attribute \src "ls180.v:1672.6-1672.24"
wire \libresocsim_start0
- attribute \src "ls180.v:1665.5-1665.23"
+ attribute \src "ls180.v:1681.5-1681.23"
wire \libresocsim_start1
- attribute \src "ls180.v:1670.6-1670.31"
+ attribute \src "ls180.v:1686.6-1686.31"
wire \libresocsim_status_status
- attribute \src "ls180.v:1671.6-1671.27"
+ attribute \src "ls180.v:1687.6-1687.27"
wire \libresocsim_status_we
- attribute \src "ls180.v:1692.12-1692.31"
+ attribute \src "ls180.v:1708.12-1708.31"
wire width 16 \libresocsim_storage
- attribute \src "ls180.v:806.6-806.18"
+ attribute \src "ls180.v:814.6-814.18"
wire \main_ack_cmd
- attribute \src "ls180.v:808.6-808.20"
+ attribute \src "ls180.v:816.6-816.20"
wire \main_ack_rdata
- attribute \src "ls180.v:807.6-807.20"
+ attribute \src "ls180.v:815.6-815.20"
wire \main_ack_wdata
- attribute \src "ls180.v:804.5-804.22"
+ attribute \src "ls180.v:812.5-812.22"
wire \main_cmd_consumed
- attribute \src "ls180.v:801.5-801.27"
+ attribute \src "ls180.v:809.5-809.27"
wire \main_converter_counter
- attribute \src "ls180.v:1741.5-1741.48"
+ attribute \src "ls180.v:1757.5-1757.48"
wire \main_converter_counter_converter_next_value
- attribute \src "ls180.v:1742.5-1742.51"
+ attribute \src "ls180.v:1758.5-1758.51"
wire \main_converter_counter_converter_next_value_ce
- attribute \src "ls180.v:803.12-803.32"
+ attribute \src "ls180.v:811.12-811.32"
wire width 32 \main_converter_dat_r
- attribute \src "ls180.v:802.6-802.26"
+ attribute \src "ls180.v:810.6-810.26"
wire \main_converter_reset
- attribute \src "ls180.v:800.5-800.24"
+ attribute \src "ls180.v:808.5-808.24"
wire \main_converter_skip
- attribute \src "ls180.v:230.6-230.23"
+ attribute \src "ls180.v:238.6-238.23"
wire \main_dfi_p0_act_n
- attribute \src "ls180.v:221.13-221.32"
+ attribute \src "ls180.v:229.13-229.32"
wire width 13 \main_dfi_p0_address
- attribute \src "ls180.v:222.12-222.28"
+ attribute \src "ls180.v:230.12-230.28"
wire width 2 \main_dfi_p0_bank
- attribute \src "ls180.v:223.6-223.23"
+ attribute \src "ls180.v:231.6-231.23"
wire \main_dfi_p0_cas_n
- attribute \src "ls180.v:227.6-227.21"
+ attribute \src "ls180.v:235.6-235.21"
wire \main_dfi_p0_cke
- attribute \src "ls180.v:224.6-224.22"
+ attribute \src "ls180.v:232.6-232.22"
wire \main_dfi_p0_cs_n
- attribute \src "ls180.v:228.6-228.21"
+ attribute \src "ls180.v:236.6-236.21"
wire \main_dfi_p0_odt
- attribute \src "ls180.v:225.6-225.23"
+ attribute \src "ls180.v:233.6-233.23"
wire \main_dfi_p0_ras_n
- attribute \src "ls180.v:235.12-235.30"
+ attribute \src "ls180.v:243.12-243.30"
wire width 16 \main_dfi_p0_rddata
- attribute \src "ls180.v:234.6-234.27"
+ attribute \src "ls180.v:242.6-242.27"
wire \main_dfi_p0_rddata_en
- attribute \src "ls180.v:236.5-236.29"
+ attribute \src "ls180.v:244.5-244.29"
wire \main_dfi_p0_rddata_valid
- attribute \src "ls180.v:229.6-229.25"
+ attribute \src "ls180.v:237.6-237.25"
wire \main_dfi_p0_reset_n
- attribute \src "ls180.v:226.6-226.22"
+ attribute \src "ls180.v:234.6-234.22"
wire \main_dfi_p0_we_n
- attribute \src "ls180.v:231.13-231.31"
+ attribute \src "ls180.v:239.13-239.31"
wire width 16 \main_dfi_p0_wrdata
- attribute \src "ls180.v:232.6-232.27"
+ attribute \src "ls180.v:240.6-240.27"
wire \main_dfi_p0_wrdata_en
- attribute \src "ls180.v:233.12-233.35"
+ attribute \src "ls180.v:241.12-241.35"
wire width 2 \main_dfi_p0_wrdata_mask
- attribute \src "ls180.v:997.12-997.22"
- wire width 42 \main_dummy
- attribute \src "ls180.v:952.5-952.20"
+ attribute \src "ls180.v:1005.12-1005.22"
+ wire width 36 \main_dummy
+ attribute \src "ls180.v:960.5-960.20"
wire \main_gpio_oe_re
- attribute \src "ls180.v:951.12-951.32"
+ attribute \src "ls180.v:959.12-959.32"
wire width 16 \main_gpio_oe_storage
- attribute \src "ls180.v:956.5-956.21"
+ attribute \src "ls180.v:964.5-964.21"
wire \main_gpio_out_re
- attribute \src "ls180.v:955.12-955.33"
+ attribute \src "ls180.v:963.12-963.33"
wire width 16 \main_gpio_out_storage
- attribute \src "ls180.v:957.13-957.29"
+ attribute \src "ls180.v:965.13-965.29"
wire width 16 \main_gpio_pads_i
- attribute \src "ls180.v:958.13-958.29"
+ attribute \src "ls180.v:966.13-966.29"
wire width 16 \main_gpio_pads_o
- attribute \src "ls180.v:959.13-959.30"
+ attribute \src "ls180.v:967.13-967.30"
wire width 16 \main_gpio_pads_oe
- attribute \src "ls180.v:953.12-953.28"
+ attribute \src "ls180.v:961.12-961.28"
wire width 16 \main_gpio_status
- attribute \src "ls180.v:954.6-954.18"
+ attribute \src "ls180.v:962.6-962.18"
wire \main_gpio_we
- attribute \src "ls180.v:220.5-220.17"
+ attribute \src "ls180.v:1027.6-1027.17"
+ wire \main_i2c_oe
+ attribute \src "ls180.v:1030.5-1030.16"
+ wire \main_i2c_re
+ attribute \src "ls180.v:1026.6-1026.18"
+ wire \main_i2c_scl
+ attribute \src "ls180.v:1028.6-1028.19"
+ wire \main_i2c_sda0
+ attribute \src "ls180.v:1031.6-1031.19"
+ wire \main_i2c_sda1
+ attribute \src "ls180.v:1032.6-1032.21"
+ wire \main_i2c_status
+ attribute \src "ls180.v:1029.11-1029.27"
+ wire width 3 \main_i2c_storage
+ attribute \src "ls180.v:1033.6-1033.17"
+ wire \main_i2c_we
+ attribute \src "ls180.v:228.5-228.17"
wire \main_int_rst
- attribute \src "ls180.v:1477.6-1477.29"
+ attribute \src "ls180.v:1493.6-1493.29"
wire \main_interface0_bus_ack
- attribute \src "ls180.v:1471.13-1471.36"
+ attribute \src "ls180.v:1487.13-1487.36"
wire width 32 \main_interface0_bus_adr
- attribute \src "ls180.v:1480.11-1480.34"
+ attribute \src "ls180.v:1496.11-1496.34"
wire width 2 \main_interface0_bus_bte
- attribute \src "ls180.v:1479.11-1479.34"
+ attribute \src "ls180.v:1495.11-1495.34"
wire width 3 \main_interface0_bus_cti
- attribute \src "ls180.v:1475.6-1475.29"
+ attribute \src "ls180.v:1491.6-1491.29"
wire \main_interface0_bus_cyc
- attribute \src "ls180.v:1473.13-1473.38"
+ attribute \src "ls180.v:1489.13-1489.38"
wire width 32 \main_interface0_bus_dat_r
- attribute \src "ls180.v:1472.13-1472.38"
+ attribute \src "ls180.v:1488.13-1488.38"
wire width 32 \main_interface0_bus_dat_w
- attribute \src "ls180.v:1481.6-1481.29"
+ attribute \src "ls180.v:1497.6-1497.29"
wire \main_interface0_bus_err
- attribute \src "ls180.v:1474.12-1474.35"
+ attribute \src "ls180.v:1490.12-1490.35"
wire width 4 \main_interface0_bus_sel
- attribute \src "ls180.v:1476.6-1476.29"
+ attribute \src "ls180.v:1492.6-1492.29"
wire \main_interface0_bus_stb
- attribute \src "ls180.v:1478.6-1478.28"
+ attribute \src "ls180.v:1494.6-1494.28"
wire \main_interface0_bus_we
- attribute \src "ls180.v:1568.6-1568.29"
+ attribute \src "ls180.v:1584.6-1584.29"
wire \main_interface1_bus_ack
- attribute \src "ls180.v:1562.12-1562.35"
+ attribute \src "ls180.v:1578.12-1578.35"
wire width 32 \main_interface1_bus_adr
- attribute \src "ls180.v:1571.11-1571.34"
+ attribute \src "ls180.v:1587.11-1587.34"
wire width 2 \main_interface1_bus_bte
- attribute \src "ls180.v:1570.11-1570.34"
+ attribute \src "ls180.v:1586.11-1586.34"
wire width 3 \main_interface1_bus_cti
- attribute \src "ls180.v:1566.5-1566.28"
+ attribute \src "ls180.v:1582.5-1582.28"
wire \main_interface1_bus_cyc
- attribute \src "ls180.v:1564.13-1564.38"
+ attribute \src "ls180.v:1580.13-1580.38"
wire width 32 \main_interface1_bus_dat_r
- attribute \src "ls180.v:1563.12-1563.37"
+ attribute \src "ls180.v:1579.12-1579.37"
wire width 32 \main_interface1_bus_dat_w
- attribute \src "ls180.v:1572.6-1572.29"
+ attribute \src "ls180.v:1588.6-1588.29"
wire \main_interface1_bus_err
- attribute \src "ls180.v:1565.11-1565.34"
+ attribute \src "ls180.v:1581.11-1581.34"
wire width 4 \main_interface1_bus_sel
- attribute \src "ls180.v:1567.5-1567.28"
+ attribute \src "ls180.v:1583.5-1583.28"
wire \main_interface1_bus_stb
- attribute \src "ls180.v:1569.5-1569.27"
+ attribute \src "ls180.v:1585.5-1585.27"
wire \main_interface1_bus_we
- attribute \src "ls180.v:186.12-186.32"
+ attribute \src "ls180.v:194.12-194.32"
wire width 7 \main_libresocsim_adr
- attribute \src "ls180.v:56.6-56.32"
+ attribute \src "ls180.v:62.6-62.32"
wire \main_libresocsim_bus_error
- attribute \src "ls180.v:57.12-57.39"
+ attribute \src "ls180.v:63.12-63.39"
wire width 32 \main_libresocsim_bus_errors
- attribute \src "ls180.v:53.13-53.47"
+ attribute \src "ls180.v:59.13-59.47"
wire width 32 \main_libresocsim_bus_errors_status
- attribute \src "ls180.v:54.6-54.36"
+ attribute \src "ls180.v:60.6-60.36"
wire \main_libresocsim_bus_errors_we
- attribute \src "ls180.v:142.5-142.40"
+ attribute \src "ls180.v:150.5-150.40"
wire \main_libresocsim_converter0_counter
- attribute \src "ls180.v:1696.5-1696.62"
+ attribute \src "ls180.v:1712.5-1712.62"
wire \main_libresocsim_converter0_counter_converter0_next_value
- attribute \src "ls180.v:1697.5-1697.65"
+ attribute \src "ls180.v:1713.5-1713.65"
wire \main_libresocsim_converter0_counter_converter0_next_value_ce
- attribute \src "ls180.v:144.12-144.45"
+ attribute \src "ls180.v:152.12-152.45"
wire width 64 \main_libresocsim_converter0_dat_r
- attribute \src "ls180.v:143.6-143.39"
+ attribute \src "ls180.v:151.6-151.39"
wire \main_libresocsim_converter0_reset
- attribute \src "ls180.v:141.5-141.37"
+ attribute \src "ls180.v:149.5-149.37"
wire \main_libresocsim_converter0_skip
- attribute \src "ls180.v:157.5-157.40"
+ attribute \src "ls180.v:165.5-165.40"
wire \main_libresocsim_converter1_counter
- attribute \src "ls180.v:1700.5-1700.62"
+ attribute \src "ls180.v:1716.5-1716.62"
wire \main_libresocsim_converter1_counter_converter1_next_value
- attribute \src "ls180.v:1701.5-1701.65"
+ attribute \src "ls180.v:1717.5-1717.65"
wire \main_libresocsim_converter1_counter_converter1_next_value_ce
- attribute \src "ls180.v:159.12-159.45"
+ attribute \src "ls180.v:167.12-167.45"
wire width 64 \main_libresocsim_converter1_dat_r
- attribute \src "ls180.v:158.6-158.39"
+ attribute \src "ls180.v:166.6-166.39"
wire \main_libresocsim_converter1_reset
- attribute \src "ls180.v:156.5-156.37"
+ attribute \src "ls180.v:164.5-164.37"
wire \main_libresocsim_converter1_skip
- attribute \src "ls180.v:172.5-172.40"
+ attribute \src "ls180.v:180.5-180.40"
wire \main_libresocsim_converter2_counter
- attribute \src "ls180.v:1704.5-1704.62"
+ attribute \src "ls180.v:1720.5-1720.62"
wire \main_libresocsim_converter2_counter_converter2_next_value
- attribute \src "ls180.v:1705.5-1705.65"
+ attribute \src "ls180.v:1721.5-1721.65"
wire \main_libresocsim_converter2_counter_converter2_next_value_ce
- attribute \src "ls180.v:174.12-174.45"
+ attribute \src "ls180.v:182.12-182.45"
wire width 64 \main_libresocsim_converter2_dat_r
- attribute \src "ls180.v:173.6-173.39"
+ attribute \src "ls180.v:181.6-181.39"
wire \main_libresocsim_converter2_reset
- attribute \src "ls180.v:171.5-171.37"
+ attribute \src "ls180.v:179.5-179.37"
wire \main_libresocsim_converter2_skip
- attribute \src "ls180.v:187.13-187.35"
+ attribute \src "ls180.v:195.13-195.35"
wire width 32 \main_libresocsim_dat_r
- attribute \src "ls180.v:189.13-189.35"
+ attribute \src "ls180.v:197.13-197.35"
wire width 32 \main_libresocsim_dat_w
- attribute \src "ls180.v:195.5-195.27"
+ attribute \src "ls180.v:203.5-203.27"
wire \main_libresocsim_en_re
- attribute \src "ls180.v:194.5-194.32"
+ attribute \src "ls180.v:202.5-202.32"
wire \main_libresocsim_en_storage
- attribute \src "ls180.v:211.6-211.45"
+ attribute \src "ls180.v:219.6-219.45"
wire \main_libresocsim_eventmanager_pending_r
- attribute \src "ls180.v:210.6-210.46"
+ attribute \src "ls180.v:218.6-218.46"
wire \main_libresocsim_eventmanager_pending_re
- attribute \src "ls180.v:213.6-213.45"
+ attribute \src "ls180.v:221.6-221.45"
wire \main_libresocsim_eventmanager_pending_w
- attribute \src "ls180.v:212.6-212.46"
+ attribute \src "ls180.v:220.6-220.46"
wire \main_libresocsim_eventmanager_pending_we
- attribute \src "ls180.v:215.5-215.37"
+ attribute \src "ls180.v:223.5-223.37"
wire \main_libresocsim_eventmanager_re
- attribute \src "ls180.v:207.6-207.44"
+ attribute \src "ls180.v:215.6-215.44"
wire \main_libresocsim_eventmanager_status_r
- attribute \src "ls180.v:206.6-206.45"
+ attribute \src "ls180.v:214.6-214.45"
wire \main_libresocsim_eventmanager_status_re
- attribute \src "ls180.v:209.6-209.44"
+ attribute \src "ls180.v:217.6-217.44"
wire \main_libresocsim_eventmanager_status_w
- attribute \src "ls180.v:208.6-208.45"
+ attribute \src "ls180.v:216.6-216.45"
wire \main_libresocsim_eventmanager_status_we
- attribute \src "ls180.v:214.5-214.42"
+ attribute \src "ls180.v:222.5-222.42"
wire \main_libresocsim_eventmanager_storage
- attribute \src "ls180.v:136.6-136.57"
+ attribute \src "ls180.v:144.6-144.57"
wire \main_libresocsim_interface0_converted_interface_ack
- attribute \src "ls180.v:130.12-130.63"
+ attribute \src "ls180.v:138.12-138.63"
wire width 30 \main_libresocsim_interface0_converted_interface_adr
- attribute \src "ls180.v:139.11-139.62"
+ attribute \src "ls180.v:147.11-147.62"
wire width 2 \main_libresocsim_interface0_converted_interface_bte
- attribute \src "ls180.v:138.11-138.62"
+ attribute \src "ls180.v:146.11-146.62"
wire width 3 \main_libresocsim_interface0_converted_interface_cti
- attribute \src "ls180.v:134.5-134.56"
+ attribute \src "ls180.v:142.5-142.56"
wire \main_libresocsim_interface0_converted_interface_cyc
- attribute \src "ls180.v:132.13-132.66"
+ attribute \src "ls180.v:140.13-140.66"
wire width 32 \main_libresocsim_interface0_converted_interface_dat_r
- attribute \src "ls180.v:131.12-131.65"
+ attribute \src "ls180.v:139.12-139.65"
wire width 32 \main_libresocsim_interface0_converted_interface_dat_w
- attribute \src "ls180.v:140.6-140.57"
+ attribute \src "ls180.v:148.6-148.57"
wire \main_libresocsim_interface0_converted_interface_err
- attribute \src "ls180.v:133.11-133.62"
+ attribute \src "ls180.v:141.11-141.62"
wire width 4 \main_libresocsim_interface0_converted_interface_sel
- attribute \src "ls180.v:135.5-135.56"
+ attribute \src "ls180.v:143.5-143.56"
wire \main_libresocsim_interface0_converted_interface_stb
- attribute \src "ls180.v:137.5-137.55"
+ attribute \src "ls180.v:145.5-145.55"
wire \main_libresocsim_interface0_converted_interface_we
- attribute \src "ls180.v:151.6-151.57"
+ attribute \src "ls180.v:159.6-159.57"
wire \main_libresocsim_interface1_converted_interface_ack
- attribute \src "ls180.v:145.12-145.63"
+ attribute \src "ls180.v:153.12-153.63"
wire width 30 \main_libresocsim_interface1_converted_interface_adr
- attribute \src "ls180.v:154.11-154.62"
+ attribute \src "ls180.v:162.11-162.62"
wire width 2 \main_libresocsim_interface1_converted_interface_bte
- attribute \src "ls180.v:153.11-153.62"
+ attribute \src "ls180.v:161.11-161.62"
wire width 3 \main_libresocsim_interface1_converted_interface_cti
- attribute \src "ls180.v:149.5-149.56"
+ attribute \src "ls180.v:157.5-157.56"
wire \main_libresocsim_interface1_converted_interface_cyc
- attribute \src "ls180.v:147.13-147.66"
+ attribute \src "ls180.v:155.13-155.66"
wire width 32 \main_libresocsim_interface1_converted_interface_dat_r
- attribute \src "ls180.v:146.12-146.65"
+ attribute \src "ls180.v:154.12-154.65"
wire width 32 \main_libresocsim_interface1_converted_interface_dat_w
- attribute \src "ls180.v:155.6-155.57"
+ attribute \src "ls180.v:163.6-163.57"
wire \main_libresocsim_interface1_converted_interface_err
- attribute \src "ls180.v:148.11-148.62"
+ attribute \src "ls180.v:156.11-156.62"
wire width 4 \main_libresocsim_interface1_converted_interface_sel
- attribute \src "ls180.v:150.5-150.56"
+ attribute \src "ls180.v:158.5-158.56"
wire \main_libresocsim_interface1_converted_interface_stb
- attribute \src "ls180.v:152.5-152.55"
+ attribute \src "ls180.v:160.5-160.55"
wire \main_libresocsim_interface1_converted_interface_we
- attribute \src "ls180.v:166.6-166.57"
+ attribute \src "ls180.v:174.6-174.57"
wire \main_libresocsim_interface2_converted_interface_ack
- attribute \src "ls180.v:160.12-160.63"
+ attribute \src "ls180.v:168.12-168.63"
wire width 30 \main_libresocsim_interface2_converted_interface_adr
- attribute \src "ls180.v:169.11-169.62"
+ attribute \src "ls180.v:177.11-177.62"
wire width 2 \main_libresocsim_interface2_converted_interface_bte
- attribute \src "ls180.v:168.11-168.62"
+ attribute \src "ls180.v:176.11-176.62"
wire width 3 \main_libresocsim_interface2_converted_interface_cti
- attribute \src "ls180.v:164.5-164.56"
+ attribute \src "ls180.v:172.5-172.56"
wire \main_libresocsim_interface2_converted_interface_cyc
- attribute \src "ls180.v:162.13-162.66"
+ attribute \src "ls180.v:170.13-170.66"
wire width 32 \main_libresocsim_interface2_converted_interface_dat_r
- attribute \src "ls180.v:161.12-161.65"
+ attribute \src "ls180.v:169.12-169.65"
wire width 32 \main_libresocsim_interface2_converted_interface_dat_w
- attribute \src "ls180.v:170.6-170.57"
+ attribute \src "ls180.v:178.6-178.57"
wire \main_libresocsim_interface2_converted_interface_err
- attribute \src "ls180.v:163.11-163.62"
+ attribute \src "ls180.v:171.11-171.62"
wire width 4 \main_libresocsim_interface2_converted_interface_sel
- attribute \src "ls180.v:165.5-165.56"
+ attribute \src "ls180.v:173.5-173.56"
wire \main_libresocsim_interface2_converted_interface_stb
- attribute \src "ls180.v:167.5-167.55"
+ attribute \src "ls180.v:175.5-175.55"
wire \main_libresocsim_interface2_converted_interface_we
- attribute \src "ls180.v:200.6-200.26"
+ attribute \src "ls180.v:208.6-208.26"
wire \main_libresocsim_irq
- attribute \src "ls180.v:117.6-117.32"
+ attribute \src "ls180.v:123.6-123.32"
wire \main_libresocsim_libresoc0
- attribute \src "ls180.v:118.6-118.32"
+ attribute \src "ls180.v:124.6-124.32"
wire \main_libresocsim_libresoc1
- attribute \src "ls180.v:119.13-119.39"
+ attribute \src "ls180.v:125.13-125.39"
wire width 64 \main_libresocsim_libresoc2
- attribute \src "ls180.v:122.13-122.65"
+ attribute \src "ls180.v:127.12-127.45"
+ wire width 3 \main_libresocsim_libresoc_clk_sel
+ attribute \src "ls180.v:130.13-130.65"
wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_i
- attribute \src "ls180.v:123.13-123.65"
+ attribute \src "ls180.v:131.13-131.65"
wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_o
- attribute \src "ls180.v:124.13-124.66"
+ attribute \src "ls180.v:132.13-132.66"
wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_oe
- attribute \src "ls180.v:121.6-121.59"
+ attribute \src "ls180.v:129.6-129.59"
wire \main_libresocsim_libresoc_constraintmanager0_uart0_rx
- attribute \src "ls180.v:120.5-120.58"
+ attribute \src "ls180.v:128.5-128.58"
wire \main_libresocsim_libresoc_constraintmanager0_uart0_tx
- attribute \src "ls180.v:127.13-127.65"
+ attribute \src "ls180.v:135.13-135.65"
wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_i
- attribute \src "ls180.v:128.13-128.65"
+ attribute \src "ls180.v:136.13-136.65"
wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_o
- attribute \src "ls180.v:129.13-129.66"
+ attribute \src "ls180.v:137.13-137.66"
wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_oe
- attribute \src "ls180.v:126.6-126.59"
+ attribute \src "ls180.v:134.6-134.59"
wire \main_libresocsim_libresoc_constraintmanager1_uart0_rx
- attribute \src "ls180.v:125.6-125.59"
+ attribute \src "ls180.v:133.6-133.59"
wire \main_libresocsim_libresoc_constraintmanager1_uart0_tx
- attribute \src "ls180.v:66.5-66.39"
+ attribute \src "ls180.v:72.5-72.39"
wire \main_libresocsim_libresoc_dbus_ack
- attribute \src "ls180.v:60.13-60.47"
+ attribute \src "ls180.v:66.13-66.47"
wire width 29 \main_libresocsim_libresoc_dbus_adr
- attribute \src "ls180.v:69.12-69.46"
+ attribute \src "ls180.v:75.12-75.46"
wire width 2 \main_libresocsim_libresoc_dbus_bte
- attribute \src "ls180.v:68.12-68.46"
+ attribute \src "ls180.v:74.12-74.46"
wire width 3 \main_libresocsim_libresoc_dbus_cti
- attribute \src "ls180.v:64.6-64.40"
+ attribute \src "ls180.v:70.6-70.40"
wire \main_libresocsim_libresoc_dbus_cyc
- attribute \src "ls180.v:62.13-62.49"
+ attribute \src "ls180.v:68.13-68.49"
wire width 64 \main_libresocsim_libresoc_dbus_dat_r
- attribute \src "ls180.v:61.13-61.49"
+ attribute \src "ls180.v:67.13-67.49"
wire width 64 \main_libresocsim_libresoc_dbus_dat_w
- attribute \src "ls180.v:70.5-70.39"
+ attribute \src "ls180.v:76.5-76.39"
wire \main_libresocsim_libresoc_dbus_err
- attribute \src "ls180.v:63.12-63.46"
+ attribute \src "ls180.v:69.12-69.46"
wire width 8 \main_libresocsim_libresoc_dbus_sel
- attribute \src "ls180.v:65.6-65.40"
+ attribute \src "ls180.v:71.6-71.40"
wire \main_libresocsim_libresoc_dbus_stb
- attribute \src "ls180.v:67.6-67.39"
+ attribute \src "ls180.v:73.6-73.39"
wire \main_libresocsim_libresoc_dbus_we
- attribute \src "ls180.v:77.5-77.39"
+ attribute \src "ls180.v:83.5-83.39"
wire \main_libresocsim_libresoc_ibus_ack
- attribute \src "ls180.v:71.13-71.47"
+ attribute \src "ls180.v:77.13-77.47"
wire width 29 \main_libresocsim_libresoc_ibus_adr
- attribute \src "ls180.v:80.12-80.46"
+ attribute \src "ls180.v:86.12-86.46"
wire width 2 \main_libresocsim_libresoc_ibus_bte
- attribute \src "ls180.v:79.12-79.46"
+ attribute \src "ls180.v:85.12-85.46"
wire width 3 \main_libresocsim_libresoc_ibus_cti
- attribute \src "ls180.v:75.6-75.40"
+ attribute \src "ls180.v:81.6-81.40"
wire \main_libresocsim_libresoc_ibus_cyc
- attribute \src "ls180.v:73.13-73.49"
+ attribute \src "ls180.v:79.13-79.49"
wire width 64 \main_libresocsim_libresoc_ibus_dat_r
- attribute \src "ls180.v:72.13-72.49"
+ attribute \src "ls180.v:78.13-78.49"
wire width 64 \main_libresocsim_libresoc_ibus_dat_w
- attribute \src "ls180.v:81.5-81.39"
+ attribute \src "ls180.v:87.5-87.39"
wire \main_libresocsim_libresoc_ibus_err
- attribute \src "ls180.v:74.12-74.46"
+ attribute \src "ls180.v:80.12-80.46"
wire width 8 \main_libresocsim_libresoc_ibus_sel
- attribute \src "ls180.v:76.6-76.40"
+ attribute \src "ls180.v:82.6-82.40"
wire \main_libresocsim_libresoc_ibus_stb
- attribute \src "ls180.v:78.6-78.39"
+ attribute \src "ls180.v:84.6-84.39"
wire \main_libresocsim_libresoc_ibus_we
- attribute \src "ls180.v:59.12-59.47"
+ attribute \src "ls180.v:65.12-65.47"
wire width 16 \main_libresocsim_libresoc_interrupt
- attribute \src "ls180.v:113.6-113.40"
+ attribute \src "ls180.v:119.6-119.40"
wire \main_libresocsim_libresoc_jtag_tck
- attribute \src "ls180.v:115.6-115.40"
+ attribute \src "ls180.v:121.6-121.40"
wire \main_libresocsim_libresoc_jtag_tdi
- attribute \src "ls180.v:116.6-116.40"
+ attribute \src "ls180.v:122.6-122.40"
wire \main_libresocsim_libresoc_jtag_tdo
- attribute \src "ls180.v:114.6-114.40"
+ attribute \src "ls180.v:120.6-120.40"
wire \main_libresocsim_libresoc_jtag_tms
- attribute \src "ls180.v:110.5-110.42"
+ attribute \src "ls180.v:116.5-116.42"
wire \main_libresocsim_libresoc_jtag_wb_ack
- attribute \src "ls180.v:104.13-104.50"
+ attribute \src "ls180.v:110.13-110.50"
wire width 29 \main_libresocsim_libresoc_jtag_wb_adr
- attribute \src "ls180.v:108.6-108.43"
+ attribute \src "ls180.v:114.6-114.43"
wire \main_libresocsim_libresoc_jtag_wb_cyc
- attribute \src "ls180.v:106.13-106.52"
+ attribute \src "ls180.v:112.13-112.52"
wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r
- attribute \src "ls180.v:105.13-105.52"
+ attribute \src "ls180.v:111.13-111.52"
wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w
- attribute \src "ls180.v:112.5-112.42"
+ attribute \src "ls180.v:118.5-118.42"
wire \main_libresocsim_libresoc_jtag_wb_err
- attribute \src "ls180.v:107.12-107.49"
+ attribute \src "ls180.v:113.12-113.49"
wire width 8 \main_libresocsim_libresoc_jtag_wb_sel
- attribute \src "ls180.v:109.6-109.43"
+ attribute \src "ls180.v:115.6-115.43"
wire \main_libresocsim_libresoc_jtag_wb_stb
- attribute \src "ls180.v:111.6-111.42"
+ attribute \src "ls180.v:117.6-117.42"
wire \main_libresocsim_libresoc_jtag_wb_we
- attribute \src "ls180.v:58.6-58.37"
+ attribute \src "ls180.v:126.6-126.40"
+ wire \main_libresocsim_libresoc_pll_48_o
+ attribute \src "ls180.v:64.6-64.37"
wire \main_libresocsim_libresoc_reset
- attribute \src "ls180.v:88.6-88.44"
+ attribute \src "ls180.v:94.6-94.44"
wire \main_libresocsim_libresoc_xics_icp_ack
- attribute \src "ls180.v:82.13-82.51"
+ attribute \src "ls180.v:88.13-88.51"
wire width 30 \main_libresocsim_libresoc_xics_icp_adr
- attribute \src "ls180.v:91.12-91.50"
+ attribute \src "ls180.v:97.12-97.50"
wire width 2 \main_libresocsim_libresoc_xics_icp_bte
- attribute \src "ls180.v:90.12-90.50"
+ attribute \src "ls180.v:96.12-96.50"
wire width 3 \main_libresocsim_libresoc_xics_icp_cti
- attribute \src "ls180.v:86.6-86.44"
+ attribute \src "ls180.v:92.6-92.44"
wire \main_libresocsim_libresoc_xics_icp_cyc
- attribute \src "ls180.v:84.13-84.53"
+ attribute \src "ls180.v:90.13-90.53"
wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r
- attribute \src "ls180.v:83.13-83.53"
+ attribute \src "ls180.v:89.13-89.53"
wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w
- attribute \src "ls180.v:92.6-92.44"
+ attribute \src "ls180.v:98.6-98.44"
wire \main_libresocsim_libresoc_xics_icp_err
- attribute \src "ls180.v:85.12-85.50"
+ attribute \src "ls180.v:91.12-91.50"
wire width 4 \main_libresocsim_libresoc_xics_icp_sel
- attribute \src "ls180.v:87.6-87.44"
+ attribute \src "ls180.v:93.6-93.44"
wire \main_libresocsim_libresoc_xics_icp_stb
- attribute \src "ls180.v:89.6-89.43"
+ attribute \src "ls180.v:95.6-95.43"
wire \main_libresocsim_libresoc_xics_icp_we
- attribute \src "ls180.v:99.6-99.44"
+ attribute \src "ls180.v:105.6-105.44"
wire \main_libresocsim_libresoc_xics_ics_ack
- attribute \src "ls180.v:93.13-93.51"
+ attribute \src "ls180.v:99.13-99.51"
wire width 30 \main_libresocsim_libresoc_xics_ics_adr
- attribute \src "ls180.v:102.12-102.50"
+ attribute \src "ls180.v:108.12-108.50"
wire width 2 \main_libresocsim_libresoc_xics_ics_bte
- attribute \src "ls180.v:101.12-101.50"
+ attribute \src "ls180.v:107.12-107.50"
wire width 3 \main_libresocsim_libresoc_xics_ics_cti
- attribute \src "ls180.v:97.6-97.44"
+ attribute \src "ls180.v:103.6-103.44"
wire \main_libresocsim_libresoc_xics_ics_cyc
- attribute \src "ls180.v:95.13-95.53"
+ attribute \src "ls180.v:101.13-101.53"
wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r
- attribute \src "ls180.v:94.13-94.53"
+ attribute \src "ls180.v:100.13-100.53"
wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w
- attribute \src "ls180.v:103.6-103.44"
+ attribute \src "ls180.v:109.6-109.44"
wire \main_libresocsim_libresoc_xics_ics_err
- attribute \src "ls180.v:96.12-96.50"
+ attribute \src "ls180.v:102.12-102.50"
wire width 4 \main_libresocsim_libresoc_xics_ics_sel
- attribute \src "ls180.v:98.6-98.44"
+ attribute \src "ls180.v:104.6-104.44"
wire \main_libresocsim_libresoc_xics_ics_stb
- attribute \src "ls180.v:100.6-100.43"
+ attribute \src "ls180.v:106.6-106.43"
wire \main_libresocsim_libresoc_xics_ics_we
- attribute \src "ls180.v:191.5-191.29"
+ attribute \src "ls180.v:199.5-199.29"
wire \main_libresocsim_load_re
- attribute \src "ls180.v:190.12-190.41"
+ attribute \src "ls180.v:198.12-198.41"
wire width 32 \main_libresocsim_load_storage
- attribute \src "ls180.v:181.5-181.33"
+ attribute \src "ls180.v:189.5-189.33"
wire \main_libresocsim_ram_bus_ack
- attribute \src "ls180.v:175.13-175.41"
+ attribute \src "ls180.v:183.13-183.41"
wire width 30 \main_libresocsim_ram_bus_adr
- attribute \src "ls180.v:184.12-184.40"
+ attribute \src "ls180.v:192.12-192.40"
wire width 2 \main_libresocsim_ram_bus_bte
- attribute \src "ls180.v:183.12-183.40"
+ attribute \src "ls180.v:191.12-191.40"
wire width 3 \main_libresocsim_ram_bus_cti
- attribute \src "ls180.v:179.6-179.34"
+ attribute \src "ls180.v:187.6-187.34"
wire \main_libresocsim_ram_bus_cyc
- attribute \src "ls180.v:177.13-177.43"
+ attribute \src "ls180.v:185.13-185.43"
wire width 32 \main_libresocsim_ram_bus_dat_r
- attribute \src "ls180.v:176.13-176.43"
+ attribute \src "ls180.v:184.13-184.43"
wire width 32 \main_libresocsim_ram_bus_dat_w
- attribute \src "ls180.v:185.5-185.33"
+ attribute \src "ls180.v:193.5-193.33"
wire \main_libresocsim_ram_bus_err
- attribute \src "ls180.v:178.12-178.40"
+ attribute \src "ls180.v:186.12-186.40"
wire width 4 \main_libresocsim_ram_bus_sel
- attribute \src "ls180.v:180.6-180.34"
+ attribute \src "ls180.v:188.6-188.34"
wire \main_libresocsim_ram_bus_stb
- attribute \src "ls180.v:182.6-182.33"
+ attribute \src "ls180.v:190.6-190.33"
wire \main_libresocsim_ram_bus_we
- attribute \src "ls180.v:193.5-193.31"
+ attribute \src "ls180.v:201.5-201.31"
wire \main_libresocsim_reload_re
- attribute \src "ls180.v:192.12-192.43"
+ attribute \src "ls180.v:200.12-200.43"
wire width 32 \main_libresocsim_reload_storage
- attribute \src "ls180.v:55.6-55.28"
+ attribute \src "ls180.v:61.6-61.28"
wire \main_libresocsim_reset
- attribute \src "ls180.v:50.5-50.30"
+ attribute \src "ls180.v:56.5-56.30"
wire \main_libresocsim_reset_re
- attribute \src "ls180.v:49.5-49.35"
+ attribute \src "ls180.v:55.5-55.35"
wire \main_libresocsim_reset_storage
- attribute \src "ls180.v:52.5-52.32"
+ attribute \src "ls180.v:58.5-58.32"
wire \main_libresocsim_scratch_re
- attribute \src "ls180.v:51.12-51.44"
+ attribute \src "ls180.v:57.12-57.44"
wire width 32 \main_libresocsim_scratch_storage
- attribute \src "ls180.v:197.5-197.37"
+ attribute \src "ls180.v:205.5-205.37"
wire \main_libresocsim_update_value_re
- attribute \src "ls180.v:196.5-196.42"
+ attribute \src "ls180.v:204.5-204.42"
wire \main_libresocsim_update_value_storage
- attribute \src "ls180.v:216.12-216.34"
+ attribute \src "ls180.v:224.12-224.34"
wire width 32 \main_libresocsim_value
- attribute \src "ls180.v:198.12-198.41"
+ attribute \src "ls180.v:206.12-206.41"
wire width 32 \main_libresocsim_value_status
- attribute \src "ls180.v:199.6-199.31"
+ attribute \src "ls180.v:207.6-207.31"
wire \main_libresocsim_value_we
- attribute \src "ls180.v:188.11-188.30"
+ attribute \src "ls180.v:196.11-196.30"
wire width 4 \main_libresocsim_we
- attribute \src "ls180.v:204.5-204.32"
+ attribute \src "ls180.v:212.5-212.32"
wire \main_libresocsim_zero_clear
- attribute \src "ls180.v:205.5-205.38"
+ attribute \src "ls180.v:213.5-213.38"
wire \main_libresocsim_zero_old_trigger
- attribute \src "ls180.v:202.5-202.34"
+ attribute \src "ls180.v:210.5-210.34"
wire \main_libresocsim_zero_pending
- attribute \src "ls180.v:201.6-201.34"
+ attribute \src "ls180.v:209.6-209.34"
wire \main_libresocsim_zero_status
- attribute \src "ls180.v:203.6-203.35"
+ attribute \src "ls180.v:211.6-211.35"
wire \main_libresocsim_zero_trigger
- attribute \src "ls180.v:798.6-798.26"
+ attribute \src "ls180.v:806.6-806.26"
wire \main_litedram_wb_ack
- attribute \src "ls180.v:792.12-792.32"
+ attribute \src "ls180.v:800.12-800.32"
wire width 30 \main_litedram_wb_adr
- attribute \src "ls180.v:796.5-796.25"
+ attribute \src "ls180.v:804.5-804.25"
wire \main_litedram_wb_cyc
- attribute \src "ls180.v:794.13-794.35"
+ attribute \src "ls180.v:802.13-802.35"
wire width 16 \main_litedram_wb_dat_r
- attribute \src "ls180.v:793.12-793.34"
+ attribute \src "ls180.v:801.12-801.34"
wire width 16 \main_litedram_wb_dat_w
- attribute \src "ls180.v:795.11-795.31"
+ attribute \src "ls180.v:803.11-803.31"
wire width 2 \main_litedram_wb_sel
- attribute \src "ls180.v:797.5-797.25"
+ attribute \src "ls180.v:805.5-805.25"
wire \main_litedram_wb_stb
- attribute \src "ls180.v:799.5-799.24"
+ attribute \src "ls180.v:807.5-807.24"
wire \main_litedram_wb_we
- attribute \src "ls180.v:996.13-996.20"
- wire width 42 \main_nc
- attribute \src "ls180.v:827.12-827.37"
- wire width 32 \main_phase_accumulator_rx
- attribute \src "ls180.v:817.12-817.37"
- wire width 32 \main_phase_accumulator_tx
- attribute \src "ls180.v:771.6-771.24"
+ attribute \src "ls180.v:1004.13-1004.20"
+ wire width 36 \main_nc
+ attribute \src "ls180.v:779.6-779.24"
wire \main_port_cmd_last
- attribute \src "ls180.v:773.13-773.39"
+ attribute \src "ls180.v:781.13-781.39"
wire width 24 \main_port_cmd_payload_addr
- attribute \src "ls180.v:772.6-772.30"
+ attribute \src "ls180.v:780.6-780.30"
wire \main_port_cmd_payload_we
- attribute \src "ls180.v:770.6-770.25"
+ attribute \src "ls180.v:778.6-778.25"
wire \main_port_cmd_ready
- attribute \src "ls180.v:769.6-769.25"
+ attribute \src "ls180.v:777.6-777.25"
wire \main_port_cmd_valid
- attribute \src "ls180.v:768.6-768.21"
+ attribute \src "ls180.v:776.6-776.21"
wire \main_port_flush
- attribute \src "ls180.v:780.13-780.41"
+ attribute \src "ls180.v:788.13-788.41"
wire width 16 \main_port_rdata_payload_data
- attribute \src "ls180.v:779.6-779.27"
+ attribute \src "ls180.v:787.6-787.27"
wire \main_port_rdata_ready
- attribute \src "ls180.v:778.6-778.27"
+ attribute \src "ls180.v:786.6-786.27"
wire \main_port_rdata_valid
- attribute \src "ls180.v:776.13-776.41"
+ attribute \src "ls180.v:784.13-784.41"
wire width 16 \main_port_wdata_payload_data
- attribute \src "ls180.v:777.12-777.38"
+ attribute \src "ls180.v:785.12-785.38"
wire width 2 \main_port_wdata_payload_we
- attribute \src "ls180.v:775.6-775.27"
+ attribute \src "ls180.v:783.6-783.27"
wire \main_port_wdata_ready
- attribute \src "ls180.v:774.6-774.27"
+ attribute \src "ls180.v:782.6-782.27"
wire \main_port_wdata_valid
- attribute \src "ls180.v:1001.12-1001.29"
+ attribute \src "ls180.v:1009.12-1009.29"
wire width 32 \main_pwm0_counter
- attribute \src "ls180.v:998.6-998.22"
+ attribute \src "ls180.v:1006.6-1006.22"
wire \main_pwm0_enable
- attribute \src "ls180.v:1003.5-1003.24"
+ attribute \src "ls180.v:1011.5-1011.24"
wire \main_pwm0_enable_re
- attribute \src "ls180.v:1002.5-1002.29"
+ attribute \src "ls180.v:1010.5-1010.29"
wire \main_pwm0_enable_storage
- attribute \src "ls180.v:1000.13-1000.29"
+ attribute \src "ls180.v:1008.13-1008.29"
wire width 32 \main_pwm0_period
- attribute \src "ls180.v:1007.5-1007.24"
+ attribute \src "ls180.v:1015.5-1015.24"
wire \main_pwm0_period_re
- attribute \src "ls180.v:1006.12-1006.36"
+ attribute \src "ls180.v:1014.12-1014.36"
wire width 32 \main_pwm0_period_storage
- attribute \src "ls180.v:999.13-999.28"
+ attribute \src "ls180.v:1007.13-1007.28"
wire width 32 \main_pwm0_width
- attribute \src "ls180.v:1005.5-1005.23"
+ attribute \src "ls180.v:1013.5-1013.23"
wire \main_pwm0_width_re
- attribute \src "ls180.v:1004.12-1004.35"
+ attribute \src "ls180.v:1012.12-1012.35"
wire width 32 \main_pwm0_width_storage
- attribute \src "ls180.v:1011.12-1011.29"
+ attribute \src "ls180.v:1019.12-1019.29"
wire width 32 \main_pwm1_counter
- attribute \src "ls180.v:1008.6-1008.22"
+ attribute \src "ls180.v:1016.6-1016.22"
wire \main_pwm1_enable
- attribute \src "ls180.v:1013.5-1013.24"
+ attribute \src "ls180.v:1021.5-1021.24"
wire \main_pwm1_enable_re
- attribute \src "ls180.v:1012.5-1012.29"
+ attribute \src "ls180.v:1020.5-1020.29"
wire \main_pwm1_enable_storage
- attribute \src "ls180.v:1010.13-1010.29"
+ attribute \src "ls180.v:1018.13-1018.29"
wire width 32 \main_pwm1_period
- attribute \src "ls180.v:1017.5-1017.24"
+ attribute \src "ls180.v:1025.5-1025.24"
wire \main_pwm1_period_re
- attribute \src "ls180.v:1016.12-1016.36"
+ attribute \src "ls180.v:1024.12-1024.36"
wire width 32 \main_pwm1_period_storage
- attribute \src "ls180.v:1009.13-1009.28"
+ attribute \src "ls180.v:1017.13-1017.28"
wire width 32 \main_pwm1_width
- attribute \src "ls180.v:1015.5-1015.23"
+ attribute \src "ls180.v:1023.5-1023.23"
wire \main_pwm1_width_re
- attribute \src "ls180.v:1014.12-1014.35"
+ attribute \src "ls180.v:1022.12-1022.35"
wire width 32 \main_pwm1_width_storage
- attribute \src "ls180.v:237.11-237.25"
+ attribute \src "ls180.v:245.11-245.25"
wire width 3 \main_rddata_en
- attribute \src "ls180.v:810.5-810.12"
- wire \main_re
- attribute \src "ls180.v:828.6-828.13"
- wire \main_rx
- attribute \src "ls180.v:831.11-831.27"
- wire width 4 \main_rx_bitcount
- attribute \src "ls180.v:832.5-832.17"
- wire \main_rx_busy
- attribute \src "ls180.v:829.5-829.14"
- wire \main_rx_r
- attribute \src "ls180.v:830.11-830.22"
- wire width 8 \main_rx_reg
- attribute \src "ls180.v:1531.11-1531.43"
+ attribute \src "ls180.v:1547.11-1547.43"
wire width 2 \main_sdblock2mem_converter_demux
- attribute \src "ls180.v:1532.6-1532.42"
+ attribute \src "ls180.v:1548.6-1548.42"
wire \main_sdblock2mem_converter_load_part
- attribute \src "ls180.v:1522.6-1522.43"
+ attribute \src "ls180.v:1538.6-1538.43"
wire \main_sdblock2mem_converter_sink_first
- attribute \src "ls180.v:1523.6-1523.42"
+ attribute \src "ls180.v:1539.6-1539.42"
wire \main_sdblock2mem_converter_sink_last
- attribute \src "ls180.v:1524.12-1524.56"
+ attribute \src "ls180.v:1540.12-1540.56"
wire width 8 \main_sdblock2mem_converter_sink_payload_data
- attribute \src "ls180.v:1521.6-1521.43"
+ attribute \src "ls180.v:1537.6-1537.43"
wire \main_sdblock2mem_converter_sink_ready
- attribute \src "ls180.v:1520.6-1520.43"
+ attribute \src "ls180.v:1536.6-1536.43"
wire \main_sdblock2mem_converter_sink_valid
- attribute \src "ls180.v:1527.5-1527.44"
+ attribute \src "ls180.v:1543.5-1543.44"
wire \main_sdblock2mem_converter_source_first
- attribute \src "ls180.v:1528.5-1528.43"
+ attribute \src "ls180.v:1544.5-1544.43"
wire \main_sdblock2mem_converter_source_last
- attribute \src "ls180.v:1529.12-1529.58"
+ attribute \src "ls180.v:1545.12-1545.58"
wire width 32 \main_sdblock2mem_converter_source_payload_data
- attribute \src "ls180.v:1530.11-1530.70"
+ attribute \src "ls180.v:1546.11-1546.70"
wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count
- attribute \src "ls180.v:1526.6-1526.45"
+ attribute \src "ls180.v:1542.6-1542.45"
wire \main_sdblock2mem_converter_source_ready
- attribute \src "ls180.v:1525.6-1525.45"
+ attribute \src "ls180.v:1541.6-1541.45"
wire \main_sdblock2mem_converter_source_valid
- attribute \src "ls180.v:1533.5-1533.42"
+ attribute \src "ls180.v:1549.5-1549.42"
wire \main_sdblock2mem_converter_strobe_all
- attribute \src "ls180.v:1506.11-1506.40"
+ attribute \src "ls180.v:1522.11-1522.40"
wire width 5 \main_sdblock2mem_fifo_consume
- attribute \src "ls180.v:1511.6-1511.35"
+ attribute \src "ls180.v:1527.6-1527.35"
wire \main_sdblock2mem_fifo_do_read
- attribute \src "ls180.v:1515.6-1515.41"
+ attribute \src "ls180.v:1531.6-1531.41"
wire \main_sdblock2mem_fifo_fifo_in_first
- attribute \src "ls180.v:1516.6-1516.40"
+ attribute \src "ls180.v:1532.6-1532.40"
wire \main_sdblock2mem_fifo_fifo_in_last
- attribute \src "ls180.v:1514.12-1514.54"
+ attribute \src "ls180.v:1530.12-1530.54"
wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data
- attribute \src "ls180.v:1518.6-1518.42"
+ attribute \src "ls180.v:1534.6-1534.42"
wire \main_sdblock2mem_fifo_fifo_out_first
- attribute \src "ls180.v:1519.6-1519.41"
+ attribute \src "ls180.v:1535.6-1535.41"
wire \main_sdblock2mem_fifo_fifo_out_last
- attribute \src "ls180.v:1517.12-1517.55"
+ attribute \src "ls180.v:1533.12-1533.55"
wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data
- attribute \src "ls180.v:1503.11-1503.38"
+ attribute \src "ls180.v:1519.11-1519.38"
wire width 6 \main_sdblock2mem_fifo_level
- attribute \src "ls180.v:1505.11-1505.40"
+ attribute \src "ls180.v:1521.11-1521.40"
wire width 5 \main_sdblock2mem_fifo_produce
- attribute \src "ls180.v:1512.12-1512.44"
+ attribute \src "ls180.v:1528.12-1528.44"
wire width 5 \main_sdblock2mem_fifo_rdport_adr
- attribute \src "ls180.v:1513.12-1513.46"
+ attribute \src "ls180.v:1529.12-1529.46"
wire width 10 \main_sdblock2mem_fifo_rdport_dat_r
- attribute \src "ls180.v:1504.5-1504.34"
+ attribute \src "ls180.v:1520.5-1520.34"
wire \main_sdblock2mem_fifo_replace
- attribute \src "ls180.v:1489.6-1489.38"
+ attribute \src "ls180.v:1505.6-1505.38"
wire \main_sdblock2mem_fifo_sink_first
- attribute \src "ls180.v:1490.6-1490.37"
+ attribute \src "ls180.v:1506.6-1506.37"
wire \main_sdblock2mem_fifo_sink_last
- attribute \src "ls180.v:1491.12-1491.51"
+ attribute \src "ls180.v:1507.12-1507.51"
wire width 8 \main_sdblock2mem_fifo_sink_payload_data
- attribute \src "ls180.v:1488.6-1488.38"
+ attribute \src "ls180.v:1504.6-1504.38"
wire \main_sdblock2mem_fifo_sink_ready
- attribute \src "ls180.v:1487.6-1487.38"
+ attribute \src "ls180.v:1503.6-1503.38"
wire \main_sdblock2mem_fifo_sink_valid
- attribute \src "ls180.v:1494.6-1494.40"
+ attribute \src "ls180.v:1510.6-1510.40"
wire \main_sdblock2mem_fifo_source_first
- attribute \src "ls180.v:1495.6-1495.39"
+ attribute \src "ls180.v:1511.6-1511.39"
wire \main_sdblock2mem_fifo_source_last
- attribute \src "ls180.v:1496.12-1496.53"
+ attribute \src "ls180.v:1512.12-1512.53"
wire width 8 \main_sdblock2mem_fifo_source_payload_data
- attribute \src "ls180.v:1493.6-1493.40"
+ attribute \src "ls180.v:1509.6-1509.40"
wire \main_sdblock2mem_fifo_source_ready
- attribute \src "ls180.v:1492.6-1492.40"
+ attribute \src "ls180.v:1508.6-1508.40"
wire \main_sdblock2mem_fifo_source_valid
- attribute \src "ls180.v:1501.12-1501.46"
+ attribute \src "ls180.v:1517.12-1517.46"
wire width 10 \main_sdblock2mem_fifo_syncfifo_din
- attribute \src "ls180.v:1502.12-1502.47"
+ attribute \src "ls180.v:1518.12-1518.47"
wire width 10 \main_sdblock2mem_fifo_syncfifo_dout
- attribute \src "ls180.v:1499.6-1499.39"
+ attribute \src "ls180.v:1515.6-1515.39"
wire \main_sdblock2mem_fifo_syncfifo_re
- attribute \src "ls180.v:1500.6-1500.45"
+ attribute \src "ls180.v:1516.6-1516.45"
wire \main_sdblock2mem_fifo_syncfifo_readable
- attribute \src "ls180.v:1497.6-1497.39"
+ attribute \src "ls180.v:1513.6-1513.39"
wire \main_sdblock2mem_fifo_syncfifo_we
- attribute \src "ls180.v:1498.6-1498.45"
+ attribute \src "ls180.v:1514.6-1514.45"
wire \main_sdblock2mem_fifo_syncfifo_writable
- attribute \src "ls180.v:1507.11-1507.43"
+ attribute \src "ls180.v:1523.11-1523.43"
wire width 5 \main_sdblock2mem_fifo_wrport_adr
- attribute \src "ls180.v:1508.12-1508.46"
+ attribute \src "ls180.v:1524.12-1524.46"
wire width 10 \main_sdblock2mem_fifo_wrport_dat_r
- attribute \src "ls180.v:1510.12-1510.46"
+ attribute \src "ls180.v:1526.12-1526.46"
wire width 10 \main_sdblock2mem_fifo_wrport_dat_w
- attribute \src "ls180.v:1509.6-1509.37"
+ attribute \src "ls180.v:1525.6-1525.37"
wire \main_sdblock2mem_fifo_wrport_we
- attribute \src "ls180.v:1484.6-1484.38"
+ attribute \src "ls180.v:1500.6-1500.38"
wire \main_sdblock2mem_sink_sink_first
- attribute \src "ls180.v:1485.6-1485.37"
+ attribute \src "ls180.v:1501.6-1501.37"
wire \main_sdblock2mem_sink_sink_last
- attribute \src "ls180.v:1541.12-1541.54"
+ attribute \src "ls180.v:1557.12-1557.54"
wire width 32 \main_sdblock2mem_sink_sink_payload_address
- attribute \src "ls180.v:1486.12-1486.52"
+ attribute \src "ls180.v:1502.12-1502.52"
wire width 8 \main_sdblock2mem_sink_sink_payload_data0
- attribute \src "ls180.v:1542.12-1542.52"
+ attribute \src "ls180.v:1558.12-1558.52"
wire width 32 \main_sdblock2mem_sink_sink_payload_data1
- attribute \src "ls180.v:1483.6-1483.39"
+ attribute \src "ls180.v:1499.6-1499.39"
wire \main_sdblock2mem_sink_sink_ready0
- attribute \src "ls180.v:1540.6-1540.39"
+ attribute \src "ls180.v:1556.6-1556.39"
wire \main_sdblock2mem_sink_sink_ready1
- attribute \src "ls180.v:1482.6-1482.39"
+ attribute \src "ls180.v:1498.6-1498.39"
wire \main_sdblock2mem_sink_sink_valid0
- attribute \src "ls180.v:1539.5-1539.38"
+ attribute \src "ls180.v:1555.5-1555.38"
wire \main_sdblock2mem_sink_sink_valid1
- attribute \src "ls180.v:1536.6-1536.42"
+ attribute \src "ls180.v:1552.6-1552.42"
wire \main_sdblock2mem_source_source_first
- attribute \src "ls180.v:1537.6-1537.41"
+ attribute \src "ls180.v:1553.6-1553.41"
wire \main_sdblock2mem_source_source_last
- attribute \src "ls180.v:1538.13-1538.56"
+ attribute \src "ls180.v:1554.13-1554.56"
wire width 32 \main_sdblock2mem_source_source_payload_data
- attribute \src "ls180.v:1535.6-1535.42"
+ attribute \src "ls180.v:1551.6-1551.42"
wire \main_sdblock2mem_source_source_ready
- attribute \src "ls180.v:1534.6-1534.42"
+ attribute \src "ls180.v:1550.6-1550.42"
wire \main_sdblock2mem_source_source_valid
- attribute \src "ls180.v:1558.13-1558.52"
+ attribute \src "ls180.v:1574.13-1574.52"
wire width 32 \main_sdblock2mem_wishbonedmawriter_base
- attribute \src "ls180.v:1549.5-1549.47"
+ attribute \src "ls180.v:1565.5-1565.47"
wire \main_sdblock2mem_wishbonedmawriter_base_re
- attribute \src "ls180.v:1548.12-1548.59"
+ attribute \src "ls180.v:1564.12-1564.59"
wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage
- attribute \src "ls180.v:1553.5-1553.49"
+ attribute \src "ls180.v:1569.5-1569.49"
wire \main_sdblock2mem_wishbonedmawriter_enable_re
- attribute \src "ls180.v:1552.5-1552.54"
+ attribute \src "ls180.v:1568.5-1568.54"
wire \main_sdblock2mem_wishbonedmawriter_enable_storage
- attribute \src "ls180.v:1560.13-1560.54"
+ attribute \src "ls180.v:1576.13-1576.54"
wire width 32 \main_sdblock2mem_wishbonedmawriter_length
- attribute \src "ls180.v:1551.5-1551.49"
+ attribute \src "ls180.v:1567.5-1567.49"
wire \main_sdblock2mem_wishbonedmawriter_length_re
- attribute \src "ls180.v:1550.12-1550.61"
+ attribute \src "ls180.v:1566.12-1566.61"
wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage
- attribute \src "ls180.v:1557.5-1557.47"
+ attribute \src "ls180.v:1573.5-1573.47"
wire \main_sdblock2mem_wishbonedmawriter_loop_re
- attribute \src "ls180.v:1556.5-1556.52"
+ attribute \src "ls180.v:1572.5-1572.52"
wire \main_sdblock2mem_wishbonedmawriter_loop_storage
- attribute \src "ls180.v:1559.12-1559.53"
+ attribute \src "ls180.v:1575.12-1575.53"
wire width 32 \main_sdblock2mem_wishbonedmawriter_offset
- attribute \src "ls180.v:1813.12-1813.79"
+ attribute \src "ls180.v:1829.12-1829.79"
wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value
- attribute \src "ls180.v:1814.5-1814.75"
+ attribute \src "ls180.v:1830.5-1830.75"
wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce
- attribute \src "ls180.v:1561.6-1561.46"
+ attribute \src "ls180.v:1577.6-1577.46"
wire \main_sdblock2mem_wishbonedmawriter_reset
- attribute \src "ls180.v:1545.6-1545.51"
+ attribute \src "ls180.v:1561.6-1561.51"
wire \main_sdblock2mem_wishbonedmawriter_sink_first
- attribute \src "ls180.v:1546.6-1546.50"
+ attribute \src "ls180.v:1562.6-1562.50"
wire \main_sdblock2mem_wishbonedmawriter_sink_last
- attribute \src "ls180.v:1547.13-1547.65"
+ attribute \src "ls180.v:1563.13-1563.65"
wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data
- attribute \src "ls180.v:1544.5-1544.50"
+ attribute \src "ls180.v:1560.5-1560.50"
wire \main_sdblock2mem_wishbonedmawriter_sink_ready
- attribute \src "ls180.v:1543.6-1543.51"
+ attribute \src "ls180.v:1559.6-1559.51"
wire \main_sdblock2mem_wishbonedmawriter_sink_valid
- attribute \src "ls180.v:1554.5-1554.46"
+ attribute \src "ls180.v:1570.5-1570.46"
wire \main_sdblock2mem_wishbonedmawriter_status
- attribute \src "ls180.v:1555.6-1555.43"
+ attribute \src "ls180.v:1571.6-1571.43"
wire \main_sdblock2mem_wishbonedmawriter_we
- attribute \src "ls180.v:1323.5-1323.31"
+ attribute \src "ls180.v:1339.5-1339.31"
wire \main_sdcore_block_count_re
- attribute \src "ls180.v:1322.12-1322.43"
+ attribute \src "ls180.v:1338.12-1338.43"
wire width 32 \main_sdcore_block_count_storage
- attribute \src "ls180.v:1321.5-1321.32"
+ attribute \src "ls180.v:1337.5-1337.32"
wire \main_sdcore_block_length_re
- attribute \src "ls180.v:1320.11-1320.43"
+ attribute \src "ls180.v:1336.11-1336.43"
wire width 10 \main_sdcore_block_length_storage
- attribute \src "ls180.v:1307.5-1307.32"
+ attribute \src "ls180.v:1323.5-1323.32"
wire \main_sdcore_cmd_argument_re
- attribute \src "ls180.v:1306.12-1306.44"
+ attribute \src "ls180.v:1322.12-1322.44"
wire width 32 \main_sdcore_cmd_argument_storage
- attribute \src "ls180.v:1309.5-1309.31"
+ attribute \src "ls180.v:1325.5-1325.31"
wire \main_sdcore_cmd_command_re
- attribute \src "ls180.v:1308.12-1308.43"
+ attribute \src "ls180.v:1324.12-1324.43"
wire width 32 \main_sdcore_cmd_command_storage
- attribute \src "ls180.v:1462.11-1462.32"
+ attribute \src "ls180.v:1478.11-1478.32"
wire width 3 \main_sdcore_cmd_count
- attribute \src "ls180.v:1797.11-1797.55"
+ attribute \src "ls180.v:1813.11-1813.55"
wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2
- attribute \src "ls180.v:1798.5-1798.52"
+ attribute \src "ls180.v:1814.5-1814.52"
wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2
- attribute \src "ls180.v:1463.5-1463.25"
+ attribute \src "ls180.v:1479.5-1479.25"
wire \main_sdcore_cmd_done
- attribute \src "ls180.v:1793.5-1793.48"
+ attribute \src "ls180.v:1809.5-1809.48"
wire \main_sdcore_cmd_done_sdcore_fsm_next_value0
- attribute \src "ls180.v:1794.5-1794.51"
+ attribute \src "ls180.v:1810.5-1810.51"
wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0
- attribute \src "ls180.v:1464.5-1464.26"
+ attribute \src "ls180.v:1480.5-1480.26"
wire \main_sdcore_cmd_error
- attribute \src "ls180.v:1801.5-1801.49"
+ attribute \src "ls180.v:1817.5-1817.49"
wire \main_sdcore_cmd_error_sdcore_fsm_next_value4
- attribute \src "ls180.v:1802.5-1802.52"
+ attribute \src "ls180.v:1818.5-1818.52"
wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4
- attribute \src "ls180.v:1316.12-1316.40"
+ attribute \src "ls180.v:1332.12-1332.40"
wire width 4 \main_sdcore_cmd_event_status
- attribute \src "ls180.v:1317.6-1317.30"
+ attribute \src "ls180.v:1333.6-1333.30"
wire \main_sdcore_cmd_event_we
- attribute \src "ls180.v:1314.13-1314.44"
+ attribute \src "ls180.v:1330.13-1330.44"
wire width 128 \main_sdcore_cmd_response_status
- attribute \src "ls180.v:1809.13-1809.67"
+ attribute \src "ls180.v:1825.13-1825.67"
wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8
- attribute \src "ls180.v:1810.5-1810.62"
+ attribute \src "ls180.v:1826.5-1826.62"
wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8
- attribute \src "ls180.v:1315.6-1315.33"
+ attribute \src "ls180.v:1331.6-1331.33"
wire \main_sdcore_cmd_response_we
- attribute \src "ls180.v:1311.6-1311.28"
+ attribute \src "ls180.v:1327.6-1327.28"
wire \main_sdcore_cmd_send_r
- attribute \src "ls180.v:1310.6-1310.29"
+ attribute \src "ls180.v:1326.6-1326.29"
wire \main_sdcore_cmd_send_re
- attribute \src "ls180.v:1313.5-1313.27"
+ attribute \src "ls180.v:1329.5-1329.27"
wire \main_sdcore_cmd_send_w
- attribute \src "ls180.v:1312.6-1312.29"
+ attribute \src "ls180.v:1328.6-1328.29"
wire \main_sdcore_cmd_send_we
- attribute \src "ls180.v:1465.5-1465.28"
+ attribute \src "ls180.v:1481.5-1481.28"
wire \main_sdcore_cmd_timeout
- attribute \src "ls180.v:1803.5-1803.51"
+ attribute \src "ls180.v:1819.5-1819.51"
wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5
- attribute \src "ls180.v:1804.5-1804.54"
+ attribute \src "ls180.v:1820.5-1820.54"
wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5
- attribute \src "ls180.v:1461.12-1461.32"
+ attribute \src "ls180.v:1477.12-1477.32"
wire width 2 \main_sdcore_cmd_type
- attribute \src "ls180.v:1423.11-1423.40"
+ attribute \src "ls180.v:1439.11-1439.40"
wire width 4 \main_sdcore_crc16_checker_cnt
- attribute \src "ls180.v:1429.5-1429.39"
+ attribute \src "ls180.v:1445.5-1445.39"
wire \main_sdcore_crc16_checker_crc0_clr
- attribute \src "ls180.v:1428.12-1428.46"
+ attribute \src "ls180.v:1444.12-1444.46"
wire width 16 \main_sdcore_crc16_checker_crc0_crc
- attribute \src "ls180.v:1424.12-1424.50"
+ attribute \src "ls180.v:1440.12-1440.50"
wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0
- attribute \src "ls180.v:1425.13-1425.51"
+ attribute \src "ls180.v:1441.13-1441.51"
wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1
- attribute \src "ls180.v:1426.13-1426.51"
+ attribute \src "ls180.v:1442.13-1442.51"
wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2
- attribute \src "ls180.v:1430.6-1430.43"
+ attribute \src "ls180.v:1446.6-1446.43"
wire \main_sdcore_crc16_checker_crc0_enable
- attribute \src "ls180.v:1427.12-1427.46"
+ attribute \src "ls180.v:1443.12-1443.46"
wire width 2 \main_sdcore_crc16_checker_crc0_val
- attribute \src "ls180.v:1436.5-1436.39"
+ attribute \src "ls180.v:1452.5-1452.39"
wire \main_sdcore_crc16_checker_crc1_clr
- attribute \src "ls180.v:1435.12-1435.46"
+ attribute \src "ls180.v:1451.12-1451.46"
wire width 16 \main_sdcore_crc16_checker_crc1_crc
- attribute \src "ls180.v:1431.12-1431.50"
+ attribute \src "ls180.v:1447.12-1447.50"
wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0
- attribute \src "ls180.v:1432.13-1432.51"
+ attribute \src "ls180.v:1448.13-1448.51"
wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1
- attribute \src "ls180.v:1433.13-1433.51"
+ attribute \src "ls180.v:1449.13-1449.51"
wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2
- attribute \src "ls180.v:1437.6-1437.43"
+ attribute \src "ls180.v:1453.6-1453.43"
wire \main_sdcore_crc16_checker_crc1_enable
- attribute \src "ls180.v:1434.12-1434.46"
+ attribute \src "ls180.v:1450.12-1450.46"
wire width 2 \main_sdcore_crc16_checker_crc1_val
- attribute \src "ls180.v:1443.5-1443.39"
+ attribute \src "ls180.v:1459.5-1459.39"
wire \main_sdcore_crc16_checker_crc2_clr
- attribute \src "ls180.v:1442.12-1442.46"
+ attribute \src "ls180.v:1458.12-1458.46"
wire width 16 \main_sdcore_crc16_checker_crc2_crc
- attribute \src "ls180.v:1438.12-1438.50"
+ attribute \src "ls180.v:1454.12-1454.50"
wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0
- attribute \src "ls180.v:1439.13-1439.51"
+ attribute \src "ls180.v:1455.13-1455.51"
wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1
- attribute \src "ls180.v:1440.13-1440.51"
+ attribute \src "ls180.v:1456.13-1456.51"
wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2
- attribute \src "ls180.v:1444.6-1444.43"
+ attribute \src "ls180.v:1460.6-1460.43"
wire \main_sdcore_crc16_checker_crc2_enable
- attribute \src "ls180.v:1441.12-1441.46"
+ attribute \src "ls180.v:1457.12-1457.46"
wire width 2 \main_sdcore_crc16_checker_crc2_val
- attribute \src "ls180.v:1450.5-1450.39"
+ attribute \src "ls180.v:1466.5-1466.39"
wire \main_sdcore_crc16_checker_crc3_clr
- attribute \src "ls180.v:1449.12-1449.46"
+ attribute \src "ls180.v:1465.12-1465.46"
wire width 16 \main_sdcore_crc16_checker_crc3_crc
- attribute \src "ls180.v:1445.12-1445.50"
+ attribute \src "ls180.v:1461.12-1461.50"
wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0
- attribute \src "ls180.v:1446.13-1446.51"
+ attribute \src "ls180.v:1462.13-1462.51"
wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1
- attribute \src "ls180.v:1447.13-1447.51"
+ attribute \src "ls180.v:1463.13-1463.51"
wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2
- attribute \src "ls180.v:1451.6-1451.43"
+ attribute \src "ls180.v:1467.6-1467.43"
wire \main_sdcore_crc16_checker_crc3_enable
- attribute \src "ls180.v:1448.12-1448.46"
+ attribute \src "ls180.v:1464.12-1464.46"
wire width 2 \main_sdcore_crc16_checker_crc3_val
- attribute \src "ls180.v:1452.12-1452.45"
+ attribute \src "ls180.v:1468.12-1468.45"
wire width 16 \main_sdcore_crc16_checker_crctmp0
- attribute \src "ls180.v:1453.12-1453.45"
+ attribute \src "ls180.v:1469.12-1469.45"
wire width 16 \main_sdcore_crc16_checker_crctmp1
- attribute \src "ls180.v:1454.12-1454.45"
+ attribute \src "ls180.v:1470.12-1470.45"
wire width 16 \main_sdcore_crc16_checker_crctmp2
- attribute \src "ls180.v:1455.12-1455.45"
+ attribute \src "ls180.v:1471.12-1471.45"
wire width 16 \main_sdcore_crc16_checker_crctmp3
- attribute \src "ls180.v:1457.12-1457.43"
+ attribute \src "ls180.v:1473.12-1473.43"
wire width 16 \main_sdcore_crc16_checker_fifo0
- attribute \src "ls180.v:1458.12-1458.43"
+ attribute \src "ls180.v:1474.12-1474.43"
wire width 16 \main_sdcore_crc16_checker_fifo1
- attribute \src "ls180.v:1459.12-1459.43"
+ attribute \src "ls180.v:1475.12-1475.43"
wire width 16 \main_sdcore_crc16_checker_fifo2
- attribute \src "ls180.v:1460.12-1460.43"
+ attribute \src "ls180.v:1476.12-1476.43"
wire width 16 \main_sdcore_crc16_checker_fifo3
- attribute \src "ls180.v:1414.5-1414.41"
+ attribute \src "ls180.v:1430.5-1430.41"
wire \main_sdcore_crc16_checker_sink_first
- attribute \src "ls180.v:1415.5-1415.40"
+ attribute \src "ls180.v:1431.5-1431.40"
wire \main_sdcore_crc16_checker_sink_last
- attribute \src "ls180.v:1416.11-1416.54"
+ attribute \src "ls180.v:1432.11-1432.54"
wire width 8 \main_sdcore_crc16_checker_sink_payload_data
- attribute \src "ls180.v:1413.5-1413.41"
+ attribute \src "ls180.v:1429.5-1429.41"
wire \main_sdcore_crc16_checker_sink_ready
- attribute \src "ls180.v:1412.5-1412.41"
+ attribute \src "ls180.v:1428.5-1428.41"
wire \main_sdcore_crc16_checker_sink_valid
- attribute \src "ls180.v:1419.5-1419.43"
+ attribute \src "ls180.v:1435.5-1435.43"
wire \main_sdcore_crc16_checker_source_first
- attribute \src "ls180.v:1420.6-1420.43"
+ attribute \src "ls180.v:1436.6-1436.43"
wire \main_sdcore_crc16_checker_source_last
- attribute \src "ls180.v:1421.12-1421.57"
+ attribute \src "ls180.v:1437.12-1437.57"
wire width 8 \main_sdcore_crc16_checker_source_payload_data
- attribute \src "ls180.v:1418.6-1418.44"
+ attribute \src "ls180.v:1434.6-1434.44"
wire \main_sdcore_crc16_checker_source_ready
- attribute \src "ls180.v:1417.5-1417.43"
+ attribute \src "ls180.v:1433.5-1433.43"
wire \main_sdcore_crc16_checker_source_valid
- attribute \src "ls180.v:1422.11-1422.40"
+ attribute \src "ls180.v:1438.11-1438.40"
wire width 8 \main_sdcore_crc16_checker_val
- attribute \src "ls180.v:1456.5-1456.36"
+ attribute \src "ls180.v:1472.5-1472.36"
wire \main_sdcore_crc16_checker_valid
- attribute \src "ls180.v:1379.11-1379.41"
+ attribute \src "ls180.v:1395.11-1395.41"
wire width 3 \main_sdcore_crc16_inserter_cnt
- attribute \src "ls180.v:1789.11-1789.80"
+ attribute \src "ls180.v:1805.11-1805.80"
wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4
- attribute \src "ls180.v:1790.5-1790.77"
+ attribute \src "ls180.v:1806.5-1806.77"
wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4
- attribute \src "ls180.v:1385.6-1385.41"
+ attribute \src "ls180.v:1401.6-1401.41"
wire \main_sdcore_crc16_inserter_crc0_clr
- attribute \src "ls180.v:1384.12-1384.47"
+ attribute \src "ls180.v:1400.12-1400.47"
wire width 16 \main_sdcore_crc16_inserter_crc0_crc
- attribute \src "ls180.v:1380.12-1380.51"
+ attribute \src "ls180.v:1396.12-1396.51"
wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0
- attribute \src "ls180.v:1381.13-1381.52"
+ attribute \src "ls180.v:1397.13-1397.52"
wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1
- attribute \src "ls180.v:1382.13-1382.52"
+ attribute \src "ls180.v:1398.13-1398.52"
wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2
- attribute \src "ls180.v:1386.6-1386.44"
+ attribute \src "ls180.v:1402.6-1402.44"
wire \main_sdcore_crc16_inserter_crc0_enable
- attribute \src "ls180.v:1383.12-1383.47"
+ attribute \src "ls180.v:1399.12-1399.47"
wire width 2 \main_sdcore_crc16_inserter_crc0_val
- attribute \src "ls180.v:1392.6-1392.41"
+ attribute \src "ls180.v:1408.6-1408.41"
wire \main_sdcore_crc16_inserter_crc1_clr
- attribute \src "ls180.v:1391.12-1391.47"
+ attribute \src "ls180.v:1407.12-1407.47"
wire width 16 \main_sdcore_crc16_inserter_crc1_crc
- attribute \src "ls180.v:1387.12-1387.51"
+ attribute \src "ls180.v:1403.12-1403.51"
wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0
- attribute \src "ls180.v:1388.13-1388.52"
+ attribute \src "ls180.v:1404.13-1404.52"
wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1
- attribute \src "ls180.v:1389.13-1389.52"
+ attribute \src "ls180.v:1405.13-1405.52"
wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2
- attribute \src "ls180.v:1393.6-1393.44"
+ attribute \src "ls180.v:1409.6-1409.44"
wire \main_sdcore_crc16_inserter_crc1_enable
- attribute \src "ls180.v:1390.12-1390.47"
+ attribute \src "ls180.v:1406.12-1406.47"
wire width 2 \main_sdcore_crc16_inserter_crc1_val
- attribute \src "ls180.v:1399.6-1399.41"
+ attribute \src "ls180.v:1415.6-1415.41"
wire \main_sdcore_crc16_inserter_crc2_clr
- attribute \src "ls180.v:1398.12-1398.47"
+ attribute \src "ls180.v:1414.12-1414.47"
wire width 16 \main_sdcore_crc16_inserter_crc2_crc
- attribute \src "ls180.v:1394.12-1394.51"
+ attribute \src "ls180.v:1410.12-1410.51"
wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0
- attribute \src "ls180.v:1395.13-1395.52"
+ attribute \src "ls180.v:1411.13-1411.52"
wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1
- attribute \src "ls180.v:1396.13-1396.52"
+ attribute \src "ls180.v:1412.13-1412.52"
wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2
- attribute \src "ls180.v:1400.6-1400.44"
+ attribute \src "ls180.v:1416.6-1416.44"
wire \main_sdcore_crc16_inserter_crc2_enable
- attribute \src "ls180.v:1397.12-1397.47"
+ attribute \src "ls180.v:1413.12-1413.47"
wire width 2 \main_sdcore_crc16_inserter_crc2_val
- attribute \src "ls180.v:1406.6-1406.41"
+ attribute \src "ls180.v:1422.6-1422.41"
wire \main_sdcore_crc16_inserter_crc3_clr
- attribute \src "ls180.v:1405.12-1405.47"
+ attribute \src "ls180.v:1421.12-1421.47"
wire width 16 \main_sdcore_crc16_inserter_crc3_crc
- attribute \src "ls180.v:1401.12-1401.51"
+ attribute \src "ls180.v:1417.12-1417.51"
wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0
- attribute \src "ls180.v:1402.13-1402.52"
+ attribute \src "ls180.v:1418.13-1418.52"
wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1
- attribute \src "ls180.v:1403.13-1403.52"
+ attribute \src "ls180.v:1419.13-1419.52"
wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2
- attribute \src "ls180.v:1407.6-1407.44"
+ attribute \src "ls180.v:1423.6-1423.44"
wire \main_sdcore_crc16_inserter_crc3_enable
- attribute \src "ls180.v:1404.12-1404.47"
+ attribute \src "ls180.v:1420.12-1420.47"
wire width 2 \main_sdcore_crc16_inserter_crc3_val
- attribute \src "ls180.v:1408.12-1408.46"
+ attribute \src "ls180.v:1424.12-1424.46"
wire width 16 \main_sdcore_crc16_inserter_crctmp0
- attribute \src "ls180.v:1781.12-1781.85"
+ attribute \src "ls180.v:1797.12-1797.85"
wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0
- attribute \src "ls180.v:1782.5-1782.81"
+ attribute \src "ls180.v:1798.5-1798.81"
wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0
- attribute \src "ls180.v:1409.12-1409.46"
+ attribute \src "ls180.v:1425.12-1425.46"
wire width 16 \main_sdcore_crc16_inserter_crctmp1
- attribute \src "ls180.v:1783.12-1783.85"
+ attribute \src "ls180.v:1799.12-1799.85"
wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1
- attribute \src "ls180.v:1784.5-1784.81"
+ attribute \src "ls180.v:1800.5-1800.81"
wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1
- attribute \src "ls180.v:1410.12-1410.46"
+ attribute \src "ls180.v:1426.12-1426.46"
wire width 16 \main_sdcore_crc16_inserter_crctmp2
- attribute \src "ls180.v:1785.12-1785.85"
+ attribute \src "ls180.v:1801.12-1801.85"
wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2
- attribute \src "ls180.v:1786.5-1786.81"
+ attribute \src "ls180.v:1802.5-1802.81"
wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2
- attribute \src "ls180.v:1411.12-1411.46"
+ attribute \src "ls180.v:1427.12-1427.46"
wire width 16 \main_sdcore_crc16_inserter_crctmp3
- attribute \src "ls180.v:1787.12-1787.85"
+ attribute \src "ls180.v:1803.12-1803.85"
wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3
- attribute \src "ls180.v:1788.5-1788.81"
+ attribute \src "ls180.v:1804.5-1804.81"
wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3
- attribute \src "ls180.v:1371.6-1371.43"
+ attribute \src "ls180.v:1387.6-1387.43"
wire \main_sdcore_crc16_inserter_sink_first
- attribute \src "ls180.v:1372.6-1372.42"
+ attribute \src "ls180.v:1388.6-1388.42"
wire \main_sdcore_crc16_inserter_sink_last
- attribute \src "ls180.v:1373.12-1373.56"
+ attribute \src "ls180.v:1389.12-1389.56"
wire width 8 \main_sdcore_crc16_inserter_sink_payload_data
- attribute \src "ls180.v:1370.5-1370.42"
+ attribute \src "ls180.v:1386.5-1386.42"
wire \main_sdcore_crc16_inserter_sink_ready
- attribute \src "ls180.v:1369.6-1369.43"
+ attribute \src "ls180.v:1385.6-1385.43"
wire \main_sdcore_crc16_inserter_sink_valid
- attribute \src "ls180.v:1376.5-1376.44"
+ attribute \src "ls180.v:1392.5-1392.44"
wire \main_sdcore_crc16_inserter_source_first
- attribute \src "ls180.v:1377.5-1377.43"
+ attribute \src "ls180.v:1393.5-1393.43"
wire \main_sdcore_crc16_inserter_source_last
- attribute \src "ls180.v:1378.11-1378.57"
+ attribute \src "ls180.v:1394.11-1394.57"
wire width 8 \main_sdcore_crc16_inserter_source_payload_data
- attribute \src "ls180.v:1375.5-1375.44"
+ attribute \src "ls180.v:1391.5-1391.44"
wire \main_sdcore_crc16_inserter_source_ready
- attribute \src "ls180.v:1374.5-1374.44"
+ attribute \src "ls180.v:1390.5-1390.44"
wire \main_sdcore_crc16_inserter_source_valid
- attribute \src "ls180.v:1367.6-1367.35"
+ attribute \src "ls180.v:1383.6-1383.35"
wire \main_sdcore_crc7_inserter_clr
- attribute \src "ls180.v:1366.11-1366.40"
+ attribute \src "ls180.v:1382.11-1382.40"
wire width 7 \main_sdcore_crc7_inserter_crc
- attribute \src "ls180.v:1324.11-1324.44"
+ attribute \src "ls180.v:1340.11-1340.44"
wire width 7 \main_sdcore_crc7_inserter_crcreg0
- attribute \src "ls180.v:1325.12-1325.45"
+ attribute \src "ls180.v:1341.12-1341.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg1
- attribute \src "ls180.v:1334.12-1334.46"
+ attribute \src "ls180.v:1350.12-1350.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg10
- attribute \src "ls180.v:1335.12-1335.46"
+ attribute \src "ls180.v:1351.12-1351.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg11
- attribute \src "ls180.v:1336.12-1336.46"
+ attribute \src "ls180.v:1352.12-1352.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg12
- attribute \src "ls180.v:1337.12-1337.46"
+ attribute \src "ls180.v:1353.12-1353.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg13
- attribute \src "ls180.v:1338.12-1338.46"
+ attribute \src "ls180.v:1354.12-1354.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg14
- attribute \src "ls180.v:1339.12-1339.46"
+ attribute \src "ls180.v:1355.12-1355.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg15
- attribute \src "ls180.v:1340.12-1340.46"
+ attribute \src "ls180.v:1356.12-1356.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg16
- attribute \src "ls180.v:1341.12-1341.46"
+ attribute \src "ls180.v:1357.12-1357.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg17
- attribute \src "ls180.v:1342.12-1342.46"
+ attribute \src "ls180.v:1358.12-1358.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg18
- attribute \src "ls180.v:1343.12-1343.46"
+ attribute \src "ls180.v:1359.12-1359.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg19
- attribute \src "ls180.v:1326.12-1326.45"
+ attribute \src "ls180.v:1342.12-1342.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg2
- attribute \src "ls180.v:1344.12-1344.46"
+ attribute \src "ls180.v:1360.12-1360.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg20
- attribute \src "ls180.v:1345.12-1345.46"
+ attribute \src "ls180.v:1361.12-1361.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg21
- attribute \src "ls180.v:1346.12-1346.46"
+ attribute \src "ls180.v:1362.12-1362.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg22
- attribute \src "ls180.v:1347.12-1347.46"
+ attribute \src "ls180.v:1363.12-1363.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg23
- attribute \src "ls180.v:1348.12-1348.46"
+ attribute \src "ls180.v:1364.12-1364.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg24
- attribute \src "ls180.v:1349.12-1349.46"
+ attribute \src "ls180.v:1365.12-1365.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg25
- attribute \src "ls180.v:1350.12-1350.46"
+ attribute \src "ls180.v:1366.12-1366.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg26
- attribute \src "ls180.v:1351.12-1351.46"
+ attribute \src "ls180.v:1367.12-1367.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg27
- attribute \src "ls180.v:1352.12-1352.46"
+ attribute \src "ls180.v:1368.12-1368.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg28
- attribute \src "ls180.v:1353.12-1353.46"
+ attribute \src "ls180.v:1369.12-1369.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg29
- attribute \src "ls180.v:1327.12-1327.45"
+ attribute \src "ls180.v:1343.12-1343.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg3
- attribute \src "ls180.v:1354.12-1354.46"
+ attribute \src "ls180.v:1370.12-1370.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg30
- attribute \src "ls180.v:1355.12-1355.46"
+ attribute \src "ls180.v:1371.12-1371.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg31
- attribute \src "ls180.v:1356.12-1356.46"
+ attribute \src "ls180.v:1372.12-1372.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg32
- attribute \src "ls180.v:1357.12-1357.46"
+ attribute \src "ls180.v:1373.12-1373.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg33
- attribute \src "ls180.v:1358.12-1358.46"
+ attribute \src "ls180.v:1374.12-1374.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg34
- attribute \src "ls180.v:1359.12-1359.46"
+ attribute \src "ls180.v:1375.12-1375.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg35
- attribute \src "ls180.v:1360.12-1360.46"
+ attribute \src "ls180.v:1376.12-1376.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg36
- attribute \src "ls180.v:1361.12-1361.46"
+ attribute \src "ls180.v:1377.12-1377.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg37
- attribute \src "ls180.v:1362.12-1362.46"
+ attribute \src "ls180.v:1378.12-1378.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg38
- attribute \src "ls180.v:1363.12-1363.46"
+ attribute \src "ls180.v:1379.12-1379.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg39
- attribute \src "ls180.v:1328.12-1328.45"
+ attribute \src "ls180.v:1344.12-1344.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg4
- attribute \src "ls180.v:1364.12-1364.46"
+ attribute \src "ls180.v:1380.12-1380.46"
wire width 7 \main_sdcore_crc7_inserter_crcreg40
- attribute \src "ls180.v:1329.12-1329.45"
+ attribute \src "ls180.v:1345.12-1345.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg5
- attribute \src "ls180.v:1330.12-1330.45"
+ attribute \src "ls180.v:1346.12-1346.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg6
- attribute \src "ls180.v:1331.12-1331.45"
+ attribute \src "ls180.v:1347.12-1347.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg7
- attribute \src "ls180.v:1332.12-1332.45"
+ attribute \src "ls180.v:1348.12-1348.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg8
- attribute \src "ls180.v:1333.12-1333.45"
+ attribute \src "ls180.v:1349.12-1349.45"
wire width 7 \main_sdcore_crc7_inserter_crcreg9
- attribute \src "ls180.v:1368.6-1368.38"
+ attribute \src "ls180.v:1384.6-1384.38"
wire \main_sdcore_crc7_inserter_enable
- attribute \src "ls180.v:1365.13-1365.42"
+ attribute \src "ls180.v:1381.13-1381.42"
wire width 40 \main_sdcore_crc7_inserter_val
- attribute \src "ls180.v:1467.12-1467.34"
+ attribute \src "ls180.v:1483.12-1483.34"
wire width 32 \main_sdcore_data_count
- attribute \src "ls180.v:1799.12-1799.57"
+ attribute \src "ls180.v:1815.12-1815.57"
wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3
- attribute \src "ls180.v:1800.5-1800.53"
+ attribute \src "ls180.v:1816.5-1816.53"
wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3
- attribute \src "ls180.v:1468.5-1468.26"
+ attribute \src "ls180.v:1484.5-1484.26"
wire \main_sdcore_data_done
- attribute \src "ls180.v:1795.5-1795.49"
+ attribute \src "ls180.v:1811.5-1811.49"
wire \main_sdcore_data_done_sdcore_fsm_next_value1
- attribute \src "ls180.v:1796.5-1796.52"
+ attribute \src "ls180.v:1812.5-1812.52"
wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1
- attribute \src "ls180.v:1469.5-1469.27"
+ attribute \src "ls180.v:1485.5-1485.27"
wire \main_sdcore_data_error
- attribute \src "ls180.v:1805.5-1805.50"
+ attribute \src "ls180.v:1821.5-1821.50"
wire \main_sdcore_data_error_sdcore_fsm_next_value6
- attribute \src "ls180.v:1806.5-1806.53"
+ attribute \src "ls180.v:1822.5-1822.53"
wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6
- attribute \src "ls180.v:1318.12-1318.41"
+ attribute \src "ls180.v:1334.12-1334.41"
wire width 4 \main_sdcore_data_event_status
- attribute \src "ls180.v:1319.6-1319.31"
+ attribute \src "ls180.v:1335.6-1335.31"
wire \main_sdcore_data_event_we
- attribute \src "ls180.v:1470.5-1470.29"
+ attribute \src "ls180.v:1486.5-1486.29"
wire \main_sdcore_data_timeout
- attribute \src "ls180.v:1807.5-1807.52"
+ attribute \src "ls180.v:1823.5-1823.52"
wire \main_sdcore_data_timeout_sdcore_fsm_next_value7
- attribute \src "ls180.v:1808.5-1808.55"
+ attribute \src "ls180.v:1824.5-1824.55"
wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7
- attribute \src "ls180.v:1466.12-1466.33"
+ attribute \src "ls180.v:1482.12-1482.33"
wire width 2 \main_sdcore_data_type
- attribute \src "ls180.v:1298.6-1298.33"
+ attribute \src "ls180.v:1314.6-1314.33"
wire \main_sdcore_sink_sink_first
- attribute \src "ls180.v:1299.6-1299.32"
+ attribute \src "ls180.v:1315.6-1315.32"
wire \main_sdcore_sink_sink_last
- attribute \src "ls180.v:1300.12-1300.46"
+ attribute \src "ls180.v:1316.12-1316.46"
wire width 8 \main_sdcore_sink_sink_payload_data
- attribute \src "ls180.v:1297.6-1297.33"
+ attribute \src "ls180.v:1313.6-1313.33"
wire \main_sdcore_sink_sink_ready
- attribute \src "ls180.v:1296.6-1296.33"
+ attribute \src "ls180.v:1312.6-1312.33"
wire \main_sdcore_sink_sink_valid
- attribute \src "ls180.v:1303.6-1303.37"
+ attribute \src "ls180.v:1319.6-1319.37"
wire \main_sdcore_source_source_first
- attribute \src "ls180.v:1304.6-1304.36"
+ attribute \src "ls180.v:1320.6-1320.36"
wire \main_sdcore_source_source_last
- attribute \src "ls180.v:1305.12-1305.50"
+ attribute \src "ls180.v:1321.12-1321.50"
wire width 8 \main_sdcore_source_source_payload_data
- attribute \src "ls180.v:1302.6-1302.37"
+ attribute \src "ls180.v:1318.6-1318.37"
wire \main_sdcore_source_source_ready
- attribute \src "ls180.v:1301.6-1301.37"
+ attribute \src "ls180.v:1317.6-1317.37"
wire \main_sdcore_source_source_valid
- attribute \src "ls180.v:1616.6-1616.38"
+ attribute \src "ls180.v:1632.6-1632.38"
wire \main_sdmem2block_converter_first
- attribute \src "ls180.v:1617.6-1617.37"
+ attribute \src "ls180.v:1633.6-1633.37"
wire \main_sdmem2block_converter_last
- attribute \src "ls180.v:1615.11-1615.41"
+ attribute \src "ls180.v:1631.11-1631.41"
wire width 2 \main_sdmem2block_converter_mux
- attribute \src "ls180.v:1606.6-1606.43"
+ attribute \src "ls180.v:1622.6-1622.43"
wire \main_sdmem2block_converter_sink_first
- attribute \src "ls180.v:1607.6-1607.42"
+ attribute \src "ls180.v:1623.6-1623.42"
wire \main_sdmem2block_converter_sink_last
- attribute \src "ls180.v:1608.13-1608.57"
+ attribute \src "ls180.v:1624.13-1624.57"
wire width 32 \main_sdmem2block_converter_sink_payload_data
- attribute \src "ls180.v:1605.6-1605.43"
+ attribute \src "ls180.v:1621.6-1621.43"
wire \main_sdmem2block_converter_sink_ready
- attribute \src "ls180.v:1604.6-1604.43"
+ attribute \src "ls180.v:1620.6-1620.43"
wire \main_sdmem2block_converter_sink_valid
- attribute \src "ls180.v:1611.6-1611.45"
+ attribute \src "ls180.v:1627.6-1627.45"
wire \main_sdmem2block_converter_source_first
- attribute \src "ls180.v:1612.6-1612.44"
+ attribute \src "ls180.v:1628.6-1628.44"
wire \main_sdmem2block_converter_source_last
- attribute \src "ls180.v:1613.11-1613.57"
+ attribute \src "ls180.v:1629.11-1629.57"
wire width 8 \main_sdmem2block_converter_source_payload_data
- attribute \src "ls180.v:1614.6-1614.65"
+ attribute \src "ls180.v:1630.6-1630.65"
wire \main_sdmem2block_converter_source_payload_valid_token_count
- attribute \src "ls180.v:1610.6-1610.45"
+ attribute \src "ls180.v:1626.6-1626.45"
wire \main_sdmem2block_converter_source_ready
- attribute \src "ls180.v:1609.6-1609.45"
+ attribute \src "ls180.v:1625.6-1625.45"
wire \main_sdmem2block_converter_source_valid
- attribute \src "ls180.v:1600.13-1600.38"
+ attribute \src "ls180.v:1616.13-1616.38"
wire width 32 \main_sdmem2block_dma_base
- attribute \src "ls180.v:1589.5-1589.33"
+ attribute \src "ls180.v:1605.5-1605.33"
wire \main_sdmem2block_dma_base_re
- attribute \src "ls180.v:1588.12-1588.45"
+ attribute \src "ls180.v:1604.12-1604.45"
wire width 64 \main_sdmem2block_dma_base_storage
- attribute \src "ls180.v:1587.12-1587.37"
+ attribute \src "ls180.v:1603.12-1603.37"
wire width 32 \main_sdmem2block_dma_data
- attribute \src "ls180.v:1817.12-1817.67"
+ attribute \src "ls180.v:1833.12-1833.67"
wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value
- attribute \src "ls180.v:1818.5-1818.63"
+ attribute \src "ls180.v:1834.5-1834.63"
wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce
- attribute \src "ls180.v:1594.5-1594.37"
+ attribute \src "ls180.v:1610.5-1610.37"
wire \main_sdmem2block_dma_done_status
- attribute \src "ls180.v:1595.6-1595.34"
+ attribute \src "ls180.v:1611.6-1611.34"
wire \main_sdmem2block_dma_done_we
- attribute \src "ls180.v:1593.5-1593.35"
+ attribute \src "ls180.v:1609.5-1609.35"
wire \main_sdmem2block_dma_enable_re
- attribute \src "ls180.v:1592.5-1592.40"
+ attribute \src "ls180.v:1608.5-1608.40"
wire \main_sdmem2block_dma_enable_storage
- attribute \src "ls180.v:1602.13-1602.40"
+ attribute \src "ls180.v:1618.13-1618.40"
wire width 32 \main_sdmem2block_dma_length
- attribute \src "ls180.v:1591.5-1591.35"
+ attribute \src "ls180.v:1607.5-1607.35"
wire \main_sdmem2block_dma_length_re
- attribute \src "ls180.v:1590.12-1590.47"
+ attribute \src "ls180.v:1606.12-1606.47"
wire width 32 \main_sdmem2block_dma_length_storage
- attribute \src "ls180.v:1597.5-1597.33"
+ attribute \src "ls180.v:1613.5-1613.33"
wire \main_sdmem2block_dma_loop_re
- attribute \src "ls180.v:1596.5-1596.38"
+ attribute \src "ls180.v:1612.5-1612.38"
wire \main_sdmem2block_dma_loop_storage
- attribute \src "ls180.v:1601.12-1601.39"
+ attribute \src "ls180.v:1617.12-1617.39"
wire width 32 \main_sdmem2block_dma_offset
- attribute \src "ls180.v:1821.12-1821.79"
+ attribute \src "ls180.v:1837.12-1837.79"
wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value
- attribute \src "ls180.v:1822.5-1822.75"
+ attribute \src "ls180.v:1838.5-1838.75"
wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce
- attribute \src "ls180.v:1598.13-1598.47"
+ attribute \src "ls180.v:1614.13-1614.47"
wire width 32 \main_sdmem2block_dma_offset_status
- attribute \src "ls180.v:1599.6-1599.36"
+ attribute \src "ls180.v:1615.6-1615.36"
wire \main_sdmem2block_dma_offset_we
- attribute \src "ls180.v:1603.6-1603.32"
+ attribute \src "ls180.v:1619.6-1619.32"
wire \main_sdmem2block_dma_reset
- attribute \src "ls180.v:1580.5-1580.35"
+ attribute \src "ls180.v:1596.5-1596.35"
wire \main_sdmem2block_dma_sink_last
- attribute \src "ls180.v:1581.12-1581.53"
+ attribute \src "ls180.v:1597.12-1597.53"
wire width 32 \main_sdmem2block_dma_sink_payload_address
- attribute \src "ls180.v:1579.5-1579.36"
+ attribute \src "ls180.v:1595.5-1595.36"
wire \main_sdmem2block_dma_sink_ready
- attribute \src "ls180.v:1578.5-1578.36"
+ attribute \src "ls180.v:1594.5-1594.36"
wire \main_sdmem2block_dma_sink_valid
- attribute \src "ls180.v:1584.5-1584.38"
+ attribute \src "ls180.v:1600.5-1600.38"
wire \main_sdmem2block_dma_source_first
- attribute \src "ls180.v:1585.5-1585.37"
+ attribute \src "ls180.v:1601.5-1601.37"
wire \main_sdmem2block_dma_source_last
- attribute \src "ls180.v:1586.12-1586.52"
+ attribute \src "ls180.v:1602.12-1602.52"
wire width 32 \main_sdmem2block_dma_source_payload_data
- attribute \src "ls180.v:1583.6-1583.39"
+ attribute \src "ls180.v:1599.6-1599.39"
wire \main_sdmem2block_dma_source_ready
- attribute \src "ls180.v:1582.5-1582.38"
+ attribute \src "ls180.v:1598.5-1598.38"
wire \main_sdmem2block_dma_source_valid
- attribute \src "ls180.v:1642.11-1642.40"
+ attribute \src "ls180.v:1658.11-1658.40"
wire width 5 \main_sdmem2block_fifo_consume
- attribute \src "ls180.v:1647.6-1647.35"
+ attribute \src "ls180.v:1663.6-1663.35"
wire \main_sdmem2block_fifo_do_read
- attribute \src "ls180.v:1651.6-1651.41"
+ attribute \src "ls180.v:1667.6-1667.41"
wire \main_sdmem2block_fifo_fifo_in_first
- attribute \src "ls180.v:1652.6-1652.40"
+ attribute \src "ls180.v:1668.6-1668.40"
wire \main_sdmem2block_fifo_fifo_in_last
- attribute \src "ls180.v:1650.12-1650.54"
+ attribute \src "ls180.v:1666.12-1666.54"
wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data
- attribute \src "ls180.v:1654.6-1654.42"
+ attribute \src "ls180.v:1670.6-1670.42"
wire \main_sdmem2block_fifo_fifo_out_first
- attribute \src "ls180.v:1655.6-1655.41"
+ attribute \src "ls180.v:1671.6-1671.41"
wire \main_sdmem2block_fifo_fifo_out_last
- attribute \src "ls180.v:1653.12-1653.55"
+ attribute \src "ls180.v:1669.12-1669.55"
wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data
- attribute \src "ls180.v:1639.11-1639.38"
+ attribute \src "ls180.v:1655.11-1655.38"
wire width 6 \main_sdmem2block_fifo_level
- attribute \src "ls180.v:1641.11-1641.40"
+ attribute \src "ls180.v:1657.11-1657.40"
wire width 5 \main_sdmem2block_fifo_produce
- attribute \src "ls180.v:1648.12-1648.44"
+ attribute \src "ls180.v:1664.12-1664.44"
wire width 5 \main_sdmem2block_fifo_rdport_adr
- attribute \src "ls180.v:1649.12-1649.46"
+ attribute \src "ls180.v:1665.12-1665.46"
wire width 10 \main_sdmem2block_fifo_rdport_dat_r
- attribute \src "ls180.v:1640.5-1640.34"
+ attribute \src "ls180.v:1656.5-1656.34"
wire \main_sdmem2block_fifo_replace
- attribute \src "ls180.v:1625.6-1625.38"
+ attribute \src "ls180.v:1641.6-1641.38"
wire \main_sdmem2block_fifo_sink_first
- attribute \src "ls180.v:1626.6-1626.37"
+ attribute \src "ls180.v:1642.6-1642.37"
wire \main_sdmem2block_fifo_sink_last
- attribute \src "ls180.v:1627.12-1627.51"
+ attribute \src "ls180.v:1643.12-1643.51"
wire width 8 \main_sdmem2block_fifo_sink_payload_data
- attribute \src "ls180.v:1624.6-1624.38"
+ attribute \src "ls180.v:1640.6-1640.38"
wire \main_sdmem2block_fifo_sink_ready
- attribute \src "ls180.v:1623.6-1623.38"
+ attribute \src "ls180.v:1639.6-1639.38"
wire \main_sdmem2block_fifo_sink_valid
- attribute \src "ls180.v:1630.6-1630.40"
+ attribute \src "ls180.v:1646.6-1646.40"
wire \main_sdmem2block_fifo_source_first
- attribute \src "ls180.v:1631.6-1631.39"
+ attribute \src "ls180.v:1647.6-1647.39"
wire \main_sdmem2block_fifo_source_last
- attribute \src "ls180.v:1632.12-1632.53"
+ attribute \src "ls180.v:1648.12-1648.53"
wire width 8 \main_sdmem2block_fifo_source_payload_data
- attribute \src "ls180.v:1629.6-1629.40"
+ attribute \src "ls180.v:1645.6-1645.40"
wire \main_sdmem2block_fifo_source_ready
- attribute \src "ls180.v:1628.6-1628.40"
+ attribute \src "ls180.v:1644.6-1644.40"
wire \main_sdmem2block_fifo_source_valid
- attribute \src "ls180.v:1637.12-1637.46"
+ attribute \src "ls180.v:1653.12-1653.46"
wire width 10 \main_sdmem2block_fifo_syncfifo_din
- attribute \src "ls180.v:1638.12-1638.47"
+ attribute \src "ls180.v:1654.12-1654.47"
wire width 10 \main_sdmem2block_fifo_syncfifo_dout
- attribute \src "ls180.v:1635.6-1635.39"
+ attribute \src "ls180.v:1651.6-1651.39"
wire \main_sdmem2block_fifo_syncfifo_re
- attribute \src "ls180.v:1636.6-1636.45"
+ attribute \src "ls180.v:1652.6-1652.45"
wire \main_sdmem2block_fifo_syncfifo_readable
- attribute \src "ls180.v:1633.6-1633.39"
+ attribute \src "ls180.v:1649.6-1649.39"
wire \main_sdmem2block_fifo_syncfifo_we
- attribute \src "ls180.v:1634.6-1634.45"
+ attribute \src "ls180.v:1650.6-1650.45"
wire \main_sdmem2block_fifo_syncfifo_writable
- attribute \src "ls180.v:1643.11-1643.43"
+ attribute \src "ls180.v:1659.11-1659.43"
wire width 5 \main_sdmem2block_fifo_wrport_adr
- attribute \src "ls180.v:1644.12-1644.46"
+ attribute \src "ls180.v:1660.12-1660.46"
wire width 10 \main_sdmem2block_fifo_wrport_dat_r
- attribute \src "ls180.v:1646.12-1646.46"
+ attribute \src "ls180.v:1662.12-1662.46"
wire width 10 \main_sdmem2block_fifo_wrport_dat_w
- attribute \src "ls180.v:1645.6-1645.37"
+ attribute \src "ls180.v:1661.6-1661.37"
wire \main_sdmem2block_fifo_wrport_we
- attribute \src "ls180.v:1575.6-1575.43"
+ attribute \src "ls180.v:1591.6-1591.43"
wire \main_sdmem2block_source_source_first0
- attribute \src "ls180.v:1620.6-1620.43"
+ attribute \src "ls180.v:1636.6-1636.43"
wire \main_sdmem2block_source_source_first1
- attribute \src "ls180.v:1576.6-1576.42"
+ attribute \src "ls180.v:1592.6-1592.42"
wire \main_sdmem2block_source_source_last0
- attribute \src "ls180.v:1621.6-1621.42"
+ attribute \src "ls180.v:1637.6-1637.42"
wire \main_sdmem2block_source_source_last1
- attribute \src "ls180.v:1577.12-1577.56"
+ attribute \src "ls180.v:1593.12-1593.56"
wire width 8 \main_sdmem2block_source_source_payload_data0
- attribute \src "ls180.v:1622.12-1622.56"
+ attribute \src "ls180.v:1638.12-1638.56"
wire width 8 \main_sdmem2block_source_source_payload_data1
- attribute \src "ls180.v:1574.6-1574.43"
+ attribute \src "ls180.v:1590.6-1590.43"
wire \main_sdmem2block_source_source_ready0
- attribute \src "ls180.v:1619.6-1619.43"
+ attribute \src "ls180.v:1635.6-1635.43"
wire \main_sdmem2block_source_source_ready1
- attribute \src "ls180.v:1573.6-1573.43"
+ attribute \src "ls180.v:1589.6-1589.43"
wire \main_sdmem2block_source_source_valid0
- attribute \src "ls180.v:1618.6-1618.43"
+ attribute \src "ls180.v:1634.6-1634.43"
wire \main_sdmem2block_source_source_valid1
- attribute \src "ls180.v:1024.6-1024.27"
+ attribute \src "ls180.v:1040.6-1040.27"
wire \main_sdphy_clocker_ce
- attribute \src "ls180.v:1023.5-1023.28"
+ attribute \src "ls180.v:1039.5-1039.28"
wire \main_sdphy_clocker_clk0
- attribute \src "ls180.v:1026.5-1026.28"
+ attribute \src "ls180.v:1042.5-1042.28"
wire \main_sdphy_clocker_clk1
- attribute \src "ls180.v:1027.5-1027.29"
+ attribute \src "ls180.v:1043.5-1043.29"
wire \main_sdphy_clocker_clk_d
- attribute \src "ls180.v:1025.11-1025.34"
+ attribute \src "ls180.v:1041.11-1041.34"
wire width 9 \main_sdphy_clocker_clks
- attribute \src "ls180.v:1021.5-1021.26"
+ attribute \src "ls180.v:1037.5-1037.26"
wire \main_sdphy_clocker_re
- attribute \src "ls180.v:1022.6-1022.29"
+ attribute \src "ls180.v:1038.6-1038.29"
wire \main_sdphy_clocker_stop
- attribute \src "ls180.v:1020.11-1020.37"
+ attribute \src "ls180.v:1036.11-1036.37"
wire width 9 \main_sdphy_clocker_storage
- attribute \src "ls180.v:1124.6-1124.41"
+ attribute \src "ls180.v:1140.6-1140.41"
wire \main_sdphy_cmdr_cmdr_buf_sink_first
- attribute \src "ls180.v:1125.6-1125.40"
+ attribute \src "ls180.v:1141.6-1141.40"
wire \main_sdphy_cmdr_cmdr_buf_sink_last
- attribute \src "ls180.v:1126.12-1126.54"
+ attribute \src "ls180.v:1142.12-1142.54"
wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data
- attribute \src "ls180.v:1123.6-1123.41"
+ attribute \src "ls180.v:1139.6-1139.41"
wire \main_sdphy_cmdr_cmdr_buf_sink_ready
- attribute \src "ls180.v:1122.6-1122.41"
+ attribute \src "ls180.v:1138.6-1138.41"
wire \main_sdphy_cmdr_cmdr_buf_sink_valid
- attribute \src "ls180.v:1129.5-1129.42"
+ attribute \src "ls180.v:1145.5-1145.42"
wire \main_sdphy_cmdr_cmdr_buf_source_first
- attribute \src "ls180.v:1130.5-1130.41"
+ attribute \src "ls180.v:1146.5-1146.41"
wire \main_sdphy_cmdr_cmdr_buf_source_last
- attribute \src "ls180.v:1131.11-1131.55"
+ attribute \src "ls180.v:1147.11-1147.55"
wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data
- attribute \src "ls180.v:1128.6-1128.43"
+ attribute \src "ls180.v:1144.6-1144.43"
wire \main_sdphy_cmdr_cmdr_buf_source_ready
- attribute \src "ls180.v:1127.5-1127.42"
+ attribute \src "ls180.v:1143.5-1143.42"
wire \main_sdphy_cmdr_cmdr_buf_source_valid
- attribute \src "ls180.v:1114.11-1114.47"
+ attribute \src "ls180.v:1130.11-1130.47"
wire width 3 \main_sdphy_cmdr_cmdr_converter_demux
- attribute \src "ls180.v:1115.6-1115.46"
+ attribute \src "ls180.v:1131.6-1131.46"
wire \main_sdphy_cmdr_cmdr_converter_load_part
- attribute \src "ls180.v:1105.5-1105.46"
+ attribute \src "ls180.v:1121.5-1121.46"
wire \main_sdphy_cmdr_cmdr_converter_sink_first
- attribute \src "ls180.v:1106.5-1106.45"
+ attribute \src "ls180.v:1122.5-1122.45"
wire \main_sdphy_cmdr_cmdr_converter_sink_last
- attribute \src "ls180.v:1107.6-1107.54"
+ attribute \src "ls180.v:1123.6-1123.54"
wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data
- attribute \src "ls180.v:1104.6-1104.47"
+ attribute \src "ls180.v:1120.6-1120.47"
wire \main_sdphy_cmdr_cmdr_converter_sink_ready
- attribute \src "ls180.v:1103.6-1103.47"
+ attribute \src "ls180.v:1119.6-1119.47"
wire \main_sdphy_cmdr_cmdr_converter_sink_valid
- attribute \src "ls180.v:1110.5-1110.48"
+ attribute \src "ls180.v:1126.5-1126.48"
wire \main_sdphy_cmdr_cmdr_converter_source_first
- attribute \src "ls180.v:1111.5-1111.47"
+ attribute \src "ls180.v:1127.5-1127.47"
wire \main_sdphy_cmdr_cmdr_converter_source_last
- attribute \src "ls180.v:1112.11-1112.61"
+ attribute \src "ls180.v:1128.11-1128.61"
wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data
- attribute \src "ls180.v:1113.11-1113.74"
+ attribute \src "ls180.v:1129.11-1129.74"
wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count
- attribute \src "ls180.v:1109.6-1109.49"
+ attribute \src "ls180.v:1125.6-1125.49"
wire \main_sdphy_cmdr_cmdr_converter_source_ready
- attribute \src "ls180.v:1108.6-1108.49"
+ attribute \src "ls180.v:1124.6-1124.49"
wire \main_sdphy_cmdr_cmdr_converter_source_valid
- attribute \src "ls180.v:1116.5-1116.46"
+ attribute \src "ls180.v:1132.5-1132.46"
wire \main_sdphy_cmdr_cmdr_converter_strobe_all
- attribute \src "ls180.v:1087.6-1087.40"
+ attribute \src "ls180.v:1103.6-1103.40"
wire \main_sdphy_cmdr_cmdr_pads_in_first
- attribute \src "ls180.v:1088.6-1088.39"
+ attribute \src "ls180.v:1104.6-1104.39"
wire \main_sdphy_cmdr_cmdr_pads_in_last
- attribute \src "ls180.v:1089.6-1089.46"
+ attribute \src "ls180.v:1105.6-1105.46"
wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk
- attribute \src "ls180.v:1090.6-1090.48"
+ attribute \src "ls180.v:1106.6-1106.48"
wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i
- attribute \src "ls180.v:1091.6-1091.48"
+ attribute \src "ls180.v:1107.6-1107.48"
wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o
- attribute \src "ls180.v:1092.6-1092.49"
+ attribute \src "ls180.v:1108.6-1108.49"
wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe
- attribute \src "ls180.v:1093.12-1093.55"
+ attribute \src "ls180.v:1109.12-1109.55"
wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i
- attribute \src "ls180.v:1094.12-1094.55"
+ attribute \src "ls180.v:1110.12-1110.55"
wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o
- attribute \src "ls180.v:1095.6-1095.50"
+ attribute \src "ls180.v:1111.6-1111.50"
wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe
- attribute \src "ls180.v:1086.5-1086.39"
+ attribute \src "ls180.v:1102.5-1102.39"
wire \main_sdphy_cmdr_cmdr_pads_in_ready
- attribute \src "ls180.v:1085.6-1085.40"
+ attribute \src "ls180.v:1101.6-1101.40"
wire \main_sdphy_cmdr_cmdr_pads_in_valid
- attribute \src "ls180.v:1132.5-1132.31"
+ attribute \src "ls180.v:1148.5-1148.31"
wire \main_sdphy_cmdr_cmdr_reset
- attribute \src "ls180.v:1761.5-1761.59"
+ attribute \src "ls180.v:1777.5-1777.59"
wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2
- attribute \src "ls180.v:1762.5-1762.62"
+ attribute \src "ls180.v:1778.5-1778.62"
wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2
- attribute \src "ls180.v:1102.5-1102.29"
+ attribute \src "ls180.v:1118.5-1118.29"
wire \main_sdphy_cmdr_cmdr_run
- attribute \src "ls180.v:1098.6-1098.47"
+ attribute \src "ls180.v:1114.6-1114.47"
wire \main_sdphy_cmdr_cmdr_source_source_first0
- attribute \src "ls180.v:1119.6-1119.47"
+ attribute \src "ls180.v:1135.6-1135.47"
wire \main_sdphy_cmdr_cmdr_source_source_first1
- attribute \src "ls180.v:1099.6-1099.46"
+ attribute \src "ls180.v:1115.6-1115.46"
wire \main_sdphy_cmdr_cmdr_source_source_last0
- attribute \src "ls180.v:1120.6-1120.46"
+ attribute \src "ls180.v:1136.6-1136.46"
wire \main_sdphy_cmdr_cmdr_source_source_last1
- attribute \src "ls180.v:1100.12-1100.60"
+ attribute \src "ls180.v:1116.12-1116.60"
wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0
- attribute \src "ls180.v:1121.12-1121.60"
+ attribute \src "ls180.v:1137.12-1137.60"
wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1
- attribute \src "ls180.v:1097.5-1097.46"
+ attribute \src "ls180.v:1113.5-1113.46"
wire \main_sdphy_cmdr_cmdr_source_source_ready0
- attribute \src "ls180.v:1118.6-1118.47"
+ attribute \src "ls180.v:1134.6-1134.47"
wire \main_sdphy_cmdr_cmdr_source_source_ready1
- attribute \src "ls180.v:1096.6-1096.47"
+ attribute \src "ls180.v:1112.6-1112.47"
wire \main_sdphy_cmdr_cmdr_source_source_valid0
- attribute \src "ls180.v:1117.6-1117.47"
+ attribute \src "ls180.v:1133.6-1133.47"
wire \main_sdphy_cmdr_cmdr_source_source_valid1
- attribute \src "ls180.v:1101.6-1101.32"
+ attribute \src "ls180.v:1117.6-1117.32"
wire \main_sdphy_cmdr_cmdr_start
- attribute \src "ls180.v:1084.11-1084.32"
+ attribute \src "ls180.v:1100.11-1100.32"
wire width 8 \main_sdphy_cmdr_count
- attribute \src "ls180.v:1757.11-1757.60"
+ attribute \src "ls180.v:1773.11-1773.60"
wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0
- attribute \src "ls180.v:1758.5-1758.57"
+ attribute \src "ls180.v:1774.5-1774.57"
wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0
- attribute \src "ls180.v:1059.5-1059.42"
+ attribute \src "ls180.v:1075.5-1075.42"
wire \main_sdphy_cmdr_pads_in_pads_in_first
- attribute \src "ls180.v:1060.5-1060.41"
+ attribute \src "ls180.v:1076.5-1076.41"
wire \main_sdphy_cmdr_pads_in_pads_in_last
- attribute \src "ls180.v:1061.5-1061.48"
+ attribute \src "ls180.v:1077.5-1077.48"
wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk
- attribute \src "ls180.v:1062.6-1062.51"
+ attribute \src "ls180.v:1078.6-1078.51"
wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i
- attribute \src "ls180.v:1063.5-1063.50"
+ attribute \src "ls180.v:1079.5-1079.50"
wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o
- attribute \src "ls180.v:1064.5-1064.51"
+ attribute \src "ls180.v:1080.5-1080.51"
wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe
- attribute \src "ls180.v:1065.12-1065.58"
+ attribute \src "ls180.v:1081.12-1081.58"
wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i
- attribute \src "ls180.v:1066.11-1066.57"
+ attribute \src "ls180.v:1082.11-1082.57"
wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o
- attribute \src "ls180.v:1067.5-1067.52"
+ attribute \src "ls180.v:1083.5-1083.52"
wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe
- attribute \src "ls180.v:1058.6-1058.43"
+ attribute \src "ls180.v:1074.6-1074.43"
wire \main_sdphy_cmdr_pads_in_pads_in_ready
- attribute \src "ls180.v:1057.6-1057.43"
+ attribute \src "ls180.v:1073.6-1073.43"
wire \main_sdphy_cmdr_pads_in_pads_in_valid
- attribute \src "ls180.v:1069.5-1069.41"
+ attribute \src "ls180.v:1085.5-1085.41"
wire \main_sdphy_cmdr_pads_out_payload_clk
- attribute \src "ls180.v:1070.5-1070.43"
+ attribute \src "ls180.v:1086.5-1086.43"
wire \main_sdphy_cmdr_pads_out_payload_cmd_o
- attribute \src "ls180.v:1071.5-1071.44"
+ attribute \src "ls180.v:1087.5-1087.44"
wire \main_sdphy_cmdr_pads_out_payload_cmd_oe
- attribute \src "ls180.v:1072.11-1072.50"
+ attribute \src "ls180.v:1088.11-1088.50"
wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o
- attribute \src "ls180.v:1073.5-1073.45"
+ attribute \src "ls180.v:1089.5-1089.45"
wire \main_sdphy_cmdr_pads_out_payload_data_oe
- attribute \src "ls180.v:1068.6-1068.36"
+ attribute \src "ls180.v:1084.6-1084.36"
wire \main_sdphy_cmdr_pads_out_ready
- attribute \src "ls180.v:1076.5-1076.30"
+ attribute \src "ls180.v:1092.5-1092.30"
wire \main_sdphy_cmdr_sink_last
- attribute \src "ls180.v:1077.11-1077.46"
+ attribute \src "ls180.v:1093.11-1093.46"
wire width 8 \main_sdphy_cmdr_sink_payload_length
- attribute \src "ls180.v:1075.5-1075.31"
+ attribute \src "ls180.v:1091.5-1091.31"
wire \main_sdphy_cmdr_sink_ready
- attribute \src "ls180.v:1074.5-1074.31"
+ attribute \src "ls180.v:1090.5-1090.31"
wire \main_sdphy_cmdr_sink_valid
- attribute \src "ls180.v:1080.5-1080.32"
+ attribute \src "ls180.v:1096.5-1096.32"
wire \main_sdphy_cmdr_source_last
- attribute \src "ls180.v:1081.11-1081.46"
+ attribute \src "ls180.v:1097.11-1097.46"
wire width 8 \main_sdphy_cmdr_source_payload_data
- attribute \src "ls180.v:1082.11-1082.48"
+ attribute \src "ls180.v:1098.11-1098.48"
wire width 3 \main_sdphy_cmdr_source_payload_status
- attribute \src "ls180.v:1079.5-1079.33"
+ attribute \src "ls180.v:1095.5-1095.33"
wire \main_sdphy_cmdr_source_ready
- attribute \src "ls180.v:1078.5-1078.33"
+ attribute \src "ls180.v:1094.5-1094.33"
wire \main_sdphy_cmdr_source_valid
- attribute \src "ls180.v:1083.12-1083.35"
+ attribute \src "ls180.v:1099.12-1099.35"
wire width 32 \main_sdphy_cmdr_timeout
- attribute \src "ls180.v:1759.12-1759.63"
+ attribute \src "ls180.v:1775.12-1775.63"
wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1
- attribute \src "ls180.v:1760.5-1760.59"
+ attribute \src "ls180.v:1776.5-1776.59"
wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1
- attribute \src "ls180.v:1056.11-1056.32"
+ attribute \src "ls180.v:1072.11-1072.32"
wire width 8 \main_sdphy_cmdw_count
- attribute \src "ls180.v:1753.11-1753.59"
+ attribute \src "ls180.v:1769.11-1769.59"
wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value
- attribute \src "ls180.v:1754.5-1754.56"
+ attribute \src "ls180.v:1770.5-1770.56"
wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce
- attribute \src "ls180.v:1055.5-1055.25"
+ attribute \src "ls180.v:1071.5-1071.25"
wire \main_sdphy_cmdw_done
- attribute \src "ls180.v:1043.6-1043.43"
+ attribute \src "ls180.v:1059.6-1059.43"
wire \main_sdphy_cmdw_pads_in_payload_cmd_i
- attribute \src "ls180.v:1044.12-1044.50"
+ attribute \src "ls180.v:1060.12-1060.50"
wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i
- attribute \src "ls180.v:1042.6-1042.35"
+ attribute \src "ls180.v:1058.6-1058.35"
wire \main_sdphy_cmdw_pads_in_valid
- attribute \src "ls180.v:1046.5-1046.41"
+ attribute \src "ls180.v:1062.5-1062.41"
wire \main_sdphy_cmdw_pads_out_payload_clk
- attribute \src "ls180.v:1047.5-1047.43"
+ attribute \src "ls180.v:1063.5-1063.43"
wire \main_sdphy_cmdw_pads_out_payload_cmd_o
- attribute \src "ls180.v:1048.5-1048.44"
+ attribute \src "ls180.v:1064.5-1064.44"
wire \main_sdphy_cmdw_pads_out_payload_cmd_oe
- attribute \src "ls180.v:1049.11-1049.50"
+ attribute \src "ls180.v:1065.11-1065.50"
wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o
- attribute \src "ls180.v:1050.5-1050.45"
+ attribute \src "ls180.v:1066.5-1066.45"
wire \main_sdphy_cmdw_pads_out_payload_data_oe
- attribute \src "ls180.v:1045.6-1045.36"
+ attribute \src "ls180.v:1061.6-1061.36"
wire \main_sdphy_cmdw_pads_out_ready
- attribute \src "ls180.v:1053.5-1053.30"
+ attribute \src "ls180.v:1069.5-1069.30"
wire \main_sdphy_cmdw_sink_last
- attribute \src "ls180.v:1054.11-1054.44"
+ attribute \src "ls180.v:1070.11-1070.44"
wire width 8 \main_sdphy_cmdw_sink_payload_data
- attribute \src "ls180.v:1052.5-1052.31"
+ attribute \src "ls180.v:1068.5-1068.31"
wire \main_sdphy_cmdw_sink_ready
- attribute \src "ls180.v:1051.5-1051.31"
+ attribute \src "ls180.v:1067.5-1067.31"
wire \main_sdphy_cmdw_sink_valid
- attribute \src "ls180.v:1240.11-1240.33"
+ attribute \src "ls180.v:1256.11-1256.33"
wire width 10 \main_sdphy_datar_count
- attribute \src "ls180.v:1773.11-1773.62"
+ attribute \src "ls180.v:1789.11-1789.62"
wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0
- attribute \src "ls180.v:1774.5-1774.59"
+ attribute \src "ls180.v:1790.5-1790.59"
wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0
- attribute \src "ls180.v:1280.6-1280.43"
+ attribute \src "ls180.v:1296.6-1296.43"
wire \main_sdphy_datar_datar_buf_sink_first
- attribute \src "ls180.v:1281.6-1281.42"
+ attribute \src "ls180.v:1297.6-1297.42"
wire \main_sdphy_datar_datar_buf_sink_last
- attribute \src "ls180.v:1282.12-1282.56"
+ attribute \src "ls180.v:1298.12-1298.56"
wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data
- attribute \src "ls180.v:1279.6-1279.43"
+ attribute \src "ls180.v:1295.6-1295.43"
wire \main_sdphy_datar_datar_buf_sink_ready
- attribute \src "ls180.v:1278.6-1278.43"
+ attribute \src "ls180.v:1294.6-1294.43"
wire \main_sdphy_datar_datar_buf_sink_valid
- attribute \src "ls180.v:1285.5-1285.44"
+ attribute \src "ls180.v:1301.5-1301.44"
wire \main_sdphy_datar_datar_buf_source_first
- attribute \src "ls180.v:1286.5-1286.43"
+ attribute \src "ls180.v:1302.5-1302.43"
wire \main_sdphy_datar_datar_buf_source_last
- attribute \src "ls180.v:1287.11-1287.57"
+ attribute \src "ls180.v:1303.11-1303.57"
wire width 8 \main_sdphy_datar_datar_buf_source_payload_data
- attribute \src "ls180.v:1284.6-1284.45"
+ attribute \src "ls180.v:1300.6-1300.45"
wire \main_sdphy_datar_datar_buf_source_ready
- attribute \src "ls180.v:1283.5-1283.44"
+ attribute \src "ls180.v:1299.5-1299.44"
wire \main_sdphy_datar_datar_buf_source_valid
- attribute \src "ls180.v:1270.5-1270.43"
+ attribute \src "ls180.v:1286.5-1286.43"
wire \main_sdphy_datar_datar_converter_demux
- attribute \src "ls180.v:1271.6-1271.48"
+ attribute \src "ls180.v:1287.6-1287.48"
wire \main_sdphy_datar_datar_converter_load_part
- attribute \src "ls180.v:1261.5-1261.48"
+ attribute \src "ls180.v:1277.5-1277.48"
wire \main_sdphy_datar_datar_converter_sink_first
- attribute \src "ls180.v:1262.5-1262.47"
+ attribute \src "ls180.v:1278.5-1278.47"
wire \main_sdphy_datar_datar_converter_sink_last
- attribute \src "ls180.v:1263.12-1263.62"
+ attribute \src "ls180.v:1279.12-1279.62"
wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data
- attribute \src "ls180.v:1260.6-1260.49"
+ attribute \src "ls180.v:1276.6-1276.49"
wire \main_sdphy_datar_datar_converter_sink_ready
- attribute \src "ls180.v:1259.6-1259.49"
+ attribute \src "ls180.v:1275.6-1275.49"
wire \main_sdphy_datar_datar_converter_sink_valid
- attribute \src "ls180.v:1266.5-1266.50"
+ attribute \src "ls180.v:1282.5-1282.50"
wire \main_sdphy_datar_datar_converter_source_first
- attribute \src "ls180.v:1267.5-1267.49"
+ attribute \src "ls180.v:1283.5-1283.49"
wire \main_sdphy_datar_datar_converter_source_last
- attribute \src "ls180.v:1268.11-1268.63"
+ attribute \src "ls180.v:1284.11-1284.63"
wire width 8 \main_sdphy_datar_datar_converter_source_payload_data
- attribute \src "ls180.v:1269.11-1269.76"
+ attribute \src "ls180.v:1285.11-1285.76"
wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count
- attribute \src "ls180.v:1265.6-1265.51"
+ attribute \src "ls180.v:1281.6-1281.51"
wire \main_sdphy_datar_datar_converter_source_ready
- attribute \src "ls180.v:1264.6-1264.51"
+ attribute \src "ls180.v:1280.6-1280.51"
wire \main_sdphy_datar_datar_converter_source_valid
- attribute \src "ls180.v:1272.5-1272.48"
+ attribute \src "ls180.v:1288.5-1288.48"
wire \main_sdphy_datar_datar_converter_strobe_all
- attribute \src "ls180.v:1243.6-1243.42"
+ attribute \src "ls180.v:1259.6-1259.42"
wire \main_sdphy_datar_datar_pads_in_first
- attribute \src "ls180.v:1244.6-1244.41"
+ attribute \src "ls180.v:1260.6-1260.41"
wire \main_sdphy_datar_datar_pads_in_last
- attribute \src "ls180.v:1245.6-1245.48"
+ attribute \src "ls180.v:1261.6-1261.48"
wire \main_sdphy_datar_datar_pads_in_payload_clk
- attribute \src "ls180.v:1246.6-1246.50"
+ attribute \src "ls180.v:1262.6-1262.50"
wire \main_sdphy_datar_datar_pads_in_payload_cmd_i
- attribute \src "ls180.v:1247.6-1247.50"
+ attribute \src "ls180.v:1263.6-1263.50"
wire \main_sdphy_datar_datar_pads_in_payload_cmd_o
- attribute \src "ls180.v:1248.6-1248.51"
+ attribute \src "ls180.v:1264.6-1264.51"
wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe
- attribute \src "ls180.v:1249.12-1249.57"
+ attribute \src "ls180.v:1265.12-1265.57"
wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i
- attribute \src "ls180.v:1250.12-1250.57"
+ attribute \src "ls180.v:1266.12-1266.57"
wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o
- attribute \src "ls180.v:1251.6-1251.52"
+ attribute \src "ls180.v:1267.6-1267.52"
wire \main_sdphy_datar_datar_pads_in_payload_data_oe
- attribute \src "ls180.v:1242.5-1242.41"
+ attribute \src "ls180.v:1258.5-1258.41"
wire \main_sdphy_datar_datar_pads_in_ready
- attribute \src "ls180.v:1241.6-1241.42"
+ attribute \src "ls180.v:1257.6-1257.42"
wire \main_sdphy_datar_datar_pads_in_valid
- attribute \src "ls180.v:1288.5-1288.33"
+ attribute \src "ls180.v:1304.5-1304.33"
wire \main_sdphy_datar_datar_reset
- attribute \src "ls180.v:1777.5-1777.62"
+ attribute \src "ls180.v:1793.5-1793.62"
wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2
- attribute \src "ls180.v:1778.5-1778.65"
+ attribute \src "ls180.v:1794.5-1794.65"
wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2
- attribute \src "ls180.v:1258.5-1258.31"
+ attribute \src "ls180.v:1274.5-1274.31"
wire \main_sdphy_datar_datar_run
- attribute \src "ls180.v:1254.6-1254.49"
+ attribute \src "ls180.v:1270.6-1270.49"
wire \main_sdphy_datar_datar_source_source_first0
- attribute \src "ls180.v:1275.6-1275.49"
+ attribute \src "ls180.v:1291.6-1291.49"
wire \main_sdphy_datar_datar_source_source_first1
- attribute \src "ls180.v:1255.6-1255.48"
+ attribute \src "ls180.v:1271.6-1271.48"
wire \main_sdphy_datar_datar_source_source_last0
- attribute \src "ls180.v:1276.6-1276.48"
+ attribute \src "ls180.v:1292.6-1292.48"
wire \main_sdphy_datar_datar_source_source_last1
- attribute \src "ls180.v:1256.12-1256.62"
+ attribute \src "ls180.v:1272.12-1272.62"
wire width 8 \main_sdphy_datar_datar_source_source_payload_data0
- attribute \src "ls180.v:1277.12-1277.62"
+ attribute \src "ls180.v:1293.12-1293.62"
wire width 8 \main_sdphy_datar_datar_source_source_payload_data1
- attribute \src "ls180.v:1253.5-1253.48"
+ attribute \src "ls180.v:1269.5-1269.48"
wire \main_sdphy_datar_datar_source_source_ready0
- attribute \src "ls180.v:1274.6-1274.49"
+ attribute \src "ls180.v:1290.6-1290.49"
wire \main_sdphy_datar_datar_source_source_ready1
- attribute \src "ls180.v:1252.6-1252.49"
+ attribute \src "ls180.v:1268.6-1268.49"
wire \main_sdphy_datar_datar_source_source_valid0
- attribute \src "ls180.v:1273.6-1273.49"
+ attribute \src "ls180.v:1289.6-1289.49"
wire \main_sdphy_datar_datar_source_source_valid1
- attribute \src "ls180.v:1257.6-1257.34"
+ attribute \src "ls180.v:1273.6-1273.34"
wire \main_sdphy_datar_datar_start
- attribute \src "ls180.v:1213.5-1213.43"
+ attribute \src "ls180.v:1229.5-1229.43"
wire \main_sdphy_datar_pads_in_pads_in_first
- attribute \src "ls180.v:1214.5-1214.42"
+ attribute \src "ls180.v:1230.5-1230.42"
wire \main_sdphy_datar_pads_in_pads_in_last
- attribute \src "ls180.v:1215.5-1215.49"
+ attribute \src "ls180.v:1231.5-1231.49"
wire \main_sdphy_datar_pads_in_pads_in_payload_clk
- attribute \src "ls180.v:1216.6-1216.52"
+ attribute \src "ls180.v:1232.6-1232.52"
wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i
- attribute \src "ls180.v:1217.5-1217.51"
+ attribute \src "ls180.v:1233.5-1233.51"
wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o
- attribute \src "ls180.v:1218.5-1218.52"
+ attribute \src "ls180.v:1234.5-1234.52"
wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe
- attribute \src "ls180.v:1219.12-1219.59"
+ attribute \src "ls180.v:1235.12-1235.59"
wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i
- attribute \src "ls180.v:1220.11-1220.58"
+ attribute \src "ls180.v:1236.11-1236.58"
wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o
- attribute \src "ls180.v:1221.5-1221.53"
+ attribute \src "ls180.v:1237.5-1237.53"
wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe
- attribute \src "ls180.v:1212.6-1212.44"
+ attribute \src "ls180.v:1228.6-1228.44"
wire \main_sdphy_datar_pads_in_pads_in_ready
- attribute \src "ls180.v:1211.6-1211.44"
+ attribute \src "ls180.v:1227.6-1227.44"
wire \main_sdphy_datar_pads_in_pads_in_valid
- attribute \src "ls180.v:1223.5-1223.42"
+ attribute \src "ls180.v:1239.5-1239.42"
wire \main_sdphy_datar_pads_out_payload_clk
- attribute \src "ls180.v:1224.5-1224.44"
+ attribute \src "ls180.v:1240.5-1240.44"
wire \main_sdphy_datar_pads_out_payload_cmd_o
- attribute \src "ls180.v:1225.5-1225.45"
+ attribute \src "ls180.v:1241.5-1241.45"
wire \main_sdphy_datar_pads_out_payload_cmd_oe
- attribute \src "ls180.v:1226.11-1226.51"
+ attribute \src "ls180.v:1242.11-1242.51"
wire width 4 \main_sdphy_datar_pads_out_payload_data_o
- attribute \src "ls180.v:1227.5-1227.46"
+ attribute \src "ls180.v:1243.5-1243.46"
wire \main_sdphy_datar_pads_out_payload_data_oe
- attribute \src "ls180.v:1222.6-1222.37"
+ attribute \src "ls180.v:1238.6-1238.37"
wire \main_sdphy_datar_pads_out_ready
- attribute \src "ls180.v:1230.5-1230.31"
+ attribute \src "ls180.v:1246.5-1246.31"
wire \main_sdphy_datar_sink_last
- attribute \src "ls180.v:1231.11-1231.53"
+ attribute \src "ls180.v:1247.11-1247.53"
wire width 10 \main_sdphy_datar_sink_payload_block_length
- attribute \src "ls180.v:1229.5-1229.32"
+ attribute \src "ls180.v:1245.5-1245.32"
wire \main_sdphy_datar_sink_ready
- attribute \src "ls180.v:1228.5-1228.32"
+ attribute \src "ls180.v:1244.5-1244.32"
wire \main_sdphy_datar_sink_valid
- attribute \src "ls180.v:1234.5-1234.34"
+ attribute \src "ls180.v:1250.5-1250.34"
wire \main_sdphy_datar_source_first
- attribute \src "ls180.v:1235.5-1235.33"
+ attribute \src "ls180.v:1251.5-1251.33"
wire \main_sdphy_datar_source_last
- attribute \src "ls180.v:1236.11-1236.47"
+ attribute \src "ls180.v:1252.11-1252.47"
wire width 8 \main_sdphy_datar_source_payload_data
- attribute \src "ls180.v:1237.11-1237.49"
+ attribute \src "ls180.v:1253.11-1253.49"
wire width 3 \main_sdphy_datar_source_payload_status
- attribute \src "ls180.v:1233.5-1233.34"
+ attribute \src "ls180.v:1249.5-1249.34"
wire \main_sdphy_datar_source_ready
- attribute \src "ls180.v:1232.5-1232.34"
+ attribute \src "ls180.v:1248.5-1248.34"
wire \main_sdphy_datar_source_valid
- attribute \src "ls180.v:1238.5-1238.26"
+ attribute \src "ls180.v:1254.5-1254.26"
wire \main_sdphy_datar_stop
- attribute \src "ls180.v:1239.12-1239.36"
+ attribute \src "ls180.v:1255.12-1255.36"
wire width 32 \main_sdphy_datar_timeout
- attribute \src "ls180.v:1775.12-1775.65"
+ attribute \src "ls180.v:1791.12-1791.65"
wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1
- attribute \src "ls180.v:1776.5-1776.61"
+ attribute \src "ls180.v:1792.5-1792.61"
wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1
- attribute \src "ls180.v:1148.11-1148.33"
+ attribute \src "ls180.v:1164.11-1164.33"
wire width 8 \main_sdphy_dataw_count
- attribute \src "ls180.v:1769.11-1769.54"
+ attribute \src "ls180.v:1785.11-1785.54"
wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value
- attribute \src "ls180.v:1770.5-1770.51"
+ attribute \src "ls180.v:1786.5-1786.51"
wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce
- attribute \src "ls180.v:1202.6-1202.42"
+ attribute \src "ls180.v:1218.6-1218.42"
wire \main_sdphy_dataw_crcr_buf_sink_first
- attribute \src "ls180.v:1203.6-1203.41"
+ attribute \src "ls180.v:1219.6-1219.41"
wire \main_sdphy_dataw_crcr_buf_sink_last
- attribute \src "ls180.v:1204.12-1204.55"
+ attribute \src "ls180.v:1220.12-1220.55"
wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data
- attribute \src "ls180.v:1201.6-1201.42"
+ attribute \src "ls180.v:1217.6-1217.42"
wire \main_sdphy_dataw_crcr_buf_sink_ready
- attribute \src "ls180.v:1200.6-1200.42"
+ attribute \src "ls180.v:1216.6-1216.42"
wire \main_sdphy_dataw_crcr_buf_sink_valid
- attribute \src "ls180.v:1207.5-1207.43"
+ attribute \src "ls180.v:1223.5-1223.43"
wire \main_sdphy_dataw_crcr_buf_source_first
- attribute \src "ls180.v:1208.5-1208.42"
+ attribute \src "ls180.v:1224.5-1224.42"
wire \main_sdphy_dataw_crcr_buf_source_last
- attribute \src "ls180.v:1209.11-1209.56"
+ attribute \src "ls180.v:1225.11-1225.56"
wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data
- attribute \src "ls180.v:1206.6-1206.44"
+ attribute \src "ls180.v:1222.6-1222.44"
wire \main_sdphy_dataw_crcr_buf_source_ready
- attribute \src "ls180.v:1205.5-1205.43"
+ attribute \src "ls180.v:1221.5-1221.43"
wire \main_sdphy_dataw_crcr_buf_source_valid
- attribute \src "ls180.v:1192.11-1192.48"
+ attribute \src "ls180.v:1208.11-1208.48"
wire width 3 \main_sdphy_dataw_crcr_converter_demux
- attribute \src "ls180.v:1193.6-1193.47"
+ attribute \src "ls180.v:1209.6-1209.47"
wire \main_sdphy_dataw_crcr_converter_load_part
- attribute \src "ls180.v:1183.5-1183.47"
+ attribute \src "ls180.v:1199.5-1199.47"
wire \main_sdphy_dataw_crcr_converter_sink_first
- attribute \src "ls180.v:1184.5-1184.46"
+ attribute \src "ls180.v:1200.5-1200.46"
wire \main_sdphy_dataw_crcr_converter_sink_last
- attribute \src "ls180.v:1185.6-1185.55"
+ attribute \src "ls180.v:1201.6-1201.55"
wire \main_sdphy_dataw_crcr_converter_sink_payload_data
- attribute \src "ls180.v:1182.6-1182.48"
+ attribute \src "ls180.v:1198.6-1198.48"
wire \main_sdphy_dataw_crcr_converter_sink_ready
- attribute \src "ls180.v:1181.6-1181.48"
+ attribute \src "ls180.v:1197.6-1197.48"
wire \main_sdphy_dataw_crcr_converter_sink_valid
- attribute \src "ls180.v:1188.5-1188.49"
+ attribute \src "ls180.v:1204.5-1204.49"
wire \main_sdphy_dataw_crcr_converter_source_first
- attribute \src "ls180.v:1189.5-1189.48"
+ attribute \src "ls180.v:1205.5-1205.48"
wire \main_sdphy_dataw_crcr_converter_source_last
- attribute \src "ls180.v:1190.11-1190.62"
+ attribute \src "ls180.v:1206.11-1206.62"
wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data
- attribute \src "ls180.v:1191.11-1191.75"
+ attribute \src "ls180.v:1207.11-1207.75"
wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count
- attribute \src "ls180.v:1187.6-1187.50"
+ attribute \src "ls180.v:1203.6-1203.50"
wire \main_sdphy_dataw_crcr_converter_source_ready
- attribute \src "ls180.v:1186.6-1186.50"
+ attribute \src "ls180.v:1202.6-1202.50"
wire \main_sdphy_dataw_crcr_converter_source_valid
- attribute \src "ls180.v:1194.5-1194.47"
+ attribute \src "ls180.v:1210.5-1210.47"
wire \main_sdphy_dataw_crcr_converter_strobe_all
- attribute \src "ls180.v:1165.6-1165.41"
+ attribute \src "ls180.v:1181.6-1181.41"
wire \main_sdphy_dataw_crcr_pads_in_first
- attribute \src "ls180.v:1166.6-1166.40"
+ attribute \src "ls180.v:1182.6-1182.40"
wire \main_sdphy_dataw_crcr_pads_in_last
- attribute \src "ls180.v:1167.6-1167.47"
+ attribute \src "ls180.v:1183.6-1183.47"
wire \main_sdphy_dataw_crcr_pads_in_payload_clk
- attribute \src "ls180.v:1168.6-1168.49"
+ attribute \src "ls180.v:1184.6-1184.49"
wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i
- attribute \src "ls180.v:1169.6-1169.49"
+ attribute \src "ls180.v:1185.6-1185.49"
wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o
- attribute \src "ls180.v:1170.6-1170.50"
+ attribute \src "ls180.v:1186.6-1186.50"
wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe
- attribute \src "ls180.v:1171.12-1171.56"
+ attribute \src "ls180.v:1187.12-1187.56"
wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i
- attribute \src "ls180.v:1172.12-1172.56"
+ attribute \src "ls180.v:1188.12-1188.56"
wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o
- attribute \src "ls180.v:1173.6-1173.51"
+ attribute \src "ls180.v:1189.6-1189.51"
wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe
- attribute \src "ls180.v:1164.5-1164.40"
+ attribute \src "ls180.v:1180.5-1180.40"
wire \main_sdphy_dataw_crcr_pads_in_ready
- attribute \src "ls180.v:1163.6-1163.41"
+ attribute \src "ls180.v:1179.6-1179.41"
wire \main_sdphy_dataw_crcr_pads_in_valid
- attribute \src "ls180.v:1210.5-1210.32"
+ attribute \src "ls180.v:1226.5-1226.32"
wire \main_sdphy_dataw_crcr_reset
- attribute \src "ls180.v:1765.5-1765.59"
+ attribute \src "ls180.v:1781.5-1781.59"
wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value
- attribute \src "ls180.v:1766.5-1766.62"
+ attribute \src "ls180.v:1782.5-1782.62"
wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce
- attribute \src "ls180.v:1180.5-1180.30"
+ attribute \src "ls180.v:1196.5-1196.30"
wire \main_sdphy_dataw_crcr_run
- attribute \src "ls180.v:1176.6-1176.48"
+ attribute \src "ls180.v:1192.6-1192.48"
wire \main_sdphy_dataw_crcr_source_source_first0
- attribute \src "ls180.v:1197.6-1197.48"
+ attribute \src "ls180.v:1213.6-1213.48"
wire \main_sdphy_dataw_crcr_source_source_first1
- attribute \src "ls180.v:1177.6-1177.47"
+ attribute \src "ls180.v:1193.6-1193.47"
wire \main_sdphy_dataw_crcr_source_source_last0
- attribute \src "ls180.v:1198.6-1198.47"
+ attribute \src "ls180.v:1214.6-1214.47"
wire \main_sdphy_dataw_crcr_source_source_last1
- attribute \src "ls180.v:1178.12-1178.61"
+ attribute \src "ls180.v:1194.12-1194.61"
wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0
- attribute \src "ls180.v:1199.12-1199.61"
+ attribute \src "ls180.v:1215.12-1215.61"
wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1
- attribute \src "ls180.v:1175.5-1175.47"
+ attribute \src "ls180.v:1191.5-1191.47"
wire \main_sdphy_dataw_crcr_source_source_ready0
- attribute \src "ls180.v:1196.6-1196.48"
+ attribute \src "ls180.v:1212.6-1212.48"
wire \main_sdphy_dataw_crcr_source_source_ready1
- attribute \src "ls180.v:1174.6-1174.48"
+ attribute \src "ls180.v:1190.6-1190.48"
wire \main_sdphy_dataw_crcr_source_source_valid0
- attribute \src "ls180.v:1195.6-1195.48"
+ attribute \src "ls180.v:1211.6-1211.48"
wire \main_sdphy_dataw_crcr_source_source_valid1
- attribute \src "ls180.v:1179.6-1179.33"
+ attribute \src "ls180.v:1195.6-1195.33"
wire \main_sdphy_dataw_crcr_start
- attribute \src "ls180.v:1162.5-1162.27"
+ attribute \src "ls180.v:1178.5-1178.27"
wire \main_sdphy_dataw_error
- attribute \src "ls180.v:1151.5-1151.43"
+ attribute \src "ls180.v:1167.5-1167.43"
wire \main_sdphy_dataw_pads_in_pads_in_first
- attribute \src "ls180.v:1152.5-1152.42"
+ attribute \src "ls180.v:1168.5-1168.42"
wire \main_sdphy_dataw_pads_in_pads_in_last
- attribute \src "ls180.v:1153.5-1153.49"
+ attribute \src "ls180.v:1169.5-1169.49"
wire \main_sdphy_dataw_pads_in_pads_in_payload_clk
- attribute \src "ls180.v:1154.5-1154.51"
+ attribute \src "ls180.v:1170.5-1170.51"
wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i
- attribute \src "ls180.v:1155.5-1155.51"
+ attribute \src "ls180.v:1171.5-1171.51"
wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o
- attribute \src "ls180.v:1156.5-1156.52"
+ attribute \src "ls180.v:1172.5-1172.52"
wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe
- attribute \src "ls180.v:1157.11-1157.58"
+ attribute \src "ls180.v:1173.11-1173.58"
wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i
- attribute \src "ls180.v:1158.11-1158.58"
+ attribute \src "ls180.v:1174.11-1174.58"
wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o
- attribute \src "ls180.v:1159.5-1159.53"
+ attribute \src "ls180.v:1175.5-1175.53"
wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe
- attribute \src "ls180.v:1150.6-1150.44"
+ attribute \src "ls180.v:1166.6-1166.44"
wire \main_sdphy_dataw_pads_in_pads_in_ready
- attribute \src "ls180.v:1149.5-1149.43"
+ attribute \src "ls180.v:1165.5-1165.43"
wire \main_sdphy_dataw_pads_in_pads_in_valid
- attribute \src "ls180.v:1134.6-1134.44"
+ attribute \src "ls180.v:1150.6-1150.44"
wire \main_sdphy_dataw_pads_in_payload_cmd_i
- attribute \src "ls180.v:1135.12-1135.51"
+ attribute \src "ls180.v:1151.12-1151.51"
wire width 4 \main_sdphy_dataw_pads_in_payload_data_i
- attribute \src "ls180.v:1133.6-1133.36"
+ attribute \src "ls180.v:1149.6-1149.36"
wire \main_sdphy_dataw_pads_in_valid
- attribute \src "ls180.v:1137.5-1137.42"
+ attribute \src "ls180.v:1153.5-1153.42"
wire \main_sdphy_dataw_pads_out_payload_clk
- attribute \src "ls180.v:1138.5-1138.44"
+ attribute \src "ls180.v:1154.5-1154.44"
wire \main_sdphy_dataw_pads_out_payload_cmd_o
- attribute \src "ls180.v:1139.5-1139.45"
+ attribute \src "ls180.v:1155.5-1155.45"
wire \main_sdphy_dataw_pads_out_payload_cmd_oe
- attribute \src "ls180.v:1140.11-1140.51"
+ attribute \src "ls180.v:1156.11-1156.51"
wire width 4 \main_sdphy_dataw_pads_out_payload_data_o
- attribute \src "ls180.v:1141.5-1141.46"
+ attribute \src "ls180.v:1157.5-1157.46"
wire \main_sdphy_dataw_pads_out_payload_data_oe
- attribute \src "ls180.v:1136.6-1136.37"
+ attribute \src "ls180.v:1152.6-1152.37"
wire \main_sdphy_dataw_pads_out_ready
- attribute \src "ls180.v:1144.5-1144.32"
+ attribute \src "ls180.v:1160.5-1160.32"
wire \main_sdphy_dataw_sink_first
- attribute \src "ls180.v:1145.5-1145.31"
+ attribute \src "ls180.v:1161.5-1161.31"
wire \main_sdphy_dataw_sink_last
- attribute \src "ls180.v:1146.11-1146.45"
+ attribute \src "ls180.v:1162.11-1162.45"
wire width 8 \main_sdphy_dataw_sink_payload_data
- attribute \src "ls180.v:1143.5-1143.32"
+ attribute \src "ls180.v:1159.5-1159.32"
wire \main_sdphy_dataw_sink_ready
- attribute \src "ls180.v:1142.5-1142.32"
+ attribute \src "ls180.v:1158.5-1158.32"
wire \main_sdphy_dataw_sink_valid
- attribute \src "ls180.v:1160.5-1160.27"
+ attribute \src "ls180.v:1176.5-1176.27"
wire \main_sdphy_dataw_start
- attribute \src "ls180.v:1147.5-1147.26"
+ attribute \src "ls180.v:1163.5-1163.26"
wire \main_sdphy_dataw_stop
- attribute \src "ls180.v:1161.5-1161.27"
+ attribute \src "ls180.v:1177.5-1177.27"
wire \main_sdphy_dataw_valid
- attribute \src "ls180.v:1041.11-1041.32"
+ attribute \src "ls180.v:1057.11-1057.32"
wire width 8 \main_sdphy_init_count
- attribute \src "ls180.v:1749.11-1749.59"
+ attribute \src "ls180.v:1765.11-1765.59"
wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value
- attribute \src "ls180.v:1750.5-1750.56"
+ attribute \src "ls180.v:1766.5-1766.56"
wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce
- attribute \src "ls180.v:1029.6-1029.34"
+ attribute \src "ls180.v:1045.6-1045.34"
wire \main_sdphy_init_initialize_r
- attribute \src "ls180.v:1028.6-1028.35"
+ attribute \src "ls180.v:1044.6-1044.35"
wire \main_sdphy_init_initialize_re
- attribute \src "ls180.v:1031.5-1031.33"
+ attribute \src "ls180.v:1047.5-1047.33"
wire \main_sdphy_init_initialize_w
- attribute \src "ls180.v:1030.6-1030.35"
+ attribute \src "ls180.v:1046.6-1046.35"
wire \main_sdphy_init_initialize_we
- attribute \src "ls180.v:1033.6-1033.43"
+ attribute \src "ls180.v:1049.6-1049.43"
wire \main_sdphy_init_pads_in_payload_cmd_i
- attribute \src "ls180.v:1034.12-1034.50"
+ attribute \src "ls180.v:1050.12-1050.50"
wire width 4 \main_sdphy_init_pads_in_payload_data_i
- attribute \src "ls180.v:1032.6-1032.35"
+ attribute \src "ls180.v:1048.6-1048.35"
wire \main_sdphy_init_pads_in_valid
- attribute \src "ls180.v:1036.5-1036.41"
+ attribute \src "ls180.v:1052.5-1052.41"
wire \main_sdphy_init_pads_out_payload_clk
- attribute \src "ls180.v:1037.5-1037.43"
+ attribute \src "ls180.v:1053.5-1053.43"
wire \main_sdphy_init_pads_out_payload_cmd_o
- attribute \src "ls180.v:1038.5-1038.44"
+ attribute \src "ls180.v:1054.5-1054.44"
wire \main_sdphy_init_pads_out_payload_cmd_oe
- attribute \src "ls180.v:1039.11-1039.50"
+ attribute \src "ls180.v:1055.11-1055.50"
wire width 4 \main_sdphy_init_pads_out_payload_data_o
- attribute \src "ls180.v:1040.5-1040.45"
+ attribute \src "ls180.v:1056.5-1056.45"
wire \main_sdphy_init_pads_out_payload_data_oe
- attribute \src "ls180.v:1035.6-1035.36"
+ attribute \src "ls180.v:1051.6-1051.36"
wire \main_sdphy_init_pads_out_ready
- attribute \src "ls180.v:1289.6-1289.27"
+ attribute \src "ls180.v:1305.6-1305.27"
wire \main_sdphy_sdpads_clk
- attribute \src "ls180.v:1290.5-1290.28"
+ attribute \src "ls180.v:1306.5-1306.28"
wire \main_sdphy_sdpads_cmd_i
- attribute \src "ls180.v:1291.6-1291.29"
+ attribute \src "ls180.v:1307.6-1307.29"
wire \main_sdphy_sdpads_cmd_o
- attribute \src "ls180.v:1292.6-1292.30"
+ attribute \src "ls180.v:1308.6-1308.30"
wire \main_sdphy_sdpads_cmd_oe
- attribute \src "ls180.v:1293.11-1293.35"
+ attribute \src "ls180.v:1309.11-1309.35"
wire width 4 \main_sdphy_sdpads_data_i
- attribute \src "ls180.v:1294.12-1294.36"
+ attribute \src "ls180.v:1310.12-1310.36"
wire width 4 \main_sdphy_sdpads_data_o
- attribute \src "ls180.v:1295.6-1295.31"
+ attribute \src "ls180.v:1311.6-1311.31"
wire \main_sdphy_sdpads_data_oe
- attribute \src "ls180.v:1018.6-1018.23"
+ attribute \src "ls180.v:1034.6-1034.23"
wire \main_sdphy_status
- attribute \src "ls180.v:1019.6-1019.19"
+ attribute \src "ls180.v:1035.6-1035.19"
wire \main_sdphy_we
- attribute \src "ls180.v:299.5-299.26"
+ attribute \src "ls180.v:307.5-307.26"
wire \main_sdram_address_re
- attribute \src "ls180.v:298.12-298.38"
+ attribute \src "ls180.v:306.12-306.38"
wire width 13 \main_sdram_address_storage
- attribute \src "ls180.v:301.5-301.27"
+ attribute \src "ls180.v:309.5-309.27"
wire \main_sdram_baddress_re
- attribute \src "ls180.v:300.11-300.38"
+ attribute \src "ls180.v:308.11-308.38"
wire width 2 \main_sdram_baddress_storage
- attribute \src "ls180.v:397.5-397.43"
+ attribute \src "ls180.v:405.5-405.43"
wire \main_sdram_bankmachine0_auto_precharge
- attribute \src "ls180.v:419.11-419.63"
+ attribute \src "ls180.v:427.11-427.63"
wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
- attribute \src "ls180.v:424.6-424.58"
+ attribute \src "ls180.v:432.6-432.58"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:429.6-429.64"
+ attribute \src "ls180.v:437.6-437.64"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first
- attribute \src "ls180.v:430.6-430.63"
+ attribute \src "ls180.v:438.6-438.63"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last
- attribute \src "ls180.v:428.13-428.78"
+ attribute \src "ls180.v:436.13-436.78"
wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr
- attribute \src "ls180.v:427.6-427.69"
+ attribute \src "ls180.v:435.6-435.69"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we
- attribute \src "ls180.v:433.6-433.65"
+ attribute \src "ls180.v:441.6-441.65"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first
- attribute \src "ls180.v:434.6-434.64"
+ attribute \src "ls180.v:442.6-442.64"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last
- attribute \src "ls180.v:432.13-432.79"
+ attribute \src "ls180.v:440.13-440.79"
wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr
- attribute \src "ls180.v:431.6-431.70"
+ attribute \src "ls180.v:439.6-439.70"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we
- attribute \src "ls180.v:416.11-416.61"
+ attribute \src "ls180.v:424.11-424.61"
wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level
- attribute \src "ls180.v:418.11-418.63"
+ attribute \src "ls180.v:426.11-426.63"
wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
- attribute \src "ls180.v:425.12-425.67"
+ attribute \src "ls180.v:433.12-433.67"
wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr
- attribute \src "ls180.v:426.13-426.70"
+ attribute \src "ls180.v:434.13-434.70"
wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r
- attribute \src "ls180.v:417.5-417.57"
+ attribute \src "ls180.v:425.5-425.57"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:400.5-400.60"
+ attribute \src "ls180.v:408.5-408.60"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first
- attribute \src "ls180.v:401.5-401.59"
+ attribute \src "ls180.v:409.5-409.59"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last
- attribute \src "ls180.v:403.13-403.75"
+ attribute \src "ls180.v:411.13-411.75"
wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr
- attribute \src "ls180.v:402.6-402.66"
+ attribute \src "ls180.v:410.6-410.66"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we
- attribute \src "ls180.v:399.6-399.61"
+ attribute \src "ls180.v:407.6-407.61"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready
- attribute \src "ls180.v:398.6-398.61"
+ attribute \src "ls180.v:406.6-406.61"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid
- attribute \src "ls180.v:406.6-406.63"
+ attribute \src "ls180.v:414.6-414.63"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first
- attribute \src "ls180.v:407.6-407.62"
+ attribute \src "ls180.v:415.6-415.62"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last
- attribute \src "ls180.v:409.13-409.77"
+ attribute \src "ls180.v:417.13-417.77"
wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr
- attribute \src "ls180.v:408.6-408.68"
+ attribute \src "ls180.v:416.6-416.68"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we
- attribute \src "ls180.v:405.6-405.63"
+ attribute \src "ls180.v:413.6-413.63"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready
- attribute \src "ls180.v:404.6-404.63"
+ attribute \src "ls180.v:412.6-412.63"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid
- attribute \src "ls180.v:414.13-414.71"
+ attribute \src "ls180.v:422.13-422.71"
wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din
- attribute \src "ls180.v:415.13-415.72"
+ attribute \src "ls180.v:423.13-423.72"
wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout
- attribute \src "ls180.v:412.6-412.63"
+ attribute \src "ls180.v:420.6-420.63"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re
- attribute \src "ls180.v:413.6-413.69"
+ attribute \src "ls180.v:421.6-421.69"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable
- attribute \src "ls180.v:410.6-410.63"
+ attribute \src "ls180.v:418.6-418.63"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
- attribute \src "ls180.v:411.6-411.69"
+ attribute \src "ls180.v:419.6-419.69"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
- attribute \src "ls180.v:420.11-420.66"
+ attribute \src "ls180.v:428.11-428.66"
wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
- attribute \src "ls180.v:421.13-421.70"
+ attribute \src "ls180.v:429.13-429.70"
wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r
- attribute \src "ls180.v:423.13-423.70"
+ attribute \src "ls180.v:431.13-431.70"
wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
- attribute \src "ls180.v:422.6-422.60"
+ attribute \src "ls180.v:430.6-430.60"
wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:437.6-437.51"
+ attribute \src "ls180.v:445.6-445.51"
wire \main_sdram_bankmachine0_cmd_buffer_sink_first
- attribute \src "ls180.v:438.6-438.50"
+ attribute \src "ls180.v:446.6-446.50"
wire \main_sdram_bankmachine0_cmd_buffer_sink_last
- attribute \src "ls180.v:440.13-440.65"
+ attribute \src "ls180.v:448.13-448.65"
wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr
- attribute \src "ls180.v:439.6-439.56"
+ attribute \src "ls180.v:447.6-447.56"
wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we
- attribute \src "ls180.v:436.6-436.51"
+ attribute \src "ls180.v:444.6-444.51"
wire \main_sdram_bankmachine0_cmd_buffer_sink_ready
- attribute \src "ls180.v:435.6-435.51"
+ attribute \src "ls180.v:443.6-443.51"
wire \main_sdram_bankmachine0_cmd_buffer_sink_valid
- attribute \src "ls180.v:443.5-443.52"
+ attribute \src "ls180.v:451.5-451.52"
wire \main_sdram_bankmachine0_cmd_buffer_source_first
- attribute \src "ls180.v:444.5-444.51"
+ attribute \src "ls180.v:452.5-452.51"
wire \main_sdram_bankmachine0_cmd_buffer_source_last
- attribute \src "ls180.v:446.12-446.66"
+ attribute \src "ls180.v:454.12-454.66"
wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr
- attribute \src "ls180.v:445.5-445.57"
+ attribute \src "ls180.v:453.5-453.57"
wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we
- attribute \src "ls180.v:442.6-442.53"
+ attribute \src "ls180.v:450.6-450.53"
wire \main_sdram_bankmachine0_cmd_buffer_source_ready
- attribute \src "ls180.v:441.5-441.52"
+ attribute \src "ls180.v:449.5-449.52"
wire \main_sdram_bankmachine0_cmd_buffer_source_valid
- attribute \src "ls180.v:389.12-389.49"
+ attribute \src "ls180.v:397.12-397.49"
wire width 13 \main_sdram_bankmachine0_cmd_payload_a
- attribute \src "ls180.v:390.12-390.50"
+ attribute \src "ls180.v:398.12-398.50"
wire width 2 \main_sdram_bankmachine0_cmd_payload_ba
- attribute \src "ls180.v:391.5-391.44"
+ attribute \src "ls180.v:399.5-399.44"
wire \main_sdram_bankmachine0_cmd_payload_cas
- attribute \src "ls180.v:394.5-394.47"
+ attribute \src "ls180.v:402.5-402.47"
wire \main_sdram_bankmachine0_cmd_payload_is_cmd
- attribute \src "ls180.v:395.5-395.48"
+ attribute \src "ls180.v:403.5-403.48"
wire \main_sdram_bankmachine0_cmd_payload_is_read
- attribute \src "ls180.v:396.5-396.49"
+ attribute \src "ls180.v:404.5-404.49"
wire \main_sdram_bankmachine0_cmd_payload_is_write
- attribute \src "ls180.v:392.5-392.44"
+ attribute \src "ls180.v:400.5-400.44"
wire \main_sdram_bankmachine0_cmd_payload_ras
- attribute \src "ls180.v:393.5-393.43"
+ attribute \src "ls180.v:401.5-401.43"
wire \main_sdram_bankmachine0_cmd_payload_we
- attribute \src "ls180.v:388.5-388.38"
+ attribute \src "ls180.v:396.5-396.38"
wire \main_sdram_bankmachine0_cmd_ready
- attribute \src "ls180.v:387.5-387.38"
+ attribute \src "ls180.v:395.5-395.38"
wire \main_sdram_bankmachine0_cmd_valid
- attribute \src "ls180.v:386.5-386.40"
+ attribute \src "ls180.v:394.5-394.40"
wire \main_sdram_bankmachine0_refresh_gnt
- attribute \src "ls180.v:385.6-385.41"
+ attribute \src "ls180.v:393.6-393.41"
wire \main_sdram_bankmachine0_refresh_req
- attribute \src "ls180.v:381.13-381.45"
+ attribute \src "ls180.v:389.13-389.45"
wire width 22 \main_sdram_bankmachine0_req_addr
- attribute \src "ls180.v:382.6-382.38"
+ attribute \src "ls180.v:390.6-390.38"
wire \main_sdram_bankmachine0_req_lock
- attribute \src "ls180.v:384.5-384.44"
+ attribute \src "ls180.v:392.5-392.44"
wire \main_sdram_bankmachine0_req_rdata_valid
- attribute \src "ls180.v:379.6-379.39"
+ attribute \src "ls180.v:387.6-387.39"
wire \main_sdram_bankmachine0_req_ready
- attribute \src "ls180.v:378.6-378.39"
+ attribute \src "ls180.v:386.6-386.39"
wire \main_sdram_bankmachine0_req_valid
- attribute \src "ls180.v:383.5-383.44"
+ attribute \src "ls180.v:391.5-391.44"
wire \main_sdram_bankmachine0_req_wdata_ready
- attribute \src "ls180.v:380.6-380.36"
+ attribute \src "ls180.v:388.6-388.36"
wire \main_sdram_bankmachine0_req_we
- attribute \src "ls180.v:447.12-447.39"
+ attribute \src "ls180.v:455.12-455.39"
wire width 13 \main_sdram_bankmachine0_row
- attribute \src "ls180.v:451.5-451.38"
+ attribute \src "ls180.v:459.5-459.38"
wire \main_sdram_bankmachine0_row_close
- attribute \src "ls180.v:452.5-452.47"
+ attribute \src "ls180.v:460.5-460.47"
wire \main_sdram_bankmachine0_row_col_n_addr_sel
- attribute \src "ls180.v:449.6-449.37"
+ attribute \src "ls180.v:457.6-457.37"
wire \main_sdram_bankmachine0_row_hit
- attribute \src "ls180.v:450.5-450.37"
+ attribute \src "ls180.v:458.5-458.37"
wire \main_sdram_bankmachine0_row_open
- attribute \src "ls180.v:448.5-448.39"
+ attribute \src "ls180.v:456.5-456.39"
wire \main_sdram_bankmachine0_row_opened
attribute \no_retiming "true"
- attribute \src "ls180.v:459.32-459.69"
+ attribute \src "ls180.v:467.32-467.69"
wire \main_sdram_bankmachine0_trascon_ready
- attribute \src "ls180.v:458.6-458.43"
+ attribute \src "ls180.v:466.6-466.43"
wire \main_sdram_bankmachine0_trascon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:457.32-457.68"
+ attribute \src "ls180.v:465.32-465.68"
wire \main_sdram_bankmachine0_trccon_ready
- attribute \src "ls180.v:456.6-456.42"
+ attribute \src "ls180.v:464.6-464.42"
wire \main_sdram_bankmachine0_trccon_valid
- attribute \src "ls180.v:455.11-455.48"
+ attribute \src "ls180.v:463.11-463.48"
wire width 3 \main_sdram_bankmachine0_twtpcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:454.32-454.69"
+ attribute \src "ls180.v:462.32-462.69"
wire \main_sdram_bankmachine0_twtpcon_ready
- attribute \src "ls180.v:453.6-453.43"
+ attribute \src "ls180.v:461.6-461.43"
wire \main_sdram_bankmachine0_twtpcon_valid
- attribute \src "ls180.v:479.5-479.43"
+ attribute \src "ls180.v:487.5-487.43"
wire \main_sdram_bankmachine1_auto_precharge
- attribute \src "ls180.v:501.11-501.63"
+ attribute \src "ls180.v:509.11-509.63"
wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
- attribute \src "ls180.v:506.6-506.58"
+ attribute \src "ls180.v:514.6-514.58"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:511.6-511.64"
+ attribute \src "ls180.v:519.6-519.64"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first
- attribute \src "ls180.v:512.6-512.63"
+ attribute \src "ls180.v:520.6-520.63"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last
- attribute \src "ls180.v:510.13-510.78"
+ attribute \src "ls180.v:518.13-518.78"
wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr
- attribute \src "ls180.v:509.6-509.69"
+ attribute \src "ls180.v:517.6-517.69"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we
- attribute \src "ls180.v:515.6-515.65"
+ attribute \src "ls180.v:523.6-523.65"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first
- attribute \src "ls180.v:516.6-516.64"
+ attribute \src "ls180.v:524.6-524.64"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last
- attribute \src "ls180.v:514.13-514.79"
+ attribute \src "ls180.v:522.13-522.79"
wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr
- attribute \src "ls180.v:513.6-513.70"
+ attribute \src "ls180.v:521.6-521.70"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we
- attribute \src "ls180.v:498.11-498.61"
+ attribute \src "ls180.v:506.11-506.61"
wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level
- attribute \src "ls180.v:500.11-500.63"
+ attribute \src "ls180.v:508.11-508.63"
wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
- attribute \src "ls180.v:507.12-507.67"
+ attribute \src "ls180.v:515.12-515.67"
wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr
- attribute \src "ls180.v:508.13-508.70"
+ attribute \src "ls180.v:516.13-516.70"
wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r
- attribute \src "ls180.v:499.5-499.57"
+ attribute \src "ls180.v:507.5-507.57"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:482.5-482.60"
+ attribute \src "ls180.v:490.5-490.60"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first
- attribute \src "ls180.v:483.5-483.59"
+ attribute \src "ls180.v:491.5-491.59"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last
- attribute \src "ls180.v:485.13-485.75"
+ attribute \src "ls180.v:493.13-493.75"
wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr
- attribute \src "ls180.v:484.6-484.66"
+ attribute \src "ls180.v:492.6-492.66"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we
- attribute \src "ls180.v:481.6-481.61"
+ attribute \src "ls180.v:489.6-489.61"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready
- attribute \src "ls180.v:480.6-480.61"
+ attribute \src "ls180.v:488.6-488.61"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid
- attribute \src "ls180.v:488.6-488.63"
+ attribute \src "ls180.v:496.6-496.63"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first
- attribute \src "ls180.v:489.6-489.62"
+ attribute \src "ls180.v:497.6-497.62"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last
- attribute \src "ls180.v:491.13-491.77"
+ attribute \src "ls180.v:499.13-499.77"
wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr
- attribute \src "ls180.v:490.6-490.68"
+ attribute \src "ls180.v:498.6-498.68"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we
- attribute \src "ls180.v:487.6-487.63"
+ attribute \src "ls180.v:495.6-495.63"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready
- attribute \src "ls180.v:486.6-486.63"
+ attribute \src "ls180.v:494.6-494.63"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid
- attribute \src "ls180.v:496.13-496.71"
+ attribute \src "ls180.v:504.13-504.71"
wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din
- attribute \src "ls180.v:497.13-497.72"
+ attribute \src "ls180.v:505.13-505.72"
wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout
- attribute \src "ls180.v:494.6-494.63"
+ attribute \src "ls180.v:502.6-502.63"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re
- attribute \src "ls180.v:495.6-495.69"
+ attribute \src "ls180.v:503.6-503.69"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable
- attribute \src "ls180.v:492.6-492.63"
+ attribute \src "ls180.v:500.6-500.63"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
- attribute \src "ls180.v:493.6-493.69"
+ attribute \src "ls180.v:501.6-501.69"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
- attribute \src "ls180.v:502.11-502.66"
+ attribute \src "ls180.v:510.11-510.66"
wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
- attribute \src "ls180.v:503.13-503.70"
+ attribute \src "ls180.v:511.13-511.70"
wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r
- attribute \src "ls180.v:505.13-505.70"
+ attribute \src "ls180.v:513.13-513.70"
wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
- attribute \src "ls180.v:504.6-504.60"
+ attribute \src "ls180.v:512.6-512.60"
wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:519.6-519.51"
+ attribute \src "ls180.v:527.6-527.51"
wire \main_sdram_bankmachine1_cmd_buffer_sink_first
- attribute \src "ls180.v:520.6-520.50"
+ attribute \src "ls180.v:528.6-528.50"
wire \main_sdram_bankmachine1_cmd_buffer_sink_last
- attribute \src "ls180.v:522.13-522.65"
+ attribute \src "ls180.v:530.13-530.65"
wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr
- attribute \src "ls180.v:521.6-521.56"
+ attribute \src "ls180.v:529.6-529.56"
wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we
- attribute \src "ls180.v:518.6-518.51"
+ attribute \src "ls180.v:526.6-526.51"
wire \main_sdram_bankmachine1_cmd_buffer_sink_ready
- attribute \src "ls180.v:517.6-517.51"
+ attribute \src "ls180.v:525.6-525.51"
wire \main_sdram_bankmachine1_cmd_buffer_sink_valid
- attribute \src "ls180.v:525.5-525.52"
+ attribute \src "ls180.v:533.5-533.52"
wire \main_sdram_bankmachine1_cmd_buffer_source_first
- attribute \src "ls180.v:526.5-526.51"
+ attribute \src "ls180.v:534.5-534.51"
wire \main_sdram_bankmachine1_cmd_buffer_source_last
- attribute \src "ls180.v:528.12-528.66"
+ attribute \src "ls180.v:536.12-536.66"
wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr
- attribute \src "ls180.v:527.5-527.57"
+ attribute \src "ls180.v:535.5-535.57"
wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we
- attribute \src "ls180.v:524.6-524.53"
+ attribute \src "ls180.v:532.6-532.53"
wire \main_sdram_bankmachine1_cmd_buffer_source_ready
- attribute \src "ls180.v:523.5-523.52"
+ attribute \src "ls180.v:531.5-531.52"
wire \main_sdram_bankmachine1_cmd_buffer_source_valid
- attribute \src "ls180.v:471.12-471.49"
+ attribute \src "ls180.v:479.12-479.49"
wire width 13 \main_sdram_bankmachine1_cmd_payload_a
- attribute \src "ls180.v:472.12-472.50"
+ attribute \src "ls180.v:480.12-480.50"
wire width 2 \main_sdram_bankmachine1_cmd_payload_ba
- attribute \src "ls180.v:473.5-473.44"
+ attribute \src "ls180.v:481.5-481.44"
wire \main_sdram_bankmachine1_cmd_payload_cas
- attribute \src "ls180.v:476.5-476.47"
+ attribute \src "ls180.v:484.5-484.47"
wire \main_sdram_bankmachine1_cmd_payload_is_cmd
- attribute \src "ls180.v:477.5-477.48"
+ attribute \src "ls180.v:485.5-485.48"
wire \main_sdram_bankmachine1_cmd_payload_is_read
- attribute \src "ls180.v:478.5-478.49"
+ attribute \src "ls180.v:486.5-486.49"
wire \main_sdram_bankmachine1_cmd_payload_is_write
- attribute \src "ls180.v:474.5-474.44"
+ attribute \src "ls180.v:482.5-482.44"
wire \main_sdram_bankmachine1_cmd_payload_ras
- attribute \src "ls180.v:475.5-475.43"
+ attribute \src "ls180.v:483.5-483.43"
wire \main_sdram_bankmachine1_cmd_payload_we
- attribute \src "ls180.v:470.5-470.38"
+ attribute \src "ls180.v:478.5-478.38"
wire \main_sdram_bankmachine1_cmd_ready
- attribute \src "ls180.v:469.5-469.38"
+ attribute \src "ls180.v:477.5-477.38"
wire \main_sdram_bankmachine1_cmd_valid
- attribute \src "ls180.v:468.5-468.40"
+ attribute \src "ls180.v:476.5-476.40"
wire \main_sdram_bankmachine1_refresh_gnt
- attribute \src "ls180.v:467.6-467.41"
+ attribute \src "ls180.v:475.6-475.41"
wire \main_sdram_bankmachine1_refresh_req
- attribute \src "ls180.v:463.13-463.45"
+ attribute \src "ls180.v:471.13-471.45"
wire width 22 \main_sdram_bankmachine1_req_addr
- attribute \src "ls180.v:464.6-464.38"
+ attribute \src "ls180.v:472.6-472.38"
wire \main_sdram_bankmachine1_req_lock
- attribute \src "ls180.v:466.5-466.44"
+ attribute \src "ls180.v:474.5-474.44"
wire \main_sdram_bankmachine1_req_rdata_valid
- attribute \src "ls180.v:461.6-461.39"
+ attribute \src "ls180.v:469.6-469.39"
wire \main_sdram_bankmachine1_req_ready
- attribute \src "ls180.v:460.6-460.39"
+ attribute \src "ls180.v:468.6-468.39"
wire \main_sdram_bankmachine1_req_valid
- attribute \src "ls180.v:465.5-465.44"
+ attribute \src "ls180.v:473.5-473.44"
wire \main_sdram_bankmachine1_req_wdata_ready
- attribute \src "ls180.v:462.6-462.36"
+ attribute \src "ls180.v:470.6-470.36"
wire \main_sdram_bankmachine1_req_we
- attribute \src "ls180.v:529.12-529.39"
+ attribute \src "ls180.v:537.12-537.39"
wire width 13 \main_sdram_bankmachine1_row
- attribute \src "ls180.v:533.5-533.38"
+ attribute \src "ls180.v:541.5-541.38"
wire \main_sdram_bankmachine1_row_close
- attribute \src "ls180.v:534.5-534.47"
+ attribute \src "ls180.v:542.5-542.47"
wire \main_sdram_bankmachine1_row_col_n_addr_sel
- attribute \src "ls180.v:531.6-531.37"
+ attribute \src "ls180.v:539.6-539.37"
wire \main_sdram_bankmachine1_row_hit
- attribute \src "ls180.v:532.5-532.37"
+ attribute \src "ls180.v:540.5-540.37"
wire \main_sdram_bankmachine1_row_open
- attribute \src "ls180.v:530.5-530.39"
+ attribute \src "ls180.v:538.5-538.39"
wire \main_sdram_bankmachine1_row_opened
attribute \no_retiming "true"
- attribute \src "ls180.v:541.32-541.69"
+ attribute \src "ls180.v:549.32-549.69"
wire \main_sdram_bankmachine1_trascon_ready
- attribute \src "ls180.v:540.6-540.43"
+ attribute \src "ls180.v:548.6-548.43"
wire \main_sdram_bankmachine1_trascon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:539.32-539.68"
+ attribute \src "ls180.v:547.32-547.68"
wire \main_sdram_bankmachine1_trccon_ready
- attribute \src "ls180.v:538.6-538.42"
+ attribute \src "ls180.v:546.6-546.42"
wire \main_sdram_bankmachine1_trccon_valid
- attribute \src "ls180.v:537.11-537.48"
+ attribute \src "ls180.v:545.11-545.48"
wire width 3 \main_sdram_bankmachine1_twtpcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:536.32-536.69"
+ attribute \src "ls180.v:544.32-544.69"
wire \main_sdram_bankmachine1_twtpcon_ready
- attribute \src "ls180.v:535.6-535.43"
+ attribute \src "ls180.v:543.6-543.43"
wire \main_sdram_bankmachine1_twtpcon_valid
- attribute \src "ls180.v:561.5-561.43"
+ attribute \src "ls180.v:569.5-569.43"
wire \main_sdram_bankmachine2_auto_precharge
- attribute \src "ls180.v:583.11-583.63"
+ attribute \src "ls180.v:591.11-591.63"
wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
- attribute \src "ls180.v:588.6-588.58"
+ attribute \src "ls180.v:596.6-596.58"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:593.6-593.64"
+ attribute \src "ls180.v:601.6-601.64"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first
- attribute \src "ls180.v:594.6-594.63"
+ attribute \src "ls180.v:602.6-602.63"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last
- attribute \src "ls180.v:592.13-592.78"
+ attribute \src "ls180.v:600.13-600.78"
wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr
- attribute \src "ls180.v:591.6-591.69"
+ attribute \src "ls180.v:599.6-599.69"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we
- attribute \src "ls180.v:597.6-597.65"
+ attribute \src "ls180.v:605.6-605.65"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first
- attribute \src "ls180.v:598.6-598.64"
+ attribute \src "ls180.v:606.6-606.64"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last
- attribute \src "ls180.v:596.13-596.79"
+ attribute \src "ls180.v:604.13-604.79"
wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr
- attribute \src "ls180.v:595.6-595.70"
+ attribute \src "ls180.v:603.6-603.70"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we
- attribute \src "ls180.v:580.11-580.61"
+ attribute \src "ls180.v:588.11-588.61"
wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level
- attribute \src "ls180.v:582.11-582.63"
+ attribute \src "ls180.v:590.11-590.63"
wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
- attribute \src "ls180.v:589.12-589.67"
+ attribute \src "ls180.v:597.12-597.67"
wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr
- attribute \src "ls180.v:590.13-590.70"
+ attribute \src "ls180.v:598.13-598.70"
wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r
- attribute \src "ls180.v:581.5-581.57"
+ attribute \src "ls180.v:589.5-589.57"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:564.5-564.60"
+ attribute \src "ls180.v:572.5-572.60"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first
- attribute \src "ls180.v:565.5-565.59"
+ attribute \src "ls180.v:573.5-573.59"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last
- attribute \src "ls180.v:567.13-567.75"
+ attribute \src "ls180.v:575.13-575.75"
wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr
- attribute \src "ls180.v:566.6-566.66"
+ attribute \src "ls180.v:574.6-574.66"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we
- attribute \src "ls180.v:563.6-563.61"
+ attribute \src "ls180.v:571.6-571.61"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready
- attribute \src "ls180.v:562.6-562.61"
+ attribute \src "ls180.v:570.6-570.61"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid
- attribute \src "ls180.v:570.6-570.63"
+ attribute \src "ls180.v:578.6-578.63"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first
- attribute \src "ls180.v:571.6-571.62"
+ attribute \src "ls180.v:579.6-579.62"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last
- attribute \src "ls180.v:573.13-573.77"
+ attribute \src "ls180.v:581.13-581.77"
wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr
- attribute \src "ls180.v:572.6-572.68"
+ attribute \src "ls180.v:580.6-580.68"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we
- attribute \src "ls180.v:569.6-569.63"
+ attribute \src "ls180.v:577.6-577.63"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready
- attribute \src "ls180.v:568.6-568.63"
+ attribute \src "ls180.v:576.6-576.63"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid
- attribute \src "ls180.v:578.13-578.71"
+ attribute \src "ls180.v:586.13-586.71"
wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din
- attribute \src "ls180.v:579.13-579.72"
+ attribute \src "ls180.v:587.13-587.72"
wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout
- attribute \src "ls180.v:576.6-576.63"
+ attribute \src "ls180.v:584.6-584.63"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re
- attribute \src "ls180.v:577.6-577.69"
+ attribute \src "ls180.v:585.6-585.69"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable
- attribute \src "ls180.v:574.6-574.63"
+ attribute \src "ls180.v:582.6-582.63"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
- attribute \src "ls180.v:575.6-575.69"
+ attribute \src "ls180.v:583.6-583.69"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
- attribute \src "ls180.v:584.11-584.66"
+ attribute \src "ls180.v:592.11-592.66"
wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
- attribute \src "ls180.v:585.13-585.70"
+ attribute \src "ls180.v:593.13-593.70"
wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r
- attribute \src "ls180.v:587.13-587.70"
+ attribute \src "ls180.v:595.13-595.70"
wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
- attribute \src "ls180.v:586.6-586.60"
+ attribute \src "ls180.v:594.6-594.60"
wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:601.6-601.51"
+ attribute \src "ls180.v:609.6-609.51"
wire \main_sdram_bankmachine2_cmd_buffer_sink_first
- attribute \src "ls180.v:602.6-602.50"
+ attribute \src "ls180.v:610.6-610.50"
wire \main_sdram_bankmachine2_cmd_buffer_sink_last
- attribute \src "ls180.v:604.13-604.65"
+ attribute \src "ls180.v:612.13-612.65"
wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr
- attribute \src "ls180.v:603.6-603.56"
+ attribute \src "ls180.v:611.6-611.56"
wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we
- attribute \src "ls180.v:600.6-600.51"
+ attribute \src "ls180.v:608.6-608.51"
wire \main_sdram_bankmachine2_cmd_buffer_sink_ready
- attribute \src "ls180.v:599.6-599.51"
+ attribute \src "ls180.v:607.6-607.51"
wire \main_sdram_bankmachine2_cmd_buffer_sink_valid
- attribute \src "ls180.v:607.5-607.52"
+ attribute \src "ls180.v:615.5-615.52"
wire \main_sdram_bankmachine2_cmd_buffer_source_first
- attribute \src "ls180.v:608.5-608.51"
+ attribute \src "ls180.v:616.5-616.51"
wire \main_sdram_bankmachine2_cmd_buffer_source_last
- attribute \src "ls180.v:610.12-610.66"
+ attribute \src "ls180.v:618.12-618.66"
wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr
- attribute \src "ls180.v:609.5-609.57"
+ attribute \src "ls180.v:617.5-617.57"
wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we
- attribute \src "ls180.v:606.6-606.53"
+ attribute \src "ls180.v:614.6-614.53"
wire \main_sdram_bankmachine2_cmd_buffer_source_ready
- attribute \src "ls180.v:605.5-605.52"
+ attribute \src "ls180.v:613.5-613.52"
wire \main_sdram_bankmachine2_cmd_buffer_source_valid
- attribute \src "ls180.v:553.12-553.49"
+ attribute \src "ls180.v:561.12-561.49"
wire width 13 \main_sdram_bankmachine2_cmd_payload_a
- attribute \src "ls180.v:554.12-554.50"
+ attribute \src "ls180.v:562.12-562.50"
wire width 2 \main_sdram_bankmachine2_cmd_payload_ba
- attribute \src "ls180.v:555.5-555.44"
+ attribute \src "ls180.v:563.5-563.44"
wire \main_sdram_bankmachine2_cmd_payload_cas
- attribute \src "ls180.v:558.5-558.47"
+ attribute \src "ls180.v:566.5-566.47"
wire \main_sdram_bankmachine2_cmd_payload_is_cmd
- attribute \src "ls180.v:559.5-559.48"
+ attribute \src "ls180.v:567.5-567.48"
wire \main_sdram_bankmachine2_cmd_payload_is_read
- attribute \src "ls180.v:560.5-560.49"
+ attribute \src "ls180.v:568.5-568.49"
wire \main_sdram_bankmachine2_cmd_payload_is_write
- attribute \src "ls180.v:556.5-556.44"
+ attribute \src "ls180.v:564.5-564.44"
wire \main_sdram_bankmachine2_cmd_payload_ras
- attribute \src "ls180.v:557.5-557.43"
+ attribute \src "ls180.v:565.5-565.43"
wire \main_sdram_bankmachine2_cmd_payload_we
- attribute \src "ls180.v:552.5-552.38"
+ attribute \src "ls180.v:560.5-560.38"
wire \main_sdram_bankmachine2_cmd_ready
- attribute \src "ls180.v:551.5-551.38"
+ attribute \src "ls180.v:559.5-559.38"
wire \main_sdram_bankmachine2_cmd_valid
- attribute \src "ls180.v:550.5-550.40"
+ attribute \src "ls180.v:558.5-558.40"
wire \main_sdram_bankmachine2_refresh_gnt
- attribute \src "ls180.v:549.6-549.41"
+ attribute \src "ls180.v:557.6-557.41"
wire \main_sdram_bankmachine2_refresh_req
- attribute \src "ls180.v:545.13-545.45"
+ attribute \src "ls180.v:553.13-553.45"
wire width 22 \main_sdram_bankmachine2_req_addr
- attribute \src "ls180.v:546.6-546.38"
+ attribute \src "ls180.v:554.6-554.38"
wire \main_sdram_bankmachine2_req_lock
- attribute \src "ls180.v:548.5-548.44"
+ attribute \src "ls180.v:556.5-556.44"
wire \main_sdram_bankmachine2_req_rdata_valid
- attribute \src "ls180.v:543.6-543.39"
+ attribute \src "ls180.v:551.6-551.39"
wire \main_sdram_bankmachine2_req_ready
- attribute \src "ls180.v:542.6-542.39"
+ attribute \src "ls180.v:550.6-550.39"
wire \main_sdram_bankmachine2_req_valid
- attribute \src "ls180.v:547.5-547.44"
+ attribute \src "ls180.v:555.5-555.44"
wire \main_sdram_bankmachine2_req_wdata_ready
- attribute \src "ls180.v:544.6-544.36"
+ attribute \src "ls180.v:552.6-552.36"
wire \main_sdram_bankmachine2_req_we
- attribute \src "ls180.v:611.12-611.39"
+ attribute \src "ls180.v:619.12-619.39"
wire width 13 \main_sdram_bankmachine2_row
- attribute \src "ls180.v:615.5-615.38"
+ attribute \src "ls180.v:623.5-623.38"
wire \main_sdram_bankmachine2_row_close
- attribute \src "ls180.v:616.5-616.47"
+ attribute \src "ls180.v:624.5-624.47"
wire \main_sdram_bankmachine2_row_col_n_addr_sel
- attribute \src "ls180.v:613.6-613.37"
+ attribute \src "ls180.v:621.6-621.37"
wire \main_sdram_bankmachine2_row_hit
- attribute \src "ls180.v:614.5-614.37"
+ attribute \src "ls180.v:622.5-622.37"
wire \main_sdram_bankmachine2_row_open
- attribute \src "ls180.v:612.5-612.39"
+ attribute \src "ls180.v:620.5-620.39"
wire \main_sdram_bankmachine2_row_opened
attribute \no_retiming "true"
- attribute \src "ls180.v:623.32-623.69"
+ attribute \src "ls180.v:631.32-631.69"
wire \main_sdram_bankmachine2_trascon_ready
- attribute \src "ls180.v:622.6-622.43"
+ attribute \src "ls180.v:630.6-630.43"
wire \main_sdram_bankmachine2_trascon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:621.32-621.68"
+ attribute \src "ls180.v:629.32-629.68"
wire \main_sdram_bankmachine2_trccon_ready
- attribute \src "ls180.v:620.6-620.42"
+ attribute \src "ls180.v:628.6-628.42"
wire \main_sdram_bankmachine2_trccon_valid
- attribute \src "ls180.v:619.11-619.48"
+ attribute \src "ls180.v:627.11-627.48"
wire width 3 \main_sdram_bankmachine2_twtpcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:618.32-618.69"
+ attribute \src "ls180.v:626.32-626.69"
wire \main_sdram_bankmachine2_twtpcon_ready
- attribute \src "ls180.v:617.6-617.43"
+ attribute \src "ls180.v:625.6-625.43"
wire \main_sdram_bankmachine2_twtpcon_valid
- attribute \src "ls180.v:643.5-643.43"
+ attribute \src "ls180.v:651.5-651.43"
wire \main_sdram_bankmachine3_auto_precharge
- attribute \src "ls180.v:665.11-665.63"
+ attribute \src "ls180.v:673.11-673.63"
wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
- attribute \src "ls180.v:670.6-670.58"
+ attribute \src "ls180.v:678.6-678.58"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:675.6-675.64"
+ attribute \src "ls180.v:683.6-683.64"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first
- attribute \src "ls180.v:676.6-676.63"
+ attribute \src "ls180.v:684.6-684.63"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last
- attribute \src "ls180.v:674.13-674.78"
+ attribute \src "ls180.v:682.13-682.78"
wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr
- attribute \src "ls180.v:673.6-673.69"
+ attribute \src "ls180.v:681.6-681.69"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we
- attribute \src "ls180.v:679.6-679.65"
+ attribute \src "ls180.v:687.6-687.65"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first
- attribute \src "ls180.v:680.6-680.64"
+ attribute \src "ls180.v:688.6-688.64"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last
- attribute \src "ls180.v:678.13-678.79"
+ attribute \src "ls180.v:686.13-686.79"
wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr
- attribute \src "ls180.v:677.6-677.70"
+ attribute \src "ls180.v:685.6-685.70"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we
- attribute \src "ls180.v:662.11-662.61"
+ attribute \src "ls180.v:670.11-670.61"
wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level
- attribute \src "ls180.v:664.11-664.63"
+ attribute \src "ls180.v:672.11-672.63"
wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
- attribute \src "ls180.v:671.12-671.67"
+ attribute \src "ls180.v:679.12-679.67"
wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr
- attribute \src "ls180.v:672.13-672.70"
+ attribute \src "ls180.v:680.13-680.70"
wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r
- attribute \src "ls180.v:663.5-663.57"
+ attribute \src "ls180.v:671.5-671.57"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:646.5-646.60"
+ attribute \src "ls180.v:654.5-654.60"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first
- attribute \src "ls180.v:647.5-647.59"
+ attribute \src "ls180.v:655.5-655.59"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last
- attribute \src "ls180.v:649.13-649.75"
+ attribute \src "ls180.v:657.13-657.75"
wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr
- attribute \src "ls180.v:648.6-648.66"
+ attribute \src "ls180.v:656.6-656.66"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we
- attribute \src "ls180.v:645.6-645.61"
+ attribute \src "ls180.v:653.6-653.61"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready
- attribute \src "ls180.v:644.6-644.61"
+ attribute \src "ls180.v:652.6-652.61"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid
- attribute \src "ls180.v:652.6-652.63"
+ attribute \src "ls180.v:660.6-660.63"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first
- attribute \src "ls180.v:653.6-653.62"
+ attribute \src "ls180.v:661.6-661.62"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last
- attribute \src "ls180.v:655.13-655.77"
+ attribute \src "ls180.v:663.13-663.77"
wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr
- attribute \src "ls180.v:654.6-654.68"
+ attribute \src "ls180.v:662.6-662.68"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we
- attribute \src "ls180.v:651.6-651.63"
+ attribute \src "ls180.v:659.6-659.63"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready
- attribute \src "ls180.v:650.6-650.63"
+ attribute \src "ls180.v:658.6-658.63"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid
- attribute \src "ls180.v:660.13-660.71"
+ attribute \src "ls180.v:668.13-668.71"
wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din
- attribute \src "ls180.v:661.13-661.72"
+ attribute \src "ls180.v:669.13-669.72"
wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout
- attribute \src "ls180.v:658.6-658.63"
+ attribute \src "ls180.v:666.6-666.63"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re
- attribute \src "ls180.v:659.6-659.69"
+ attribute \src "ls180.v:667.6-667.69"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable
- attribute \src "ls180.v:656.6-656.63"
+ attribute \src "ls180.v:664.6-664.63"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
- attribute \src "ls180.v:657.6-657.69"
+ attribute \src "ls180.v:665.6-665.69"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
- attribute \src "ls180.v:666.11-666.66"
+ attribute \src "ls180.v:674.11-674.66"
wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
- attribute \src "ls180.v:667.13-667.70"
+ attribute \src "ls180.v:675.13-675.70"
wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r
- attribute \src "ls180.v:669.13-669.70"
+ attribute \src "ls180.v:677.13-677.70"
wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
- attribute \src "ls180.v:668.6-668.60"
+ attribute \src "ls180.v:676.6-676.60"
wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:683.6-683.51"
+ attribute \src "ls180.v:691.6-691.51"
wire \main_sdram_bankmachine3_cmd_buffer_sink_first
- attribute \src "ls180.v:684.6-684.50"
+ attribute \src "ls180.v:692.6-692.50"
wire \main_sdram_bankmachine3_cmd_buffer_sink_last
- attribute \src "ls180.v:686.13-686.65"
+ attribute \src "ls180.v:694.13-694.65"
wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr
- attribute \src "ls180.v:685.6-685.56"
+ attribute \src "ls180.v:693.6-693.56"
wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we
- attribute \src "ls180.v:682.6-682.51"
+ attribute \src "ls180.v:690.6-690.51"
wire \main_sdram_bankmachine3_cmd_buffer_sink_ready
- attribute \src "ls180.v:681.6-681.51"
+ attribute \src "ls180.v:689.6-689.51"
wire \main_sdram_bankmachine3_cmd_buffer_sink_valid
- attribute \src "ls180.v:689.5-689.52"
+ attribute \src "ls180.v:697.5-697.52"
wire \main_sdram_bankmachine3_cmd_buffer_source_first
- attribute \src "ls180.v:690.5-690.51"
+ attribute \src "ls180.v:698.5-698.51"
wire \main_sdram_bankmachine3_cmd_buffer_source_last
- attribute \src "ls180.v:692.12-692.66"
+ attribute \src "ls180.v:700.12-700.66"
wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr
- attribute \src "ls180.v:691.5-691.57"
+ attribute \src "ls180.v:699.5-699.57"
wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we
- attribute \src "ls180.v:688.6-688.53"
+ attribute \src "ls180.v:696.6-696.53"
wire \main_sdram_bankmachine3_cmd_buffer_source_ready
- attribute \src "ls180.v:687.5-687.52"
+ attribute \src "ls180.v:695.5-695.52"
wire \main_sdram_bankmachine3_cmd_buffer_source_valid
- attribute \src "ls180.v:635.12-635.49"
+ attribute \src "ls180.v:643.12-643.49"
wire width 13 \main_sdram_bankmachine3_cmd_payload_a
- attribute \src "ls180.v:636.12-636.50"
+ attribute \src "ls180.v:644.12-644.50"
wire width 2 \main_sdram_bankmachine3_cmd_payload_ba
- attribute \src "ls180.v:637.5-637.44"
+ attribute \src "ls180.v:645.5-645.44"
wire \main_sdram_bankmachine3_cmd_payload_cas
- attribute \src "ls180.v:640.5-640.47"
+ attribute \src "ls180.v:648.5-648.47"
wire \main_sdram_bankmachine3_cmd_payload_is_cmd
- attribute \src "ls180.v:641.5-641.48"
+ attribute \src "ls180.v:649.5-649.48"
wire \main_sdram_bankmachine3_cmd_payload_is_read
- attribute \src "ls180.v:642.5-642.49"
+ attribute \src "ls180.v:650.5-650.49"
wire \main_sdram_bankmachine3_cmd_payload_is_write
- attribute \src "ls180.v:638.5-638.44"
+ attribute \src "ls180.v:646.5-646.44"
wire \main_sdram_bankmachine3_cmd_payload_ras
- attribute \src "ls180.v:639.5-639.43"
+ attribute \src "ls180.v:647.5-647.43"
wire \main_sdram_bankmachine3_cmd_payload_we
- attribute \src "ls180.v:634.5-634.38"
+ attribute \src "ls180.v:642.5-642.38"
wire \main_sdram_bankmachine3_cmd_ready
- attribute \src "ls180.v:633.5-633.38"
+ attribute \src "ls180.v:641.5-641.38"
wire \main_sdram_bankmachine3_cmd_valid
- attribute \src "ls180.v:632.5-632.40"
+ attribute \src "ls180.v:640.5-640.40"
wire \main_sdram_bankmachine3_refresh_gnt
- attribute \src "ls180.v:631.6-631.41"
+ attribute \src "ls180.v:639.6-639.41"
wire \main_sdram_bankmachine3_refresh_req
- attribute \src "ls180.v:627.13-627.45"
+ attribute \src "ls180.v:635.13-635.45"
wire width 22 \main_sdram_bankmachine3_req_addr
- attribute \src "ls180.v:628.6-628.38"
+ attribute \src "ls180.v:636.6-636.38"
wire \main_sdram_bankmachine3_req_lock
- attribute \src "ls180.v:630.5-630.44"
+ attribute \src "ls180.v:638.5-638.44"
wire \main_sdram_bankmachine3_req_rdata_valid
- attribute \src "ls180.v:625.6-625.39"
+ attribute \src "ls180.v:633.6-633.39"
wire \main_sdram_bankmachine3_req_ready
- attribute \src "ls180.v:624.6-624.39"
+ attribute \src "ls180.v:632.6-632.39"
wire \main_sdram_bankmachine3_req_valid
- attribute \src "ls180.v:629.5-629.44"
+ attribute \src "ls180.v:637.5-637.44"
wire \main_sdram_bankmachine3_req_wdata_ready
- attribute \src "ls180.v:626.6-626.36"
+ attribute \src "ls180.v:634.6-634.36"
wire \main_sdram_bankmachine3_req_we
- attribute \src "ls180.v:693.12-693.39"
+ attribute \src "ls180.v:701.12-701.39"
wire width 13 \main_sdram_bankmachine3_row
- attribute \src "ls180.v:697.5-697.38"
+ attribute \src "ls180.v:705.5-705.38"
wire \main_sdram_bankmachine3_row_close
- attribute \src "ls180.v:698.5-698.47"
+ attribute \src "ls180.v:706.5-706.47"
wire \main_sdram_bankmachine3_row_col_n_addr_sel
- attribute \src "ls180.v:695.6-695.37"
+ attribute \src "ls180.v:703.6-703.37"
wire \main_sdram_bankmachine3_row_hit
- attribute \src "ls180.v:696.5-696.37"
+ attribute \src "ls180.v:704.5-704.37"
wire \main_sdram_bankmachine3_row_open
- attribute \src "ls180.v:694.5-694.39"
+ attribute \src "ls180.v:702.5-702.39"
wire \main_sdram_bankmachine3_row_opened
attribute \no_retiming "true"
- attribute \src "ls180.v:705.32-705.69"
+ attribute \src "ls180.v:713.32-713.69"
wire \main_sdram_bankmachine3_trascon_ready
- attribute \src "ls180.v:704.6-704.43"
+ attribute \src "ls180.v:712.6-712.43"
wire \main_sdram_bankmachine3_trascon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:703.32-703.68"
+ attribute \src "ls180.v:711.32-711.68"
wire \main_sdram_bankmachine3_trccon_ready
- attribute \src "ls180.v:702.6-702.42"
+ attribute \src "ls180.v:710.6-710.42"
wire \main_sdram_bankmachine3_trccon_valid
- attribute \src "ls180.v:701.11-701.48"
+ attribute \src "ls180.v:709.11-709.48"
wire width 3 \main_sdram_bankmachine3_twtpcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:700.32-700.69"
+ attribute \src "ls180.v:708.32-708.69"
wire \main_sdram_bankmachine3_twtpcon_ready
- attribute \src "ls180.v:699.6-699.43"
+ attribute \src "ls180.v:707.6-707.43"
wire \main_sdram_bankmachine3_twtpcon_valid
- attribute \src "ls180.v:707.6-707.28"
+ attribute \src "ls180.v:715.6-715.28"
wire \main_sdram_cas_allowed
- attribute \src "ls180.v:725.6-725.30"
+ attribute \src "ls180.v:733.6-733.30"
wire \main_sdram_choose_cmd_ce
- attribute \src "ls180.v:714.13-714.48"
+ attribute \src "ls180.v:722.13-722.48"
wire width 13 \main_sdram_choose_cmd_cmd_payload_a
- attribute \src "ls180.v:715.12-715.48"
+ attribute \src "ls180.v:723.12-723.48"
wire width 2 \main_sdram_choose_cmd_cmd_payload_ba
- attribute \src "ls180.v:716.5-716.42"
+ attribute \src "ls180.v:724.5-724.42"
wire \main_sdram_choose_cmd_cmd_payload_cas
- attribute \src "ls180.v:719.6-719.46"
+ attribute \src "ls180.v:727.6-727.46"
wire \main_sdram_choose_cmd_cmd_payload_is_cmd
- attribute \src "ls180.v:720.6-720.47"
+ attribute \src "ls180.v:728.6-728.47"
wire \main_sdram_choose_cmd_cmd_payload_is_read
- attribute \src "ls180.v:721.6-721.48"
+ attribute \src "ls180.v:729.6-729.48"
wire \main_sdram_choose_cmd_cmd_payload_is_write
- attribute \src "ls180.v:717.5-717.42"
+ attribute \src "ls180.v:725.5-725.42"
wire \main_sdram_choose_cmd_cmd_payload_ras
- attribute \src "ls180.v:718.5-718.41"
+ attribute \src "ls180.v:726.5-726.41"
wire \main_sdram_choose_cmd_cmd_payload_we
- attribute \src "ls180.v:713.5-713.36"
+ attribute \src "ls180.v:721.5-721.36"
wire \main_sdram_choose_cmd_cmd_ready
- attribute \src "ls180.v:712.6-712.37"
+ attribute \src "ls180.v:720.6-720.37"
wire \main_sdram_choose_cmd_cmd_valid
- attribute \src "ls180.v:724.11-724.38"
+ attribute \src "ls180.v:732.11-732.38"
wire width 2 \main_sdram_choose_cmd_grant
- attribute \src "ls180.v:723.12-723.41"
+ attribute \src "ls180.v:731.12-731.41"
wire width 4 \main_sdram_choose_cmd_request
- attribute \src "ls180.v:722.11-722.39"
+ attribute \src "ls180.v:730.11-730.39"
wire width 4 \main_sdram_choose_cmd_valids
- attribute \src "ls180.v:711.5-711.41"
+ attribute \src "ls180.v:719.5-719.41"
wire \main_sdram_choose_cmd_want_activates
- attribute \src "ls180.v:710.5-710.36"
+ attribute \src "ls180.v:718.5-718.36"
wire \main_sdram_choose_cmd_want_cmds
- attribute \src "ls180.v:708.5-708.37"
+ attribute \src "ls180.v:716.5-716.37"
wire \main_sdram_choose_cmd_want_reads
- attribute \src "ls180.v:709.5-709.38"
+ attribute \src "ls180.v:717.5-717.38"
wire \main_sdram_choose_cmd_want_writes
- attribute \src "ls180.v:743.6-743.30"
+ attribute \src "ls180.v:751.6-751.30"
wire \main_sdram_choose_req_ce
- attribute \src "ls180.v:732.13-732.48"
+ attribute \src "ls180.v:740.13-740.48"
wire width 13 \main_sdram_choose_req_cmd_payload_a
- attribute \src "ls180.v:733.12-733.48"
+ attribute \src "ls180.v:741.12-741.48"
wire width 2 \main_sdram_choose_req_cmd_payload_ba
- attribute \src "ls180.v:734.5-734.42"
+ attribute \src "ls180.v:742.5-742.42"
wire \main_sdram_choose_req_cmd_payload_cas
- attribute \src "ls180.v:737.6-737.46"
+ attribute \src "ls180.v:745.6-745.46"
wire \main_sdram_choose_req_cmd_payload_is_cmd
- attribute \src "ls180.v:738.6-738.47"
+ attribute \src "ls180.v:746.6-746.47"
wire \main_sdram_choose_req_cmd_payload_is_read
- attribute \src "ls180.v:739.6-739.48"
+ attribute \src "ls180.v:747.6-747.48"
wire \main_sdram_choose_req_cmd_payload_is_write
- attribute \src "ls180.v:735.5-735.42"
+ attribute \src "ls180.v:743.5-743.42"
wire \main_sdram_choose_req_cmd_payload_ras
- attribute \src "ls180.v:736.5-736.41"
+ attribute \src "ls180.v:744.5-744.41"
wire \main_sdram_choose_req_cmd_payload_we
- attribute \src "ls180.v:731.5-731.36"
+ attribute \src "ls180.v:739.5-739.36"
wire \main_sdram_choose_req_cmd_ready
- attribute \src "ls180.v:730.6-730.37"
+ attribute \src "ls180.v:738.6-738.37"
wire \main_sdram_choose_req_cmd_valid
- attribute \src "ls180.v:742.11-742.38"
+ attribute \src "ls180.v:750.11-750.38"
wire width 2 \main_sdram_choose_req_grant
- attribute \src "ls180.v:741.12-741.41"
+ attribute \src "ls180.v:749.12-749.41"
wire width 4 \main_sdram_choose_req_request
- attribute \src "ls180.v:740.11-740.39"
+ attribute \src "ls180.v:748.11-748.39"
wire width 4 \main_sdram_choose_req_valids
- attribute \src "ls180.v:729.5-729.41"
+ attribute \src "ls180.v:737.5-737.41"
wire \main_sdram_choose_req_want_activates
- attribute \src "ls180.v:728.6-728.37"
+ attribute \src "ls180.v:736.6-736.37"
wire \main_sdram_choose_req_want_cmds
- attribute \src "ls180.v:726.5-726.37"
+ attribute \src "ls180.v:734.5-734.37"
wire \main_sdram_choose_req_want_reads
- attribute \src "ls180.v:727.5-727.38"
+ attribute \src "ls180.v:735.5-735.38"
wire \main_sdram_choose_req_want_writes
- attribute \src "ls180.v:287.6-287.20"
+ attribute \src "ls180.v:295.6-295.20"
wire \main_sdram_cke
- attribute \src "ls180.v:355.5-355.24"
+ attribute \src "ls180.v:363.5-363.24"
wire \main_sdram_cmd_last
- attribute \src "ls180.v:356.12-356.36"
+ attribute \src "ls180.v:364.12-364.36"
wire width 13 \main_sdram_cmd_payload_a
- attribute \src "ls180.v:357.11-357.36"
+ attribute \src "ls180.v:365.11-365.36"
wire width 2 \main_sdram_cmd_payload_ba
- attribute \src "ls180.v:358.5-358.31"
+ attribute \src "ls180.v:366.5-366.31"
wire \main_sdram_cmd_payload_cas
- attribute \src "ls180.v:361.5-361.35"
+ attribute \src "ls180.v:369.5-369.35"
wire \main_sdram_cmd_payload_is_read
- attribute \src "ls180.v:362.5-362.36"
+ attribute \src "ls180.v:370.5-370.36"
wire \main_sdram_cmd_payload_is_write
- attribute \src "ls180.v:359.5-359.31"
+ attribute \src "ls180.v:367.5-367.31"
wire \main_sdram_cmd_payload_ras
- attribute \src "ls180.v:360.5-360.30"
+ attribute \src "ls180.v:368.5-368.30"
wire \main_sdram_cmd_payload_we
- attribute \src "ls180.v:354.5-354.25"
+ attribute \src "ls180.v:362.5-362.25"
wire \main_sdram_cmd_ready
- attribute \src "ls180.v:353.5-353.25"
+ attribute \src "ls180.v:361.5-361.25"
wire \main_sdram_cmd_valid
- attribute \src "ls180.v:295.6-295.32"
+ attribute \src "ls180.v:303.6-303.32"
wire \main_sdram_command_issue_r
- attribute \src "ls180.v:294.6-294.33"
+ attribute \src "ls180.v:302.6-302.33"
wire \main_sdram_command_issue_re
- attribute \src "ls180.v:297.5-297.31"
+ attribute \src "ls180.v:305.5-305.31"
wire \main_sdram_command_issue_w
- attribute \src "ls180.v:296.6-296.33"
+ attribute \src "ls180.v:304.6-304.33"
wire \main_sdram_command_issue_we
- attribute \src "ls180.v:293.5-293.26"
+ attribute \src "ls180.v:301.5-301.26"
wire \main_sdram_command_re
- attribute \src "ls180.v:292.11-292.37"
+ attribute \src "ls180.v:300.11-300.37"
wire width 6 \main_sdram_command_storage
- attribute \src "ls180.v:346.5-346.28"
+ attribute \src "ls180.v:354.5-354.28"
wire \main_sdram_dfi_p0_act_n
- attribute \src "ls180.v:337.12-337.37"
+ attribute \src "ls180.v:345.12-345.37"
wire width 13 \main_sdram_dfi_p0_address
- attribute \src "ls180.v:338.11-338.33"
+ attribute \src "ls180.v:346.11-346.33"
wire width 2 \main_sdram_dfi_p0_bank
- attribute \src "ls180.v:339.5-339.28"
+ attribute \src "ls180.v:347.5-347.28"
wire \main_sdram_dfi_p0_cas_n
- attribute \src "ls180.v:343.6-343.27"
+ attribute \src "ls180.v:351.6-351.27"
wire \main_sdram_dfi_p0_cke
- attribute \src "ls180.v:340.5-340.27"
+ attribute \src "ls180.v:348.5-348.27"
wire \main_sdram_dfi_p0_cs_n
- attribute \src "ls180.v:344.6-344.27"
+ attribute \src "ls180.v:352.6-352.27"
wire \main_sdram_dfi_p0_odt
- attribute \src "ls180.v:341.5-341.28"
+ attribute \src "ls180.v:349.5-349.28"
wire \main_sdram_dfi_p0_ras_n
- attribute \src "ls180.v:351.13-351.37"
+ attribute \src "ls180.v:359.13-359.37"
wire width 16 \main_sdram_dfi_p0_rddata
- attribute \src "ls180.v:350.5-350.32"
+ attribute \src "ls180.v:358.5-358.32"
wire \main_sdram_dfi_p0_rddata_en
- attribute \src "ls180.v:352.6-352.36"
+ attribute \src "ls180.v:360.6-360.36"
wire \main_sdram_dfi_p0_rddata_valid
- attribute \src "ls180.v:345.6-345.31"
+ attribute \src "ls180.v:353.6-353.31"
wire \main_sdram_dfi_p0_reset_n
- attribute \src "ls180.v:342.5-342.27"
+ attribute \src "ls180.v:350.5-350.27"
wire \main_sdram_dfi_p0_we_n
- attribute \src "ls180.v:347.13-347.37"
+ attribute \src "ls180.v:355.13-355.37"
wire width 16 \main_sdram_dfi_p0_wrdata
- attribute \src "ls180.v:348.5-348.32"
+ attribute \src "ls180.v:356.5-356.32"
wire \main_sdram_dfi_p0_wrdata_en
- attribute \src "ls180.v:349.12-349.41"
+ attribute \src "ls180.v:357.12-357.41"
wire width 2 \main_sdram_dfi_p0_wrdata_mask
- attribute \src "ls180.v:761.5-761.19"
+ attribute \src "ls180.v:769.5-769.19"
wire \main_sdram_en0
- attribute \src "ls180.v:764.5-764.19"
+ attribute \src "ls180.v:772.5-772.19"
wire \main_sdram_en1
- attribute \src "ls180.v:767.6-767.30"
+ attribute \src "ls180.v:775.6-775.30"
wire \main_sdram_go_to_refresh
- attribute \src "ls180.v:309.13-309.44"
+ attribute \src "ls180.v:317.13-317.44"
wire width 22 \main_sdram_interface_bank0_addr
- attribute \src "ls180.v:310.6-310.37"
+ attribute \src "ls180.v:318.6-318.37"
wire \main_sdram_interface_bank0_lock
- attribute \src "ls180.v:312.6-312.44"
+ attribute \src "ls180.v:320.6-320.44"
wire \main_sdram_interface_bank0_rdata_valid
- attribute \src "ls180.v:307.6-307.38"
+ attribute \src "ls180.v:315.6-315.38"
wire \main_sdram_interface_bank0_ready
- attribute \src "ls180.v:306.6-306.38"
+ attribute \src "ls180.v:314.6-314.38"
wire \main_sdram_interface_bank0_valid
- attribute \src "ls180.v:311.6-311.44"
+ attribute \src "ls180.v:319.6-319.44"
wire \main_sdram_interface_bank0_wdata_ready
- attribute \src "ls180.v:308.6-308.35"
+ attribute \src "ls180.v:316.6-316.35"
wire \main_sdram_interface_bank0_we
- attribute \src "ls180.v:316.13-316.44"
+ attribute \src "ls180.v:324.13-324.44"
wire width 22 \main_sdram_interface_bank1_addr
- attribute \src "ls180.v:317.6-317.37"
+ attribute \src "ls180.v:325.6-325.37"
wire \main_sdram_interface_bank1_lock
- attribute \src "ls180.v:319.6-319.44"
+ attribute \src "ls180.v:327.6-327.44"
wire \main_sdram_interface_bank1_rdata_valid
- attribute \src "ls180.v:314.6-314.38"
+ attribute \src "ls180.v:322.6-322.38"
wire \main_sdram_interface_bank1_ready
- attribute \src "ls180.v:313.6-313.38"
+ attribute \src "ls180.v:321.6-321.38"
wire \main_sdram_interface_bank1_valid
- attribute \src "ls180.v:318.6-318.44"
+ attribute \src "ls180.v:326.6-326.44"
wire \main_sdram_interface_bank1_wdata_ready
- attribute \src "ls180.v:315.6-315.35"
+ attribute \src "ls180.v:323.6-323.35"
wire \main_sdram_interface_bank1_we
- attribute \src "ls180.v:323.13-323.44"
+ attribute \src "ls180.v:331.13-331.44"
wire width 22 \main_sdram_interface_bank2_addr
- attribute \src "ls180.v:324.6-324.37"
+ attribute \src "ls180.v:332.6-332.37"
wire \main_sdram_interface_bank2_lock
- attribute \src "ls180.v:326.6-326.44"
+ attribute \src "ls180.v:334.6-334.44"
wire \main_sdram_interface_bank2_rdata_valid
- attribute \src "ls180.v:321.6-321.38"
+ attribute \src "ls180.v:329.6-329.38"
wire \main_sdram_interface_bank2_ready
- attribute \src "ls180.v:320.6-320.38"
+ attribute \src "ls180.v:328.6-328.38"
wire \main_sdram_interface_bank2_valid
- attribute \src "ls180.v:325.6-325.44"
+ attribute \src "ls180.v:333.6-333.44"
wire \main_sdram_interface_bank2_wdata_ready
- attribute \src "ls180.v:322.6-322.35"
+ attribute \src "ls180.v:330.6-330.35"
wire \main_sdram_interface_bank2_we
- attribute \src "ls180.v:330.13-330.44"
+ attribute \src "ls180.v:338.13-338.44"
wire width 22 \main_sdram_interface_bank3_addr
- attribute \src "ls180.v:331.6-331.37"
+ attribute \src "ls180.v:339.6-339.37"
wire \main_sdram_interface_bank3_lock
- attribute \src "ls180.v:333.6-333.44"
+ attribute \src "ls180.v:341.6-341.44"
wire \main_sdram_interface_bank3_rdata_valid
- attribute \src "ls180.v:328.6-328.38"
+ attribute \src "ls180.v:336.6-336.38"
wire \main_sdram_interface_bank3_ready
- attribute \src "ls180.v:327.6-327.38"
+ attribute \src "ls180.v:335.6-335.38"
wire \main_sdram_interface_bank3_valid
- attribute \src "ls180.v:332.6-332.44"
+ attribute \src "ls180.v:340.6-340.44"
wire \main_sdram_interface_bank3_wdata_ready
- attribute \src "ls180.v:329.6-329.35"
+ attribute \src "ls180.v:337.6-337.35"
wire \main_sdram_interface_bank3_we
- attribute \src "ls180.v:336.13-336.39"
+ attribute \src "ls180.v:344.13-344.39"
wire width 16 \main_sdram_interface_rdata
- attribute \src "ls180.v:334.12-334.38"
+ attribute \src "ls180.v:342.12-342.38"
wire width 16 \main_sdram_interface_wdata
- attribute \src "ls180.v:335.11-335.40"
+ attribute \src "ls180.v:343.11-343.40"
wire width 2 \main_sdram_interface_wdata_we
- attribute \src "ls180.v:247.5-247.29"
+ attribute \src "ls180.v:255.5-255.29"
wire \main_sdram_inti_p0_act_n
- attribute \src "ls180.v:238.13-238.39"
+ attribute \src "ls180.v:246.13-246.39"
wire width 13 \main_sdram_inti_p0_address
- attribute \src "ls180.v:239.12-239.35"
+ attribute \src "ls180.v:247.12-247.35"
wire width 2 \main_sdram_inti_p0_bank
- attribute \src "ls180.v:240.5-240.29"
+ attribute \src "ls180.v:248.5-248.29"
wire \main_sdram_inti_p0_cas_n
- attribute \src "ls180.v:244.6-244.28"
+ attribute \src "ls180.v:252.6-252.28"
wire \main_sdram_inti_p0_cke
- attribute \src "ls180.v:241.5-241.28"
+ attribute \src "ls180.v:249.5-249.28"
wire \main_sdram_inti_p0_cs_n
- attribute \src "ls180.v:245.6-245.28"
+ attribute \src "ls180.v:253.6-253.28"
wire \main_sdram_inti_p0_odt
- attribute \src "ls180.v:242.5-242.29"
+ attribute \src "ls180.v:250.5-250.29"
wire \main_sdram_inti_p0_ras_n
- attribute \src "ls180.v:252.12-252.37"
+ attribute \src "ls180.v:260.12-260.37"
wire width 16 \main_sdram_inti_p0_rddata
- attribute \src "ls180.v:251.6-251.34"
+ attribute \src "ls180.v:259.6-259.34"
wire \main_sdram_inti_p0_rddata_en
- attribute \src "ls180.v:253.5-253.36"
+ attribute \src "ls180.v:261.5-261.36"
wire \main_sdram_inti_p0_rddata_valid
- attribute \src "ls180.v:246.6-246.32"
+ attribute \src "ls180.v:254.6-254.32"
wire \main_sdram_inti_p0_reset_n
- attribute \src "ls180.v:243.5-243.28"
+ attribute \src "ls180.v:251.5-251.28"
wire \main_sdram_inti_p0_we_n
- attribute \src "ls180.v:248.13-248.38"
+ attribute \src "ls180.v:256.13-256.38"
wire width 16 \main_sdram_inti_p0_wrdata
- attribute \src "ls180.v:249.6-249.34"
+ attribute \src "ls180.v:257.6-257.34"
wire \main_sdram_inti_p0_wrdata_en
- attribute \src "ls180.v:250.12-250.42"
+ attribute \src "ls180.v:258.12-258.42"
wire width 2 \main_sdram_inti_p0_wrdata_mask
- attribute \src "ls180.v:279.5-279.31"
+ attribute \src "ls180.v:287.5-287.31"
wire \main_sdram_master_p0_act_n
- attribute \src "ls180.v:270.12-270.40"
+ attribute \src "ls180.v:278.12-278.40"
wire width 13 \main_sdram_master_p0_address
- attribute \src "ls180.v:271.11-271.36"
+ attribute \src "ls180.v:279.11-279.36"
wire width 2 \main_sdram_master_p0_bank
- attribute \src "ls180.v:272.5-272.31"
+ attribute \src "ls180.v:280.5-280.31"
wire \main_sdram_master_p0_cas_n
- attribute \src "ls180.v:276.5-276.29"
+ attribute \src "ls180.v:284.5-284.29"
wire \main_sdram_master_p0_cke
- attribute \src "ls180.v:273.5-273.30"
+ attribute \src "ls180.v:281.5-281.30"
wire \main_sdram_master_p0_cs_n
- attribute \src "ls180.v:277.5-277.29"
+ attribute \src "ls180.v:285.5-285.29"
wire \main_sdram_master_p0_odt
- attribute \src "ls180.v:274.5-274.31"
+ attribute \src "ls180.v:282.5-282.31"
wire \main_sdram_master_p0_ras_n
- attribute \src "ls180.v:284.13-284.40"
+ attribute \src "ls180.v:292.13-292.40"
wire width 16 \main_sdram_master_p0_rddata
- attribute \src "ls180.v:283.5-283.35"
+ attribute \src "ls180.v:291.5-291.35"
wire \main_sdram_master_p0_rddata_en
- attribute \src "ls180.v:285.6-285.39"
+ attribute \src "ls180.v:293.6-293.39"
wire \main_sdram_master_p0_rddata_valid
- attribute \src "ls180.v:278.5-278.33"
+ attribute \src "ls180.v:286.5-286.33"
wire \main_sdram_master_p0_reset_n
- attribute \src "ls180.v:275.5-275.30"
+ attribute \src "ls180.v:283.5-283.30"
wire \main_sdram_master_p0_we_n
- attribute \src "ls180.v:280.12-280.39"
+ attribute \src "ls180.v:288.12-288.39"
wire width 16 \main_sdram_master_p0_wrdata
- attribute \src "ls180.v:281.5-281.35"
+ attribute \src "ls180.v:289.5-289.35"
wire \main_sdram_master_p0_wrdata_en
- attribute \src "ls180.v:282.11-282.43"
+ attribute \src "ls180.v:290.11-290.43"
wire width 2 \main_sdram_master_p0_wrdata_mask
- attribute \src "ls180.v:762.6-762.26"
+ attribute \src "ls180.v:770.6-770.26"
wire \main_sdram_max_time0
- attribute \src "ls180.v:765.6-765.26"
+ attribute \src "ls180.v:773.6-773.26"
wire \main_sdram_max_time1
- attribute \src "ls180.v:744.12-744.28"
+ attribute \src "ls180.v:752.12-752.28"
wire width 13 \main_sdram_nop_a
- attribute \src "ls180.v:745.11-745.28"
+ attribute \src "ls180.v:753.11-753.28"
wire width 2 \main_sdram_nop_ba
- attribute \src "ls180.v:288.6-288.20"
+ attribute \src "ls180.v:296.6-296.20"
wire \main_sdram_odt
- attribute \src "ls180.v:371.5-371.31"
+ attribute \src "ls180.v:379.5-379.31"
wire \main_sdram_postponer_count
- attribute \src "ls180.v:369.6-369.32"
+ attribute \src "ls180.v:377.6-377.32"
wire \main_sdram_postponer_req_i
- attribute \src "ls180.v:370.5-370.31"
+ attribute \src "ls180.v:378.5-378.31"
wire \main_sdram_postponer_req_o
- attribute \src "ls180.v:706.6-706.28"
+ attribute \src "ls180.v:714.6-714.28"
wire \main_sdram_ras_allowed
- attribute \src "ls180.v:291.5-291.18"
+ attribute \src "ls180.v:299.5-299.18"
wire \main_sdram_re
- attribute \src "ls180.v:759.6-759.31"
+ attribute \src "ls180.v:767.6-767.31"
wire \main_sdram_read_available
- attribute \src "ls180.v:289.6-289.24"
+ attribute \src "ls180.v:297.6-297.24"
wire \main_sdram_reset_n
- attribute \src "ls180.v:286.6-286.20"
+ attribute \src "ls180.v:294.6-294.20"
wire \main_sdram_sel
- attribute \src "ls180.v:377.5-377.31"
+ attribute \src "ls180.v:385.5-385.31"
wire \main_sdram_sequencer_count
- attribute \src "ls180.v:376.11-376.39"
+ attribute \src "ls180.v:384.11-384.39"
wire width 4 \main_sdram_sequencer_counter
- attribute \src "ls180.v:373.6-373.32"
+ attribute \src "ls180.v:381.6-381.32"
wire \main_sdram_sequencer_done0
- attribute \src "ls180.v:375.5-375.31"
+ attribute \src "ls180.v:383.5-383.31"
wire \main_sdram_sequencer_done1
- attribute \src "ls180.v:372.5-372.32"
+ attribute \src "ls180.v:380.5-380.32"
wire \main_sdram_sequencer_start0
- attribute \src "ls180.v:374.6-374.33"
+ attribute \src "ls180.v:382.6-382.33"
wire \main_sdram_sequencer_start1
- attribute \src "ls180.v:263.6-263.31"
+ attribute \src "ls180.v:271.6-271.31"
wire \main_sdram_slave_p0_act_n
- attribute \src "ls180.v:254.13-254.40"
+ attribute \src "ls180.v:262.13-262.40"
wire width 13 \main_sdram_slave_p0_address
- attribute \src "ls180.v:255.12-255.36"
+ attribute \src "ls180.v:263.12-263.36"
wire width 2 \main_sdram_slave_p0_bank
- attribute \src "ls180.v:256.6-256.31"
+ attribute \src "ls180.v:264.6-264.31"
wire \main_sdram_slave_p0_cas_n
- attribute \src "ls180.v:260.6-260.29"
+ attribute \src "ls180.v:268.6-268.29"
wire \main_sdram_slave_p0_cke
- attribute \src "ls180.v:257.6-257.30"
+ attribute \src "ls180.v:265.6-265.30"
wire \main_sdram_slave_p0_cs_n
- attribute \src "ls180.v:261.6-261.29"
+ attribute \src "ls180.v:269.6-269.29"
wire \main_sdram_slave_p0_odt
- attribute \src "ls180.v:258.6-258.31"
+ attribute \src "ls180.v:266.6-266.31"
wire \main_sdram_slave_p0_ras_n
- attribute \src "ls180.v:268.12-268.38"
+ attribute \src "ls180.v:276.12-276.38"
wire width 16 \main_sdram_slave_p0_rddata
- attribute \src "ls180.v:267.6-267.35"
+ attribute \src "ls180.v:275.6-275.35"
wire \main_sdram_slave_p0_rddata_en
- attribute \src "ls180.v:269.5-269.37"
+ attribute \src "ls180.v:277.5-277.37"
wire \main_sdram_slave_p0_rddata_valid
- attribute \src "ls180.v:262.6-262.33"
+ attribute \src "ls180.v:270.6-270.33"
wire \main_sdram_slave_p0_reset_n
- attribute \src "ls180.v:259.6-259.30"
+ attribute \src "ls180.v:267.6-267.30"
wire \main_sdram_slave_p0_we_n
- attribute \src "ls180.v:264.13-264.39"
+ attribute \src "ls180.v:272.13-272.39"
wire width 16 \main_sdram_slave_p0_wrdata
- attribute \src "ls180.v:265.6-265.35"
+ attribute \src "ls180.v:273.6-273.35"
wire \main_sdram_slave_p0_wrdata_en
- attribute \src "ls180.v:266.12-266.43"
+ attribute \src "ls180.v:274.12-274.43"
wire width 2 \main_sdram_slave_p0_wrdata_mask
- attribute \src "ls180.v:304.12-304.29"
+ attribute \src "ls180.v:312.12-312.29"
wire width 16 \main_sdram_status
- attribute \src "ls180.v:747.5-747.24"
+ attribute \src "ls180.v:755.5-755.24"
wire \main_sdram_steerer0
- attribute \src "ls180.v:748.5-748.24"
+ attribute \src "ls180.v:756.5-756.24"
wire \main_sdram_steerer1
- attribute \src "ls180.v:746.11-746.33"
+ attribute \src "ls180.v:754.11-754.33"
wire width 2 \main_sdram_steerer_sel
- attribute \src "ls180.v:290.11-290.29"
+ attribute \src "ls180.v:298.11-298.29"
wire width 4 \main_sdram_storage
- attribute \src "ls180.v:755.5-755.29"
+ attribute \src "ls180.v:763.5-763.29"
wire \main_sdram_tccdcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:754.32-754.56"
+ attribute \src "ls180.v:762.32-762.56"
wire \main_sdram_tccdcon_ready
- attribute \src "ls180.v:753.6-753.30"
+ attribute \src "ls180.v:761.6-761.30"
wire \main_sdram_tccdcon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:752.32-752.56"
+ attribute \src "ls180.v:760.32-760.56"
wire \main_sdram_tfawcon_ready
- attribute \src "ls180.v:751.6-751.30"
+ attribute \src "ls180.v:759.6-759.30"
wire \main_sdram_tfawcon_valid
- attribute \src "ls180.v:763.11-763.27"
+ attribute \src "ls180.v:771.11-771.27"
wire width 5 \main_sdram_time0
- attribute \src "ls180.v:766.11-766.27"
+ attribute \src "ls180.v:774.11-774.27"
wire width 4 \main_sdram_time1
- attribute \src "ls180.v:366.12-366.35"
+ attribute \src "ls180.v:374.12-374.35"
wire width 10 \main_sdram_timer_count0
- attribute \src "ls180.v:368.11-368.34"
+ attribute \src "ls180.v:376.11-376.34"
wire width 10 \main_sdram_timer_count1
- attribute \src "ls180.v:365.6-365.28"
+ attribute \src "ls180.v:373.6-373.28"
wire \main_sdram_timer_done0
- attribute \src "ls180.v:367.6-367.28"
+ attribute \src "ls180.v:375.6-375.28"
wire \main_sdram_timer_done1
- attribute \src "ls180.v:364.6-364.27"
+ attribute \src "ls180.v:372.6-372.27"
wire \main_sdram_timer_wait
attribute \no_retiming "true"
- attribute \src "ls180.v:750.32-750.56"
+ attribute \src "ls180.v:758.32-758.56"
wire \main_sdram_trrdcon_ready
- attribute \src "ls180.v:749.6-749.30"
+ attribute \src "ls180.v:757.6-757.30"
wire \main_sdram_trrdcon_valid
- attribute \src "ls180.v:758.11-758.35"
+ attribute \src "ls180.v:766.11-766.35"
wire width 3 \main_sdram_twtrcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:757.32-757.56"
+ attribute \src "ls180.v:765.32-765.56"
wire \main_sdram_twtrcon_ready
- attribute \src "ls180.v:756.6-756.30"
+ attribute \src "ls180.v:764.6-764.30"
wire \main_sdram_twtrcon_valid
- attribute \src "ls180.v:363.6-363.30"
+ attribute \src "ls180.v:371.6-371.30"
wire \main_sdram_wants_refresh
- attribute \src "ls180.v:305.6-305.19"
+ attribute \src "ls180.v:313.6-313.19"
wire \main_sdram_we
- attribute \src "ls180.v:303.5-303.25"
+ attribute \src "ls180.v:311.5-311.25"
wire \main_sdram_wrdata_re
- attribute \src "ls180.v:302.12-302.37"
+ attribute \src "ls180.v:310.12-310.37"
wire width 16 \main_sdram_wrdata_storage
- attribute \src "ls180.v:760.6-760.32"
+ attribute \src "ls180.v:768.6-768.32"
wire \main_sdram_write_available
- attribute \src "ls180.v:813.6-813.21"
- wire \main_sink_first
- attribute \src "ls180.v:814.6-814.20"
- wire \main_sink_last
- attribute \src "ls180.v:815.12-815.34"
- wire width 8 \main_sink_payload_data
- attribute \src "ls180.v:812.5-812.20"
- wire \main_sink_ready
- attribute \src "ls180.v:811.6-811.21"
- wire \main_sink_valid
- attribute \src "ls180.v:823.5-823.22"
- wire \main_source_first
- attribute \src "ls180.v:824.5-824.21"
- wire \main_source_last
- attribute \src "ls180.v:825.11-825.35"
- wire width 8 \main_source_payload_data
- attribute \src "ls180.v:822.6-822.23"
- wire \main_source_ready
- attribute \src "ls180.v:821.5-821.22"
- wire \main_source_valid
- attribute \src "ls180.v:968.12-968.40"
+ attribute \src "ls180.v:976.12-976.40"
wire width 16 \main_spi_master_clk_divider0
- attribute \src "ls180.v:990.12-990.40"
+ attribute \src "ls180.v:998.12-998.40"
wire width 16 \main_spi_master_clk_divider1
- attribute \src "ls180.v:985.5-985.31"
+ attribute \src "ls180.v:993.5-993.31"
wire \main_spi_master_clk_enable
- attribute \src "ls180.v:992.6-992.30"
+ attribute \src "ls180.v:1000.6-1000.30"
wire \main_spi_master_clk_fall
- attribute \src "ls180.v:991.6-991.30"
+ attribute \src "ls180.v:999.6-999.30"
wire \main_spi_master_clk_rise
- attribute \src "ls180.v:972.5-972.31"
+ attribute \src "ls180.v:980.5-980.31"
wire \main_spi_master_control_re
- attribute \src "ls180.v:971.12-971.43"
+ attribute \src "ls180.v:979.12-979.43"
wire width 16 \main_spi_master_control_storage
- attribute \src "ls180.v:987.11-987.32"
+ attribute \src "ls180.v:995.11-995.32"
wire width 3 \main_spi_master_count
- attribute \src "ls180.v:1745.11-1745.54"
+ attribute \src "ls180.v:1761.11-1761.54"
wire width 3 \main_spi_master_count_spimaster0_next_value
- attribute \src "ls180.v:1746.5-1746.51"
+ attribute \src "ls180.v:1762.5-1762.51"
wire \main_spi_master_count_spimaster0_next_value_ce
- attribute \src "ls180.v:966.6-966.24"
+ attribute \src "ls180.v:974.6-974.24"
wire \main_spi_master_cs
- attribute \src "ls180.v:986.5-986.30"
+ attribute \src "ls180.v:994.5-994.30"
wire \main_spi_master_cs_enable
- attribute \src "ls180.v:982.5-982.26"
+ attribute \src "ls180.v:990.5-990.26"
wire \main_spi_master_cs_re
- attribute \src "ls180.v:981.5-981.31"
+ attribute \src "ls180.v:989.5-989.31"
wire \main_spi_master_cs_storage
- attribute \src "ls180.v:962.5-962.26"
+ attribute \src "ls180.v:970.5-970.26"
wire \main_spi_master_done0
- attribute \src "ls180.v:973.6-973.27"
+ attribute \src "ls180.v:981.6-981.27"
wire \main_spi_master_done1
- attribute \src "ls180.v:963.5-963.24"
+ attribute \src "ls180.v:971.5-971.24"
wire \main_spi_master_irq
- attribute \src "ls180.v:961.12-961.35"
+ attribute \src "ls180.v:969.12-969.35"
wire width 8 \main_spi_master_length0
- attribute \src "ls180.v:970.12-970.35"
+ attribute \src "ls180.v:978.12-978.35"
wire width 8 \main_spi_master_length1
- attribute \src "ls180.v:967.6-967.30"
+ attribute \src "ls180.v:975.6-975.30"
wire \main_spi_master_loopback
- attribute \src "ls180.v:984.5-984.32"
+ attribute \src "ls180.v:992.5-992.32"
wire \main_spi_master_loopback_re
- attribute \src "ls180.v:983.5-983.37"
+ attribute \src "ls180.v:991.5-991.37"
wire \main_spi_master_loopback_storage
- attribute \src "ls180.v:965.11-965.31"
+ attribute \src "ls180.v:973.11-973.31"
wire width 8 \main_spi_master_miso
- attribute \src "ls180.v:995.11-995.36"
+ attribute \src "ls180.v:1003.11-1003.36"
wire width 8 \main_spi_master_miso_data
- attribute \src "ls180.v:989.5-989.31"
+ attribute \src "ls180.v:997.5-997.31"
wire \main_spi_master_miso_latch
- attribute \src "ls180.v:978.12-978.39"
+ attribute \src "ls180.v:986.12-986.39"
wire width 8 \main_spi_master_miso_status
- attribute \src "ls180.v:979.6-979.29"
+ attribute \src "ls180.v:987.6-987.29"
wire \main_spi_master_miso_we
- attribute \src "ls180.v:964.12-964.32"
+ attribute \src "ls180.v:972.12-972.32"
wire width 8 \main_spi_master_mosi
- attribute \src "ls180.v:993.11-993.36"
+ attribute \src "ls180.v:1001.11-1001.36"
wire width 8 \main_spi_master_mosi_data
- attribute \src "ls180.v:988.5-988.31"
+ attribute \src "ls180.v:996.5-996.31"
wire \main_spi_master_mosi_latch
- attribute \src "ls180.v:977.5-977.28"
+ attribute \src "ls180.v:985.5-985.28"
wire \main_spi_master_mosi_re
- attribute \src "ls180.v:994.11-994.35"
+ attribute \src "ls180.v:1002.11-1002.35"
wire width 3 \main_spi_master_mosi_sel
- attribute \src "ls180.v:976.11-976.39"
+ attribute \src "ls180.v:984.11-984.39"
wire width 8 \main_spi_master_mosi_storage
- attribute \src "ls180.v:980.6-980.25"
+ attribute \src "ls180.v:988.6-988.25"
wire \main_spi_master_sel
- attribute \src "ls180.v:960.6-960.28"
+ attribute \src "ls180.v:968.6-968.28"
wire \main_spi_master_start0
- attribute \src "ls180.v:969.5-969.27"
+ attribute \src "ls180.v:977.5-977.27"
wire \main_spi_master_start1
- attribute \src "ls180.v:974.6-974.35"
+ attribute \src "ls180.v:982.6-982.35"
wire \main_spi_master_status_status
- attribute \src "ls180.v:975.6-975.31"
+ attribute \src "ls180.v:983.6-983.31"
wire \main_spi_master_status_we
- attribute \src "ls180.v:809.12-809.24"
- wire width 32 \main_storage
- attribute \src "ls180.v:819.11-819.27"
- wire width 4 \main_tx_bitcount
- attribute \src "ls180.v:820.5-820.17"
- wire \main_tx_busy
- attribute \src "ls180.v:818.11-818.22"
- wire width 8 \main_tx_reg
- attribute \src "ls180.v:826.5-826.23"
- wire \main_uart_clk_rxen
- attribute \src "ls180.v:816.5-816.23"
- wire \main_uart_clk_txen
- attribute \src "ls180.v:857.12-857.44"
+ attribute \src "ls180.v:865.12-865.44"
wire width 2 \main_uart_eventmanager_pending_r
- attribute \src "ls180.v:856.6-856.39"
+ attribute \src "ls180.v:864.6-864.39"
wire \main_uart_eventmanager_pending_re
- attribute \src "ls180.v:859.11-859.43"
+ attribute \src "ls180.v:867.11-867.43"
wire width 2 \main_uart_eventmanager_pending_w
- attribute \src "ls180.v:858.6-858.39"
+ attribute \src "ls180.v:866.6-866.39"
wire \main_uart_eventmanager_pending_we
- attribute \src "ls180.v:861.5-861.30"
+ attribute \src "ls180.v:869.5-869.30"
wire \main_uart_eventmanager_re
- attribute \src "ls180.v:853.12-853.43"
+ attribute \src "ls180.v:861.12-861.43"
wire width 2 \main_uart_eventmanager_status_r
- attribute \src "ls180.v:852.6-852.38"
+ attribute \src "ls180.v:860.6-860.38"
wire \main_uart_eventmanager_status_re
- attribute \src "ls180.v:855.11-855.42"
+ attribute \src "ls180.v:863.11-863.42"
wire width 2 \main_uart_eventmanager_status_w
- attribute \src "ls180.v:854.6-854.38"
+ attribute \src "ls180.v:862.6-862.38"
wire \main_uart_eventmanager_status_we
- attribute \src "ls180.v:860.11-860.41"
+ attribute \src "ls180.v:868.11-868.41"
wire width 2 \main_uart_eventmanager_storage
- attribute \src "ls180.v:841.6-841.19"
+ attribute \src "ls180.v:849.6-849.19"
wire \main_uart_irq
- attribute \src "ls180.v:950.5-950.20"
+ attribute \src "ls180.v:835.12-835.46"
+ wire width 32 \main_uart_phy_phase_accumulator_rx
+ attribute \src "ls180.v:825.12-825.46"
+ wire width 32 \main_uart_phy_phase_accumulator_tx
+ attribute \src "ls180.v:818.5-818.21"
+ wire \main_uart_phy_re
+ attribute \src "ls180.v:836.6-836.22"
+ wire \main_uart_phy_rx
+ attribute \src "ls180.v:839.11-839.36"
+ wire width 4 \main_uart_phy_rx_bitcount
+ attribute \src "ls180.v:840.5-840.26"
+ wire \main_uart_phy_rx_busy
+ attribute \src "ls180.v:837.5-837.23"
+ wire \main_uart_phy_rx_r
+ attribute \src "ls180.v:838.11-838.31"
+ wire width 8 \main_uart_phy_rx_reg
+ attribute \src "ls180.v:821.6-821.30"
+ wire \main_uart_phy_sink_first
+ attribute \src "ls180.v:822.6-822.29"
+ wire \main_uart_phy_sink_last
+ attribute \src "ls180.v:823.12-823.43"
+ wire width 8 \main_uart_phy_sink_payload_data
+ attribute \src "ls180.v:820.5-820.29"
+ wire \main_uart_phy_sink_ready
+ attribute \src "ls180.v:819.6-819.30"
+ wire \main_uart_phy_sink_valid
+ attribute \src "ls180.v:831.5-831.31"
+ wire \main_uart_phy_source_first
+ attribute \src "ls180.v:832.5-832.30"
+ wire \main_uart_phy_source_last
+ attribute \src "ls180.v:833.11-833.44"
+ wire width 8 \main_uart_phy_source_payload_data
+ attribute \src "ls180.v:830.6-830.32"
+ wire \main_uart_phy_source_ready
+ attribute \src "ls180.v:829.5-829.31"
+ wire \main_uart_phy_source_valid
+ attribute \src "ls180.v:817.12-817.33"
+ wire width 32 \main_uart_phy_storage
+ attribute \src "ls180.v:827.11-827.36"
+ wire width 4 \main_uart_phy_tx_bitcount
+ attribute \src "ls180.v:828.5-828.26"
+ wire \main_uart_phy_tx_busy
+ attribute \src "ls180.v:826.11-826.31"
+ wire width 8 \main_uart_phy_tx_reg
+ attribute \src "ls180.v:834.5-834.32"
+ wire \main_uart_phy_uart_clk_rxen
+ attribute \src "ls180.v:824.5-824.32"
+ wire \main_uart_phy_uart_clk_txen
+ attribute \src "ls180.v:958.5-958.20"
wire \main_uart_reset
- attribute \src "ls180.v:850.5-850.23"
+ attribute \src "ls180.v:858.5-858.23"
wire \main_uart_rx_clear
- attribute \src "ls180.v:934.11-934.36"
+ attribute \src "ls180.v:942.11-942.36"
wire width 4 \main_uart_rx_fifo_consume
- attribute \src "ls180.v:939.6-939.31"
+ attribute \src "ls180.v:947.6-947.31"
wire \main_uart_rx_fifo_do_read
- attribute \src "ls180.v:945.6-945.37"
+ attribute \src "ls180.v:953.6-953.37"
wire \main_uart_rx_fifo_fifo_in_first
- attribute \src "ls180.v:946.6-946.36"
+ attribute \src "ls180.v:954.6-954.36"
wire \main_uart_rx_fifo_fifo_in_last
- attribute \src "ls180.v:944.12-944.50"
+ attribute \src "ls180.v:952.12-952.50"
wire width 8 \main_uart_rx_fifo_fifo_in_payload_data
- attribute \src "ls180.v:948.6-948.38"
+ attribute \src "ls180.v:956.6-956.38"
wire \main_uart_rx_fifo_fifo_out_first
- attribute \src "ls180.v:949.6-949.37"
+ attribute \src "ls180.v:957.6-957.37"
wire \main_uart_rx_fifo_fifo_out_last
- attribute \src "ls180.v:947.12-947.51"
+ attribute \src "ls180.v:955.12-955.51"
wire width 8 \main_uart_rx_fifo_fifo_out_payload_data
- attribute \src "ls180.v:931.11-931.35"
+ attribute \src "ls180.v:939.11-939.35"
wire width 5 \main_uart_rx_fifo_level0
- attribute \src "ls180.v:943.12-943.36"
+ attribute \src "ls180.v:951.12-951.36"
wire width 5 \main_uart_rx_fifo_level1
- attribute \src "ls180.v:933.11-933.36"
+ attribute \src "ls180.v:941.11-941.36"
wire width 4 \main_uart_rx_fifo_produce
- attribute \src "ls180.v:940.12-940.40"
+ attribute \src "ls180.v:948.12-948.40"
wire width 4 \main_uart_rx_fifo_rdport_adr
- attribute \src "ls180.v:941.12-941.42"
+ attribute \src "ls180.v:949.12-949.42"
wire width 10 \main_uart_rx_fifo_rdport_dat_r
- attribute \src "ls180.v:942.6-942.33"
+ attribute \src "ls180.v:950.6-950.33"
wire \main_uart_rx_fifo_rdport_re
- attribute \src "ls180.v:923.6-923.26"
+ attribute \src "ls180.v:931.6-931.26"
wire \main_uart_rx_fifo_re
- attribute \src "ls180.v:924.5-924.31"
+ attribute \src "ls180.v:932.5-932.31"
wire \main_uart_rx_fifo_readable
- attribute \src "ls180.v:932.5-932.30"
+ attribute \src "ls180.v:940.5-940.30"
wire \main_uart_rx_fifo_replace
- attribute \src "ls180.v:915.6-915.34"
+ attribute \src "ls180.v:923.6-923.34"
wire \main_uart_rx_fifo_sink_first
- attribute \src "ls180.v:916.6-916.33"
+ attribute \src "ls180.v:924.6-924.33"
wire \main_uart_rx_fifo_sink_last
- attribute \src "ls180.v:917.12-917.47"
+ attribute \src "ls180.v:925.12-925.47"
wire width 8 \main_uart_rx_fifo_sink_payload_data
- attribute \src "ls180.v:914.6-914.34"
+ attribute \src "ls180.v:922.6-922.34"
wire \main_uart_rx_fifo_sink_ready
- attribute \src "ls180.v:913.6-913.34"
+ attribute \src "ls180.v:921.6-921.34"
wire \main_uart_rx_fifo_sink_valid
- attribute \src "ls180.v:920.6-920.36"
+ attribute \src "ls180.v:928.6-928.36"
wire \main_uart_rx_fifo_source_first
- attribute \src "ls180.v:921.6-921.35"
+ attribute \src "ls180.v:929.6-929.35"
wire \main_uart_rx_fifo_source_last
- attribute \src "ls180.v:922.12-922.49"
+ attribute \src "ls180.v:930.12-930.49"
wire width 8 \main_uart_rx_fifo_source_payload_data
- attribute \src "ls180.v:919.6-919.36"
+ attribute \src "ls180.v:927.6-927.36"
wire \main_uart_rx_fifo_source_ready
- attribute \src "ls180.v:918.6-918.36"
+ attribute \src "ls180.v:926.6-926.36"
wire \main_uart_rx_fifo_source_valid
- attribute \src "ls180.v:929.12-929.42"
+ attribute \src "ls180.v:937.12-937.42"
wire width 10 \main_uart_rx_fifo_syncfifo_din
- attribute \src "ls180.v:930.12-930.43"
+ attribute \src "ls180.v:938.12-938.43"
wire width 10 \main_uart_rx_fifo_syncfifo_dout
- attribute \src "ls180.v:927.6-927.35"
+ attribute \src "ls180.v:935.6-935.35"
wire \main_uart_rx_fifo_syncfifo_re
- attribute \src "ls180.v:928.6-928.41"
+ attribute \src "ls180.v:936.6-936.41"
wire \main_uart_rx_fifo_syncfifo_readable
- attribute \src "ls180.v:925.6-925.35"
+ attribute \src "ls180.v:933.6-933.35"
wire \main_uart_rx_fifo_syncfifo_we
- attribute \src "ls180.v:926.6-926.41"
+ attribute \src "ls180.v:934.6-934.41"
wire \main_uart_rx_fifo_syncfifo_writable
- attribute \src "ls180.v:935.11-935.39"
+ attribute \src "ls180.v:943.11-943.39"
wire width 4 \main_uart_rx_fifo_wrport_adr
- attribute \src "ls180.v:936.12-936.42"
+ attribute \src "ls180.v:944.12-944.42"
wire width 10 \main_uart_rx_fifo_wrport_dat_r
- attribute \src "ls180.v:938.12-938.42"
+ attribute \src "ls180.v:946.12-946.42"
wire width 10 \main_uart_rx_fifo_wrport_dat_w
- attribute \src "ls180.v:937.6-937.33"
+ attribute \src "ls180.v:945.6-945.33"
wire \main_uart_rx_fifo_wrport_we
- attribute \src "ls180.v:851.5-851.29"
+ attribute \src "ls180.v:859.5-859.29"
wire \main_uart_rx_old_trigger
- attribute \src "ls180.v:848.5-848.25"
+ attribute \src "ls180.v:856.5-856.25"
wire \main_uart_rx_pending
- attribute \src "ls180.v:847.6-847.25"
+ attribute \src "ls180.v:855.6-855.25"
wire \main_uart_rx_status
- attribute \src "ls180.v:849.6-849.26"
+ attribute \src "ls180.v:857.6-857.26"
wire \main_uart_rx_trigger
- attribute \src "ls180.v:839.6-839.30"
+ attribute \src "ls180.v:847.6-847.30"
wire \main_uart_rxempty_status
- attribute \src "ls180.v:840.6-840.26"
+ attribute \src "ls180.v:848.6-848.26"
wire \main_uart_rxempty_we
- attribute \src "ls180.v:864.6-864.29"
+ attribute \src "ls180.v:872.6-872.29"
wire \main_uart_rxfull_status
- attribute \src "ls180.v:865.6-865.25"
+ attribute \src "ls180.v:873.6-873.25"
wire \main_uart_rxfull_we
- attribute \src "ls180.v:834.12-834.28"
+ attribute \src "ls180.v:842.12-842.28"
wire width 8 \main_uart_rxtx_r
- attribute \src "ls180.v:833.6-833.23"
+ attribute \src "ls180.v:841.6-841.23"
wire \main_uart_rxtx_re
- attribute \src "ls180.v:836.12-836.28"
+ attribute \src "ls180.v:844.12-844.28"
wire width 8 \main_uart_rxtx_w
- attribute \src "ls180.v:835.6-835.23"
+ attribute \src "ls180.v:843.6-843.23"
wire \main_uart_rxtx_we
- attribute \src "ls180.v:845.5-845.23"
+ attribute \src "ls180.v:853.5-853.23"
wire \main_uart_tx_clear
- attribute \src "ls180.v:897.11-897.36"
+ attribute \src "ls180.v:905.11-905.36"
wire width 4 \main_uart_tx_fifo_consume
- attribute \src "ls180.v:902.6-902.31"
+ attribute \src "ls180.v:910.6-910.31"
wire \main_uart_tx_fifo_do_read
- attribute \src "ls180.v:908.6-908.37"
+ attribute \src "ls180.v:916.6-916.37"
wire \main_uart_tx_fifo_fifo_in_first
- attribute \src "ls180.v:909.6-909.36"
+ attribute \src "ls180.v:917.6-917.36"
wire \main_uart_tx_fifo_fifo_in_last
- attribute \src "ls180.v:907.12-907.50"
+ attribute \src "ls180.v:915.12-915.50"
wire width 8 \main_uart_tx_fifo_fifo_in_payload_data
- attribute \src "ls180.v:911.6-911.38"
+ attribute \src "ls180.v:919.6-919.38"
wire \main_uart_tx_fifo_fifo_out_first
- attribute \src "ls180.v:912.6-912.37"
+ attribute \src "ls180.v:920.6-920.37"
wire \main_uart_tx_fifo_fifo_out_last
- attribute \src "ls180.v:910.12-910.51"
+ attribute \src "ls180.v:918.12-918.51"
wire width 8 \main_uart_tx_fifo_fifo_out_payload_data
- attribute \src "ls180.v:894.11-894.35"
+ attribute \src "ls180.v:902.11-902.35"
wire width 5 \main_uart_tx_fifo_level0
- attribute \src "ls180.v:906.12-906.36"
+ attribute \src "ls180.v:914.12-914.36"
wire width 5 \main_uart_tx_fifo_level1
- attribute \src "ls180.v:896.11-896.36"
+ attribute \src "ls180.v:904.11-904.36"
wire width 4 \main_uart_tx_fifo_produce
- attribute \src "ls180.v:903.12-903.40"
+ attribute \src "ls180.v:911.12-911.40"
wire width 4 \main_uart_tx_fifo_rdport_adr
- attribute \src "ls180.v:904.12-904.42"
+ attribute \src "ls180.v:912.12-912.42"
wire width 10 \main_uart_tx_fifo_rdport_dat_r
- attribute \src "ls180.v:905.6-905.33"
+ attribute \src "ls180.v:913.6-913.33"
wire \main_uart_tx_fifo_rdport_re
- attribute \src "ls180.v:886.6-886.26"
+ attribute \src "ls180.v:894.6-894.26"
wire \main_uart_tx_fifo_re
- attribute \src "ls180.v:887.5-887.31"
+ attribute \src "ls180.v:895.5-895.31"
wire \main_uart_tx_fifo_readable
- attribute \src "ls180.v:895.5-895.30"
+ attribute \src "ls180.v:903.5-903.30"
wire \main_uart_tx_fifo_replace
- attribute \src "ls180.v:878.5-878.33"
+ attribute \src "ls180.v:886.5-886.33"
wire \main_uart_tx_fifo_sink_first
- attribute \src "ls180.v:879.5-879.32"
+ attribute \src "ls180.v:887.5-887.32"
wire \main_uart_tx_fifo_sink_last
- attribute \src "ls180.v:880.12-880.47"
+ attribute \src "ls180.v:888.12-888.47"
wire width 8 \main_uart_tx_fifo_sink_payload_data
- attribute \src "ls180.v:877.6-877.34"
+ attribute \src "ls180.v:885.6-885.34"
wire \main_uart_tx_fifo_sink_ready
- attribute \src "ls180.v:876.6-876.34"
+ attribute \src "ls180.v:884.6-884.34"
wire \main_uart_tx_fifo_sink_valid
- attribute \src "ls180.v:883.6-883.36"
+ attribute \src "ls180.v:891.6-891.36"
wire \main_uart_tx_fifo_source_first
- attribute \src "ls180.v:884.6-884.35"
+ attribute \src "ls180.v:892.6-892.35"
wire \main_uart_tx_fifo_source_last
- attribute \src "ls180.v:885.12-885.49"
+ attribute \src "ls180.v:893.12-893.49"
wire width 8 \main_uart_tx_fifo_source_payload_data
- attribute \src "ls180.v:882.6-882.36"
+ attribute \src "ls180.v:890.6-890.36"
wire \main_uart_tx_fifo_source_ready
- attribute \src "ls180.v:881.6-881.36"
+ attribute \src "ls180.v:889.6-889.36"
wire \main_uart_tx_fifo_source_valid
- attribute \src "ls180.v:892.12-892.42"
+ attribute \src "ls180.v:900.12-900.42"
wire width 10 \main_uart_tx_fifo_syncfifo_din
- attribute \src "ls180.v:893.12-893.43"
+ attribute \src "ls180.v:901.12-901.43"
wire width 10 \main_uart_tx_fifo_syncfifo_dout
- attribute \src "ls180.v:890.6-890.35"
+ attribute \src "ls180.v:898.6-898.35"
wire \main_uart_tx_fifo_syncfifo_re
- attribute \src "ls180.v:891.6-891.41"
+ attribute \src "ls180.v:899.6-899.41"
wire \main_uart_tx_fifo_syncfifo_readable
- attribute \src "ls180.v:888.6-888.35"
+ attribute \src "ls180.v:896.6-896.35"
wire \main_uart_tx_fifo_syncfifo_we
- attribute \src "ls180.v:889.6-889.41"
+ attribute \src "ls180.v:897.6-897.41"
wire \main_uart_tx_fifo_syncfifo_writable
- attribute \src "ls180.v:898.11-898.39"
+ attribute \src "ls180.v:906.11-906.39"
wire width 4 \main_uart_tx_fifo_wrport_adr
- attribute \src "ls180.v:899.12-899.42"
+ attribute \src "ls180.v:907.12-907.42"
wire width 10 \main_uart_tx_fifo_wrport_dat_r
- attribute \src "ls180.v:901.12-901.42"
+ attribute \src "ls180.v:909.12-909.42"
wire width 10 \main_uart_tx_fifo_wrport_dat_w
- attribute \src "ls180.v:900.6-900.33"
+ attribute \src "ls180.v:908.6-908.33"
wire \main_uart_tx_fifo_wrport_we
- attribute \src "ls180.v:846.5-846.29"
+ attribute \src "ls180.v:854.5-854.29"
wire \main_uart_tx_old_trigger
- attribute \src "ls180.v:843.5-843.25"
+ attribute \src "ls180.v:851.5-851.25"
wire \main_uart_tx_pending
- attribute \src "ls180.v:842.6-842.25"
+ attribute \src "ls180.v:850.6-850.25"
wire \main_uart_tx_status
- attribute \src "ls180.v:844.6-844.26"
+ attribute \src "ls180.v:852.6-852.26"
wire \main_uart_tx_trigger
- attribute \src "ls180.v:862.6-862.30"
+ attribute \src "ls180.v:870.6-870.30"
wire \main_uart_txempty_status
- attribute \src "ls180.v:863.6-863.26"
+ attribute \src "ls180.v:871.6-871.26"
wire \main_uart_txempty_we
- attribute \src "ls180.v:837.6-837.29"
+ attribute \src "ls180.v:845.6-845.29"
wire \main_uart_txfull_status
- attribute \src "ls180.v:838.6-838.25"
+ attribute \src "ls180.v:846.6-846.25"
wire \main_uart_txfull_we
- attribute \src "ls180.v:868.6-868.31"
+ attribute \src "ls180.v:876.6-876.31"
wire \main_uart_uart_sink_first
- attribute \src "ls180.v:869.6-869.30"
+ attribute \src "ls180.v:877.6-877.30"
wire \main_uart_uart_sink_last
- attribute \src "ls180.v:870.12-870.44"
+ attribute \src "ls180.v:878.12-878.44"
wire width 8 \main_uart_uart_sink_payload_data
- attribute \src "ls180.v:867.6-867.31"
+ attribute \src "ls180.v:875.6-875.31"
wire \main_uart_uart_sink_ready
- attribute \src "ls180.v:866.6-866.31"
+ attribute \src "ls180.v:874.6-874.31"
wire \main_uart_uart_sink_valid
- attribute \src "ls180.v:873.6-873.33"
+ attribute \src "ls180.v:881.6-881.33"
wire \main_uart_uart_source_first
- attribute \src "ls180.v:874.6-874.32"
+ attribute \src "ls180.v:882.6-882.32"
wire \main_uart_uart_source_last
- attribute \src "ls180.v:875.12-875.46"
+ attribute \src "ls180.v:883.12-883.46"
wire width 8 \main_uart_uart_source_payload_data
- attribute \src "ls180.v:872.6-872.33"
+ attribute \src "ls180.v:880.6-880.33"
wire \main_uart_uart_source_ready
- attribute \src "ls180.v:871.6-871.33"
+ attribute \src "ls180.v:879.6-879.33"
wire \main_uart_uart_source_valid
- attribute \src "ls180.v:787.5-787.22"
+ attribute \src "ls180.v:795.5-795.22"
wire \main_wb_sdram_ack
- attribute \src "ls180.v:781.13-781.30"
+ attribute \src "ls180.v:789.13-789.30"
wire width 30 \main_wb_sdram_adr
- attribute \src "ls180.v:790.12-790.29"
+ attribute \src "ls180.v:798.12-798.29"
wire width 2 \main_wb_sdram_bte
- attribute \src "ls180.v:789.12-789.29"
+ attribute \src "ls180.v:797.12-797.29"
wire width 3 \main_wb_sdram_cti
- attribute \src "ls180.v:785.6-785.23"
+ attribute \src "ls180.v:793.6-793.23"
wire \main_wb_sdram_cyc
- attribute \src "ls180.v:783.13-783.32"
+ attribute \src "ls180.v:791.13-791.32"
wire width 32 \main_wb_sdram_dat_r
- attribute \src "ls180.v:782.13-782.32"
+ attribute \src "ls180.v:790.13-790.32"
wire width 32 \main_wb_sdram_dat_w
- attribute \src "ls180.v:791.5-791.22"
+ attribute \src "ls180.v:799.5-799.22"
wire \main_wb_sdram_err
- attribute \src "ls180.v:784.12-784.29"
+ attribute \src "ls180.v:792.12-792.29"
wire width 4 \main_wb_sdram_sel
- attribute \src "ls180.v:786.6-786.23"
+ attribute \src "ls180.v:794.6-794.23"
wire \main_wb_sdram_stb
- attribute \src "ls180.v:788.6-788.22"
+ attribute \src "ls180.v:796.6-796.22"
wire \main_wb_sdram_we
- attribute \src "ls180.v:805.5-805.24"
+ attribute \src "ls180.v:813.5-813.24"
wire \main_wdata_consumed
- attribute \src "ls180.v:9976.11-9976.17"
+ attribute \src "ls180.v:10039.11-10039.17"
wire width 7 \memadr
- attribute \src "ls180.v:9996.12-9996.18"
+ attribute \src "ls180.v:10059.12-10059.18"
wire width 25 \memdat
- attribute \src "ls180.v:10010.12-10010.20"
+ attribute \src "ls180.v:10073.12-10073.20"
wire width 25 \memdat_1
- attribute \src "ls180.v:10024.12-10024.20"
+ attribute \src "ls180.v:10087.12-10087.20"
wire width 25 \memdat_2
- attribute \src "ls180.v:10038.12-10038.20"
+ attribute \src "ls180.v:10101.12-10101.20"
wire width 25 \memdat_3
- attribute \src "ls180.v:10052.11-10052.19"
+ attribute \src "ls180.v:10115.11-10115.19"
wire width 10 \memdat_4
- attribute \src "ls180.v:10053.11-10053.19"
+ attribute \src "ls180.v:10116.11-10116.19"
wire width 10 \memdat_5
- attribute \src "ls180.v:10069.11-10069.19"
+ attribute \src "ls180.v:10132.11-10132.19"
wire width 10 \memdat_6
- attribute \src "ls180.v:10070.11-10070.19"
+ attribute \src "ls180.v:10133.11-10133.19"
wire width 10 \memdat_7
- attribute \src "ls180.v:10086.11-10086.19"
+ attribute \src "ls180.v:10149.11-10149.19"
wire width 10 \memdat_8
- attribute \src "ls180.v:10100.11-10100.19"
+ attribute \src "ls180.v:10163.11-10163.19"
wire width 10 \memdat_9
- attribute \src "ls180.v:33.20-33.22"
- wire width 42 input 29 \nc
- attribute \src "ls180.v:219.6-219.13"
+ attribute \src "ls180.v:35.20-35.22"
+ wire width 36 input 31 \nc
+ attribute \src "ls180.v:227.6-227.13"
wire \por_clk
- attribute \src "ls180.v:34.13-34.17"
- wire output 30 \pwm0
- attribute \src "ls180.v:35.13-35.17"
- wire output 31 \pwm1
- attribute \src "ls180.v:36.13-36.23"
- wire output 32 \sdcard_clk
- attribute \src "ls180.v:37.13-37.25"
- wire input 33 \sdcard_cmd_i
- attribute \src "ls180.v:38.13-38.25"
- wire output 34 \sdcard_cmd_o
- attribute \src "ls180.v:39.13-39.26"
- wire output 35 \sdcard_cmd_oe
- attribute \src "ls180.v:40.19-40.32"
- wire width 4 input 36 \sdcard_data_i
- attribute \src "ls180.v:41.19-41.32"
- wire width 4 output 37 \sdcard_data_o
- attribute \src "ls180.v:42.13-42.27"
- wire output 38 \sdcard_data_oe
- attribute \src "ls180.v:7.20-7.27"
- wire width 13 output 3 \sdram_a
- attribute \src "ls180.v:16.19-16.27"
- wire width 2 output 12 \sdram_ba
- attribute \src "ls180.v:13.13-13.24"
- wire output 9 \sdram_cas_n
- attribute \src "ls180.v:15.13-15.22"
- wire output 11 \sdram_cke
- attribute \src "ls180.v:18.13-18.24"
- wire output 14 \sdram_clock
- attribute \src "ls180.v:14.13-14.23"
- wire output 10 \sdram_cs_n
- attribute \src "ls180.v:17.19-17.27"
- wire width 2 output 13 \sdram_dm
- attribute \src "ls180.v:8.20-8.30"
- wire width 16 input 4 \sdram_dq_i
- attribute \src "ls180.v:9.20-9.30"
- wire width 16 output 5 \sdram_dq_o
- attribute \src "ls180.v:10.13-10.24"
- wire output 6 \sdram_dq_oe
+ attribute \src "ls180.v:36.13-36.17"
+ wire output 32 \pwm0
+ attribute \src "ls180.v:37.13-37.17"
+ wire output 33 \pwm1
+ attribute \src "ls180.v:42.13-42.23"
+ wire output 38 \sdcard_clk
+ attribute \src "ls180.v:43.13-43.25"
+ wire input 39 \sdcard_cmd_i
+ attribute \src "ls180.v:44.13-44.25"
+ wire output 40 \sdcard_cmd_o
+ attribute \src "ls180.v:45.13-45.26"
+ wire output 41 \sdcard_cmd_oe
+ attribute \src "ls180.v:46.19-46.32"
+ wire width 4 input 42 \sdcard_data_i
+ attribute \src "ls180.v:47.19-47.32"
+ wire width 4 output 43 \sdcard_data_o
+ attribute \src "ls180.v:48.13-48.27"
+ wire output 44 \sdcard_data_oe
+ attribute \src "ls180.v:9.20-9.27"
+ wire width 13 output 5 \sdram_a
+ attribute \src "ls180.v:18.19-18.27"
+ wire width 2 output 14 \sdram_ba
+ attribute \src "ls180.v:15.13-15.24"
+ wire output 11 \sdram_cas_n
+ attribute \src "ls180.v:17.13-17.22"
+ wire output 13 \sdram_cke
+ attribute \src "ls180.v:20.13-20.24"
+ wire output 16 \sdram_clock
+ attribute \src "ls180.v:16.13-16.23"
+ wire output 12 \sdram_cs_n
+ attribute \src "ls180.v:19.19-19.27"
+ wire width 2 output 15 \sdram_dm
+ attribute \src "ls180.v:10.20-10.30"
+ wire width 16 input 6 \sdram_dq_i
+ attribute \src "ls180.v:11.20-11.30"
+ wire width 16 output 7 \sdram_dq_o
attribute \src "ls180.v:12.13-12.24"
- wire output 8 \sdram_ras_n
- attribute \src "ls180.v:11.13-11.23"
- wire output 7 \sdram_we_n
- attribute \src "ls180.v:2594.6-2594.15"
+ wire output 8 \sdram_dq_oe
+ attribute \src "ls180.v:14.13-14.24"
+ wire output 10 \sdram_ras_n
+ attribute \src "ls180.v:13.13-13.23"
+ wire output 9 \sdram_we_n
+ attribute \src "ls180.v:2623.6-2623.15"
wire \sdrio_clk
- attribute \src "ls180.v:2595.6-2595.17"
+ attribute \src "ls180.v:2624.6-2624.17"
wire \sdrio_clk_1
- attribute \src "ls180.v:2604.6-2604.18"
+ attribute \src "ls180.v:2633.6-2633.18"
wire \sdrio_clk_10
- attribute \src "ls180.v:2605.6-2605.18"
+ attribute \src "ls180.v:2634.6-2634.18"
wire \sdrio_clk_11
- attribute \src "ls180.v:2606.6-2606.18"
+ attribute \src "ls180.v:2635.6-2635.18"
wire \sdrio_clk_12
- attribute \src "ls180.v:2607.6-2607.18"
+ attribute \src "ls180.v:2636.6-2636.18"
wire \sdrio_clk_13
- attribute \src "ls180.v:2608.6-2608.18"
+ attribute \src "ls180.v:2637.6-2637.18"
wire \sdrio_clk_14
- attribute \src "ls180.v:2609.6-2609.18"
+ attribute \src "ls180.v:2638.6-2638.18"
wire \sdrio_clk_15
- attribute \src "ls180.v:2610.6-2610.18"
+ attribute \src "ls180.v:2639.6-2639.18"
wire \sdrio_clk_16
- attribute \src "ls180.v:2611.6-2611.18"
+ attribute \src "ls180.v:2640.6-2640.18"
wire \sdrio_clk_17
- attribute \src "ls180.v:2612.6-2612.18"
+ attribute \src "ls180.v:2641.6-2641.18"
wire \sdrio_clk_18
- attribute \src "ls180.v:2613.6-2613.18"
+ attribute \src "ls180.v:2642.6-2642.18"
wire \sdrio_clk_19
- attribute \src "ls180.v:2596.6-2596.17"
+ attribute \src "ls180.v:2625.6-2625.17"
wire \sdrio_clk_2
- attribute \src "ls180.v:2614.6-2614.18"
+ attribute \src "ls180.v:2643.6-2643.18"
wire \sdrio_clk_20
- attribute \src "ls180.v:2615.6-2615.18"
+ attribute \src "ls180.v:2644.6-2644.18"
wire \sdrio_clk_21
- attribute \src "ls180.v:2616.6-2616.18"
+ attribute \src "ls180.v:2645.6-2645.18"
wire \sdrio_clk_22
- attribute \src "ls180.v:2617.6-2617.18"
+ attribute \src "ls180.v:2646.6-2646.18"
wire \sdrio_clk_23
- attribute \src "ls180.v:2618.6-2618.18"
+ attribute \src "ls180.v:2647.6-2647.18"
wire \sdrio_clk_24
- attribute \src "ls180.v:2619.6-2619.18"
+ attribute \src "ls180.v:2648.6-2648.18"
wire \sdrio_clk_25
- attribute \src "ls180.v:2620.6-2620.18"
+ attribute \src "ls180.v:2649.6-2649.18"
wire \sdrio_clk_26
- attribute \src "ls180.v:2621.6-2621.18"
+ attribute \src "ls180.v:2650.6-2650.18"
wire \sdrio_clk_27
- attribute \src "ls180.v:2622.6-2622.18"
+ attribute \src "ls180.v:2651.6-2651.18"
wire \sdrio_clk_28
- attribute \src "ls180.v:2623.6-2623.18"
+ attribute \src "ls180.v:2652.6-2652.18"
wire \sdrio_clk_29
- attribute \src "ls180.v:2597.6-2597.17"
+ attribute \src "ls180.v:2626.6-2626.17"
wire \sdrio_clk_3
- attribute \src "ls180.v:2624.6-2624.18"
+ attribute \src "ls180.v:2653.6-2653.18"
wire \sdrio_clk_30
- attribute \src "ls180.v:2625.6-2625.18"
+ attribute \src "ls180.v:2654.6-2654.18"
wire \sdrio_clk_31
- attribute \src "ls180.v:2626.6-2626.18"
+ attribute \src "ls180.v:2655.6-2655.18"
wire \sdrio_clk_32
- attribute \src "ls180.v:2627.6-2627.18"
+ attribute \src "ls180.v:2656.6-2656.18"
wire \sdrio_clk_33
- attribute \src "ls180.v:2628.6-2628.18"
+ attribute \src "ls180.v:2657.6-2657.18"
wire \sdrio_clk_34
- attribute \src "ls180.v:2629.6-2629.18"
+ attribute \src "ls180.v:2658.6-2658.18"
wire \sdrio_clk_35
- attribute \src "ls180.v:2630.6-2630.18"
+ attribute \src "ls180.v:2659.6-2659.18"
wire \sdrio_clk_36
- attribute \src "ls180.v:2631.6-2631.18"
+ attribute \src "ls180.v:2660.6-2660.18"
wire \sdrio_clk_37
- attribute \src "ls180.v:2632.6-2632.18"
+ attribute \src "ls180.v:2661.6-2661.18"
wire \sdrio_clk_38
- attribute \src "ls180.v:2633.6-2633.18"
+ attribute \src "ls180.v:2662.6-2662.18"
wire \sdrio_clk_39
- attribute \src "ls180.v:2598.6-2598.17"
+ attribute \src "ls180.v:2627.6-2627.17"
wire \sdrio_clk_4
- attribute \src "ls180.v:2634.6-2634.18"
+ attribute \src "ls180.v:2663.6-2663.18"
wire \sdrio_clk_40
- attribute \src "ls180.v:2635.6-2635.18"
+ attribute \src "ls180.v:2664.6-2664.18"
wire \sdrio_clk_41
- attribute \src "ls180.v:2636.6-2636.18"
+ attribute \src "ls180.v:2665.6-2665.18"
wire \sdrio_clk_42
- attribute \src "ls180.v:2637.6-2637.18"
+ attribute \src "ls180.v:2666.6-2666.18"
wire \sdrio_clk_43
- attribute \src "ls180.v:2638.6-2638.18"
+ attribute \src "ls180.v:2667.6-2667.18"
wire \sdrio_clk_44
- attribute \src "ls180.v:2639.6-2639.18"
+ attribute \src "ls180.v:2668.6-2668.18"
wire \sdrio_clk_45
- attribute \src "ls180.v:2640.6-2640.18"
+ attribute \src "ls180.v:2669.6-2669.18"
wire \sdrio_clk_46
- attribute \src "ls180.v:2641.6-2641.18"
+ attribute \src "ls180.v:2670.6-2670.18"
wire \sdrio_clk_47
- attribute \src "ls180.v:2642.6-2642.18"
+ attribute \src "ls180.v:2671.6-2671.18"
wire \sdrio_clk_48
- attribute \src "ls180.v:2643.6-2643.18"
+ attribute \src "ls180.v:2672.6-2672.18"
wire \sdrio_clk_49
- attribute \src "ls180.v:2599.6-2599.17"
+ attribute \src "ls180.v:2628.6-2628.17"
wire \sdrio_clk_5
- attribute \src "ls180.v:2644.6-2644.18"
+ attribute \src "ls180.v:2673.6-2673.18"
wire \sdrio_clk_50
- attribute \src "ls180.v:2645.6-2645.18"
+ attribute \src "ls180.v:2674.6-2674.18"
wire \sdrio_clk_51
- attribute \src "ls180.v:2646.6-2646.18"
+ attribute \src "ls180.v:2675.6-2675.18"
wire \sdrio_clk_52
- attribute \src "ls180.v:2647.6-2647.18"
+ attribute \src "ls180.v:2676.6-2676.18"
wire \sdrio_clk_53
- attribute \src "ls180.v:2648.6-2648.18"
+ attribute \src "ls180.v:2677.6-2677.18"
wire \sdrio_clk_54
- attribute \src "ls180.v:2649.6-2649.18"
+ attribute \src "ls180.v:2678.6-2678.18"
wire \sdrio_clk_55
- attribute \src "ls180.v:2684.6-2684.18"
+ attribute \src "ls180.v:2713.6-2713.18"
wire \sdrio_clk_56
- attribute \src "ls180.v:2685.6-2685.18"
+ attribute \src "ls180.v:2714.6-2714.18"
wire \sdrio_clk_57
- attribute \src "ls180.v:2686.6-2686.18"
+ attribute \src "ls180.v:2715.6-2715.18"
wire \sdrio_clk_58
- attribute \src "ls180.v:2687.6-2687.18"
+ attribute \src "ls180.v:2716.6-2716.18"
wire \sdrio_clk_59
- attribute \src "ls180.v:2600.6-2600.17"
+ attribute \src "ls180.v:2629.6-2629.17"
wire \sdrio_clk_6
- attribute \src "ls180.v:2688.6-2688.18"
+ attribute \src "ls180.v:2717.6-2717.18"
wire \sdrio_clk_60
- attribute \src "ls180.v:2689.6-2689.18"
+ attribute \src "ls180.v:2718.6-2718.18"
wire \sdrio_clk_61
- attribute \src "ls180.v:2690.6-2690.18"
+ attribute \src "ls180.v:2719.6-2719.18"
wire \sdrio_clk_62
- attribute \src "ls180.v:2691.6-2691.18"
+ attribute \src "ls180.v:2720.6-2720.18"
wire \sdrio_clk_63
- attribute \src "ls180.v:2692.6-2692.18"
+ attribute \src "ls180.v:2721.6-2721.18"
wire \sdrio_clk_64
- attribute \src "ls180.v:2693.6-2693.18"
+ attribute \src "ls180.v:2722.6-2722.18"
wire \sdrio_clk_65
- attribute \src "ls180.v:2694.6-2694.18"
+ attribute \src "ls180.v:2723.6-2723.18"
wire \sdrio_clk_66
- attribute \src "ls180.v:2695.6-2695.18"
+ attribute \src "ls180.v:2724.6-2724.18"
wire \sdrio_clk_67
- attribute \src "ls180.v:2696.6-2696.18"
+ attribute \src "ls180.v:2725.6-2725.18"
wire \sdrio_clk_68
- attribute \src "ls180.v:2601.6-2601.17"
+ attribute \src "ls180.v:2630.6-2630.17"
wire \sdrio_clk_7
- attribute \src "ls180.v:2602.6-2602.17"
+ attribute \src "ls180.v:2631.6-2631.17"
wire \sdrio_clk_8
- attribute \src "ls180.v:2603.6-2603.17"
+ attribute \src "ls180.v:2632.6-2632.17"
wire \sdrio_clk_9
- attribute \src "ls180.v:24.13-24.27"
- wire output 20 \spi_master_clk
- attribute \src "ls180.v:26.13-26.28"
- wire output 22 \spi_master_cs_n
+ attribute \src "ls180.v:26.13-26.27"
+ wire output 22 \spi_master_clk
+ attribute \src "ls180.v:28.13-28.28"
+ wire output 24 \spi_master_cs_n
+ attribute \src "ls180.v:29.13-29.28"
+ wire input 25 \spi_master_miso
attribute \src "ls180.v:27.13-27.28"
- wire input 23 \spi_master_miso
- attribute \src "ls180.v:25.13-25.28"
- wire output 21 \spi_master_mosi
- attribute \src "ls180.v:43.13-43.26"
- wire output 39 \spisdcard_clk
- attribute \src "ls180.v:45.13-45.27"
- wire output 41 \spisdcard_cs_n
- attribute \src "ls180.v:46.13-46.27"
- wire input 42 \spisdcard_miso
- attribute \src "ls180.v:44.13-44.27"
- wire output 40 \spisdcard_mosi
+ wire output 23 \spi_master_mosi
+ attribute \src "ls180.v:49.13-49.26"
+ wire output 45 \spisdcard_clk
+ attribute \src "ls180.v:51.13-51.27"
+ wire output 47 \spisdcard_cs_n
+ attribute \src "ls180.v:52.13-52.27"
+ wire input 48 \spisdcard_miso
+ attribute \src "ls180.v:50.13-50.27"
+ wire output 46 \spisdcard_mosi
attribute \src "ls180.v:5.13-5.20"
wire input 1 \sys_clk
- attribute \src "ls180.v:217.6-217.15"
+ attribute \src "ls180.v:225.6-225.15"
wire \sys_clk_1
+ attribute \src "ls180.v:7.19-7.31"
+ wire width 3 input 3 \sys_clksel_i
+ attribute \src "ls180.v:8.14-8.26"
+ wire output 4 \sys_pll_48_o
attribute \src "ls180.v:6.13-6.20"
wire input 2 \sys_rst
- attribute \src "ls180.v:218.6-218.15"
+ attribute \src "ls180.v:226.6-226.15"
wire \sys_rst_1
- attribute \src "ls180.v:20.13-20.20"
- wire input 16 \uart_rx
- attribute \src "ls180.v:19.14-19.21"
- wire output 15 \uart_tx
- attribute \src "ls180.v:9975.12-9975.15"
+ attribute \src "ls180.v:22.13-22.20"
+ wire input 18 \uart_rx
+ attribute \src "ls180.v:21.14-21.21"
+ wire output 17 \uart_tx
+ attribute \src "ls180.v:10038.12-10038.15"
memory width 32 size 128 \mem
- attribute \src "ls180.v:9995.12-9995.19"
+ attribute \src "ls180.v:10058.12-10058.19"
memory width 25 size 8 \storage
- attribute \src "ls180.v:10009.12-10009.21"
+ attribute \src "ls180.v:10072.12-10072.21"
memory width 25 size 8 \storage_1
- attribute \src "ls180.v:10023.12-10023.21"
+ attribute \src "ls180.v:10086.12-10086.21"
memory width 25 size 8 \storage_2
- attribute \src "ls180.v:10037.12-10037.21"
+ attribute \src "ls180.v:10100.12-10100.21"
memory width 25 size 8 \storage_3
- attribute \src "ls180.v:10051.11-10051.20"
+ attribute \src "ls180.v:10114.11-10114.20"
memory width 10 size 16 \storage_4
- attribute \src "ls180.v:10068.11-10068.20"
+ attribute \src "ls180.v:10131.11-10131.20"
memory width 10 size 16 \storage_5
- attribute \src "ls180.v:10085.11-10085.20"
+ attribute \src "ls180.v:10148.11-10148.20"
memory width 10 size 32 \storage_6
- attribute \src "ls180.v:10099.11-10099.20"
+ attribute \src "ls180.v:10162.11-10162.20"
memory width 10 size 32 \storage_7
- attribute \src "ls180.v:2768.68-2768.110"
- cell $add $add$ls180.v:2768$22
+ attribute \src "ls180.v:2799.68-2799.110"
+ cell $add $add$ls180.v:2799$22
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter0_counter
connect \B 1'1
- connect \Y $add$ls180.v:2768$22_Y
+ connect \Y $add$ls180.v:2799$22_Y
end
- attribute \src "ls180.v:2828.68-2828.110"
- cell $add $add$ls180.v:2828$33
+ attribute \src "ls180.v:2859.68-2859.110"
+ cell $add $add$ls180.v:2859$33
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter1_counter
connect \B 1'1
- connect \Y $add$ls180.v:2828$33_Y
+ connect \Y $add$ls180.v:2859$33_Y
end
- attribute \src "ls180.v:2888.68-2888.110"
- cell $add $add$ls180.v:2888$44
+ attribute \src "ls180.v:2919.68-2919.110"
+ cell $add $add$ls180.v:2919$44
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter2_counter
connect \B 1'1
- connect \Y $add$ls180.v:2888$44_Y
+ connect \Y $add$ls180.v:2919$44_Y
end
- attribute \src "ls180.v:4021.54-4021.83"
- cell $add $add$ls180.v:4021$537
+ attribute \src "ls180.v:4052.54-4052.83"
+ cell $add $add$ls180.v:4052$537
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_converter_counter
connect \B 1'1
- connect \Y $add$ls180.v:4021$537_Y
+ connect \Y $add$ls180.v:4052$537_Y
end
- attribute \src "ls180.v:4121.36-4121.89"
- cell $add $add$ls180.v:4121$583
+ attribute \src "ls180.v:4152.36-4152.89"
+ cell $add $add$ls180.v:4152$583
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_uart_tx_fifo_level0
connect \B \main_uart_tx_fifo_readable
- connect \Y $add$ls180.v:4121$583_Y
+ connect \Y $add$ls180.v:4152$583_Y
end
- attribute \src "ls180.v:4151.36-4151.89"
- cell $add $add$ls180.v:4151$594
+ attribute \src "ls180.v:4182.36-4182.89"
+ cell $add $add$ls180.v:4182$594
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_uart_rx_fifo_level0
connect \B \main_uart_rx_fifo_readable
- connect \Y $add$ls180.v:4151$594_Y
+ connect \Y $add$ls180.v:4182$594_Y
end
- attribute \src "ls180.v:4206.53-4206.81"
- cell $add $add$ls180.v:4206$607
+ attribute \src "ls180.v:4237.53-4237.81"
+ cell $add $add$ls180.v:4237$607
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_spi_master_count
connect \B 1'1
- connect \Y $add$ls180.v:4206$607_Y
+ connect \Y $add$ls180.v:4237$607_Y
end
- attribute \src "ls180.v:4306.58-4306.86"
- cell $add $add$ls180.v:4306$635
+ attribute \src "ls180.v:4341.58-4341.86"
+ cell $add $add$ls180.v:4341$635
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_init_count
connect \B 1'1
- connect \Y $add$ls180.v:4306$635_Y
+ connect \Y $add$ls180.v:4341$635_Y
end
- attribute \src "ls180.v:4363.58-4363.86"
- cell $add $add$ls180.v:4363$638
+ attribute \src "ls180.v:4398.58-4398.86"
+ cell $add $add$ls180.v:4398$638
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_cmdw_count
connect \B 1'1
- connect \Y $add$ls180.v:4363$638_Y
+ connect \Y $add$ls180.v:4398$638_Y
end
- attribute \src "ls180.v:4380.58-4380.86"
- cell $add $add$ls180.v:4380$640
+ attribute \src "ls180.v:4415.58-4415.86"
+ cell $add $add$ls180.v:4415$640
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_cmdw_count
connect \B 1'1
- connect \Y $add$ls180.v:4380$640_Y
+ connect \Y $add$ls180.v:4415$640_Y
end
- attribute \src "ls180.v:4473.59-4473.87"
- cell $add $add$ls180.v:4473$657
+ attribute \src "ls180.v:4508.59-4508.87"
+ cell $add $add$ls180.v:4508$657
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_cmdr_count
connect \B 1'1
- connect \Y $add$ls180.v:4473$657_Y
+ connect \Y $add$ls180.v:4508$657_Y
end
- attribute \src "ls180.v:4498.59-4498.87"
- cell $add $add$ls180.v:4498$660
+ attribute \src "ls180.v:4533.59-4533.87"
+ cell $add $add$ls180.v:4533$660
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_cmdr_count
connect \B 1'1
- connect \Y $add$ls180.v:4498$660_Y
+ connect \Y $add$ls180.v:4533$660_Y
end
- attribute \src "ls180.v:4620.53-4620.82"
- cell $add $add$ls180.v:4620$677
+ attribute \src "ls180.v:4655.53-4655.82"
+ cell $add $add$ls180.v:4655$677
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_dataw_count
connect \B 1'1
- connect \Y $add$ls180.v:4620$677_Y
+ connect \Y $add$ls180.v:4655$677_Y
end
- attribute \src "ls180.v:4731.65-4731.114"
- cell $add $add$ls180.v:4731$691
+ attribute \src "ls180.v:4766.65-4766.114"
+ cell $add $add$ls180.v:4766$691
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \main_sdphy_datar_sink_payload_block_length
connect \B 4'1000
- connect \Y $add$ls180.v:4731$691_Y
+ connect \Y $add$ls180.v:4766$691_Y
end
- attribute \src "ls180.v:4736.62-4736.91"
- cell $add $add$ls180.v:4736$694
+ attribute \src "ls180.v:4771.62-4771.91"
+ cell $add $add$ls180.v:4771$694
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \main_sdphy_datar_count
connect \B 1'1
- connect \Y $add$ls180.v:4736$694_Y
+ connect \Y $add$ls180.v:4771$694_Y
end
- attribute \src "ls180.v:4762.61-4762.90"
- cell $add $add$ls180.v:4762$697
+ attribute \src "ls180.v:4797.61-4797.90"
+ cell $add $add$ls180.v:4797$697
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \main_sdphy_datar_count
connect \B 1'1
- connect \Y $add$ls180.v:4762$697_Y
+ connect \Y $add$ls180.v:4797$697_Y
end
- attribute \src "ls180.v:4966.80-4966.117"
- cell $add $add$ls180.v:4966$882
+ attribute \src "ls180.v:5001.80-5001.117"
+ cell $add $add$ls180.v:5001$882
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdcore_crc16_inserter_cnt
connect \B 1'1
- connect \Y $add$ls180.v:4966$882_Y
+ connect \Y $add$ls180.v:5001$882_Y
end
- attribute \src "ls180.v:5160.54-5160.82"
- cell $add $add$ls180.v:5160$957
+ attribute \src "ls180.v:5195.54-5195.82"
+ cell $add $add$ls180.v:5195$957
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdcore_cmd_count
connect \B 1'1
- connect \Y $add$ls180.v:5160$957_Y
+ connect \Y $add$ls180.v:5195$957_Y
end
- attribute \src "ls180.v:5212.55-5212.84"
- cell $add $add$ls180.v:5212$967
+ attribute \src "ls180.v:5247.55-5247.84"
+ cell $add $add$ls180.v:5247$967
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdcore_data_count
connect \B 1'1
- connect \Y $add$ls180.v:5212$967_Y
+ connect \Y $add$ls180.v:5247$967_Y
end
- attribute \src "ls180.v:5238.57-5238.86"
- cell $add $add$ls180.v:5238$975
+ attribute \src "ls180.v:5273.57-5273.86"
+ cell $add $add$ls180.v:5273$975
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdcore_data_count
connect \B 1'1
- connect \Y $add$ls180.v:5238$975_Y
+ connect \Y $add$ls180.v:5273$975_Y
end
- attribute \src "ls180.v:5359.51-5359.134"
- cell $add $add$ls180.v:5359$991
+ attribute \src "ls180.v:5394.51-5394.134"
+ cell $add $add$ls180.v:5394$991
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdblock2mem_wishbonedmawriter_base
connect \B \main_sdblock2mem_wishbonedmawriter_offset
- connect \Y $add$ls180.v:5359$991_Y
+ connect \Y $add$ls180.v:5394$991_Y
end
- attribute \src "ls180.v:5362.77-5362.125"
- cell $add $add$ls180.v:5362$993
+ attribute \src "ls180.v:5397.77-5397.125"
+ cell $add $add$ls180.v:5397$993
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdblock2mem_wishbonedmawriter_offset
connect \B 1'1
- connect \Y $add$ls180.v:5362$993_Y
+ connect \Y $add$ls180.v:5397$993_Y
end
- attribute \src "ls180.v:5455.50-5455.105"
- cell $add $add$ls180.v:5455$1002
+ attribute \src "ls180.v:5490.50-5490.105"
+ cell $add $add$ls180.v:5490$1002
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdmem2block_dma_base
connect \B \main_sdmem2block_dma_offset
- connect \Y $add$ls180.v:5455$1002_Y
+ connect \Y $add$ls180.v:5490$1002_Y
end
- attribute \src "ls180.v:5457.77-5457.111"
- cell $add $add$ls180.v:5457$1003
+ attribute \src "ls180.v:5492.77-5492.111"
+ cell $add $add$ls180.v:5492$1003
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdmem2block_dma_offset
connect \B 1'1
- connect \Y $add$ls180.v:5457$1003_Y
+ connect \Y $add$ls180.v:5492$1003_Y
end
- attribute \src "ls180.v:5569.49-5569.73"
- cell $add $add$ls180.v:5569$1022
+ attribute \src "ls180.v:5604.49-5604.73"
+ cell $add $add$ls180.v:5604$1022
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \libresocsim_count
connect \B 1'1
- connect \Y $add$ls180.v:5569$1022_Y
+ connect \Y $add$ls180.v:5604$1022_Y
end
- attribute \src "ls180.v:7437.36-7437.70"
- cell $add $add$ls180.v:7437$2405
+ attribute \src "ls180.v:7483.36-7483.70"
+ cell $add $add$ls180.v:7483$2415
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_libresocsim_bus_errors
connect \B 1'1
- connect \Y $add$ls180.v:7437$2405_Y
+ connect \Y $add$ls180.v:7483$2415_Y
end
- attribute \src "ls180.v:7522.37-7522.72"
- cell $add $add$ls180.v:7522$2426
+ attribute \src "ls180.v:7568.37-7568.72"
+ cell $add $add$ls180.v:7568$2436
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_sequencer_counter
connect \B 1'1
- connect \Y $add$ls180.v:7522$2426_Y
+ connect \Y $add$ls180.v:7568$2436_Y
end
- attribute \src "ls180.v:7539.60-7539.119"
- cell $add $add$ls180.v:7539$2430
+ attribute \src "ls180.v:7585.60-7585.119"
+ cell $add $add$ls180.v:7585$2440
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $add$ls180.v:7539$2430_Y
+ connect \Y $add$ls180.v:7585$2440_Y
end
- attribute \src "ls180.v:7542.60-7542.119"
- cell $add $add$ls180.v:7542$2431
+ attribute \src "ls180.v:7588.60-7588.119"
+ cell $add $add$ls180.v:7588$2441
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
connect \B 1'1
- connect \Y $add$ls180.v:7542$2431_Y
+ connect \Y $add$ls180.v:7588$2441_Y
end
- attribute \src "ls180.v:7546.59-7546.116"
- cell $add $add$ls180.v:7546$2436
+ attribute \src "ls180.v:7592.59-7592.116"
+ cell $add $add$ls180.v:7592$2446
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $add$ls180.v:7546$2436_Y
+ connect \Y $add$ls180.v:7592$2446_Y
end
- attribute \src "ls180.v:7585.60-7585.119"
- cell $add $add$ls180.v:7585$2446
+ attribute \src "ls180.v:7631.60-7631.119"
+ cell $add $add$ls180.v:7631$2456
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $add$ls180.v:7585$2446_Y
+ connect \Y $add$ls180.v:7631$2456_Y
end
- attribute \src "ls180.v:7588.60-7588.119"
- cell $add $add$ls180.v:7588$2447
+ attribute \src "ls180.v:7634.60-7634.119"
+ cell $add $add$ls180.v:7634$2457
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
connect \B 1'1
- connect \Y $add$ls180.v:7588$2447_Y
+ connect \Y $add$ls180.v:7634$2457_Y
end
- attribute \src "ls180.v:7592.59-7592.116"
- cell $add $add$ls180.v:7592$2452
+ attribute \src "ls180.v:7638.59-7638.116"
+ cell $add $add$ls180.v:7638$2462
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $add$ls180.v:7592$2452_Y
+ connect \Y $add$ls180.v:7638$2462_Y
end
- attribute \src "ls180.v:7631.60-7631.119"
- cell $add $add$ls180.v:7631$2462
+ attribute \src "ls180.v:7677.60-7677.119"
+ cell $add $add$ls180.v:7677$2472
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $add$ls180.v:7631$2462_Y
+ connect \Y $add$ls180.v:7677$2472_Y
end
- attribute \src "ls180.v:7634.60-7634.119"
- cell $add $add$ls180.v:7634$2463
+ attribute \src "ls180.v:7680.60-7680.119"
+ cell $add $add$ls180.v:7680$2473
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
connect \B 1'1
- connect \Y $add$ls180.v:7634$2463_Y
+ connect \Y $add$ls180.v:7680$2473_Y
end
- attribute \src "ls180.v:7638.59-7638.116"
- cell $add $add$ls180.v:7638$2468
+ attribute \src "ls180.v:7684.59-7684.116"
+ cell $add $add$ls180.v:7684$2478
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $add$ls180.v:7638$2468_Y
+ connect \Y $add$ls180.v:7684$2478_Y
end
- attribute \src "ls180.v:7677.60-7677.119"
- cell $add $add$ls180.v:7677$2478
+ attribute \src "ls180.v:7723.60-7723.119"
+ cell $add $add$ls180.v:7723$2488
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $add$ls180.v:7677$2478_Y
+ connect \Y $add$ls180.v:7723$2488_Y
end
- attribute \src "ls180.v:7680.60-7680.119"
- cell $add $add$ls180.v:7680$2479
+ attribute \src "ls180.v:7726.60-7726.119"
+ cell $add $add$ls180.v:7726$2489
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
connect \B 1'1
- connect \Y $add$ls180.v:7680$2479_Y
+ connect \Y $add$ls180.v:7726$2489_Y
end
- attribute \src "ls180.v:7684.59-7684.116"
- cell $add $add$ls180.v:7684$2484
+ attribute \src "ls180.v:7730.59-7730.116"
+ cell $add $add$ls180.v:7730$2494
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $add$ls180.v:7684$2484_Y
+ connect \Y $add$ls180.v:7730$2494_Y
end
- attribute \src "ls180.v:7914.25-7914.48"
- cell $add $add$ls180.v:7914$2538
+ attribute \src "ls180.v:7960.34-7960.66"
+ cell $add $add$ls180.v:7960$2548
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 4
- connect \A \main_tx_bitcount
+ connect \A \main_uart_phy_tx_bitcount
connect \B 1'1
- connect \Y $add$ls180.v:7914$2538_Y
+ connect \Y $add$ls180.v:7960$2548_Y
end
- attribute \src "ls180.v:7930.55-7930.95"
- cell $add $add$ls180.v:7930$2541
+ attribute \src "ls180.v:7976.73-7976.131"
+ cell $add $add$ls180.v:7976$2551
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 33
- connect \A \main_phase_accumulator_tx
- connect \B \main_storage
- connect \Y $add$ls180.v:7930$2541_Y
+ connect \A \main_uart_phy_phase_accumulator_tx
+ connect \B \main_uart_phy_storage
+ connect \Y $add$ls180.v:7976$2551_Y
end
- attribute \src "ls180.v:7943.25-7943.48"
- cell $add $add$ls180.v:7943$2545
+ attribute \src "ls180.v:7989.34-7989.66"
+ cell $add $add$ls180.v:7989$2555
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 4
- connect \A \main_rx_bitcount
+ connect \A \main_uart_phy_rx_bitcount
connect \B 1'1
- connect \Y $add$ls180.v:7943$2545_Y
+ connect \Y $add$ls180.v:7989$2555_Y
end
- attribute \src "ls180.v:7962.55-7962.95"
- cell $add $add$ls180.v:7962$2548
+ attribute \src "ls180.v:8008.73-8008.131"
+ cell $add $add$ls180.v:8008$2558
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 33
- connect \A \main_phase_accumulator_rx
- connect \B \main_storage
- connect \Y $add$ls180.v:7962$2548_Y
+ connect \A \main_uart_phy_phase_accumulator_rx
+ connect \B \main_uart_phy_storage
+ connect \Y $add$ls180.v:8008$2558_Y
end
- attribute \src "ls180.v:7988.33-7988.65"
- cell $add $add$ls180.v:7988$2556
+ attribute \src "ls180.v:8034.33-8034.65"
+ cell $add $add$ls180.v:8034$2566
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_tx_fifo_produce
connect \B 1'1
- connect \Y $add$ls180.v:7988$2556_Y
+ connect \Y $add$ls180.v:8034$2566_Y
end
- attribute \src "ls180.v:7991.33-7991.65"
- cell $add $add$ls180.v:7991$2557
+ attribute \src "ls180.v:8037.33-8037.65"
+ cell $add $add$ls180.v:8037$2567
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_tx_fifo_consume
connect \B 1'1
- connect \Y $add$ls180.v:7991$2557_Y
+ connect \Y $add$ls180.v:8037$2567_Y
end
- attribute \src "ls180.v:7995.33-7995.64"
- cell $add $add$ls180.v:7995$2562
+ attribute \src "ls180.v:8041.33-8041.64"
+ cell $add $add$ls180.v:8041$2572
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_uart_tx_fifo_level0
connect \B 1'1
- connect \Y $add$ls180.v:7995$2562_Y
+ connect \Y $add$ls180.v:8041$2572_Y
end
- attribute \src "ls180.v:8010.33-8010.65"
- cell $add $add$ls180.v:8010$2567
+ attribute \src "ls180.v:8056.33-8056.65"
+ cell $add $add$ls180.v:8056$2577
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_rx_fifo_produce
connect \B 1'1
- connect \Y $add$ls180.v:8010$2567_Y
+ connect \Y $add$ls180.v:8056$2577_Y
end
- attribute \src "ls180.v:8013.33-8013.65"
- cell $add $add$ls180.v:8013$2568
+ attribute \src "ls180.v:8059.33-8059.65"
+ cell $add $add$ls180.v:8059$2578
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_rx_fifo_consume
connect \B 1'1
- connect \Y $add$ls180.v:8013$2568_Y
+ connect \Y $add$ls180.v:8059$2578_Y
end
- attribute \src "ls180.v:8017.33-8017.64"
- cell $add $add$ls180.v:8017$2573
+ attribute \src "ls180.v:8063.33-8063.64"
+ cell $add $add$ls180.v:8063$2583
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_uart_rx_fifo_level0
connect \B 1'1
- connect \Y $add$ls180.v:8017$2573_Y
+ connect \Y $add$ls180.v:8063$2583_Y
end
- attribute \src "ls180.v:8038.35-8038.70"
- cell $add $add$ls180.v:8038$2575
+ attribute \src "ls180.v:8084.35-8084.70"
+ cell $add $add$ls180.v:8084$2585
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \main_spi_master_clk_divider1
connect \B 1'1
- connect \Y $add$ls180.v:8038$2575_Y
+ connect \Y $add$ls180.v:8084$2585_Y
end
- attribute \src "ls180.v:8074.25-8074.49"
- cell $add $add$ls180.v:8074$2580
+ attribute \src "ls180.v:8120.25-8120.49"
+ cell $add $add$ls180.v:8120$2590
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_pwm0_counter
connect \B 1'1
- connect \Y $add$ls180.v:8074$2580_Y
+ connect \Y $add$ls180.v:8120$2590_Y
end
- attribute \src "ls180.v:8088.25-8088.49"
- cell $add $add$ls180.v:8088$2584
+ attribute \src "ls180.v:8134.25-8134.49"
+ cell $add $add$ls180.v:8134$2594
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_pwm1_counter
connect \B 1'1
- connect \Y $add$ls180.v:8088$2584_Y
+ connect \Y $add$ls180.v:8134$2594_Y
end
- attribute \src "ls180.v:8102.31-8102.61"
- cell $add $add$ls180.v:8102$2589
+ attribute \src "ls180.v:8148.31-8148.61"
+ cell $add $add$ls180.v:8148$2599
parameter \A_SIGNED 0
parameter \A_WIDTH 9
parameter \B_SIGNED 0
parameter \Y_WIDTH 9
connect \A \main_sdphy_clocker_clks
connect \B 1'1
- connect \Y $add$ls180.v:8102$2589_Y
+ connect \Y $add$ls180.v:8148$2599_Y
end
- attribute \src "ls180.v:8125.45-8125.88"
- cell $add $add$ls180.v:8125$2593
+ attribute \src "ls180.v:8171.45-8171.88"
+ cell $add $add$ls180.v:8171$2603
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdphy_cmdr_cmdr_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8125$2593_Y
+ connect \Y $add$ls180.v:8171$2603_Y
end
- attribute \src "ls180.v:8171.71-8171.114"
- cell $add $add$ls180.v:8171$2599
+ attribute \src "ls180.v:8217.71-8217.114"
+ cell $add $add$ls180.v:8217$2609
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdphy_cmdr_cmdr_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8171$2599_Y
+ connect \Y $add$ls180.v:8217$2609_Y
end
- attribute \src "ls180.v:8206.46-8206.90"
- cell $add $add$ls180.v:8206$2605
+ attribute \src "ls180.v:8252.46-8252.90"
+ cell $add $add$ls180.v:8252$2615
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdphy_dataw_crcr_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8206$2605_Y
+ connect \Y $add$ls180.v:8252$2615_Y
end
- attribute \src "ls180.v:8252.72-8252.116"
- cell $add $add$ls180.v:8252$2611
+ attribute \src "ls180.v:8298.72-8298.116"
+ cell $add $add$ls180.v:8298$2621
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdphy_dataw_crcr_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8252$2611_Y
+ connect \Y $add$ls180.v:8298$2621_Y
end
- attribute \src "ls180.v:8285.47-8285.92"
- cell $add $add$ls180.v:8285$2617
+ attribute \src "ls180.v:8331.47-8331.92"
+ cell $add $add$ls180.v:8331$2627
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8285$2617_Y
+ connect \Y $add$ls180.v:8331$2627_Y
end
- attribute \src "ls180.v:8313.73-8313.118"
- cell $add $add$ls180.v:8313$2623
+ attribute \src "ls180.v:8359.73-8359.118"
+ cell $add $add$ls180.v:8359$2633
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \main_sdphy_datar_datar_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8313$2623_Y
+ connect \Y $add$ls180.v:8359$2633_Y
end
- attribute \src "ls180.v:8425.39-8425.75"
- cell $add $add$ls180.v:8425$2636
+ attribute \src "ls180.v:8471.39-8471.75"
+ cell $add $add$ls180.v:8471$2646
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdcore_crc16_checker_cnt
connect \B 1'1
- connect \Y $add$ls180.v:8425$2636_Y
+ connect \Y $add$ls180.v:8471$2646_Y
end
- attribute \src "ls180.v:8486.37-8486.73"
- cell $add $add$ls180.v:8486$2640
+ attribute \src "ls180.v:8532.37-8532.73"
+ cell $add $add$ls180.v:8532$2650
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdblock2mem_fifo_produce
connect \B 1'1
- connect \Y $add$ls180.v:8486$2640_Y
+ connect \Y $add$ls180.v:8532$2650_Y
end
- attribute \src "ls180.v:8489.37-8489.73"
- cell $add $add$ls180.v:8489$2641
+ attribute \src "ls180.v:8535.37-8535.73"
+ cell $add $add$ls180.v:8535$2651
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdblock2mem_fifo_consume
connect \B 1'1
- connect \Y $add$ls180.v:8489$2641_Y
+ connect \Y $add$ls180.v:8535$2651_Y
end
- attribute \src "ls180.v:8493.36-8493.70"
- cell $add $add$ls180.v:8493$2646
+ attribute \src "ls180.v:8539.36-8539.70"
+ cell $add $add$ls180.v:8539$2656
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \main_sdblock2mem_fifo_level
connect \B 1'1
- connect \Y $add$ls180.v:8493$2646_Y
+ connect \Y $add$ls180.v:8539$2656_Y
end
- attribute \src "ls180.v:8508.41-8508.80"
- cell $add $add$ls180.v:8508$2650
+ attribute \src "ls180.v:8554.41-8554.80"
+ cell $add $add$ls180.v:8554$2660
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \main_sdblock2mem_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8508$2650_Y
+ connect \Y $add$ls180.v:8554$2660_Y
end
- attribute \src "ls180.v:8542.67-8542.106"
- cell $add $add$ls180.v:8542$2656
+ attribute \src "ls180.v:8588.67-8588.106"
+ cell $add $add$ls180.v:8588$2666
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdblock2mem_converter_demux
connect \B 1'1
- connect \Y $add$ls180.v:8542$2656_Y
+ connect \Y $add$ls180.v:8588$2666_Y
end
- attribute \src "ls180.v:8568.39-8568.76"
- cell $add $add$ls180.v:8568$2658
+ attribute \src "ls180.v:8614.39-8614.76"
+ cell $add $add$ls180.v:8614$2668
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \main_sdmem2block_converter_mux
connect \B 1'1
- connect \Y $add$ls180.v:8568$2658_Y
+ connect \Y $add$ls180.v:8614$2668_Y
end
- attribute \src "ls180.v:8572.37-8572.73"
- cell $add $add$ls180.v:8572$2662
+ attribute \src "ls180.v:8618.37-8618.73"
+ cell $add $add$ls180.v:8618$2672
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdmem2block_fifo_produce
connect \B 1'1
- connect \Y $add$ls180.v:8572$2662_Y
+ connect \Y $add$ls180.v:8618$2672_Y
end
- attribute \src "ls180.v:8575.37-8575.73"
- cell $add $add$ls180.v:8575$2663
+ attribute \src "ls180.v:8621.37-8621.73"
+ cell $add $add$ls180.v:8621$2673
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdmem2block_fifo_consume
connect \B 1'1
- connect \Y $add$ls180.v:8575$2663_Y
+ connect \Y $add$ls180.v:8621$2673_Y
end
- attribute \src "ls180.v:8579.36-8579.70"
- cell $add $add$ls180.v:8579$2668
+ attribute \src "ls180.v:8625.36-8625.70"
+ cell $add $add$ls180.v:8625$2678
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \main_sdmem2block_fifo_level
connect \B 1'1
- connect \Y $add$ls180.v:8579$2668_Y
+ connect \Y $add$ls180.v:8625$2678_Y
end
- attribute \src "ls180.v:8586.31-8586.62"
- cell $add $add$ls180.v:8586$2670
+ attribute \src "ls180.v:8632.31-8632.62"
+ cell $add $add$ls180.v:8632$2680
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \libresocsim_clk_divider1
connect \B 1'1
- connect \Y $add$ls180.v:8586$2670_Y
+ connect \Y $add$ls180.v:8632$2680_Y
end
- attribute \src "ls180.v:2762.9-2762.80"
- cell $and $and$ls180.v:2762$17
+ attribute \src "ls180.v:2793.9-2793.80"
+ cell $and $and$ls180.v:2793$17
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_ibus_stb
connect \B \main_libresocsim_libresoc_ibus_cyc
- connect \Y $and$ls180.v:2762$17_Y
+ connect \Y $and$ls180.v:2793$17_Y
end
- attribute \src "ls180.v:2780.9-2780.80"
- cell $and $and$ls180.v:2780$24
+ attribute \src "ls180.v:2811.9-2811.80"
+ cell $and $and$ls180.v:2811$24
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_ibus_stb
connect \B \main_libresocsim_libresoc_ibus_cyc
- connect \Y $and$ls180.v:2780$24_Y
+ connect \Y $and$ls180.v:2811$24_Y
end
- attribute \src "ls180.v:2822.9-2822.80"
- cell $and $and$ls180.v:2822$28
+ attribute \src "ls180.v:2853.9-2853.80"
+ cell $and $and$ls180.v:2853$28
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_dbus_stb
connect \B \main_libresocsim_libresoc_dbus_cyc
- connect \Y $and$ls180.v:2822$28_Y
+ connect \Y $and$ls180.v:2853$28_Y
end
- attribute \src "ls180.v:2840.9-2840.80"
- cell $and $and$ls180.v:2840$35
+ attribute \src "ls180.v:2871.9-2871.80"
+ cell $and $and$ls180.v:2871$35
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_dbus_stb
connect \B \main_libresocsim_libresoc_dbus_cyc
- connect \Y $and$ls180.v:2840$35_Y
+ connect \Y $and$ls180.v:2871$35_Y
end
- attribute \src "ls180.v:2882.9-2882.86"
- cell $and $and$ls180.v:2882$39
+ attribute \src "ls180.v:2913.9-2913.86"
+ cell $and $and$ls180.v:2913$39
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_jtag_wb_stb
connect \B \main_libresocsim_libresoc_jtag_wb_cyc
- connect \Y $and$ls180.v:2882$39_Y
+ connect \Y $and$ls180.v:2913$39_Y
end
- attribute \src "ls180.v:2900.9-2900.86"
- cell $and $and$ls180.v:2900$46
+ attribute \src "ls180.v:2931.9-2931.86"
+ cell $and $and$ls180.v:2931$46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_jtag_wb_stb
connect \B \main_libresocsim_libresoc_jtag_wb_cyc
- connect \Y $and$ls180.v:2900$46_Y
+ connect \Y $and$ls180.v:2931$46_Y
end
- attribute \src "ls180.v:2910.31-2910.90"
- cell $and $and$ls180.v:2910$48
+ attribute \src "ls180.v:2941.31-2941.90"
+ cell $and $and$ls180.v:2941$48
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_cyc
connect \B \main_libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:2910$48_Y
+ connect \Y $and$ls180.v:2941$48_Y
end
- attribute \src "ls180.v:2910.30-2910.121"
- cell $and $and$ls180.v:2910$49
+ attribute \src "ls180.v:2941.30-2941.121"
+ cell $and $and$ls180.v:2941$49
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2910$48_Y
+ connect \A $and$ls180.v:2941$48_Y
connect \B \main_libresocsim_ram_bus_we
- connect \Y $and$ls180.v:2910$49_Y
+ connect \Y $and$ls180.v:2941$49_Y
end
- attribute \src "ls180.v:2910.29-2910.156"
- cell $and $and$ls180.v:2910$50
+ attribute \src "ls180.v:2941.29-2941.156"
+ cell $and $and$ls180.v:2941$50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2910$49_Y
+ connect \A $and$ls180.v:2941$49_Y
connect \B \main_libresocsim_ram_bus_sel [0]
- connect \Y $and$ls180.v:2910$50_Y
+ connect \Y $and$ls180.v:2941$50_Y
end
- attribute \src "ls180.v:2911.31-2911.90"
- cell $and $and$ls180.v:2911$51
+ attribute \src "ls180.v:2942.31-2942.90"
+ cell $and $and$ls180.v:2942$51
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_cyc
connect \B \main_libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:2911$51_Y
+ connect \Y $and$ls180.v:2942$51_Y
end
- attribute \src "ls180.v:2911.30-2911.121"
- cell $and $and$ls180.v:2911$52
+ attribute \src "ls180.v:2942.30-2942.121"
+ cell $and $and$ls180.v:2942$52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2911$51_Y
+ connect \A $and$ls180.v:2942$51_Y
connect \B \main_libresocsim_ram_bus_we
- connect \Y $and$ls180.v:2911$52_Y
+ connect \Y $and$ls180.v:2942$52_Y
end
- attribute \src "ls180.v:2911.29-2911.156"
- cell $and $and$ls180.v:2911$53
+ attribute \src "ls180.v:2942.29-2942.156"
+ cell $and $and$ls180.v:2942$53
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2911$52_Y
+ connect \A $and$ls180.v:2942$52_Y
connect \B \main_libresocsim_ram_bus_sel [1]
- connect \Y $and$ls180.v:2911$53_Y
+ connect \Y $and$ls180.v:2942$53_Y
end
- attribute \src "ls180.v:2912.31-2912.90"
- cell $and $and$ls180.v:2912$54
+ attribute \src "ls180.v:2943.31-2943.90"
+ cell $and $and$ls180.v:2943$54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_cyc
connect \B \main_libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:2912$54_Y
+ connect \Y $and$ls180.v:2943$54_Y
end
- attribute \src "ls180.v:2912.30-2912.121"
- cell $and $and$ls180.v:2912$55
+ attribute \src "ls180.v:2943.30-2943.121"
+ cell $and $and$ls180.v:2943$55
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2912$54_Y
+ connect \A $and$ls180.v:2943$54_Y
connect \B \main_libresocsim_ram_bus_we
- connect \Y $and$ls180.v:2912$55_Y
+ connect \Y $and$ls180.v:2943$55_Y
end
- attribute \src "ls180.v:2912.29-2912.156"
- cell $and $and$ls180.v:2912$56
+ attribute \src "ls180.v:2943.29-2943.156"
+ cell $and $and$ls180.v:2943$56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2912$55_Y
+ connect \A $and$ls180.v:2943$55_Y
connect \B \main_libresocsim_ram_bus_sel [2]
- connect \Y $and$ls180.v:2912$56_Y
+ connect \Y $and$ls180.v:2943$56_Y
end
- attribute \src "ls180.v:2913.31-2913.90"
- cell $and $and$ls180.v:2913$57
+ attribute \src "ls180.v:2944.31-2944.90"
+ cell $and $and$ls180.v:2944$57
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_cyc
connect \B \main_libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:2913$57_Y
+ connect \Y $and$ls180.v:2944$57_Y
end
- attribute \src "ls180.v:2913.30-2913.121"
- cell $and $and$ls180.v:2913$58
+ attribute \src "ls180.v:2944.30-2944.121"
+ cell $and $and$ls180.v:2944$58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2913$57_Y
+ connect \A $and$ls180.v:2944$57_Y
connect \B \main_libresocsim_ram_bus_we
- connect \Y $and$ls180.v:2913$58_Y
+ connect \Y $and$ls180.v:2944$58_Y
end
- attribute \src "ls180.v:2913.29-2913.156"
- cell $and $and$ls180.v:2913$59
+ attribute \src "ls180.v:2944.29-2944.156"
+ cell $and $and$ls180.v:2944$59
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2913$58_Y
+ connect \A $and$ls180.v:2944$58_Y
connect \B \main_libresocsim_ram_bus_sel [3]
- connect \Y $and$ls180.v:2913$59_Y
+ connect \Y $and$ls180.v:2944$59_Y
end
- attribute \src "ls180.v:2922.7-2922.89"
- cell $and $and$ls180.v:2922$62
+ attribute \src "ls180.v:2953.7-2953.89"
+ cell $and $and$ls180.v:2953$62
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_eventmanager_pending_re
connect \B \main_libresocsim_eventmanager_pending_r
- connect \Y $and$ls180.v:2922$62_Y
+ connect \Y $and$ls180.v:2953$62_Y
end
- attribute \src "ls180.v:2927.32-2927.111"
- cell $and $and$ls180.v:2927$63
+ attribute \src "ls180.v:2958.32-2958.111"
+ cell $and $and$ls180.v:2958$63
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_eventmanager_pending_w
connect \B \main_libresocsim_eventmanager_storage
- connect \Y $and$ls180.v:2927$63_Y
+ connect \Y $and$ls180.v:2958$63_Y
end
- attribute \src "ls180.v:3041.40-3041.99"
- cell $and $and$ls180.v:3041$70
+ attribute \src "ls180.v:3072.40-3072.99"
+ cell $and $and$ls180.v:3072$70
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_command_issue_re
connect \B \main_sdram_command_storage [4]
- connect \Y $and$ls180.v:3041$70_Y
+ connect \Y $and$ls180.v:3072$70_Y
end
- attribute \src "ls180.v:3042.40-3042.99"
- cell $and $and$ls180.v:3042$71
+ attribute \src "ls180.v:3073.40-3073.99"
+ cell $and $and$ls180.v:3073$71
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_command_issue_re
connect \B \main_sdram_command_storage [5]
- connect \Y $and$ls180.v:3042$71_Y
+ connect \Y $and$ls180.v:3073$71_Y
end
- attribute \src "ls180.v:3080.38-3080.103"
- cell $and $and$ls180.v:3080$77
+ attribute \src "ls180.v:3111.38-3111.103"
+ cell $and $and$ls180.v:3111$77
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_done1
- connect \B $eq$ls180.v:3080$76_Y
- connect \Y $and$ls180.v:3080$77_Y
+ connect \B $eq$ls180.v:3111$76_Y
+ connect \Y $and$ls180.v:3111$77_Y
end
- attribute \src "ls180.v:3134.50-3134.119"
- cell $and $and$ls180.v:3134$85
+ attribute \src "ls180.v:3165.50-3165.119"
+ cell $and $and$ls180.v:3165$85
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
connect \B \main_sdram_bankmachine0_cmd_ready
- connect \Y $and$ls180.v:3134$85_Y
+ connect \Y $and$ls180.v:3165$85_Y
end
- attribute \src "ls180.v:3134.49-3134.167"
- cell $and $and$ls180.v:3134$86
+ attribute \src "ls180.v:3165.49-3165.167"
+ cell $and $and$ls180.v:3165$86
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3134$85_Y
+ connect \A $and$ls180.v:3165$85_Y
connect \B \main_sdram_bankmachine0_cmd_payload_is_write
- connect \Y $and$ls180.v:3134$86_Y
+ connect \Y $and$ls180.v:3165$86_Y
end
- attribute \src "ls180.v:3135.49-3135.118"
- cell $and $and$ls180.v:3135$87
+ attribute \src "ls180.v:3166.49-3166.118"
+ cell $and $and$ls180.v:3166$87
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
connect \B \main_sdram_bankmachine0_cmd_ready
- connect \Y $and$ls180.v:3135$87_Y
+ connect \Y $and$ls180.v:3166$87_Y
end
- attribute \src "ls180.v:3135.48-3135.154"
- cell $and $and$ls180.v:3135$88
+ attribute \src "ls180.v:3166.48-3166.154"
+ cell $and $and$ls180.v:3166$88
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3135$87_Y
+ connect \A $and$ls180.v:3166$87_Y
connect \B \main_sdram_bankmachine0_row_open
- connect \Y $and$ls180.v:3135$88_Y
+ connect \Y $and$ls180.v:3166$88_Y
end
- attribute \src "ls180.v:3136.50-3136.119"
- cell $and $and$ls180.v:3136$89
+ attribute \src "ls180.v:3167.50-3167.119"
+ cell $and $and$ls180.v:3167$89
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
connect \B \main_sdram_bankmachine0_cmd_ready
- connect \Y $and$ls180.v:3136$89_Y
+ connect \Y $and$ls180.v:3167$89_Y
end
- attribute \src "ls180.v:3136.49-3136.155"
- cell $and $and$ls180.v:3136$90
+ attribute \src "ls180.v:3167.49-3167.155"
+ cell $and $and$ls180.v:3167$90
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3136$89_Y
+ connect \A $and$ls180.v:3167$89_Y
connect \B \main_sdram_bankmachine0_row_open
- connect \Y $and$ls180.v:3136$90_Y
+ connect \Y $and$ls180.v:3167$90_Y
end
- attribute \src "ls180.v:3139.7-3139.114"
- cell $and $and$ls180.v:3139$92
+ attribute \src "ls180.v:3170.7-3170.114"
+ cell $and $and$ls180.v:3170$92
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid
- connect \Y $and$ls180.v:3139$92_Y
+ connect \Y $and$ls180.v:3170$92_Y
end
- attribute \src "ls180.v:3168.66-3168.246"
- cell $and $and$ls180.v:3168$98
+ attribute \src "ls180.v:3199.66-3199.246"
+ cell $and $and$ls180.v:3199$98
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
- connect \B $or$ls180.v:3168$97_Y
- connect \Y $and$ls180.v:3168$98_Y
+ connect \B $or$ls180.v:3199$97_Y
+ connect \Y $and$ls180.v:3199$98_Y
end
- attribute \src "ls180.v:3169.64-3169.187"
- cell $and $and$ls180.v:3169$99
+ attribute \src "ls180.v:3200.64-3200.187"
+ cell $and $and$ls180.v:3200$99
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable
connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re
- connect \Y $and$ls180.v:3169$99_Y
+ connect \Y $and$ls180.v:3200$99_Y
end
- attribute \src "ls180.v:3193.9-3193.86"
- cell $and $and$ls180.v:3193$105
+ attribute \src "ls180.v:3224.9-3224.86"
+ cell $and $and$ls180.v:3224$105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_twtpcon_ready
connect \B \main_sdram_bankmachine0_trascon_ready
- connect \Y $and$ls180.v:3193$105_Y
+ connect \Y $and$ls180.v:3224$105_Y
end
- attribute \src "ls180.v:3205.9-3205.86"
- cell $and $and$ls180.v:3205$106
+ attribute \src "ls180.v:3236.9-3236.86"
+ cell $and $and$ls180.v:3236$106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_twtpcon_ready
connect \B \main_sdram_bankmachine0_trascon_ready
- connect \Y $and$ls180.v:3205$106_Y
+ connect \Y $and$ls180.v:3236$106_Y
end
- attribute \src "ls180.v:3255.13-3255.87"
- cell $and $and$ls180.v:3255$108
+ attribute \src "ls180.v:3286.13-3286.87"
+ cell $and $and$ls180.v:3286$108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_ready
connect \B \main_sdram_bankmachine0_auto_precharge
- connect \Y $and$ls180.v:3255$108_Y
+ connect \Y $and$ls180.v:3286$108_Y
end
- attribute \src "ls180.v:3291.50-3291.119"
- cell $and $and$ls180.v:3291$115
+ attribute \src "ls180.v:3322.50-3322.119"
+ cell $and $and$ls180.v:3322$115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
connect \B \main_sdram_bankmachine1_cmd_ready
- connect \Y $and$ls180.v:3291$115_Y
+ connect \Y $and$ls180.v:3322$115_Y
end
- attribute \src "ls180.v:3291.49-3291.167"
- cell $and $and$ls180.v:3291$116
+ attribute \src "ls180.v:3322.49-3322.167"
+ cell $and $and$ls180.v:3322$116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3291$115_Y
+ connect \A $and$ls180.v:3322$115_Y
connect \B \main_sdram_bankmachine1_cmd_payload_is_write
- connect \Y $and$ls180.v:3291$116_Y
+ connect \Y $and$ls180.v:3322$116_Y
end
- attribute \src "ls180.v:3292.49-3292.118"
- cell $and $and$ls180.v:3292$117
+ attribute \src "ls180.v:3323.49-3323.118"
+ cell $and $and$ls180.v:3323$117
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
connect \B \main_sdram_bankmachine1_cmd_ready
- connect \Y $and$ls180.v:3292$117_Y
+ connect \Y $and$ls180.v:3323$117_Y
end
- attribute \src "ls180.v:3292.48-3292.154"
- cell $and $and$ls180.v:3292$118
+ attribute \src "ls180.v:3323.48-3323.154"
+ cell $and $and$ls180.v:3323$118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3292$117_Y
+ connect \A $and$ls180.v:3323$117_Y
connect \B \main_sdram_bankmachine1_row_open
- connect \Y $and$ls180.v:3292$118_Y
+ connect \Y $and$ls180.v:3323$118_Y
end
- attribute \src "ls180.v:3293.50-3293.119"
- cell $and $and$ls180.v:3293$119
+ attribute \src "ls180.v:3324.50-3324.119"
+ cell $and $and$ls180.v:3324$119
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
connect \B \main_sdram_bankmachine1_cmd_ready
- connect \Y $and$ls180.v:3293$119_Y
+ connect \Y $and$ls180.v:3324$119_Y
end
- attribute \src "ls180.v:3293.49-3293.155"
- cell $and $and$ls180.v:3293$120
+ attribute \src "ls180.v:3324.49-3324.155"
+ cell $and $and$ls180.v:3324$120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3293$119_Y
+ connect \A $and$ls180.v:3324$119_Y
connect \B \main_sdram_bankmachine1_row_open
- connect \Y $and$ls180.v:3293$120_Y
+ connect \Y $and$ls180.v:3324$120_Y
end
- attribute \src "ls180.v:3296.7-3296.114"
- cell $and $and$ls180.v:3296$122
+ attribute \src "ls180.v:3327.7-3327.114"
+ cell $and $and$ls180.v:3327$122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid
- connect \Y $and$ls180.v:3296$122_Y
+ connect \Y $and$ls180.v:3327$122_Y
end
- attribute \src "ls180.v:3325.66-3325.246"
- cell $and $and$ls180.v:3325$128
+ attribute \src "ls180.v:3356.66-3356.246"
+ cell $and $and$ls180.v:3356$128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
- connect \B $or$ls180.v:3325$127_Y
- connect \Y $and$ls180.v:3325$128_Y
+ connect \B $or$ls180.v:3356$127_Y
+ connect \Y $and$ls180.v:3356$128_Y
end
- attribute \src "ls180.v:3326.64-3326.187"
- cell $and $and$ls180.v:3326$129
+ attribute \src "ls180.v:3357.64-3357.187"
+ cell $and $and$ls180.v:3357$129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable
connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re
- connect \Y $and$ls180.v:3326$129_Y
+ connect \Y $and$ls180.v:3357$129_Y
end
- attribute \src "ls180.v:3350.9-3350.86"
- cell $and $and$ls180.v:3350$135
+ attribute \src "ls180.v:3381.9-3381.86"
+ cell $and $and$ls180.v:3381$135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_twtpcon_ready
connect \B \main_sdram_bankmachine1_trascon_ready
- connect \Y $and$ls180.v:3350$135_Y
+ connect \Y $and$ls180.v:3381$135_Y
end
- attribute \src "ls180.v:3362.9-3362.86"
- cell $and $and$ls180.v:3362$136
+ attribute \src "ls180.v:3393.9-3393.86"
+ cell $and $and$ls180.v:3393$136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_twtpcon_ready
connect \B \main_sdram_bankmachine1_trascon_ready
- connect \Y $and$ls180.v:3362$136_Y
+ connect \Y $and$ls180.v:3393$136_Y
end
- attribute \src "ls180.v:3412.13-3412.87"
- cell $and $and$ls180.v:3412$138
+ attribute \src "ls180.v:3443.13-3443.87"
+ cell $and $and$ls180.v:3443$138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_ready
connect \B \main_sdram_bankmachine1_auto_precharge
- connect \Y $and$ls180.v:3412$138_Y
+ connect \Y $and$ls180.v:3443$138_Y
end
- attribute \src "ls180.v:3448.50-3448.119"
- cell $and $and$ls180.v:3448$145
+ attribute \src "ls180.v:3479.50-3479.119"
+ cell $and $and$ls180.v:3479$145
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
connect \B \main_sdram_bankmachine2_cmd_ready
- connect \Y $and$ls180.v:3448$145_Y
+ connect \Y $and$ls180.v:3479$145_Y
end
- attribute \src "ls180.v:3448.49-3448.167"
- cell $and $and$ls180.v:3448$146
+ attribute \src "ls180.v:3479.49-3479.167"
+ cell $and $and$ls180.v:3479$146
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3448$145_Y
+ connect \A $and$ls180.v:3479$145_Y
connect \B \main_sdram_bankmachine2_cmd_payload_is_write
- connect \Y $and$ls180.v:3448$146_Y
+ connect \Y $and$ls180.v:3479$146_Y
end
- attribute \src "ls180.v:3449.49-3449.118"
- cell $and $and$ls180.v:3449$147
+ attribute \src "ls180.v:3480.49-3480.118"
+ cell $and $and$ls180.v:3480$147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
connect \B \main_sdram_bankmachine2_cmd_ready
- connect \Y $and$ls180.v:3449$147_Y
+ connect \Y $and$ls180.v:3480$147_Y
end
- attribute \src "ls180.v:3449.48-3449.154"
- cell $and $and$ls180.v:3449$148
+ attribute \src "ls180.v:3480.48-3480.154"
+ cell $and $and$ls180.v:3480$148
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3449$147_Y
+ connect \A $and$ls180.v:3480$147_Y
connect \B \main_sdram_bankmachine2_row_open
- connect \Y $and$ls180.v:3449$148_Y
+ connect \Y $and$ls180.v:3480$148_Y
end
- attribute \src "ls180.v:3450.50-3450.119"
- cell $and $and$ls180.v:3450$149
+ attribute \src "ls180.v:3481.50-3481.119"
+ cell $and $and$ls180.v:3481$149
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
connect \B \main_sdram_bankmachine2_cmd_ready
- connect \Y $and$ls180.v:3450$149_Y
+ connect \Y $and$ls180.v:3481$149_Y
end
- attribute \src "ls180.v:3450.49-3450.155"
- cell $and $and$ls180.v:3450$150
+ attribute \src "ls180.v:3481.49-3481.155"
+ cell $and $and$ls180.v:3481$150
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3450$149_Y
+ connect \A $and$ls180.v:3481$149_Y
connect \B \main_sdram_bankmachine2_row_open
- connect \Y $and$ls180.v:3450$150_Y
+ connect \Y $and$ls180.v:3481$150_Y
end
- attribute \src "ls180.v:3453.7-3453.114"
- cell $and $and$ls180.v:3453$152
+ attribute \src "ls180.v:3484.7-3484.114"
+ cell $and $and$ls180.v:3484$152
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid
- connect \Y $and$ls180.v:3453$152_Y
+ connect \Y $and$ls180.v:3484$152_Y
end
- attribute \src "ls180.v:3482.66-3482.246"
- cell $and $and$ls180.v:3482$158
+ attribute \src "ls180.v:3513.66-3513.246"
+ cell $and $and$ls180.v:3513$158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
- connect \B $or$ls180.v:3482$157_Y
- connect \Y $and$ls180.v:3482$158_Y
+ connect \B $or$ls180.v:3513$157_Y
+ connect \Y $and$ls180.v:3513$158_Y
end
- attribute \src "ls180.v:3483.64-3483.187"
- cell $and $and$ls180.v:3483$159
+ attribute \src "ls180.v:3514.64-3514.187"
+ cell $and $and$ls180.v:3514$159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable
connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re
- connect \Y $and$ls180.v:3483$159_Y
+ connect \Y $and$ls180.v:3514$159_Y
end
- attribute \src "ls180.v:3507.9-3507.86"
- cell $and $and$ls180.v:3507$165
+ attribute \src "ls180.v:3538.9-3538.86"
+ cell $and $and$ls180.v:3538$165
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_twtpcon_ready
connect \B \main_sdram_bankmachine2_trascon_ready
- connect \Y $and$ls180.v:3507$165_Y
+ connect \Y $and$ls180.v:3538$165_Y
end
- attribute \src "ls180.v:3519.9-3519.86"
- cell $and $and$ls180.v:3519$166
+ attribute \src "ls180.v:3550.9-3550.86"
+ cell $and $and$ls180.v:3550$166
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_twtpcon_ready
connect \B \main_sdram_bankmachine2_trascon_ready
- connect \Y $and$ls180.v:3519$166_Y
+ connect \Y $and$ls180.v:3550$166_Y
end
- attribute \src "ls180.v:3569.13-3569.87"
- cell $and $and$ls180.v:3569$168
+ attribute \src "ls180.v:3600.13-3600.87"
+ cell $and $and$ls180.v:3600$168
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_ready
connect \B \main_sdram_bankmachine2_auto_precharge
- connect \Y $and$ls180.v:3569$168_Y
+ connect \Y $and$ls180.v:3600$168_Y
end
- attribute \src "ls180.v:3605.50-3605.119"
- cell $and $and$ls180.v:3605$175
+ attribute \src "ls180.v:3636.50-3636.119"
+ cell $and $and$ls180.v:3636$175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
connect \B \main_sdram_bankmachine3_cmd_ready
- connect \Y $and$ls180.v:3605$175_Y
+ connect \Y $and$ls180.v:3636$175_Y
end
- attribute \src "ls180.v:3605.49-3605.167"
- cell $and $and$ls180.v:3605$176
+ attribute \src "ls180.v:3636.49-3636.167"
+ cell $and $and$ls180.v:3636$176
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3605$175_Y
+ connect \A $and$ls180.v:3636$175_Y
connect \B \main_sdram_bankmachine3_cmd_payload_is_write
- connect \Y $and$ls180.v:3605$176_Y
+ connect \Y $and$ls180.v:3636$176_Y
end
- attribute \src "ls180.v:3606.49-3606.118"
- cell $and $and$ls180.v:3606$177
+ attribute \src "ls180.v:3637.49-3637.118"
+ cell $and $and$ls180.v:3637$177
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
connect \B \main_sdram_bankmachine3_cmd_ready
- connect \Y $and$ls180.v:3606$177_Y
+ connect \Y $and$ls180.v:3637$177_Y
end
- attribute \src "ls180.v:3606.48-3606.154"
- cell $and $and$ls180.v:3606$178
+ attribute \src "ls180.v:3637.48-3637.154"
+ cell $and $and$ls180.v:3637$178
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3606$177_Y
+ connect \A $and$ls180.v:3637$177_Y
connect \B \main_sdram_bankmachine3_row_open
- connect \Y $and$ls180.v:3606$178_Y
+ connect \Y $and$ls180.v:3637$178_Y
end
- attribute \src "ls180.v:3607.50-3607.119"
- cell $and $and$ls180.v:3607$179
+ attribute \src "ls180.v:3638.50-3638.119"
+ cell $and $and$ls180.v:3638$179
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
connect \B \main_sdram_bankmachine3_cmd_ready
- connect \Y $and$ls180.v:3607$179_Y
+ connect \Y $and$ls180.v:3638$179_Y
end
- attribute \src "ls180.v:3607.49-3607.155"
- cell $and $and$ls180.v:3607$180
+ attribute \src "ls180.v:3638.49-3638.155"
+ cell $and $and$ls180.v:3638$180
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3607$179_Y
+ connect \A $and$ls180.v:3638$179_Y
connect \B \main_sdram_bankmachine3_row_open
- connect \Y $and$ls180.v:3607$180_Y
+ connect \Y $and$ls180.v:3638$180_Y
end
- attribute \src "ls180.v:3610.7-3610.114"
- cell $and $and$ls180.v:3610$182
+ attribute \src "ls180.v:3641.7-3641.114"
+ cell $and $and$ls180.v:3641$182
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid
- connect \Y $and$ls180.v:3610$182_Y
+ connect \Y $and$ls180.v:3641$182_Y
end
- attribute \src "ls180.v:3639.66-3639.246"
- cell $and $and$ls180.v:3639$188
+ attribute \src "ls180.v:3670.66-3670.246"
+ cell $and $and$ls180.v:3670$188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
- connect \B $or$ls180.v:3639$187_Y
- connect \Y $and$ls180.v:3639$188_Y
+ connect \B $or$ls180.v:3670$187_Y
+ connect \Y $and$ls180.v:3670$188_Y
end
- attribute \src "ls180.v:3640.64-3640.187"
- cell $and $and$ls180.v:3640$189
+ attribute \src "ls180.v:3671.64-3671.187"
+ cell $and $and$ls180.v:3671$189
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable
connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re
- connect \Y $and$ls180.v:3640$189_Y
+ connect \Y $and$ls180.v:3671$189_Y
end
- attribute \src "ls180.v:3664.9-3664.86"
- cell $and $and$ls180.v:3664$195
+ attribute \src "ls180.v:3695.9-3695.86"
+ cell $and $and$ls180.v:3695$195
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_twtpcon_ready
connect \B \main_sdram_bankmachine3_trascon_ready
- connect \Y $and$ls180.v:3664$195_Y
+ connect \Y $and$ls180.v:3695$195_Y
end
- attribute \src "ls180.v:3676.9-3676.86"
- cell $and $and$ls180.v:3676$196
+ attribute \src "ls180.v:3707.9-3707.86"
+ cell $and $and$ls180.v:3707$196
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_twtpcon_ready
connect \B \main_sdram_bankmachine3_trascon_ready
- connect \Y $and$ls180.v:3676$196_Y
+ connect \Y $and$ls180.v:3707$196_Y
end
- attribute \src "ls180.v:3726.13-3726.87"
- cell $and $and$ls180.v:3726$198
+ attribute \src "ls180.v:3757.13-3757.87"
+ cell $and $and$ls180.v:3757$198
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_ready
connect \B \main_sdram_bankmachine3_auto_precharge
- connect \Y $and$ls180.v:3726$198_Y
+ connect \Y $and$ls180.v:3757$198_Y
end
- attribute \src "ls180.v:3741.37-3741.102"
- cell $and $and$ls180.v:3741$199
+ attribute \src "ls180.v:3772.37-3772.102"
+ cell $and $and$ls180.v:3772$199
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3741$199_Y
+ connect \Y $and$ls180.v:3772$199_Y
end
- attribute \src "ls180.v:3741.108-3741.188"
- cell $and $and$ls180.v:3741$201
+ attribute \src "ls180.v:3772.108-3772.188"
+ cell $and $and$ls180.v:3772$201
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_ras
- connect \B $not$ls180.v:3741$200_Y
- connect \Y $and$ls180.v:3741$201_Y
+ connect \B $not$ls180.v:3772$200_Y
+ connect \Y $and$ls180.v:3772$201_Y
end
- attribute \src "ls180.v:3741.107-3741.231"
- cell $and $and$ls180.v:3741$203
+ attribute \src "ls180.v:3772.107-3772.231"
+ cell $and $and$ls180.v:3772$203
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3741$201_Y
- connect \B $not$ls180.v:3741$202_Y
- connect \Y $and$ls180.v:3741$203_Y
+ connect \A $and$ls180.v:3772$201_Y
+ connect \B $not$ls180.v:3772$202_Y
+ connect \Y $and$ls180.v:3772$203_Y
end
- attribute \src "ls180.v:3741.36-3741.232"
- cell $and $and$ls180.v:3741$204
+ attribute \src "ls180.v:3772.36-3772.232"
+ cell $and $and$ls180.v:3772$204
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3741$199_Y
- connect \B $and$ls180.v:3741$203_Y
- connect \Y $and$ls180.v:3741$204_Y
+ connect \A $and$ls180.v:3772$199_Y
+ connect \B $and$ls180.v:3772$203_Y
+ connect \Y $and$ls180.v:3772$204_Y
end
- attribute \src "ls180.v:3742.37-3742.102"
- cell $and $and$ls180.v:3742$205
+ attribute \src "ls180.v:3773.37-3773.102"
+ cell $and $and$ls180.v:3773$205
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3742$205_Y
+ connect \Y $and$ls180.v:3773$205_Y
end
- attribute \src "ls180.v:3742.108-3742.188"
- cell $and $and$ls180.v:3742$207
+ attribute \src "ls180.v:3773.108-3773.188"
+ cell $and $and$ls180.v:3773$207
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_ras
- connect \B $not$ls180.v:3742$206_Y
- connect \Y $and$ls180.v:3742$207_Y
+ connect \B $not$ls180.v:3773$206_Y
+ connect \Y $and$ls180.v:3773$207_Y
end
- attribute \src "ls180.v:3742.107-3742.231"
- cell $and $and$ls180.v:3742$209
+ attribute \src "ls180.v:3773.107-3773.231"
+ cell $and $and$ls180.v:3773$209
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3742$207_Y
- connect \B $not$ls180.v:3742$208_Y
- connect \Y $and$ls180.v:3742$209_Y
+ connect \A $and$ls180.v:3773$207_Y
+ connect \B $not$ls180.v:3773$208_Y
+ connect \Y $and$ls180.v:3773$209_Y
end
- attribute \src "ls180.v:3742.36-3742.232"
- cell $and $and$ls180.v:3742$210
+ attribute \src "ls180.v:3773.36-3773.232"
+ cell $and $and$ls180.v:3773$210
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3742$205_Y
- connect \B $and$ls180.v:3742$209_Y
- connect \Y $and$ls180.v:3742$210_Y
+ connect \A $and$ls180.v:3773$205_Y
+ connect \B $and$ls180.v:3773$209_Y
+ connect \Y $and$ls180.v:3773$210_Y
end
- attribute \src "ls180.v:3743.34-3743.85"
- cell $and $and$ls180.v:3743$211
+ attribute \src "ls180.v:3774.34-3774.85"
+ cell $and $and$ls180.v:3774$211
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_trrdcon_ready
connect \B \main_sdram_tfawcon_ready
- connect \Y $and$ls180.v:3743$211_Y
+ connect \Y $and$ls180.v:3774$211_Y
end
- attribute \src "ls180.v:3744.37-3744.102"
- cell $and $and$ls180.v:3744$212
+ attribute \src "ls180.v:3775.37-3775.102"
+ cell $and $and$ls180.v:3775$212
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3744$212_Y
+ connect \Y $and$ls180.v:3775$212_Y
end
- attribute \src "ls180.v:3744.36-3744.194"
- cell $and $and$ls180.v:3744$214
+ attribute \src "ls180.v:3775.36-3775.194"
+ cell $and $and$ls180.v:3775$214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3744$212_Y
- connect \B $or$ls180.v:3744$213_Y
- connect \Y $and$ls180.v:3744$214_Y
+ connect \A $and$ls180.v:3775$212_Y
+ connect \B $or$ls180.v:3775$213_Y
+ connect \Y $and$ls180.v:3775$214_Y
end
- attribute \src "ls180.v:3746.37-3746.102"
- cell $and $and$ls180.v:3746$215
+ attribute \src "ls180.v:3777.37-3777.102"
+ cell $and $and$ls180.v:3777$215
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3746$215_Y
+ connect \Y $and$ls180.v:3777$215_Y
end
- attribute \src "ls180.v:3746.36-3746.148"
- cell $and $and$ls180.v:3746$216
+ attribute \src "ls180.v:3777.36-3777.148"
+ cell $and $and$ls180.v:3777$216
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3746$215_Y
+ connect \A $and$ls180.v:3777$215_Y
connect \B \main_sdram_choose_req_cmd_payload_is_write
- connect \Y $and$ls180.v:3746$216_Y
+ connect \Y $and$ls180.v:3777$216_Y
end
- attribute \src "ls180.v:3747.40-3747.119"
- cell $and $and$ls180.v:3747$217
+ attribute \src "ls180.v:3778.40-3778.119"
+ cell $and $and$ls180.v:3778$217
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
connect \B \main_sdram_bankmachine0_cmd_payload_is_read
- connect \Y $and$ls180.v:3747$217_Y
+ connect \Y $and$ls180.v:3778$217_Y
end
- attribute \src "ls180.v:3747.124-3747.203"
- cell $and $and$ls180.v:3747$218
+ attribute \src "ls180.v:3778.124-3778.203"
+ cell $and $and$ls180.v:3778$218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
connect \B \main_sdram_bankmachine1_cmd_payload_is_read
- connect \Y $and$ls180.v:3747$218_Y
+ connect \Y $and$ls180.v:3778$218_Y
end
- attribute \src "ls180.v:3747.209-3747.288"
- cell $and $and$ls180.v:3747$220
+ attribute \src "ls180.v:3778.209-3778.288"
+ cell $and $and$ls180.v:3778$220
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
connect \B \main_sdram_bankmachine2_cmd_payload_is_read
- connect \Y $and$ls180.v:3747$220_Y
+ connect \Y $and$ls180.v:3778$220_Y
end
- attribute \src "ls180.v:3747.294-3747.373"
- cell $and $and$ls180.v:3747$222
+ attribute \src "ls180.v:3778.294-3778.373"
+ cell $and $and$ls180.v:3778$222
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
connect \B \main_sdram_bankmachine3_cmd_payload_is_read
- connect \Y $and$ls180.v:3747$222_Y
+ connect \Y $and$ls180.v:3778$222_Y
end
- attribute \src "ls180.v:3748.41-3748.121"
- cell $and $and$ls180.v:3748$224
+ attribute \src "ls180.v:3779.41-3779.121"
+ cell $and $and$ls180.v:3779$224
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
connect \B \main_sdram_bankmachine0_cmd_payload_is_write
- connect \Y $and$ls180.v:3748$224_Y
+ connect \Y $and$ls180.v:3779$224_Y
end
- attribute \src "ls180.v:3748.126-3748.206"
- cell $and $and$ls180.v:3748$225
+ attribute \src "ls180.v:3779.126-3779.206"
+ cell $and $and$ls180.v:3779$225
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
connect \B \main_sdram_bankmachine1_cmd_payload_is_write
- connect \Y $and$ls180.v:3748$225_Y
+ connect \Y $and$ls180.v:3779$225_Y
end
- attribute \src "ls180.v:3748.212-3748.292"
- cell $and $and$ls180.v:3748$227
+ attribute \src "ls180.v:3779.212-3779.292"
+ cell $and $and$ls180.v:3779$227
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
connect \B \main_sdram_bankmachine2_cmd_payload_is_write
- connect \Y $and$ls180.v:3748$227_Y
+ connect \Y $and$ls180.v:3779$227_Y
end
- attribute \src "ls180.v:3748.298-3748.378"
- cell $and $and$ls180.v:3748$229
+ attribute \src "ls180.v:3779.298-3779.378"
+ cell $and $and$ls180.v:3779$229
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
connect \B \main_sdram_bankmachine3_cmd_payload_is_write
- connect \Y $and$ls180.v:3748$229_Y
+ connect \Y $and$ls180.v:3779$229_Y
end
- attribute \src "ls180.v:3755.38-3755.111"
- cell $and $and$ls180.v:3755$233
+ attribute \src "ls180.v:3786.38-3786.111"
+ cell $and $and$ls180.v:3786$233
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_refresh_gnt
connect \B \main_sdram_bankmachine1_refresh_gnt
- connect \Y $and$ls180.v:3755$233_Y
+ connect \Y $and$ls180.v:3786$233_Y
end
- attribute \src "ls180.v:3755.37-3755.150"
- cell $and $and$ls180.v:3755$234
+ attribute \src "ls180.v:3786.37-3786.150"
+ cell $and $and$ls180.v:3786$234
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3755$233_Y
+ connect \A $and$ls180.v:3786$233_Y
connect \B \main_sdram_bankmachine2_refresh_gnt
- connect \Y $and$ls180.v:3755$234_Y
+ connect \Y $and$ls180.v:3786$234_Y
end
- attribute \src "ls180.v:3755.36-3755.189"
- cell $and $and$ls180.v:3755$235
+ attribute \src "ls180.v:3786.36-3786.189"
+ cell $and $and$ls180.v:3786$235
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3755$234_Y
+ connect \A $and$ls180.v:3786$234_Y
connect \B \main_sdram_bankmachine3_refresh_gnt
- connect \Y $and$ls180.v:3755$235_Y
+ connect \Y $and$ls180.v:3786$235_Y
end
- attribute \src "ls180.v:3761.77-3761.153"
- cell $and $and$ls180.v:3761$238
+ attribute \src "ls180.v:3792.77-3792.153"
+ cell $and $and$ls180.v:3792$238
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd
connect \B \main_sdram_choose_cmd_want_cmds
- connect \Y $and$ls180.v:3761$238_Y
+ connect \Y $and$ls180.v:3792$238_Y
end
- attribute \src "ls180.v:3761.162-3761.246"
- cell $and $and$ls180.v:3761$240
+ attribute \src "ls180.v:3792.162-3792.246"
+ cell $and $and$ls180.v:3792$240
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_ras
- connect \B $not$ls180.v:3761$239_Y
- connect \Y $and$ls180.v:3761$240_Y
+ connect \B $not$ls180.v:3792$239_Y
+ connect \Y $and$ls180.v:3792$240_Y
end
- attribute \src "ls180.v:3761.161-3761.291"
- cell $and $and$ls180.v:3761$242
+ attribute \src "ls180.v:3792.161-3792.291"
+ cell $and $and$ls180.v:3792$242
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3761$240_Y
- connect \B $not$ls180.v:3761$241_Y
- connect \Y $and$ls180.v:3761$242_Y
+ connect \A $and$ls180.v:3792$240_Y
+ connect \B $not$ls180.v:3792$241_Y
+ connect \Y $and$ls180.v:3792$242_Y
end
- attribute \src "ls180.v:3761.76-3761.333"
- cell $and $and$ls180.v:3761$245
+ attribute \src "ls180.v:3792.76-3792.333"
+ cell $and $and$ls180.v:3792$245
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3761$238_Y
- connect \B $or$ls180.v:3761$244_Y
- connect \Y $and$ls180.v:3761$245_Y
+ connect \A $and$ls180.v:3792$238_Y
+ connect \B $or$ls180.v:3792$244_Y
+ connect \Y $and$ls180.v:3792$245_Y
end
- attribute \src "ls180.v:3761.338-3761.505"
- cell $and $and$ls180.v:3761$248
+ attribute \src "ls180.v:3792.338-3792.505"
+ cell $and $and$ls180.v:3792$248
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3761$246_Y
- connect \B $eq$ls180.v:3761$247_Y
- connect \Y $and$ls180.v:3761$248_Y
+ connect \A $eq$ls180.v:3792$246_Y
+ connect \B $eq$ls180.v:3792$247_Y
+ connect \Y $and$ls180.v:3792$248_Y
end
- attribute \src "ls180.v:3761.38-3761.507"
- cell $and $and$ls180.v:3761$250
+ attribute \src "ls180.v:3792.38-3792.507"
+ cell $and $and$ls180.v:3792$250
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
- connect \B $or$ls180.v:3761$249_Y
- connect \Y $and$ls180.v:3761$250_Y
+ connect \B $or$ls180.v:3792$249_Y
+ connect \Y $and$ls180.v:3792$250_Y
end
- attribute \src "ls180.v:3762.77-3762.153"
- cell $and $and$ls180.v:3762$251
+ attribute \src "ls180.v:3793.77-3793.153"
+ cell $and $and$ls180.v:3793$251
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd
connect \B \main_sdram_choose_cmd_want_cmds
- connect \Y $and$ls180.v:3762$251_Y
+ connect \Y $and$ls180.v:3793$251_Y
end
- attribute \src "ls180.v:3762.162-3762.246"
- cell $and $and$ls180.v:3762$253
+ attribute \src "ls180.v:3793.162-3793.246"
+ cell $and $and$ls180.v:3793$253
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_ras
- connect \B $not$ls180.v:3762$252_Y
- connect \Y $and$ls180.v:3762$253_Y
+ connect \B $not$ls180.v:3793$252_Y
+ connect \Y $and$ls180.v:3793$253_Y
end
- attribute \src "ls180.v:3762.161-3762.291"
- cell $and $and$ls180.v:3762$255
+ attribute \src "ls180.v:3793.161-3793.291"
+ cell $and $and$ls180.v:3793$255
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3762$253_Y
- connect \B $not$ls180.v:3762$254_Y
- connect \Y $and$ls180.v:3762$255_Y
+ connect \A $and$ls180.v:3793$253_Y
+ connect \B $not$ls180.v:3793$254_Y
+ connect \Y $and$ls180.v:3793$255_Y
end
- attribute \src "ls180.v:3762.76-3762.333"
- cell $and $and$ls180.v:3762$258
+ attribute \src "ls180.v:3793.76-3793.333"
+ cell $and $and$ls180.v:3793$258
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3762$251_Y
- connect \B $or$ls180.v:3762$257_Y
- connect \Y $and$ls180.v:3762$258_Y
+ connect \A $and$ls180.v:3793$251_Y
+ connect \B $or$ls180.v:3793$257_Y
+ connect \Y $and$ls180.v:3793$258_Y
end
- attribute \src "ls180.v:3762.338-3762.505"
- cell $and $and$ls180.v:3762$261
+ attribute \src "ls180.v:3793.338-3793.505"
+ cell $and $and$ls180.v:3793$261
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3762$259_Y
- connect \B $eq$ls180.v:3762$260_Y
- connect \Y $and$ls180.v:3762$261_Y
+ connect \A $eq$ls180.v:3793$259_Y
+ connect \B $eq$ls180.v:3793$260_Y
+ connect \Y $and$ls180.v:3793$261_Y
end
- attribute \src "ls180.v:3762.38-3762.507"
- cell $and $and$ls180.v:3762$263
+ attribute \src "ls180.v:3793.38-3793.507"
+ cell $and $and$ls180.v:3793$263
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
- connect \B $or$ls180.v:3762$262_Y
- connect \Y $and$ls180.v:3762$263_Y
+ connect \B $or$ls180.v:3793$262_Y
+ connect \Y $and$ls180.v:3793$263_Y
end
- attribute \src "ls180.v:3763.77-3763.153"
- cell $and $and$ls180.v:3763$264
+ attribute \src "ls180.v:3794.77-3794.153"
+ cell $and $and$ls180.v:3794$264
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd
connect \B \main_sdram_choose_cmd_want_cmds
- connect \Y $and$ls180.v:3763$264_Y
+ connect \Y $and$ls180.v:3794$264_Y
end
- attribute \src "ls180.v:3763.162-3763.246"
- cell $and $and$ls180.v:3763$266
+ attribute \src "ls180.v:3794.162-3794.246"
+ cell $and $and$ls180.v:3794$266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_ras
- connect \B $not$ls180.v:3763$265_Y
- connect \Y $and$ls180.v:3763$266_Y
+ connect \B $not$ls180.v:3794$265_Y
+ connect \Y $and$ls180.v:3794$266_Y
end
- attribute \src "ls180.v:3763.161-3763.291"
- cell $and $and$ls180.v:3763$268
+ attribute \src "ls180.v:3794.161-3794.291"
+ cell $and $and$ls180.v:3794$268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3763$266_Y
- connect \B $not$ls180.v:3763$267_Y
- connect \Y $and$ls180.v:3763$268_Y
+ connect \A $and$ls180.v:3794$266_Y
+ connect \B $not$ls180.v:3794$267_Y
+ connect \Y $and$ls180.v:3794$268_Y
end
- attribute \src "ls180.v:3763.76-3763.333"
- cell $and $and$ls180.v:3763$271
+ attribute \src "ls180.v:3794.76-3794.333"
+ cell $and $and$ls180.v:3794$271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3763$264_Y
- connect \B $or$ls180.v:3763$270_Y
- connect \Y $and$ls180.v:3763$271_Y
+ connect \A $and$ls180.v:3794$264_Y
+ connect \B $or$ls180.v:3794$270_Y
+ connect \Y $and$ls180.v:3794$271_Y
end
- attribute \src "ls180.v:3763.338-3763.505"
- cell $and $and$ls180.v:3763$274
+ attribute \src "ls180.v:3794.338-3794.505"
+ cell $and $and$ls180.v:3794$274
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3763$272_Y
- connect \B $eq$ls180.v:3763$273_Y
- connect \Y $and$ls180.v:3763$274_Y
+ connect \A $eq$ls180.v:3794$272_Y
+ connect \B $eq$ls180.v:3794$273_Y
+ connect \Y $and$ls180.v:3794$274_Y
end
- attribute \src "ls180.v:3763.38-3763.507"
- cell $and $and$ls180.v:3763$276
+ attribute \src "ls180.v:3794.38-3794.507"
+ cell $and $and$ls180.v:3794$276
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
- connect \B $or$ls180.v:3763$275_Y
- connect \Y $and$ls180.v:3763$276_Y
+ connect \B $or$ls180.v:3794$275_Y
+ connect \Y $and$ls180.v:3794$276_Y
end
- attribute \src "ls180.v:3764.77-3764.153"
- cell $and $and$ls180.v:3764$277
+ attribute \src "ls180.v:3795.77-3795.153"
+ cell $and $and$ls180.v:3795$277
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd
connect \B \main_sdram_choose_cmd_want_cmds
- connect \Y $and$ls180.v:3764$277_Y
+ connect \Y $and$ls180.v:3795$277_Y
end
- attribute \src "ls180.v:3764.162-3764.246"
- cell $and $and$ls180.v:3764$279
+ attribute \src "ls180.v:3795.162-3795.246"
+ cell $and $and$ls180.v:3795$279
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_ras
- connect \B $not$ls180.v:3764$278_Y
- connect \Y $and$ls180.v:3764$279_Y
+ connect \B $not$ls180.v:3795$278_Y
+ connect \Y $and$ls180.v:3795$279_Y
end
- attribute \src "ls180.v:3764.161-3764.291"
- cell $and $and$ls180.v:3764$281
+ attribute \src "ls180.v:3795.161-3795.291"
+ cell $and $and$ls180.v:3795$281
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3764$279_Y
- connect \B $not$ls180.v:3764$280_Y
- connect \Y $and$ls180.v:3764$281_Y
+ connect \A $and$ls180.v:3795$279_Y
+ connect \B $not$ls180.v:3795$280_Y
+ connect \Y $and$ls180.v:3795$281_Y
end
- attribute \src "ls180.v:3764.76-3764.333"
- cell $and $and$ls180.v:3764$284
+ attribute \src "ls180.v:3795.76-3795.333"
+ cell $and $and$ls180.v:3795$284
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3764$277_Y
- connect \B $or$ls180.v:3764$283_Y
- connect \Y $and$ls180.v:3764$284_Y
+ connect \A $and$ls180.v:3795$277_Y
+ connect \B $or$ls180.v:3795$283_Y
+ connect \Y $and$ls180.v:3795$284_Y
end
- attribute \src "ls180.v:3764.338-3764.505"
- cell $and $and$ls180.v:3764$287
+ attribute \src "ls180.v:3795.338-3795.505"
+ cell $and $and$ls180.v:3795$287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3764$285_Y
- connect \B $eq$ls180.v:3764$286_Y
- connect \Y $and$ls180.v:3764$287_Y
+ connect \A $eq$ls180.v:3795$285_Y
+ connect \B $eq$ls180.v:3795$286_Y
+ connect \Y $and$ls180.v:3795$287_Y
end
- attribute \src "ls180.v:3764.38-3764.507"
- cell $and $and$ls180.v:3764$289
+ attribute \src "ls180.v:3795.38-3795.507"
+ cell $and $and$ls180.v:3795$289
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
- connect \B $or$ls180.v:3764$288_Y
- connect \Y $and$ls180.v:3764$289_Y
+ connect \B $or$ls180.v:3795$288_Y
+ connect \Y $and$ls180.v:3795$289_Y
end
- attribute \src "ls180.v:3794.77-3794.153"
- cell $and $and$ls180.v:3794$296
+ attribute \src "ls180.v:3825.77-3825.153"
+ cell $and $and$ls180.v:3825$296
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd
connect \B \main_sdram_choose_req_want_cmds
- connect \Y $and$ls180.v:3794$296_Y
+ connect \Y $and$ls180.v:3825$296_Y
end
- attribute \src "ls180.v:3794.162-3794.246"
- cell $and $and$ls180.v:3794$298
+ attribute \src "ls180.v:3825.162-3825.246"
+ cell $and $and$ls180.v:3825$298
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_ras
- connect \B $not$ls180.v:3794$297_Y
- connect \Y $and$ls180.v:3794$298_Y
+ connect \B $not$ls180.v:3825$297_Y
+ connect \Y $and$ls180.v:3825$298_Y
end
- attribute \src "ls180.v:3794.161-3794.291"
- cell $and $and$ls180.v:3794$300
+ attribute \src "ls180.v:3825.161-3825.291"
+ cell $and $and$ls180.v:3825$300
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3794$298_Y
- connect \B $not$ls180.v:3794$299_Y
- connect \Y $and$ls180.v:3794$300_Y
+ connect \A $and$ls180.v:3825$298_Y
+ connect \B $not$ls180.v:3825$299_Y
+ connect \Y $and$ls180.v:3825$300_Y
end
- attribute \src "ls180.v:3794.76-3794.333"
- cell $and $and$ls180.v:3794$303
+ attribute \src "ls180.v:3825.76-3825.333"
+ cell $and $and$ls180.v:3825$303
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3794$296_Y
- connect \B $or$ls180.v:3794$302_Y
- connect \Y $and$ls180.v:3794$303_Y
+ connect \A $and$ls180.v:3825$296_Y
+ connect \B $or$ls180.v:3825$302_Y
+ connect \Y $and$ls180.v:3825$303_Y
end
- attribute \src "ls180.v:3794.338-3794.505"
- cell $and $and$ls180.v:3794$306
+ attribute \src "ls180.v:3825.338-3825.505"
+ cell $and $and$ls180.v:3825$306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3794$304_Y
- connect \B $eq$ls180.v:3794$305_Y
- connect \Y $and$ls180.v:3794$306_Y
+ connect \A $eq$ls180.v:3825$304_Y
+ connect \B $eq$ls180.v:3825$305_Y
+ connect \Y $and$ls180.v:3825$306_Y
end
- attribute \src "ls180.v:3794.38-3794.507"
- cell $and $and$ls180.v:3794$308
+ attribute \src "ls180.v:3825.38-3825.507"
+ cell $and $and$ls180.v:3825$308
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_valid
- connect \B $or$ls180.v:3794$307_Y
- connect \Y $and$ls180.v:3794$308_Y
+ connect \B $or$ls180.v:3825$307_Y
+ connect \Y $and$ls180.v:3825$308_Y
end
- attribute \src "ls180.v:3795.77-3795.153"
- cell $and $and$ls180.v:3795$309
+ attribute \src "ls180.v:3826.77-3826.153"
+ cell $and $and$ls180.v:3826$309
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd
connect \B \main_sdram_choose_req_want_cmds
- connect \Y $and$ls180.v:3795$309_Y
+ connect \Y $and$ls180.v:3826$309_Y
end
- attribute \src "ls180.v:3795.162-3795.246"
- cell $and $and$ls180.v:3795$311
+ attribute \src "ls180.v:3826.162-3826.246"
+ cell $and $and$ls180.v:3826$311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_ras
- connect \B $not$ls180.v:3795$310_Y
- connect \Y $and$ls180.v:3795$311_Y
+ connect \B $not$ls180.v:3826$310_Y
+ connect \Y $and$ls180.v:3826$311_Y
end
- attribute \src "ls180.v:3795.161-3795.291"
- cell $and $and$ls180.v:3795$313
+ attribute \src "ls180.v:3826.161-3826.291"
+ cell $and $and$ls180.v:3826$313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3795$311_Y
- connect \B $not$ls180.v:3795$312_Y
- connect \Y $and$ls180.v:3795$313_Y
+ connect \A $and$ls180.v:3826$311_Y
+ connect \B $not$ls180.v:3826$312_Y
+ connect \Y $and$ls180.v:3826$313_Y
end
- attribute \src "ls180.v:3795.76-3795.333"
- cell $and $and$ls180.v:3795$316
+ attribute \src "ls180.v:3826.76-3826.333"
+ cell $and $and$ls180.v:3826$316
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3795$309_Y
- connect \B $or$ls180.v:3795$315_Y
- connect \Y $and$ls180.v:3795$316_Y
+ connect \A $and$ls180.v:3826$309_Y
+ connect \B $or$ls180.v:3826$315_Y
+ connect \Y $and$ls180.v:3826$316_Y
end
- attribute \src "ls180.v:3795.338-3795.505"
- cell $and $and$ls180.v:3795$319
+ attribute \src "ls180.v:3826.338-3826.505"
+ cell $and $and$ls180.v:3826$319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3795$317_Y
- connect \B $eq$ls180.v:3795$318_Y
- connect \Y $and$ls180.v:3795$319_Y
+ connect \A $eq$ls180.v:3826$317_Y
+ connect \B $eq$ls180.v:3826$318_Y
+ connect \Y $and$ls180.v:3826$319_Y
end
- attribute \src "ls180.v:3795.38-3795.507"
- cell $and $and$ls180.v:3795$321
+ attribute \src "ls180.v:3826.38-3826.507"
+ cell $and $and$ls180.v:3826$321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_valid
- connect \B $or$ls180.v:3795$320_Y
- connect \Y $and$ls180.v:3795$321_Y
+ connect \B $or$ls180.v:3826$320_Y
+ connect \Y $and$ls180.v:3826$321_Y
end
- attribute \src "ls180.v:3796.77-3796.153"
- cell $and $and$ls180.v:3796$322
+ attribute \src "ls180.v:3827.77-3827.153"
+ cell $and $and$ls180.v:3827$322
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd
connect \B \main_sdram_choose_req_want_cmds
- connect \Y $and$ls180.v:3796$322_Y
+ connect \Y $and$ls180.v:3827$322_Y
end
- attribute \src "ls180.v:3796.162-3796.246"
- cell $and $and$ls180.v:3796$324
+ attribute \src "ls180.v:3827.162-3827.246"
+ cell $and $and$ls180.v:3827$324
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_ras
- connect \B $not$ls180.v:3796$323_Y
- connect \Y $and$ls180.v:3796$324_Y
+ connect \B $not$ls180.v:3827$323_Y
+ connect \Y $and$ls180.v:3827$324_Y
end
- attribute \src "ls180.v:3796.161-3796.291"
- cell $and $and$ls180.v:3796$326
+ attribute \src "ls180.v:3827.161-3827.291"
+ cell $and $and$ls180.v:3827$326
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3796$324_Y
- connect \B $not$ls180.v:3796$325_Y
- connect \Y $and$ls180.v:3796$326_Y
+ connect \A $and$ls180.v:3827$324_Y
+ connect \B $not$ls180.v:3827$325_Y
+ connect \Y $and$ls180.v:3827$326_Y
end
- attribute \src "ls180.v:3796.76-3796.333"
- cell $and $and$ls180.v:3796$329
+ attribute \src "ls180.v:3827.76-3827.333"
+ cell $and $and$ls180.v:3827$329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3796$322_Y
- connect \B $or$ls180.v:3796$328_Y
- connect \Y $and$ls180.v:3796$329_Y
+ connect \A $and$ls180.v:3827$322_Y
+ connect \B $or$ls180.v:3827$328_Y
+ connect \Y $and$ls180.v:3827$329_Y
end
- attribute \src "ls180.v:3796.338-3796.505"
- cell $and $and$ls180.v:3796$332
+ attribute \src "ls180.v:3827.338-3827.505"
+ cell $and $and$ls180.v:3827$332
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3796$330_Y
- connect \B $eq$ls180.v:3796$331_Y
- connect \Y $and$ls180.v:3796$332_Y
+ connect \A $eq$ls180.v:3827$330_Y
+ connect \B $eq$ls180.v:3827$331_Y
+ connect \Y $and$ls180.v:3827$332_Y
end
- attribute \src "ls180.v:3796.38-3796.507"
- cell $and $and$ls180.v:3796$334
+ attribute \src "ls180.v:3827.38-3827.507"
+ cell $and $and$ls180.v:3827$334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_valid
- connect \B $or$ls180.v:3796$333_Y
- connect \Y $and$ls180.v:3796$334_Y
+ connect \B $or$ls180.v:3827$333_Y
+ connect \Y $and$ls180.v:3827$334_Y
end
- attribute \src "ls180.v:3797.77-3797.153"
- cell $and $and$ls180.v:3797$335
+ attribute \src "ls180.v:3828.77-3828.153"
+ cell $and $and$ls180.v:3828$335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd
connect \B \main_sdram_choose_req_want_cmds
- connect \Y $and$ls180.v:3797$335_Y
+ connect \Y $and$ls180.v:3828$335_Y
end
- attribute \src "ls180.v:3797.162-3797.246"
- cell $and $and$ls180.v:3797$337
+ attribute \src "ls180.v:3828.162-3828.246"
+ cell $and $and$ls180.v:3828$337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_ras
- connect \B $not$ls180.v:3797$336_Y
- connect \Y $and$ls180.v:3797$337_Y
+ connect \B $not$ls180.v:3828$336_Y
+ connect \Y $and$ls180.v:3828$337_Y
end
- attribute \src "ls180.v:3797.161-3797.291"
- cell $and $and$ls180.v:3797$339
+ attribute \src "ls180.v:3828.161-3828.291"
+ cell $and $and$ls180.v:3828$339
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3797$337_Y
- connect \B $not$ls180.v:3797$338_Y
- connect \Y $and$ls180.v:3797$339_Y
+ connect \A $and$ls180.v:3828$337_Y
+ connect \B $not$ls180.v:3828$338_Y
+ connect \Y $and$ls180.v:3828$339_Y
end
- attribute \src "ls180.v:3797.76-3797.333"
- cell $and $and$ls180.v:3797$342
+ attribute \src "ls180.v:3828.76-3828.333"
+ cell $and $and$ls180.v:3828$342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3797$335_Y
- connect \B $or$ls180.v:3797$341_Y
- connect \Y $and$ls180.v:3797$342_Y
+ connect \A $and$ls180.v:3828$335_Y
+ connect \B $or$ls180.v:3828$341_Y
+ connect \Y $and$ls180.v:3828$342_Y
end
- attribute \src "ls180.v:3797.338-3797.505"
- cell $and $and$ls180.v:3797$345
+ attribute \src "ls180.v:3828.338-3828.505"
+ cell $and $and$ls180.v:3828$345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3797$343_Y
- connect \B $eq$ls180.v:3797$344_Y
- connect \Y $and$ls180.v:3797$345_Y
+ connect \A $eq$ls180.v:3828$343_Y
+ connect \B $eq$ls180.v:3828$344_Y
+ connect \Y $and$ls180.v:3828$345_Y
end
- attribute \src "ls180.v:3797.38-3797.507"
- cell $and $and$ls180.v:3797$347
+ attribute \src "ls180.v:3828.38-3828.507"
+ cell $and $and$ls180.v:3828$347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_valid
- connect \B $or$ls180.v:3797$346_Y
- connect \Y $and$ls180.v:3797$347_Y
+ connect \B $or$ls180.v:3828$346_Y
+ connect \Y $and$ls180.v:3828$347_Y
end
- attribute \src "ls180.v:3826.8-3826.73"
- cell $and $and$ls180.v:3826$352
+ attribute \src "ls180.v:3857.8-3857.73"
+ cell $and $and$ls180.v:3857$352
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_cmd_valid
connect \B \main_sdram_choose_cmd_cmd_ready
- connect \Y $and$ls180.v:3826$352_Y
+ connect \Y $and$ls180.v:3857$352_Y
end
- attribute \src "ls180.v:3826.7-3826.114"
- cell $and $and$ls180.v:3826$354
+ attribute \src "ls180.v:3857.7-3857.114"
+ cell $and $and$ls180.v:3857$354
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3826$352_Y
- connect \B $eq$ls180.v:3826$353_Y
- connect \Y $and$ls180.v:3826$354_Y
+ connect \A $and$ls180.v:3857$352_Y
+ connect \B $eq$ls180.v:3857$353_Y
+ connect \Y $and$ls180.v:3857$354_Y
end
- attribute \src "ls180.v:3829.8-3829.73"
- cell $and $and$ls180.v:3829$355
+ attribute \src "ls180.v:3860.8-3860.73"
+ cell $and $and$ls180.v:3860$355
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3829$355_Y
+ connect \Y $and$ls180.v:3860$355_Y
end
- attribute \src "ls180.v:3829.7-3829.114"
- cell $and $and$ls180.v:3829$357
+ attribute \src "ls180.v:3860.7-3860.114"
+ cell $and $and$ls180.v:3860$357
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3829$355_Y
- connect \B $eq$ls180.v:3829$356_Y
- connect \Y $and$ls180.v:3829$357_Y
+ connect \A $and$ls180.v:3860$355_Y
+ connect \B $eq$ls180.v:3860$356_Y
+ connect \Y $and$ls180.v:3860$357_Y
end
- attribute \src "ls180.v:3835.8-3835.73"
- cell $and $and$ls180.v:3835$359
+ attribute \src "ls180.v:3866.8-3866.73"
+ cell $and $and$ls180.v:3866$359
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_cmd_valid
connect \B \main_sdram_choose_cmd_cmd_ready
- connect \Y $and$ls180.v:3835$359_Y
+ connect \Y $and$ls180.v:3866$359_Y
end
- attribute \src "ls180.v:3835.7-3835.114"
- cell $and $and$ls180.v:3835$361
+ attribute \src "ls180.v:3866.7-3866.114"
+ cell $and $and$ls180.v:3866$361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3835$359_Y
- connect \B $eq$ls180.v:3835$360_Y
- connect \Y $and$ls180.v:3835$361_Y
+ connect \A $and$ls180.v:3866$359_Y
+ connect \B $eq$ls180.v:3866$360_Y
+ connect \Y $and$ls180.v:3866$361_Y
end
- attribute \src "ls180.v:3838.8-3838.73"
- cell $and $and$ls180.v:3838$362
+ attribute \src "ls180.v:3869.8-3869.73"
+ cell $and $and$ls180.v:3869$362
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3838$362_Y
+ connect \Y $and$ls180.v:3869$362_Y
end
- attribute \src "ls180.v:3838.7-3838.114"
- cell $and $and$ls180.v:3838$364
+ attribute \src "ls180.v:3869.7-3869.114"
+ cell $and $and$ls180.v:3869$364
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3838$362_Y
- connect \B $eq$ls180.v:3838$363_Y
- connect \Y $and$ls180.v:3838$364_Y
+ connect \A $and$ls180.v:3869$362_Y
+ connect \B $eq$ls180.v:3869$363_Y
+ connect \Y $and$ls180.v:3869$364_Y
end
- attribute \src "ls180.v:3844.8-3844.73"
- cell $and $and$ls180.v:3844$366
+ attribute \src "ls180.v:3875.8-3875.73"
+ cell $and $and$ls180.v:3875$366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_cmd_valid
connect \B \main_sdram_choose_cmd_cmd_ready
- connect \Y $and$ls180.v:3844$366_Y
+ connect \Y $and$ls180.v:3875$366_Y
end
- attribute \src "ls180.v:3844.7-3844.114"
- cell $and $and$ls180.v:3844$368
+ attribute \src "ls180.v:3875.7-3875.114"
+ cell $and $and$ls180.v:3875$368
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3844$366_Y
- connect \B $eq$ls180.v:3844$367_Y
- connect \Y $and$ls180.v:3844$368_Y
+ connect \A $and$ls180.v:3875$366_Y
+ connect \B $eq$ls180.v:3875$367_Y
+ connect \Y $and$ls180.v:3875$368_Y
end
- attribute \src "ls180.v:3847.8-3847.73"
- cell $and $and$ls180.v:3847$369
+ attribute \src "ls180.v:3878.8-3878.73"
+ cell $and $and$ls180.v:3878$369
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3847$369_Y
+ connect \Y $and$ls180.v:3878$369_Y
end
- attribute \src "ls180.v:3847.7-3847.114"
- cell $and $and$ls180.v:3847$371
+ attribute \src "ls180.v:3878.7-3878.114"
+ cell $and $and$ls180.v:3878$371
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3847$369_Y
- connect \B $eq$ls180.v:3847$370_Y
- connect \Y $and$ls180.v:3847$371_Y
+ connect \A $and$ls180.v:3878$369_Y
+ connect \B $eq$ls180.v:3878$370_Y
+ connect \Y $and$ls180.v:3878$371_Y
end
- attribute \src "ls180.v:3853.8-3853.73"
- cell $and $and$ls180.v:3853$373
+ attribute \src "ls180.v:3884.8-3884.73"
+ cell $and $and$ls180.v:3884$373
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_cmd_valid
connect \B \main_sdram_choose_cmd_cmd_ready
- connect \Y $and$ls180.v:3853$373_Y
+ connect \Y $and$ls180.v:3884$373_Y
end
- attribute \src "ls180.v:3853.7-3853.114"
- cell $and $and$ls180.v:3853$375
+ attribute \src "ls180.v:3884.7-3884.114"
+ cell $and $and$ls180.v:3884$375
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3853$373_Y
- connect \B $eq$ls180.v:3853$374_Y
- connect \Y $and$ls180.v:3853$375_Y
+ connect \A $and$ls180.v:3884$373_Y
+ connect \B $eq$ls180.v:3884$374_Y
+ connect \Y $and$ls180.v:3884$375_Y
end
- attribute \src "ls180.v:3856.8-3856.73"
- cell $and $and$ls180.v:3856$376
+ attribute \src "ls180.v:3887.8-3887.73"
+ cell $and $and$ls180.v:3887$376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3856$376_Y
+ connect \Y $and$ls180.v:3887$376_Y
end
- attribute \src "ls180.v:3856.7-3856.114"
- cell $and $and$ls180.v:3856$378
+ attribute \src "ls180.v:3887.7-3887.114"
+ cell $and $and$ls180.v:3887$378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3856$376_Y
- connect \B $eq$ls180.v:3856$377_Y
- connect \Y $and$ls180.v:3856$378_Y
+ connect \A $and$ls180.v:3887$376_Y
+ connect \B $eq$ls180.v:3887$377_Y
+ connect \Y $and$ls180.v:3887$378_Y
end
- attribute \src "ls180.v:3881.71-3881.151"
- cell $and $and$ls180.v:3881$383
+ attribute \src "ls180.v:3912.71-3912.151"
+ cell $and $and$ls180.v:3912$383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_ras
- connect \B $not$ls180.v:3881$382_Y
- connect \Y $and$ls180.v:3881$383_Y
+ connect \B $not$ls180.v:3912$382_Y
+ connect \Y $and$ls180.v:3912$383_Y
end
- attribute \src "ls180.v:3881.70-3881.194"
- cell $and $and$ls180.v:3881$385
+ attribute \src "ls180.v:3912.70-3912.194"
+ cell $and $and$ls180.v:3912$385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3881$383_Y
- connect \B $not$ls180.v:3881$384_Y
- connect \Y $and$ls180.v:3881$385_Y
+ connect \A $and$ls180.v:3912$383_Y
+ connect \B $not$ls180.v:3912$384_Y
+ connect \Y $and$ls180.v:3912$385_Y
end
- attribute \src "ls180.v:3881.41-3881.222"
- cell $and $and$ls180.v:3881$388
+ attribute \src "ls180.v:3912.41-3912.222"
+ cell $and $and$ls180.v:3912$388
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_cas_allowed
- connect \B $or$ls180.v:3881$387_Y
- connect \Y $and$ls180.v:3881$388_Y
+ connect \B $or$ls180.v:3912$387_Y
+ connect \Y $and$ls180.v:3912$388_Y
end
- attribute \src "ls180.v:3919.71-3919.151"
- cell $and $and$ls180.v:3919$392
+ attribute \src "ls180.v:3950.71-3950.151"
+ cell $and $and$ls180.v:3950$392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_ras
- connect \B $not$ls180.v:3919$391_Y
- connect \Y $and$ls180.v:3919$392_Y
+ connect \B $not$ls180.v:3950$391_Y
+ connect \Y $and$ls180.v:3950$392_Y
end
- attribute \src "ls180.v:3919.70-3919.194"
- cell $and $and$ls180.v:3919$394
+ attribute \src "ls180.v:3950.70-3950.194"
+ cell $and $and$ls180.v:3950$394
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3919$392_Y
- connect \B $not$ls180.v:3919$393_Y
- connect \Y $and$ls180.v:3919$394_Y
+ connect \A $and$ls180.v:3950$392_Y
+ connect \B $not$ls180.v:3950$393_Y
+ connect \Y $and$ls180.v:3950$394_Y
end
- attribute \src "ls180.v:3919.41-3919.222"
- cell $and $and$ls180.v:3919$397
+ attribute \src "ls180.v:3950.41-3950.222"
+ cell $and $and$ls180.v:3950$397
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_cas_allowed
- connect \B $or$ls180.v:3919$396_Y
- connect \Y $and$ls180.v:3919$397_Y
+ connect \B $or$ls180.v:3950$396_Y
+ connect \Y $and$ls180.v:3950$397_Y
end
- attribute \src "ls180.v:3937.110-3937.179"
- cell $and $and$ls180.v:3937$402
+ attribute \src "ls180.v:3968.110-3968.179"
+ cell $and $and$ls180.v:3968$402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:3937$401_Y
- connect \Y $and$ls180.v:3937$402_Y
+ connect \B $eq$ls180.v:3968$401_Y
+ connect \Y $and$ls180.v:3968$402_Y
end
- attribute \src "ls180.v:3937.185-3937.254"
- cell $and $and$ls180.v:3937$405
+ attribute \src "ls180.v:3968.185-3968.254"
+ cell $and $and$ls180.v:3968$405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:3937$404_Y
- connect \Y $and$ls180.v:3937$405_Y
+ connect \B $eq$ls180.v:3968$404_Y
+ connect \Y $and$ls180.v:3968$405_Y
end
- attribute \src "ls180.v:3937.260-3937.329"
- cell $and $and$ls180.v:3937$408
+ attribute \src "ls180.v:3968.260-3968.329"
+ cell $and $and$ls180.v:3968$408
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:3937$407_Y
- connect \Y $and$ls180.v:3937$408_Y
+ connect \B $eq$ls180.v:3968$407_Y
+ connect \Y $and$ls180.v:3968$408_Y
end
- attribute \src "ls180.v:3937.41-3937.332"
- cell $and $and$ls180.v:3937$411
+ attribute \src "ls180.v:3968.41-3968.332"
+ cell $and $and$ls180.v:3968$411
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3937$400_Y
- connect \B $not$ls180.v:3937$410_Y
- connect \Y $and$ls180.v:3937$411_Y
+ connect \A $eq$ls180.v:3968$400_Y
+ connect \B $not$ls180.v:3968$410_Y
+ connect \Y $and$ls180.v:3968$411_Y
end
- attribute \src "ls180.v:3937.40-3937.355"
- cell $and $and$ls180.v:3937$412
+ attribute \src "ls180.v:3968.40-3968.355"
+ cell $and $and$ls180.v:3968$412
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3937$411_Y
+ connect \A $and$ls180.v:3968$411_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:3937$412_Y
+ connect \Y $and$ls180.v:3968$412_Y
end
- attribute \src "ls180.v:3938.34-3938.106"
- cell $and $and$ls180.v:3938$415
+ attribute \src "ls180.v:3969.34-3969.106"
+ cell $and $and$ls180.v:3969$415
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3938$413_Y
- connect \B $not$ls180.v:3938$414_Y
- connect \Y $and$ls180.v:3938$415_Y
+ connect \A $not$ls180.v:3969$413_Y
+ connect \B $not$ls180.v:3969$414_Y
+ connect \Y $and$ls180.v:3969$415_Y
end
- attribute \src "ls180.v:3942.110-3942.179"
- cell $and $and$ls180.v:3942$418
+ attribute \src "ls180.v:3973.110-3973.179"
+ cell $and $and$ls180.v:3973$418
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:3942$417_Y
- connect \Y $and$ls180.v:3942$418_Y
+ connect \B $eq$ls180.v:3973$417_Y
+ connect \Y $and$ls180.v:3973$418_Y
end
- attribute \src "ls180.v:3942.185-3942.254"
- cell $and $and$ls180.v:3942$421
+ attribute \src "ls180.v:3973.185-3973.254"
+ cell $and $and$ls180.v:3973$421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:3942$420_Y
- connect \Y $and$ls180.v:3942$421_Y
+ connect \B $eq$ls180.v:3973$420_Y
+ connect \Y $and$ls180.v:3973$421_Y
end
- attribute \src "ls180.v:3942.260-3942.329"
- cell $and $and$ls180.v:3942$424
+ attribute \src "ls180.v:3973.260-3973.329"
+ cell $and $and$ls180.v:3973$424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:3942$423_Y
- connect \Y $and$ls180.v:3942$424_Y
+ connect \B $eq$ls180.v:3973$423_Y
+ connect \Y $and$ls180.v:3973$424_Y
end
- attribute \src "ls180.v:3942.41-3942.332"
- cell $and $and$ls180.v:3942$427
+ attribute \src "ls180.v:3973.41-3973.332"
+ cell $and $and$ls180.v:3973$427
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3942$416_Y
- connect \B $not$ls180.v:3942$426_Y
- connect \Y $and$ls180.v:3942$427_Y
+ connect \A $eq$ls180.v:3973$416_Y
+ connect \B $not$ls180.v:3973$426_Y
+ connect \Y $and$ls180.v:3973$427_Y
end
- attribute \src "ls180.v:3942.40-3942.355"
- cell $and $and$ls180.v:3942$428
+ attribute \src "ls180.v:3973.40-3973.355"
+ cell $and $and$ls180.v:3973$428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3942$427_Y
+ connect \A $and$ls180.v:3973$427_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:3942$428_Y
+ connect \Y $and$ls180.v:3973$428_Y
end
- attribute \src "ls180.v:3943.34-3943.106"
- cell $and $and$ls180.v:3943$431
+ attribute \src "ls180.v:3974.34-3974.106"
+ cell $and $and$ls180.v:3974$431
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3943$429_Y
- connect \B $not$ls180.v:3943$430_Y
- connect \Y $and$ls180.v:3943$431_Y
+ connect \A $not$ls180.v:3974$429_Y
+ connect \B $not$ls180.v:3974$430_Y
+ connect \Y $and$ls180.v:3974$431_Y
end
- attribute \src "ls180.v:3947.110-3947.179"
- cell $and $and$ls180.v:3947$434
+ attribute \src "ls180.v:3978.110-3978.179"
+ cell $and $and$ls180.v:3978$434
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:3947$433_Y
- connect \Y $and$ls180.v:3947$434_Y
+ connect \B $eq$ls180.v:3978$433_Y
+ connect \Y $and$ls180.v:3978$434_Y
end
- attribute \src "ls180.v:3947.185-3947.254"
- cell $and $and$ls180.v:3947$437
+ attribute \src "ls180.v:3978.185-3978.254"
+ cell $and $and$ls180.v:3978$437
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:3947$436_Y
- connect \Y $and$ls180.v:3947$437_Y
+ connect \B $eq$ls180.v:3978$436_Y
+ connect \Y $and$ls180.v:3978$437_Y
end
- attribute \src "ls180.v:3947.260-3947.329"
- cell $and $and$ls180.v:3947$440
+ attribute \src "ls180.v:3978.260-3978.329"
+ cell $and $and$ls180.v:3978$440
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:3947$439_Y
- connect \Y $and$ls180.v:3947$440_Y
+ connect \B $eq$ls180.v:3978$439_Y
+ connect \Y $and$ls180.v:3978$440_Y
end
- attribute \src "ls180.v:3947.41-3947.332"
- cell $and $and$ls180.v:3947$443
+ attribute \src "ls180.v:3978.41-3978.332"
+ cell $and $and$ls180.v:3978$443
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3947$432_Y
- connect \B $not$ls180.v:3947$442_Y
- connect \Y $and$ls180.v:3947$443_Y
+ connect \A $eq$ls180.v:3978$432_Y
+ connect \B $not$ls180.v:3978$442_Y
+ connect \Y $and$ls180.v:3978$443_Y
end
- attribute \src "ls180.v:3947.40-3947.355"
- cell $and $and$ls180.v:3947$444
+ attribute \src "ls180.v:3978.40-3978.355"
+ cell $and $and$ls180.v:3978$444
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3947$443_Y
+ connect \A $and$ls180.v:3978$443_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:3947$444_Y
+ connect \Y $and$ls180.v:3978$444_Y
end
- attribute \src "ls180.v:3948.34-3948.106"
- cell $and $and$ls180.v:3948$447
+ attribute \src "ls180.v:3979.34-3979.106"
+ cell $and $and$ls180.v:3979$447
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3948$445_Y
- connect \B $not$ls180.v:3948$446_Y
- connect \Y $and$ls180.v:3948$447_Y
+ connect \A $not$ls180.v:3979$445_Y
+ connect \B $not$ls180.v:3979$446_Y
+ connect \Y $and$ls180.v:3979$447_Y
end
- attribute \src "ls180.v:3952.110-3952.179"
- cell $and $and$ls180.v:3952$450
+ attribute \src "ls180.v:3983.110-3983.179"
+ cell $and $and$ls180.v:3983$450
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:3952$449_Y
- connect \Y $and$ls180.v:3952$450_Y
+ connect \B $eq$ls180.v:3983$449_Y
+ connect \Y $and$ls180.v:3983$450_Y
end
- attribute \src "ls180.v:3952.185-3952.254"
- cell $and $and$ls180.v:3952$453
+ attribute \src "ls180.v:3983.185-3983.254"
+ cell $and $and$ls180.v:3983$453
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:3952$452_Y
- connect \Y $and$ls180.v:3952$453_Y
+ connect \B $eq$ls180.v:3983$452_Y
+ connect \Y $and$ls180.v:3983$453_Y
end
- attribute \src "ls180.v:3952.260-3952.329"
- cell $and $and$ls180.v:3952$456
+ attribute \src "ls180.v:3983.260-3983.329"
+ cell $and $and$ls180.v:3983$456
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:3952$455_Y
- connect \Y $and$ls180.v:3952$456_Y
+ connect \B $eq$ls180.v:3983$455_Y
+ connect \Y $and$ls180.v:3983$456_Y
end
- attribute \src "ls180.v:3952.41-3952.332"
- cell $and $and$ls180.v:3952$459
+ attribute \src "ls180.v:3983.41-3983.332"
+ cell $and $and$ls180.v:3983$459
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3952$448_Y
- connect \B $not$ls180.v:3952$458_Y
- connect \Y $and$ls180.v:3952$459_Y
+ connect \A $eq$ls180.v:3983$448_Y
+ connect \B $not$ls180.v:3983$458_Y
+ connect \Y $and$ls180.v:3983$459_Y
end
- attribute \src "ls180.v:3952.40-3952.355"
- cell $and $and$ls180.v:3952$460
+ attribute \src "ls180.v:3983.40-3983.355"
+ cell $and $and$ls180.v:3983$460
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3952$459_Y
+ connect \A $and$ls180.v:3983$459_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:3952$460_Y
+ connect \Y $and$ls180.v:3983$460_Y
end
- attribute \src "ls180.v:3953.34-3953.106"
- cell $and $and$ls180.v:3953$463
+ attribute \src "ls180.v:3984.34-3984.106"
+ cell $and $and$ls180.v:3984$463
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3953$461_Y
- connect \B $not$ls180.v:3953$462_Y
- connect \Y $and$ls180.v:3953$463_Y
+ connect \A $not$ls180.v:3984$461_Y
+ connect \B $not$ls180.v:3984$462_Y
+ connect \Y $and$ls180.v:3984$463_Y
end
- attribute \src "ls180.v:3957.151-3957.220"
- cell $and $and$ls180.v:3957$467
+ attribute \src "ls180.v:3988.151-3988.220"
+ cell $and $and$ls180.v:3988$467
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:3957$466_Y
- connect \Y $and$ls180.v:3957$467_Y
+ connect \B $eq$ls180.v:3988$466_Y
+ connect \Y $and$ls180.v:3988$467_Y
end
- attribute \src "ls180.v:3957.226-3957.295"
- cell $and $and$ls180.v:3957$470
+ attribute \src "ls180.v:3988.226-3988.295"
+ cell $and $and$ls180.v:3988$470
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:3957$469_Y
- connect \Y $and$ls180.v:3957$470_Y
+ connect \B $eq$ls180.v:3988$469_Y
+ connect \Y $and$ls180.v:3988$470_Y
end
- attribute \src "ls180.v:3957.301-3957.370"
- cell $and $and$ls180.v:3957$473
+ attribute \src "ls180.v:3988.301-3988.370"
+ cell $and $and$ls180.v:3988$473
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:3957$472_Y
- connect \Y $and$ls180.v:3957$473_Y
+ connect \B $eq$ls180.v:3988$472_Y
+ connect \Y $and$ls180.v:3988$473_Y
end
- attribute \src "ls180.v:3957.82-3957.373"
- cell $and $and$ls180.v:3957$476
+ attribute \src "ls180.v:3988.82-3988.373"
+ cell $and $and$ls180.v:3988$476
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3957$465_Y
- connect \B $not$ls180.v:3957$475_Y
- connect \Y $and$ls180.v:3957$476_Y
+ connect \A $eq$ls180.v:3988$465_Y
+ connect \B $not$ls180.v:3988$475_Y
+ connect \Y $and$ls180.v:3988$476_Y
end
- attribute \src "ls180.v:3957.43-3957.374"
- cell $and $and$ls180.v:3957$477
+ attribute \src "ls180.v:3988.43-3988.374"
+ cell $and $and$ls180.v:3988$477
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3957$464_Y
- connect \B $and$ls180.v:3957$476_Y
- connect \Y $and$ls180.v:3957$477_Y
+ connect \A $eq$ls180.v:3988$464_Y
+ connect \B $and$ls180.v:3988$476_Y
+ connect \Y $and$ls180.v:3988$477_Y
end
- attribute \src "ls180.v:3957.42-3957.410"
- cell $and $and$ls180.v:3957$478
+ attribute \src "ls180.v:3988.42-3988.410"
+ cell $and $and$ls180.v:3988$478
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3957$477_Y
+ connect \A $and$ls180.v:3988$477_Y
connect \B \main_sdram_interface_bank0_ready
- connect \Y $and$ls180.v:3957$478_Y
+ connect \Y $and$ls180.v:3988$478_Y
end
- attribute \src "ls180.v:3957.525-3957.594"
- cell $and $and$ls180.v:3957$483
+ attribute \src "ls180.v:3988.525-3988.594"
+ cell $and $and$ls180.v:3988$483
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:3957$482_Y
- connect \Y $and$ls180.v:3957$483_Y
+ connect \B $eq$ls180.v:3988$482_Y
+ connect \Y $and$ls180.v:3988$483_Y
end
- attribute \src "ls180.v:3957.600-3957.669"
- cell $and $and$ls180.v:3957$486
+ attribute \src "ls180.v:3988.600-3988.669"
+ cell $and $and$ls180.v:3988$486
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:3957$485_Y
- connect \Y $and$ls180.v:3957$486_Y
+ connect \B $eq$ls180.v:3988$485_Y
+ connect \Y $and$ls180.v:3988$486_Y
end
- attribute \src "ls180.v:3957.675-3957.744"
- cell $and $and$ls180.v:3957$489
+ attribute \src "ls180.v:3988.675-3988.744"
+ cell $and $and$ls180.v:3988$489
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:3957$488_Y
- connect \Y $and$ls180.v:3957$489_Y
+ connect \B $eq$ls180.v:3988$488_Y
+ connect \Y $and$ls180.v:3988$489_Y
end
- attribute \src "ls180.v:3957.456-3957.747"
- cell $and $and$ls180.v:3957$492
+ attribute \src "ls180.v:3988.456-3988.747"
+ cell $and $and$ls180.v:3988$492
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3957$481_Y
- connect \B $not$ls180.v:3957$491_Y
- connect \Y $and$ls180.v:3957$492_Y
+ connect \A $eq$ls180.v:3988$481_Y
+ connect \B $not$ls180.v:3988$491_Y
+ connect \Y $and$ls180.v:3988$492_Y
end
- attribute \src "ls180.v:3957.417-3957.748"
- cell $and $and$ls180.v:3957$493
+ attribute \src "ls180.v:3988.417-3988.748"
+ cell $and $and$ls180.v:3988$493
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3957$480_Y
- connect \B $and$ls180.v:3957$492_Y
- connect \Y $and$ls180.v:3957$493_Y
+ connect \A $eq$ls180.v:3988$480_Y
+ connect \B $and$ls180.v:3988$492_Y
+ connect \Y $and$ls180.v:3988$493_Y
end
- attribute \src "ls180.v:3957.416-3957.784"
- cell $and $and$ls180.v:3957$494
+ attribute \src "ls180.v:3988.416-3988.784"
+ cell $and $and$ls180.v:3988$494
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3957$493_Y
+ connect \A $and$ls180.v:3988$493_Y
connect \B \main_sdram_interface_bank1_ready
- connect \Y $and$ls180.v:3957$494_Y
+ connect \Y $and$ls180.v:3988$494_Y
end
- attribute \src "ls180.v:3957.899-3957.968"
- cell $and $and$ls180.v:3957$499
+ attribute \src "ls180.v:3988.899-3988.968"
+ cell $and $and$ls180.v:3988$499
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:3957$498_Y
- connect \Y $and$ls180.v:3957$499_Y
+ connect \B $eq$ls180.v:3988$498_Y
+ connect \Y $and$ls180.v:3988$499_Y
end
- attribute \src "ls180.v:3957.974-3957.1043"
- cell $and $and$ls180.v:3957$502
+ attribute \src "ls180.v:3988.974-3988.1043"
+ cell $and $and$ls180.v:3988$502
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:3957$501_Y
- connect \Y $and$ls180.v:3957$502_Y
+ connect \B $eq$ls180.v:3988$501_Y
+ connect \Y $and$ls180.v:3988$502_Y
end
- attribute \src "ls180.v:3957.1049-3957.1118"
- cell $and $and$ls180.v:3957$505
+ attribute \src "ls180.v:3988.1049-3988.1118"
+ cell $and $and$ls180.v:3988$505
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:3957$504_Y
- connect \Y $and$ls180.v:3957$505_Y
+ connect \B $eq$ls180.v:3988$504_Y
+ connect \Y $and$ls180.v:3988$505_Y
end
- attribute \src "ls180.v:3957.830-3957.1121"
- cell $and $and$ls180.v:3957$508
+ attribute \src "ls180.v:3988.830-3988.1121"
+ cell $and $and$ls180.v:3988$508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3957$497_Y
- connect \B $not$ls180.v:3957$507_Y
- connect \Y $and$ls180.v:3957$508_Y
+ connect \A $eq$ls180.v:3988$497_Y
+ connect \B $not$ls180.v:3988$507_Y
+ connect \Y $and$ls180.v:3988$508_Y
end
- attribute \src "ls180.v:3957.791-3957.1122"
- cell $and $and$ls180.v:3957$509
+ attribute \src "ls180.v:3988.791-3988.1122"
+ cell $and $and$ls180.v:3988$509
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3957$496_Y
- connect \B $and$ls180.v:3957$508_Y
- connect \Y $and$ls180.v:3957$509_Y
+ connect \A $eq$ls180.v:3988$496_Y
+ connect \B $and$ls180.v:3988$508_Y
+ connect \Y $and$ls180.v:3988$509_Y
end
- attribute \src "ls180.v:3957.790-3957.1158"
- cell $and $and$ls180.v:3957$510
+ attribute \src "ls180.v:3988.790-3988.1158"
+ cell $and $and$ls180.v:3988$510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3957$509_Y
+ connect \A $and$ls180.v:3988$509_Y
connect \B \main_sdram_interface_bank2_ready
- connect \Y $and$ls180.v:3957$510_Y
+ connect \Y $and$ls180.v:3988$510_Y
end
- attribute \src "ls180.v:3957.1273-3957.1342"
- cell $and $and$ls180.v:3957$515
+ attribute \src "ls180.v:3988.1273-3988.1342"
+ cell $and $and$ls180.v:3988$515
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:3957$514_Y
- connect \Y $and$ls180.v:3957$515_Y
+ connect \B $eq$ls180.v:3988$514_Y
+ connect \Y $and$ls180.v:3988$515_Y
end
- attribute \src "ls180.v:3957.1348-3957.1417"
- cell $and $and$ls180.v:3957$518
+ attribute \src "ls180.v:3988.1348-3988.1417"
+ cell $and $and$ls180.v:3988$518
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:3957$517_Y
- connect \Y $and$ls180.v:3957$518_Y
+ connect \B $eq$ls180.v:3988$517_Y
+ connect \Y $and$ls180.v:3988$518_Y
end
- attribute \src "ls180.v:3957.1423-3957.1492"
- cell $and $and$ls180.v:3957$521
+ attribute \src "ls180.v:3988.1423-3988.1492"
+ cell $and $and$ls180.v:3988$521
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:3957$520_Y
- connect \Y $and$ls180.v:3957$521_Y
+ connect \B $eq$ls180.v:3988$520_Y
+ connect \Y $and$ls180.v:3988$521_Y
end
- attribute \src "ls180.v:3957.1204-3957.1495"
- cell $and $and$ls180.v:3957$524
+ attribute \src "ls180.v:3988.1204-3988.1495"
+ cell $and $and$ls180.v:3988$524
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3957$513_Y
- connect \B $not$ls180.v:3957$523_Y
- connect \Y $and$ls180.v:3957$524_Y
+ connect \A $eq$ls180.v:3988$513_Y
+ connect \B $not$ls180.v:3988$523_Y
+ connect \Y $and$ls180.v:3988$524_Y
end
- attribute \src "ls180.v:3957.1165-3957.1496"
- cell $and $and$ls180.v:3957$525
+ attribute \src "ls180.v:3988.1165-3988.1496"
+ cell $and $and$ls180.v:3988$525
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3957$512_Y
- connect \B $and$ls180.v:3957$524_Y
- connect \Y $and$ls180.v:3957$525_Y
+ connect \A $eq$ls180.v:3988$512_Y
+ connect \B $and$ls180.v:3988$524_Y
+ connect \Y $and$ls180.v:3988$525_Y
end
- attribute \src "ls180.v:3957.1164-3957.1532"
- cell $and $and$ls180.v:3957$526
+ attribute \src "ls180.v:3988.1164-3988.1532"
+ cell $and $and$ls180.v:3988$526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3957$525_Y
+ connect \A $and$ls180.v:3988$525_Y
connect \B \main_sdram_interface_bank3_ready
- connect \Y $and$ls180.v:3957$526_Y
+ connect \Y $and$ls180.v:3988$526_Y
end
- attribute \src "ls180.v:4015.9-4015.46"
- cell $and $and$ls180.v:4015$532
+ attribute \src "ls180.v:4046.9-4046.46"
+ cell $and $and$ls180.v:4046$532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_wb_sdram_stb
connect \B \main_wb_sdram_cyc
- connect \Y $and$ls180.v:4015$532_Y
+ connect \Y $and$ls180.v:4046$532_Y
end
- attribute \src "ls180.v:4033.9-4033.46"
- cell $and $and$ls180.v:4033$539
+ attribute \src "ls180.v:4064.9-4064.46"
+ cell $and $and$ls180.v:4064$539
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_wb_sdram_stb
connect \B \main_wb_sdram_cyc
- connect \Y $and$ls180.v:4033$539_Y
+ connect \Y $and$ls180.v:4064$539_Y
end
- attribute \src "ls180.v:4046.32-4046.75"
- cell $and $and$ls180.v:4046$543
+ attribute \src "ls180.v:4077.32-4077.75"
+ cell $and $and$ls180.v:4077$543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_cyc
connect \B \main_litedram_wb_stb
- connect \Y $and$ls180.v:4046$543_Y
+ connect \Y $and$ls180.v:4077$543_Y
end
- attribute \src "ls180.v:4046.31-4046.99"
- cell $and $and$ls180.v:4046$545
+ attribute \src "ls180.v:4077.31-4077.99"
+ cell $and $and$ls180.v:4077$545
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4046$543_Y
- connect \B $not$ls180.v:4046$544_Y
- connect \Y $and$ls180.v:4046$545_Y
+ connect \A $and$ls180.v:4077$543_Y
+ connect \B $not$ls180.v:4077$544_Y
+ connect \Y $and$ls180.v:4077$545_Y
end
- attribute \src "ls180.v:4047.34-4047.102"
- cell $and $and$ls180.v:4047$547
+ attribute \src "ls180.v:4078.34-4078.102"
+ cell $and $and$ls180.v:4078$547
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4047$546_Y
+ connect \A $or$ls180.v:4078$546_Y
connect \B \main_port_cmd_payload_we
- connect \Y $and$ls180.v:4047$547_Y
+ connect \Y $and$ls180.v:4078$547_Y
end
- attribute \src "ls180.v:4047.33-4047.128"
- cell $and $and$ls180.v:4047$549
+ attribute \src "ls180.v:4078.33-4078.128"
+ cell $and $and$ls180.v:4078$549
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4047$547_Y
- connect \B $not$ls180.v:4047$548_Y
- connect \Y $and$ls180.v:4047$549_Y
+ connect \A $and$ls180.v:4078$547_Y
+ connect \B $not$ls180.v:4078$548_Y
+ connect \Y $and$ls180.v:4078$549_Y
end
- attribute \src "ls180.v:4048.33-4048.104"
- cell $and $and$ls180.v:4048$552
+ attribute \src "ls180.v:4079.33-4079.104"
+ cell $and $and$ls180.v:4079$552
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4048$550_Y
- connect \B $not$ls180.v:4048$551_Y
- connect \Y $and$ls180.v:4048$552_Y
+ connect \A $or$ls180.v:4079$550_Y
+ connect \B $not$ls180.v:4079$551_Y
+ connect \Y $and$ls180.v:4079$552_Y
end
- attribute \src "ls180.v:4049.49-4049.85"
- cell $and $and$ls180.v:4049$553
+ attribute \src "ls180.v:4080.49-4080.85"
+ cell $and $and$ls180.v:4080$553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_we
connect \B \main_ack_wdata
- connect \Y $and$ls180.v:4049$553_Y
+ connect \Y $and$ls180.v:4080$553_Y
end
- attribute \src "ls180.v:4049.90-4049.129"
- cell $and $and$ls180.v:4049$555
+ attribute \src "ls180.v:4080.90-4080.129"
+ cell $and $and$ls180.v:4080$555
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4049$554_Y
+ connect \A $not$ls180.v:4080$554_Y
connect \B \main_ack_rdata
- connect \Y $and$ls180.v:4049$555_Y
+ connect \Y $and$ls180.v:4080$555_Y
end
- attribute \src "ls180.v:4049.32-4049.131"
- cell $and $and$ls180.v:4049$557
+ attribute \src "ls180.v:4080.32-4080.131"
+ cell $and $and$ls180.v:4080$557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_ack_cmd
- connect \B $or$ls180.v:4049$556_Y
- connect \Y $and$ls180.v:4049$557_Y
+ connect \B $or$ls180.v:4080$556_Y
+ connect \Y $and$ls180.v:4080$557_Y
end
- attribute \src "ls180.v:4050.25-4050.66"
- cell $and $and$ls180.v:4050$558
+ attribute \src "ls180.v:4081.25-4081.66"
+ cell $and $and$ls180.v:4081$558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_valid
connect \B \main_port_cmd_ready
- connect \Y $and$ls180.v:4050$558_Y
+ connect \Y $and$ls180.v:4081$558_Y
end
- attribute \src "ls180.v:4051.27-4051.72"
- cell $and $and$ls180.v:4051$560
+ attribute \src "ls180.v:4082.27-4082.72"
+ cell $and $and$ls180.v:4082$560
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_wdata_valid
connect \B \main_port_wdata_ready
- connect \Y $and$ls180.v:4051$560_Y
+ connect \Y $and$ls180.v:4082$560_Y
end
- attribute \src "ls180.v:4052.26-4052.71"
- cell $and $and$ls180.v:4052$562
+ attribute \src "ls180.v:4083.26-4083.71"
+ cell $and $and$ls180.v:4083$562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_rdata_valid
connect \B \main_port_rdata_ready
- connect \Y $and$ls180.v:4052$562_Y
+ connect \Y $and$ls180.v:4083$562_Y
end
- attribute \src "ls180.v:4081.64-4081.88"
- cell $and $and$ls180.v:4081$568
+ attribute \src "ls180.v:4112.64-4112.88"
+ cell $and $and$ls180.v:4112$568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A 1'0
connect \B \main_uart_rxtx_we
- connect \Y $and$ls180.v:4081$568_Y
+ connect \Y $and$ls180.v:4112$568_Y
end
- attribute \src "ls180.v:4085.7-4085.78"
- cell $and $and$ls180.v:4085$572
+ attribute \src "ls180.v:4116.7-4116.78"
+ cell $and $and$ls180.v:4116$572
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_eventmanager_pending_re
connect \B \main_uart_eventmanager_pending_r [0]
- connect \Y $and$ls180.v:4085$572_Y
+ connect \Y $and$ls180.v:4116$572_Y
end
- attribute \src "ls180.v:4096.7-4096.78"
- cell $and $and$ls180.v:4096$575
+ attribute \src "ls180.v:4127.7-4127.78"
+ cell $and $and$ls180.v:4127$575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_eventmanager_pending_re
connect \B \main_uart_eventmanager_pending_r [1]
- connect \Y $and$ls180.v:4096$575_Y
+ connect \Y $and$ls180.v:4127$575_Y
end
- attribute \src "ls180.v:4105.26-4105.97"
- cell $and $and$ls180.v:4105$577
+ attribute \src "ls180.v:4136.26-4136.97"
+ cell $and $and$ls180.v:4136$577
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_eventmanager_pending_w [0]
connect \B \main_uart_eventmanager_storage [0]
- connect \Y $and$ls180.v:4105$577_Y
+ connect \Y $and$ls180.v:4136$577_Y
end
- attribute \src "ls180.v:4105.102-4105.173"
- cell $and $and$ls180.v:4105$578
+ attribute \src "ls180.v:4136.102-4136.173"
+ cell $and $and$ls180.v:4136$578
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_eventmanager_pending_w [1]
connect \B \main_uart_eventmanager_storage [1]
- connect \Y $and$ls180.v:4105$578_Y
+ connect \Y $and$ls180.v:4136$578_Y
end
- attribute \src "ls180.v:4120.41-4120.133"
- cell $and $and$ls180.v:4120$582
+ attribute \src "ls180.v:4151.41-4151.133"
+ cell $and $and$ls180.v:4151$582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_syncfifo_readable
- connect \B $or$ls180.v:4120$581_Y
- connect \Y $and$ls180.v:4120$582_Y
+ connect \B $or$ls180.v:4151$581_Y
+ connect \Y $and$ls180.v:4151$582_Y
end
- attribute \src "ls180.v:4131.39-4131.136"
- cell $and $and$ls180.v:4131$587
+ attribute \src "ls180.v:4162.39-4162.136"
+ cell $and $and$ls180.v:4162$587
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_syncfifo_we
- connect \B $or$ls180.v:4131$586_Y
- connect \Y $and$ls180.v:4131$587_Y
+ connect \B $or$ls180.v:4162$586_Y
+ connect \Y $and$ls180.v:4162$587_Y
end
- attribute \src "ls180.v:4132.37-4132.104"
- cell $and $and$ls180.v:4132$588
+ attribute \src "ls180.v:4163.37-4163.104"
+ cell $and $and$ls180.v:4163$588
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_syncfifo_readable
connect \B \main_uart_tx_fifo_syncfifo_re
- connect \Y $and$ls180.v:4132$588_Y
+ connect \Y $and$ls180.v:4163$588_Y
end
- attribute \src "ls180.v:4150.41-4150.133"
- cell $and $and$ls180.v:4150$593
+ attribute \src "ls180.v:4181.41-4181.133"
+ cell $and $and$ls180.v:4181$593
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_syncfifo_readable
- connect \B $or$ls180.v:4150$592_Y
- connect \Y $and$ls180.v:4150$593_Y
+ connect \B $or$ls180.v:4181$592_Y
+ connect \Y $and$ls180.v:4181$593_Y
end
- attribute \src "ls180.v:4161.39-4161.136"
- cell $and $and$ls180.v:4161$598
+ attribute \src "ls180.v:4192.39-4192.136"
+ cell $and $and$ls180.v:4192$598
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_syncfifo_we
- connect \B $or$ls180.v:4161$597_Y
- connect \Y $and$ls180.v:4161$598_Y
+ connect \B $or$ls180.v:4192$597_Y
+ connect \Y $and$ls180.v:4192$598_Y
end
- attribute \src "ls180.v:4162.37-4162.104"
- cell $and $and$ls180.v:4162$599
+ attribute \src "ls180.v:4193.37-4193.104"
+ cell $and $and$ls180.v:4193$599
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_syncfifo_readable
connect \B \main_uart_rx_fifo_syncfifo_re
- connect \Y $and$ls180.v:4162$599_Y
+ connect \Y $and$ls180.v:4193$599_Y
end
- attribute \src "ls180.v:4287.33-4287.86"
- cell $and $and$ls180.v:4287$633
+ attribute \src "ls180.v:4322.33-4322.86"
+ cell $and $and$ls180.v:4322$633
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_clocker_clk1
- connect \B $not$ls180.v:4287$632_Y
- connect \Y $and$ls180.v:4287$633_Y
+ connect \B $not$ls180.v:4322$632_Y
+ connect \Y $and$ls180.v:4322$633_Y
end
- attribute \src "ls180.v:4391.9-4391.68"
- cell $and $and$ls180.v:4391$642
+ attribute \src "ls180.v:4426.9-4426.68"
+ cell $and $and$ls180.v:4426$642
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdw_sink_valid
connect \B \main_sdphy_cmdw_pads_out_ready
- connect \Y $and$ls180.v:4391$642_Y
+ connect \Y $and$ls180.v:4426$642_Y
end
- attribute \src "ls180.v:4411.53-4411.145"
- cell $and $and$ls180.v:4411$645
+ attribute \src "ls180.v:4446.53-4446.145"
+ cell $and $and$ls180.v:4446$645
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_pads_in_valid
- connect \B $or$ls180.v:4411$644_Y
- connect \Y $and$ls180.v:4411$645_Y
+ connect \B $or$ls180.v:4446$644_Y
+ connect \Y $and$ls180.v:4446$645_Y
end
- attribute \src "ls180.v:4430.52-4430.137"
- cell $and $and$ls180.v:4430$648
+ attribute \src "ls180.v:4465.52-4465.137"
+ cell $and $and$ls180.v:4465$648
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
- connect \Y $and$ls180.v:4430$648_Y
+ connect \Y $and$ls180.v:4465$648_Y
end
- attribute \src "ls180.v:4471.9-4471.68"
- cell $and $and$ls180.v:4471$656
+ attribute \src "ls180.v:4506.9-4506.68"
+ cell $and $and$ls180.v:4506$656
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_source_valid
connect \B \main_sdphy_cmdr_source_ready
- connect \Y $and$ls180.v:4471$656_Y
+ connect \Y $and$ls180.v:4506$656_Y
end
- attribute \src "ls180.v:4509.9-4509.68"
- cell $and $and$ls180.v:4509$662
+ attribute \src "ls180.v:4544.9-4544.68"
+ cell $and $and$ls180.v:4544$662
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_source_valid
connect \B \main_sdphy_cmdr_source_ready
- connect \Y $and$ls180.v:4509$662_Y
+ connect \Y $and$ls180.v:4544$662_Y
end
- attribute \src "ls180.v:4518.10-4518.69"
- cell $and $and$ls180.v:4518$663
+ attribute \src "ls180.v:4553.10-4553.69"
+ cell $and $and$ls180.v:4553$663
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_sink_valid
connect \B \main_sdphy_cmdr_pads_out_ready
- connect \Y $and$ls180.v:4518$663_Y
+ connect \Y $and$ls180.v:4553$663_Y
end
- attribute \src "ls180.v:4518.9-4518.93"
- cell $and $and$ls180.v:4518$664
+ attribute \src "ls180.v:4553.9-4553.93"
+ cell $and $and$ls180.v:4553$664
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4518$663_Y
+ connect \A $and$ls180.v:4553$663_Y
connect \B \main_sdphy_cmdw_done
- connect \Y $and$ls180.v:4518$664_Y
+ connect \Y $and$ls180.v:4553$664_Y
end
- attribute \src "ls180.v:4538.54-4538.117"
- cell $and $and$ls180.v:4538$666
+ attribute \src "ls180.v:4573.54-4573.117"
+ cell $and $and$ls180.v:4573$666
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_pads_in_valid
connect \B \main_sdphy_dataw_crcr_run
- connect \Y $and$ls180.v:4538$666_Y
+ connect \Y $and$ls180.v:4573$666_Y
end
- attribute \src "ls180.v:4557.53-4557.140"
- cell $and $and$ls180.v:4557$669
+ attribute \src "ls180.v:4592.53-4592.140"
+ cell $and $and$ls180.v:4592$669
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_sink_valid
connect \B \main_sdphy_dataw_crcr_converter_sink_ready
- connect \Y $and$ls180.v:4557$669_Y
+ connect \Y $and$ls180.v:4592$669_Y
end
- attribute \src "ls180.v:4654.9-4654.70"
- cell $and $and$ls180.v:4654$679
+ attribute \src "ls180.v:4689.9-4689.70"
+ cell $and $and$ls180.v:4689$679
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_sink_valid
connect \B \main_sdphy_dataw_pads_out_ready
- connect \Y $and$ls180.v:4654$679_Y
+ connect \Y $and$ls180.v:4689$679_Y
end
- attribute \src "ls180.v:4672.55-4672.120"
- cell $and $and$ls180.v:4672$681
+ attribute \src "ls180.v:4707.55-4707.120"
+ cell $and $and$ls180.v:4707$681
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_pads_in_valid
connect \B \main_sdphy_datar_datar_run
- connect \Y $and$ls180.v:4672$681_Y
+ connect \Y $and$ls180.v:4707$681_Y
end
- attribute \src "ls180.v:4691.54-4691.143"
- cell $and $and$ls180.v:4691$684
+ attribute \src "ls180.v:4726.54-4726.143"
+ cell $and $and$ls180.v:4726$684
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_sink_valid
connect \B \main_sdphy_datar_datar_converter_sink_ready
- connect \Y $and$ls180.v:4691$684_Y
+ connect \Y $and$ls180.v:4726$684_Y
end
- attribute \src "ls180.v:4773.9-4773.70"
- cell $and $and$ls180.v:4773$699
+ attribute \src "ls180.v:4808.9-4808.70"
+ cell $and $and$ls180.v:4808$699
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_source_valid
connect \B \main_sdphy_datar_source_ready
- connect \Y $and$ls180.v:4773$699_Y
+ connect \Y $and$ls180.v:4808$699_Y
end
- attribute \src "ls180.v:4780.9-4780.70"
- cell $and $and$ls180.v:4780$700
+ attribute \src "ls180.v:4815.9-4815.70"
+ cell $and $and$ls180.v:4815$700
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_sink_valid
connect \B \main_sdphy_datar_pads_out_ready
- connect \Y $and$ls180.v:4780$700_Y
+ connect \Y $and$ls180.v:4815$700_Y
end
- attribute \src "ls180.v:4861.48-4861.124"
- cell $and $and$ls180.v:4861$823
+ attribute \src "ls180.v:4896.48-4896.124"
+ cell $and $and$ls180.v:4896$823
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_last
connect \B \main_sdcore_crc16_inserter_sink_valid
- connect \Y $and$ls180.v:4861$823_Y
+ connect \Y $and$ls180.v:4896$823_Y
end
- attribute \src "ls180.v:4861.47-4861.165"
- cell $and $and$ls180.v:4861$824
+ attribute \src "ls180.v:4896.47-4896.165"
+ cell $and $and$ls180.v:4896$824
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4861$823_Y
+ connect \A $and$ls180.v:4896$823_Y
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4861$824_Y
+ connect \Y $and$ls180.v:4896$824_Y
end
- attribute \src "ls180.v:4862.50-4862.127"
- cell $and $and$ls180.v:4862$825
+ attribute \src "ls180.v:4897.50-4897.127"
+ cell $and $and$ls180.v:4897$825
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_valid
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4862$825_Y
+ connect \Y $and$ls180.v:4897$825_Y
end
- attribute \src "ls180.v:4864.48-4864.124"
- cell $and $and$ls180.v:4864$826
+ attribute \src "ls180.v:4899.48-4899.124"
+ cell $and $and$ls180.v:4899$826
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_last
connect \B \main_sdcore_crc16_inserter_sink_valid
- connect \Y $and$ls180.v:4864$826_Y
+ connect \Y $and$ls180.v:4899$826_Y
end
- attribute \src "ls180.v:4864.47-4864.165"
- cell $and $and$ls180.v:4864$827
+ attribute \src "ls180.v:4899.47-4899.165"
+ cell $and $and$ls180.v:4899$827
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4864$826_Y
+ connect \A $and$ls180.v:4899$826_Y
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4864$827_Y
+ connect \Y $and$ls180.v:4899$827_Y
end
- attribute \src "ls180.v:4865.50-4865.127"
- cell $and $and$ls180.v:4865$828
+ attribute \src "ls180.v:4900.50-4900.127"
+ cell $and $and$ls180.v:4900$828
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_valid
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4865$828_Y
+ connect \Y $and$ls180.v:4900$828_Y
end
- attribute \src "ls180.v:4867.48-4867.124"
- cell $and $and$ls180.v:4867$829
+ attribute \src "ls180.v:4902.48-4902.124"
+ cell $and $and$ls180.v:4902$829
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_last
connect \B \main_sdcore_crc16_inserter_sink_valid
- connect \Y $and$ls180.v:4867$829_Y
+ connect \Y $and$ls180.v:4902$829_Y
end
- attribute \src "ls180.v:4867.47-4867.165"
- cell $and $and$ls180.v:4867$830
+ attribute \src "ls180.v:4902.47-4902.165"
+ cell $and $and$ls180.v:4902$830
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4867$829_Y
+ connect \A $and$ls180.v:4902$829_Y
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4867$830_Y
+ connect \Y $and$ls180.v:4902$830_Y
end
- attribute \src "ls180.v:4868.50-4868.127"
- cell $and $and$ls180.v:4868$831
+ attribute \src "ls180.v:4903.50-4903.127"
+ cell $and $and$ls180.v:4903$831
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_valid
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4868$831_Y
+ connect \Y $and$ls180.v:4903$831_Y
end
- attribute \src "ls180.v:4870.48-4870.124"
- cell $and $and$ls180.v:4870$832
+ attribute \src "ls180.v:4905.48-4905.124"
+ cell $and $and$ls180.v:4905$832
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_last
connect \B \main_sdcore_crc16_inserter_sink_valid
- connect \Y $and$ls180.v:4870$832_Y
+ connect \Y $and$ls180.v:4905$832_Y
end
- attribute \src "ls180.v:4870.47-4870.165"
- cell $and $and$ls180.v:4870$833
+ attribute \src "ls180.v:4905.47-4905.165"
+ cell $and $and$ls180.v:4905$833
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4870$832_Y
+ connect \A $and$ls180.v:4905$832_Y
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4870$833_Y
+ connect \Y $and$ls180.v:4905$833_Y
end
- attribute \src "ls180.v:4871.50-4871.127"
- cell $and $and$ls180.v:4871$834
+ attribute \src "ls180.v:4906.50-4906.127"
+ cell $and $and$ls180.v:4906$834
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_valid
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4871$834_Y
+ connect \Y $and$ls180.v:4906$834_Y
end
- attribute \src "ls180.v:4984.10-4984.86"
- cell $and $and$ls180.v:4984$883
+ attribute \src "ls180.v:5019.10-5019.86"
+ cell $and $and$ls180.v:5019$883
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_sink_valid
connect \B \main_sdcore_crc16_inserter_sink_last
- connect \Y $and$ls180.v:4984$883_Y
+ connect \Y $and$ls180.v:5019$883_Y
end
- attribute \src "ls180.v:4984.9-4984.127"
- cell $and $and$ls180.v:4984$884
+ attribute \src "ls180.v:5019.9-5019.127"
+ cell $and $and$ls180.v:5019$884
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4984$883_Y
+ connect \A $and$ls180.v:5019$883_Y
connect \B \main_sdcore_crc16_inserter_sink_ready
- connect \Y $and$ls180.v:4984$884_Y
+ connect \Y $and$ls180.v:5019$884_Y
end
- attribute \src "ls180.v:4994.9-4994.152"
- cell $and $and$ls180.v:4994$888
+ attribute \src "ls180.v:5029.9-5029.152"
+ cell $and $and$ls180.v:5029$888
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4994$886_Y
- connect \B $eq$ls180.v:4994$887_Y
- connect \Y $and$ls180.v:4994$888_Y
+ connect \A $eq$ls180.v:5029$886_Y
+ connect \B $eq$ls180.v:5029$887_Y
+ connect \Y $and$ls180.v:5029$888_Y
end
- attribute \src "ls180.v:4994.8-4994.226"
- cell $and $and$ls180.v:4994$890
+ attribute \src "ls180.v:5029.8-5029.226"
+ cell $and $and$ls180.v:5029$890
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4994$888_Y
- connect \B $eq$ls180.v:4994$889_Y
- connect \Y $and$ls180.v:4994$890_Y
+ connect \A $and$ls180.v:5029$888_Y
+ connect \B $eq$ls180.v:5029$889_Y
+ connect \Y $and$ls180.v:5029$890_Y
end
- attribute \src "ls180.v:4994.7-4994.300"
- cell $and $and$ls180.v:4994$892
+ attribute \src "ls180.v:5029.7-5029.300"
+ cell $and $and$ls180.v:5029$892
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4994$890_Y
- connect \B $eq$ls180.v:4994$891_Y
- connect \Y $and$ls180.v:4994$892_Y
+ connect \A $and$ls180.v:5029$890_Y
+ connect \B $eq$ls180.v:5029$891_Y
+ connect \Y $and$ls180.v:5029$892_Y
end
- attribute \src "ls180.v:4999.49-4999.124"
- cell $and $and$ls180.v:4999$893
+ attribute \src "ls180.v:5034.49-5034.124"
+ cell $and $and$ls180.v:5034$893
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:4999$893_Y
+ connect \Y $and$ls180.v:5034$893_Y
end
- attribute \src "ls180.v:5009.49-5009.124"
- cell $and $and$ls180.v:5009$896
+ attribute \src "ls180.v:5044.49-5044.124"
+ cell $and $and$ls180.v:5044$896
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:5009$896_Y
+ connect \Y $and$ls180.v:5044$896_Y
end
- attribute \src "ls180.v:5019.49-5019.124"
- cell $and $and$ls180.v:5019$899
+ attribute \src "ls180.v:5054.49-5054.124"
+ cell $and $and$ls180.v:5054$899
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:5019$899_Y
+ connect \Y $and$ls180.v:5054$899_Y
end
- attribute \src "ls180.v:5029.49-5029.124"
- cell $and $and$ls180.v:5029$902
+ attribute \src "ls180.v:5064.49-5064.124"
+ cell $and $and$ls180.v:5064$902
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:5029$902_Y
+ connect \Y $and$ls180.v:5064$902_Y
end
- attribute \src "ls180.v:5041.7-5041.84"
- cell $and $and$ls180.v:5041$907
+ attribute \src "ls180.v:5076.7-5076.84"
+ cell $and $and$ls180.v:5076$907
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
- connect \B $gt$ls180.v:5041$906_Y
- connect \Y $and$ls180.v:5041$907_Y
+ connect \B $gt$ls180.v:5076$906_Y
+ connect \Y $and$ls180.v:5076$907_Y
end
- attribute \src "ls180.v:5159.9-5159.64"
- cell $and $and$ls180.v:5159$956
+ attribute \src "ls180.v:5194.9-5194.64"
+ cell $and $and$ls180.v:5194$956
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdw_sink_valid
connect \B \main_sdphy_cmdw_sink_ready
- connect \Y $and$ls180.v:5159$956_Y
+ connect \Y $and$ls180.v:5194$956_Y
end
- attribute \src "ls180.v:5211.10-5211.66"
- cell $and $and$ls180.v:5211$965
+ attribute \src "ls180.v:5246.10-5246.66"
+ cell $and $and$ls180.v:5246$965
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_sink_valid
connect \B \main_sdphy_dataw_sink_last
- connect \Y $and$ls180.v:5211$965_Y
+ connect \Y $and$ls180.v:5246$965_Y
end
- attribute \src "ls180.v:5211.9-5211.97"
- cell $and $and$ls180.v:5211$966
+ attribute \src "ls180.v:5246.9-5246.97"
+ cell $and $and$ls180.v:5246$966
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5211$965_Y
+ connect \A $and$ls180.v:5246$965_Y
connect \B \main_sdphy_dataw_sink_ready
- connect \Y $and$ls180.v:5211$966_Y
+ connect \Y $and$ls180.v:5246$966_Y
end
- attribute \src "ls180.v:5237.11-5237.71"
- cell $and $and$ls180.v:5237$974
+ attribute \src "ls180.v:5272.11-5272.71"
+ cell $and $and$ls180.v:5272$974
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_source_last
connect \B \main_sdphy_datar_source_ready
- connect \Y $and$ls180.v:5237$974_Y
+ connect \Y $and$ls180.v:5272$974_Y
end
- attribute \src "ls180.v:5321.43-5321.152"
- cell $and $and$ls180.v:5321$982
+ attribute \src "ls180.v:5356.43-5356.152"
+ cell $and $and$ls180.v:5356$982
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_syncfifo_we
- connect \B $or$ls180.v:5321$981_Y
- connect \Y $and$ls180.v:5321$982_Y
+ connect \B $or$ls180.v:5356$981_Y
+ connect \Y $and$ls180.v:5356$982_Y
end
- attribute \src "ls180.v:5322.41-5322.116"
- cell $and $and$ls180.v:5322$983
+ attribute \src "ls180.v:5357.41-5357.116"
+ cell $and $and$ls180.v:5357$983
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_syncfifo_readable
connect \B \main_sdblock2mem_fifo_syncfifo_re
- connect \Y $and$ls180.v:5322$983_Y
+ connect \Y $and$ls180.v:5357$983_Y
end
- attribute \src "ls180.v:5334.48-5334.125"
- cell $and $and$ls180.v:5334$988
+ attribute \src "ls180.v:5369.48-5369.125"
+ cell $and $and$ls180.v:5369$988
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_sink_valid
connect \B \main_sdblock2mem_converter_sink_ready
- connect \Y $and$ls180.v:5334$988_Y
+ connect \Y $and$ls180.v:5369$988_Y
end
- attribute \src "ls180.v:5361.9-5361.102"
- cell $and $and$ls180.v:5361$992
+ attribute \src "ls180.v:5396.9-5396.102"
+ cell $and $and$ls180.v:5396$992
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid
connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready
- connect \Y $and$ls180.v:5361$992_Y
+ connect \Y $and$ls180.v:5396$992_Y
end
- attribute \src "ls180.v:5434.9-5434.58"
- cell $and $and$ls180.v:5434$998
+ attribute \src "ls180.v:5469.9-5469.58"
+ cell $and $and$ls180.v:5469$998
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_interface1_bus_stb
connect \B \main_interface1_bus_ack
- connect \Y $and$ls180.v:5434$998_Y
+ connect \Y $and$ls180.v:5469$998_Y
end
- attribute \src "ls180.v:5487.51-5487.123"
- cell $and $and$ls180.v:5487$1006
+ attribute \src "ls180.v:5522.51-5522.123"
+ cell $and $and$ls180.v:5522$1006
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_converter_sink_first
connect \B \main_sdmem2block_converter_first
- connect \Y $and$ls180.v:5487$1006_Y
+ connect \Y $and$ls180.v:5522$1006_Y
end
- attribute \src "ls180.v:5488.50-5488.120"
- cell $and $and$ls180.v:5488$1007
+ attribute \src "ls180.v:5523.50-5523.120"
+ cell $and $and$ls180.v:5523$1007
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_converter_sink_last
connect \B \main_sdmem2block_converter_last
- connect \Y $and$ls180.v:5488$1007_Y
+ connect \Y $and$ls180.v:5523$1007_Y
end
- attribute \src "ls180.v:5489.49-5489.122"
- cell $and $and$ls180.v:5489$1008
+ attribute \src "ls180.v:5524.49-5524.122"
+ cell $and $and$ls180.v:5524$1008
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_converter_last
connect \B \main_sdmem2block_converter_source_ready
- connect \Y $and$ls180.v:5489$1008_Y
+ connect \Y $and$ls180.v:5524$1008_Y
end
- attribute \src "ls180.v:5529.43-5529.152"
- cell $and $and$ls180.v:5529$1013
+ attribute \src "ls180.v:5564.43-5564.152"
+ cell $and $and$ls180.v:5564$1013
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_syncfifo_we
- connect \B $or$ls180.v:5529$1012_Y
- connect \Y $and$ls180.v:5529$1013_Y
+ connect \B $or$ls180.v:5564$1012_Y
+ connect \Y $and$ls180.v:5564$1013_Y
end
- attribute \src "ls180.v:5530.41-5530.116"
- cell $and $and$ls180.v:5530$1014
+ attribute \src "ls180.v:5565.41-5565.116"
+ cell $and $and$ls180.v:5565$1014
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_syncfifo_readable
connect \B \main_sdmem2block_fifo_syncfifo_re
- connect \Y $and$ls180.v:5530$1014_Y
+ connect \Y $and$ls180.v:5565$1014_Y
end
- attribute \src "ls180.v:5621.9-5621.76"
- cell $and $and$ls180.v:5621$1026
+ attribute \src "ls180.v:5656.9-5656.76"
+ cell $and $and$ls180.v:5656$1026
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_libresocsim_wishbone_cyc
connect \B \builder_libresocsim_wishbone_stb
- connect \Y $and$ls180.v:5621$1026_Y
+ connect \Y $and$ls180.v:5656$1026_Y
end
- attribute \src "ls180.v:5624.44-5624.120"
- cell $and $and$ls180.v:5624$1028
+ attribute \src "ls180.v:5659.44-5659.120"
+ cell $and $and$ls180.v:5659$1028
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_libresocsim_wishbone_we
- connect \B $ne$ls180.v:5624$1027_Y
- connect \Y $and$ls180.v:5624$1028_Y
+ connect \B $ne$ls180.v:5659$1027_Y
+ connect \Y $and$ls180.v:5659$1028_Y
end
- attribute \src "ls180.v:5644.63-5644.107"
- cell $and $and$ls180.v:5644$1030
+ attribute \src "ls180.v:5679.63-5679.107"
+ cell $and $and$ls180.v:5679$1030
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_ack
- connect \B $eq$ls180.v:5644$1029_Y
- connect \Y $and$ls180.v:5644$1030_Y
+ connect \B $eq$ls180.v:5679$1029_Y
+ connect \Y $and$ls180.v:5679$1030_Y
end
- attribute \src "ls180.v:5645.63-5645.107"
- cell $and $and$ls180.v:5645$1032
+ attribute \src "ls180.v:5680.63-5680.107"
+ cell $and $and$ls180.v:5680$1032
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_ack
- connect \B $eq$ls180.v:5645$1031_Y
- connect \Y $and$ls180.v:5645$1032_Y
+ connect \B $eq$ls180.v:5680$1031_Y
+ connect \Y $and$ls180.v:5680$1032_Y
end
- attribute \src "ls180.v:5646.63-5646.107"
- cell $and $and$ls180.v:5646$1034
+ attribute \src "ls180.v:5681.63-5681.107"
+ cell $and $and$ls180.v:5681$1034
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_ack
- connect \B $eq$ls180.v:5646$1033_Y
- connect \Y $and$ls180.v:5646$1034_Y
+ connect \B $eq$ls180.v:5681$1033_Y
+ connect \Y $and$ls180.v:5681$1034_Y
end
- attribute \src "ls180.v:5647.35-5647.79"
- cell $and $and$ls180.v:5647$1036
+ attribute \src "ls180.v:5682.35-5682.79"
+ cell $and $and$ls180.v:5682$1036
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_ack
- connect \B $eq$ls180.v:5647$1035_Y
- connect \Y $and$ls180.v:5647$1036_Y
+ connect \B $eq$ls180.v:5682$1035_Y
+ connect \Y $and$ls180.v:5682$1036_Y
end
- attribute \src "ls180.v:5648.35-5648.79"
- cell $and $and$ls180.v:5648$1038
+ attribute \src "ls180.v:5683.35-5683.79"
+ cell $and $and$ls180.v:5683$1038
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_ack
- connect \B $eq$ls180.v:5648$1037_Y
- connect \Y $and$ls180.v:5648$1038_Y
+ connect \B $eq$ls180.v:5683$1037_Y
+ connect \Y $and$ls180.v:5683$1038_Y
end
- attribute \src "ls180.v:5649.63-5649.107"
- cell $and $and$ls180.v:5649$1040
+ attribute \src "ls180.v:5684.63-5684.107"
+ cell $and $and$ls180.v:5684$1040
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_err
- connect \B $eq$ls180.v:5649$1039_Y
- connect \Y $and$ls180.v:5649$1040_Y
+ connect \B $eq$ls180.v:5684$1039_Y
+ connect \Y $and$ls180.v:5684$1040_Y
end
- attribute \src "ls180.v:5650.63-5650.107"
- cell $and $and$ls180.v:5650$1042
+ attribute \src "ls180.v:5685.63-5685.107"
+ cell $and $and$ls180.v:5685$1042
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_err
- connect \B $eq$ls180.v:5650$1041_Y
- connect \Y $and$ls180.v:5650$1042_Y
+ connect \B $eq$ls180.v:5685$1041_Y
+ connect \Y $and$ls180.v:5685$1042_Y
end
- attribute \src "ls180.v:5651.63-5651.107"
- cell $and $and$ls180.v:5651$1044
+ attribute \src "ls180.v:5686.63-5686.107"
+ cell $and $and$ls180.v:5686$1044
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_err
- connect \B $eq$ls180.v:5651$1043_Y
- connect \Y $and$ls180.v:5651$1044_Y
+ connect \B $eq$ls180.v:5686$1043_Y
+ connect \Y $and$ls180.v:5686$1044_Y
end
- attribute \src "ls180.v:5652.35-5652.79"
- cell $and $and$ls180.v:5652$1046
+ attribute \src "ls180.v:5687.35-5687.79"
+ cell $and $and$ls180.v:5687$1046
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_err
- connect \B $eq$ls180.v:5652$1045_Y
- connect \Y $and$ls180.v:5652$1046_Y
+ connect \B $eq$ls180.v:5687$1045_Y
+ connect \Y $and$ls180.v:5687$1046_Y
end
- attribute \src "ls180.v:5653.35-5653.79"
- cell $and $and$ls180.v:5653$1048
+ attribute \src "ls180.v:5688.35-5688.79"
+ cell $and $and$ls180.v:5688$1048
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_err
- connect \B $eq$ls180.v:5653$1047_Y
- connect \Y $and$ls180.v:5653$1048_Y
+ connect \B $eq$ls180.v:5688$1047_Y
+ connect \Y $and$ls180.v:5688$1048_Y
end
- attribute \src "ls180.v:5698.40-5698.81"
- cell $and $and$ls180.v:5698$1055
+ attribute \src "ls180.v:5733.40-5733.81"
+ cell $and $and$ls180.v:5733$1055
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_cyc
connect \B \builder_slave_sel [0]
- connect \Y $and$ls180.v:5698$1055_Y
+ connect \Y $and$ls180.v:5733$1055_Y
end
- attribute \src "ls180.v:5699.50-5699.91"
- cell $and $and$ls180.v:5699$1056
+ attribute \src "ls180.v:5734.50-5734.91"
+ cell $and $and$ls180.v:5734$1056
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_cyc
connect \B \builder_slave_sel [1]
- connect \Y $and$ls180.v:5699$1056_Y
+ connect \Y $and$ls180.v:5734$1056_Y
end
- attribute \src "ls180.v:5700.50-5700.91"
- cell $and $and$ls180.v:5700$1057
+ attribute \src "ls180.v:5735.50-5735.91"
+ cell $and $and$ls180.v:5735$1057
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_cyc
connect \B \builder_slave_sel [2]
- connect \Y $and$ls180.v:5700$1057_Y
+ connect \Y $and$ls180.v:5735$1057_Y
end
- attribute \src "ls180.v:5701.29-5701.70"
- cell $and $and$ls180.v:5701$1058
+ attribute \src "ls180.v:5736.29-5736.70"
+ cell $and $and$ls180.v:5736$1058
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_cyc
connect \B \builder_slave_sel [3]
- connect \Y $and$ls180.v:5701$1058_Y
+ connect \Y $and$ls180.v:5736$1058_Y
end
- attribute \src "ls180.v:5702.44-5702.85"
- cell $and $and$ls180.v:5702$1059
+ attribute \src "ls180.v:5737.44-5737.85"
+ cell $and $and$ls180.v:5737$1059
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_cyc
connect \B \builder_slave_sel [4]
- connect \Y $and$ls180.v:5702$1059_Y
+ connect \Y $and$ls180.v:5737$1059_Y
end
- attribute \src "ls180.v:5704.25-5704.64"
- cell $and $and$ls180.v:5704$1064
+ attribute \src "ls180.v:5739.25-5739.64"
+ cell $and $and$ls180.v:5739$1064
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_stb
connect \B \builder_shared_cyc
- connect \Y $and$ls180.v:5704$1064_Y
+ connect \Y $and$ls180.v:5739$1064_Y
end
- attribute \src "ls180.v:5704.24-5704.89"
- cell $and $and$ls180.v:5704$1066
+ attribute \src "ls180.v:5739.24-5739.89"
+ cell $and $and$ls180.v:5739$1066
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5704$1064_Y
- connect \B $not$ls180.v:5704$1065_Y
- connect \Y $and$ls180.v:5704$1066_Y
+ connect \A $and$ls180.v:5739$1064_Y
+ connect \B $not$ls180.v:5739$1065_Y
+ connect \Y $and$ls180.v:5739$1066_Y
end
- attribute \src "ls180.v:5710.31-5710.92"
- cell $and $and$ls180.v:5710$1072
+ attribute \src "ls180.v:5745.31-5745.92"
+ cell $and $and$ls180.v:5745$1072
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] }
connect \B \main_libresocsim_ram_bus_dat_r
- connect \Y $and$ls180.v:5710$1072_Y
+ connect \Y $and$ls180.v:5745$1072_Y
end
- attribute \src "ls180.v:5710.97-5710.168"
- cell $and $and$ls180.v:5710$1073
+ attribute \src "ls180.v:5745.97-5745.168"
+ cell $and $and$ls180.v:5745$1073
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] }
connect \B \main_libresocsim_libresoc_xics_icp_dat_r
- connect \Y $and$ls180.v:5710$1073_Y
+ connect \Y $and$ls180.v:5745$1073_Y
end
- attribute \src "ls180.v:5710.174-5710.245"
- cell $and $and$ls180.v:5710$1075
+ attribute \src "ls180.v:5745.174-5745.245"
+ cell $and $and$ls180.v:5745$1075
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] }
connect \B \main_libresocsim_libresoc_xics_ics_dat_r
- connect \Y $and$ls180.v:5710$1075_Y
+ connect \Y $and$ls180.v:5745$1075_Y
end
- attribute \src "ls180.v:5710.251-5710.301"
- cell $and $and$ls180.v:5710$1077
+ attribute \src "ls180.v:5745.251-5745.301"
+ cell $and $and$ls180.v:5745$1077
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] }
connect \B \main_wb_sdram_dat_r
- connect \Y $and$ls180.v:5710$1077_Y
+ connect \Y $and$ls180.v:5745$1077_Y
end
- attribute \src "ls180.v:5710.307-5710.372"
- cell $and $and$ls180.v:5710$1079
+ attribute \src "ls180.v:5745.307-5745.372"
+ cell $and $and$ls180.v:5745$1079
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] }
connect \B \builder_libresocsim_wishbone_dat_r
- connect \Y $and$ls180.v:5710$1079_Y
+ connect \Y $and$ls180.v:5745$1079_Y
end
- attribute \src "ls180.v:5720.39-5720.92"
- cell $and $and$ls180.v:5720$1083
+ attribute \src "ls180.v:5755.39-5755.92"
+ cell $and $and$ls180.v:5755$1083
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5720$1083_Y
+ connect \Y $and$ls180.v:5755$1083_Y
end
- attribute \src "ls180.v:5720.38-5720.142"
- cell $and $and$ls180.v:5720$1085
+ attribute \src "ls180.v:5755.38-5755.142"
+ cell $and $and$ls180.v:5755$1085
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5720$1083_Y
- connect \B $eq$ls180.v:5720$1084_Y
- connect \Y $and$ls180.v:5720$1085_Y
+ connect \A $and$ls180.v:5755$1083_Y
+ connect \B $eq$ls180.v:5755$1084_Y
+ connect \Y $and$ls180.v:5755$1085_Y
end
- attribute \src "ls180.v:5721.39-5721.95"
- cell $and $and$ls180.v:5721$1087
+ attribute \src "ls180.v:5756.39-5756.95"
+ cell $and $and$ls180.v:5756$1087
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5721$1086_Y
- connect \Y $and$ls180.v:5721$1087_Y
+ connect \B $not$ls180.v:5756$1086_Y
+ connect \Y $and$ls180.v:5756$1087_Y
end
- attribute \src "ls180.v:5721.38-5721.145"
- cell $and $and$ls180.v:5721$1089
+ attribute \src "ls180.v:5756.38-5756.145"
+ cell $and $and$ls180.v:5756$1089
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5721$1087_Y
- connect \B $eq$ls180.v:5721$1088_Y
- connect \Y $and$ls180.v:5721$1089_Y
+ connect \A $and$ls180.v:5756$1087_Y
+ connect \B $eq$ls180.v:5756$1088_Y
+ connect \Y $and$ls180.v:5756$1089_Y
end
- attribute \src "ls180.v:5723.41-5723.94"
- cell $and $and$ls180.v:5723$1090
+ attribute \src "ls180.v:5758.41-5758.94"
+ cell $and $and$ls180.v:5758$1090
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5723$1090_Y
+ connect \Y $and$ls180.v:5758$1090_Y
end
- attribute \src "ls180.v:5723.40-5723.144"
- cell $and $and$ls180.v:5723$1092
+ attribute \src "ls180.v:5758.40-5758.144"
+ cell $and $and$ls180.v:5758$1092
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5723$1090_Y
- connect \B $eq$ls180.v:5723$1091_Y
- connect \Y $and$ls180.v:5723$1092_Y
+ connect \A $and$ls180.v:5758$1090_Y
+ connect \B $eq$ls180.v:5758$1091_Y
+ connect \Y $and$ls180.v:5758$1092_Y
end
- attribute \src "ls180.v:5724.41-5724.97"
- cell $and $and$ls180.v:5724$1094
+ attribute \src "ls180.v:5759.41-5759.97"
+ cell $and $and$ls180.v:5759$1094
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5724$1093_Y
- connect \Y $and$ls180.v:5724$1094_Y
+ connect \B $not$ls180.v:5759$1093_Y
+ connect \Y $and$ls180.v:5759$1094_Y
end
- attribute \src "ls180.v:5724.40-5724.147"
- cell $and $and$ls180.v:5724$1096
+ attribute \src "ls180.v:5759.40-5759.147"
+ cell $and $and$ls180.v:5759$1096
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5724$1094_Y
- connect \B $eq$ls180.v:5724$1095_Y
- connect \Y $and$ls180.v:5724$1096_Y
+ connect \A $and$ls180.v:5759$1094_Y
+ connect \B $eq$ls180.v:5759$1095_Y
+ connect \Y $and$ls180.v:5759$1096_Y
end
- attribute \src "ls180.v:5726.41-5726.94"
- cell $and $and$ls180.v:5726$1097
+ attribute \src "ls180.v:5761.41-5761.94"
+ cell $and $and$ls180.v:5761$1097
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5726$1097_Y
+ connect \Y $and$ls180.v:5761$1097_Y
end
- attribute \src "ls180.v:5726.40-5726.144"
- cell $and $and$ls180.v:5726$1099
+ attribute \src "ls180.v:5761.40-5761.144"
+ cell $and $and$ls180.v:5761$1099
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5726$1097_Y
- connect \B $eq$ls180.v:5726$1098_Y
- connect \Y $and$ls180.v:5726$1099_Y
+ connect \A $and$ls180.v:5761$1097_Y
+ connect \B $eq$ls180.v:5761$1098_Y
+ connect \Y $and$ls180.v:5761$1099_Y
end
- attribute \src "ls180.v:5727.41-5727.97"
- cell $and $and$ls180.v:5727$1101
+ attribute \src "ls180.v:5762.41-5762.97"
+ cell $and $and$ls180.v:5762$1101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5727$1100_Y
- connect \Y $and$ls180.v:5727$1101_Y
+ connect \B $not$ls180.v:5762$1100_Y
+ connect \Y $and$ls180.v:5762$1101_Y
end
- attribute \src "ls180.v:5727.40-5727.147"
- cell $and $and$ls180.v:5727$1103
+ attribute \src "ls180.v:5762.40-5762.147"
+ cell $and $and$ls180.v:5762$1103
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5727$1101_Y
- connect \B $eq$ls180.v:5727$1102_Y
- connect \Y $and$ls180.v:5727$1103_Y
+ connect \A $and$ls180.v:5762$1101_Y
+ connect \B $eq$ls180.v:5762$1102_Y
+ connect \Y $and$ls180.v:5762$1103_Y
end
- attribute \src "ls180.v:5729.41-5729.94"
- cell $and $and$ls180.v:5729$1104
+ attribute \src "ls180.v:5764.41-5764.94"
+ cell $and $and$ls180.v:5764$1104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5729$1104_Y
+ connect \Y $and$ls180.v:5764$1104_Y
end
- attribute \src "ls180.v:5729.40-5729.144"
- cell $and $and$ls180.v:5729$1106
+ attribute \src "ls180.v:5764.40-5764.144"
+ cell $and $and$ls180.v:5764$1106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5729$1104_Y
- connect \B $eq$ls180.v:5729$1105_Y
- connect \Y $and$ls180.v:5729$1106_Y
+ connect \A $and$ls180.v:5764$1104_Y
+ connect \B $eq$ls180.v:5764$1105_Y
+ connect \Y $and$ls180.v:5764$1106_Y
end
- attribute \src "ls180.v:5730.41-5730.97"
- cell $and $and$ls180.v:5730$1108
+ attribute \src "ls180.v:5765.41-5765.97"
+ cell $and $and$ls180.v:5765$1108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5730$1107_Y
- connect \Y $and$ls180.v:5730$1108_Y
+ connect \B $not$ls180.v:5765$1107_Y
+ connect \Y $and$ls180.v:5765$1108_Y
end
- attribute \src "ls180.v:5730.40-5730.147"
- cell $and $and$ls180.v:5730$1110
+ attribute \src "ls180.v:5765.40-5765.147"
+ cell $and $and$ls180.v:5765$1110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5730$1108_Y
- connect \B $eq$ls180.v:5730$1109_Y
- connect \Y $and$ls180.v:5730$1110_Y
+ connect \A $and$ls180.v:5765$1108_Y
+ connect \B $eq$ls180.v:5765$1109_Y
+ connect \Y $and$ls180.v:5765$1110_Y
end
- attribute \src "ls180.v:5732.41-5732.94"
- cell $and $and$ls180.v:5732$1111
+ attribute \src "ls180.v:5767.41-5767.94"
+ cell $and $and$ls180.v:5767$1111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5732$1111_Y
+ connect \Y $and$ls180.v:5767$1111_Y
end
- attribute \src "ls180.v:5732.40-5732.144"
- cell $and $and$ls180.v:5732$1113
+ attribute \src "ls180.v:5767.40-5767.144"
+ cell $and $and$ls180.v:5767$1113
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5732$1111_Y
- connect \B $eq$ls180.v:5732$1112_Y
- connect \Y $and$ls180.v:5732$1113_Y
+ connect \A $and$ls180.v:5767$1111_Y
+ connect \B $eq$ls180.v:5767$1112_Y
+ connect \Y $and$ls180.v:5767$1113_Y
end
- attribute \src "ls180.v:5733.41-5733.97"
- cell $and $and$ls180.v:5733$1115
+ attribute \src "ls180.v:5768.41-5768.97"
+ cell $and $and$ls180.v:5768$1115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5733$1114_Y
- connect \Y $and$ls180.v:5733$1115_Y
+ connect \B $not$ls180.v:5768$1114_Y
+ connect \Y $and$ls180.v:5768$1115_Y
end
- attribute \src "ls180.v:5733.40-5733.147"
- cell $and $and$ls180.v:5733$1117
+ attribute \src "ls180.v:5768.40-5768.147"
+ cell $and $and$ls180.v:5768$1117
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5733$1115_Y
- connect \B $eq$ls180.v:5733$1116_Y
- connect \Y $and$ls180.v:5733$1117_Y
+ connect \A $and$ls180.v:5768$1115_Y
+ connect \B $eq$ls180.v:5768$1116_Y
+ connect \Y $and$ls180.v:5768$1117_Y
end
- attribute \src "ls180.v:5735.44-5735.97"
- cell $and $and$ls180.v:5735$1118
+ attribute \src "ls180.v:5770.44-5770.97"
+ cell $and $and$ls180.v:5770$1118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5735$1118_Y
+ connect \Y $and$ls180.v:5770$1118_Y
end
- attribute \src "ls180.v:5735.43-5735.147"
- cell $and $and$ls180.v:5735$1120
+ attribute \src "ls180.v:5770.43-5770.147"
+ cell $and $and$ls180.v:5770$1120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5735$1118_Y
- connect \B $eq$ls180.v:5735$1119_Y
- connect \Y $and$ls180.v:5735$1120_Y
+ connect \A $and$ls180.v:5770$1118_Y
+ connect \B $eq$ls180.v:5770$1119_Y
+ connect \Y $and$ls180.v:5770$1120_Y
end
- attribute \src "ls180.v:5736.44-5736.100"
- cell $and $and$ls180.v:5736$1122
+ attribute \src "ls180.v:5771.44-5771.100"
+ cell $and $and$ls180.v:5771$1122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5736$1121_Y
- connect \Y $and$ls180.v:5736$1122_Y
+ connect \B $not$ls180.v:5771$1121_Y
+ connect \Y $and$ls180.v:5771$1122_Y
end
- attribute \src "ls180.v:5736.43-5736.150"
- cell $and $and$ls180.v:5736$1124
+ attribute \src "ls180.v:5771.43-5771.150"
+ cell $and $and$ls180.v:5771$1124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5736$1122_Y
- connect \B $eq$ls180.v:5736$1123_Y
- connect \Y $and$ls180.v:5736$1124_Y
+ connect \A $and$ls180.v:5771$1122_Y
+ connect \B $eq$ls180.v:5771$1123_Y
+ connect \Y $and$ls180.v:5771$1124_Y
end
- attribute \src "ls180.v:5738.44-5738.97"
- cell $and $and$ls180.v:5738$1125
+ attribute \src "ls180.v:5773.44-5773.97"
+ cell $and $and$ls180.v:5773$1125
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5738$1125_Y
+ connect \Y $and$ls180.v:5773$1125_Y
end
- attribute \src "ls180.v:5738.43-5738.147"
- cell $and $and$ls180.v:5738$1127
+ attribute \src "ls180.v:5773.43-5773.147"
+ cell $and $and$ls180.v:5773$1127
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5738$1125_Y
- connect \B $eq$ls180.v:5738$1126_Y
- connect \Y $and$ls180.v:5738$1127_Y
+ connect \A $and$ls180.v:5773$1125_Y
+ connect \B $eq$ls180.v:5773$1126_Y
+ connect \Y $and$ls180.v:5773$1127_Y
end
- attribute \src "ls180.v:5739.44-5739.100"
- cell $and $and$ls180.v:5739$1129
+ attribute \src "ls180.v:5774.44-5774.100"
+ cell $and $and$ls180.v:5774$1129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5739$1128_Y
- connect \Y $and$ls180.v:5739$1129_Y
+ connect \B $not$ls180.v:5774$1128_Y
+ connect \Y $and$ls180.v:5774$1129_Y
end
- attribute \src "ls180.v:5739.43-5739.150"
- cell $and $and$ls180.v:5739$1131
+ attribute \src "ls180.v:5774.43-5774.150"
+ cell $and $and$ls180.v:5774$1131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5739$1129_Y
- connect \B $eq$ls180.v:5739$1130_Y
- connect \Y $and$ls180.v:5739$1131_Y
+ connect \A $and$ls180.v:5774$1129_Y
+ connect \B $eq$ls180.v:5774$1130_Y
+ connect \Y $and$ls180.v:5774$1131_Y
end
- attribute \src "ls180.v:5741.44-5741.97"
- cell $and $and$ls180.v:5741$1132
+ attribute \src "ls180.v:5776.44-5776.97"
+ cell $and $and$ls180.v:5776$1132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5741$1132_Y
+ connect \Y $and$ls180.v:5776$1132_Y
end
- attribute \src "ls180.v:5741.43-5741.147"
- cell $and $and$ls180.v:5741$1134
+ attribute \src "ls180.v:5776.43-5776.147"
+ cell $and $and$ls180.v:5776$1134
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5741$1132_Y
- connect \B $eq$ls180.v:5741$1133_Y
- connect \Y $and$ls180.v:5741$1134_Y
+ connect \A $and$ls180.v:5776$1132_Y
+ connect \B $eq$ls180.v:5776$1133_Y
+ connect \Y $and$ls180.v:5776$1134_Y
end
- attribute \src "ls180.v:5742.44-5742.100"
- cell $and $and$ls180.v:5742$1136
+ attribute \src "ls180.v:5777.44-5777.100"
+ cell $and $and$ls180.v:5777$1136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5742$1135_Y
- connect \Y $and$ls180.v:5742$1136_Y
+ connect \B $not$ls180.v:5777$1135_Y
+ connect \Y $and$ls180.v:5777$1136_Y
end
- attribute \src "ls180.v:5742.43-5742.150"
- cell $and $and$ls180.v:5742$1138
+ attribute \src "ls180.v:5777.43-5777.150"
+ cell $and $and$ls180.v:5777$1138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5742$1136_Y
- connect \B $eq$ls180.v:5742$1137_Y
- connect \Y $and$ls180.v:5742$1138_Y
+ connect \A $and$ls180.v:5777$1136_Y
+ connect \B $eq$ls180.v:5777$1137_Y
+ connect \Y $and$ls180.v:5777$1138_Y
end
- attribute \src "ls180.v:5744.44-5744.97"
- cell $and $and$ls180.v:5744$1139
+ attribute \src "ls180.v:5779.44-5779.97"
+ cell $and $and$ls180.v:5779$1139
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
connect \B \builder_interface0_bank_bus_we
- connect \Y $and$ls180.v:5744$1139_Y
+ connect \Y $and$ls180.v:5779$1139_Y
end
- attribute \src "ls180.v:5744.43-5744.147"
- cell $and $and$ls180.v:5744$1141
+ attribute \src "ls180.v:5779.43-5779.147"
+ cell $and $and$ls180.v:5779$1141
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5744$1139_Y
- connect \B $eq$ls180.v:5744$1140_Y
- connect \Y $and$ls180.v:5744$1141_Y
+ connect \A $and$ls180.v:5779$1139_Y
+ connect \B $eq$ls180.v:5779$1140_Y
+ connect \Y $and$ls180.v:5779$1141_Y
end
- attribute \src "ls180.v:5745.44-5745.100"
- cell $and $and$ls180.v:5745$1143
+ attribute \src "ls180.v:5780.44-5780.100"
+ cell $and $and$ls180.v:5780$1143
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank0_sel
- connect \B $not$ls180.v:5745$1142_Y
- connect \Y $and$ls180.v:5745$1143_Y
+ connect \B $not$ls180.v:5780$1142_Y
+ connect \Y $and$ls180.v:5780$1143_Y
end
- attribute \src "ls180.v:5745.43-5745.150"
- cell $and $and$ls180.v:5745$1145
+ attribute \src "ls180.v:5780.43-5780.150"
+ cell $and $and$ls180.v:5780$1145
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5745$1143_Y
- connect \B $eq$ls180.v:5745$1144_Y
- connect \Y $and$ls180.v:5745$1145_Y
+ connect \A $and$ls180.v:5780$1143_Y
+ connect \B $eq$ls180.v:5780$1144_Y
+ connect \Y $and$ls180.v:5780$1145_Y
end
- attribute \src "ls180.v:5758.36-5758.89"
- cell $and $and$ls180.v:5758$1147
+ attribute \src "ls180.v:5793.36-5793.89"
+ cell $and $and$ls180.v:5793$1147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
connect \B \builder_interface1_bank_bus_we
- connect \Y $and$ls180.v:5758$1147_Y
+ connect \Y $and$ls180.v:5793$1147_Y
end
- attribute \src "ls180.v:5758.35-5758.139"
- cell $and $and$ls180.v:5758$1149
+ attribute \src "ls180.v:5793.35-5793.139"
+ cell $and $and$ls180.v:5793$1149
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5758$1147_Y
- connect \B $eq$ls180.v:5758$1148_Y
- connect \Y $and$ls180.v:5758$1149_Y
+ connect \A $and$ls180.v:5793$1147_Y
+ connect \B $eq$ls180.v:5793$1148_Y
+ connect \Y $and$ls180.v:5793$1149_Y
end
- attribute \src "ls180.v:5759.36-5759.92"
- cell $and $and$ls180.v:5759$1151
+ attribute \src "ls180.v:5794.36-5794.92"
+ cell $and $and$ls180.v:5794$1151
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
- connect \B $not$ls180.v:5759$1150_Y
- connect \Y $and$ls180.v:5759$1151_Y
+ connect \B $not$ls180.v:5794$1150_Y
+ connect \Y $and$ls180.v:5794$1151_Y
end
- attribute \src "ls180.v:5759.35-5759.142"
- cell $and $and$ls180.v:5759$1153
+ attribute \src "ls180.v:5794.35-5794.142"
+ cell $and $and$ls180.v:5794$1153
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5759$1151_Y
- connect \B $eq$ls180.v:5759$1152_Y
- connect \Y $and$ls180.v:5759$1153_Y
+ connect \A $and$ls180.v:5794$1151_Y
+ connect \B $eq$ls180.v:5794$1152_Y
+ connect \Y $and$ls180.v:5794$1153_Y
end
- attribute \src "ls180.v:5761.36-5761.89"
- cell $and $and$ls180.v:5761$1154
+ attribute \src "ls180.v:5796.36-5796.89"
+ cell $and $and$ls180.v:5796$1154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
connect \B \builder_interface1_bank_bus_we
- connect \Y $and$ls180.v:5761$1154_Y
+ connect \Y $and$ls180.v:5796$1154_Y
end
- attribute \src "ls180.v:5761.35-5761.139"
- cell $and $and$ls180.v:5761$1156
+ attribute \src "ls180.v:5796.35-5796.139"
+ cell $and $and$ls180.v:5796$1156
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5761$1154_Y
- connect \B $eq$ls180.v:5761$1155_Y
- connect \Y $and$ls180.v:5761$1156_Y
+ connect \A $and$ls180.v:5796$1154_Y
+ connect \B $eq$ls180.v:5796$1155_Y
+ connect \Y $and$ls180.v:5796$1156_Y
end
- attribute \src "ls180.v:5762.36-5762.92"
- cell $and $and$ls180.v:5762$1158
+ attribute \src "ls180.v:5797.36-5797.92"
+ cell $and $and$ls180.v:5797$1158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
- connect \B $not$ls180.v:5762$1157_Y
- connect \Y $and$ls180.v:5762$1158_Y
+ connect \B $not$ls180.v:5797$1157_Y
+ connect \Y $and$ls180.v:5797$1158_Y
end
- attribute \src "ls180.v:5762.35-5762.142"
- cell $and $and$ls180.v:5762$1160
+ attribute \src "ls180.v:5797.35-5797.142"
+ cell $and $and$ls180.v:5797$1160
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5762$1158_Y
- connect \B $eq$ls180.v:5762$1159_Y
- connect \Y $and$ls180.v:5762$1160_Y
+ connect \A $and$ls180.v:5797$1158_Y
+ connect \B $eq$ls180.v:5797$1159_Y
+ connect \Y $and$ls180.v:5797$1160_Y
end
- attribute \src "ls180.v:5764.36-5764.89"
- cell $and $and$ls180.v:5764$1161
+ attribute \src "ls180.v:5799.36-5799.89"
+ cell $and $and$ls180.v:5799$1161
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
connect \B \builder_interface1_bank_bus_we
- connect \Y $and$ls180.v:5764$1161_Y
+ connect \Y $and$ls180.v:5799$1161_Y
end
- attribute \src "ls180.v:5764.35-5764.139"
- cell $and $and$ls180.v:5764$1163
+ attribute \src "ls180.v:5799.35-5799.139"
+ cell $and $and$ls180.v:5799$1163
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5764$1161_Y
- connect \B $eq$ls180.v:5764$1162_Y
- connect \Y $and$ls180.v:5764$1163_Y
+ connect \A $and$ls180.v:5799$1161_Y
+ connect \B $eq$ls180.v:5799$1162_Y
+ connect \Y $and$ls180.v:5799$1163_Y
end
- attribute \src "ls180.v:5765.36-5765.92"
- cell $and $and$ls180.v:5765$1165
+ attribute \src "ls180.v:5800.36-5800.92"
+ cell $and $and$ls180.v:5800$1165
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
- connect \B $not$ls180.v:5765$1164_Y
- connect \Y $and$ls180.v:5765$1165_Y
+ connect \B $not$ls180.v:5800$1164_Y
+ connect \Y $and$ls180.v:5800$1165_Y
end
- attribute \src "ls180.v:5765.35-5765.142"
- cell $and $and$ls180.v:5765$1167
+ attribute \src "ls180.v:5800.35-5800.142"
+ cell $and $and$ls180.v:5800$1167
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5765$1165_Y
- connect \B $eq$ls180.v:5765$1166_Y
- connect \Y $and$ls180.v:5765$1167_Y
+ connect \A $and$ls180.v:5800$1165_Y
+ connect \B $eq$ls180.v:5800$1166_Y
+ connect \Y $and$ls180.v:5800$1167_Y
end
- attribute \src "ls180.v:5767.36-5767.89"
- cell $and $and$ls180.v:5767$1168
+ attribute \src "ls180.v:5802.36-5802.89"
+ cell $and $and$ls180.v:5802$1168
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
connect \B \builder_interface1_bank_bus_we
- connect \Y $and$ls180.v:5767$1168_Y
+ connect \Y $and$ls180.v:5802$1168_Y
end
- attribute \src "ls180.v:5767.35-5767.139"
- cell $and $and$ls180.v:5767$1170
+ attribute \src "ls180.v:5802.35-5802.139"
+ cell $and $and$ls180.v:5802$1170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5767$1168_Y
- connect \B $eq$ls180.v:5767$1169_Y
- connect \Y $and$ls180.v:5767$1170_Y
+ connect \A $and$ls180.v:5802$1168_Y
+ connect \B $eq$ls180.v:5802$1169_Y
+ connect \Y $and$ls180.v:5802$1170_Y
end
- attribute \src "ls180.v:5768.36-5768.92"
- cell $and $and$ls180.v:5768$1172
+ attribute \src "ls180.v:5803.36-5803.92"
+ cell $and $and$ls180.v:5803$1172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
- connect \B $not$ls180.v:5768$1171_Y
- connect \Y $and$ls180.v:5768$1172_Y
+ connect \B $not$ls180.v:5803$1171_Y
+ connect \Y $and$ls180.v:5803$1172_Y
end
- attribute \src "ls180.v:5768.35-5768.142"
- cell $and $and$ls180.v:5768$1174
+ attribute \src "ls180.v:5803.35-5803.142"
+ cell $and $and$ls180.v:5803$1174
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5768$1172_Y
- connect \B $eq$ls180.v:5768$1173_Y
- connect \Y $and$ls180.v:5768$1174_Y
+ connect \A $and$ls180.v:5803$1172_Y
+ connect \B $eq$ls180.v:5803$1173_Y
+ connect \Y $and$ls180.v:5803$1174_Y
end
- attribute \src "ls180.v:5770.37-5770.90"
- cell $and $and$ls180.v:5770$1175
+ attribute \src "ls180.v:5805.37-5805.90"
+ cell $and $and$ls180.v:5805$1175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
connect \B \builder_interface1_bank_bus_we
- connect \Y $and$ls180.v:5770$1175_Y
+ connect \Y $and$ls180.v:5805$1175_Y
end
- attribute \src "ls180.v:5770.36-5770.140"
- cell $and $and$ls180.v:5770$1177
+ attribute \src "ls180.v:5805.36-5805.140"
+ cell $and $and$ls180.v:5805$1177
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5770$1175_Y
- connect \B $eq$ls180.v:5770$1176_Y
- connect \Y $and$ls180.v:5770$1177_Y
+ connect \A $and$ls180.v:5805$1175_Y
+ connect \B $eq$ls180.v:5805$1176_Y
+ connect \Y $and$ls180.v:5805$1177_Y
end
- attribute \src "ls180.v:5771.37-5771.93"
- cell $and $and$ls180.v:5771$1179
+ attribute \src "ls180.v:5806.37-5806.93"
+ cell $and $and$ls180.v:5806$1179
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
- connect \B $not$ls180.v:5771$1178_Y
- connect \Y $and$ls180.v:5771$1179_Y
+ connect \B $not$ls180.v:5806$1178_Y
+ connect \Y $and$ls180.v:5806$1179_Y
end
- attribute \src "ls180.v:5771.36-5771.143"
- cell $and $and$ls180.v:5771$1181
+ attribute \src "ls180.v:5806.36-5806.143"
+ cell $and $and$ls180.v:5806$1181
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5771$1179_Y
- connect \B $eq$ls180.v:5771$1180_Y
- connect \Y $and$ls180.v:5771$1181_Y
+ connect \A $and$ls180.v:5806$1179_Y
+ connect \B $eq$ls180.v:5806$1180_Y
+ connect \Y $and$ls180.v:5806$1181_Y
end
- attribute \src "ls180.v:5773.37-5773.90"
- cell $and $and$ls180.v:5773$1182
+ attribute \src "ls180.v:5808.37-5808.90"
+ cell $and $and$ls180.v:5808$1182
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
connect \B \builder_interface1_bank_bus_we
- connect \Y $and$ls180.v:5773$1182_Y
+ connect \Y $and$ls180.v:5808$1182_Y
end
- attribute \src "ls180.v:5773.36-5773.140"
- cell $and $and$ls180.v:5773$1184
+ attribute \src "ls180.v:5808.36-5808.140"
+ cell $and $and$ls180.v:5808$1184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5773$1182_Y
- connect \B $eq$ls180.v:5773$1183_Y
- connect \Y $and$ls180.v:5773$1184_Y
+ connect \A $and$ls180.v:5808$1182_Y
+ connect \B $eq$ls180.v:5808$1183_Y
+ connect \Y $and$ls180.v:5808$1184_Y
end
- attribute \src "ls180.v:5774.37-5774.93"
- cell $and $and$ls180.v:5774$1186
+ attribute \src "ls180.v:5809.37-5809.93"
+ cell $and $and$ls180.v:5809$1186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank1_sel
- connect \B $not$ls180.v:5774$1185_Y
- connect \Y $and$ls180.v:5774$1186_Y
- end
- attribute \src "ls180.v:5774.36-5774.143"
- cell $and $and$ls180.v:5774$1188
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5774$1186_Y
- connect \B $eq$ls180.v:5774$1187_Y
- connect \Y $and$ls180.v:5774$1188_Y
- end
- attribute \src "ls180.v:5784.40-5784.93"
- cell $and $and$ls180.v:5784$1190
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B \builder_interface2_bank_bus_we
- connect \Y $and$ls180.v:5784$1190_Y
- end
- attribute \src "ls180.v:5784.39-5784.143"
- cell $and $and$ls180.v:5784$1192
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5784$1190_Y
- connect \B $eq$ls180.v:5784$1191_Y
- connect \Y $and$ls180.v:5784$1192_Y
- end
- attribute \src "ls180.v:5785.40-5785.96"
- cell $and $and$ls180.v:5785$1194
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B $not$ls180.v:5785$1193_Y
- connect \Y $and$ls180.v:5785$1194_Y
- end
- attribute \src "ls180.v:5785.39-5785.146"
- cell $and $and$ls180.v:5785$1196
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5785$1194_Y
- connect \B $eq$ls180.v:5785$1195_Y
- connect \Y $and$ls180.v:5785$1196_Y
- end
- attribute \src "ls180.v:5787.39-5787.92"
- cell $and $and$ls180.v:5787$1197
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B \builder_interface2_bank_bus_we
- connect \Y $and$ls180.v:5787$1197_Y
- end
- attribute \src "ls180.v:5787.38-5787.142"
- cell $and $and$ls180.v:5787$1199
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5787$1197_Y
- connect \B $eq$ls180.v:5787$1198_Y
- connect \Y $and$ls180.v:5787$1199_Y
- end
- attribute \src "ls180.v:5788.39-5788.95"
- cell $and $and$ls180.v:5788$1201
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B $not$ls180.v:5788$1200_Y
- connect \Y $and$ls180.v:5788$1201_Y
- end
- attribute \src "ls180.v:5788.38-5788.145"
- cell $and $and$ls180.v:5788$1203
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5788$1201_Y
- connect \B $eq$ls180.v:5788$1202_Y
- connect \Y $and$ls180.v:5788$1203_Y
- end
- attribute \src "ls180.v:5790.39-5790.92"
- cell $and $and$ls180.v:5790$1204
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B \builder_interface2_bank_bus_we
- connect \Y $and$ls180.v:5790$1204_Y
- end
- attribute \src "ls180.v:5790.38-5790.142"
- cell $and $and$ls180.v:5790$1206
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5790$1204_Y
- connect \B $eq$ls180.v:5790$1205_Y
- connect \Y $and$ls180.v:5790$1206_Y
- end
- attribute \src "ls180.v:5791.39-5791.95"
- cell $and $and$ls180.v:5791$1208
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B $not$ls180.v:5791$1207_Y
- connect \Y $and$ls180.v:5791$1208_Y
- end
- attribute \src "ls180.v:5791.38-5791.145"
- cell $and $and$ls180.v:5791$1210
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5791$1208_Y
- connect \B $eq$ls180.v:5791$1209_Y
- connect \Y $and$ls180.v:5791$1210_Y
+ connect \B $not$ls180.v:5809$1185_Y
+ connect \Y $and$ls180.v:5809$1186_Y
end
- attribute \src "ls180.v:5793.39-5793.92"
- cell $and $and$ls180.v:5793$1211
+ attribute \src "ls180.v:5809.36-5809.143"
+ cell $and $and$ls180.v:5809$1188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B \builder_interface2_bank_bus_we
- connect \Y $and$ls180.v:5793$1211_Y
+ connect \A $and$ls180.v:5809$1186_Y
+ connect \B $eq$ls180.v:5809$1187_Y
+ connect \Y $and$ls180.v:5809$1188_Y
end
- attribute \src "ls180.v:5793.38-5793.142"
- cell $and $and$ls180.v:5793$1213
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5793$1211_Y
- connect \B $eq$ls180.v:5793$1212_Y
- connect \Y $and$ls180.v:5793$1213_Y
- end
- attribute \src "ls180.v:5794.39-5794.95"
- cell $and $and$ls180.v:5794$1215
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B $not$ls180.v:5794$1214_Y
- connect \Y $and$ls180.v:5794$1215_Y
- end
- attribute \src "ls180.v:5794.38-5794.145"
- cell $and $and$ls180.v:5794$1217
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5794$1215_Y
- connect \B $eq$ls180.v:5794$1216_Y
- connect \Y $and$ls180.v:5794$1217_Y
- end
- attribute \src "ls180.v:5796.39-5796.92"
- cell $and $and$ls180.v:5796$1218
+ attribute \src "ls180.v:5819.35-5819.88"
+ cell $and $and$ls180.v:5819$1190
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank2_sel
connect \B \builder_interface2_bank_bus_we
- connect \Y $and$ls180.v:5796$1218_Y
+ connect \Y $and$ls180.v:5819$1190_Y
end
- attribute \src "ls180.v:5796.38-5796.142"
- cell $and $and$ls180.v:5796$1220
+ attribute \src "ls180.v:5819.34-5819.136"
+ cell $and $and$ls180.v:5819$1192
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5796$1218_Y
- connect \B $eq$ls180.v:5796$1219_Y
- connect \Y $and$ls180.v:5796$1220_Y
+ connect \A $and$ls180.v:5819$1190_Y
+ connect \B $eq$ls180.v:5819$1191_Y
+ connect \Y $and$ls180.v:5819$1192_Y
end
- attribute \src "ls180.v:5797.39-5797.95"
- cell $and $and$ls180.v:5797$1222
+ attribute \src "ls180.v:5820.35-5820.91"
+ cell $and $and$ls180.v:5820$1194
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank2_sel
- connect \B $not$ls180.v:5797$1221_Y
- connect \Y $and$ls180.v:5797$1222_Y
+ connect \B $not$ls180.v:5820$1193_Y
+ connect \Y $and$ls180.v:5820$1194_Y
end
- attribute \src "ls180.v:5797.38-5797.145"
- cell $and $and$ls180.v:5797$1224
+ attribute \src "ls180.v:5820.34-5820.139"
+ cell $and $and$ls180.v:5820$1196
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5797$1222_Y
- connect \B $eq$ls180.v:5797$1223_Y
- connect \Y $and$ls180.v:5797$1224_Y
+ connect \A $and$ls180.v:5820$1194_Y
+ connect \B $eq$ls180.v:5820$1195_Y
+ connect \Y $and$ls180.v:5820$1196_Y
end
- attribute \src "ls180.v:5799.40-5799.93"
- cell $and $and$ls180.v:5799$1225
+ attribute \src "ls180.v:5822.34-5822.87"
+ cell $and $and$ls180.v:5822$1197
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank2_sel
connect \B \builder_interface2_bank_bus_we
- connect \Y $and$ls180.v:5799$1225_Y
+ connect \Y $and$ls180.v:5822$1197_Y
end
- attribute \src "ls180.v:5799.39-5799.143"
- cell $and $and$ls180.v:5799$1227
+ attribute \src "ls180.v:5822.33-5822.135"
+ cell $and $and$ls180.v:5822$1199
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5799$1225_Y
- connect \B $eq$ls180.v:5799$1226_Y
- connect \Y $and$ls180.v:5799$1227_Y
+ connect \A $and$ls180.v:5822$1197_Y
+ connect \B $eq$ls180.v:5822$1198_Y
+ connect \Y $and$ls180.v:5822$1199_Y
end
- attribute \src "ls180.v:5800.40-5800.96"
- cell $and $and$ls180.v:5800$1229
+ attribute \src "ls180.v:5823.34-5823.90"
+ cell $and $and$ls180.v:5823$1201
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank2_sel
- connect \B $not$ls180.v:5800$1228_Y
- connect \Y $and$ls180.v:5800$1229_Y
- end
- attribute \src "ls180.v:5800.39-5800.146"
- cell $and $and$ls180.v:5800$1231
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5800$1229_Y
- connect \B $eq$ls180.v:5800$1230_Y
- connect \Y $and$ls180.v:5800$1231_Y
+ connect \B $not$ls180.v:5823$1200_Y
+ connect \Y $and$ls180.v:5823$1201_Y
end
- attribute \src "ls180.v:5802.40-5802.93"
- cell $and $and$ls180.v:5802$1232
+ attribute \src "ls180.v:5823.33-5823.138"
+ cell $and $and$ls180.v:5823$1203
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B \builder_interface2_bank_bus_we
- connect \Y $and$ls180.v:5802$1232_Y
+ connect \A $and$ls180.v:5823$1201_Y
+ connect \B $eq$ls180.v:5823$1202_Y
+ connect \Y $and$ls180.v:5823$1203_Y
end
- attribute \src "ls180.v:5802.39-5802.143"
- cell $and $and$ls180.v:5802$1234
+ attribute \src "ls180.v:5833.40-5833.93"
+ cell $and $and$ls180.v:5833$1205
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5802$1232_Y
- connect \B $eq$ls180.v:5802$1233_Y
- connect \Y $and$ls180.v:5802$1234_Y
- end
- attribute \src "ls180.v:5803.40-5803.96"
- cell $and $and$ls180.v:5803$1236
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B $not$ls180.v:5803$1235_Y
- connect \Y $and$ls180.v:5803$1236_Y
- end
- attribute \src "ls180.v:5803.39-5803.146"
- cell $and $and$ls180.v:5803$1238
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5803$1236_Y
- connect \B $eq$ls180.v:5803$1237_Y
- connect \Y $and$ls180.v:5803$1238_Y
- end
- attribute \src "ls180.v:5805.40-5805.93"
- cell $and $and$ls180.v:5805$1239
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B \builder_interface2_bank_bus_we
- connect \Y $and$ls180.v:5805$1239_Y
- end
- attribute \src "ls180.v:5805.39-5805.143"
- cell $and $and$ls180.v:5805$1241
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5805$1239_Y
- connect \B $eq$ls180.v:5805$1240_Y
- connect \Y $and$ls180.v:5805$1241_Y
- end
- attribute \src "ls180.v:5806.40-5806.96"
- cell $and $and$ls180.v:5806$1243
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B $not$ls180.v:5806$1242_Y
- connect \Y $and$ls180.v:5806$1243_Y
- end
- attribute \src "ls180.v:5806.39-5806.146"
- cell $and $and$ls180.v:5806$1245
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5806$1243_Y
- connect \B $eq$ls180.v:5806$1244_Y
- connect \Y $and$ls180.v:5806$1245_Y
- end
- attribute \src "ls180.v:5808.40-5808.93"
- cell $and $and$ls180.v:5808$1246
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B \builder_interface2_bank_bus_we
- connect \Y $and$ls180.v:5808$1246_Y
+ connect \A \builder_csrbank3_sel
+ connect \B \builder_interface3_bank_bus_we
+ connect \Y $and$ls180.v:5833$1205_Y
end
- attribute \src "ls180.v:5808.39-5808.143"
- cell $and $and$ls180.v:5808$1248
+ attribute \src "ls180.v:5833.39-5833.143"
+ cell $and $and$ls180.v:5833$1207
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5808$1246_Y
- connect \B $eq$ls180.v:5808$1247_Y
- connect \Y $and$ls180.v:5808$1248_Y
+ connect \A $and$ls180.v:5833$1205_Y
+ connect \B $eq$ls180.v:5833$1206_Y
+ connect \Y $and$ls180.v:5833$1207_Y
end
- attribute \src "ls180.v:5809.40-5809.96"
- cell $and $and$ls180.v:5809$1250
+ attribute \src "ls180.v:5834.40-5834.96"
+ cell $and $and$ls180.v:5834$1209
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank2_sel
- connect \B $not$ls180.v:5809$1249_Y
- connect \Y $and$ls180.v:5809$1250_Y
+ connect \A \builder_csrbank3_sel
+ connect \B $not$ls180.v:5834$1208_Y
+ connect \Y $and$ls180.v:5834$1209_Y
end
- attribute \src "ls180.v:5809.39-5809.146"
- cell $and $and$ls180.v:5809$1252
+ attribute \src "ls180.v:5834.39-5834.146"
+ cell $and $and$ls180.v:5834$1211
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5809$1250_Y
- connect \B $eq$ls180.v:5809$1251_Y
- connect \Y $and$ls180.v:5809$1252_Y
+ connect \A $and$ls180.v:5834$1209_Y
+ connect \B $eq$ls180.v:5834$1210_Y
+ connect \Y $and$ls180.v:5834$1211_Y
end
- attribute \src "ls180.v:5821.40-5821.93"
- cell $and $and$ls180.v:5821$1254
+ attribute \src "ls180.v:5836.39-5836.92"
+ cell $and $and$ls180.v:5836$1212
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5821$1254_Y
+ connect \Y $and$ls180.v:5836$1212_Y
end
- attribute \src "ls180.v:5821.39-5821.143"
- cell $and $and$ls180.v:5821$1256
+ attribute \src "ls180.v:5836.38-5836.142"
+ cell $and $and$ls180.v:5836$1214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5821$1254_Y
- connect \B $eq$ls180.v:5821$1255_Y
- connect \Y $and$ls180.v:5821$1256_Y
+ connect \A $and$ls180.v:5836$1212_Y
+ connect \B $eq$ls180.v:5836$1213_Y
+ connect \Y $and$ls180.v:5836$1214_Y
end
- attribute \src "ls180.v:5822.40-5822.96"
- cell $and $and$ls180.v:5822$1258
+ attribute \src "ls180.v:5837.39-5837.95"
+ cell $and $and$ls180.v:5837$1216
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5822$1257_Y
- connect \Y $and$ls180.v:5822$1258_Y
+ connect \B $not$ls180.v:5837$1215_Y
+ connect \Y $and$ls180.v:5837$1216_Y
end
- attribute \src "ls180.v:5822.39-5822.146"
- cell $and $and$ls180.v:5822$1260
+ attribute \src "ls180.v:5837.38-5837.145"
+ cell $and $and$ls180.v:5837$1218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5822$1258_Y
- connect \B $eq$ls180.v:5822$1259_Y
- connect \Y $and$ls180.v:5822$1260_Y
+ connect \A $and$ls180.v:5837$1216_Y
+ connect \B $eq$ls180.v:5837$1217_Y
+ connect \Y $and$ls180.v:5837$1218_Y
end
- attribute \src "ls180.v:5824.39-5824.92"
- cell $and $and$ls180.v:5824$1261
+ attribute \src "ls180.v:5839.39-5839.92"
+ cell $and $and$ls180.v:5839$1219
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5824$1261_Y
+ connect \Y $and$ls180.v:5839$1219_Y
end
- attribute \src "ls180.v:5824.38-5824.142"
- cell $and $and$ls180.v:5824$1263
+ attribute \src "ls180.v:5839.38-5839.142"
+ cell $and $and$ls180.v:5839$1221
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5824$1261_Y
- connect \B $eq$ls180.v:5824$1262_Y
- connect \Y $and$ls180.v:5824$1263_Y
+ connect \A $and$ls180.v:5839$1219_Y
+ connect \B $eq$ls180.v:5839$1220_Y
+ connect \Y $and$ls180.v:5839$1221_Y
end
- attribute \src "ls180.v:5825.39-5825.95"
- cell $and $and$ls180.v:5825$1265
+ attribute \src "ls180.v:5840.39-5840.95"
+ cell $and $and$ls180.v:5840$1223
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5825$1264_Y
- connect \Y $and$ls180.v:5825$1265_Y
+ connect \B $not$ls180.v:5840$1222_Y
+ connect \Y $and$ls180.v:5840$1223_Y
end
- attribute \src "ls180.v:5825.38-5825.145"
- cell $and $and$ls180.v:5825$1267
+ attribute \src "ls180.v:5840.38-5840.145"
+ cell $and $and$ls180.v:5840$1225
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5825$1265_Y
- connect \B $eq$ls180.v:5825$1266_Y
- connect \Y $and$ls180.v:5825$1267_Y
+ connect \A $and$ls180.v:5840$1223_Y
+ connect \B $eq$ls180.v:5840$1224_Y
+ connect \Y $and$ls180.v:5840$1225_Y
end
- attribute \src "ls180.v:5827.39-5827.92"
- cell $and $and$ls180.v:5827$1268
+ attribute \src "ls180.v:5842.39-5842.92"
+ cell $and $and$ls180.v:5842$1226
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5827$1268_Y
+ connect \Y $and$ls180.v:5842$1226_Y
end
- attribute \src "ls180.v:5827.38-5827.142"
- cell $and $and$ls180.v:5827$1270
+ attribute \src "ls180.v:5842.38-5842.142"
+ cell $and $and$ls180.v:5842$1228
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5827$1268_Y
- connect \B $eq$ls180.v:5827$1269_Y
- connect \Y $and$ls180.v:5827$1270_Y
+ connect \A $and$ls180.v:5842$1226_Y
+ connect \B $eq$ls180.v:5842$1227_Y
+ connect \Y $and$ls180.v:5842$1228_Y
end
- attribute \src "ls180.v:5828.39-5828.95"
- cell $and $and$ls180.v:5828$1272
+ attribute \src "ls180.v:5843.39-5843.95"
+ cell $and $and$ls180.v:5843$1230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5828$1271_Y
- connect \Y $and$ls180.v:5828$1272_Y
+ connect \B $not$ls180.v:5843$1229_Y
+ connect \Y $and$ls180.v:5843$1230_Y
end
- attribute \src "ls180.v:5828.38-5828.145"
- cell $and $and$ls180.v:5828$1274
+ attribute \src "ls180.v:5843.38-5843.145"
+ cell $and $and$ls180.v:5843$1232
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5828$1272_Y
- connect \B $eq$ls180.v:5828$1273_Y
- connect \Y $and$ls180.v:5828$1274_Y
+ connect \A $and$ls180.v:5843$1230_Y
+ connect \B $eq$ls180.v:5843$1231_Y
+ connect \Y $and$ls180.v:5843$1232_Y
end
- attribute \src "ls180.v:5830.39-5830.92"
- cell $and $and$ls180.v:5830$1275
+ attribute \src "ls180.v:5845.39-5845.92"
+ cell $and $and$ls180.v:5845$1233
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5830$1275_Y
+ connect \Y $and$ls180.v:5845$1233_Y
end
- attribute \src "ls180.v:5830.38-5830.142"
- cell $and $and$ls180.v:5830$1277
+ attribute \src "ls180.v:5845.38-5845.142"
+ cell $and $and$ls180.v:5845$1235
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5830$1275_Y
- connect \B $eq$ls180.v:5830$1276_Y
- connect \Y $and$ls180.v:5830$1277_Y
+ connect \A $and$ls180.v:5845$1233_Y
+ connect \B $eq$ls180.v:5845$1234_Y
+ connect \Y $and$ls180.v:5845$1235_Y
end
- attribute \src "ls180.v:5831.39-5831.95"
- cell $and $and$ls180.v:5831$1279
+ attribute \src "ls180.v:5846.39-5846.95"
+ cell $and $and$ls180.v:5846$1237
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5831$1278_Y
- connect \Y $and$ls180.v:5831$1279_Y
+ connect \B $not$ls180.v:5846$1236_Y
+ connect \Y $and$ls180.v:5846$1237_Y
end
- attribute \src "ls180.v:5831.38-5831.145"
- cell $and $and$ls180.v:5831$1281
+ attribute \src "ls180.v:5846.38-5846.145"
+ cell $and $and$ls180.v:5846$1239
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5831$1279_Y
- connect \B $eq$ls180.v:5831$1280_Y
- connect \Y $and$ls180.v:5831$1281_Y
+ connect \A $and$ls180.v:5846$1237_Y
+ connect \B $eq$ls180.v:5846$1238_Y
+ connect \Y $and$ls180.v:5846$1239_Y
end
- attribute \src "ls180.v:5833.39-5833.92"
- cell $and $and$ls180.v:5833$1282
+ attribute \src "ls180.v:5848.40-5848.93"
+ cell $and $and$ls180.v:5848$1240
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5833$1282_Y
+ connect \Y $and$ls180.v:5848$1240_Y
end
- attribute \src "ls180.v:5833.38-5833.142"
- cell $and $and$ls180.v:5833$1284
+ attribute \src "ls180.v:5848.39-5848.143"
+ cell $and $and$ls180.v:5848$1242
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5833$1282_Y
- connect \B $eq$ls180.v:5833$1283_Y
- connect \Y $and$ls180.v:5833$1284_Y
+ connect \A $and$ls180.v:5848$1240_Y
+ connect \B $eq$ls180.v:5848$1241_Y
+ connect \Y $and$ls180.v:5848$1242_Y
end
- attribute \src "ls180.v:5834.39-5834.95"
- cell $and $and$ls180.v:5834$1286
+ attribute \src "ls180.v:5849.40-5849.96"
+ cell $and $and$ls180.v:5849$1244
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5834$1285_Y
- connect \Y $and$ls180.v:5834$1286_Y
+ connect \B $not$ls180.v:5849$1243_Y
+ connect \Y $and$ls180.v:5849$1244_Y
end
- attribute \src "ls180.v:5834.38-5834.145"
- cell $and $and$ls180.v:5834$1288
+ attribute \src "ls180.v:5849.39-5849.146"
+ cell $and $and$ls180.v:5849$1246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5834$1286_Y
- connect \B $eq$ls180.v:5834$1287_Y
- connect \Y $and$ls180.v:5834$1288_Y
+ connect \A $and$ls180.v:5849$1244_Y
+ connect \B $eq$ls180.v:5849$1245_Y
+ connect \Y $and$ls180.v:5849$1246_Y
end
- attribute \src "ls180.v:5836.40-5836.93"
- cell $and $and$ls180.v:5836$1289
+ attribute \src "ls180.v:5851.40-5851.93"
+ cell $and $and$ls180.v:5851$1247
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5836$1289_Y
+ connect \Y $and$ls180.v:5851$1247_Y
end
- attribute \src "ls180.v:5836.39-5836.143"
- cell $and $and$ls180.v:5836$1291
+ attribute \src "ls180.v:5851.39-5851.143"
+ cell $and $and$ls180.v:5851$1249
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5836$1289_Y
- connect \B $eq$ls180.v:5836$1290_Y
- connect \Y $and$ls180.v:5836$1291_Y
+ connect \A $and$ls180.v:5851$1247_Y
+ connect \B $eq$ls180.v:5851$1248_Y
+ connect \Y $and$ls180.v:5851$1249_Y
end
- attribute \src "ls180.v:5837.40-5837.96"
- cell $and $and$ls180.v:5837$1293
+ attribute \src "ls180.v:5852.40-5852.96"
+ cell $and $and$ls180.v:5852$1251
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5837$1292_Y
- connect \Y $and$ls180.v:5837$1293_Y
+ connect \B $not$ls180.v:5852$1250_Y
+ connect \Y $and$ls180.v:5852$1251_Y
end
- attribute \src "ls180.v:5837.39-5837.146"
- cell $and $and$ls180.v:5837$1295
+ attribute \src "ls180.v:5852.39-5852.146"
+ cell $and $and$ls180.v:5852$1253
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5837$1293_Y
- connect \B $eq$ls180.v:5837$1294_Y
- connect \Y $and$ls180.v:5837$1295_Y
+ connect \A $and$ls180.v:5852$1251_Y
+ connect \B $eq$ls180.v:5852$1252_Y
+ connect \Y $and$ls180.v:5852$1253_Y
end
- attribute \src "ls180.v:5839.40-5839.93"
- cell $and $and$ls180.v:5839$1296
+ attribute \src "ls180.v:5854.40-5854.93"
+ cell $and $and$ls180.v:5854$1254
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5839$1296_Y
+ connect \Y $and$ls180.v:5854$1254_Y
end
- attribute \src "ls180.v:5839.39-5839.143"
- cell $and $and$ls180.v:5839$1298
+ attribute \src "ls180.v:5854.39-5854.143"
+ cell $and $and$ls180.v:5854$1256
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5839$1296_Y
- connect \B $eq$ls180.v:5839$1297_Y
- connect \Y $and$ls180.v:5839$1298_Y
+ connect \A $and$ls180.v:5854$1254_Y
+ connect \B $eq$ls180.v:5854$1255_Y
+ connect \Y $and$ls180.v:5854$1256_Y
end
- attribute \src "ls180.v:5840.40-5840.96"
- cell $and $and$ls180.v:5840$1300
+ attribute \src "ls180.v:5855.40-5855.96"
+ cell $and $and$ls180.v:5855$1258
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5840$1299_Y
- connect \Y $and$ls180.v:5840$1300_Y
+ connect \B $not$ls180.v:5855$1257_Y
+ connect \Y $and$ls180.v:5855$1258_Y
end
- attribute \src "ls180.v:5840.39-5840.146"
- cell $and $and$ls180.v:5840$1302
+ attribute \src "ls180.v:5855.39-5855.146"
+ cell $and $and$ls180.v:5855$1260
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5840$1300_Y
- connect \B $eq$ls180.v:5840$1301_Y
- connect \Y $and$ls180.v:5840$1302_Y
+ connect \A $and$ls180.v:5855$1258_Y
+ connect \B $eq$ls180.v:5855$1259_Y
+ connect \Y $and$ls180.v:5855$1260_Y
end
- attribute \src "ls180.v:5842.40-5842.93"
- cell $and $and$ls180.v:5842$1303
+ attribute \src "ls180.v:5857.40-5857.93"
+ cell $and $and$ls180.v:5857$1261
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5842$1303_Y
+ connect \Y $and$ls180.v:5857$1261_Y
end
- attribute \src "ls180.v:5842.39-5842.143"
- cell $and $and$ls180.v:5842$1305
+ attribute \src "ls180.v:5857.39-5857.143"
+ cell $and $and$ls180.v:5857$1263
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5842$1303_Y
- connect \B $eq$ls180.v:5842$1304_Y
- connect \Y $and$ls180.v:5842$1305_Y
+ connect \A $and$ls180.v:5857$1261_Y
+ connect \B $eq$ls180.v:5857$1262_Y
+ connect \Y $and$ls180.v:5857$1263_Y
end
- attribute \src "ls180.v:5843.40-5843.96"
- cell $and $and$ls180.v:5843$1307
+ attribute \src "ls180.v:5858.40-5858.96"
+ cell $and $and$ls180.v:5858$1265
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5843$1306_Y
- connect \Y $and$ls180.v:5843$1307_Y
+ connect \B $not$ls180.v:5858$1264_Y
+ connect \Y $and$ls180.v:5858$1265_Y
end
- attribute \src "ls180.v:5843.39-5843.146"
- cell $and $and$ls180.v:5843$1309
+ attribute \src "ls180.v:5858.39-5858.146"
+ cell $and $and$ls180.v:5858$1267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5843$1307_Y
- connect \B $eq$ls180.v:5843$1308_Y
- connect \Y $and$ls180.v:5843$1309_Y
+ connect \A $and$ls180.v:5858$1265_Y
+ connect \B $eq$ls180.v:5858$1266_Y
+ connect \Y $and$ls180.v:5858$1267_Y
end
- attribute \src "ls180.v:5845.40-5845.93"
- cell $and $and$ls180.v:5845$1310
+ attribute \src "ls180.v:5870.40-5870.93"
+ cell $and $and$ls180.v:5870$1269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank3_sel
- connect \B \builder_interface3_bank_bus_we
- connect \Y $and$ls180.v:5845$1310_Y
+ connect \A \builder_csrbank4_sel
+ connect \B \builder_interface4_bank_bus_we
+ connect \Y $and$ls180.v:5870$1269_Y
end
- attribute \src "ls180.v:5845.39-5845.143"
- cell $and $and$ls180.v:5845$1312
+ attribute \src "ls180.v:5870.39-5870.143"
+ cell $and $and$ls180.v:5870$1271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5845$1310_Y
- connect \B $eq$ls180.v:5845$1311_Y
- connect \Y $and$ls180.v:5845$1312_Y
+ connect \A $and$ls180.v:5870$1269_Y
+ connect \B $eq$ls180.v:5870$1270_Y
+ connect \Y $and$ls180.v:5870$1271_Y
end
- attribute \src "ls180.v:5846.40-5846.96"
- cell $and $and$ls180.v:5846$1314
+ attribute \src "ls180.v:5871.40-5871.96"
+ cell $and $and$ls180.v:5871$1273
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank3_sel
- connect \B $not$ls180.v:5846$1313_Y
- connect \Y $and$ls180.v:5846$1314_Y
+ connect \A \builder_csrbank4_sel
+ connect \B $not$ls180.v:5871$1272_Y
+ connect \Y $and$ls180.v:5871$1273_Y
end
- attribute \src "ls180.v:5846.39-5846.146"
- cell $and $and$ls180.v:5846$1316
+ attribute \src "ls180.v:5871.39-5871.146"
+ cell $and $and$ls180.v:5871$1275
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5846$1314_Y
- connect \B $eq$ls180.v:5846$1315_Y
- connect \Y $and$ls180.v:5846$1316_Y
+ connect \A $and$ls180.v:5871$1273_Y
+ connect \B $eq$ls180.v:5871$1274_Y
+ connect \Y $and$ls180.v:5871$1275_Y
end
- attribute \src "ls180.v:5858.42-5858.95"
- cell $and $and$ls180.v:5858$1318
+ attribute \src "ls180.v:5873.39-5873.92"
+ cell $and $and$ls180.v:5873$1276
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5858$1318_Y
+ connect \Y $and$ls180.v:5873$1276_Y
end
- attribute \src "ls180.v:5858.41-5858.145"
- cell $and $and$ls180.v:5858$1320
+ attribute \src "ls180.v:5873.38-5873.142"
+ cell $and $and$ls180.v:5873$1278
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5858$1318_Y
- connect \B $eq$ls180.v:5858$1319_Y
- connect \Y $and$ls180.v:5858$1320_Y
+ connect \A $and$ls180.v:5873$1276_Y
+ connect \B $eq$ls180.v:5873$1277_Y
+ connect \Y $and$ls180.v:5873$1278_Y
end
- attribute \src "ls180.v:5859.42-5859.98"
- cell $and $and$ls180.v:5859$1322
+ attribute \src "ls180.v:5874.39-5874.95"
+ cell $and $and$ls180.v:5874$1280
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5859$1321_Y
- connect \Y $and$ls180.v:5859$1322_Y
+ connect \B $not$ls180.v:5874$1279_Y
+ connect \Y $and$ls180.v:5874$1280_Y
end
- attribute \src "ls180.v:5859.41-5859.148"
- cell $and $and$ls180.v:5859$1324
+ attribute \src "ls180.v:5874.38-5874.145"
+ cell $and $and$ls180.v:5874$1282
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5859$1322_Y
- connect \B $eq$ls180.v:5859$1323_Y
- connect \Y $and$ls180.v:5859$1324_Y
+ connect \A $and$ls180.v:5874$1280_Y
+ connect \B $eq$ls180.v:5874$1281_Y
+ connect \Y $and$ls180.v:5874$1282_Y
end
- attribute \src "ls180.v:5861.42-5861.95"
- cell $and $and$ls180.v:5861$1325
+ attribute \src "ls180.v:5876.39-5876.92"
+ cell $and $and$ls180.v:5876$1283
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5861$1325_Y
+ connect \Y $and$ls180.v:5876$1283_Y
end
- attribute \src "ls180.v:5861.41-5861.145"
- cell $and $and$ls180.v:5861$1327
+ attribute \src "ls180.v:5876.38-5876.142"
+ cell $and $and$ls180.v:5876$1285
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5861$1325_Y
- connect \B $eq$ls180.v:5861$1326_Y
- connect \Y $and$ls180.v:5861$1327_Y
+ connect \A $and$ls180.v:5876$1283_Y
+ connect \B $eq$ls180.v:5876$1284_Y
+ connect \Y $and$ls180.v:5876$1285_Y
end
- attribute \src "ls180.v:5862.42-5862.98"
- cell $and $and$ls180.v:5862$1329
+ attribute \src "ls180.v:5877.39-5877.95"
+ cell $and $and$ls180.v:5877$1287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5862$1328_Y
- connect \Y $and$ls180.v:5862$1329_Y
+ connect \B $not$ls180.v:5877$1286_Y
+ connect \Y $and$ls180.v:5877$1287_Y
end
- attribute \src "ls180.v:5862.41-5862.148"
- cell $and $and$ls180.v:5862$1331
+ attribute \src "ls180.v:5877.38-5877.145"
+ cell $and $and$ls180.v:5877$1289
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5862$1329_Y
- connect \B $eq$ls180.v:5862$1330_Y
- connect \Y $and$ls180.v:5862$1331_Y
+ connect \A $and$ls180.v:5877$1287_Y
+ connect \B $eq$ls180.v:5877$1288_Y
+ connect \Y $and$ls180.v:5877$1289_Y
end
- attribute \src "ls180.v:5864.42-5864.95"
- cell $and $and$ls180.v:5864$1332
+ attribute \src "ls180.v:5879.39-5879.92"
+ cell $and $and$ls180.v:5879$1290
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5864$1332_Y
+ connect \Y $and$ls180.v:5879$1290_Y
end
- attribute \src "ls180.v:5864.41-5864.145"
- cell $and $and$ls180.v:5864$1334
+ attribute \src "ls180.v:5879.38-5879.142"
+ cell $and $and$ls180.v:5879$1292
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5864$1332_Y
- connect \B $eq$ls180.v:5864$1333_Y
- connect \Y $and$ls180.v:5864$1334_Y
+ connect \A $and$ls180.v:5879$1290_Y
+ connect \B $eq$ls180.v:5879$1291_Y
+ connect \Y $and$ls180.v:5879$1292_Y
end
- attribute \src "ls180.v:5865.42-5865.98"
- cell $and $and$ls180.v:5865$1336
+ attribute \src "ls180.v:5880.39-5880.95"
+ cell $and $and$ls180.v:5880$1294
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5865$1335_Y
- connect \Y $and$ls180.v:5865$1336_Y
+ connect \B $not$ls180.v:5880$1293_Y
+ connect \Y $and$ls180.v:5880$1294_Y
end
- attribute \src "ls180.v:5865.41-5865.148"
- cell $and $and$ls180.v:5865$1338
+ attribute \src "ls180.v:5880.38-5880.145"
+ cell $and $and$ls180.v:5880$1296
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5865$1336_Y
- connect \B $eq$ls180.v:5865$1337_Y
- connect \Y $and$ls180.v:5865$1338_Y
+ connect \A $and$ls180.v:5880$1294_Y
+ connect \B $eq$ls180.v:5880$1295_Y
+ connect \Y $and$ls180.v:5880$1296_Y
end
- attribute \src "ls180.v:5867.42-5867.95"
- cell $and $and$ls180.v:5867$1339
+ attribute \src "ls180.v:5882.39-5882.92"
+ cell $and $and$ls180.v:5882$1297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5867$1339_Y
+ connect \Y $and$ls180.v:5882$1297_Y
end
- attribute \src "ls180.v:5867.41-5867.145"
- cell $and $and$ls180.v:5867$1341
+ attribute \src "ls180.v:5882.38-5882.142"
+ cell $and $and$ls180.v:5882$1299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5867$1339_Y
- connect \B $eq$ls180.v:5867$1340_Y
- connect \Y $and$ls180.v:5867$1341_Y
+ connect \A $and$ls180.v:5882$1297_Y
+ connect \B $eq$ls180.v:5882$1298_Y
+ connect \Y $and$ls180.v:5882$1299_Y
end
- attribute \src "ls180.v:5868.42-5868.98"
- cell $and $and$ls180.v:5868$1343
+ attribute \src "ls180.v:5883.39-5883.95"
+ cell $and $and$ls180.v:5883$1301
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5868$1342_Y
- connect \Y $and$ls180.v:5868$1343_Y
+ connect \B $not$ls180.v:5883$1300_Y
+ connect \Y $and$ls180.v:5883$1301_Y
end
- attribute \src "ls180.v:5868.41-5868.148"
- cell $and $and$ls180.v:5868$1345
+ attribute \src "ls180.v:5883.38-5883.145"
+ cell $and $and$ls180.v:5883$1303
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5868$1343_Y
- connect \B $eq$ls180.v:5868$1344_Y
- connect \Y $and$ls180.v:5868$1345_Y
+ connect \A $and$ls180.v:5883$1301_Y
+ connect \B $eq$ls180.v:5883$1302_Y
+ connect \Y $and$ls180.v:5883$1303_Y
end
- attribute \src "ls180.v:5870.42-5870.95"
- cell $and $and$ls180.v:5870$1346
+ attribute \src "ls180.v:5885.40-5885.93"
+ cell $and $and$ls180.v:5885$1304
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5870$1346_Y
+ connect \Y $and$ls180.v:5885$1304_Y
end
- attribute \src "ls180.v:5870.41-5870.145"
- cell $and $and$ls180.v:5870$1348
+ attribute \src "ls180.v:5885.39-5885.143"
+ cell $and $and$ls180.v:5885$1306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5870$1346_Y
- connect \B $eq$ls180.v:5870$1347_Y
- connect \Y $and$ls180.v:5870$1348_Y
+ connect \A $and$ls180.v:5885$1304_Y
+ connect \B $eq$ls180.v:5885$1305_Y
+ connect \Y $and$ls180.v:5885$1306_Y
end
- attribute \src "ls180.v:5871.42-5871.98"
- cell $and $and$ls180.v:5871$1350
+ attribute \src "ls180.v:5886.40-5886.96"
+ cell $and $and$ls180.v:5886$1308
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5871$1349_Y
- connect \Y $and$ls180.v:5871$1350_Y
+ connect \B $not$ls180.v:5886$1307_Y
+ connect \Y $and$ls180.v:5886$1308_Y
end
- attribute \src "ls180.v:5871.41-5871.148"
- cell $and $and$ls180.v:5871$1352
+ attribute \src "ls180.v:5886.39-5886.146"
+ cell $and $and$ls180.v:5886$1310
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5871$1350_Y
- connect \B $eq$ls180.v:5871$1351_Y
- connect \Y $and$ls180.v:5871$1352_Y
+ connect \A $and$ls180.v:5886$1308_Y
+ connect \B $eq$ls180.v:5886$1309_Y
+ connect \Y $and$ls180.v:5886$1310_Y
end
- attribute \src "ls180.v:5873.42-5873.95"
- cell $and $and$ls180.v:5873$1353
+ attribute \src "ls180.v:5888.40-5888.93"
+ cell $and $and$ls180.v:5888$1311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5873$1353_Y
+ connect \Y $and$ls180.v:5888$1311_Y
end
- attribute \src "ls180.v:5873.41-5873.145"
- cell $and $and$ls180.v:5873$1355
+ attribute \src "ls180.v:5888.39-5888.143"
+ cell $and $and$ls180.v:5888$1313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5873$1353_Y
- connect \B $eq$ls180.v:5873$1354_Y
- connect \Y $and$ls180.v:5873$1355_Y
+ connect \A $and$ls180.v:5888$1311_Y
+ connect \B $eq$ls180.v:5888$1312_Y
+ connect \Y $and$ls180.v:5888$1313_Y
end
- attribute \src "ls180.v:5874.42-5874.98"
- cell $and $and$ls180.v:5874$1357
+ attribute \src "ls180.v:5889.40-5889.96"
+ cell $and $and$ls180.v:5889$1315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5874$1356_Y
- connect \Y $and$ls180.v:5874$1357_Y
+ connect \B $not$ls180.v:5889$1314_Y
+ connect \Y $and$ls180.v:5889$1315_Y
end
- attribute \src "ls180.v:5874.41-5874.148"
- cell $and $and$ls180.v:5874$1359
+ attribute \src "ls180.v:5889.39-5889.146"
+ cell $and $and$ls180.v:5889$1317
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5874$1357_Y
- connect \B $eq$ls180.v:5874$1358_Y
- connect \Y $and$ls180.v:5874$1359_Y
+ connect \A $and$ls180.v:5889$1315_Y
+ connect \B $eq$ls180.v:5889$1316_Y
+ connect \Y $and$ls180.v:5889$1317_Y
end
- attribute \src "ls180.v:5876.42-5876.95"
- cell $and $and$ls180.v:5876$1360
+ attribute \src "ls180.v:5891.40-5891.93"
+ cell $and $and$ls180.v:5891$1318
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5876$1360_Y
+ connect \Y $and$ls180.v:5891$1318_Y
end
- attribute \src "ls180.v:5876.41-5876.145"
- cell $and $and$ls180.v:5876$1362
+ attribute \src "ls180.v:5891.39-5891.143"
+ cell $and $and$ls180.v:5891$1320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5876$1360_Y
- connect \B $eq$ls180.v:5876$1361_Y
- connect \Y $and$ls180.v:5876$1362_Y
+ connect \A $and$ls180.v:5891$1318_Y
+ connect \B $eq$ls180.v:5891$1319_Y
+ connect \Y $and$ls180.v:5891$1320_Y
end
- attribute \src "ls180.v:5877.42-5877.98"
- cell $and $and$ls180.v:5877$1364
+ attribute \src "ls180.v:5892.40-5892.96"
+ cell $and $and$ls180.v:5892$1322
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5877$1363_Y
- connect \Y $and$ls180.v:5877$1364_Y
+ connect \B $not$ls180.v:5892$1321_Y
+ connect \Y $and$ls180.v:5892$1322_Y
end
- attribute \src "ls180.v:5877.41-5877.148"
- cell $and $and$ls180.v:5877$1366
+ attribute \src "ls180.v:5892.39-5892.146"
+ cell $and $and$ls180.v:5892$1324
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5877$1364_Y
- connect \B $eq$ls180.v:5877$1365_Y
- connect \Y $and$ls180.v:5877$1366_Y
+ connect \A $and$ls180.v:5892$1322_Y
+ connect \B $eq$ls180.v:5892$1323_Y
+ connect \Y $and$ls180.v:5892$1324_Y
end
- attribute \src "ls180.v:5879.42-5879.95"
- cell $and $and$ls180.v:5879$1367
+ attribute \src "ls180.v:5894.40-5894.93"
+ cell $and $and$ls180.v:5894$1325
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5879$1367_Y
+ connect \Y $and$ls180.v:5894$1325_Y
end
- attribute \src "ls180.v:5879.41-5879.145"
- cell $and $and$ls180.v:5879$1369
+ attribute \src "ls180.v:5894.39-5894.143"
+ cell $and $and$ls180.v:5894$1327
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5879$1367_Y
- connect \B $eq$ls180.v:5879$1368_Y
- connect \Y $and$ls180.v:5879$1369_Y
+ connect \A $and$ls180.v:5894$1325_Y
+ connect \B $eq$ls180.v:5894$1326_Y
+ connect \Y $and$ls180.v:5894$1327_Y
end
- attribute \src "ls180.v:5880.42-5880.98"
- cell $and $and$ls180.v:5880$1371
+ attribute \src "ls180.v:5895.40-5895.96"
+ cell $and $and$ls180.v:5895$1329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5880$1370_Y
- connect \Y $and$ls180.v:5880$1371_Y
+ connect \B $not$ls180.v:5895$1328_Y
+ connect \Y $and$ls180.v:5895$1329_Y
end
- attribute \src "ls180.v:5880.41-5880.148"
- cell $and $and$ls180.v:5880$1373
+ attribute \src "ls180.v:5895.39-5895.146"
+ cell $and $and$ls180.v:5895$1331
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5880$1371_Y
- connect \B $eq$ls180.v:5880$1372_Y
- connect \Y $and$ls180.v:5880$1373_Y
+ connect \A $and$ls180.v:5895$1329_Y
+ connect \B $eq$ls180.v:5895$1330_Y
+ connect \Y $and$ls180.v:5895$1331_Y
end
- attribute \src "ls180.v:5882.44-5882.97"
- cell $and $and$ls180.v:5882$1374
+ attribute \src "ls180.v:5907.42-5907.95"
+ cell $and $and$ls180.v:5907$1333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5882$1374_Y
+ connect \A \builder_csrbank5_sel
+ connect \B \builder_interface5_bank_bus_we
+ connect \Y $and$ls180.v:5907$1333_Y
end
- attribute \src "ls180.v:5882.43-5882.147"
- cell $and $and$ls180.v:5882$1376
+ attribute \src "ls180.v:5907.41-5907.145"
+ cell $and $and$ls180.v:5907$1335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5882$1374_Y
- connect \B $eq$ls180.v:5882$1375_Y
- connect \Y $and$ls180.v:5882$1376_Y
+ connect \A $and$ls180.v:5907$1333_Y
+ connect \B $eq$ls180.v:5907$1334_Y
+ connect \Y $and$ls180.v:5907$1335_Y
end
- attribute \src "ls180.v:5883.44-5883.100"
- cell $and $and$ls180.v:5883$1378
+ attribute \src "ls180.v:5908.42-5908.98"
+ cell $and $and$ls180.v:5908$1337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5883$1377_Y
- connect \Y $and$ls180.v:5883$1378_Y
+ connect \A \builder_csrbank5_sel
+ connect \B $not$ls180.v:5908$1336_Y
+ connect \Y $and$ls180.v:5908$1337_Y
end
- attribute \src "ls180.v:5883.43-5883.150"
- cell $and $and$ls180.v:5883$1380
+ attribute \src "ls180.v:5908.41-5908.148"
+ cell $and $and$ls180.v:5908$1339
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5883$1378_Y
- connect \B $eq$ls180.v:5883$1379_Y
- connect \Y $and$ls180.v:5883$1380_Y
+ connect \A $and$ls180.v:5908$1337_Y
+ connect \B $eq$ls180.v:5908$1338_Y
+ connect \Y $and$ls180.v:5908$1339_Y
end
- attribute \src "ls180.v:5885.44-5885.97"
- cell $and $and$ls180.v:5885$1381
+ attribute \src "ls180.v:5910.42-5910.95"
+ cell $and $and$ls180.v:5910$1340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5885$1381_Y
+ connect \A \builder_csrbank5_sel
+ connect \B \builder_interface5_bank_bus_we
+ connect \Y $and$ls180.v:5910$1340_Y
end
- attribute \src "ls180.v:5885.43-5885.147"
- cell $and $and$ls180.v:5885$1383
+ attribute \src "ls180.v:5910.41-5910.145"
+ cell $and $and$ls180.v:5910$1342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5885$1381_Y
- connect \B $eq$ls180.v:5885$1382_Y
- connect \Y $and$ls180.v:5885$1383_Y
+ connect \A $and$ls180.v:5910$1340_Y
+ connect \B $eq$ls180.v:5910$1341_Y
+ connect \Y $and$ls180.v:5910$1342_Y
end
- attribute \src "ls180.v:5886.44-5886.100"
- cell $and $and$ls180.v:5886$1385
+ attribute \src "ls180.v:5911.42-5911.98"
+ cell $and $and$ls180.v:5911$1344
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5886$1384_Y
- connect \Y $and$ls180.v:5886$1385_Y
+ connect \A \builder_csrbank5_sel
+ connect \B $not$ls180.v:5911$1343_Y
+ connect \Y $and$ls180.v:5911$1344_Y
end
- attribute \src "ls180.v:5886.43-5886.150"
- cell $and $and$ls180.v:5886$1387
+ attribute \src "ls180.v:5911.41-5911.148"
+ cell $and $and$ls180.v:5911$1346
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5886$1385_Y
- connect \B $eq$ls180.v:5886$1386_Y
- connect \Y $and$ls180.v:5886$1387_Y
+ connect \A $and$ls180.v:5911$1344_Y
+ connect \B $eq$ls180.v:5911$1345_Y
+ connect \Y $and$ls180.v:5911$1346_Y
end
- attribute \src "ls180.v:5888.44-5888.97"
- cell $and $and$ls180.v:5888$1388
+ attribute \src "ls180.v:5913.42-5913.95"
+ cell $and $and$ls180.v:5913$1347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5888$1388_Y
+ connect \A \builder_csrbank5_sel
+ connect \B \builder_interface5_bank_bus_we
+ connect \Y $and$ls180.v:5913$1347_Y
end
- attribute \src "ls180.v:5888.43-5888.148"
- cell $and $and$ls180.v:5888$1390
+ attribute \src "ls180.v:5913.41-5913.145"
+ cell $and $and$ls180.v:5913$1349
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5888$1388_Y
- connect \B $eq$ls180.v:5888$1389_Y
- connect \Y $and$ls180.v:5888$1390_Y
+ connect \A $and$ls180.v:5913$1347_Y
+ connect \B $eq$ls180.v:5913$1348_Y
+ connect \Y $and$ls180.v:5913$1349_Y
end
- attribute \src "ls180.v:5889.44-5889.100"
- cell $and $and$ls180.v:5889$1392
+ attribute \src "ls180.v:5914.42-5914.98"
+ cell $and $and$ls180.v:5914$1351
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5889$1391_Y
- connect \Y $and$ls180.v:5889$1392_Y
+ connect \A \builder_csrbank5_sel
+ connect \B $not$ls180.v:5914$1350_Y
+ connect \Y $and$ls180.v:5914$1351_Y
end
- attribute \src "ls180.v:5889.43-5889.151"
- cell $and $and$ls180.v:5889$1394
+ attribute \src "ls180.v:5914.41-5914.148"
+ cell $and $and$ls180.v:5914$1353
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5889$1392_Y
- connect \B $eq$ls180.v:5889$1393_Y
- connect \Y $and$ls180.v:5889$1394_Y
+ connect \A $and$ls180.v:5914$1351_Y
+ connect \B $eq$ls180.v:5914$1352_Y
+ connect \Y $and$ls180.v:5914$1353_Y
end
- attribute \src "ls180.v:5891.44-5891.97"
- cell $and $and$ls180.v:5891$1395
+ attribute \src "ls180.v:5916.42-5916.95"
+ cell $and $and$ls180.v:5916$1354
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5891$1395_Y
+ connect \A \builder_csrbank5_sel
+ connect \B \builder_interface5_bank_bus_we
+ connect \Y $and$ls180.v:5916$1354_Y
end
- attribute \src "ls180.v:5891.43-5891.148"
- cell $and $and$ls180.v:5891$1397
+ attribute \src "ls180.v:5916.41-5916.145"
+ cell $and $and$ls180.v:5916$1356
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5891$1395_Y
- connect \B $eq$ls180.v:5891$1396_Y
- connect \Y $and$ls180.v:5891$1397_Y
+ connect \A $and$ls180.v:5916$1354_Y
+ connect \B $eq$ls180.v:5916$1355_Y
+ connect \Y $and$ls180.v:5916$1356_Y
end
- attribute \src "ls180.v:5892.44-5892.100"
- cell $and $and$ls180.v:5892$1399
+ attribute \src "ls180.v:5917.42-5917.98"
+ cell $and $and$ls180.v:5917$1358
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5892$1398_Y
- connect \Y $and$ls180.v:5892$1399_Y
+ connect \A \builder_csrbank5_sel
+ connect \B $not$ls180.v:5917$1357_Y
+ connect \Y $and$ls180.v:5917$1358_Y
end
- attribute \src "ls180.v:5892.43-5892.151"
- cell $and $and$ls180.v:5892$1401
+ attribute \src "ls180.v:5917.41-5917.148"
+ cell $and $and$ls180.v:5917$1360
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5892$1399_Y
- connect \B $eq$ls180.v:5892$1400_Y
- connect \Y $and$ls180.v:5892$1401_Y
+ connect \A $and$ls180.v:5917$1358_Y
+ connect \B $eq$ls180.v:5917$1359_Y
+ connect \Y $and$ls180.v:5917$1360_Y
end
- attribute \src "ls180.v:5894.44-5894.97"
- cell $and $and$ls180.v:5894$1402
+ attribute \src "ls180.v:5919.42-5919.95"
+ cell $and $and$ls180.v:5919$1361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5894$1402_Y
+ connect \A \builder_csrbank5_sel
+ connect \B \builder_interface5_bank_bus_we
+ connect \Y $and$ls180.v:5919$1361_Y
end
- attribute \src "ls180.v:5894.43-5894.148"
- cell $and $and$ls180.v:5894$1404
+ attribute \src "ls180.v:5919.41-5919.145"
+ cell $and $and$ls180.v:5919$1363
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5894$1402_Y
- connect \B $eq$ls180.v:5894$1403_Y
- connect \Y $and$ls180.v:5894$1404_Y
+ connect \A $and$ls180.v:5919$1361_Y
+ connect \B $eq$ls180.v:5919$1362_Y
+ connect \Y $and$ls180.v:5919$1363_Y
end
- attribute \src "ls180.v:5895.44-5895.100"
- cell $and $and$ls180.v:5895$1406
+ attribute \src "ls180.v:5920.42-5920.98"
+ cell $and $and$ls180.v:5920$1365
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5895$1405_Y
- connect \Y $and$ls180.v:5895$1406_Y
+ connect \A \builder_csrbank5_sel
+ connect \B $not$ls180.v:5920$1364_Y
+ connect \Y $and$ls180.v:5920$1365_Y
end
- attribute \src "ls180.v:5895.43-5895.151"
- cell $and $and$ls180.v:5895$1408
+ attribute \src "ls180.v:5920.41-5920.148"
+ cell $and $and$ls180.v:5920$1367
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5895$1406_Y
- connect \B $eq$ls180.v:5895$1407_Y
- connect \Y $and$ls180.v:5895$1408_Y
+ connect \A $and$ls180.v:5920$1365_Y
+ connect \B $eq$ls180.v:5920$1366_Y
+ connect \Y $and$ls180.v:5920$1367_Y
end
- attribute \src "ls180.v:5897.41-5897.94"
- cell $and $and$ls180.v:5897$1409
+ attribute \src "ls180.v:5922.42-5922.95"
+ cell $and $and$ls180.v:5922$1368
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5897$1409_Y
+ connect \A \builder_csrbank5_sel
+ connect \B \builder_interface5_bank_bus_we
+ connect \Y $and$ls180.v:5922$1368_Y
end
- attribute \src "ls180.v:5897.40-5897.145"
- cell $and $and$ls180.v:5897$1411
+ attribute \src "ls180.v:5922.41-5922.145"
+ cell $and $and$ls180.v:5922$1370
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5897$1409_Y
- connect \B $eq$ls180.v:5897$1410_Y
- connect \Y $and$ls180.v:5897$1411_Y
+ connect \A $and$ls180.v:5922$1368_Y
+ connect \B $eq$ls180.v:5922$1369_Y
+ connect \Y $and$ls180.v:5922$1370_Y
end
- attribute \src "ls180.v:5898.41-5898.97"
- cell $and $and$ls180.v:5898$1413
+ attribute \src "ls180.v:5923.42-5923.98"
+ cell $and $and$ls180.v:5923$1372
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5898$1412_Y
- connect \Y $and$ls180.v:5898$1413_Y
+ connect \A \builder_csrbank5_sel
+ connect \B $not$ls180.v:5923$1371_Y
+ connect \Y $and$ls180.v:5923$1372_Y
end
- attribute \src "ls180.v:5898.40-5898.148"
- cell $and $and$ls180.v:5898$1415
+ attribute \src "ls180.v:5923.41-5923.148"
+ cell $and $and$ls180.v:5923$1374
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5898$1413_Y
- connect \B $eq$ls180.v:5898$1414_Y
- connect \Y $and$ls180.v:5898$1415_Y
+ connect \A $and$ls180.v:5923$1372_Y
+ connect \B $eq$ls180.v:5923$1373_Y
+ connect \Y $and$ls180.v:5923$1374_Y
end
- attribute \src "ls180.v:5900.42-5900.95"
- cell $and $and$ls180.v:5900$1416
+ attribute \src "ls180.v:5925.42-5925.95"
+ cell $and $and$ls180.v:5925$1375
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B \builder_interface4_bank_bus_we
- connect \Y $and$ls180.v:5900$1416_Y
+ connect \A \builder_csrbank5_sel
+ connect \B \builder_interface5_bank_bus_we
+ connect \Y $and$ls180.v:5925$1375_Y
end
- attribute \src "ls180.v:5900.41-5900.146"
- cell $and $and$ls180.v:5900$1418
+ attribute \src "ls180.v:5925.41-5925.145"
+ cell $and $and$ls180.v:5925$1377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5900$1416_Y
- connect \B $eq$ls180.v:5900$1417_Y
- connect \Y $and$ls180.v:5900$1418_Y
+ connect \A $and$ls180.v:5925$1375_Y
+ connect \B $eq$ls180.v:5925$1376_Y
+ connect \Y $and$ls180.v:5925$1377_Y
end
- attribute \src "ls180.v:5901.42-5901.98"
- cell $and $and$ls180.v:5901$1420
+ attribute \src "ls180.v:5926.42-5926.98"
+ cell $and $and$ls180.v:5926$1379
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank4_sel
- connect \B $not$ls180.v:5901$1419_Y
- connect \Y $and$ls180.v:5901$1420_Y
+ connect \A \builder_csrbank5_sel
+ connect \B $not$ls180.v:5926$1378_Y
+ connect \Y $and$ls180.v:5926$1379_Y
end
- attribute \src "ls180.v:5901.41-5901.149"
- cell $and $and$ls180.v:5901$1422
+ attribute \src "ls180.v:5926.41-5926.148"
+ cell $and $and$ls180.v:5926$1381
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5901$1420_Y
- connect \B $eq$ls180.v:5901$1421_Y
- connect \Y $and$ls180.v:5901$1422_Y
+ connect \A $and$ls180.v:5926$1379_Y
+ connect \B $eq$ls180.v:5926$1380_Y
+ connect \Y $and$ls180.v:5926$1381_Y
end
- attribute \src "ls180.v:5920.46-5920.99"
- cell $and $and$ls180.v:5920$1424
+ attribute \src "ls180.v:5928.42-5928.95"
+ cell $and $and$ls180.v:5928$1382
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5920$1424_Y
+ connect \Y $and$ls180.v:5928$1382_Y
end
- attribute \src "ls180.v:5920.45-5920.149"
- cell $and $and$ls180.v:5920$1426
+ attribute \src "ls180.v:5928.41-5928.145"
+ cell $and $and$ls180.v:5928$1384
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5920$1424_Y
- connect \B $eq$ls180.v:5920$1425_Y
- connect \Y $and$ls180.v:5920$1426_Y
+ connect \A $and$ls180.v:5928$1382_Y
+ connect \B $eq$ls180.v:5928$1383_Y
+ connect \Y $and$ls180.v:5928$1384_Y
end
- attribute \src "ls180.v:5921.46-5921.102"
- cell $and $and$ls180.v:5921$1428
+ attribute \src "ls180.v:5929.42-5929.98"
+ cell $and $and$ls180.v:5929$1386
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5921$1427_Y
- connect \Y $and$ls180.v:5921$1428_Y
+ connect \B $not$ls180.v:5929$1385_Y
+ connect \Y $and$ls180.v:5929$1386_Y
end
- attribute \src "ls180.v:5921.45-5921.152"
- cell $and $and$ls180.v:5921$1430
+ attribute \src "ls180.v:5929.41-5929.148"
+ cell $and $and$ls180.v:5929$1388
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5921$1428_Y
- connect \B $eq$ls180.v:5921$1429_Y
- connect \Y $and$ls180.v:5921$1430_Y
+ connect \A $and$ls180.v:5929$1386_Y
+ connect \B $eq$ls180.v:5929$1387_Y
+ connect \Y $and$ls180.v:5929$1388_Y
end
- attribute \src "ls180.v:5923.46-5923.99"
- cell $and $and$ls180.v:5923$1431
+ attribute \src "ls180.v:5931.44-5931.97"
+ cell $and $and$ls180.v:5931$1389
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5923$1431_Y
+ connect \Y $and$ls180.v:5931$1389_Y
end
- attribute \src "ls180.v:5923.45-5923.149"
- cell $and $and$ls180.v:5923$1433
+ attribute \src "ls180.v:5931.43-5931.147"
+ cell $and $and$ls180.v:5931$1391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5923$1431_Y
- connect \B $eq$ls180.v:5923$1432_Y
- connect \Y $and$ls180.v:5923$1433_Y
+ connect \A $and$ls180.v:5931$1389_Y
+ connect \B $eq$ls180.v:5931$1390_Y
+ connect \Y $and$ls180.v:5931$1391_Y
end
- attribute \src "ls180.v:5924.46-5924.102"
- cell $and $and$ls180.v:5924$1435
+ attribute \src "ls180.v:5932.44-5932.100"
+ cell $and $and$ls180.v:5932$1393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5924$1434_Y
- connect \Y $and$ls180.v:5924$1435_Y
+ connect \B $not$ls180.v:5932$1392_Y
+ connect \Y $and$ls180.v:5932$1393_Y
end
- attribute \src "ls180.v:5924.45-5924.152"
- cell $and $and$ls180.v:5924$1437
+ attribute \src "ls180.v:5932.43-5932.150"
+ cell $and $and$ls180.v:5932$1395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5924$1435_Y
- connect \B $eq$ls180.v:5924$1436_Y
- connect \Y $and$ls180.v:5924$1437_Y
+ connect \A $and$ls180.v:5932$1393_Y
+ connect \B $eq$ls180.v:5932$1394_Y
+ connect \Y $and$ls180.v:5932$1395_Y
end
- attribute \src "ls180.v:5926.46-5926.99"
- cell $and $and$ls180.v:5926$1438
+ attribute \src "ls180.v:5934.44-5934.97"
+ cell $and $and$ls180.v:5934$1396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5926$1438_Y
+ connect \Y $and$ls180.v:5934$1396_Y
end
- attribute \src "ls180.v:5926.45-5926.149"
- cell $and $and$ls180.v:5926$1440
+ attribute \src "ls180.v:5934.43-5934.147"
+ cell $and $and$ls180.v:5934$1398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5926$1438_Y
- connect \B $eq$ls180.v:5926$1439_Y
- connect \Y $and$ls180.v:5926$1440_Y
+ connect \A $and$ls180.v:5934$1396_Y
+ connect \B $eq$ls180.v:5934$1397_Y
+ connect \Y $and$ls180.v:5934$1398_Y
end
- attribute \src "ls180.v:5927.46-5927.102"
- cell $and $and$ls180.v:5927$1442
+ attribute \src "ls180.v:5935.44-5935.100"
+ cell $and $and$ls180.v:5935$1400
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5927$1441_Y
- connect \Y $and$ls180.v:5927$1442_Y
+ connect \B $not$ls180.v:5935$1399_Y
+ connect \Y $and$ls180.v:5935$1400_Y
end
- attribute \src "ls180.v:5927.45-5927.152"
- cell $and $and$ls180.v:5927$1444
+ attribute \src "ls180.v:5935.43-5935.150"
+ cell $and $and$ls180.v:5935$1402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5927$1442_Y
- connect \B $eq$ls180.v:5927$1443_Y
- connect \Y $and$ls180.v:5927$1444_Y
+ connect \A $and$ls180.v:5935$1400_Y
+ connect \B $eq$ls180.v:5935$1401_Y
+ connect \Y $and$ls180.v:5935$1402_Y
end
- attribute \src "ls180.v:5929.46-5929.99"
- cell $and $and$ls180.v:5929$1445
+ attribute \src "ls180.v:5937.44-5937.97"
+ cell $and $and$ls180.v:5937$1403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5929$1445_Y
+ connect \Y $and$ls180.v:5937$1403_Y
end
- attribute \src "ls180.v:5929.45-5929.149"
- cell $and $and$ls180.v:5929$1447
+ attribute \src "ls180.v:5937.43-5937.148"
+ cell $and $and$ls180.v:5937$1405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5929$1445_Y
- connect \B $eq$ls180.v:5929$1446_Y
- connect \Y $and$ls180.v:5929$1447_Y
+ connect \A $and$ls180.v:5937$1403_Y
+ connect \B $eq$ls180.v:5937$1404_Y
+ connect \Y $and$ls180.v:5937$1405_Y
end
- attribute \src "ls180.v:5930.46-5930.102"
- cell $and $and$ls180.v:5930$1449
+ attribute \src "ls180.v:5938.44-5938.100"
+ cell $and $and$ls180.v:5938$1407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5930$1448_Y
- connect \Y $and$ls180.v:5930$1449_Y
+ connect \B $not$ls180.v:5938$1406_Y
+ connect \Y $and$ls180.v:5938$1407_Y
end
- attribute \src "ls180.v:5930.45-5930.152"
- cell $and $and$ls180.v:5930$1451
+ attribute \src "ls180.v:5938.43-5938.151"
+ cell $and $and$ls180.v:5938$1409
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5930$1449_Y
- connect \B $eq$ls180.v:5930$1450_Y
- connect \Y $and$ls180.v:5930$1451_Y
+ connect \A $and$ls180.v:5938$1407_Y
+ connect \B $eq$ls180.v:5938$1408_Y
+ connect \Y $and$ls180.v:5938$1409_Y
end
- attribute \src "ls180.v:5932.45-5932.98"
- cell $and $and$ls180.v:5932$1452
+ attribute \src "ls180.v:5940.44-5940.97"
+ cell $and $and$ls180.v:5940$1410
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5932$1452_Y
+ connect \Y $and$ls180.v:5940$1410_Y
end
- attribute \src "ls180.v:5932.44-5932.148"
- cell $and $and$ls180.v:5932$1454
+ attribute \src "ls180.v:5940.43-5940.148"
+ cell $and $and$ls180.v:5940$1412
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5932$1452_Y
- connect \B $eq$ls180.v:5932$1453_Y
- connect \Y $and$ls180.v:5932$1454_Y
+ connect \A $and$ls180.v:5940$1410_Y
+ connect \B $eq$ls180.v:5940$1411_Y
+ connect \Y $and$ls180.v:5940$1412_Y
end
- attribute \src "ls180.v:5933.45-5933.101"
- cell $and $and$ls180.v:5933$1456
+ attribute \src "ls180.v:5941.44-5941.100"
+ cell $and $and$ls180.v:5941$1414
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5933$1455_Y
- connect \Y $and$ls180.v:5933$1456_Y
+ connect \B $not$ls180.v:5941$1413_Y
+ connect \Y $and$ls180.v:5941$1414_Y
end
- attribute \src "ls180.v:5933.44-5933.151"
- cell $and $and$ls180.v:5933$1458
+ attribute \src "ls180.v:5941.43-5941.151"
+ cell $and $and$ls180.v:5941$1416
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5933$1456_Y
- connect \B $eq$ls180.v:5933$1457_Y
- connect \Y $and$ls180.v:5933$1458_Y
+ connect \A $and$ls180.v:5941$1414_Y
+ connect \B $eq$ls180.v:5941$1415_Y
+ connect \Y $and$ls180.v:5941$1416_Y
end
- attribute \src "ls180.v:5935.45-5935.98"
- cell $and $and$ls180.v:5935$1459
+ attribute \src "ls180.v:5943.44-5943.97"
+ cell $and $and$ls180.v:5943$1417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5935$1459_Y
+ connect \Y $and$ls180.v:5943$1417_Y
end
- attribute \src "ls180.v:5935.44-5935.148"
- cell $and $and$ls180.v:5935$1461
+ attribute \src "ls180.v:5943.43-5943.148"
+ cell $and $and$ls180.v:5943$1419
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5935$1459_Y
- connect \B $eq$ls180.v:5935$1460_Y
- connect \Y $and$ls180.v:5935$1461_Y
+ connect \A $and$ls180.v:5943$1417_Y
+ connect \B $eq$ls180.v:5943$1418_Y
+ connect \Y $and$ls180.v:5943$1419_Y
end
- attribute \src "ls180.v:5936.45-5936.101"
- cell $and $and$ls180.v:5936$1463
+ attribute \src "ls180.v:5944.44-5944.100"
+ cell $and $and$ls180.v:5944$1421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5936$1462_Y
- connect \Y $and$ls180.v:5936$1463_Y
+ connect \B $not$ls180.v:5944$1420_Y
+ connect \Y $and$ls180.v:5944$1421_Y
end
- attribute \src "ls180.v:5936.44-5936.151"
- cell $and $and$ls180.v:5936$1465
+ attribute \src "ls180.v:5944.43-5944.151"
+ cell $and $and$ls180.v:5944$1423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5936$1463_Y
- connect \B $eq$ls180.v:5936$1464_Y
- connect \Y $and$ls180.v:5936$1465_Y
+ connect \A $and$ls180.v:5944$1421_Y
+ connect \B $eq$ls180.v:5944$1422_Y
+ connect \Y $and$ls180.v:5944$1423_Y
end
- attribute \src "ls180.v:5938.45-5938.98"
- cell $and $and$ls180.v:5938$1466
+ attribute \src "ls180.v:5946.41-5946.94"
+ cell $and $and$ls180.v:5946$1424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5938$1466_Y
+ connect \Y $and$ls180.v:5946$1424_Y
end
- attribute \src "ls180.v:5938.44-5938.148"
- cell $and $and$ls180.v:5938$1468
+ attribute \src "ls180.v:5946.40-5946.145"
+ cell $and $and$ls180.v:5946$1426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5938$1466_Y
- connect \B $eq$ls180.v:5938$1467_Y
- connect \Y $and$ls180.v:5938$1468_Y
+ connect \A $and$ls180.v:5946$1424_Y
+ connect \B $eq$ls180.v:5946$1425_Y
+ connect \Y $and$ls180.v:5946$1426_Y
end
- attribute \src "ls180.v:5939.45-5939.101"
- cell $and $and$ls180.v:5939$1470
+ attribute \src "ls180.v:5947.41-5947.97"
+ cell $and $and$ls180.v:5947$1428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5939$1469_Y
- connect \Y $and$ls180.v:5939$1470_Y
+ connect \B $not$ls180.v:5947$1427_Y
+ connect \Y $and$ls180.v:5947$1428_Y
end
- attribute \src "ls180.v:5939.44-5939.151"
- cell $and $and$ls180.v:5939$1472
+ attribute \src "ls180.v:5947.40-5947.148"
+ cell $and $and$ls180.v:5947$1430
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5939$1470_Y
- connect \B $eq$ls180.v:5939$1471_Y
- connect \Y $and$ls180.v:5939$1472_Y
+ connect \A $and$ls180.v:5947$1428_Y
+ connect \B $eq$ls180.v:5947$1429_Y
+ connect \Y $and$ls180.v:5947$1430_Y
end
- attribute \src "ls180.v:5941.45-5941.98"
- cell $and $and$ls180.v:5941$1473
+ attribute \src "ls180.v:5949.42-5949.95"
+ cell $and $and$ls180.v:5949$1431
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5941$1473_Y
+ connect \Y $and$ls180.v:5949$1431_Y
end
- attribute \src "ls180.v:5941.44-5941.148"
- cell $and $and$ls180.v:5941$1475
+ attribute \src "ls180.v:5949.41-5949.146"
+ cell $and $and$ls180.v:5949$1433
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5941$1473_Y
- connect \B $eq$ls180.v:5941$1474_Y
- connect \Y $and$ls180.v:5941$1475_Y
+ connect \A $and$ls180.v:5949$1431_Y
+ connect \B $eq$ls180.v:5949$1432_Y
+ connect \Y $and$ls180.v:5949$1433_Y
end
- attribute \src "ls180.v:5942.45-5942.101"
- cell $and $and$ls180.v:5942$1477
+ attribute \src "ls180.v:5950.42-5950.98"
+ cell $and $and$ls180.v:5950$1435
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5942$1476_Y
- connect \Y $and$ls180.v:5942$1477_Y
+ connect \B $not$ls180.v:5950$1434_Y
+ connect \Y $and$ls180.v:5950$1435_Y
end
- attribute \src "ls180.v:5942.44-5942.151"
- cell $and $and$ls180.v:5942$1479
+ attribute \src "ls180.v:5950.41-5950.149"
+ cell $and $and$ls180.v:5950$1437
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5942$1477_Y
- connect \B $eq$ls180.v:5942$1478_Y
- connect \Y $and$ls180.v:5942$1479_Y
+ connect \A $and$ls180.v:5950$1435_Y
+ connect \B $eq$ls180.v:5950$1436_Y
+ connect \Y $and$ls180.v:5950$1437_Y
end
- attribute \src "ls180.v:5944.36-5944.89"
- cell $and $and$ls180.v:5944$1480
+ attribute \src "ls180.v:5969.46-5969.99"
+ cell $and $and$ls180.v:5969$1439
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5944$1480_Y
- end
- attribute \src "ls180.v:5944.35-5944.139"
- cell $and $and$ls180.v:5944$1482
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5944$1480_Y
- connect \B $eq$ls180.v:5944$1481_Y
- connect \Y $and$ls180.v:5944$1482_Y
- end
- attribute \src "ls180.v:5945.36-5945.92"
- cell $and $and$ls180.v:5945$1484
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5945$1483_Y
- connect \Y $and$ls180.v:5945$1484_Y
- end
- attribute \src "ls180.v:5945.35-5945.142"
- cell $and $and$ls180.v:5945$1486
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5945$1484_Y
- connect \B $eq$ls180.v:5945$1485_Y
- connect \Y $and$ls180.v:5945$1486_Y
- end
- attribute \src "ls180.v:5947.47-5947.100"
- cell $and $and$ls180.v:5947$1487
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5947$1487_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:5969$1439_Y
end
- attribute \src "ls180.v:5947.46-5947.150"
- cell $and $and$ls180.v:5947$1489
+ attribute \src "ls180.v:5969.45-5969.149"
+ cell $and $and$ls180.v:5969$1441
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5947$1487_Y
- connect \B $eq$ls180.v:5947$1488_Y
- connect \Y $and$ls180.v:5947$1489_Y
+ connect \A $and$ls180.v:5969$1439_Y
+ connect \B $eq$ls180.v:5969$1440_Y
+ connect \Y $and$ls180.v:5969$1441_Y
end
- attribute \src "ls180.v:5948.47-5948.103"
- cell $and $and$ls180.v:5948$1491
+ attribute \src "ls180.v:5970.46-5970.102"
+ cell $and $and$ls180.v:5970$1443
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5948$1490_Y
- connect \Y $and$ls180.v:5948$1491_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:5970$1442_Y
+ connect \Y $and$ls180.v:5970$1443_Y
end
- attribute \src "ls180.v:5948.46-5948.153"
- cell $and $and$ls180.v:5948$1493
+ attribute \src "ls180.v:5970.45-5970.152"
+ cell $and $and$ls180.v:5970$1445
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5948$1491_Y
- connect \B $eq$ls180.v:5948$1492_Y
- connect \Y $and$ls180.v:5948$1493_Y
+ connect \A $and$ls180.v:5970$1443_Y
+ connect \B $eq$ls180.v:5970$1444_Y
+ connect \Y $and$ls180.v:5970$1445_Y
end
- attribute \src "ls180.v:5950.47-5950.100"
- cell $and $and$ls180.v:5950$1494
+ attribute \src "ls180.v:5972.46-5972.99"
+ cell $and $and$ls180.v:5972$1446
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5950$1494_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:5972$1446_Y
end
- attribute \src "ls180.v:5950.46-5950.151"
- cell $and $and$ls180.v:5950$1496
+ attribute \src "ls180.v:5972.45-5972.149"
+ cell $and $and$ls180.v:5972$1448
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5950$1494_Y
- connect \B $eq$ls180.v:5950$1495_Y
- connect \Y $and$ls180.v:5950$1496_Y
+ connect \A $and$ls180.v:5972$1446_Y
+ connect \B $eq$ls180.v:5972$1447_Y
+ connect \Y $and$ls180.v:5972$1448_Y
end
- attribute \src "ls180.v:5951.47-5951.103"
- cell $and $and$ls180.v:5951$1498
+ attribute \src "ls180.v:5973.46-5973.102"
+ cell $and $and$ls180.v:5973$1450
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5951$1497_Y
- connect \Y $and$ls180.v:5951$1498_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:5973$1449_Y
+ connect \Y $and$ls180.v:5973$1450_Y
end
- attribute \src "ls180.v:5951.46-5951.154"
- cell $and $and$ls180.v:5951$1500
+ attribute \src "ls180.v:5973.45-5973.152"
+ cell $and $and$ls180.v:5973$1452
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5951$1498_Y
- connect \B $eq$ls180.v:5951$1499_Y
- connect \Y $and$ls180.v:5951$1500_Y
+ connect \A $and$ls180.v:5973$1450_Y
+ connect \B $eq$ls180.v:5973$1451_Y
+ connect \Y $and$ls180.v:5973$1452_Y
end
- attribute \src "ls180.v:5953.47-5953.100"
- cell $and $and$ls180.v:5953$1501
+ attribute \src "ls180.v:5975.46-5975.99"
+ cell $and $and$ls180.v:5975$1453
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5953$1501_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:5975$1453_Y
end
- attribute \src "ls180.v:5953.46-5953.151"
- cell $and $and$ls180.v:5953$1503
+ attribute \src "ls180.v:5975.45-5975.149"
+ cell $and $and$ls180.v:5975$1455
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5953$1501_Y
- connect \B $eq$ls180.v:5953$1502_Y
- connect \Y $and$ls180.v:5953$1503_Y
+ connect \A $and$ls180.v:5975$1453_Y
+ connect \B $eq$ls180.v:5975$1454_Y
+ connect \Y $and$ls180.v:5975$1455_Y
end
- attribute \src "ls180.v:5954.47-5954.103"
- cell $and $and$ls180.v:5954$1505
+ attribute \src "ls180.v:5976.46-5976.102"
+ cell $and $and$ls180.v:5976$1457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5954$1504_Y
- connect \Y $and$ls180.v:5954$1505_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:5976$1456_Y
+ connect \Y $and$ls180.v:5976$1457_Y
end
- attribute \src "ls180.v:5954.46-5954.154"
- cell $and $and$ls180.v:5954$1507
+ attribute \src "ls180.v:5976.45-5976.152"
+ cell $and $and$ls180.v:5976$1459
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5954$1505_Y
- connect \B $eq$ls180.v:5954$1506_Y
- connect \Y $and$ls180.v:5954$1507_Y
+ connect \A $and$ls180.v:5976$1457_Y
+ connect \B $eq$ls180.v:5976$1458_Y
+ connect \Y $and$ls180.v:5976$1459_Y
end
- attribute \src "ls180.v:5956.47-5956.100"
- cell $and $and$ls180.v:5956$1508
+ attribute \src "ls180.v:5978.46-5978.99"
+ cell $and $and$ls180.v:5978$1460
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5956$1508_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:5978$1460_Y
end
- attribute \src "ls180.v:5956.46-5956.151"
- cell $and $and$ls180.v:5956$1510
+ attribute \src "ls180.v:5978.45-5978.149"
+ cell $and $and$ls180.v:5978$1462
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5956$1508_Y
- connect \B $eq$ls180.v:5956$1509_Y
- connect \Y $and$ls180.v:5956$1510_Y
+ connect \A $and$ls180.v:5978$1460_Y
+ connect \B $eq$ls180.v:5978$1461_Y
+ connect \Y $and$ls180.v:5978$1462_Y
end
- attribute \src "ls180.v:5957.47-5957.103"
- cell $and $and$ls180.v:5957$1512
+ attribute \src "ls180.v:5979.46-5979.102"
+ cell $and $and$ls180.v:5979$1464
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5957$1511_Y
- connect \Y $and$ls180.v:5957$1512_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:5979$1463_Y
+ connect \Y $and$ls180.v:5979$1464_Y
end
- attribute \src "ls180.v:5957.46-5957.154"
- cell $and $and$ls180.v:5957$1514
+ attribute \src "ls180.v:5979.45-5979.152"
+ cell $and $and$ls180.v:5979$1466
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5957$1512_Y
- connect \B $eq$ls180.v:5957$1513_Y
- connect \Y $and$ls180.v:5957$1514_Y
+ connect \A $and$ls180.v:5979$1464_Y
+ connect \B $eq$ls180.v:5979$1465_Y
+ connect \Y $and$ls180.v:5979$1466_Y
end
- attribute \src "ls180.v:5959.47-5959.100"
- cell $and $and$ls180.v:5959$1515
+ attribute \src "ls180.v:5981.45-5981.98"
+ cell $and $and$ls180.v:5981$1467
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5959$1515_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:5981$1467_Y
end
- attribute \src "ls180.v:5959.46-5959.151"
- cell $and $and$ls180.v:5959$1517
+ attribute \src "ls180.v:5981.44-5981.148"
+ cell $and $and$ls180.v:5981$1469
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5959$1515_Y
- connect \B $eq$ls180.v:5959$1516_Y
- connect \Y $and$ls180.v:5959$1517_Y
+ connect \A $and$ls180.v:5981$1467_Y
+ connect \B $eq$ls180.v:5981$1468_Y
+ connect \Y $and$ls180.v:5981$1469_Y
end
- attribute \src "ls180.v:5960.47-5960.103"
- cell $and $and$ls180.v:5960$1519
+ attribute \src "ls180.v:5982.45-5982.101"
+ cell $and $and$ls180.v:5982$1471
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5960$1518_Y
- connect \Y $and$ls180.v:5960$1519_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:5982$1470_Y
+ connect \Y $and$ls180.v:5982$1471_Y
end
- attribute \src "ls180.v:5960.46-5960.154"
- cell $and $and$ls180.v:5960$1521
+ attribute \src "ls180.v:5982.44-5982.151"
+ cell $and $and$ls180.v:5982$1473
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5960$1519_Y
- connect \B $eq$ls180.v:5960$1520_Y
- connect \Y $and$ls180.v:5960$1521_Y
+ connect \A $and$ls180.v:5982$1471_Y
+ connect \B $eq$ls180.v:5982$1472_Y
+ connect \Y $and$ls180.v:5982$1473_Y
end
- attribute \src "ls180.v:5962.47-5962.100"
- cell $and $and$ls180.v:5962$1522
+ attribute \src "ls180.v:5984.45-5984.98"
+ cell $and $and$ls180.v:5984$1474
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5962$1522_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:5984$1474_Y
end
- attribute \src "ls180.v:5962.46-5962.151"
- cell $and $and$ls180.v:5962$1524
+ attribute \src "ls180.v:5984.44-5984.148"
+ cell $and $and$ls180.v:5984$1476
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5962$1522_Y
- connect \B $eq$ls180.v:5962$1523_Y
- connect \Y $and$ls180.v:5962$1524_Y
+ connect \A $and$ls180.v:5984$1474_Y
+ connect \B $eq$ls180.v:5984$1475_Y
+ connect \Y $and$ls180.v:5984$1476_Y
end
- attribute \src "ls180.v:5963.47-5963.103"
- cell $and $and$ls180.v:5963$1526
+ attribute \src "ls180.v:5985.45-5985.101"
+ cell $and $and$ls180.v:5985$1478
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5963$1525_Y
- connect \Y $and$ls180.v:5963$1526_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:5985$1477_Y
+ connect \Y $and$ls180.v:5985$1478_Y
end
- attribute \src "ls180.v:5963.46-5963.154"
- cell $and $and$ls180.v:5963$1528
+ attribute \src "ls180.v:5985.44-5985.151"
+ cell $and $and$ls180.v:5985$1480
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5963$1526_Y
- connect \B $eq$ls180.v:5963$1527_Y
- connect \Y $and$ls180.v:5963$1528_Y
+ connect \A $and$ls180.v:5985$1478_Y
+ connect \B $eq$ls180.v:5985$1479_Y
+ connect \Y $and$ls180.v:5985$1480_Y
end
- attribute \src "ls180.v:5965.46-5965.99"
- cell $and $and$ls180.v:5965$1529
+ attribute \src "ls180.v:5987.45-5987.98"
+ cell $and $and$ls180.v:5987$1481
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5965$1529_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:5987$1481_Y
end
- attribute \src "ls180.v:5965.45-5965.150"
- cell $and $and$ls180.v:5965$1531
+ attribute \src "ls180.v:5987.44-5987.148"
+ cell $and $and$ls180.v:5987$1483
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5965$1529_Y
- connect \B $eq$ls180.v:5965$1530_Y
- connect \Y $and$ls180.v:5965$1531_Y
+ connect \A $and$ls180.v:5987$1481_Y
+ connect \B $eq$ls180.v:5987$1482_Y
+ connect \Y $and$ls180.v:5987$1483_Y
end
- attribute \src "ls180.v:5966.46-5966.102"
- cell $and $and$ls180.v:5966$1533
+ attribute \src "ls180.v:5988.45-5988.101"
+ cell $and $and$ls180.v:5988$1485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5966$1532_Y
- connect \Y $and$ls180.v:5966$1533_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:5988$1484_Y
+ connect \Y $and$ls180.v:5988$1485_Y
end
- attribute \src "ls180.v:5966.45-5966.153"
- cell $and $and$ls180.v:5966$1535
+ attribute \src "ls180.v:5988.44-5988.151"
+ cell $and $and$ls180.v:5988$1487
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5966$1533_Y
- connect \B $eq$ls180.v:5966$1534_Y
- connect \Y $and$ls180.v:5966$1535_Y
+ connect \A $and$ls180.v:5988$1485_Y
+ connect \B $eq$ls180.v:5988$1486_Y
+ connect \Y $and$ls180.v:5988$1487_Y
end
- attribute \src "ls180.v:5968.46-5968.99"
- cell $and $and$ls180.v:5968$1536
+ attribute \src "ls180.v:5990.45-5990.98"
+ cell $and $and$ls180.v:5990$1488
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5968$1536_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:5990$1488_Y
end
- attribute \src "ls180.v:5968.45-5968.150"
- cell $and $and$ls180.v:5968$1538
+ attribute \src "ls180.v:5990.44-5990.148"
+ cell $and $and$ls180.v:5990$1490
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5968$1536_Y
- connect \B $eq$ls180.v:5968$1537_Y
- connect \Y $and$ls180.v:5968$1538_Y
+ connect \A $and$ls180.v:5990$1488_Y
+ connect \B $eq$ls180.v:5990$1489_Y
+ connect \Y $and$ls180.v:5990$1490_Y
end
- attribute \src "ls180.v:5969.46-5969.102"
- cell $and $and$ls180.v:5969$1540
+ attribute \src "ls180.v:5991.45-5991.101"
+ cell $and $and$ls180.v:5991$1492
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5969$1539_Y
- connect \Y $and$ls180.v:5969$1540_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:5991$1491_Y
+ connect \Y $and$ls180.v:5991$1492_Y
end
- attribute \src "ls180.v:5969.45-5969.153"
- cell $and $and$ls180.v:5969$1542
+ attribute \src "ls180.v:5991.44-5991.151"
+ cell $and $and$ls180.v:5991$1494
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5969$1540_Y
- connect \B $eq$ls180.v:5969$1541_Y
- connect \Y $and$ls180.v:5969$1542_Y
+ connect \A $and$ls180.v:5991$1492_Y
+ connect \B $eq$ls180.v:5991$1493_Y
+ connect \Y $and$ls180.v:5991$1494_Y
end
- attribute \src "ls180.v:5971.46-5971.99"
- cell $and $and$ls180.v:5971$1543
+ attribute \src "ls180.v:5993.36-5993.89"
+ cell $and $and$ls180.v:5993$1495
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5971$1543_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:5993$1495_Y
end
- attribute \src "ls180.v:5971.45-5971.150"
- cell $and $and$ls180.v:5971$1545
+ attribute \src "ls180.v:5993.35-5993.139"
+ cell $and $and$ls180.v:5993$1497
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5971$1543_Y
- connect \B $eq$ls180.v:5971$1544_Y
- connect \Y $and$ls180.v:5971$1545_Y
+ connect \A $and$ls180.v:5993$1495_Y
+ connect \B $eq$ls180.v:5993$1496_Y
+ connect \Y $and$ls180.v:5993$1497_Y
end
- attribute \src "ls180.v:5972.46-5972.102"
- cell $and $and$ls180.v:5972$1547
+ attribute \src "ls180.v:5994.36-5994.92"
+ cell $and $and$ls180.v:5994$1499
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5972$1546_Y
- connect \Y $and$ls180.v:5972$1547_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:5994$1498_Y
+ connect \Y $and$ls180.v:5994$1499_Y
end
- attribute \src "ls180.v:5972.45-5972.153"
- cell $and $and$ls180.v:5972$1549
+ attribute \src "ls180.v:5994.35-5994.142"
+ cell $and $and$ls180.v:5994$1501
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5972$1547_Y
- connect \B $eq$ls180.v:5972$1548_Y
- connect \Y $and$ls180.v:5972$1549_Y
+ connect \A $and$ls180.v:5994$1499_Y
+ connect \B $eq$ls180.v:5994$1500_Y
+ connect \Y $and$ls180.v:5994$1501_Y
end
- attribute \src "ls180.v:5974.46-5974.99"
- cell $and $and$ls180.v:5974$1550
+ attribute \src "ls180.v:5996.47-5996.100"
+ cell $and $and$ls180.v:5996$1502
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5974$1550_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:5996$1502_Y
end
- attribute \src "ls180.v:5974.45-5974.150"
- cell $and $and$ls180.v:5974$1552
+ attribute \src "ls180.v:5996.46-5996.150"
+ cell $and $and$ls180.v:5996$1504
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5974$1550_Y
- connect \B $eq$ls180.v:5974$1551_Y
- connect \Y $and$ls180.v:5974$1552_Y
+ connect \A $and$ls180.v:5996$1502_Y
+ connect \B $eq$ls180.v:5996$1503_Y
+ connect \Y $and$ls180.v:5996$1504_Y
end
- attribute \src "ls180.v:5975.46-5975.102"
- cell $and $and$ls180.v:5975$1554
+ attribute \src "ls180.v:5997.47-5997.103"
+ cell $and $and$ls180.v:5997$1506
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5975$1553_Y
- connect \Y $and$ls180.v:5975$1554_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:5997$1505_Y
+ connect \Y $and$ls180.v:5997$1506_Y
end
- attribute \src "ls180.v:5975.45-5975.153"
- cell $and $and$ls180.v:5975$1556
+ attribute \src "ls180.v:5997.46-5997.153"
+ cell $and $and$ls180.v:5997$1508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5975$1554_Y
- connect \B $eq$ls180.v:5975$1555_Y
- connect \Y $and$ls180.v:5975$1556_Y
+ connect \A $and$ls180.v:5997$1506_Y
+ connect \B $eq$ls180.v:5997$1507_Y
+ connect \Y $and$ls180.v:5997$1508_Y
end
- attribute \src "ls180.v:5977.46-5977.99"
- cell $and $and$ls180.v:5977$1557
+ attribute \src "ls180.v:5999.47-5999.100"
+ cell $and $and$ls180.v:5999$1509
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5977$1557_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:5999$1509_Y
end
- attribute \src "ls180.v:5977.45-5977.150"
- cell $and $and$ls180.v:5977$1559
+ attribute \src "ls180.v:5999.46-5999.151"
+ cell $and $and$ls180.v:5999$1511
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5977$1557_Y
- connect \B $eq$ls180.v:5977$1558_Y
- connect \Y $and$ls180.v:5977$1559_Y
+ connect \A $and$ls180.v:5999$1509_Y
+ connect \B $eq$ls180.v:5999$1510_Y
+ connect \Y $and$ls180.v:5999$1511_Y
end
- attribute \src "ls180.v:5978.46-5978.102"
- cell $and $and$ls180.v:5978$1561
+ attribute \src "ls180.v:6000.47-6000.103"
+ cell $and $and$ls180.v:6000$1513
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5978$1560_Y
- connect \Y $and$ls180.v:5978$1561_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6000$1512_Y
+ connect \Y $and$ls180.v:6000$1513_Y
end
- attribute \src "ls180.v:5978.45-5978.153"
- cell $and $and$ls180.v:5978$1563
+ attribute \src "ls180.v:6000.46-6000.154"
+ cell $and $and$ls180.v:6000$1515
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5978$1561_Y
- connect \B $eq$ls180.v:5978$1562_Y
- connect \Y $and$ls180.v:5978$1563_Y
+ connect \A $and$ls180.v:6000$1513_Y
+ connect \B $eq$ls180.v:6000$1514_Y
+ connect \Y $and$ls180.v:6000$1515_Y
end
- attribute \src "ls180.v:5980.46-5980.99"
- cell $and $and$ls180.v:5980$1564
+ attribute \src "ls180.v:6002.47-6002.100"
+ cell $and $and$ls180.v:6002$1516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5980$1564_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:6002$1516_Y
end
- attribute \src "ls180.v:5980.45-5980.150"
- cell $and $and$ls180.v:5980$1566
+ attribute \src "ls180.v:6002.46-6002.151"
+ cell $and $and$ls180.v:6002$1518
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5980$1564_Y
- connect \B $eq$ls180.v:5980$1565_Y
- connect \Y $and$ls180.v:5980$1566_Y
+ connect \A $and$ls180.v:6002$1516_Y
+ connect \B $eq$ls180.v:6002$1517_Y
+ connect \Y $and$ls180.v:6002$1518_Y
end
- attribute \src "ls180.v:5981.46-5981.102"
- cell $and $and$ls180.v:5981$1568
+ attribute \src "ls180.v:6003.47-6003.103"
+ cell $and $and$ls180.v:6003$1520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5981$1567_Y
- connect \Y $and$ls180.v:5981$1568_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6003$1519_Y
+ connect \Y $and$ls180.v:6003$1520_Y
end
- attribute \src "ls180.v:5981.45-5981.153"
- cell $and $and$ls180.v:5981$1570
+ attribute \src "ls180.v:6003.46-6003.154"
+ cell $and $and$ls180.v:6003$1522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5981$1568_Y
- connect \B $eq$ls180.v:5981$1569_Y
- connect \Y $and$ls180.v:5981$1570_Y
+ connect \A $and$ls180.v:6003$1520_Y
+ connect \B $eq$ls180.v:6003$1521_Y
+ connect \Y $and$ls180.v:6003$1522_Y
end
- attribute \src "ls180.v:5983.46-5983.99"
- cell $and $and$ls180.v:5983$1571
+ attribute \src "ls180.v:6005.47-6005.100"
+ cell $and $and$ls180.v:6005$1523
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5983$1571_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:6005$1523_Y
end
- attribute \src "ls180.v:5983.45-5983.150"
- cell $and $and$ls180.v:5983$1573
+ attribute \src "ls180.v:6005.46-6005.151"
+ cell $and $and$ls180.v:6005$1525
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5983$1571_Y
- connect \B $eq$ls180.v:5983$1572_Y
- connect \Y $and$ls180.v:5983$1573_Y
+ connect \A $and$ls180.v:6005$1523_Y
+ connect \B $eq$ls180.v:6005$1524_Y
+ connect \Y $and$ls180.v:6005$1525_Y
end
- attribute \src "ls180.v:5984.46-5984.102"
- cell $and $and$ls180.v:5984$1575
+ attribute \src "ls180.v:6006.47-6006.103"
+ cell $and $and$ls180.v:6006$1527
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5984$1574_Y
- connect \Y $and$ls180.v:5984$1575_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6006$1526_Y
+ connect \Y $and$ls180.v:6006$1527_Y
end
- attribute \src "ls180.v:5984.45-5984.153"
- cell $and $and$ls180.v:5984$1577
+ attribute \src "ls180.v:6006.46-6006.154"
+ cell $and $and$ls180.v:6006$1529
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5984$1575_Y
- connect \B $eq$ls180.v:5984$1576_Y
- connect \Y $and$ls180.v:5984$1577_Y
+ connect \A $and$ls180.v:6006$1527_Y
+ connect \B $eq$ls180.v:6006$1528_Y
+ connect \Y $and$ls180.v:6006$1529_Y
end
- attribute \src "ls180.v:5986.46-5986.99"
- cell $and $and$ls180.v:5986$1578
+ attribute \src "ls180.v:6008.47-6008.100"
+ cell $and $and$ls180.v:6008$1530
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5986$1578_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:6008$1530_Y
end
- attribute \src "ls180.v:5986.45-5986.150"
- cell $and $and$ls180.v:5986$1580
+ attribute \src "ls180.v:6008.46-6008.151"
+ cell $and $and$ls180.v:6008$1532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5986$1578_Y
- connect \B $eq$ls180.v:5986$1579_Y
- connect \Y $and$ls180.v:5986$1580_Y
+ connect \A $and$ls180.v:6008$1530_Y
+ connect \B $eq$ls180.v:6008$1531_Y
+ connect \Y $and$ls180.v:6008$1532_Y
end
- attribute \src "ls180.v:5987.46-5987.102"
- cell $and $and$ls180.v:5987$1582
+ attribute \src "ls180.v:6009.47-6009.103"
+ cell $and $and$ls180.v:6009$1534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5987$1581_Y
- connect \Y $and$ls180.v:5987$1582_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6009$1533_Y
+ connect \Y $and$ls180.v:6009$1534_Y
end
- attribute \src "ls180.v:5987.45-5987.153"
- cell $and $and$ls180.v:5987$1584
+ attribute \src "ls180.v:6009.46-6009.154"
+ cell $and $and$ls180.v:6009$1536
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5987$1582_Y
- connect \B $eq$ls180.v:5987$1583_Y
- connect \Y $and$ls180.v:5987$1584_Y
+ connect \A $and$ls180.v:6009$1534_Y
+ connect \B $eq$ls180.v:6009$1535_Y
+ connect \Y $and$ls180.v:6009$1536_Y
end
- attribute \src "ls180.v:5989.46-5989.99"
- cell $and $and$ls180.v:5989$1585
+ attribute \src "ls180.v:6011.47-6011.100"
+ cell $and $and$ls180.v:6011$1537
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5989$1585_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:6011$1537_Y
end
- attribute \src "ls180.v:5989.45-5989.150"
- cell $and $and$ls180.v:5989$1587
+ attribute \src "ls180.v:6011.46-6011.151"
+ cell $and $and$ls180.v:6011$1539
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5989$1585_Y
- connect \B $eq$ls180.v:5989$1586_Y
- connect \Y $and$ls180.v:5989$1587_Y
+ connect \A $and$ls180.v:6011$1537_Y
+ connect \B $eq$ls180.v:6011$1538_Y
+ connect \Y $and$ls180.v:6011$1539_Y
end
- attribute \src "ls180.v:5990.46-5990.102"
- cell $and $and$ls180.v:5990$1589
+ attribute \src "ls180.v:6012.47-6012.103"
+ cell $and $and$ls180.v:6012$1541
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5990$1588_Y
- connect \Y $and$ls180.v:5990$1589_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6012$1540_Y
+ connect \Y $and$ls180.v:6012$1541_Y
end
- attribute \src "ls180.v:5990.45-5990.153"
- cell $and $and$ls180.v:5990$1591
+ attribute \src "ls180.v:6012.46-6012.154"
+ cell $and $and$ls180.v:6012$1543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5990$1589_Y
- connect \B $eq$ls180.v:5990$1590_Y
- connect \Y $and$ls180.v:5990$1591_Y
+ connect \A $and$ls180.v:6012$1541_Y
+ connect \B $eq$ls180.v:6012$1542_Y
+ connect \Y $and$ls180.v:6012$1543_Y
end
- attribute \src "ls180.v:5992.46-5992.99"
- cell $and $and$ls180.v:5992$1592
+ attribute \src "ls180.v:6014.46-6014.99"
+ cell $and $and$ls180.v:6014$1544
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5992$1592_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:6014$1544_Y
end
- attribute \src "ls180.v:5992.45-5992.150"
- cell $and $and$ls180.v:5992$1594
+ attribute \src "ls180.v:6014.45-6014.150"
+ cell $and $and$ls180.v:6014$1546
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5992$1592_Y
- connect \B $eq$ls180.v:5992$1593_Y
- connect \Y $and$ls180.v:5992$1594_Y
+ connect \A $and$ls180.v:6014$1544_Y
+ connect \B $eq$ls180.v:6014$1545_Y
+ connect \Y $and$ls180.v:6014$1546_Y
end
- attribute \src "ls180.v:5993.46-5993.102"
- cell $and $and$ls180.v:5993$1596
+ attribute \src "ls180.v:6015.46-6015.102"
+ cell $and $and$ls180.v:6015$1548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5993$1595_Y
- connect \Y $and$ls180.v:5993$1596_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6015$1547_Y
+ connect \Y $and$ls180.v:6015$1548_Y
end
- attribute \src "ls180.v:5993.45-5993.153"
- cell $and $and$ls180.v:5993$1598
+ attribute \src "ls180.v:6015.45-6015.153"
+ cell $and $and$ls180.v:6015$1550
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5993$1596_Y
- connect \B $eq$ls180.v:5993$1597_Y
- connect \Y $and$ls180.v:5993$1598_Y
+ connect \A $and$ls180.v:6015$1548_Y
+ connect \B $eq$ls180.v:6015$1549_Y
+ connect \Y $and$ls180.v:6015$1550_Y
end
- attribute \src "ls180.v:5995.42-5995.95"
- cell $and $and$ls180.v:5995$1599
+ attribute \src "ls180.v:6017.46-6017.99"
+ cell $and $and$ls180.v:6017$1551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5995$1599_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:6017$1551_Y
end
- attribute \src "ls180.v:5995.41-5995.146"
- cell $and $and$ls180.v:5995$1601
+ attribute \src "ls180.v:6017.45-6017.150"
+ cell $and $and$ls180.v:6017$1553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5995$1599_Y
- connect \B $eq$ls180.v:5995$1600_Y
- connect \Y $and$ls180.v:5995$1601_Y
+ connect \A $and$ls180.v:6017$1551_Y
+ connect \B $eq$ls180.v:6017$1552_Y
+ connect \Y $and$ls180.v:6017$1553_Y
end
- attribute \src "ls180.v:5996.42-5996.98"
- cell $and $and$ls180.v:5996$1603
+ attribute \src "ls180.v:6018.46-6018.102"
+ cell $and $and$ls180.v:6018$1555
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5996$1602_Y
- connect \Y $and$ls180.v:5996$1603_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6018$1554_Y
+ connect \Y $and$ls180.v:6018$1555_Y
end
- attribute \src "ls180.v:5996.41-5996.149"
- cell $and $and$ls180.v:5996$1605
+ attribute \src "ls180.v:6018.45-6018.153"
+ cell $and $and$ls180.v:6018$1557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5996$1603_Y
- connect \B $eq$ls180.v:5996$1604_Y
- connect \Y $and$ls180.v:5996$1605_Y
+ connect \A $and$ls180.v:6018$1555_Y
+ connect \B $eq$ls180.v:6018$1556_Y
+ connect \Y $and$ls180.v:6018$1557_Y
end
- attribute \src "ls180.v:5998.43-5998.96"
- cell $and $and$ls180.v:5998$1606
+ attribute \src "ls180.v:6020.46-6020.99"
+ cell $and $and$ls180.v:6020$1558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:5998$1606_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:6020$1558_Y
end
- attribute \src "ls180.v:5998.42-5998.147"
- cell $and $and$ls180.v:5998$1608
+ attribute \src "ls180.v:6020.45-6020.150"
+ cell $and $and$ls180.v:6020$1560
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5998$1606_Y
- connect \B $eq$ls180.v:5998$1607_Y
- connect \Y $and$ls180.v:5998$1608_Y
+ connect \A $and$ls180.v:6020$1558_Y
+ connect \B $eq$ls180.v:6020$1559_Y
+ connect \Y $and$ls180.v:6020$1560_Y
end
- attribute \src "ls180.v:5999.43-5999.99"
- cell $and $and$ls180.v:5999$1610
+ attribute \src "ls180.v:6021.46-6021.102"
+ cell $and $and$ls180.v:6021$1562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:5999$1609_Y
- connect \Y $and$ls180.v:5999$1610_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6021$1561_Y
+ connect \Y $and$ls180.v:6021$1562_Y
end
- attribute \src "ls180.v:5999.42-5999.150"
- cell $and $and$ls180.v:5999$1612
+ attribute \src "ls180.v:6021.45-6021.153"
+ cell $and $and$ls180.v:6021$1564
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:5999$1610_Y
- connect \B $eq$ls180.v:5999$1611_Y
- connect \Y $and$ls180.v:5999$1612_Y
+ connect \A $and$ls180.v:6021$1562_Y
+ connect \B $eq$ls180.v:6021$1563_Y
+ connect \Y $and$ls180.v:6021$1564_Y
end
- attribute \src "ls180.v:6001.46-6001.99"
- cell $and $and$ls180.v:6001$1613
+ attribute \src "ls180.v:6023.46-6023.99"
+ cell $and $and$ls180.v:6023$1565
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:6001$1613_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:6023$1565_Y
end
- attribute \src "ls180.v:6001.45-6001.150"
- cell $and $and$ls180.v:6001$1615
+ attribute \src "ls180.v:6023.45-6023.150"
+ cell $and $and$ls180.v:6023$1567
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6001$1613_Y
- connect \B $eq$ls180.v:6001$1614_Y
- connect \Y $and$ls180.v:6001$1615_Y
+ connect \A $and$ls180.v:6023$1565_Y
+ connect \B $eq$ls180.v:6023$1566_Y
+ connect \Y $and$ls180.v:6023$1567_Y
end
- attribute \src "ls180.v:6002.46-6002.102"
- cell $and $and$ls180.v:6002$1617
+ attribute \src "ls180.v:6024.46-6024.102"
+ cell $and $and$ls180.v:6024$1569
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:6002$1616_Y
- connect \Y $and$ls180.v:6002$1617_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6024$1568_Y
+ connect \Y $and$ls180.v:6024$1569_Y
end
- attribute \src "ls180.v:6002.45-6002.153"
- cell $and $and$ls180.v:6002$1619
+ attribute \src "ls180.v:6024.45-6024.153"
+ cell $and $and$ls180.v:6024$1571
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6002$1617_Y
- connect \B $eq$ls180.v:6002$1618_Y
- connect \Y $and$ls180.v:6002$1619_Y
+ connect \A $and$ls180.v:6024$1569_Y
+ connect \B $eq$ls180.v:6024$1570_Y
+ connect \Y $and$ls180.v:6024$1571_Y
end
- attribute \src "ls180.v:6004.46-6004.99"
- cell $and $and$ls180.v:6004$1620
+ attribute \src "ls180.v:6026.46-6026.99"
+ cell $and $and$ls180.v:6026$1572
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:6004$1620_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:6026$1572_Y
end
- attribute \src "ls180.v:6004.45-6004.150"
- cell $and $and$ls180.v:6004$1622
+ attribute \src "ls180.v:6026.45-6026.150"
+ cell $and $and$ls180.v:6026$1574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6004$1620_Y
- connect \B $eq$ls180.v:6004$1621_Y
- connect \Y $and$ls180.v:6004$1622_Y
+ connect \A $and$ls180.v:6026$1572_Y
+ connect \B $eq$ls180.v:6026$1573_Y
+ connect \Y $and$ls180.v:6026$1574_Y
end
- attribute \src "ls180.v:6005.46-6005.102"
- cell $and $and$ls180.v:6005$1624
+ attribute \src "ls180.v:6027.46-6027.102"
+ cell $and $and$ls180.v:6027$1576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:6005$1623_Y
- connect \Y $and$ls180.v:6005$1624_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6027$1575_Y
+ connect \Y $and$ls180.v:6027$1576_Y
end
- attribute \src "ls180.v:6005.45-6005.153"
- cell $and $and$ls180.v:6005$1626
+ attribute \src "ls180.v:6027.45-6027.153"
+ cell $and $and$ls180.v:6027$1578
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6005$1624_Y
- connect \B $eq$ls180.v:6005$1625_Y
- connect \Y $and$ls180.v:6005$1626_Y
+ connect \A $and$ls180.v:6027$1576_Y
+ connect \B $eq$ls180.v:6027$1577_Y
+ connect \Y $and$ls180.v:6027$1578_Y
end
- attribute \src "ls180.v:6007.45-6007.98"
- cell $and $and$ls180.v:6007$1627
+ attribute \src "ls180.v:6029.46-6029.99"
+ cell $and $and$ls180.v:6029$1579
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:6007$1627_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:6029$1579_Y
end
- attribute \src "ls180.v:6007.44-6007.149"
- cell $and $and$ls180.v:6007$1629
+ attribute \src "ls180.v:6029.45-6029.150"
+ cell $and $and$ls180.v:6029$1581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6007$1627_Y
- connect \B $eq$ls180.v:6007$1628_Y
- connect \Y $and$ls180.v:6007$1629_Y
+ connect \A $and$ls180.v:6029$1579_Y
+ connect \B $eq$ls180.v:6029$1580_Y
+ connect \Y $and$ls180.v:6029$1581_Y
end
- attribute \src "ls180.v:6008.45-6008.101"
- cell $and $and$ls180.v:6008$1631
+ attribute \src "ls180.v:6030.46-6030.102"
+ cell $and $and$ls180.v:6030$1583
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:6008$1630_Y
- connect \Y $and$ls180.v:6008$1631_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6030$1582_Y
+ connect \Y $and$ls180.v:6030$1583_Y
end
- attribute \src "ls180.v:6008.44-6008.152"
- cell $and $and$ls180.v:6008$1633
+ attribute \src "ls180.v:6030.45-6030.153"
+ cell $and $and$ls180.v:6030$1585
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6008$1631_Y
- connect \B $eq$ls180.v:6008$1632_Y
- connect \Y $and$ls180.v:6008$1633_Y
+ connect \A $and$ls180.v:6030$1583_Y
+ connect \B $eq$ls180.v:6030$1584_Y
+ connect \Y $and$ls180.v:6030$1585_Y
end
- attribute \src "ls180.v:6010.45-6010.98"
- cell $and $and$ls180.v:6010$1634
+ attribute \src "ls180.v:6032.46-6032.99"
+ cell $and $and$ls180.v:6032$1586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:6010$1634_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:6032$1586_Y
end
- attribute \src "ls180.v:6010.44-6010.149"
- cell $and $and$ls180.v:6010$1636
+ attribute \src "ls180.v:6032.45-6032.150"
+ cell $and $and$ls180.v:6032$1588
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6010$1634_Y
- connect \B $eq$ls180.v:6010$1635_Y
- connect \Y $and$ls180.v:6010$1636_Y
+ connect \A $and$ls180.v:6032$1586_Y
+ connect \B $eq$ls180.v:6032$1587_Y
+ connect \Y $and$ls180.v:6032$1588_Y
end
- attribute \src "ls180.v:6011.45-6011.101"
- cell $and $and$ls180.v:6011$1638
+ attribute \src "ls180.v:6033.46-6033.102"
+ cell $and $and$ls180.v:6033$1590
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:6011$1637_Y
- connect \Y $and$ls180.v:6011$1638_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6033$1589_Y
+ connect \Y $and$ls180.v:6033$1590_Y
end
- attribute \src "ls180.v:6011.44-6011.152"
- cell $and $and$ls180.v:6011$1640
+ attribute \src "ls180.v:6033.45-6033.153"
+ cell $and $and$ls180.v:6033$1592
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6011$1638_Y
- connect \B $eq$ls180.v:6011$1639_Y
- connect \Y $and$ls180.v:6011$1640_Y
+ connect \A $and$ls180.v:6033$1590_Y
+ connect \B $eq$ls180.v:6033$1591_Y
+ connect \Y $and$ls180.v:6033$1592_Y
end
- attribute \src "ls180.v:6013.45-6013.98"
- cell $and $and$ls180.v:6013$1641
+ attribute \src "ls180.v:6035.46-6035.99"
+ cell $and $and$ls180.v:6035$1593
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:6013$1641_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:6035$1593_Y
end
- attribute \src "ls180.v:6013.44-6013.149"
- cell $and $and$ls180.v:6013$1643
+ attribute \src "ls180.v:6035.45-6035.150"
+ cell $and $and$ls180.v:6035$1595
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6013$1641_Y
- connect \B $eq$ls180.v:6013$1642_Y
- connect \Y $and$ls180.v:6013$1643_Y
+ connect \A $and$ls180.v:6035$1593_Y
+ connect \B $eq$ls180.v:6035$1594_Y
+ connect \Y $and$ls180.v:6035$1595_Y
end
- attribute \src "ls180.v:6014.45-6014.101"
- cell $and $and$ls180.v:6014$1645
+ attribute \src "ls180.v:6036.46-6036.102"
+ cell $and $and$ls180.v:6036$1597
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:6014$1644_Y
- connect \Y $and$ls180.v:6014$1645_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6036$1596_Y
+ connect \Y $and$ls180.v:6036$1597_Y
end
- attribute \src "ls180.v:6014.44-6014.152"
- cell $and $and$ls180.v:6014$1647
+ attribute \src "ls180.v:6036.45-6036.153"
+ cell $and $and$ls180.v:6036$1599
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6014$1645_Y
- connect \B $eq$ls180.v:6014$1646_Y
- connect \Y $and$ls180.v:6014$1647_Y
+ connect \A $and$ls180.v:6036$1597_Y
+ connect \B $eq$ls180.v:6036$1598_Y
+ connect \Y $and$ls180.v:6036$1599_Y
end
- attribute \src "ls180.v:6016.45-6016.98"
- cell $and $and$ls180.v:6016$1648
+ attribute \src "ls180.v:6038.46-6038.99"
+ cell $and $and$ls180.v:6038$1600
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B \builder_interface5_bank_bus_we
- connect \Y $and$ls180.v:6016$1648_Y
+ connect \A \builder_csrbank6_sel
+ connect \B \builder_interface6_bank_bus_we
+ connect \Y $and$ls180.v:6038$1600_Y
end
- attribute \src "ls180.v:6016.44-6016.149"
- cell $and $and$ls180.v:6016$1650
+ attribute \src "ls180.v:6038.45-6038.150"
+ cell $and $and$ls180.v:6038$1602
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6016$1648_Y
- connect \B $eq$ls180.v:6016$1649_Y
- connect \Y $and$ls180.v:6016$1650_Y
+ connect \A $and$ls180.v:6038$1600_Y
+ connect \B $eq$ls180.v:6038$1601_Y
+ connect \Y $and$ls180.v:6038$1602_Y
end
- attribute \src "ls180.v:6017.45-6017.101"
- cell $and $and$ls180.v:6017$1652
+ attribute \src "ls180.v:6039.46-6039.102"
+ cell $and $and$ls180.v:6039$1604
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank5_sel
- connect \B $not$ls180.v:6017$1651_Y
- connect \Y $and$ls180.v:6017$1652_Y
+ connect \A \builder_csrbank6_sel
+ connect \B $not$ls180.v:6039$1603_Y
+ connect \Y $and$ls180.v:6039$1604_Y
end
- attribute \src "ls180.v:6017.44-6017.152"
- cell $and $and$ls180.v:6017$1654
+ attribute \src "ls180.v:6039.45-6039.153"
+ cell $and $and$ls180.v:6039$1606
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6017$1652_Y
- connect \B $eq$ls180.v:6017$1653_Y
- connect \Y $and$ls180.v:6017$1654_Y
+ connect \A $and$ls180.v:6039$1604_Y
+ connect \B $eq$ls180.v:6039$1605_Y
+ connect \Y $and$ls180.v:6039$1606_Y
end
- attribute \src "ls180.v:6055.42-6055.95"
- cell $and $and$ls180.v:6055$1656
+ attribute \src "ls180.v:6041.46-6041.99"
+ cell $and $and$ls180.v:6041$1607
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6055$1656_Y
+ connect \Y $and$ls180.v:6041$1607_Y
end
- attribute \src "ls180.v:6055.41-6055.145"
- cell $and $and$ls180.v:6055$1658
+ attribute \src "ls180.v:6041.45-6041.150"
+ cell $and $and$ls180.v:6041$1609
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6055$1656_Y
- connect \B $eq$ls180.v:6055$1657_Y
- connect \Y $and$ls180.v:6055$1658_Y
+ connect \A $and$ls180.v:6041$1607_Y
+ connect \B $eq$ls180.v:6041$1608_Y
+ connect \Y $and$ls180.v:6041$1609_Y
end
- attribute \src "ls180.v:6056.42-6056.98"
- cell $and $and$ls180.v:6056$1660
+ attribute \src "ls180.v:6042.46-6042.102"
+ cell $and $and$ls180.v:6042$1611
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6056$1659_Y
- connect \Y $and$ls180.v:6056$1660_Y
+ connect \B $not$ls180.v:6042$1610_Y
+ connect \Y $and$ls180.v:6042$1611_Y
end
- attribute \src "ls180.v:6056.41-6056.148"
- cell $and $and$ls180.v:6056$1662
+ attribute \src "ls180.v:6042.45-6042.153"
+ cell $and $and$ls180.v:6042$1613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6056$1660_Y
- connect \B $eq$ls180.v:6056$1661_Y
- connect \Y $and$ls180.v:6056$1662_Y
+ connect \A $and$ls180.v:6042$1611_Y
+ connect \B $eq$ls180.v:6042$1612_Y
+ connect \Y $and$ls180.v:6042$1613_Y
end
- attribute \src "ls180.v:6058.42-6058.95"
- cell $and $and$ls180.v:6058$1663
+ attribute \src "ls180.v:6044.42-6044.95"
+ cell $and $and$ls180.v:6044$1614
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6058$1663_Y
+ connect \Y $and$ls180.v:6044$1614_Y
end
- attribute \src "ls180.v:6058.41-6058.145"
- cell $and $and$ls180.v:6058$1665
+ attribute \src "ls180.v:6044.41-6044.146"
+ cell $and $and$ls180.v:6044$1616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6058$1663_Y
- connect \B $eq$ls180.v:6058$1664_Y
- connect \Y $and$ls180.v:6058$1665_Y
+ connect \A $and$ls180.v:6044$1614_Y
+ connect \B $eq$ls180.v:6044$1615_Y
+ connect \Y $and$ls180.v:6044$1616_Y
end
- attribute \src "ls180.v:6059.42-6059.98"
- cell $and $and$ls180.v:6059$1667
+ attribute \src "ls180.v:6045.42-6045.98"
+ cell $and $and$ls180.v:6045$1618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6059$1666_Y
- connect \Y $and$ls180.v:6059$1667_Y
+ connect \B $not$ls180.v:6045$1617_Y
+ connect \Y $and$ls180.v:6045$1618_Y
end
- attribute \src "ls180.v:6059.41-6059.148"
- cell $and $and$ls180.v:6059$1669
+ attribute \src "ls180.v:6045.41-6045.149"
+ cell $and $and$ls180.v:6045$1620
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6059$1667_Y
- connect \B $eq$ls180.v:6059$1668_Y
- connect \Y $and$ls180.v:6059$1669_Y
+ connect \A $and$ls180.v:6045$1618_Y
+ connect \B $eq$ls180.v:6045$1619_Y
+ connect \Y $and$ls180.v:6045$1620_Y
end
- attribute \src "ls180.v:6061.42-6061.95"
- cell $and $and$ls180.v:6061$1670
+ attribute \src "ls180.v:6047.43-6047.96"
+ cell $and $and$ls180.v:6047$1621
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6061$1670_Y
+ connect \Y $and$ls180.v:6047$1621_Y
end
- attribute \src "ls180.v:6061.41-6061.145"
- cell $and $and$ls180.v:6061$1672
+ attribute \src "ls180.v:6047.42-6047.147"
+ cell $and $and$ls180.v:6047$1623
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6061$1670_Y
- connect \B $eq$ls180.v:6061$1671_Y
- connect \Y $and$ls180.v:6061$1672_Y
+ connect \A $and$ls180.v:6047$1621_Y
+ connect \B $eq$ls180.v:6047$1622_Y
+ connect \Y $and$ls180.v:6047$1623_Y
end
- attribute \src "ls180.v:6062.42-6062.98"
- cell $and $and$ls180.v:6062$1674
+ attribute \src "ls180.v:6048.43-6048.99"
+ cell $and $and$ls180.v:6048$1625
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6062$1673_Y
- connect \Y $and$ls180.v:6062$1674_Y
+ connect \B $not$ls180.v:6048$1624_Y
+ connect \Y $and$ls180.v:6048$1625_Y
end
- attribute \src "ls180.v:6062.41-6062.148"
- cell $and $and$ls180.v:6062$1676
+ attribute \src "ls180.v:6048.42-6048.150"
+ cell $and $and$ls180.v:6048$1627
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6062$1674_Y
- connect \B $eq$ls180.v:6062$1675_Y
- connect \Y $and$ls180.v:6062$1676_Y
+ connect \A $and$ls180.v:6048$1625_Y
+ connect \B $eq$ls180.v:6048$1626_Y
+ connect \Y $and$ls180.v:6048$1627_Y
end
- attribute \src "ls180.v:6064.42-6064.95"
- cell $and $and$ls180.v:6064$1677
+ attribute \src "ls180.v:6050.46-6050.99"
+ cell $and $and$ls180.v:6050$1628
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6064$1677_Y
+ connect \Y $and$ls180.v:6050$1628_Y
end
- attribute \src "ls180.v:6064.41-6064.145"
- cell $and $and$ls180.v:6064$1679
+ attribute \src "ls180.v:6050.45-6050.150"
+ cell $and $and$ls180.v:6050$1630
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6064$1677_Y
- connect \B $eq$ls180.v:6064$1678_Y
- connect \Y $and$ls180.v:6064$1679_Y
+ connect \A $and$ls180.v:6050$1628_Y
+ connect \B $eq$ls180.v:6050$1629_Y
+ connect \Y $and$ls180.v:6050$1630_Y
end
- attribute \src "ls180.v:6065.42-6065.98"
- cell $and $and$ls180.v:6065$1681
+ attribute \src "ls180.v:6051.46-6051.102"
+ cell $and $and$ls180.v:6051$1632
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6065$1680_Y
- connect \Y $and$ls180.v:6065$1681_Y
+ connect \B $not$ls180.v:6051$1631_Y
+ connect \Y $and$ls180.v:6051$1632_Y
end
- attribute \src "ls180.v:6065.41-6065.148"
- cell $and $and$ls180.v:6065$1683
+ attribute \src "ls180.v:6051.45-6051.153"
+ cell $and $and$ls180.v:6051$1634
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6065$1681_Y
- connect \B $eq$ls180.v:6065$1682_Y
- connect \Y $and$ls180.v:6065$1683_Y
+ connect \A $and$ls180.v:6051$1632_Y
+ connect \B $eq$ls180.v:6051$1633_Y
+ connect \Y $and$ls180.v:6051$1634_Y
end
- attribute \src "ls180.v:6067.42-6067.95"
- cell $and $and$ls180.v:6067$1684
+ attribute \src "ls180.v:6053.46-6053.99"
+ cell $and $and$ls180.v:6053$1635
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6067$1684_Y
+ connect \Y $and$ls180.v:6053$1635_Y
end
- attribute \src "ls180.v:6067.41-6067.145"
- cell $and $and$ls180.v:6067$1686
+ attribute \src "ls180.v:6053.45-6053.150"
+ cell $and $and$ls180.v:6053$1637
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6067$1684_Y
- connect \B $eq$ls180.v:6067$1685_Y
- connect \Y $and$ls180.v:6067$1686_Y
+ connect \A $and$ls180.v:6053$1635_Y
+ connect \B $eq$ls180.v:6053$1636_Y
+ connect \Y $and$ls180.v:6053$1637_Y
end
- attribute \src "ls180.v:6068.42-6068.98"
- cell $and $and$ls180.v:6068$1688
+ attribute \src "ls180.v:6054.46-6054.102"
+ cell $and $and$ls180.v:6054$1639
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6068$1687_Y
- connect \Y $and$ls180.v:6068$1688_Y
+ connect \B $not$ls180.v:6054$1638_Y
+ connect \Y $and$ls180.v:6054$1639_Y
end
- attribute \src "ls180.v:6068.41-6068.148"
- cell $and $and$ls180.v:6068$1690
+ attribute \src "ls180.v:6054.45-6054.153"
+ cell $and $and$ls180.v:6054$1641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6068$1688_Y
- connect \B $eq$ls180.v:6068$1689_Y
- connect \Y $and$ls180.v:6068$1690_Y
+ connect \A $and$ls180.v:6054$1639_Y
+ connect \B $eq$ls180.v:6054$1640_Y
+ connect \Y $and$ls180.v:6054$1641_Y
end
- attribute \src "ls180.v:6070.42-6070.95"
- cell $and $and$ls180.v:6070$1691
+ attribute \src "ls180.v:6056.45-6056.98"
+ cell $and $and$ls180.v:6056$1642
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6070$1691_Y
+ connect \Y $and$ls180.v:6056$1642_Y
end
- attribute \src "ls180.v:6070.41-6070.145"
- cell $and $and$ls180.v:6070$1693
+ attribute \src "ls180.v:6056.44-6056.149"
+ cell $and $and$ls180.v:6056$1644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6070$1691_Y
- connect \B $eq$ls180.v:6070$1692_Y
- connect \Y $and$ls180.v:6070$1693_Y
+ connect \A $and$ls180.v:6056$1642_Y
+ connect \B $eq$ls180.v:6056$1643_Y
+ connect \Y $and$ls180.v:6056$1644_Y
end
- attribute \src "ls180.v:6071.42-6071.98"
- cell $and $and$ls180.v:6071$1695
+ attribute \src "ls180.v:6057.45-6057.101"
+ cell $and $and$ls180.v:6057$1646
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6071$1694_Y
- connect \Y $and$ls180.v:6071$1695_Y
+ connect \B $not$ls180.v:6057$1645_Y
+ connect \Y $and$ls180.v:6057$1646_Y
end
- attribute \src "ls180.v:6071.41-6071.148"
- cell $and $and$ls180.v:6071$1697
+ attribute \src "ls180.v:6057.44-6057.152"
+ cell $and $and$ls180.v:6057$1648
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6071$1695_Y
- connect \B $eq$ls180.v:6071$1696_Y
- connect \Y $and$ls180.v:6071$1697_Y
+ connect \A $and$ls180.v:6057$1646_Y
+ connect \B $eq$ls180.v:6057$1647_Y
+ connect \Y $and$ls180.v:6057$1648_Y
end
- attribute \src "ls180.v:6073.42-6073.95"
- cell $and $and$ls180.v:6073$1698
+ attribute \src "ls180.v:6059.45-6059.98"
+ cell $and $and$ls180.v:6059$1649
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6073$1698_Y
+ connect \Y $and$ls180.v:6059$1649_Y
end
- attribute \src "ls180.v:6073.41-6073.145"
- cell $and $and$ls180.v:6073$1700
+ attribute \src "ls180.v:6059.44-6059.149"
+ cell $and $and$ls180.v:6059$1651
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6073$1698_Y
- connect \B $eq$ls180.v:6073$1699_Y
- connect \Y $and$ls180.v:6073$1700_Y
+ connect \A $and$ls180.v:6059$1649_Y
+ connect \B $eq$ls180.v:6059$1650_Y
+ connect \Y $and$ls180.v:6059$1651_Y
end
- attribute \src "ls180.v:6074.42-6074.98"
- cell $and $and$ls180.v:6074$1702
+ attribute \src "ls180.v:6060.45-6060.101"
+ cell $and $and$ls180.v:6060$1653
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6074$1701_Y
- connect \Y $and$ls180.v:6074$1702_Y
+ connect \B $not$ls180.v:6060$1652_Y
+ connect \Y $and$ls180.v:6060$1653_Y
end
- attribute \src "ls180.v:6074.41-6074.148"
- cell $and $and$ls180.v:6074$1704
+ attribute \src "ls180.v:6060.44-6060.152"
+ cell $and $and$ls180.v:6060$1655
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6074$1702_Y
- connect \B $eq$ls180.v:6074$1703_Y
- connect \Y $and$ls180.v:6074$1704_Y
+ connect \A $and$ls180.v:6060$1653_Y
+ connect \B $eq$ls180.v:6060$1654_Y
+ connect \Y $and$ls180.v:6060$1655_Y
end
- attribute \src "ls180.v:6076.42-6076.95"
- cell $and $and$ls180.v:6076$1705
+ attribute \src "ls180.v:6062.45-6062.98"
+ cell $and $and$ls180.v:6062$1656
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6076$1705_Y
+ connect \Y $and$ls180.v:6062$1656_Y
end
- attribute \src "ls180.v:6076.41-6076.145"
- cell $and $and$ls180.v:6076$1707
+ attribute \src "ls180.v:6062.44-6062.149"
+ cell $and $and$ls180.v:6062$1658
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6076$1705_Y
- connect \B $eq$ls180.v:6076$1706_Y
- connect \Y $and$ls180.v:6076$1707_Y
+ connect \A $and$ls180.v:6062$1656_Y
+ connect \B $eq$ls180.v:6062$1657_Y
+ connect \Y $and$ls180.v:6062$1658_Y
end
- attribute \src "ls180.v:6077.42-6077.98"
- cell $and $and$ls180.v:6077$1709
+ attribute \src "ls180.v:6063.45-6063.101"
+ cell $and $and$ls180.v:6063$1660
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6077$1708_Y
- connect \Y $and$ls180.v:6077$1709_Y
+ connect \B $not$ls180.v:6063$1659_Y
+ connect \Y $and$ls180.v:6063$1660_Y
end
- attribute \src "ls180.v:6077.41-6077.148"
- cell $and $and$ls180.v:6077$1711
+ attribute \src "ls180.v:6063.44-6063.152"
+ cell $and $and$ls180.v:6063$1662
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6077$1709_Y
- connect \B $eq$ls180.v:6077$1710_Y
- connect \Y $and$ls180.v:6077$1711_Y
+ connect \A $and$ls180.v:6063$1660_Y
+ connect \B $eq$ls180.v:6063$1661_Y
+ connect \Y $and$ls180.v:6063$1662_Y
end
- attribute \src "ls180.v:6079.44-6079.97"
- cell $and $and$ls180.v:6079$1712
+ attribute \src "ls180.v:6065.45-6065.98"
+ cell $and $and$ls180.v:6065$1663
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6079$1712_Y
+ connect \Y $and$ls180.v:6065$1663_Y
end
- attribute \src "ls180.v:6079.43-6079.147"
- cell $and $and$ls180.v:6079$1714
+ attribute \src "ls180.v:6065.44-6065.149"
+ cell $and $and$ls180.v:6065$1665
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6079$1712_Y
- connect \B $eq$ls180.v:6079$1713_Y
- connect \Y $and$ls180.v:6079$1714_Y
+ connect \A $and$ls180.v:6065$1663_Y
+ connect \B $eq$ls180.v:6065$1664_Y
+ connect \Y $and$ls180.v:6065$1665_Y
end
- attribute \src "ls180.v:6080.44-6080.100"
- cell $and $and$ls180.v:6080$1716
+ attribute \src "ls180.v:6066.45-6066.101"
+ cell $and $and$ls180.v:6066$1667
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6080$1715_Y
- connect \Y $and$ls180.v:6080$1716_Y
+ connect \B $not$ls180.v:6066$1666_Y
+ connect \Y $and$ls180.v:6066$1667_Y
end
- attribute \src "ls180.v:6080.43-6080.150"
- cell $and $and$ls180.v:6080$1718
+ attribute \src "ls180.v:6066.44-6066.152"
+ cell $and $and$ls180.v:6066$1669
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6080$1716_Y
- connect \B $eq$ls180.v:6080$1717_Y
- connect \Y $and$ls180.v:6080$1718_Y
+ connect \A $and$ls180.v:6066$1667_Y
+ connect \B $eq$ls180.v:6066$1668_Y
+ connect \Y $and$ls180.v:6066$1669_Y
end
- attribute \src "ls180.v:6082.44-6082.97"
- cell $and $and$ls180.v:6082$1719
+ attribute \src "ls180.v:6104.42-6104.95"
+ cell $and $and$ls180.v:6104$1671
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6082$1719_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6104$1671_Y
end
- attribute \src "ls180.v:6082.43-6082.147"
- cell $and $and$ls180.v:6082$1721
+ attribute \src "ls180.v:6104.41-6104.145"
+ cell $and $and$ls180.v:6104$1673
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6082$1719_Y
- connect \B $eq$ls180.v:6082$1720_Y
- connect \Y $and$ls180.v:6082$1721_Y
+ connect \A $and$ls180.v:6104$1671_Y
+ connect \B $eq$ls180.v:6104$1672_Y
+ connect \Y $and$ls180.v:6104$1673_Y
end
- attribute \src "ls180.v:6083.44-6083.100"
- cell $and $and$ls180.v:6083$1723
+ attribute \src "ls180.v:6105.42-6105.98"
+ cell $and $and$ls180.v:6105$1675
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6083$1722_Y
- connect \Y $and$ls180.v:6083$1723_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6105$1674_Y
+ connect \Y $and$ls180.v:6105$1675_Y
end
- attribute \src "ls180.v:6083.43-6083.150"
- cell $and $and$ls180.v:6083$1725
+ attribute \src "ls180.v:6105.41-6105.148"
+ cell $and $and$ls180.v:6105$1677
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6083$1723_Y
- connect \B $eq$ls180.v:6083$1724_Y
- connect \Y $and$ls180.v:6083$1725_Y
+ connect \A $and$ls180.v:6105$1675_Y
+ connect \B $eq$ls180.v:6105$1676_Y
+ connect \Y $and$ls180.v:6105$1677_Y
end
- attribute \src "ls180.v:6085.44-6085.97"
- cell $and $and$ls180.v:6085$1726
+ attribute \src "ls180.v:6107.42-6107.95"
+ cell $and $and$ls180.v:6107$1678
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6085$1726_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6107$1678_Y
end
- attribute \src "ls180.v:6085.43-6085.148"
- cell $and $and$ls180.v:6085$1728
+ attribute \src "ls180.v:6107.41-6107.145"
+ cell $and $and$ls180.v:6107$1680
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6085$1726_Y
- connect \B $eq$ls180.v:6085$1727_Y
- connect \Y $and$ls180.v:6085$1728_Y
+ connect \A $and$ls180.v:6107$1678_Y
+ connect \B $eq$ls180.v:6107$1679_Y
+ connect \Y $and$ls180.v:6107$1680_Y
end
- attribute \src "ls180.v:6086.44-6086.100"
- cell $and $and$ls180.v:6086$1730
+ attribute \src "ls180.v:6108.42-6108.98"
+ cell $and $and$ls180.v:6108$1682
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6086$1729_Y
- connect \Y $and$ls180.v:6086$1730_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6108$1681_Y
+ connect \Y $and$ls180.v:6108$1682_Y
end
- attribute \src "ls180.v:6086.43-6086.151"
- cell $and $and$ls180.v:6086$1732
+ attribute \src "ls180.v:6108.41-6108.148"
+ cell $and $and$ls180.v:6108$1684
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6086$1730_Y
- connect \B $eq$ls180.v:6086$1731_Y
- connect \Y $and$ls180.v:6086$1732_Y
+ connect \A $and$ls180.v:6108$1682_Y
+ connect \B $eq$ls180.v:6108$1683_Y
+ connect \Y $and$ls180.v:6108$1684_Y
end
- attribute \src "ls180.v:6088.44-6088.97"
- cell $and $and$ls180.v:6088$1733
+ attribute \src "ls180.v:6110.42-6110.95"
+ cell $and $and$ls180.v:6110$1685
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6088$1733_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6110$1685_Y
end
- attribute \src "ls180.v:6088.43-6088.148"
- cell $and $and$ls180.v:6088$1735
+ attribute \src "ls180.v:6110.41-6110.145"
+ cell $and $and$ls180.v:6110$1687
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6088$1733_Y
- connect \B $eq$ls180.v:6088$1734_Y
- connect \Y $and$ls180.v:6088$1735_Y
+ connect \A $and$ls180.v:6110$1685_Y
+ connect \B $eq$ls180.v:6110$1686_Y
+ connect \Y $and$ls180.v:6110$1687_Y
end
- attribute \src "ls180.v:6089.44-6089.100"
- cell $and $and$ls180.v:6089$1737
+ attribute \src "ls180.v:6111.42-6111.98"
+ cell $and $and$ls180.v:6111$1689
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6089$1736_Y
- connect \Y $and$ls180.v:6089$1737_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6111$1688_Y
+ connect \Y $and$ls180.v:6111$1689_Y
end
- attribute \src "ls180.v:6089.43-6089.151"
- cell $and $and$ls180.v:6089$1739
+ attribute \src "ls180.v:6111.41-6111.148"
+ cell $and $and$ls180.v:6111$1691
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6089$1737_Y
- connect \B $eq$ls180.v:6089$1738_Y
- connect \Y $and$ls180.v:6089$1739_Y
+ connect \A $and$ls180.v:6111$1689_Y
+ connect \B $eq$ls180.v:6111$1690_Y
+ connect \Y $and$ls180.v:6111$1691_Y
end
- attribute \src "ls180.v:6091.44-6091.97"
- cell $and $and$ls180.v:6091$1740
+ attribute \src "ls180.v:6113.42-6113.95"
+ cell $and $and$ls180.v:6113$1692
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6091$1740_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6113$1692_Y
end
- attribute \src "ls180.v:6091.43-6091.148"
- cell $and $and$ls180.v:6091$1742
+ attribute \src "ls180.v:6113.41-6113.145"
+ cell $and $and$ls180.v:6113$1694
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6091$1740_Y
- connect \B $eq$ls180.v:6091$1741_Y
- connect \Y $and$ls180.v:6091$1742_Y
+ connect \A $and$ls180.v:6113$1692_Y
+ connect \B $eq$ls180.v:6113$1693_Y
+ connect \Y $and$ls180.v:6113$1694_Y
end
- attribute \src "ls180.v:6092.44-6092.100"
- cell $and $and$ls180.v:6092$1744
+ attribute \src "ls180.v:6114.42-6114.98"
+ cell $and $and$ls180.v:6114$1696
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6092$1743_Y
- connect \Y $and$ls180.v:6092$1744_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6114$1695_Y
+ connect \Y $and$ls180.v:6114$1696_Y
end
- attribute \src "ls180.v:6092.43-6092.151"
- cell $and $and$ls180.v:6092$1746
+ attribute \src "ls180.v:6114.41-6114.148"
+ cell $and $and$ls180.v:6114$1698
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6092$1744_Y
- connect \B $eq$ls180.v:6092$1745_Y
- connect \Y $and$ls180.v:6092$1746_Y
+ connect \A $and$ls180.v:6114$1696_Y
+ connect \B $eq$ls180.v:6114$1697_Y
+ connect \Y $and$ls180.v:6114$1698_Y
end
- attribute \src "ls180.v:6094.41-6094.94"
- cell $and $and$ls180.v:6094$1747
+ attribute \src "ls180.v:6116.42-6116.95"
+ cell $and $and$ls180.v:6116$1699
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6094$1747_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6116$1699_Y
end
- attribute \src "ls180.v:6094.40-6094.145"
- cell $and $and$ls180.v:6094$1749
+ attribute \src "ls180.v:6116.41-6116.145"
+ cell $and $and$ls180.v:6116$1701
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6094$1747_Y
- connect \B $eq$ls180.v:6094$1748_Y
- connect \Y $and$ls180.v:6094$1749_Y
+ connect \A $and$ls180.v:6116$1699_Y
+ connect \B $eq$ls180.v:6116$1700_Y
+ connect \Y $and$ls180.v:6116$1701_Y
end
- attribute \src "ls180.v:6095.41-6095.97"
- cell $and $and$ls180.v:6095$1751
+ attribute \src "ls180.v:6117.42-6117.98"
+ cell $and $and$ls180.v:6117$1703
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6095$1750_Y
- connect \Y $and$ls180.v:6095$1751_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6117$1702_Y
+ connect \Y $and$ls180.v:6117$1703_Y
end
- attribute \src "ls180.v:6095.40-6095.148"
- cell $and $and$ls180.v:6095$1753
+ attribute \src "ls180.v:6117.41-6117.148"
+ cell $and $and$ls180.v:6117$1705
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6095$1751_Y
- connect \B $eq$ls180.v:6095$1752_Y
- connect \Y $and$ls180.v:6095$1753_Y
+ connect \A $and$ls180.v:6117$1703_Y
+ connect \B $eq$ls180.v:6117$1704_Y
+ connect \Y $and$ls180.v:6117$1705_Y
end
- attribute \src "ls180.v:6097.42-6097.95"
- cell $and $and$ls180.v:6097$1754
+ attribute \src "ls180.v:6119.42-6119.95"
+ cell $and $and$ls180.v:6119$1706
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6097$1754_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6119$1706_Y
end
- attribute \src "ls180.v:6097.41-6097.146"
- cell $and $and$ls180.v:6097$1756
+ attribute \src "ls180.v:6119.41-6119.145"
+ cell $and $and$ls180.v:6119$1708
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6097$1754_Y
- connect \B $eq$ls180.v:6097$1755_Y
- connect \Y $and$ls180.v:6097$1756_Y
+ connect \A $and$ls180.v:6119$1706_Y
+ connect \B $eq$ls180.v:6119$1707_Y
+ connect \Y $and$ls180.v:6119$1708_Y
end
- attribute \src "ls180.v:6098.42-6098.98"
- cell $and $and$ls180.v:6098$1758
+ attribute \src "ls180.v:6120.42-6120.98"
+ cell $and $and$ls180.v:6120$1710
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6098$1757_Y
- connect \Y $and$ls180.v:6098$1758_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6120$1709_Y
+ connect \Y $and$ls180.v:6120$1710_Y
end
- attribute \src "ls180.v:6098.41-6098.149"
- cell $and $and$ls180.v:6098$1760
+ attribute \src "ls180.v:6120.41-6120.148"
+ cell $and $and$ls180.v:6120$1712
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6098$1758_Y
- connect \B $eq$ls180.v:6098$1759_Y
- connect \Y $and$ls180.v:6098$1760_Y
+ connect \A $and$ls180.v:6120$1710_Y
+ connect \B $eq$ls180.v:6120$1711_Y
+ connect \Y $and$ls180.v:6120$1712_Y
end
- attribute \src "ls180.v:6100.44-6100.97"
- cell $and $and$ls180.v:6100$1761
+ attribute \src "ls180.v:6122.42-6122.95"
+ cell $and $and$ls180.v:6122$1713
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6100$1761_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6122$1713_Y
end
- attribute \src "ls180.v:6100.43-6100.148"
- cell $and $and$ls180.v:6100$1763
+ attribute \src "ls180.v:6122.41-6122.145"
+ cell $and $and$ls180.v:6122$1715
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6100$1761_Y
- connect \B $eq$ls180.v:6100$1762_Y
- connect \Y $and$ls180.v:6100$1763_Y
+ connect \A $and$ls180.v:6122$1713_Y
+ connect \B $eq$ls180.v:6122$1714_Y
+ connect \Y $and$ls180.v:6122$1715_Y
end
- attribute \src "ls180.v:6101.44-6101.100"
- cell $and $and$ls180.v:6101$1765
+ attribute \src "ls180.v:6123.42-6123.98"
+ cell $and $and$ls180.v:6123$1717
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6101$1764_Y
- connect \Y $and$ls180.v:6101$1765_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6123$1716_Y
+ connect \Y $and$ls180.v:6123$1717_Y
end
- attribute \src "ls180.v:6101.43-6101.151"
- cell $and $and$ls180.v:6101$1767
+ attribute \src "ls180.v:6123.41-6123.148"
+ cell $and $and$ls180.v:6123$1719
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6101$1765_Y
- connect \B $eq$ls180.v:6101$1766_Y
- connect \Y $and$ls180.v:6101$1767_Y
+ connect \A $and$ls180.v:6123$1717_Y
+ connect \B $eq$ls180.v:6123$1718_Y
+ connect \Y $and$ls180.v:6123$1719_Y
end
- attribute \src "ls180.v:6103.44-6103.97"
- cell $and $and$ls180.v:6103$1768
+ attribute \src "ls180.v:6125.42-6125.95"
+ cell $and $and$ls180.v:6125$1720
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6103$1768_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6125$1720_Y
end
- attribute \src "ls180.v:6103.43-6103.148"
- cell $and $and$ls180.v:6103$1770
+ attribute \src "ls180.v:6125.41-6125.145"
+ cell $and $and$ls180.v:6125$1722
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6103$1768_Y
- connect \B $eq$ls180.v:6103$1769_Y
- connect \Y $and$ls180.v:6103$1770_Y
+ connect \A $and$ls180.v:6125$1720_Y
+ connect \B $eq$ls180.v:6125$1721_Y
+ connect \Y $and$ls180.v:6125$1722_Y
end
- attribute \src "ls180.v:6104.44-6104.100"
- cell $and $and$ls180.v:6104$1772
+ attribute \src "ls180.v:6126.42-6126.98"
+ cell $and $and$ls180.v:6126$1724
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6104$1771_Y
- connect \Y $and$ls180.v:6104$1772_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6126$1723_Y
+ connect \Y $and$ls180.v:6126$1724_Y
end
- attribute \src "ls180.v:6104.43-6104.151"
- cell $and $and$ls180.v:6104$1774
+ attribute \src "ls180.v:6126.41-6126.148"
+ cell $and $and$ls180.v:6126$1726
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6104$1772_Y
- connect \B $eq$ls180.v:6104$1773_Y
- connect \Y $and$ls180.v:6104$1774_Y
+ connect \A $and$ls180.v:6126$1724_Y
+ connect \B $eq$ls180.v:6126$1725_Y
+ connect \Y $and$ls180.v:6126$1726_Y
end
- attribute \src "ls180.v:6106.44-6106.97"
- cell $and $and$ls180.v:6106$1775
+ attribute \src "ls180.v:6128.44-6128.97"
+ cell $and $and$ls180.v:6128$1727
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6106$1775_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6128$1727_Y
end
- attribute \src "ls180.v:6106.43-6106.148"
- cell $and $and$ls180.v:6106$1777
+ attribute \src "ls180.v:6128.43-6128.147"
+ cell $and $and$ls180.v:6128$1729
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6106$1775_Y
- connect \B $eq$ls180.v:6106$1776_Y
- connect \Y $and$ls180.v:6106$1777_Y
+ connect \A $and$ls180.v:6128$1727_Y
+ connect \B $eq$ls180.v:6128$1728_Y
+ connect \Y $and$ls180.v:6128$1729_Y
end
- attribute \src "ls180.v:6107.44-6107.100"
- cell $and $and$ls180.v:6107$1779
+ attribute \src "ls180.v:6129.44-6129.100"
+ cell $and $and$ls180.v:6129$1731
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6107$1778_Y
- connect \Y $and$ls180.v:6107$1779_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6129$1730_Y
+ connect \Y $and$ls180.v:6129$1731_Y
end
- attribute \src "ls180.v:6107.43-6107.151"
- cell $and $and$ls180.v:6107$1781
+ attribute \src "ls180.v:6129.43-6129.150"
+ cell $and $and$ls180.v:6129$1733
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6107$1779_Y
- connect \B $eq$ls180.v:6107$1780_Y
- connect \Y $and$ls180.v:6107$1781_Y
+ connect \A $and$ls180.v:6129$1731_Y
+ connect \B $eq$ls180.v:6129$1732_Y
+ connect \Y $and$ls180.v:6129$1733_Y
end
- attribute \src "ls180.v:6109.44-6109.97"
- cell $and $and$ls180.v:6109$1782
+ attribute \src "ls180.v:6131.44-6131.97"
+ cell $and $and$ls180.v:6131$1734
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B \builder_interface6_bank_bus_we
- connect \Y $and$ls180.v:6109$1782_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6131$1734_Y
end
- attribute \src "ls180.v:6109.43-6109.148"
- cell $and $and$ls180.v:6109$1784
+ attribute \src "ls180.v:6131.43-6131.147"
+ cell $and $and$ls180.v:6131$1736
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6109$1782_Y
- connect \B $eq$ls180.v:6109$1783_Y
- connect \Y $and$ls180.v:6109$1784_Y
+ connect \A $and$ls180.v:6131$1734_Y
+ connect \B $eq$ls180.v:6131$1735_Y
+ connect \Y $and$ls180.v:6131$1736_Y
end
- attribute \src "ls180.v:6110.44-6110.100"
- cell $and $and$ls180.v:6110$1786
+ attribute \src "ls180.v:6132.44-6132.100"
+ cell $and $and$ls180.v:6132$1738
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank6_sel
- connect \B $not$ls180.v:6110$1785_Y
- connect \Y $and$ls180.v:6110$1786_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6132$1737_Y
+ connect \Y $and$ls180.v:6132$1738_Y
end
- attribute \src "ls180.v:6110.43-6110.151"
- cell $and $and$ls180.v:6110$1788
+ attribute \src "ls180.v:6132.43-6132.150"
+ cell $and $and$ls180.v:6132$1740
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6110$1786_Y
- connect \B $eq$ls180.v:6110$1787_Y
- connect \Y $and$ls180.v:6110$1788_Y
+ connect \A $and$ls180.v:6132$1738_Y
+ connect \B $eq$ls180.v:6132$1739_Y
+ connect \Y $and$ls180.v:6132$1740_Y
end
attribute \src "ls180.v:6134.44-6134.97"
- cell $and $and$ls180.v:6134$1790
+ cell $and $and$ls180.v:6134$1741
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6134$1790_Y
+ connect \Y $and$ls180.v:6134$1741_Y
end
- attribute \src "ls180.v:6134.43-6134.147"
- cell $and $and$ls180.v:6134$1792
+ attribute \src "ls180.v:6134.43-6134.148"
+ cell $and $and$ls180.v:6134$1743
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6134$1790_Y
- connect \B $eq$ls180.v:6134$1791_Y
- connect \Y $and$ls180.v:6134$1792_Y
+ connect \A $and$ls180.v:6134$1741_Y
+ connect \B $eq$ls180.v:6134$1742_Y
+ connect \Y $and$ls180.v:6134$1743_Y
end
attribute \src "ls180.v:6135.44-6135.100"
- cell $and $and$ls180.v:6135$1794
+ cell $and $and$ls180.v:6135$1745
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6135$1793_Y
- connect \Y $and$ls180.v:6135$1794_Y
+ connect \B $not$ls180.v:6135$1744_Y
+ connect \Y $and$ls180.v:6135$1745_Y
end
- attribute \src "ls180.v:6135.43-6135.150"
- cell $and $and$ls180.v:6135$1796
+ attribute \src "ls180.v:6135.43-6135.151"
+ cell $and $and$ls180.v:6135$1747
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6135$1794_Y
- connect \B $eq$ls180.v:6135$1795_Y
- connect \Y $and$ls180.v:6135$1796_Y
+ connect \A $and$ls180.v:6135$1745_Y
+ connect \B $eq$ls180.v:6135$1746_Y
+ connect \Y $and$ls180.v:6135$1747_Y
end
- attribute \src "ls180.v:6137.49-6137.102"
- cell $and $and$ls180.v:6137$1797
+ attribute \src "ls180.v:6137.44-6137.97"
+ cell $and $and$ls180.v:6137$1748
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6137$1797_Y
+ connect \Y $and$ls180.v:6137$1748_Y
end
- attribute \src "ls180.v:6137.48-6137.152"
- cell $and $and$ls180.v:6137$1799
+ attribute \src "ls180.v:6137.43-6137.148"
+ cell $and $and$ls180.v:6137$1750
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6137$1797_Y
- connect \B $eq$ls180.v:6137$1798_Y
- connect \Y $and$ls180.v:6137$1799_Y
+ connect \A $and$ls180.v:6137$1748_Y
+ connect \B $eq$ls180.v:6137$1749_Y
+ connect \Y $and$ls180.v:6137$1750_Y
end
- attribute \src "ls180.v:6138.49-6138.105"
- cell $and $and$ls180.v:6138$1801
+ attribute \src "ls180.v:6138.44-6138.100"
+ cell $and $and$ls180.v:6138$1752
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6138$1800_Y
- connect \Y $and$ls180.v:6138$1801_Y
+ connect \B $not$ls180.v:6138$1751_Y
+ connect \Y $and$ls180.v:6138$1752_Y
end
- attribute \src "ls180.v:6138.48-6138.155"
- cell $and $and$ls180.v:6138$1803
+ attribute \src "ls180.v:6138.43-6138.151"
+ cell $and $and$ls180.v:6138$1754
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6138$1801_Y
- connect \B $eq$ls180.v:6138$1802_Y
- connect \Y $and$ls180.v:6138$1803_Y
+ connect \A $and$ls180.v:6138$1752_Y
+ connect \B $eq$ls180.v:6138$1753_Y
+ connect \Y $and$ls180.v:6138$1754_Y
end
- attribute \src "ls180.v:6140.49-6140.102"
- cell $and $and$ls180.v:6140$1804
+ attribute \src "ls180.v:6140.44-6140.97"
+ cell $and $and$ls180.v:6140$1755
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6140$1804_Y
+ connect \Y $and$ls180.v:6140$1755_Y
end
- attribute \src "ls180.v:6140.48-6140.152"
- cell $and $and$ls180.v:6140$1806
+ attribute \src "ls180.v:6140.43-6140.148"
+ cell $and $and$ls180.v:6140$1757
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6140$1804_Y
- connect \B $eq$ls180.v:6140$1805_Y
- connect \Y $and$ls180.v:6140$1806_Y
+ connect \A $and$ls180.v:6140$1755_Y
+ connect \B $eq$ls180.v:6140$1756_Y
+ connect \Y $and$ls180.v:6140$1757_Y
end
- attribute \src "ls180.v:6141.49-6141.105"
- cell $and $and$ls180.v:6141$1808
+ attribute \src "ls180.v:6141.44-6141.100"
+ cell $and $and$ls180.v:6141$1759
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6141$1807_Y
- connect \Y $and$ls180.v:6141$1808_Y
+ connect \B $not$ls180.v:6141$1758_Y
+ connect \Y $and$ls180.v:6141$1759_Y
end
- attribute \src "ls180.v:6141.48-6141.155"
- cell $and $and$ls180.v:6141$1810
+ attribute \src "ls180.v:6141.43-6141.151"
+ cell $and $and$ls180.v:6141$1761
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6141$1808_Y
- connect \B $eq$ls180.v:6141$1809_Y
- connect \Y $and$ls180.v:6141$1810_Y
+ connect \A $and$ls180.v:6141$1759_Y
+ connect \B $eq$ls180.v:6141$1760_Y
+ connect \Y $and$ls180.v:6141$1761_Y
end
- attribute \src "ls180.v:6143.42-6143.95"
- cell $and $and$ls180.v:6143$1811
+ attribute \src "ls180.v:6143.41-6143.94"
+ cell $and $and$ls180.v:6143$1762
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
connect \B \builder_interface7_bank_bus_we
- connect \Y $and$ls180.v:6143$1811_Y
+ connect \Y $and$ls180.v:6143$1762_Y
end
- attribute \src "ls180.v:6143.41-6143.145"
- cell $and $and$ls180.v:6143$1813
+ attribute \src "ls180.v:6143.40-6143.145"
+ cell $and $and$ls180.v:6143$1764
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6143$1811_Y
- connect \B $eq$ls180.v:6143$1812_Y
- connect \Y $and$ls180.v:6143$1813_Y
+ connect \A $and$ls180.v:6143$1762_Y
+ connect \B $eq$ls180.v:6143$1763_Y
+ connect \Y $and$ls180.v:6143$1764_Y
end
- attribute \src "ls180.v:6144.42-6144.98"
- cell $and $and$ls180.v:6144$1815
+ attribute \src "ls180.v:6144.41-6144.97"
+ cell $and $and$ls180.v:6144$1766
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank7_sel
- connect \B $not$ls180.v:6144$1814_Y
- connect \Y $and$ls180.v:6144$1815_Y
+ connect \B $not$ls180.v:6144$1765_Y
+ connect \Y $and$ls180.v:6144$1766_Y
end
- attribute \src "ls180.v:6144.41-6144.148"
- cell $and $and$ls180.v:6144$1817
+ attribute \src "ls180.v:6144.40-6144.148"
+ cell $and $and$ls180.v:6144$1768
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6144$1815_Y
- connect \B $eq$ls180.v:6144$1816_Y
- connect \Y $and$ls180.v:6144$1817_Y
+ connect \A $and$ls180.v:6144$1766_Y
+ connect \B $eq$ls180.v:6144$1767_Y
+ connect \Y $and$ls180.v:6144$1768_Y
end
- attribute \src "ls180.v:6151.46-6151.99"
- cell $and $and$ls180.v:6151$1819
+ attribute \src "ls180.v:6146.42-6146.95"
+ cell $and $and$ls180.v:6146$1769
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank8_sel
- connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6151$1819_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6146$1769_Y
end
- attribute \src "ls180.v:6151.45-6151.149"
- cell $and $and$ls180.v:6151$1821
+ attribute \src "ls180.v:6146.41-6146.146"
+ cell $and $and$ls180.v:6146$1771
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6151$1819_Y
- connect \B $eq$ls180.v:6151$1820_Y
- connect \Y $and$ls180.v:6151$1821_Y
+ connect \A $and$ls180.v:6146$1769_Y
+ connect \B $eq$ls180.v:6146$1770_Y
+ connect \Y $and$ls180.v:6146$1771_Y
end
- attribute \src "ls180.v:6152.46-6152.102"
- cell $and $and$ls180.v:6152$1823
+ attribute \src "ls180.v:6147.42-6147.98"
+ cell $and $and$ls180.v:6147$1773
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6152$1822_Y
- connect \Y $and$ls180.v:6152$1823_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6147$1772_Y
+ connect \Y $and$ls180.v:6147$1773_Y
end
- attribute \src "ls180.v:6152.45-6152.152"
- cell $and $and$ls180.v:6152$1825
+ attribute \src "ls180.v:6147.41-6147.149"
+ cell $and $and$ls180.v:6147$1775
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6152$1823_Y
- connect \B $eq$ls180.v:6152$1824_Y
- connect \Y $and$ls180.v:6152$1825_Y
+ connect \A $and$ls180.v:6147$1773_Y
+ connect \B $eq$ls180.v:6147$1774_Y
+ connect \Y $and$ls180.v:6147$1775_Y
end
- attribute \src "ls180.v:6154.50-6154.103"
- cell $and $and$ls180.v:6154$1826
+ attribute \src "ls180.v:6149.44-6149.97"
+ cell $and $and$ls180.v:6149$1776
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank8_sel
- connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6154$1826_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6149$1776_Y
end
- attribute \src "ls180.v:6154.49-6154.153"
- cell $and $and$ls180.v:6154$1828
+ attribute \src "ls180.v:6149.43-6149.148"
+ cell $and $and$ls180.v:6149$1778
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6154$1826_Y
- connect \B $eq$ls180.v:6154$1827_Y
- connect \Y $and$ls180.v:6154$1828_Y
+ connect \A $and$ls180.v:6149$1776_Y
+ connect \B $eq$ls180.v:6149$1777_Y
+ connect \Y $and$ls180.v:6149$1778_Y
end
- attribute \src "ls180.v:6155.50-6155.106"
- cell $and $and$ls180.v:6155$1830
+ attribute \src "ls180.v:6150.44-6150.100"
+ cell $and $and$ls180.v:6150$1780
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6155$1829_Y
- connect \Y $and$ls180.v:6155$1830_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6150$1779_Y
+ connect \Y $and$ls180.v:6150$1780_Y
end
- attribute \src "ls180.v:6155.49-6155.156"
- cell $and $and$ls180.v:6155$1832
+ attribute \src "ls180.v:6150.43-6150.151"
+ cell $and $and$ls180.v:6150$1782
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6155$1830_Y
- connect \B $eq$ls180.v:6155$1831_Y
- connect \Y $and$ls180.v:6155$1832_Y
+ connect \A $and$ls180.v:6150$1780_Y
+ connect \B $eq$ls180.v:6150$1781_Y
+ connect \Y $and$ls180.v:6150$1782_Y
end
- attribute \src "ls180.v:6157.40-6157.93"
- cell $and $and$ls180.v:6157$1833
+ attribute \src "ls180.v:6152.44-6152.97"
+ cell $and $and$ls180.v:6152$1783
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank8_sel
- connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6157$1833_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6152$1783_Y
end
- attribute \src "ls180.v:6157.39-6157.143"
- cell $and $and$ls180.v:6157$1835
+ attribute \src "ls180.v:6152.43-6152.148"
+ cell $and $and$ls180.v:6152$1785
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6157$1833_Y
- connect \B $eq$ls180.v:6157$1834_Y
- connect \Y $and$ls180.v:6157$1835_Y
+ connect \A $and$ls180.v:6152$1783_Y
+ connect \B $eq$ls180.v:6152$1784_Y
+ connect \Y $and$ls180.v:6152$1785_Y
end
- attribute \src "ls180.v:6158.40-6158.96"
- cell $and $and$ls180.v:6158$1837
+ attribute \src "ls180.v:6153.44-6153.100"
+ cell $and $and$ls180.v:6153$1787
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6158$1836_Y
- connect \Y $and$ls180.v:6158$1837_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6153$1786_Y
+ connect \Y $and$ls180.v:6153$1787_Y
end
- attribute \src "ls180.v:6158.39-6158.146"
- cell $and $and$ls180.v:6158$1839
+ attribute \src "ls180.v:6153.43-6153.151"
+ cell $and $and$ls180.v:6153$1789
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6158$1837_Y
- connect \B $eq$ls180.v:6158$1838_Y
- connect \Y $and$ls180.v:6158$1839_Y
+ connect \A $and$ls180.v:6153$1787_Y
+ connect \B $eq$ls180.v:6153$1788_Y
+ connect \Y $and$ls180.v:6153$1789_Y
end
- attribute \src "ls180.v:6160.50-6160.103"
- cell $and $and$ls180.v:6160$1840
+ attribute \src "ls180.v:6155.44-6155.97"
+ cell $and $and$ls180.v:6155$1790
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank8_sel
- connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6160$1840_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6155$1790_Y
end
- attribute \src "ls180.v:6160.49-6160.153"
- cell $and $and$ls180.v:6160$1842
+ attribute \src "ls180.v:6155.43-6155.148"
+ cell $and $and$ls180.v:6155$1792
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6160$1840_Y
- connect \B $eq$ls180.v:6160$1841_Y
- connect \Y $and$ls180.v:6160$1842_Y
+ connect \A $and$ls180.v:6155$1790_Y
+ connect \B $eq$ls180.v:6155$1791_Y
+ connect \Y $and$ls180.v:6155$1792_Y
end
- attribute \src "ls180.v:6161.50-6161.106"
- cell $and $and$ls180.v:6161$1844
+ attribute \src "ls180.v:6156.44-6156.100"
+ cell $and $and$ls180.v:6156$1794
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6161$1843_Y
- connect \Y $and$ls180.v:6161$1844_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6156$1793_Y
+ connect \Y $and$ls180.v:6156$1794_Y
end
- attribute \src "ls180.v:6161.49-6161.156"
- cell $and $and$ls180.v:6161$1846
+ attribute \src "ls180.v:6156.43-6156.151"
+ cell $and $and$ls180.v:6156$1796
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6161$1844_Y
- connect \B $eq$ls180.v:6161$1845_Y
- connect \Y $and$ls180.v:6161$1846_Y
+ connect \A $and$ls180.v:6156$1794_Y
+ connect \B $eq$ls180.v:6156$1795_Y
+ connect \Y $and$ls180.v:6156$1796_Y
end
- attribute \src "ls180.v:6163.50-6163.103"
- cell $and $and$ls180.v:6163$1847
+ attribute \src "ls180.v:6158.44-6158.97"
+ cell $and $and$ls180.v:6158$1797
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank8_sel
- connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6163$1847_Y
+ connect \A \builder_csrbank7_sel
+ connect \B \builder_interface7_bank_bus_we
+ connect \Y $and$ls180.v:6158$1797_Y
end
- attribute \src "ls180.v:6163.49-6163.153"
- cell $and $and$ls180.v:6163$1849
+ attribute \src "ls180.v:6158.43-6158.148"
+ cell $and $and$ls180.v:6158$1799
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6163$1847_Y
- connect \B $eq$ls180.v:6163$1848_Y
- connect \Y $and$ls180.v:6163$1849_Y
+ connect \A $and$ls180.v:6158$1797_Y
+ connect \B $eq$ls180.v:6158$1798_Y
+ connect \Y $and$ls180.v:6158$1799_Y
end
- attribute \src "ls180.v:6164.50-6164.106"
- cell $and $and$ls180.v:6164$1851
+ attribute \src "ls180.v:6159.44-6159.100"
+ cell $and $and$ls180.v:6159$1801
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6164$1850_Y
- connect \Y $and$ls180.v:6164$1851_Y
+ connect \A \builder_csrbank7_sel
+ connect \B $not$ls180.v:6159$1800_Y
+ connect \Y $and$ls180.v:6159$1801_Y
end
- attribute \src "ls180.v:6164.49-6164.156"
- cell $and $and$ls180.v:6164$1853
+ attribute \src "ls180.v:6159.43-6159.151"
+ cell $and $and$ls180.v:6159$1803
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6164$1851_Y
- connect \B $eq$ls180.v:6164$1852_Y
- connect \Y $and$ls180.v:6164$1853_Y
+ connect \A $and$ls180.v:6159$1801_Y
+ connect \B $eq$ls180.v:6159$1802_Y
+ connect \Y $and$ls180.v:6159$1803_Y
end
- attribute \src "ls180.v:6166.51-6166.104"
- cell $and $and$ls180.v:6166$1854
+ attribute \src "ls180.v:6183.44-6183.97"
+ cell $and $and$ls180.v:6183$1805
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6166$1854_Y
+ connect \Y $and$ls180.v:6183$1805_Y
end
- attribute \src "ls180.v:6166.50-6166.154"
- cell $and $and$ls180.v:6166$1856
+ attribute \src "ls180.v:6183.43-6183.147"
+ cell $and $and$ls180.v:6183$1807
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6166$1854_Y
- connect \B $eq$ls180.v:6166$1855_Y
- connect \Y $and$ls180.v:6166$1856_Y
+ connect \A $and$ls180.v:6183$1805_Y
+ connect \B $eq$ls180.v:6183$1806_Y
+ connect \Y $and$ls180.v:6183$1807_Y
end
- attribute \src "ls180.v:6167.51-6167.107"
- cell $and $and$ls180.v:6167$1858
+ attribute \src "ls180.v:6184.44-6184.100"
+ cell $and $and$ls180.v:6184$1809
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6167$1857_Y
- connect \Y $and$ls180.v:6167$1858_Y
+ connect \B $not$ls180.v:6184$1808_Y
+ connect \Y $and$ls180.v:6184$1809_Y
end
- attribute \src "ls180.v:6167.50-6167.157"
- cell $and $and$ls180.v:6167$1860
+ attribute \src "ls180.v:6184.43-6184.150"
+ cell $and $and$ls180.v:6184$1811
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6167$1858_Y
- connect \B $eq$ls180.v:6167$1859_Y
- connect \Y $and$ls180.v:6167$1860_Y
+ connect \A $and$ls180.v:6184$1809_Y
+ connect \B $eq$ls180.v:6184$1810_Y
+ connect \Y $and$ls180.v:6184$1811_Y
end
- attribute \src "ls180.v:6169.49-6169.102"
- cell $and $and$ls180.v:6169$1861
+ attribute \src "ls180.v:6186.49-6186.102"
+ cell $and $and$ls180.v:6186$1812
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6169$1861_Y
+ connect \Y $and$ls180.v:6186$1812_Y
end
- attribute \src "ls180.v:6169.48-6169.152"
- cell $and $and$ls180.v:6169$1863
+ attribute \src "ls180.v:6186.48-6186.152"
+ cell $and $and$ls180.v:6186$1814
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6169$1861_Y
- connect \B $eq$ls180.v:6169$1862_Y
- connect \Y $and$ls180.v:6169$1863_Y
+ connect \A $and$ls180.v:6186$1812_Y
+ connect \B $eq$ls180.v:6186$1813_Y
+ connect \Y $and$ls180.v:6186$1814_Y
end
- attribute \src "ls180.v:6170.49-6170.105"
- cell $and $and$ls180.v:6170$1865
+ attribute \src "ls180.v:6187.49-6187.105"
+ cell $and $and$ls180.v:6187$1816
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6170$1864_Y
- connect \Y $and$ls180.v:6170$1865_Y
+ connect \B $not$ls180.v:6187$1815_Y
+ connect \Y $and$ls180.v:6187$1816_Y
end
- attribute \src "ls180.v:6170.48-6170.155"
- cell $and $and$ls180.v:6170$1867
+ attribute \src "ls180.v:6187.48-6187.155"
+ cell $and $and$ls180.v:6187$1818
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6170$1865_Y
- connect \B $eq$ls180.v:6170$1866_Y
- connect \Y $and$ls180.v:6170$1867_Y
+ connect \A $and$ls180.v:6187$1816_Y
+ connect \B $eq$ls180.v:6187$1817_Y
+ connect \Y $and$ls180.v:6187$1818_Y
end
- attribute \src "ls180.v:6172.49-6172.102"
- cell $and $and$ls180.v:6172$1868
+ attribute \src "ls180.v:6189.49-6189.102"
+ cell $and $and$ls180.v:6189$1819
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6172$1868_Y
+ connect \Y $and$ls180.v:6189$1819_Y
end
- attribute \src "ls180.v:6172.48-6172.152"
- cell $and $and$ls180.v:6172$1870
+ attribute \src "ls180.v:6189.48-6189.152"
+ cell $and $and$ls180.v:6189$1821
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6172$1868_Y
- connect \B $eq$ls180.v:6172$1869_Y
- connect \Y $and$ls180.v:6172$1870_Y
+ connect \A $and$ls180.v:6189$1819_Y
+ connect \B $eq$ls180.v:6189$1820_Y
+ connect \Y $and$ls180.v:6189$1821_Y
end
- attribute \src "ls180.v:6173.49-6173.105"
- cell $and $and$ls180.v:6173$1872
+ attribute \src "ls180.v:6190.49-6190.105"
+ cell $and $and$ls180.v:6190$1823
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6173$1871_Y
- connect \Y $and$ls180.v:6173$1872_Y
+ connect \B $not$ls180.v:6190$1822_Y
+ connect \Y $and$ls180.v:6190$1823_Y
end
- attribute \src "ls180.v:6173.48-6173.155"
- cell $and $and$ls180.v:6173$1874
+ attribute \src "ls180.v:6190.48-6190.155"
+ cell $and $and$ls180.v:6190$1825
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6173$1872_Y
- connect \B $eq$ls180.v:6173$1873_Y
- connect \Y $and$ls180.v:6173$1874_Y
+ connect \A $and$ls180.v:6190$1823_Y
+ connect \B $eq$ls180.v:6190$1824_Y
+ connect \Y $and$ls180.v:6190$1825_Y
end
- attribute \src "ls180.v:6175.49-6175.102"
- cell $and $and$ls180.v:6175$1875
+ attribute \src "ls180.v:6192.42-6192.95"
+ cell $and $and$ls180.v:6192$1826
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6175$1875_Y
+ connect \Y $and$ls180.v:6192$1826_Y
end
- attribute \src "ls180.v:6175.48-6175.152"
- cell $and $and$ls180.v:6175$1877
+ attribute \src "ls180.v:6192.41-6192.145"
+ cell $and $and$ls180.v:6192$1828
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6175$1875_Y
- connect \B $eq$ls180.v:6175$1876_Y
- connect \Y $and$ls180.v:6175$1877_Y
+ connect \A $and$ls180.v:6192$1826_Y
+ connect \B $eq$ls180.v:6192$1827_Y
+ connect \Y $and$ls180.v:6192$1828_Y
end
- attribute \src "ls180.v:6176.49-6176.105"
- cell $and $and$ls180.v:6176$1879
+ attribute \src "ls180.v:6193.42-6193.98"
+ cell $and $and$ls180.v:6193$1830
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6176$1878_Y
- connect \Y $and$ls180.v:6176$1879_Y
+ connect \B $not$ls180.v:6193$1829_Y
+ connect \Y $and$ls180.v:6193$1830_Y
end
- attribute \src "ls180.v:6176.48-6176.155"
- cell $and $and$ls180.v:6176$1881
+ attribute \src "ls180.v:6193.41-6193.148"
+ cell $and $and$ls180.v:6193$1832
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6176$1879_Y
- connect \B $eq$ls180.v:6176$1880_Y
- connect \Y $and$ls180.v:6176$1881_Y
+ connect \A $and$ls180.v:6193$1830_Y
+ connect \B $eq$ls180.v:6193$1831_Y
+ connect \Y $and$ls180.v:6193$1832_Y
end
- attribute \src "ls180.v:6178.49-6178.102"
- cell $and $and$ls180.v:6178$1882
+ attribute \src "ls180.v:6200.46-6200.99"
+ cell $and $and$ls180.v:6200$1834
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank8_sel
- connect \B \builder_interface8_bank_bus_we
- connect \Y $and$ls180.v:6178$1882_Y
+ connect \A \builder_csrbank9_sel
+ connect \B \builder_interface9_bank_bus_we
+ connect \Y $and$ls180.v:6200$1834_Y
end
- attribute \src "ls180.v:6178.48-6178.152"
- cell $and $and$ls180.v:6178$1884
+ attribute \src "ls180.v:6200.45-6200.149"
+ cell $and $and$ls180.v:6200$1836
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6178$1882_Y
- connect \B $eq$ls180.v:6178$1883_Y
- connect \Y $and$ls180.v:6178$1884_Y
+ connect \A $and$ls180.v:6200$1834_Y
+ connect \B $eq$ls180.v:6200$1835_Y
+ connect \Y $and$ls180.v:6200$1836_Y
end
- attribute \src "ls180.v:6179.49-6179.105"
- cell $and $and$ls180.v:6179$1886
+ attribute \src "ls180.v:6201.46-6201.102"
+ cell $and $and$ls180.v:6201$1838
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank8_sel
- connect \B $not$ls180.v:6179$1885_Y
- connect \Y $and$ls180.v:6179$1886_Y
+ connect \A \builder_csrbank9_sel
+ connect \B $not$ls180.v:6201$1837_Y
+ connect \Y $and$ls180.v:6201$1838_Y
end
- attribute \src "ls180.v:6179.48-6179.155"
- cell $and $and$ls180.v:6179$1888
+ attribute \src "ls180.v:6201.45-6201.152"
+ cell $and $and$ls180.v:6201$1840
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6179$1886_Y
- connect \B $eq$ls180.v:6179$1887_Y
- connect \Y $and$ls180.v:6179$1888_Y
+ connect \A $and$ls180.v:6201$1838_Y
+ connect \B $eq$ls180.v:6201$1839_Y
+ connect \Y $and$ls180.v:6201$1840_Y
end
- attribute \src "ls180.v:6196.41-6196.94"
- cell $and $and$ls180.v:6196$1890
+ attribute \src "ls180.v:6203.50-6203.103"
+ cell $and $and$ls180.v:6203$1841
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6196$1890_Y
+ connect \Y $and$ls180.v:6203$1841_Y
end
- attribute \src "ls180.v:6196.40-6196.144"
- cell $and $and$ls180.v:6196$1892
+ attribute \src "ls180.v:6203.49-6203.153"
+ cell $and $and$ls180.v:6203$1843
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6196$1890_Y
- connect \B $eq$ls180.v:6196$1891_Y
- connect \Y $and$ls180.v:6196$1892_Y
+ connect \A $and$ls180.v:6203$1841_Y
+ connect \B $eq$ls180.v:6203$1842_Y
+ connect \Y $and$ls180.v:6203$1843_Y
end
- attribute \src "ls180.v:6197.41-6197.97"
- cell $and $and$ls180.v:6197$1894
+ attribute \src "ls180.v:6204.50-6204.106"
+ cell $and $and$ls180.v:6204$1845
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6197$1893_Y
- connect \Y $and$ls180.v:6197$1894_Y
+ connect \B $not$ls180.v:6204$1844_Y
+ connect \Y $and$ls180.v:6204$1845_Y
end
- attribute \src "ls180.v:6197.40-6197.147"
- cell $and $and$ls180.v:6197$1896
+ attribute \src "ls180.v:6204.49-6204.156"
+ cell $and $and$ls180.v:6204$1847
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6197$1894_Y
- connect \B $eq$ls180.v:6197$1895_Y
- connect \Y $and$ls180.v:6197$1896_Y
+ connect \A $and$ls180.v:6204$1845_Y
+ connect \B $eq$ls180.v:6204$1846_Y
+ connect \Y $and$ls180.v:6204$1847_Y
end
- attribute \src "ls180.v:6199.41-6199.94"
- cell $and $and$ls180.v:6199$1897
+ attribute \src "ls180.v:6206.40-6206.93"
+ cell $and $and$ls180.v:6206$1848
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6199$1897_Y
+ connect \Y $and$ls180.v:6206$1848_Y
end
- attribute \src "ls180.v:6199.40-6199.144"
- cell $and $and$ls180.v:6199$1899
+ attribute \src "ls180.v:6206.39-6206.143"
+ cell $and $and$ls180.v:6206$1850
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6199$1897_Y
- connect \B $eq$ls180.v:6199$1898_Y
- connect \Y $and$ls180.v:6199$1899_Y
+ connect \A $and$ls180.v:6206$1848_Y
+ connect \B $eq$ls180.v:6206$1849_Y
+ connect \Y $and$ls180.v:6206$1850_Y
end
- attribute \src "ls180.v:6200.41-6200.97"
- cell $and $and$ls180.v:6200$1901
+ attribute \src "ls180.v:6207.40-6207.96"
+ cell $and $and$ls180.v:6207$1852
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6200$1900_Y
- connect \Y $and$ls180.v:6200$1901_Y
+ connect \B $not$ls180.v:6207$1851_Y
+ connect \Y $and$ls180.v:6207$1852_Y
end
- attribute \src "ls180.v:6200.40-6200.147"
- cell $and $and$ls180.v:6200$1903
+ attribute \src "ls180.v:6207.39-6207.146"
+ cell $and $and$ls180.v:6207$1854
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6200$1901_Y
- connect \B $eq$ls180.v:6200$1902_Y
- connect \Y $and$ls180.v:6200$1903_Y
+ connect \A $and$ls180.v:6207$1852_Y
+ connect \B $eq$ls180.v:6207$1853_Y
+ connect \Y $and$ls180.v:6207$1854_Y
end
- attribute \src "ls180.v:6202.39-6202.92"
- cell $and $and$ls180.v:6202$1904
+ attribute \src "ls180.v:6209.50-6209.103"
+ cell $and $and$ls180.v:6209$1855
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6202$1904_Y
+ connect \Y $and$ls180.v:6209$1855_Y
end
- attribute \src "ls180.v:6202.38-6202.142"
- cell $and $and$ls180.v:6202$1906
+ attribute \src "ls180.v:6209.49-6209.153"
+ cell $and $and$ls180.v:6209$1857
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6202$1904_Y
- connect \B $eq$ls180.v:6202$1905_Y
- connect \Y $and$ls180.v:6202$1906_Y
+ connect \A $and$ls180.v:6209$1855_Y
+ connect \B $eq$ls180.v:6209$1856_Y
+ connect \Y $and$ls180.v:6209$1857_Y
end
- attribute \src "ls180.v:6203.39-6203.95"
- cell $and $and$ls180.v:6203$1908
+ attribute \src "ls180.v:6210.50-6210.106"
+ cell $and $and$ls180.v:6210$1859
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6203$1907_Y
- connect \Y $and$ls180.v:6203$1908_Y
+ connect \B $not$ls180.v:6210$1858_Y
+ connect \Y $and$ls180.v:6210$1859_Y
end
- attribute \src "ls180.v:6203.38-6203.145"
- cell $and $and$ls180.v:6203$1910
+ attribute \src "ls180.v:6210.49-6210.156"
+ cell $and $and$ls180.v:6210$1861
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6203$1908_Y
- connect \B $eq$ls180.v:6203$1909_Y
- connect \Y $and$ls180.v:6203$1910_Y
+ connect \A $and$ls180.v:6210$1859_Y
+ connect \B $eq$ls180.v:6210$1860_Y
+ connect \Y $and$ls180.v:6210$1861_Y
end
- attribute \src "ls180.v:6205.38-6205.91"
- cell $and $and$ls180.v:6205$1911
+ attribute \src "ls180.v:6212.50-6212.103"
+ cell $and $and$ls180.v:6212$1862
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6205$1911_Y
+ connect \Y $and$ls180.v:6212$1862_Y
end
- attribute \src "ls180.v:6205.37-6205.141"
- cell $and $and$ls180.v:6205$1913
+ attribute \src "ls180.v:6212.49-6212.153"
+ cell $and $and$ls180.v:6212$1864
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6205$1911_Y
- connect \B $eq$ls180.v:6205$1912_Y
- connect \Y $and$ls180.v:6205$1913_Y
+ connect \A $and$ls180.v:6212$1862_Y
+ connect \B $eq$ls180.v:6212$1863_Y
+ connect \Y $and$ls180.v:6212$1864_Y
end
- attribute \src "ls180.v:6206.38-6206.94"
- cell $and $and$ls180.v:6206$1915
+ attribute \src "ls180.v:6213.50-6213.106"
+ cell $and $and$ls180.v:6213$1866
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6206$1914_Y
- connect \Y $and$ls180.v:6206$1915_Y
+ connect \B $not$ls180.v:6213$1865_Y
+ connect \Y $and$ls180.v:6213$1866_Y
end
- attribute \src "ls180.v:6206.37-6206.144"
- cell $and $and$ls180.v:6206$1917
+ attribute \src "ls180.v:6213.49-6213.156"
+ cell $and $and$ls180.v:6213$1868
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6206$1915_Y
- connect \B $eq$ls180.v:6206$1916_Y
- connect \Y $and$ls180.v:6206$1917_Y
+ connect \A $and$ls180.v:6213$1866_Y
+ connect \B $eq$ls180.v:6213$1867_Y
+ connect \Y $and$ls180.v:6213$1868_Y
end
- attribute \src "ls180.v:6208.37-6208.90"
- cell $and $and$ls180.v:6208$1918
+ attribute \src "ls180.v:6215.51-6215.104"
+ cell $and $and$ls180.v:6215$1869
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6208$1918_Y
+ connect \Y $and$ls180.v:6215$1869_Y
end
- attribute \src "ls180.v:6208.36-6208.140"
- cell $and $and$ls180.v:6208$1920
+ attribute \src "ls180.v:6215.50-6215.154"
+ cell $and $and$ls180.v:6215$1871
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6208$1918_Y
- connect \B $eq$ls180.v:6208$1919_Y
- connect \Y $and$ls180.v:6208$1920_Y
+ connect \A $and$ls180.v:6215$1869_Y
+ connect \B $eq$ls180.v:6215$1870_Y
+ connect \Y $and$ls180.v:6215$1871_Y
end
- attribute \src "ls180.v:6209.37-6209.93"
- cell $and $and$ls180.v:6209$1922
+ attribute \src "ls180.v:6216.51-6216.107"
+ cell $and $and$ls180.v:6216$1873
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6209$1921_Y
- connect \Y $and$ls180.v:6209$1922_Y
+ connect \B $not$ls180.v:6216$1872_Y
+ connect \Y $and$ls180.v:6216$1873_Y
end
- attribute \src "ls180.v:6209.36-6209.143"
- cell $and $and$ls180.v:6209$1924
+ attribute \src "ls180.v:6216.50-6216.157"
+ cell $and $and$ls180.v:6216$1875
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6209$1922_Y
- connect \B $eq$ls180.v:6209$1923_Y
- connect \Y $and$ls180.v:6209$1924_Y
+ connect \A $and$ls180.v:6216$1873_Y
+ connect \B $eq$ls180.v:6216$1874_Y
+ connect \Y $and$ls180.v:6216$1875_Y
end
- attribute \src "ls180.v:6211.36-6211.89"
- cell $and $and$ls180.v:6211$1925
+ attribute \src "ls180.v:6218.49-6218.102"
+ cell $and $and$ls180.v:6218$1876
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6211$1925_Y
+ connect \Y $and$ls180.v:6218$1876_Y
end
- attribute \src "ls180.v:6211.35-6211.139"
- cell $and $and$ls180.v:6211$1927
+ attribute \src "ls180.v:6218.48-6218.152"
+ cell $and $and$ls180.v:6218$1878
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6211$1925_Y
- connect \B $eq$ls180.v:6211$1926_Y
- connect \Y $and$ls180.v:6211$1927_Y
+ connect \A $and$ls180.v:6218$1876_Y
+ connect \B $eq$ls180.v:6218$1877_Y
+ connect \Y $and$ls180.v:6218$1878_Y
end
- attribute \src "ls180.v:6212.36-6212.92"
- cell $and $and$ls180.v:6212$1929
+ attribute \src "ls180.v:6219.49-6219.105"
+ cell $and $and$ls180.v:6219$1880
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6212$1928_Y
- connect \Y $and$ls180.v:6212$1929_Y
+ connect \B $not$ls180.v:6219$1879_Y
+ connect \Y $and$ls180.v:6219$1880_Y
end
- attribute \src "ls180.v:6212.35-6212.142"
- cell $and $and$ls180.v:6212$1931
+ attribute \src "ls180.v:6219.48-6219.155"
+ cell $and $and$ls180.v:6219$1882
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6212$1929_Y
- connect \B $eq$ls180.v:6212$1930_Y
- connect \Y $and$ls180.v:6212$1931_Y
+ connect \A $and$ls180.v:6219$1880_Y
+ connect \B $eq$ls180.v:6219$1881_Y
+ connect \Y $and$ls180.v:6219$1882_Y
end
- attribute \src "ls180.v:6214.42-6214.95"
- cell $and $and$ls180.v:6214$1932
+ attribute \src "ls180.v:6221.49-6221.102"
+ cell $and $and$ls180.v:6221$1883
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
connect \B \builder_interface9_bank_bus_we
- connect \Y $and$ls180.v:6214$1932_Y
+ connect \Y $and$ls180.v:6221$1883_Y
end
- attribute \src "ls180.v:6214.41-6214.145"
- cell $and $and$ls180.v:6214$1934
+ attribute \src "ls180.v:6221.48-6221.152"
+ cell $and $and$ls180.v:6221$1885
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6214$1932_Y
- connect \B $eq$ls180.v:6214$1933_Y
- connect \Y $and$ls180.v:6214$1934_Y
+ connect \A $and$ls180.v:6221$1883_Y
+ connect \B $eq$ls180.v:6221$1884_Y
+ connect \Y $and$ls180.v:6221$1885_Y
end
- attribute \src "ls180.v:6215.42-6215.98"
- cell $and $and$ls180.v:6215$1936
+ attribute \src "ls180.v:6222.49-6222.105"
+ cell $and $and$ls180.v:6222$1887
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank9_sel
- connect \B $not$ls180.v:6215$1935_Y
- connect \Y $and$ls180.v:6215$1936_Y
+ connect \B $not$ls180.v:6222$1886_Y
+ connect \Y $and$ls180.v:6222$1887_Y
end
- attribute \src "ls180.v:6215.41-6215.148"
- cell $and $and$ls180.v:6215$1938
+ attribute \src "ls180.v:6222.48-6222.155"
+ cell $and $and$ls180.v:6222$1889
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6215$1936_Y
- connect \B $eq$ls180.v:6215$1937_Y
- connect \Y $and$ls180.v:6215$1938_Y
+ connect \A $and$ls180.v:6222$1887_Y
+ connect \B $eq$ls180.v:6222$1888_Y
+ connect \Y $and$ls180.v:6222$1889_Y
end
- attribute \src "ls180.v:6236.42-6236.97"
- cell $and $and$ls180.v:6236$1941
+ attribute \src "ls180.v:6224.49-6224.102"
+ cell $and $and$ls180.v:6224$1890
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank10_sel
- connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6236$1941_Y
+ connect \A \builder_csrbank9_sel
+ connect \B \builder_interface9_bank_bus_we
+ connect \Y $and$ls180.v:6224$1890_Y
end
- attribute \src "ls180.v:6236.41-6236.148"
- cell $and $and$ls180.v:6236$1943
+ attribute \src "ls180.v:6224.48-6224.152"
+ cell $and $and$ls180.v:6224$1892
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6236$1941_Y
- connect \B $eq$ls180.v:6236$1942_Y
- connect \Y $and$ls180.v:6236$1943_Y
+ connect \A $and$ls180.v:6224$1890_Y
+ connect \B $eq$ls180.v:6224$1891_Y
+ connect \Y $and$ls180.v:6224$1892_Y
end
- attribute \src "ls180.v:6237.42-6237.100"
- cell $and $and$ls180.v:6237$1945
+ attribute \src "ls180.v:6225.49-6225.105"
+ cell $and $and$ls180.v:6225$1894
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6237$1944_Y
- connect \Y $and$ls180.v:6237$1945_Y
+ connect \A \builder_csrbank9_sel
+ connect \B $not$ls180.v:6225$1893_Y
+ connect \Y $and$ls180.v:6225$1894_Y
end
- attribute \src "ls180.v:6237.41-6237.151"
- cell $and $and$ls180.v:6237$1947
+ attribute \src "ls180.v:6225.48-6225.155"
+ cell $and $and$ls180.v:6225$1896
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6237$1945_Y
- connect \B $eq$ls180.v:6237$1946_Y
- connect \Y $and$ls180.v:6237$1947_Y
+ connect \A $and$ls180.v:6225$1894_Y
+ connect \B $eq$ls180.v:6225$1895_Y
+ connect \Y $and$ls180.v:6225$1896_Y
end
- attribute \src "ls180.v:6239.42-6239.97"
- cell $and $and$ls180.v:6239$1948
+ attribute \src "ls180.v:6227.49-6227.102"
+ cell $and $and$ls180.v:6227$1897
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank10_sel
- connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6239$1948_Y
+ connect \A \builder_csrbank9_sel
+ connect \B \builder_interface9_bank_bus_we
+ connect \Y $and$ls180.v:6227$1897_Y
end
- attribute \src "ls180.v:6239.41-6239.148"
- cell $and $and$ls180.v:6239$1950
+ attribute \src "ls180.v:6227.48-6227.152"
+ cell $and $and$ls180.v:6227$1899
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6239$1948_Y
- connect \B $eq$ls180.v:6239$1949_Y
- connect \Y $and$ls180.v:6239$1950_Y
+ connect \A $and$ls180.v:6227$1897_Y
+ connect \B $eq$ls180.v:6227$1898_Y
+ connect \Y $and$ls180.v:6227$1899_Y
end
- attribute \src "ls180.v:6240.42-6240.100"
- cell $and $and$ls180.v:6240$1952
+ attribute \src "ls180.v:6228.49-6228.105"
+ cell $and $and$ls180.v:6228$1901
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6240$1951_Y
- connect \Y $and$ls180.v:6240$1952_Y
+ connect \A \builder_csrbank9_sel
+ connect \B $not$ls180.v:6228$1900_Y
+ connect \Y $and$ls180.v:6228$1901_Y
end
- attribute \src "ls180.v:6240.41-6240.151"
- cell $and $and$ls180.v:6240$1954
+ attribute \src "ls180.v:6228.48-6228.155"
+ cell $and $and$ls180.v:6228$1903
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6240$1952_Y
- connect \B $eq$ls180.v:6240$1953_Y
- connect \Y $and$ls180.v:6240$1954_Y
+ connect \A $and$ls180.v:6228$1901_Y
+ connect \B $eq$ls180.v:6228$1902_Y
+ connect \Y $and$ls180.v:6228$1903_Y
end
- attribute \src "ls180.v:6242.40-6242.95"
- cell $and $and$ls180.v:6242$1955
+ attribute \src "ls180.v:6245.42-6245.97"
+ cell $and $and$ls180.v:6245$1905
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6242$1955_Y
+ connect \Y $and$ls180.v:6245$1905_Y
end
- attribute \src "ls180.v:6242.39-6242.146"
- cell $and $and$ls180.v:6242$1957
+ attribute \src "ls180.v:6245.41-6245.148"
+ cell $and $and$ls180.v:6245$1907
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6242$1955_Y
- connect \B $eq$ls180.v:6242$1956_Y
- connect \Y $and$ls180.v:6242$1957_Y
+ connect \A $and$ls180.v:6245$1905_Y
+ connect \B $eq$ls180.v:6245$1906_Y
+ connect \Y $and$ls180.v:6245$1907_Y
end
- attribute \src "ls180.v:6243.40-6243.98"
- cell $and $and$ls180.v:6243$1959
+ attribute \src "ls180.v:6246.42-6246.100"
+ cell $and $and$ls180.v:6246$1909
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6243$1958_Y
- connect \Y $and$ls180.v:6243$1959_Y
+ connect \B $not$ls180.v:6246$1908_Y
+ connect \Y $and$ls180.v:6246$1909_Y
end
- attribute \src "ls180.v:6243.39-6243.149"
- cell $and $and$ls180.v:6243$1961
+ attribute \src "ls180.v:6246.41-6246.151"
+ cell $and $and$ls180.v:6246$1911
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6243$1959_Y
- connect \B $eq$ls180.v:6243$1960_Y
- connect \Y $and$ls180.v:6243$1961_Y
+ connect \A $and$ls180.v:6246$1909_Y
+ connect \B $eq$ls180.v:6246$1910_Y
+ connect \Y $and$ls180.v:6246$1911_Y
end
- attribute \src "ls180.v:6245.39-6245.94"
- cell $and $and$ls180.v:6245$1962
+ attribute \src "ls180.v:6248.42-6248.97"
+ cell $and $and$ls180.v:6248$1912
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6245$1962_Y
+ connect \Y $and$ls180.v:6248$1912_Y
end
- attribute \src "ls180.v:6245.38-6245.145"
- cell $and $and$ls180.v:6245$1964
+ attribute \src "ls180.v:6248.41-6248.148"
+ cell $and $and$ls180.v:6248$1914
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6245$1962_Y
- connect \B $eq$ls180.v:6245$1963_Y
- connect \Y $and$ls180.v:6245$1964_Y
+ connect \A $and$ls180.v:6248$1912_Y
+ connect \B $eq$ls180.v:6248$1913_Y
+ connect \Y $and$ls180.v:6248$1914_Y
end
- attribute \src "ls180.v:6246.39-6246.97"
- cell $and $and$ls180.v:6246$1966
+ attribute \src "ls180.v:6249.42-6249.100"
+ cell $and $and$ls180.v:6249$1916
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6246$1965_Y
- connect \Y $and$ls180.v:6246$1966_Y
+ connect \B $not$ls180.v:6249$1915_Y
+ connect \Y $and$ls180.v:6249$1916_Y
end
- attribute \src "ls180.v:6246.38-6246.148"
- cell $and $and$ls180.v:6246$1968
+ attribute \src "ls180.v:6249.41-6249.151"
+ cell $and $and$ls180.v:6249$1918
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6246$1966_Y
- connect \B $eq$ls180.v:6246$1967_Y
- connect \Y $and$ls180.v:6246$1968_Y
+ connect \A $and$ls180.v:6249$1916_Y
+ connect \B $eq$ls180.v:6249$1917_Y
+ connect \Y $and$ls180.v:6249$1918_Y
end
- attribute \src "ls180.v:6248.38-6248.93"
- cell $and $and$ls180.v:6248$1969
+ attribute \src "ls180.v:6251.40-6251.95"
+ cell $and $and$ls180.v:6251$1919
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6248$1969_Y
+ connect \Y $and$ls180.v:6251$1919_Y
end
- attribute \src "ls180.v:6248.37-6248.144"
- cell $and $and$ls180.v:6248$1971
+ attribute \src "ls180.v:6251.39-6251.146"
+ cell $and $and$ls180.v:6251$1921
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6248$1969_Y
- connect \B $eq$ls180.v:6248$1970_Y
- connect \Y $and$ls180.v:6248$1971_Y
+ connect \A $and$ls180.v:6251$1919_Y
+ connect \B $eq$ls180.v:6251$1920_Y
+ connect \Y $and$ls180.v:6251$1921_Y
end
- attribute \src "ls180.v:6249.38-6249.96"
- cell $and $and$ls180.v:6249$1973
+ attribute \src "ls180.v:6252.40-6252.98"
+ cell $and $and$ls180.v:6252$1923
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6249$1972_Y
- connect \Y $and$ls180.v:6249$1973_Y
+ connect \B $not$ls180.v:6252$1922_Y
+ connect \Y $and$ls180.v:6252$1923_Y
end
- attribute \src "ls180.v:6249.37-6249.147"
- cell $and $and$ls180.v:6249$1975
+ attribute \src "ls180.v:6252.39-6252.149"
+ cell $and $and$ls180.v:6252$1925
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6249$1973_Y
- connect \B $eq$ls180.v:6249$1974_Y
- connect \Y $and$ls180.v:6249$1975_Y
+ connect \A $and$ls180.v:6252$1923_Y
+ connect \B $eq$ls180.v:6252$1924_Y
+ connect \Y $and$ls180.v:6252$1925_Y
end
- attribute \src "ls180.v:6251.37-6251.92"
- cell $and $and$ls180.v:6251$1976
+ attribute \src "ls180.v:6254.39-6254.94"
+ cell $and $and$ls180.v:6254$1926
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6251$1976_Y
+ connect \Y $and$ls180.v:6254$1926_Y
end
- attribute \src "ls180.v:6251.36-6251.143"
- cell $and $and$ls180.v:6251$1978
+ attribute \src "ls180.v:6254.38-6254.145"
+ cell $and $and$ls180.v:6254$1928
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6251$1976_Y
- connect \B $eq$ls180.v:6251$1977_Y
- connect \Y $and$ls180.v:6251$1978_Y
+ connect \A $and$ls180.v:6254$1926_Y
+ connect \B $eq$ls180.v:6254$1927_Y
+ connect \Y $and$ls180.v:6254$1928_Y
end
- attribute \src "ls180.v:6252.37-6252.95"
- cell $and $and$ls180.v:6252$1980
+ attribute \src "ls180.v:6255.39-6255.97"
+ cell $and $and$ls180.v:6255$1930
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6252$1979_Y
- connect \Y $and$ls180.v:6252$1980_Y
+ connect \B $not$ls180.v:6255$1929_Y
+ connect \Y $and$ls180.v:6255$1930_Y
end
- attribute \src "ls180.v:6252.36-6252.146"
- cell $and $and$ls180.v:6252$1982
+ attribute \src "ls180.v:6255.38-6255.148"
+ cell $and $and$ls180.v:6255$1932
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6252$1980_Y
- connect \B $eq$ls180.v:6252$1981_Y
- connect \Y $and$ls180.v:6252$1982_Y
+ connect \A $and$ls180.v:6255$1930_Y
+ connect \B $eq$ls180.v:6255$1931_Y
+ connect \Y $and$ls180.v:6255$1932_Y
end
- attribute \src "ls180.v:6254.43-6254.98"
- cell $and $and$ls180.v:6254$1983
+ attribute \src "ls180.v:6257.38-6257.93"
+ cell $and $and$ls180.v:6257$1933
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6254$1983_Y
+ connect \Y $and$ls180.v:6257$1933_Y
end
- attribute \src "ls180.v:6254.42-6254.149"
- cell $and $and$ls180.v:6254$1985
+ attribute \src "ls180.v:6257.37-6257.144"
+ cell $and $and$ls180.v:6257$1935
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6254$1983_Y
- connect \B $eq$ls180.v:6254$1984_Y
- connect \Y $and$ls180.v:6254$1985_Y
+ connect \A $and$ls180.v:6257$1933_Y
+ connect \B $eq$ls180.v:6257$1934_Y
+ connect \Y $and$ls180.v:6257$1935_Y
end
- attribute \src "ls180.v:6255.43-6255.101"
- cell $and $and$ls180.v:6255$1987
+ attribute \src "ls180.v:6258.38-6258.96"
+ cell $and $and$ls180.v:6258$1937
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6255$1986_Y
- connect \Y $and$ls180.v:6255$1987_Y
+ connect \B $not$ls180.v:6258$1936_Y
+ connect \Y $and$ls180.v:6258$1937_Y
end
- attribute \src "ls180.v:6255.42-6255.152"
- cell $and $and$ls180.v:6255$1989
+ attribute \src "ls180.v:6258.37-6258.147"
+ cell $and $and$ls180.v:6258$1939
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6255$1987_Y
- connect \B $eq$ls180.v:6255$1988_Y
- connect \Y $and$ls180.v:6255$1989_Y
+ connect \A $and$ls180.v:6258$1937_Y
+ connect \B $eq$ls180.v:6258$1938_Y
+ connect \Y $and$ls180.v:6258$1939_Y
end
- attribute \src "ls180.v:6257.46-6257.101"
- cell $and $and$ls180.v:6257$1990
+ attribute \src "ls180.v:6260.37-6260.92"
+ cell $and $and$ls180.v:6260$1940
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6257$1990_Y
+ connect \Y $and$ls180.v:6260$1940_Y
end
- attribute \src "ls180.v:6257.45-6257.152"
- cell $and $and$ls180.v:6257$1992
+ attribute \src "ls180.v:6260.36-6260.143"
+ cell $and $and$ls180.v:6260$1942
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6257$1990_Y
- connect \B $eq$ls180.v:6257$1991_Y
- connect \Y $and$ls180.v:6257$1992_Y
+ connect \A $and$ls180.v:6260$1940_Y
+ connect \B $eq$ls180.v:6260$1941_Y
+ connect \Y $and$ls180.v:6260$1942_Y
end
- attribute \src "ls180.v:6258.46-6258.104"
- cell $and $and$ls180.v:6258$1994
+ attribute \src "ls180.v:6261.37-6261.95"
+ cell $and $and$ls180.v:6261$1944
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6258$1993_Y
- connect \Y $and$ls180.v:6258$1994_Y
+ connect \B $not$ls180.v:6261$1943_Y
+ connect \Y $and$ls180.v:6261$1944_Y
end
- attribute \src "ls180.v:6258.45-6258.155"
- cell $and $and$ls180.v:6258$1996
+ attribute \src "ls180.v:6261.36-6261.146"
+ cell $and $and$ls180.v:6261$1946
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6258$1994_Y
- connect \B $eq$ls180.v:6258$1995_Y
- connect \Y $and$ls180.v:6258$1996_Y
+ connect \A $and$ls180.v:6261$1944_Y
+ connect \B $eq$ls180.v:6261$1945_Y
+ connect \Y $and$ls180.v:6261$1946_Y
end
- attribute \src "ls180.v:6260.46-6260.101"
- cell $and $and$ls180.v:6260$1997
+ attribute \src "ls180.v:6263.43-6263.98"
+ cell $and $and$ls180.v:6263$1947
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
connect \B \builder_interface10_bank_bus_we
- connect \Y $and$ls180.v:6260$1997_Y
+ connect \Y $and$ls180.v:6263$1947_Y
end
- attribute \src "ls180.v:6260.45-6260.152"
- cell $and $and$ls180.v:6260$1999
+ attribute \src "ls180.v:6263.42-6263.149"
+ cell $and $and$ls180.v:6263$1949
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6260$1997_Y
- connect \B $eq$ls180.v:6260$1998_Y
- connect \Y $and$ls180.v:6260$1999_Y
+ connect \A $and$ls180.v:6263$1947_Y
+ connect \B $eq$ls180.v:6263$1948_Y
+ connect \Y $and$ls180.v:6263$1949_Y
end
- attribute \src "ls180.v:6261.46-6261.104"
- cell $and $and$ls180.v:6261$2001
+ attribute \src "ls180.v:6264.43-6264.101"
+ cell $and $and$ls180.v:6264$1951
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank10_sel
- connect \B $not$ls180.v:6261$2000_Y
- connect \Y $and$ls180.v:6261$2001_Y
+ connect \B $not$ls180.v:6264$1950_Y
+ connect \Y $and$ls180.v:6264$1951_Y
end
- attribute \src "ls180.v:6261.45-6261.155"
- cell $and $and$ls180.v:6261$2003
+ attribute \src "ls180.v:6264.42-6264.152"
+ cell $and $and$ls180.v:6264$1953
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6261$2001_Y
- connect \B $eq$ls180.v:6261$2002_Y
- connect \Y $and$ls180.v:6261$2003_Y
+ connect \A $and$ls180.v:6264$1951_Y
+ connect \B $eq$ls180.v:6264$1952_Y
+ connect \Y $and$ls180.v:6264$1953_Y
end
- attribute \src "ls180.v:6284.39-6284.94"
- cell $and $and$ls180.v:6284$2006
+ attribute \src "ls180.v:6285.42-6285.97"
+ cell $and $and$ls180.v:6285$1956
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6284$2006_Y
+ connect \Y $and$ls180.v:6285$1956_Y
end
- attribute \src "ls180.v:6284.38-6284.145"
- cell $and $and$ls180.v:6284$2008
+ attribute \src "ls180.v:6285.41-6285.148"
+ cell $and $and$ls180.v:6285$1958
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6284$2006_Y
- connect \B $eq$ls180.v:6284$2007_Y
- connect \Y $and$ls180.v:6284$2008_Y
+ connect \A $and$ls180.v:6285$1956_Y
+ connect \B $eq$ls180.v:6285$1957_Y
+ connect \Y $and$ls180.v:6285$1958_Y
end
- attribute \src "ls180.v:6285.39-6285.97"
- cell $and $and$ls180.v:6285$2010
+ attribute \src "ls180.v:6286.42-6286.100"
+ cell $and $and$ls180.v:6286$1960
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6285$2009_Y
- connect \Y $and$ls180.v:6285$2010_Y
+ connect \B $not$ls180.v:6286$1959_Y
+ connect \Y $and$ls180.v:6286$1960_Y
end
- attribute \src "ls180.v:6285.38-6285.148"
- cell $and $and$ls180.v:6285$2012
+ attribute \src "ls180.v:6286.41-6286.151"
+ cell $and $and$ls180.v:6286$1962
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6285$2010_Y
- connect \B $eq$ls180.v:6285$2011_Y
- connect \Y $and$ls180.v:6285$2012_Y
+ connect \A $and$ls180.v:6286$1960_Y
+ connect \B $eq$ls180.v:6286$1961_Y
+ connect \Y $and$ls180.v:6286$1962_Y
end
- attribute \src "ls180.v:6287.39-6287.94"
- cell $and $and$ls180.v:6287$2013
+ attribute \src "ls180.v:6288.42-6288.97"
+ cell $and $and$ls180.v:6288$1963
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6287$2013_Y
+ connect \Y $and$ls180.v:6288$1963_Y
end
- attribute \src "ls180.v:6287.38-6287.145"
- cell $and $and$ls180.v:6287$2015
+ attribute \src "ls180.v:6288.41-6288.148"
+ cell $and $and$ls180.v:6288$1965
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6287$2013_Y
- connect \B $eq$ls180.v:6287$2014_Y
- connect \Y $and$ls180.v:6287$2015_Y
+ connect \A $and$ls180.v:6288$1963_Y
+ connect \B $eq$ls180.v:6288$1964_Y
+ connect \Y $and$ls180.v:6288$1965_Y
end
- attribute \src "ls180.v:6288.39-6288.97"
- cell $and $and$ls180.v:6288$2017
+ attribute \src "ls180.v:6289.42-6289.100"
+ cell $and $and$ls180.v:6289$1967
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6288$2016_Y
- connect \Y $and$ls180.v:6288$2017_Y
+ connect \B $not$ls180.v:6289$1966_Y
+ connect \Y $and$ls180.v:6289$1967_Y
end
- attribute \src "ls180.v:6288.38-6288.148"
- cell $and $and$ls180.v:6288$2019
+ attribute \src "ls180.v:6289.41-6289.151"
+ cell $and $and$ls180.v:6289$1969
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6288$2017_Y
- connect \B $eq$ls180.v:6288$2018_Y
- connect \Y $and$ls180.v:6288$2019_Y
+ connect \A $and$ls180.v:6289$1967_Y
+ connect \B $eq$ls180.v:6289$1968_Y
+ connect \Y $and$ls180.v:6289$1969_Y
end
- attribute \src "ls180.v:6290.39-6290.94"
- cell $and $and$ls180.v:6290$2020
+ attribute \src "ls180.v:6291.40-6291.95"
+ cell $and $and$ls180.v:6291$1970
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6290$2020_Y
+ connect \Y $and$ls180.v:6291$1970_Y
end
- attribute \src "ls180.v:6290.38-6290.145"
- cell $and $and$ls180.v:6290$2022
+ attribute \src "ls180.v:6291.39-6291.146"
+ cell $and $and$ls180.v:6291$1972
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6290$2020_Y
- connect \B $eq$ls180.v:6290$2021_Y
- connect \Y $and$ls180.v:6290$2022_Y
+ connect \A $and$ls180.v:6291$1970_Y
+ connect \B $eq$ls180.v:6291$1971_Y
+ connect \Y $and$ls180.v:6291$1972_Y
end
- attribute \src "ls180.v:6291.39-6291.97"
- cell $and $and$ls180.v:6291$2024
+ attribute \src "ls180.v:6292.40-6292.98"
+ cell $and $and$ls180.v:6292$1974
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6291$2023_Y
- connect \Y $and$ls180.v:6291$2024_Y
+ connect \B $not$ls180.v:6292$1973_Y
+ connect \Y $and$ls180.v:6292$1974_Y
end
- attribute \src "ls180.v:6291.38-6291.148"
- cell $and $and$ls180.v:6291$2026
+ attribute \src "ls180.v:6292.39-6292.149"
+ cell $and $and$ls180.v:6292$1976
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6291$2024_Y
- connect \B $eq$ls180.v:6291$2025_Y
- connect \Y $and$ls180.v:6291$2026_Y
+ connect \A $and$ls180.v:6292$1974_Y
+ connect \B $eq$ls180.v:6292$1975_Y
+ connect \Y $and$ls180.v:6292$1976_Y
end
- attribute \src "ls180.v:6293.39-6293.94"
- cell $and $and$ls180.v:6293$2027
+ attribute \src "ls180.v:6294.39-6294.94"
+ cell $and $and$ls180.v:6294$1977
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6293$2027_Y
+ connect \Y $and$ls180.v:6294$1977_Y
end
- attribute \src "ls180.v:6293.38-6293.145"
- cell $and $and$ls180.v:6293$2029
+ attribute \src "ls180.v:6294.38-6294.145"
+ cell $and $and$ls180.v:6294$1979
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6293$2027_Y
- connect \B $eq$ls180.v:6293$2028_Y
- connect \Y $and$ls180.v:6293$2029_Y
+ connect \A $and$ls180.v:6294$1977_Y
+ connect \B $eq$ls180.v:6294$1978_Y
+ connect \Y $and$ls180.v:6294$1979_Y
end
- attribute \src "ls180.v:6294.39-6294.97"
- cell $and $and$ls180.v:6294$2031
+ attribute \src "ls180.v:6295.39-6295.97"
+ cell $and $and$ls180.v:6295$1981
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6294$2030_Y
- connect \Y $and$ls180.v:6294$2031_Y
+ connect \B $not$ls180.v:6295$1980_Y
+ connect \Y $and$ls180.v:6295$1981_Y
end
- attribute \src "ls180.v:6294.38-6294.148"
- cell $and $and$ls180.v:6294$2033
+ attribute \src "ls180.v:6295.38-6295.148"
+ cell $and $and$ls180.v:6295$1983
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6294$2031_Y
- connect \B $eq$ls180.v:6294$2032_Y
- connect \Y $and$ls180.v:6294$2033_Y
+ connect \A $and$ls180.v:6295$1981_Y
+ connect \B $eq$ls180.v:6295$1982_Y
+ connect \Y $and$ls180.v:6295$1983_Y
end
- attribute \src "ls180.v:6296.41-6296.96"
- cell $and $and$ls180.v:6296$2034
+ attribute \src "ls180.v:6297.38-6297.93"
+ cell $and $and$ls180.v:6297$1984
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6296$2034_Y
+ connect \Y $and$ls180.v:6297$1984_Y
end
- attribute \src "ls180.v:6296.40-6296.147"
- cell $and $and$ls180.v:6296$2036
+ attribute \src "ls180.v:6297.37-6297.144"
+ cell $and $and$ls180.v:6297$1986
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6296$2034_Y
- connect \B $eq$ls180.v:6296$2035_Y
- connect \Y $and$ls180.v:6296$2036_Y
+ connect \A $and$ls180.v:6297$1984_Y
+ connect \B $eq$ls180.v:6297$1985_Y
+ connect \Y $and$ls180.v:6297$1986_Y
end
- attribute \src "ls180.v:6297.41-6297.99"
- cell $and $and$ls180.v:6297$2038
+ attribute \src "ls180.v:6298.38-6298.96"
+ cell $and $and$ls180.v:6298$1988
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6297$2037_Y
- connect \Y $and$ls180.v:6297$2038_Y
+ connect \B $not$ls180.v:6298$1987_Y
+ connect \Y $and$ls180.v:6298$1988_Y
end
- attribute \src "ls180.v:6297.40-6297.150"
- cell $and $and$ls180.v:6297$2040
+ attribute \src "ls180.v:6298.37-6298.147"
+ cell $and $and$ls180.v:6298$1990
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6297$2038_Y
- connect \B $eq$ls180.v:6297$2039_Y
- connect \Y $and$ls180.v:6297$2040_Y
+ connect \A $and$ls180.v:6298$1988_Y
+ connect \B $eq$ls180.v:6298$1989_Y
+ connect \Y $and$ls180.v:6298$1990_Y
end
- attribute \src "ls180.v:6299.41-6299.96"
- cell $and $and$ls180.v:6299$2041
+ attribute \src "ls180.v:6300.37-6300.92"
+ cell $and $and$ls180.v:6300$1991
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6299$2041_Y
+ connect \Y $and$ls180.v:6300$1991_Y
end
- attribute \src "ls180.v:6299.40-6299.147"
- cell $and $and$ls180.v:6299$2043
+ attribute \src "ls180.v:6300.36-6300.143"
+ cell $and $and$ls180.v:6300$1993
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6299$2041_Y
- connect \B $eq$ls180.v:6299$2042_Y
- connect \Y $and$ls180.v:6299$2043_Y
+ connect \A $and$ls180.v:6300$1991_Y
+ connect \B $eq$ls180.v:6300$1992_Y
+ connect \Y $and$ls180.v:6300$1993_Y
end
- attribute \src "ls180.v:6300.41-6300.99"
- cell $and $and$ls180.v:6300$2045
+ attribute \src "ls180.v:6301.37-6301.95"
+ cell $and $and$ls180.v:6301$1995
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6300$2044_Y
- connect \Y $and$ls180.v:6300$2045_Y
+ connect \B $not$ls180.v:6301$1994_Y
+ connect \Y $and$ls180.v:6301$1995_Y
end
- attribute \src "ls180.v:6300.40-6300.150"
- cell $and $and$ls180.v:6300$2047
+ attribute \src "ls180.v:6301.36-6301.146"
+ cell $and $and$ls180.v:6301$1997
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6300$2045_Y
- connect \B $eq$ls180.v:6300$2046_Y
- connect \Y $and$ls180.v:6300$2047_Y
+ connect \A $and$ls180.v:6301$1995_Y
+ connect \B $eq$ls180.v:6301$1996_Y
+ connect \Y $and$ls180.v:6301$1997_Y
end
- attribute \src "ls180.v:6302.41-6302.96"
- cell $and $and$ls180.v:6302$2048
+ attribute \src "ls180.v:6303.43-6303.98"
+ cell $and $and$ls180.v:6303$1998
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6302$2048_Y
+ connect \Y $and$ls180.v:6303$1998_Y
end
- attribute \src "ls180.v:6302.40-6302.147"
- cell $and $and$ls180.v:6302$2050
+ attribute \src "ls180.v:6303.42-6303.149"
+ cell $and $and$ls180.v:6303$2000
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6302$2048_Y
- connect \B $eq$ls180.v:6302$2049_Y
- connect \Y $and$ls180.v:6302$2050_Y
+ connect \A $and$ls180.v:6303$1998_Y
+ connect \B $eq$ls180.v:6303$1999_Y
+ connect \Y $and$ls180.v:6303$2000_Y
end
- attribute \src "ls180.v:6303.41-6303.99"
- cell $and $and$ls180.v:6303$2052
+ attribute \src "ls180.v:6304.43-6304.101"
+ cell $and $and$ls180.v:6304$2002
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6303$2051_Y
- connect \Y $and$ls180.v:6303$2052_Y
+ connect \B $not$ls180.v:6304$2001_Y
+ connect \Y $and$ls180.v:6304$2002_Y
end
- attribute \src "ls180.v:6303.40-6303.150"
- cell $and $and$ls180.v:6303$2054
+ attribute \src "ls180.v:6304.42-6304.152"
+ cell $and $and$ls180.v:6304$2004
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6303$2052_Y
- connect \B $eq$ls180.v:6303$2053_Y
- connect \Y $and$ls180.v:6303$2054_Y
+ connect \A $and$ls180.v:6304$2002_Y
+ connect \B $eq$ls180.v:6304$2003_Y
+ connect \Y $and$ls180.v:6304$2004_Y
end
- attribute \src "ls180.v:6305.41-6305.96"
- cell $and $and$ls180.v:6305$2055
+ attribute \src "ls180.v:6306.46-6306.101"
+ cell $and $and$ls180.v:6306$2005
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6305$2055_Y
+ connect \Y $and$ls180.v:6306$2005_Y
end
- attribute \src "ls180.v:6305.40-6305.147"
- cell $and $and$ls180.v:6305$2057
+ attribute \src "ls180.v:6306.45-6306.152"
+ cell $and $and$ls180.v:6306$2007
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6305$2055_Y
- connect \B $eq$ls180.v:6305$2056_Y
- connect \Y $and$ls180.v:6305$2057_Y
+ connect \A $and$ls180.v:6306$2005_Y
+ connect \B $eq$ls180.v:6306$2006_Y
+ connect \Y $and$ls180.v:6306$2007_Y
end
- attribute \src "ls180.v:6306.41-6306.99"
- cell $and $and$ls180.v:6306$2059
+ attribute \src "ls180.v:6307.46-6307.104"
+ cell $and $and$ls180.v:6307$2009
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6306$2058_Y
- connect \Y $and$ls180.v:6306$2059_Y
+ connect \B $not$ls180.v:6307$2008_Y
+ connect \Y $and$ls180.v:6307$2009_Y
end
- attribute \src "ls180.v:6306.40-6306.150"
- cell $and $and$ls180.v:6306$2061
+ attribute \src "ls180.v:6307.45-6307.155"
+ cell $and $and$ls180.v:6307$2011
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6306$2059_Y
- connect \B $eq$ls180.v:6306$2060_Y
- connect \Y $and$ls180.v:6306$2061_Y
+ connect \A $and$ls180.v:6307$2009_Y
+ connect \B $eq$ls180.v:6307$2010_Y
+ connect \Y $and$ls180.v:6307$2011_Y
end
- attribute \src "ls180.v:6308.37-6308.92"
- cell $and $and$ls180.v:6308$2062
+ attribute \src "ls180.v:6309.46-6309.101"
+ cell $and $and$ls180.v:6309$2012
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6308$2062_Y
+ connect \Y $and$ls180.v:6309$2012_Y
end
- attribute \src "ls180.v:6308.36-6308.143"
- cell $and $and$ls180.v:6308$2064
+ attribute \src "ls180.v:6309.45-6309.152"
+ cell $and $and$ls180.v:6309$2014
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6308$2062_Y
- connect \B $eq$ls180.v:6308$2063_Y
- connect \Y $and$ls180.v:6308$2064_Y
+ connect \A $and$ls180.v:6309$2012_Y
+ connect \B $eq$ls180.v:6309$2013_Y
+ connect \Y $and$ls180.v:6309$2014_Y
end
- attribute \src "ls180.v:6309.37-6309.95"
- cell $and $and$ls180.v:6309$2066
+ attribute \src "ls180.v:6310.46-6310.104"
+ cell $and $and$ls180.v:6310$2016
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6309$2065_Y
- connect \Y $and$ls180.v:6309$2066_Y
+ connect \B $not$ls180.v:6310$2015_Y
+ connect \Y $and$ls180.v:6310$2016_Y
end
- attribute \src "ls180.v:6309.36-6309.146"
- cell $and $and$ls180.v:6309$2068
+ attribute \src "ls180.v:6310.45-6310.155"
+ cell $and $and$ls180.v:6310$2018
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6309$2066_Y
- connect \B $eq$ls180.v:6309$2067_Y
- connect \Y $and$ls180.v:6309$2068_Y
+ connect \A $and$ls180.v:6310$2016_Y
+ connect \B $eq$ls180.v:6310$2017_Y
+ connect \Y $and$ls180.v:6310$2018_Y
end
- attribute \src "ls180.v:6311.47-6311.102"
- cell $and $and$ls180.v:6311$2069
+ attribute \src "ls180.v:6333.39-6333.94"
+ cell $and $and$ls180.v:6333$2021
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6311$2069_Y
+ connect \A \builder_csrbank12_sel
+ connect \B \builder_interface12_bank_bus_we
+ connect \Y $and$ls180.v:6333$2021_Y
end
- attribute \src "ls180.v:6311.46-6311.153"
- cell $and $and$ls180.v:6311$2071
+ attribute \src "ls180.v:6333.38-6333.145"
+ cell $and $and$ls180.v:6333$2023
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6311$2069_Y
- connect \B $eq$ls180.v:6311$2070_Y
- connect \Y $and$ls180.v:6311$2071_Y
+ connect \A $and$ls180.v:6333$2021_Y
+ connect \B $eq$ls180.v:6333$2022_Y
+ connect \Y $and$ls180.v:6333$2023_Y
end
- attribute \src "ls180.v:6312.47-6312.105"
- cell $and $and$ls180.v:6312$2073
+ attribute \src "ls180.v:6334.39-6334.97"
+ cell $and $and$ls180.v:6334$2025
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6312$2072_Y
- connect \Y $and$ls180.v:6312$2073_Y
+ connect \A \builder_csrbank12_sel
+ connect \B $not$ls180.v:6334$2024_Y
+ connect \Y $and$ls180.v:6334$2025_Y
end
- attribute \src "ls180.v:6312.46-6312.156"
- cell $and $and$ls180.v:6312$2075
+ attribute \src "ls180.v:6334.38-6334.148"
+ cell $and $and$ls180.v:6334$2027
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6312$2073_Y
- connect \B $eq$ls180.v:6312$2074_Y
- connect \Y $and$ls180.v:6312$2075_Y
+ connect \A $and$ls180.v:6334$2025_Y
+ connect \B $eq$ls180.v:6334$2026_Y
+ connect \Y $and$ls180.v:6334$2027_Y
end
- attribute \src "ls180.v:6314.40-6314.95"
- cell $and $and$ls180.v:6314$2076
+ attribute \src "ls180.v:6336.39-6336.94"
+ cell $and $and$ls180.v:6336$2028
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6314$2076_Y
+ connect \A \builder_csrbank12_sel
+ connect \B \builder_interface12_bank_bus_we
+ connect \Y $and$ls180.v:6336$2028_Y
end
- attribute \src "ls180.v:6314.39-6314.147"
- cell $and $and$ls180.v:6314$2078
+ attribute \src "ls180.v:6336.38-6336.145"
+ cell $and $and$ls180.v:6336$2030
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6314$2076_Y
- connect \B $eq$ls180.v:6314$2077_Y
- connect \Y $and$ls180.v:6314$2078_Y
+ connect \A $and$ls180.v:6336$2028_Y
+ connect \B $eq$ls180.v:6336$2029_Y
+ connect \Y $and$ls180.v:6336$2030_Y
end
- attribute \src "ls180.v:6315.40-6315.98"
- cell $and $and$ls180.v:6315$2080
+ attribute \src "ls180.v:6337.39-6337.97"
+ cell $and $and$ls180.v:6337$2032
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6315$2079_Y
- connect \Y $and$ls180.v:6315$2080_Y
+ connect \A \builder_csrbank12_sel
+ connect \B $not$ls180.v:6337$2031_Y
+ connect \Y $and$ls180.v:6337$2032_Y
end
- attribute \src "ls180.v:6315.39-6315.150"
- cell $and $and$ls180.v:6315$2082
+ attribute \src "ls180.v:6337.38-6337.148"
+ cell $and $and$ls180.v:6337$2034
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6315$2080_Y
- connect \B $eq$ls180.v:6315$2081_Y
- connect \Y $and$ls180.v:6315$2082_Y
+ connect \A $and$ls180.v:6337$2032_Y
+ connect \B $eq$ls180.v:6337$2033_Y
+ connect \Y $and$ls180.v:6337$2034_Y
end
- attribute \src "ls180.v:6317.40-6317.95"
- cell $and $and$ls180.v:6317$2083
+ attribute \src "ls180.v:6339.39-6339.94"
+ cell $and $and$ls180.v:6339$2035
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6317$2083_Y
+ connect \A \builder_csrbank12_sel
+ connect \B \builder_interface12_bank_bus_we
+ connect \Y $and$ls180.v:6339$2035_Y
end
- attribute \src "ls180.v:6317.39-6317.147"
- cell $and $and$ls180.v:6317$2085
+ attribute \src "ls180.v:6339.38-6339.145"
+ cell $and $and$ls180.v:6339$2037
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6317$2083_Y
- connect \B $eq$ls180.v:6317$2084_Y
- connect \Y $and$ls180.v:6317$2085_Y
+ connect \A $and$ls180.v:6339$2035_Y
+ connect \B $eq$ls180.v:6339$2036_Y
+ connect \Y $and$ls180.v:6339$2037_Y
end
- attribute \src "ls180.v:6318.40-6318.98"
- cell $and $and$ls180.v:6318$2087
+ attribute \src "ls180.v:6340.39-6340.97"
+ cell $and $and$ls180.v:6340$2039
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6318$2086_Y
- connect \Y $and$ls180.v:6318$2087_Y
+ connect \A \builder_csrbank12_sel
+ connect \B $not$ls180.v:6340$2038_Y
+ connect \Y $and$ls180.v:6340$2039_Y
end
- attribute \src "ls180.v:6318.39-6318.150"
- cell $and $and$ls180.v:6318$2089
+ attribute \src "ls180.v:6340.38-6340.148"
+ cell $and $and$ls180.v:6340$2041
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6318$2087_Y
- connect \B $eq$ls180.v:6318$2088_Y
- connect \Y $and$ls180.v:6318$2089_Y
+ connect \A $and$ls180.v:6340$2039_Y
+ connect \B $eq$ls180.v:6340$2040_Y
+ connect \Y $and$ls180.v:6340$2041_Y
end
- attribute \src "ls180.v:6320.40-6320.95"
- cell $and $and$ls180.v:6320$2090
+ attribute \src "ls180.v:6342.39-6342.94"
+ cell $and $and$ls180.v:6342$2042
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6320$2090_Y
+ connect \A \builder_csrbank12_sel
+ connect \B \builder_interface12_bank_bus_we
+ connect \Y $and$ls180.v:6342$2042_Y
end
- attribute \src "ls180.v:6320.39-6320.147"
- cell $and $and$ls180.v:6320$2092
+ attribute \src "ls180.v:6342.38-6342.145"
+ cell $and $and$ls180.v:6342$2044
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6320$2090_Y
- connect \B $eq$ls180.v:6320$2091_Y
- connect \Y $and$ls180.v:6320$2092_Y
+ connect \A $and$ls180.v:6342$2042_Y
+ connect \B $eq$ls180.v:6342$2043_Y
+ connect \Y $and$ls180.v:6342$2044_Y
end
- attribute \src "ls180.v:6321.40-6321.98"
- cell $and $and$ls180.v:6321$2094
+ attribute \src "ls180.v:6343.39-6343.97"
+ cell $and $and$ls180.v:6343$2046
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6321$2093_Y
- connect \Y $and$ls180.v:6321$2094_Y
+ connect \A \builder_csrbank12_sel
+ connect \B $not$ls180.v:6343$2045_Y
+ connect \Y $and$ls180.v:6343$2046_Y
end
- attribute \src "ls180.v:6321.39-6321.150"
- cell $and $and$ls180.v:6321$2096
+ attribute \src "ls180.v:6343.38-6343.148"
+ cell $and $and$ls180.v:6343$2048
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6321$2094_Y
- connect \B $eq$ls180.v:6321$2095_Y
- connect \Y $and$ls180.v:6321$2096_Y
+ connect \A $and$ls180.v:6343$2046_Y
+ connect \B $eq$ls180.v:6343$2047_Y
+ connect \Y $and$ls180.v:6343$2048_Y
end
- attribute \src "ls180.v:6323.40-6323.95"
- cell $and $and$ls180.v:6323$2097
+ attribute \src "ls180.v:6345.41-6345.96"
+ cell $and $and$ls180.v:6345$2049
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6323$2097_Y
+ connect \A \builder_csrbank12_sel
+ connect \B \builder_interface12_bank_bus_we
+ connect \Y $and$ls180.v:6345$2049_Y
end
- attribute \src "ls180.v:6323.39-6323.147"
- cell $and $and$ls180.v:6323$2099
+ attribute \src "ls180.v:6345.40-6345.147"
+ cell $and $and$ls180.v:6345$2051
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6323$2097_Y
- connect \B $eq$ls180.v:6323$2098_Y
- connect \Y $and$ls180.v:6323$2099_Y
+ connect \A $and$ls180.v:6345$2049_Y
+ connect \B $eq$ls180.v:6345$2050_Y
+ connect \Y $and$ls180.v:6345$2051_Y
end
- attribute \src "ls180.v:6324.40-6324.98"
- cell $and $and$ls180.v:6324$2101
+ attribute \src "ls180.v:6346.41-6346.99"
+ cell $and $and$ls180.v:6346$2053
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6324$2100_Y
- connect \Y $and$ls180.v:6324$2101_Y
+ connect \A \builder_csrbank12_sel
+ connect \B $not$ls180.v:6346$2052_Y
+ connect \Y $and$ls180.v:6346$2053_Y
end
- attribute \src "ls180.v:6324.39-6324.150"
- cell $and $and$ls180.v:6324$2103
+ attribute \src "ls180.v:6346.40-6346.150"
+ cell $and $and$ls180.v:6346$2055
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6324$2101_Y
- connect \B $eq$ls180.v:6324$2102_Y
- connect \Y $and$ls180.v:6324$2103_Y
+ connect \A $and$ls180.v:6346$2053_Y
+ connect \B $eq$ls180.v:6346$2054_Y
+ connect \Y $and$ls180.v:6346$2055_Y
end
- attribute \src "ls180.v:6326.52-6326.107"
- cell $and $and$ls180.v:6326$2104
+ attribute \src "ls180.v:6348.41-6348.96"
+ cell $and $and$ls180.v:6348$2056
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6326$2104_Y
+ connect \A \builder_csrbank12_sel
+ connect \B \builder_interface12_bank_bus_we
+ connect \Y $and$ls180.v:6348$2056_Y
end
- attribute \src "ls180.v:6326.51-6326.159"
- cell $and $and$ls180.v:6326$2106
+ attribute \src "ls180.v:6348.40-6348.147"
+ cell $and $and$ls180.v:6348$2058
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6326$2104_Y
- connect \B $eq$ls180.v:6326$2105_Y
- connect \Y $and$ls180.v:6326$2106_Y
+ connect \A $and$ls180.v:6348$2056_Y
+ connect \B $eq$ls180.v:6348$2057_Y
+ connect \Y $and$ls180.v:6348$2058_Y
end
- attribute \src "ls180.v:6327.52-6327.110"
- cell $and $and$ls180.v:6327$2108
+ attribute \src "ls180.v:6349.41-6349.99"
+ cell $and $and$ls180.v:6349$2060
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6327$2107_Y
- connect \Y $and$ls180.v:6327$2108_Y
+ connect \A \builder_csrbank12_sel
+ connect \B $not$ls180.v:6349$2059_Y
+ connect \Y $and$ls180.v:6349$2060_Y
end
- attribute \src "ls180.v:6327.51-6327.162"
- cell $and $and$ls180.v:6327$2110
+ attribute \src "ls180.v:6349.40-6349.150"
+ cell $and $and$ls180.v:6349$2062
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6327$2108_Y
- connect \B $eq$ls180.v:6327$2109_Y
- connect \Y $and$ls180.v:6327$2110_Y
+ connect \A $and$ls180.v:6349$2060_Y
+ connect \B $eq$ls180.v:6349$2061_Y
+ connect \Y $and$ls180.v:6349$2062_Y
end
- attribute \src "ls180.v:6329.53-6329.108"
- cell $and $and$ls180.v:6329$2111
+ attribute \src "ls180.v:6351.41-6351.96"
+ cell $and $and$ls180.v:6351$2063
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6329$2111_Y
+ connect \A \builder_csrbank12_sel
+ connect \B \builder_interface12_bank_bus_we
+ connect \Y $and$ls180.v:6351$2063_Y
end
- attribute \src "ls180.v:6329.52-6329.160"
- cell $and $and$ls180.v:6329$2113
+ attribute \src "ls180.v:6351.40-6351.147"
+ cell $and $and$ls180.v:6351$2065
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6329$2111_Y
- connect \B $eq$ls180.v:6329$2112_Y
- connect \Y $and$ls180.v:6329$2113_Y
+ connect \A $and$ls180.v:6351$2063_Y
+ connect \B $eq$ls180.v:6351$2064_Y
+ connect \Y $and$ls180.v:6351$2065_Y
end
- attribute \src "ls180.v:6330.53-6330.111"
- cell $and $and$ls180.v:6330$2115
+ attribute \src "ls180.v:6352.41-6352.99"
+ cell $and $and$ls180.v:6352$2067
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6330$2114_Y
- connect \Y $and$ls180.v:6330$2115_Y
+ connect \A \builder_csrbank12_sel
+ connect \B $not$ls180.v:6352$2066_Y
+ connect \Y $and$ls180.v:6352$2067_Y
end
- attribute \src "ls180.v:6330.52-6330.163"
- cell $and $and$ls180.v:6330$2117
+ attribute \src "ls180.v:6352.40-6352.150"
+ cell $and $and$ls180.v:6352$2069
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6330$2115_Y
- connect \B $eq$ls180.v:6330$2116_Y
- connect \Y $and$ls180.v:6330$2117_Y
+ connect \A $and$ls180.v:6352$2067_Y
+ connect \B $eq$ls180.v:6352$2068_Y
+ connect \Y $and$ls180.v:6352$2069_Y
end
- attribute \src "ls180.v:6332.44-6332.99"
- cell $and $and$ls180.v:6332$2118
+ attribute \src "ls180.v:6354.41-6354.96"
+ cell $and $and$ls180.v:6354$2070
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B \builder_interface11_bank_bus_we
- connect \Y $and$ls180.v:6332$2118_Y
+ connect \A \builder_csrbank12_sel
+ connect \B \builder_interface12_bank_bus_we
+ connect \Y $and$ls180.v:6354$2070_Y
end
- attribute \src "ls180.v:6332.43-6332.151"
- cell $and $and$ls180.v:6332$2120
+ attribute \src "ls180.v:6354.40-6354.147"
+ cell $and $and$ls180.v:6354$2072
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6332$2118_Y
- connect \B $eq$ls180.v:6332$2119_Y
- connect \Y $and$ls180.v:6332$2120_Y
+ connect \A $and$ls180.v:6354$2070_Y
+ connect \B $eq$ls180.v:6354$2071_Y
+ connect \Y $and$ls180.v:6354$2072_Y
end
- attribute \src "ls180.v:6333.44-6333.102"
- cell $and $and$ls180.v:6333$2122
+ attribute \src "ls180.v:6355.41-6355.99"
+ cell $and $and$ls180.v:6355$2074
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_csrbank11_sel
- connect \B $not$ls180.v:6333$2121_Y
- connect \Y $and$ls180.v:6333$2122_Y
+ connect \A \builder_csrbank12_sel
+ connect \B $not$ls180.v:6355$2073_Y
+ connect \Y $and$ls180.v:6355$2074_Y
end
- attribute \src "ls180.v:6333.43-6333.154"
- cell $and $and$ls180.v:6333$2124
+ attribute \src "ls180.v:6355.40-6355.150"
+ cell $and $and$ls180.v:6355$2076
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6333$2122_Y
- connect \B $eq$ls180.v:6333$2123_Y
- connect \Y $and$ls180.v:6333$2124_Y
+ connect \A $and$ls180.v:6355$2074_Y
+ connect \B $eq$ls180.v:6355$2075_Y
+ connect \Y $and$ls180.v:6355$2076_Y
end
- attribute \src "ls180.v:6352.30-6352.85"
- cell $and $and$ls180.v:6352$2126
+ attribute \src "ls180.v:6357.37-6357.92"
+ cell $and $and$ls180.v:6357$2077
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6352$2126_Y
+ connect \Y $and$ls180.v:6357$2077_Y
end
- attribute \src "ls180.v:6352.29-6352.136"
- cell $and $and$ls180.v:6352$2128
+ attribute \src "ls180.v:6357.36-6357.143"
+ cell $and $and$ls180.v:6357$2079
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6352$2126_Y
- connect \B $eq$ls180.v:6352$2127_Y
- connect \Y $and$ls180.v:6352$2128_Y
+ connect \A $and$ls180.v:6357$2077_Y
+ connect \B $eq$ls180.v:6357$2078_Y
+ connect \Y $and$ls180.v:6357$2079_Y
end
- attribute \src "ls180.v:6353.30-6353.88"
- cell $and $and$ls180.v:6353$2130
+ attribute \src "ls180.v:6358.37-6358.95"
+ cell $and $and$ls180.v:6358$2081
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6353$2129_Y
- connect \Y $and$ls180.v:6353$2130_Y
+ connect \B $not$ls180.v:6358$2080_Y
+ connect \Y $and$ls180.v:6358$2081_Y
end
- attribute \src "ls180.v:6353.29-6353.139"
- cell $and $and$ls180.v:6353$2132
+ attribute \src "ls180.v:6358.36-6358.146"
+ cell $and $and$ls180.v:6358$2083
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6353$2130_Y
- connect \B $eq$ls180.v:6353$2131_Y
- connect \Y $and$ls180.v:6353$2132_Y
+ connect \A $and$ls180.v:6358$2081_Y
+ connect \B $eq$ls180.v:6358$2082_Y
+ connect \Y $and$ls180.v:6358$2083_Y
end
- attribute \src "ls180.v:6355.40-6355.95"
- cell $and $and$ls180.v:6355$2133
+ attribute \src "ls180.v:6360.47-6360.102"
+ cell $and $and$ls180.v:6360$2084
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6355$2133_Y
+ connect \Y $and$ls180.v:6360$2084_Y
end
- attribute \src "ls180.v:6355.39-6355.146"
- cell $and $and$ls180.v:6355$2135
+ attribute \src "ls180.v:6360.46-6360.153"
+ cell $and $and$ls180.v:6360$2086
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6355$2133_Y
- connect \B $eq$ls180.v:6355$2134_Y
- connect \Y $and$ls180.v:6355$2135_Y
+ connect \A $and$ls180.v:6360$2084_Y
+ connect \B $eq$ls180.v:6360$2085_Y
+ connect \Y $and$ls180.v:6360$2086_Y
end
- attribute \src "ls180.v:6356.40-6356.98"
- cell $and $and$ls180.v:6356$2137
+ attribute \src "ls180.v:6361.47-6361.105"
+ cell $and $and$ls180.v:6361$2088
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6356$2136_Y
- connect \Y $and$ls180.v:6356$2137_Y
+ connect \B $not$ls180.v:6361$2087_Y
+ connect \Y $and$ls180.v:6361$2088_Y
end
- attribute \src "ls180.v:6356.39-6356.149"
- cell $and $and$ls180.v:6356$2139
+ attribute \src "ls180.v:6361.46-6361.156"
+ cell $and $and$ls180.v:6361$2090
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6356$2137_Y
- connect \B $eq$ls180.v:6356$2138_Y
- connect \Y $and$ls180.v:6356$2139_Y
+ connect \A $and$ls180.v:6361$2088_Y
+ connect \B $eq$ls180.v:6361$2089_Y
+ connect \Y $and$ls180.v:6361$2090_Y
end
- attribute \src "ls180.v:6358.41-6358.96"
- cell $and $and$ls180.v:6358$2140
+ attribute \src "ls180.v:6363.40-6363.95"
+ cell $and $and$ls180.v:6363$2091
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6358$2140_Y
+ connect \Y $and$ls180.v:6363$2091_Y
end
- attribute \src "ls180.v:6358.40-6358.147"
- cell $and $and$ls180.v:6358$2142
+ attribute \src "ls180.v:6363.39-6363.147"
+ cell $and $and$ls180.v:6363$2093
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6358$2140_Y
- connect \B $eq$ls180.v:6358$2141_Y
- connect \Y $and$ls180.v:6358$2142_Y
+ connect \A $and$ls180.v:6363$2091_Y
+ connect \B $eq$ls180.v:6363$2092_Y
+ connect \Y $and$ls180.v:6363$2093_Y
end
- attribute \src "ls180.v:6359.41-6359.99"
- cell $and $and$ls180.v:6359$2144
+ attribute \src "ls180.v:6364.40-6364.98"
+ cell $and $and$ls180.v:6364$2095
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6359$2143_Y
- connect \Y $and$ls180.v:6359$2144_Y
+ connect \B $not$ls180.v:6364$2094_Y
+ connect \Y $and$ls180.v:6364$2095_Y
end
- attribute \src "ls180.v:6359.40-6359.150"
- cell $and $and$ls180.v:6359$2146
+ attribute \src "ls180.v:6364.39-6364.150"
+ cell $and $and$ls180.v:6364$2097
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6359$2144_Y
- connect \B $eq$ls180.v:6359$2145_Y
- connect \Y $and$ls180.v:6359$2146_Y
+ connect \A $and$ls180.v:6364$2095_Y
+ connect \B $eq$ls180.v:6364$2096_Y
+ connect \Y $and$ls180.v:6364$2097_Y
end
- attribute \src "ls180.v:6361.45-6361.100"
- cell $and $and$ls180.v:6361$2147
+ attribute \src "ls180.v:6366.40-6366.95"
+ cell $and $and$ls180.v:6366$2098
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6361$2147_Y
+ connect \Y $and$ls180.v:6366$2098_Y
end
- attribute \src "ls180.v:6361.44-6361.151"
- cell $and $and$ls180.v:6361$2149
+ attribute \src "ls180.v:6366.39-6366.147"
+ cell $and $and$ls180.v:6366$2100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6361$2147_Y
- connect \B $eq$ls180.v:6361$2148_Y
- connect \Y $and$ls180.v:6361$2149_Y
+ connect \A $and$ls180.v:6366$2098_Y
+ connect \B $eq$ls180.v:6366$2099_Y
+ connect \Y $and$ls180.v:6366$2100_Y
end
- attribute \src "ls180.v:6362.45-6362.103"
- cell $and $and$ls180.v:6362$2151
+ attribute \src "ls180.v:6367.40-6367.98"
+ cell $and $and$ls180.v:6367$2102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6362$2150_Y
- connect \Y $and$ls180.v:6362$2151_Y
+ connect \B $not$ls180.v:6367$2101_Y
+ connect \Y $and$ls180.v:6367$2102_Y
end
- attribute \src "ls180.v:6362.44-6362.154"
- cell $and $and$ls180.v:6362$2153
+ attribute \src "ls180.v:6367.39-6367.150"
+ cell $and $and$ls180.v:6367$2104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6362$2151_Y
- connect \B $eq$ls180.v:6362$2152_Y
- connect \Y $and$ls180.v:6362$2153_Y
+ connect \A $and$ls180.v:6367$2102_Y
+ connect \B $eq$ls180.v:6367$2103_Y
+ connect \Y $and$ls180.v:6367$2104_Y
end
- attribute \src "ls180.v:6364.46-6364.101"
- cell $and $and$ls180.v:6364$2154
+ attribute \src "ls180.v:6369.40-6369.95"
+ cell $and $and$ls180.v:6369$2105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6364$2154_Y
+ connect \Y $and$ls180.v:6369$2105_Y
end
- attribute \src "ls180.v:6364.45-6364.152"
- cell $and $and$ls180.v:6364$2156
+ attribute \src "ls180.v:6369.39-6369.147"
+ cell $and $and$ls180.v:6369$2107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6364$2154_Y
- connect \B $eq$ls180.v:6364$2155_Y
- connect \Y $and$ls180.v:6364$2156_Y
+ connect \A $and$ls180.v:6369$2105_Y
+ connect \B $eq$ls180.v:6369$2106_Y
+ connect \Y $and$ls180.v:6369$2107_Y
end
- attribute \src "ls180.v:6365.46-6365.104"
- cell $and $and$ls180.v:6365$2158
+ attribute \src "ls180.v:6370.40-6370.98"
+ cell $and $and$ls180.v:6370$2109
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6365$2157_Y
- connect \Y $and$ls180.v:6365$2158_Y
+ connect \B $not$ls180.v:6370$2108_Y
+ connect \Y $and$ls180.v:6370$2109_Y
end
- attribute \src "ls180.v:6365.45-6365.155"
- cell $and $and$ls180.v:6365$2160
+ attribute \src "ls180.v:6370.39-6370.150"
+ cell $and $and$ls180.v:6370$2111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6365$2158_Y
- connect \B $eq$ls180.v:6365$2159_Y
- connect \Y $and$ls180.v:6365$2160_Y
+ connect \A $and$ls180.v:6370$2109_Y
+ connect \B $eq$ls180.v:6370$2110_Y
+ connect \Y $and$ls180.v:6370$2111_Y
end
- attribute \src "ls180.v:6367.44-6367.99"
- cell $and $and$ls180.v:6367$2161
+ attribute \src "ls180.v:6372.40-6372.95"
+ cell $and $and$ls180.v:6372$2112
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6367$2161_Y
+ connect \Y $and$ls180.v:6372$2112_Y
end
- attribute \src "ls180.v:6367.43-6367.150"
- cell $and $and$ls180.v:6367$2163
+ attribute \src "ls180.v:6372.39-6372.147"
+ cell $and $and$ls180.v:6372$2114
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6367$2161_Y
- connect \B $eq$ls180.v:6367$2162_Y
- connect \Y $and$ls180.v:6367$2163_Y
+ connect \A $and$ls180.v:6372$2112_Y
+ connect \B $eq$ls180.v:6372$2113_Y
+ connect \Y $and$ls180.v:6372$2114_Y
end
- attribute \src "ls180.v:6368.44-6368.102"
- cell $and $and$ls180.v:6368$2165
+ attribute \src "ls180.v:6373.40-6373.98"
+ cell $and $and$ls180.v:6373$2116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6368$2164_Y
- connect \Y $and$ls180.v:6368$2165_Y
+ connect \B $not$ls180.v:6373$2115_Y
+ connect \Y $and$ls180.v:6373$2116_Y
end
- attribute \src "ls180.v:6368.43-6368.153"
- cell $and $and$ls180.v:6368$2167
+ attribute \src "ls180.v:6373.39-6373.150"
+ cell $and $and$ls180.v:6373$2118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6368$2165_Y
- connect \B $eq$ls180.v:6368$2166_Y
- connect \Y $and$ls180.v:6368$2167_Y
+ connect \A $and$ls180.v:6373$2116_Y
+ connect \B $eq$ls180.v:6373$2117_Y
+ connect \Y $and$ls180.v:6373$2118_Y
end
- attribute \src "ls180.v:6370.41-6370.96"
- cell $and $and$ls180.v:6370$2168
+ attribute \src "ls180.v:6375.52-6375.107"
+ cell $and $and$ls180.v:6375$2119
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6370$2168_Y
+ connect \Y $and$ls180.v:6375$2119_Y
end
- attribute \src "ls180.v:6370.40-6370.147"
- cell $and $and$ls180.v:6370$2170
+ attribute \src "ls180.v:6375.51-6375.159"
+ cell $and $and$ls180.v:6375$2121
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6370$2168_Y
- connect \B $eq$ls180.v:6370$2169_Y
- connect \Y $and$ls180.v:6370$2170_Y
+ connect \A $and$ls180.v:6375$2119_Y
+ connect \B $eq$ls180.v:6375$2120_Y
+ connect \Y $and$ls180.v:6375$2121_Y
end
- attribute \src "ls180.v:6371.41-6371.99"
- cell $and $and$ls180.v:6371$2172
+ attribute \src "ls180.v:6376.52-6376.110"
+ cell $and $and$ls180.v:6376$2123
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6371$2171_Y
- connect \Y $and$ls180.v:6371$2172_Y
+ connect \B $not$ls180.v:6376$2122_Y
+ connect \Y $and$ls180.v:6376$2123_Y
end
- attribute \src "ls180.v:6371.40-6371.150"
- cell $and $and$ls180.v:6371$2174
+ attribute \src "ls180.v:6376.51-6376.162"
+ cell $and $and$ls180.v:6376$2125
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6371$2172_Y
- connect \B $eq$ls180.v:6371$2173_Y
- connect \Y $and$ls180.v:6371$2174_Y
+ connect \A $and$ls180.v:6376$2123_Y
+ connect \B $eq$ls180.v:6376$2124_Y
+ connect \Y $and$ls180.v:6376$2125_Y
end
- attribute \src "ls180.v:6373.40-6373.95"
- cell $and $and$ls180.v:6373$2175
+ attribute \src "ls180.v:6378.53-6378.108"
+ cell $and $and$ls180.v:6378$2126
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
connect \B \builder_interface12_bank_bus_we
- connect \Y $and$ls180.v:6373$2175_Y
+ connect \Y $and$ls180.v:6378$2126_Y
end
- attribute \src "ls180.v:6373.39-6373.146"
- cell $and $and$ls180.v:6373$2177
+ attribute \src "ls180.v:6378.52-6378.160"
+ cell $and $and$ls180.v:6378$2128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6373$2175_Y
- connect \B $eq$ls180.v:6373$2176_Y
- connect \Y $and$ls180.v:6373$2177_Y
+ connect \A $and$ls180.v:6378$2126_Y
+ connect \B $eq$ls180.v:6378$2127_Y
+ connect \Y $and$ls180.v:6378$2128_Y
end
- attribute \src "ls180.v:6374.40-6374.98"
- cell $and $and$ls180.v:6374$2179
+ attribute \src "ls180.v:6379.53-6379.111"
+ cell $and $and$ls180.v:6379$2130
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank12_sel
- connect \B $not$ls180.v:6374$2178_Y
- connect \Y $and$ls180.v:6374$2179_Y
+ connect \B $not$ls180.v:6379$2129_Y
+ connect \Y $and$ls180.v:6379$2130_Y
end
- attribute \src "ls180.v:6374.39-6374.149"
- cell $and $and$ls180.v:6374$2181
+ attribute \src "ls180.v:6379.52-6379.163"
+ cell $and $and$ls180.v:6379$2132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6374$2179_Y
- connect \B $eq$ls180.v:6374$2180_Y
- connect \Y $and$ls180.v:6374$2181_Y
+ connect \A $and$ls180.v:6379$2130_Y
+ connect \B $eq$ls180.v:6379$2131_Y
+ connect \Y $and$ls180.v:6379$2132_Y
end
- attribute \src "ls180.v:6386.46-6386.101"
- cell $and $and$ls180.v:6386$2183
+ attribute \src "ls180.v:6381.44-6381.99"
+ cell $and $and$ls180.v:6381$2133
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank12_sel
+ connect \B \builder_interface12_bank_bus_we
+ connect \Y $and$ls180.v:6381$2133_Y
+ end
+ attribute \src "ls180.v:6381.43-6381.151"
+ cell $and $and$ls180.v:6381$2135
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6381$2133_Y
+ connect \B $eq$ls180.v:6381$2134_Y
+ connect \Y $and$ls180.v:6381$2135_Y
+ end
+ attribute \src "ls180.v:6382.44-6382.102"
+ cell $and $and$ls180.v:6382$2137
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank12_sel
+ connect \B $not$ls180.v:6382$2136_Y
+ connect \Y $and$ls180.v:6382$2137_Y
+ end
+ attribute \src "ls180.v:6382.43-6382.154"
+ cell $and $and$ls180.v:6382$2139
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6382$2137_Y
+ connect \B $eq$ls180.v:6382$2138_Y
+ connect \Y $and$ls180.v:6382$2139_Y
+ end
+ attribute \src "ls180.v:6401.30-6401.85"
+ cell $and $and$ls180.v:6401$2141
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
connect \B \builder_interface13_bank_bus_we
- connect \Y $and$ls180.v:6386$2183_Y
+ connect \Y $and$ls180.v:6401$2141_Y
end
- attribute \src "ls180.v:6386.45-6386.152"
- cell $and $and$ls180.v:6386$2185
+ attribute \src "ls180.v:6401.29-6401.136"
+ cell $and $and$ls180.v:6401$2143
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6386$2183_Y
- connect \B $eq$ls180.v:6386$2184_Y
- connect \Y $and$ls180.v:6386$2185_Y
+ connect \A $and$ls180.v:6401$2141_Y
+ connect \B $eq$ls180.v:6401$2142_Y
+ connect \Y $and$ls180.v:6401$2143_Y
end
- attribute \src "ls180.v:6387.46-6387.104"
- cell $and $and$ls180.v:6387$2187
+ attribute \src "ls180.v:6402.30-6402.88"
+ cell $and $and$ls180.v:6402$2145
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
- connect \B $not$ls180.v:6387$2186_Y
- connect \Y $and$ls180.v:6387$2187_Y
+ connect \B $not$ls180.v:6402$2144_Y
+ connect \Y $and$ls180.v:6402$2145_Y
end
- attribute \src "ls180.v:6387.45-6387.155"
- cell $and $and$ls180.v:6387$2189
+ attribute \src "ls180.v:6402.29-6402.139"
+ cell $and $and$ls180.v:6402$2147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6387$2187_Y
- connect \B $eq$ls180.v:6387$2188_Y
- connect \Y $and$ls180.v:6387$2189_Y
+ connect \A $and$ls180.v:6402$2145_Y
+ connect \B $eq$ls180.v:6402$2146_Y
+ connect \Y $and$ls180.v:6402$2147_Y
end
- attribute \src "ls180.v:6389.46-6389.101"
- cell $and $and$ls180.v:6389$2190
+ attribute \src "ls180.v:6404.40-6404.95"
+ cell $and $and$ls180.v:6404$2148
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
connect \B \builder_interface13_bank_bus_we
- connect \Y $and$ls180.v:6389$2190_Y
+ connect \Y $and$ls180.v:6404$2148_Y
end
- attribute \src "ls180.v:6389.45-6389.152"
- cell $and $and$ls180.v:6389$2192
+ attribute \src "ls180.v:6404.39-6404.146"
+ cell $and $and$ls180.v:6404$2150
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6389$2190_Y
- connect \B $eq$ls180.v:6389$2191_Y
- connect \Y $and$ls180.v:6389$2192_Y
+ connect \A $and$ls180.v:6404$2148_Y
+ connect \B $eq$ls180.v:6404$2149_Y
+ connect \Y $and$ls180.v:6404$2150_Y
end
- attribute \src "ls180.v:6390.46-6390.104"
- cell $and $and$ls180.v:6390$2194
+ attribute \src "ls180.v:6405.40-6405.98"
+ cell $and $and$ls180.v:6405$2152
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
- connect \B $not$ls180.v:6390$2193_Y
- connect \Y $and$ls180.v:6390$2194_Y
+ connect \B $not$ls180.v:6405$2151_Y
+ connect \Y $and$ls180.v:6405$2152_Y
end
- attribute \src "ls180.v:6390.45-6390.155"
- cell $and $and$ls180.v:6390$2196
+ attribute \src "ls180.v:6405.39-6405.149"
+ cell $and $and$ls180.v:6405$2154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6390$2194_Y
- connect \B $eq$ls180.v:6390$2195_Y
- connect \Y $and$ls180.v:6390$2196_Y
+ connect \A $and$ls180.v:6405$2152_Y
+ connect \B $eq$ls180.v:6405$2153_Y
+ connect \Y $and$ls180.v:6405$2154_Y
end
- attribute \src "ls180.v:6392.46-6392.101"
- cell $and $and$ls180.v:6392$2197
+ attribute \src "ls180.v:6407.41-6407.96"
+ cell $and $and$ls180.v:6407$2155
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
connect \B \builder_interface13_bank_bus_we
- connect \Y $and$ls180.v:6392$2197_Y
+ connect \Y $and$ls180.v:6407$2155_Y
end
- attribute \src "ls180.v:6392.45-6392.152"
- cell $and $and$ls180.v:6392$2199
+ attribute \src "ls180.v:6407.40-6407.147"
+ cell $and $and$ls180.v:6407$2157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6392$2197_Y
- connect \B $eq$ls180.v:6392$2198_Y
- connect \Y $and$ls180.v:6392$2199_Y
+ connect \A $and$ls180.v:6407$2155_Y
+ connect \B $eq$ls180.v:6407$2156_Y
+ connect \Y $and$ls180.v:6407$2157_Y
end
- attribute \src "ls180.v:6393.46-6393.104"
- cell $and $and$ls180.v:6393$2201
+ attribute \src "ls180.v:6408.41-6408.99"
+ cell $and $and$ls180.v:6408$2159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
- connect \B $not$ls180.v:6393$2200_Y
- connect \Y $and$ls180.v:6393$2201_Y
+ connect \B $not$ls180.v:6408$2158_Y
+ connect \Y $and$ls180.v:6408$2159_Y
end
- attribute \src "ls180.v:6393.45-6393.155"
- cell $and $and$ls180.v:6393$2203
+ attribute \src "ls180.v:6408.40-6408.150"
+ cell $and $and$ls180.v:6408$2161
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6393$2201_Y
- connect \B $eq$ls180.v:6393$2202_Y
- connect \Y $and$ls180.v:6393$2203_Y
+ connect \A $and$ls180.v:6408$2159_Y
+ connect \B $eq$ls180.v:6408$2160_Y
+ connect \Y $and$ls180.v:6408$2161_Y
end
- attribute \src "ls180.v:6395.46-6395.101"
- cell $and $and$ls180.v:6395$2204
+ attribute \src "ls180.v:6410.45-6410.100"
+ cell $and $and$ls180.v:6410$2162
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
connect \B \builder_interface13_bank_bus_we
- connect \Y $and$ls180.v:6395$2204_Y
+ connect \Y $and$ls180.v:6410$2162_Y
end
- attribute \src "ls180.v:6395.45-6395.152"
- cell $and $and$ls180.v:6395$2206
+ attribute \src "ls180.v:6410.44-6410.151"
+ cell $and $and$ls180.v:6410$2164
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6395$2204_Y
- connect \B $eq$ls180.v:6395$2205_Y
- connect \Y $and$ls180.v:6395$2206_Y
+ connect \A $and$ls180.v:6410$2162_Y
+ connect \B $eq$ls180.v:6410$2163_Y
+ connect \Y $and$ls180.v:6410$2164_Y
end
- attribute \src "ls180.v:6396.46-6396.104"
- cell $and $and$ls180.v:6396$2208
+ attribute \src "ls180.v:6411.45-6411.103"
+ cell $and $and$ls180.v:6411$2166
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_csrbank13_sel
- connect \B $not$ls180.v:6396$2207_Y
- connect \Y $and$ls180.v:6396$2208_Y
+ connect \B $not$ls180.v:6411$2165_Y
+ connect \Y $and$ls180.v:6411$2166_Y
end
- attribute \src "ls180.v:6396.45-6396.155"
- cell $and $and$ls180.v:6396$2210
+ attribute \src "ls180.v:6411.44-6411.154"
+ cell $and $and$ls180.v:6411$2168
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6396$2208_Y
- connect \B $eq$ls180.v:6396$2209_Y
- connect \Y $and$ls180.v:6396$2210_Y
+ connect \A $and$ls180.v:6411$2166_Y
+ connect \B $eq$ls180.v:6411$2167_Y
+ connect \Y $and$ls180.v:6411$2168_Y
end
- attribute \src "ls180.v:6774.109-6774.178"
- cell $and $and$ls180.v:6774$2247
+ attribute \src "ls180.v:6413.46-6413.101"
+ cell $and $and$ls180.v:6413$2169
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:6774$2246_Y
- connect \Y $and$ls180.v:6774$2247_Y
+ connect \A \builder_csrbank13_sel
+ connect \B \builder_interface13_bank_bus_we
+ connect \Y $and$ls180.v:6413$2169_Y
end
- attribute \src "ls180.v:6774.184-6774.253"
- cell $and $and$ls180.v:6774$2250
+ attribute \src "ls180.v:6413.45-6413.152"
+ cell $and $and$ls180.v:6413$2171
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:6774$2249_Y
- connect \Y $and$ls180.v:6774$2250_Y
+ connect \A $and$ls180.v:6413$2169_Y
+ connect \B $eq$ls180.v:6413$2170_Y
+ connect \Y $and$ls180.v:6413$2171_Y
end
- attribute \src "ls180.v:6774.259-6774.328"
- cell $and $and$ls180.v:6774$2253
+ attribute \src "ls180.v:6414.46-6414.104"
+ cell $and $and$ls180.v:6414$2173
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:6774$2252_Y
- connect \Y $and$ls180.v:6774$2253_Y
+ connect \A \builder_csrbank13_sel
+ connect \B $not$ls180.v:6414$2172_Y
+ connect \Y $and$ls180.v:6414$2173_Y
end
- attribute \src "ls180.v:6774.40-6774.331"
- cell $and $and$ls180.v:6774$2256
+ attribute \src "ls180.v:6414.45-6414.155"
+ cell $and $and$ls180.v:6414$2175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:6774$2245_Y
- connect \B $not$ls180.v:6774$2255_Y
- connect \Y $and$ls180.v:6774$2256_Y
+ connect \A $and$ls180.v:6414$2173_Y
+ connect \B $eq$ls180.v:6414$2174_Y
+ connect \Y $and$ls180.v:6414$2175_Y
end
- attribute \src "ls180.v:6774.39-6774.354"
- cell $and $and$ls180.v:6774$2257
+ attribute \src "ls180.v:6416.44-6416.99"
+ cell $and $and$ls180.v:6416$2176
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6774$2256_Y
- connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:6774$2257_Y
+ connect \A \builder_csrbank13_sel
+ connect \B \builder_interface13_bank_bus_we
+ connect \Y $and$ls180.v:6416$2176_Y
end
- attribute \src "ls180.v:6798.109-6798.178"
- cell $and $and$ls180.v:6798$2263
+ attribute \src "ls180.v:6416.43-6416.150"
+ cell $and $and$ls180.v:6416$2178
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:6798$2262_Y
- connect \Y $and$ls180.v:6798$2263_Y
+ connect \A $and$ls180.v:6416$2176_Y
+ connect \B $eq$ls180.v:6416$2177_Y
+ connect \Y $and$ls180.v:6416$2178_Y
+ end
+ attribute \src "ls180.v:6417.44-6417.102"
+ cell $and $and$ls180.v:6417$2180
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank13_sel
+ connect \B $not$ls180.v:6417$2179_Y
+ connect \Y $and$ls180.v:6417$2180_Y
+ end
+ attribute \src "ls180.v:6417.43-6417.153"
+ cell $and $and$ls180.v:6417$2182
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6417$2180_Y
+ connect \B $eq$ls180.v:6417$2181_Y
+ connect \Y $and$ls180.v:6417$2182_Y
+ end
+ attribute \src "ls180.v:6419.41-6419.96"
+ cell $and $and$ls180.v:6419$2183
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank13_sel
+ connect \B \builder_interface13_bank_bus_we
+ connect \Y $and$ls180.v:6419$2183_Y
+ end
+ attribute \src "ls180.v:6419.40-6419.147"
+ cell $and $and$ls180.v:6419$2185
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6419$2183_Y
+ connect \B $eq$ls180.v:6419$2184_Y
+ connect \Y $and$ls180.v:6419$2185_Y
+ end
+ attribute \src "ls180.v:6420.41-6420.99"
+ cell $and $and$ls180.v:6420$2187
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank13_sel
+ connect \B $not$ls180.v:6420$2186_Y
+ connect \Y $and$ls180.v:6420$2187_Y
+ end
+ attribute \src "ls180.v:6420.40-6420.150"
+ cell $and $and$ls180.v:6420$2189
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6420$2187_Y
+ connect \B $eq$ls180.v:6420$2188_Y
+ connect \Y $and$ls180.v:6420$2189_Y
+ end
+ attribute \src "ls180.v:6422.40-6422.95"
+ cell $and $and$ls180.v:6422$2190
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank13_sel
+ connect \B \builder_interface13_bank_bus_we
+ connect \Y $and$ls180.v:6422$2190_Y
+ end
+ attribute \src "ls180.v:6422.39-6422.146"
+ cell $and $and$ls180.v:6422$2192
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6422$2190_Y
+ connect \B $eq$ls180.v:6422$2191_Y
+ connect \Y $and$ls180.v:6422$2192_Y
+ end
+ attribute \src "ls180.v:6423.40-6423.98"
+ cell $and $and$ls180.v:6423$2194
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank13_sel
+ connect \B $not$ls180.v:6423$2193_Y
+ connect \Y $and$ls180.v:6423$2194_Y
+ end
+ attribute \src "ls180.v:6423.39-6423.149"
+ cell $and $and$ls180.v:6423$2196
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6423$2194_Y
+ connect \B $eq$ls180.v:6423$2195_Y
+ connect \Y $and$ls180.v:6423$2196_Y
+ end
+ attribute \src "ls180.v:6435.46-6435.101"
+ cell $and $and$ls180.v:6435$2198
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank14_sel
+ connect \B \builder_interface14_bank_bus_we
+ connect \Y $and$ls180.v:6435$2198_Y
+ end
+ attribute \src "ls180.v:6435.45-6435.152"
+ cell $and $and$ls180.v:6435$2200
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6435$2198_Y
+ connect \B $eq$ls180.v:6435$2199_Y
+ connect \Y $and$ls180.v:6435$2200_Y
+ end
+ attribute \src "ls180.v:6436.46-6436.104"
+ cell $and $and$ls180.v:6436$2202
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank14_sel
+ connect \B $not$ls180.v:6436$2201_Y
+ connect \Y $and$ls180.v:6436$2202_Y
+ end
+ attribute \src "ls180.v:6436.45-6436.155"
+ cell $and $and$ls180.v:6436$2204
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6436$2202_Y
+ connect \B $eq$ls180.v:6436$2203_Y
+ connect \Y $and$ls180.v:6436$2204_Y
+ end
+ attribute \src "ls180.v:6438.46-6438.101"
+ cell $and $and$ls180.v:6438$2205
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank14_sel
+ connect \B \builder_interface14_bank_bus_we
+ connect \Y $and$ls180.v:6438$2205_Y
+ end
+ attribute \src "ls180.v:6438.45-6438.152"
+ cell $and $and$ls180.v:6438$2207
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6438$2205_Y
+ connect \B $eq$ls180.v:6438$2206_Y
+ connect \Y $and$ls180.v:6438$2207_Y
+ end
+ attribute \src "ls180.v:6439.46-6439.104"
+ cell $and $and$ls180.v:6439$2209
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank14_sel
+ connect \B $not$ls180.v:6439$2208_Y
+ connect \Y $and$ls180.v:6439$2209_Y
+ end
+ attribute \src "ls180.v:6439.45-6439.155"
+ cell $and $and$ls180.v:6439$2211
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6439$2209_Y
+ connect \B $eq$ls180.v:6439$2210_Y
+ connect \Y $and$ls180.v:6439$2211_Y
+ end
+ attribute \src "ls180.v:6441.46-6441.101"
+ cell $and $and$ls180.v:6441$2212
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank14_sel
+ connect \B \builder_interface14_bank_bus_we
+ connect \Y $and$ls180.v:6441$2212_Y
+ end
+ attribute \src "ls180.v:6441.45-6441.152"
+ cell $and $and$ls180.v:6441$2214
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6441$2212_Y
+ connect \B $eq$ls180.v:6441$2213_Y
+ connect \Y $and$ls180.v:6441$2214_Y
+ end
+ attribute \src "ls180.v:6442.46-6442.104"
+ cell $and $and$ls180.v:6442$2216
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank14_sel
+ connect \B $not$ls180.v:6442$2215_Y
+ connect \Y $and$ls180.v:6442$2216_Y
+ end
+ attribute \src "ls180.v:6442.45-6442.155"
+ cell $and $and$ls180.v:6442$2218
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6442$2216_Y
+ connect \B $eq$ls180.v:6442$2217_Y
+ connect \Y $and$ls180.v:6442$2218_Y
+ end
+ attribute \src "ls180.v:6444.46-6444.101"
+ cell $and $and$ls180.v:6444$2219
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank14_sel
+ connect \B \builder_interface14_bank_bus_we
+ connect \Y $and$ls180.v:6444$2219_Y
+ end
+ attribute \src "ls180.v:6444.45-6444.152"
+ cell $and $and$ls180.v:6444$2221
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6444$2219_Y
+ connect \B $eq$ls180.v:6444$2220_Y
+ connect \Y $and$ls180.v:6444$2221_Y
+ end
+ attribute \src "ls180.v:6445.46-6445.104"
+ cell $and $and$ls180.v:6445$2223
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_csrbank14_sel
+ connect \B $not$ls180.v:6445$2222_Y
+ connect \Y $and$ls180.v:6445$2223_Y
+ end
+ attribute \src "ls180.v:6445.45-6445.155"
+ cell $and $and$ls180.v:6445$2225
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6445$2223_Y
+ connect \B $eq$ls180.v:6445$2224_Y
+ connect \Y $and$ls180.v:6445$2225_Y
+ end
+ attribute \src "ls180.v:6826.109-6826.178"
+ cell $and $and$ls180.v:6826$2263
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \main_sdram_interface_bank1_lock
+ connect \B $eq$ls180.v:6826$2262_Y
+ connect \Y $and$ls180.v:6826$2263_Y
end
- attribute \src "ls180.v:6798.184-6798.253"
- cell $and $and$ls180.v:6798$2266
+ attribute \src "ls180.v:6826.184-6826.253"
+ cell $and $and$ls180.v:6826$2266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:6798$2265_Y
- connect \Y $and$ls180.v:6798$2266_Y
+ connect \B $eq$ls180.v:6826$2265_Y
+ connect \Y $and$ls180.v:6826$2266_Y
end
- attribute \src "ls180.v:6798.259-6798.328"
- cell $and $and$ls180.v:6798$2269
+ attribute \src "ls180.v:6826.259-6826.328"
+ cell $and $and$ls180.v:6826$2269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:6798$2268_Y
- connect \Y $and$ls180.v:6798$2269_Y
+ connect \B $eq$ls180.v:6826$2268_Y
+ connect \Y $and$ls180.v:6826$2269_Y
end
- attribute \src "ls180.v:6798.40-6798.331"
- cell $and $and$ls180.v:6798$2272
+ attribute \src "ls180.v:6826.40-6826.331"
+ cell $and $and$ls180.v:6826$2272
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:6798$2261_Y
- connect \B $not$ls180.v:6798$2271_Y
- connect \Y $and$ls180.v:6798$2272_Y
+ connect \A $eq$ls180.v:6826$2261_Y
+ connect \B $not$ls180.v:6826$2271_Y
+ connect \Y $and$ls180.v:6826$2272_Y
end
- attribute \src "ls180.v:6798.39-6798.354"
- cell $and $and$ls180.v:6798$2273
+ attribute \src "ls180.v:6826.39-6826.354"
+ cell $and $and$ls180.v:6826$2273
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6798$2272_Y
+ connect \A $and$ls180.v:6826$2272_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:6798$2273_Y
+ connect \Y $and$ls180.v:6826$2273_Y
end
- attribute \src "ls180.v:6822.109-6822.178"
- cell $and $and$ls180.v:6822$2279
+ attribute \src "ls180.v:6850.109-6850.178"
+ cell $and $and$ls180.v:6850$2279
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:6822$2278_Y
- connect \Y $and$ls180.v:6822$2279_Y
+ connect \B $eq$ls180.v:6850$2278_Y
+ connect \Y $and$ls180.v:6850$2279_Y
end
- attribute \src "ls180.v:6822.184-6822.253"
- cell $and $and$ls180.v:6822$2282
+ attribute \src "ls180.v:6850.184-6850.253"
+ cell $and $and$ls180.v:6850$2282
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \main_sdram_interface_bank2_lock
+ connect \B $eq$ls180.v:6850$2281_Y
+ connect \Y $and$ls180.v:6850$2282_Y
+ end
+ attribute \src "ls180.v:6850.259-6850.328"
+ cell $and $and$ls180.v:6850$2285
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \main_sdram_interface_bank3_lock
+ connect \B $eq$ls180.v:6850$2284_Y
+ connect \Y $and$ls180.v:6850$2285_Y
+ end
+ attribute \src "ls180.v:6850.40-6850.331"
+ cell $and $and$ls180.v:6850$2288
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $eq$ls180.v:6850$2277_Y
+ connect \B $not$ls180.v:6850$2287_Y
+ connect \Y $and$ls180.v:6850$2288_Y
+ end
+ attribute \src "ls180.v:6850.39-6850.354"
+ cell $and $and$ls180.v:6850$2289
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $and$ls180.v:6850$2288_Y
+ connect \B \main_port_cmd_valid
+ connect \Y $and$ls180.v:6850$2289_Y
+ end
+ attribute \src "ls180.v:6874.109-6874.178"
+ cell $and $and$ls180.v:6874$2295
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \main_sdram_interface_bank0_lock
+ connect \B $eq$ls180.v:6874$2294_Y
+ connect \Y $and$ls180.v:6874$2295_Y
+ end
+ attribute \src "ls180.v:6874.184-6874.253"
+ cell $and $and$ls180.v:6874$2298
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:6822$2281_Y
- connect \Y $and$ls180.v:6822$2282_Y
+ connect \B $eq$ls180.v:6874$2297_Y
+ connect \Y $and$ls180.v:6874$2298_Y
end
- attribute \src "ls180.v:6822.259-6822.328"
- cell $and $and$ls180.v:6822$2285
+ attribute \src "ls180.v:6874.259-6874.328"
+ cell $and $and$ls180.v:6874$2301
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \B $eq$ls180.v:6822$2284_Y
- connect \Y $and$ls180.v:6822$2285_Y
+ connect \B $eq$ls180.v:6874$2300_Y
+ connect \Y $and$ls180.v:6874$2301_Y
end
- attribute \src "ls180.v:6822.40-6822.331"
- cell $and $and$ls180.v:6822$2288
+ attribute \src "ls180.v:6874.40-6874.331"
+ cell $and $and$ls180.v:6874$2304
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:6822$2277_Y
- connect \B $not$ls180.v:6822$2287_Y
- connect \Y $and$ls180.v:6822$2288_Y
+ connect \A $eq$ls180.v:6874$2293_Y
+ connect \B $not$ls180.v:6874$2303_Y
+ connect \Y $and$ls180.v:6874$2304_Y
end
- attribute \src "ls180.v:6822.39-6822.354"
- cell $and $and$ls180.v:6822$2289
+ attribute \src "ls180.v:6874.39-6874.354"
+ cell $and $and$ls180.v:6874$2305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6822$2288_Y
+ connect \A $and$ls180.v:6874$2304_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:6822$2289_Y
+ connect \Y $and$ls180.v:6874$2305_Y
end
- attribute \src "ls180.v:6846.109-6846.178"
- cell $and $and$ls180.v:6846$2295
+ attribute \src "ls180.v:6898.109-6898.178"
+ cell $and $and$ls180.v:6898$2311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \B $eq$ls180.v:6846$2294_Y
- connect \Y $and$ls180.v:6846$2295_Y
+ connect \B $eq$ls180.v:6898$2310_Y
+ connect \Y $and$ls180.v:6898$2311_Y
end
- attribute \src "ls180.v:6846.184-6846.253"
- cell $and $and$ls180.v:6846$2298
+ attribute \src "ls180.v:6898.184-6898.253"
+ cell $and $and$ls180.v:6898$2314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \B $eq$ls180.v:6846$2297_Y
- connect \Y $and$ls180.v:6846$2298_Y
+ connect \B $eq$ls180.v:6898$2313_Y
+ connect \Y $and$ls180.v:6898$2314_Y
end
- attribute \src "ls180.v:6846.259-6846.328"
- cell $and $and$ls180.v:6846$2301
+ attribute \src "ls180.v:6898.259-6898.328"
+ cell $and $and$ls180.v:6898$2317
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \B $eq$ls180.v:6846$2300_Y
- connect \Y $and$ls180.v:6846$2301_Y
+ connect \B $eq$ls180.v:6898$2316_Y
+ connect \Y $and$ls180.v:6898$2317_Y
end
- attribute \src "ls180.v:6846.40-6846.331"
- cell $and $and$ls180.v:6846$2304
+ attribute \src "ls180.v:6898.40-6898.331"
+ cell $and $and$ls180.v:6898$2320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:6846$2293_Y
- connect \B $not$ls180.v:6846$2303_Y
- connect \Y $and$ls180.v:6846$2304_Y
+ connect \A $eq$ls180.v:6898$2309_Y
+ connect \B $not$ls180.v:6898$2319_Y
+ connect \Y $and$ls180.v:6898$2320_Y
end
- attribute \src "ls180.v:6846.39-6846.354"
- cell $and $and$ls180.v:6846$2305
+ attribute \src "ls180.v:6898.39-6898.354"
+ cell $and $and$ls180.v:6898$2321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:6846$2304_Y
+ connect \A $and$ls180.v:6898$2320_Y
connect \B \main_port_cmd_valid
- connect \Y $and$ls180.v:6846$2305_Y
+ connect \Y $and$ls180.v:6898$2321_Y
end
- attribute \src "ls180.v:7051.39-7051.104"
- cell $and $and$ls180.v:7051$2317
+ attribute \src "ls180.v:7103.39-7103.104"
+ cell $and $and$ls180.v:7103$2333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7051$2317_Y
+ connect \Y $and$ls180.v:7103$2333_Y
end
- attribute \src "ls180.v:7051.38-7051.145"
- cell $and $and$ls180.v:7051$2318
+ attribute \src "ls180.v:7103.38-7103.145"
+ cell $and $and$ls180.v:7103$2334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7051$2317_Y
+ connect \A $and$ls180.v:7103$2333_Y
connect \B \main_sdram_choose_req_cmd_payload_cas
- connect \Y $and$ls180.v:7051$2318_Y
+ connect \Y $and$ls180.v:7103$2334_Y
end
- attribute \src "ls180.v:7054.39-7054.104"
- cell $and $and$ls180.v:7054$2319
+ attribute \src "ls180.v:7106.39-7106.104"
+ cell $and $and$ls180.v:7106$2335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7054$2319_Y
+ connect \Y $and$ls180.v:7106$2335_Y
end
- attribute \src "ls180.v:7054.38-7054.145"
- cell $and $and$ls180.v:7054$2320
+ attribute \src "ls180.v:7106.38-7106.145"
+ cell $and $and$ls180.v:7106$2336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7054$2319_Y
+ connect \A $and$ls180.v:7106$2335_Y
connect \B \main_sdram_choose_req_cmd_payload_cas
- connect \Y $and$ls180.v:7054$2320_Y
+ connect \Y $and$ls180.v:7106$2336_Y
end
- attribute \src "ls180.v:7057.39-7057.82"
- cell $and $and$ls180.v:7057$2321
+ attribute \src "ls180.v:7109.39-7109.82"
+ cell $and $and$ls180.v:7109$2337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_cmd_valid
connect \B \main_sdram_cmd_ready
- connect \Y $and$ls180.v:7057$2321_Y
+ connect \Y $and$ls180.v:7109$2337_Y
end
- attribute \src "ls180.v:7057.38-7057.112"
- cell $and $and$ls180.v:7057$2322
+ attribute \src "ls180.v:7109.38-7109.112"
+ cell $and $and$ls180.v:7109$2338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7057$2321_Y
+ connect \A $and$ls180.v:7109$2337_Y
connect \B \main_sdram_cmd_payload_cas
- connect \Y $and$ls180.v:7057$2322_Y
+ connect \Y $and$ls180.v:7109$2338_Y
end
- attribute \src "ls180.v:7068.39-7068.104"
- cell $and $and$ls180.v:7068$2324
+ attribute \src "ls180.v:7120.39-7120.104"
+ cell $and $and$ls180.v:7120$2340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7068$2324_Y
+ connect \Y $and$ls180.v:7120$2340_Y
end
- attribute \src "ls180.v:7068.38-7068.145"
- cell $and $and$ls180.v:7068$2325
+ attribute \src "ls180.v:7120.38-7120.145"
+ cell $and $and$ls180.v:7120$2341
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7068$2324_Y
+ connect \A $and$ls180.v:7120$2340_Y
connect \B \main_sdram_choose_req_cmd_payload_ras
- connect \Y $and$ls180.v:7068$2325_Y
+ connect \Y $and$ls180.v:7120$2341_Y
end
- attribute \src "ls180.v:7071.39-7071.104"
- cell $and $and$ls180.v:7071$2326
+ attribute \src "ls180.v:7123.39-7123.104"
+ cell $and $and$ls180.v:7123$2342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7071$2326_Y
+ connect \Y $and$ls180.v:7123$2342_Y
end
- attribute \src "ls180.v:7071.38-7071.145"
- cell $and $and$ls180.v:7071$2327
+ attribute \src "ls180.v:7123.38-7123.145"
+ cell $and $and$ls180.v:7123$2343
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7071$2326_Y
+ connect \A $and$ls180.v:7123$2342_Y
connect \B \main_sdram_choose_req_cmd_payload_ras
- connect \Y $and$ls180.v:7071$2327_Y
+ connect \Y $and$ls180.v:7123$2343_Y
end
- attribute \src "ls180.v:7074.39-7074.82"
- cell $and $and$ls180.v:7074$2328
+ attribute \src "ls180.v:7126.39-7126.82"
+ cell $and $and$ls180.v:7126$2344
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_cmd_valid
connect \B \main_sdram_cmd_ready
- connect \Y $and$ls180.v:7074$2328_Y
+ connect \Y $and$ls180.v:7126$2344_Y
end
- attribute \src "ls180.v:7074.38-7074.112"
- cell $and $and$ls180.v:7074$2329
+ attribute \src "ls180.v:7126.38-7126.112"
+ cell $and $and$ls180.v:7126$2345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7074$2328_Y
+ connect \A $and$ls180.v:7126$2344_Y
connect \B \main_sdram_cmd_payload_ras
- connect \Y $and$ls180.v:7074$2329_Y
+ connect \Y $and$ls180.v:7126$2345_Y
end
- attribute \src "ls180.v:7085.39-7085.104"
- cell $and $and$ls180.v:7085$2331
+ attribute \src "ls180.v:7137.39-7137.104"
+ cell $and $and$ls180.v:7137$2347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7085$2331_Y
+ connect \Y $and$ls180.v:7137$2347_Y
end
- attribute \src "ls180.v:7085.38-7085.144"
- cell $and $and$ls180.v:7085$2332
+ attribute \src "ls180.v:7137.38-7137.144"
+ cell $and $and$ls180.v:7137$2348
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7085$2331_Y
+ connect \A $and$ls180.v:7137$2347_Y
connect \B \main_sdram_choose_req_cmd_payload_we
- connect \Y $and$ls180.v:7085$2332_Y
+ connect \Y $and$ls180.v:7137$2348_Y
end
- attribute \src "ls180.v:7088.39-7088.104"
- cell $and $and$ls180.v:7088$2333
+ attribute \src "ls180.v:7140.39-7140.104"
+ cell $and $and$ls180.v:7140$2349
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7088$2333_Y
+ connect \Y $and$ls180.v:7140$2349_Y
end
- attribute \src "ls180.v:7088.38-7088.144"
- cell $and $and$ls180.v:7088$2334
+ attribute \src "ls180.v:7140.38-7140.144"
+ cell $and $and$ls180.v:7140$2350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7088$2333_Y
+ connect \A $and$ls180.v:7140$2349_Y
connect \B \main_sdram_choose_req_cmd_payload_we
- connect \Y $and$ls180.v:7088$2334_Y
+ connect \Y $and$ls180.v:7140$2350_Y
end
- attribute \src "ls180.v:7091.39-7091.82"
- cell $and $and$ls180.v:7091$2335
+ attribute \src "ls180.v:7143.39-7143.82"
+ cell $and $and$ls180.v:7143$2351
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_cmd_valid
connect \B \main_sdram_cmd_ready
- connect \Y $and$ls180.v:7091$2335_Y
+ connect \Y $and$ls180.v:7143$2351_Y
end
- attribute \src "ls180.v:7091.38-7091.111"
- cell $and $and$ls180.v:7091$2336
+ attribute \src "ls180.v:7143.38-7143.111"
+ cell $and $and$ls180.v:7143$2352
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7091$2335_Y
+ connect \A $and$ls180.v:7143$2351_Y
connect \B \main_sdram_cmd_payload_we
- connect \Y $and$ls180.v:7091$2336_Y
+ connect \Y $and$ls180.v:7143$2352_Y
end
- attribute \src "ls180.v:7102.39-7102.104"
- cell $and $and$ls180.v:7102$2338
+ attribute \src "ls180.v:7154.39-7154.104"
+ cell $and $and$ls180.v:7154$2354
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7102$2338_Y
+ connect \Y $and$ls180.v:7154$2354_Y
end
- attribute \src "ls180.v:7102.38-7102.149"
- cell $and $and$ls180.v:7102$2339
+ attribute \src "ls180.v:7154.38-7154.149"
+ cell $and $and$ls180.v:7154$2355
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7102$2338_Y
+ connect \A $and$ls180.v:7154$2354_Y
connect \B \main_sdram_choose_req_cmd_payload_is_read
- connect \Y $and$ls180.v:7102$2339_Y
+ connect \Y $and$ls180.v:7154$2355_Y
end
- attribute \src "ls180.v:7105.39-7105.104"
- cell $and $and$ls180.v:7105$2340
+ attribute \src "ls180.v:7157.39-7157.104"
+ cell $and $and$ls180.v:7157$2356
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7105$2340_Y
+ connect \Y $and$ls180.v:7157$2356_Y
end
- attribute \src "ls180.v:7105.38-7105.149"
- cell $and $and$ls180.v:7105$2341
+ attribute \src "ls180.v:7157.38-7157.149"
+ cell $and $and$ls180.v:7157$2357
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7105$2340_Y
+ connect \A $and$ls180.v:7157$2356_Y
connect \B \main_sdram_choose_req_cmd_payload_is_read
- connect \Y $and$ls180.v:7105$2341_Y
+ connect \Y $and$ls180.v:7157$2357_Y
end
- attribute \src "ls180.v:7108.39-7108.82"
- cell $and $and$ls180.v:7108$2342
+ attribute \src "ls180.v:7160.39-7160.82"
+ cell $and $and$ls180.v:7160$2358
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_cmd_valid
connect \B \main_sdram_cmd_ready
- connect \Y $and$ls180.v:7108$2342_Y
+ connect \Y $and$ls180.v:7160$2358_Y
end
- attribute \src "ls180.v:7108.38-7108.116"
- cell $and $and$ls180.v:7108$2343
+ attribute \src "ls180.v:7160.38-7160.116"
+ cell $and $and$ls180.v:7160$2359
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7108$2342_Y
+ connect \A $and$ls180.v:7160$2358_Y
connect \B \main_sdram_cmd_payload_is_read
- connect \Y $and$ls180.v:7108$2343_Y
+ connect \Y $and$ls180.v:7160$2359_Y
end
- attribute \src "ls180.v:7119.39-7119.104"
- cell $and $and$ls180.v:7119$2345
+ attribute \src "ls180.v:7171.39-7171.104"
+ cell $and $and$ls180.v:7171$2361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7119$2345_Y
+ connect \Y $and$ls180.v:7171$2361_Y
end
- attribute \src "ls180.v:7119.38-7119.150"
- cell $and $and$ls180.v:7119$2346
+ attribute \src "ls180.v:7171.38-7171.150"
+ cell $and $and$ls180.v:7171$2362
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7119$2345_Y
+ connect \A $and$ls180.v:7171$2361_Y
connect \B \main_sdram_choose_req_cmd_payload_is_write
- connect \Y $and$ls180.v:7119$2346_Y
+ connect \Y $and$ls180.v:7171$2362_Y
end
- attribute \src "ls180.v:7122.39-7122.104"
- cell $and $and$ls180.v:7122$2347
+ attribute \src "ls180.v:7174.39-7174.104"
+ cell $and $and$ls180.v:7174$2363
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
connect \B \main_sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:7122$2347_Y
+ connect \Y $and$ls180.v:7174$2363_Y
end
- attribute \src "ls180.v:7122.38-7122.150"
- cell $and $and$ls180.v:7122$2348
+ attribute \src "ls180.v:7174.38-7174.150"
+ cell $and $and$ls180.v:7174$2364
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7122$2347_Y
+ connect \A $and$ls180.v:7174$2363_Y
connect \B \main_sdram_choose_req_cmd_payload_is_write
- connect \Y $and$ls180.v:7122$2348_Y
+ connect \Y $and$ls180.v:7174$2364_Y
end
- attribute \src "ls180.v:7125.39-7125.82"
- cell $and $and$ls180.v:7125$2349
+ attribute \src "ls180.v:7177.39-7177.82"
+ cell $and $and$ls180.v:7177$2365
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_cmd_valid
connect \B \main_sdram_cmd_ready
- connect \Y $and$ls180.v:7125$2349_Y
+ connect \Y $and$ls180.v:7177$2365_Y
end
- attribute \src "ls180.v:7125.38-7125.117"
- cell $and $and$ls180.v:7125$2350
+ attribute \src "ls180.v:7177.38-7177.117"
+ cell $and $and$ls180.v:7177$2366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7125$2349_Y
+ connect \A $and$ls180.v:7177$2365_Y
connect \B \main_sdram_cmd_payload_is_write
- connect \Y $and$ls180.v:7125$2350_Y
+ connect \Y $and$ls180.v:7177$2366_Y
end
- attribute \src "ls180.v:7344.17-7344.67"
- cell $and $and$ls180.v:7344$2357
+ attribute \src "ls180.v:7396.17-7396.67"
+ cell $and $and$ls180.v:7396$2373
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7344$2356_Y
+ connect \A $not$ls180.v:7396$2372_Y
connect \B \main_sdphy_sdpads_clk
- connect \Y $and$ls180.v:7344$2357_Y
+ connect \Y $and$ls180.v:7396$2373_Y
end
- attribute \src "ls180.v:7441.8-7441.67"
- cell $and $and$ls180.v:7441$2406
+ attribute \src "ls180.v:7487.8-7487.67"
+ cell $and $and$ls180.v:7487$2416
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_cyc
connect \B \main_libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:7441$2406_Y
+ connect \Y $and$ls180.v:7487$2416_Y
end
- attribute \src "ls180.v:7441.7-7441.102"
- cell $and $and$ls180.v:7441$2408
+ attribute \src "ls180.v:7487.7-7487.102"
+ cell $and $and$ls180.v:7487$2418
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7441$2406_Y
- connect \B $not$ls180.v:7441$2407_Y
- connect \Y $and$ls180.v:7441$2408_Y
+ connect \A $and$ls180.v:7487$2416_Y
+ connect \B $not$ls180.v:7487$2417_Y
+ connect \Y $and$ls180.v:7487$2418_Y
end
- attribute \src "ls180.v:7460.7-7460.75"
- cell $and $and$ls180.v:7460$2412
+ attribute \src "ls180.v:7506.7-7506.75"
+ cell $and $and$ls180.v:7506$2422
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7460$2411_Y
+ connect \A $not$ls180.v:7506$2421_Y
connect \B \main_libresocsim_zero_old_trigger
- connect \Y $and$ls180.v:7460$2412_Y
+ connect \Y $and$ls180.v:7506$2422_Y
end
- attribute \src "ls180.v:7468.7-7468.56"
- cell $and $and$ls180.v:7468$2414
+ attribute \src "ls180.v:7514.7-7514.56"
+ cell $and $and$ls180.v:7514$2424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_timer_wait
- connect \B $not$ls180.v:7468$2413_Y
- connect \Y $and$ls180.v:7468$2414_Y
+ connect \B $not$ls180.v:7514$2423_Y
+ connect \Y $and$ls180.v:7514$2424_Y
end
- attribute \src "ls180.v:7496.7-7496.75"
- cell $and $and$ls180.v:7496$2421
+ attribute \src "ls180.v:7542.7-7542.75"
+ cell $and $and$ls180.v:7542$2431
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_start1
- connect \B $eq$ls180.v:7496$2420_Y
- connect \Y $and$ls180.v:7496$2421_Y
+ connect \B $eq$ls180.v:7542$2430_Y
+ connect \Y $and$ls180.v:7542$2431_Y
end
- attribute \src "ls180.v:7538.8-7538.131"
- cell $and $and$ls180.v:7538$2427
+ attribute \src "ls180.v:7584.8-7584.131"
+ cell $and $and$ls180.v:7584$2437
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
- connect \Y $and$ls180.v:7538$2427_Y
+ connect \Y $and$ls180.v:7584$2437_Y
end
- attribute \src "ls180.v:7538.7-7538.190"
- cell $and $and$ls180.v:7538$2429
+ attribute \src "ls180.v:7584.7-7584.190"
+ cell $and $and$ls180.v:7584$2439
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7538$2427_Y
- connect \B $not$ls180.v:7538$2428_Y
- connect \Y $and$ls180.v:7538$2429_Y
+ connect \A $and$ls180.v:7584$2437_Y
+ connect \B $not$ls180.v:7584$2438_Y
+ connect \Y $and$ls180.v:7584$2439_Y
end
- attribute \src "ls180.v:7544.8-7544.131"
- cell $and $and$ls180.v:7544$2432
+ attribute \src "ls180.v:7590.8-7590.131"
+ cell $and $and$ls180.v:7590$2442
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
- connect \Y $and$ls180.v:7544$2432_Y
+ connect \Y $and$ls180.v:7590$2442_Y
end
- attribute \src "ls180.v:7544.7-7544.190"
- cell $and $and$ls180.v:7544$2434
+ attribute \src "ls180.v:7590.7-7590.190"
+ cell $and $and$ls180.v:7590$2444
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7544$2432_Y
- connect \B $not$ls180.v:7544$2433_Y
- connect \Y $and$ls180.v:7544$2434_Y
+ connect \A $and$ls180.v:7590$2442_Y
+ connect \B $not$ls180.v:7590$2443_Y
+ connect \Y $and$ls180.v:7590$2444_Y
end
- attribute \src "ls180.v:7584.8-7584.131"
- cell $and $and$ls180.v:7584$2443
+ attribute \src "ls180.v:7630.8-7630.131"
+ cell $and $and$ls180.v:7630$2453
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
- connect \Y $and$ls180.v:7584$2443_Y
+ connect \Y $and$ls180.v:7630$2453_Y
end
- attribute \src "ls180.v:7584.7-7584.190"
- cell $and $and$ls180.v:7584$2445
+ attribute \src "ls180.v:7630.7-7630.190"
+ cell $and $and$ls180.v:7630$2455
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7584$2443_Y
- connect \B $not$ls180.v:7584$2444_Y
- connect \Y $and$ls180.v:7584$2445_Y
+ connect \A $and$ls180.v:7630$2453_Y
+ connect \B $not$ls180.v:7630$2454_Y
+ connect \Y $and$ls180.v:7630$2455_Y
end
- attribute \src "ls180.v:7590.8-7590.131"
- cell $and $and$ls180.v:7590$2448
+ attribute \src "ls180.v:7636.8-7636.131"
+ cell $and $and$ls180.v:7636$2458
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
- connect \Y $and$ls180.v:7590$2448_Y
+ connect \Y $and$ls180.v:7636$2458_Y
end
- attribute \src "ls180.v:7590.7-7590.190"
- cell $and $and$ls180.v:7590$2450
+ attribute \src "ls180.v:7636.7-7636.190"
+ cell $and $and$ls180.v:7636$2460
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7590$2448_Y
- connect \B $not$ls180.v:7590$2449_Y
- connect \Y $and$ls180.v:7590$2450_Y
+ connect \A $and$ls180.v:7636$2458_Y
+ connect \B $not$ls180.v:7636$2459_Y
+ connect \Y $and$ls180.v:7636$2460_Y
end
- attribute \src "ls180.v:7630.8-7630.131"
- cell $and $and$ls180.v:7630$2459
+ attribute \src "ls180.v:7676.8-7676.131"
+ cell $and $and$ls180.v:7676$2469
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
- connect \Y $and$ls180.v:7630$2459_Y
+ connect \Y $and$ls180.v:7676$2469_Y
end
- attribute \src "ls180.v:7630.7-7630.190"
- cell $and $and$ls180.v:7630$2461
+ attribute \src "ls180.v:7676.7-7676.190"
+ cell $and $and$ls180.v:7676$2471
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7630$2459_Y
- connect \B $not$ls180.v:7630$2460_Y
- connect \Y $and$ls180.v:7630$2461_Y
+ connect \A $and$ls180.v:7676$2469_Y
+ connect \B $not$ls180.v:7676$2470_Y
+ connect \Y $and$ls180.v:7676$2471_Y
end
- attribute \src "ls180.v:7636.8-7636.131"
- cell $and $and$ls180.v:7636$2464
+ attribute \src "ls180.v:7682.8-7682.131"
+ cell $and $and$ls180.v:7682$2474
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
- connect \Y $and$ls180.v:7636$2464_Y
+ connect \Y $and$ls180.v:7682$2474_Y
end
- attribute \src "ls180.v:7636.7-7636.190"
- cell $and $and$ls180.v:7636$2466
+ attribute \src "ls180.v:7682.7-7682.190"
+ cell $and $and$ls180.v:7682$2476
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7636$2464_Y
- connect \B $not$ls180.v:7636$2465_Y
- connect \Y $and$ls180.v:7636$2466_Y
+ connect \A $and$ls180.v:7682$2474_Y
+ connect \B $not$ls180.v:7682$2475_Y
+ connect \Y $and$ls180.v:7682$2476_Y
end
- attribute \src "ls180.v:7676.8-7676.131"
- cell $and $and$ls180.v:7676$2475
+ attribute \src "ls180.v:7722.8-7722.131"
+ cell $and $and$ls180.v:7722$2485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
- connect \Y $and$ls180.v:7676$2475_Y
+ connect \Y $and$ls180.v:7722$2485_Y
end
- attribute \src "ls180.v:7676.7-7676.190"
- cell $and $and$ls180.v:7676$2477
+ attribute \src "ls180.v:7722.7-7722.190"
+ cell $and $and$ls180.v:7722$2487
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7676$2475_Y
- connect \B $not$ls180.v:7676$2476_Y
- connect \Y $and$ls180.v:7676$2477_Y
+ connect \A $and$ls180.v:7722$2485_Y
+ connect \B $not$ls180.v:7722$2486_Y
+ connect \Y $and$ls180.v:7722$2487_Y
end
- attribute \src "ls180.v:7682.8-7682.131"
- cell $and $and$ls180.v:7682$2480
+ attribute \src "ls180.v:7728.8-7728.131"
+ cell $and $and$ls180.v:7728$2490
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
- connect \Y $and$ls180.v:7682$2480_Y
+ connect \Y $and$ls180.v:7728$2490_Y
end
- attribute \src "ls180.v:7682.7-7682.190"
- cell $and $and$ls180.v:7682$2482
+ attribute \src "ls180.v:7728.7-7728.190"
+ cell $and $and$ls180.v:7728$2492
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7682$2480_Y
- connect \B $not$ls180.v:7682$2481_Y
- connect \Y $and$ls180.v:7682$2482_Y
+ connect \A $and$ls180.v:7728$2490_Y
+ connect \B $not$ls180.v:7728$2491_Y
+ connect \Y $and$ls180.v:7728$2492_Y
end
- attribute \src "ls180.v:7879.48-7879.124"
- cell $and $and$ls180.v:7879$2507
+ attribute \src "ls180.v:7925.48-7925.124"
+ cell $and $and$ls180.v:7925$2517
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7879$2506_Y
+ connect \A $eq$ls180.v:7925$2516_Y
connect \B \main_sdram_interface_bank0_wdata_ready
- connect \Y $and$ls180.v:7879$2507_Y
+ connect \Y $and$ls180.v:7925$2517_Y
end
- attribute \src "ls180.v:7879.130-7879.206"
- cell $and $and$ls180.v:7879$2510
+ attribute \src "ls180.v:7925.130-7925.206"
+ cell $and $and$ls180.v:7925$2520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7879$2509_Y
+ connect \A $eq$ls180.v:7925$2519_Y
connect \B \main_sdram_interface_bank1_wdata_ready
- connect \Y $and$ls180.v:7879$2510_Y
+ connect \Y $and$ls180.v:7925$2520_Y
end
- attribute \src "ls180.v:7879.212-7879.288"
- cell $and $and$ls180.v:7879$2513
+ attribute \src "ls180.v:7925.212-7925.288"
+ cell $and $and$ls180.v:7925$2523
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7879$2512_Y
+ connect \A $eq$ls180.v:7925$2522_Y
connect \B \main_sdram_interface_bank2_wdata_ready
- connect \Y $and$ls180.v:7879$2513_Y
+ connect \Y $and$ls180.v:7925$2523_Y
end
- attribute \src "ls180.v:7879.294-7879.370"
- cell $and $and$ls180.v:7879$2516
+ attribute \src "ls180.v:7925.294-7925.370"
+ cell $and $and$ls180.v:7925$2526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7879$2515_Y
+ connect \A $eq$ls180.v:7925$2525_Y
connect \B \main_sdram_interface_bank3_wdata_ready
- connect \Y $and$ls180.v:7879$2516_Y
+ connect \Y $and$ls180.v:7925$2526_Y
end
- attribute \src "ls180.v:7880.49-7880.125"
- cell $and $and$ls180.v:7880$2519
+ attribute \src "ls180.v:7926.49-7926.125"
+ cell $and $and$ls180.v:7926$2529
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7880$2518_Y
+ connect \A $eq$ls180.v:7926$2528_Y
connect \B \main_sdram_interface_bank0_rdata_valid
- connect \Y $and$ls180.v:7880$2519_Y
+ connect \Y $and$ls180.v:7926$2529_Y
end
- attribute \src "ls180.v:7880.131-7880.207"
- cell $and $and$ls180.v:7880$2522
+ attribute \src "ls180.v:7926.131-7926.207"
+ cell $and $and$ls180.v:7926$2532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7880$2521_Y
+ connect \A $eq$ls180.v:7926$2531_Y
connect \B \main_sdram_interface_bank1_rdata_valid
- connect \Y $and$ls180.v:7880$2522_Y
+ connect \Y $and$ls180.v:7926$2532_Y
end
- attribute \src "ls180.v:7880.213-7880.289"
- cell $and $and$ls180.v:7880$2525
+ attribute \src "ls180.v:7926.213-7926.289"
+ cell $and $and$ls180.v:7926$2535
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7880$2524_Y
+ connect \A $eq$ls180.v:7926$2534_Y
connect \B \main_sdram_interface_bank2_rdata_valid
- connect \Y $and$ls180.v:7880$2525_Y
+ connect \Y $and$ls180.v:7926$2535_Y
end
- attribute \src "ls180.v:7880.295-7880.371"
- cell $and $and$ls180.v:7880$2528
+ attribute \src "ls180.v:7926.295-7926.371"
+ cell $and $and$ls180.v:7926$2538
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:7880$2527_Y
+ connect \A $eq$ls180.v:7926$2537_Y
connect \B \main_sdram_interface_bank3_rdata_valid
- connect \Y $and$ls180.v:7880$2528_Y
+ connect \Y $and$ls180.v:7926$2538_Y
end
- attribute \src "ls180.v:7899.8-7899.49"
- cell $and $and$ls180.v:7899$2531
+ attribute \src "ls180.v:7945.8-7945.49"
+ cell $and $and$ls180.v:7945$2541
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_valid
connect \B \main_port_cmd_ready
- connect \Y $and$ls180.v:7899$2531_Y
+ connect \Y $and$ls180.v:7945$2541_Y
end
- attribute \src "ls180.v:7902.8-7902.53"
- cell $and $and$ls180.v:7902$2532
+ attribute \src "ls180.v:7948.8-7948.53"
+ cell $and $and$ls180.v:7948$2542
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_wdata_valid
connect \B \main_port_wdata_ready
- connect \Y $and$ls180.v:7902$2532_Y
+ connect \Y $and$ls180.v:7948$2542_Y
end
- attribute \src "ls180.v:7907.8-7907.41"
- cell $and $and$ls180.v:7907$2534
+ attribute \src "ls180.v:7953.8-7953.59"
+ cell $and $and$ls180.v:7953$2544
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_sink_valid
- connect \B $not$ls180.v:7907$2533_Y
- connect \Y $and$ls180.v:7907$2534_Y
+ connect \A \main_uart_phy_sink_valid
+ connect \B $not$ls180.v:7953$2543_Y
+ connect \Y $and$ls180.v:7953$2544_Y
end
- attribute \src "ls180.v:7907.7-7907.63"
- cell $and $and$ls180.v:7907$2536
+ attribute \src "ls180.v:7953.7-7953.90"
+ cell $and $and$ls180.v:7953$2546
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7907$2534_Y
- connect \B $not$ls180.v:7907$2535_Y
- connect \Y $and$ls180.v:7907$2536_Y
+ connect \A $and$ls180.v:7953$2544_Y
+ connect \B $not$ls180.v:7953$2545_Y
+ connect \Y $and$ls180.v:7953$2546_Y
end
- attribute \src "ls180.v:7913.8-7913.41"
- cell $and $and$ls180.v:7913$2537
+ attribute \src "ls180.v:7959.8-7959.59"
+ cell $and $and$ls180.v:7959$2547
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_uart_clk_txen
- connect \B \main_tx_busy
- connect \Y $and$ls180.v:7913$2537_Y
+ connect \A \main_uart_phy_uart_clk_txen
+ connect \B \main_uart_phy_tx_busy
+ connect \Y $and$ls180.v:7959$2547_Y
end
- attribute \src "ls180.v:7937.8-7937.30"
- cell $and $and$ls180.v:7937$2544
+ attribute \src "ls180.v:7983.8-7983.48"
+ cell $and $and$ls180.v:7983$2554
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7937$2543_Y
- connect \B \main_rx_r
- connect \Y $and$ls180.v:7937$2544_Y
+ connect \A $not$ls180.v:7983$2553_Y
+ connect \B \main_uart_phy_rx_r
+ connect \Y $and$ls180.v:7983$2554_Y
end
- attribute \src "ls180.v:7970.7-7970.57"
- cell $and $and$ls180.v:7970$2550
+ attribute \src "ls180.v:8016.7-8016.57"
+ cell $and $and$ls180.v:8016$2560
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7970$2549_Y
+ connect \A $not$ls180.v:8016$2559_Y
connect \B \main_uart_tx_old_trigger
- connect \Y $and$ls180.v:7970$2550_Y
+ connect \Y $and$ls180.v:8016$2560_Y
end
- attribute \src "ls180.v:7977.7-7977.57"
- cell $and $and$ls180.v:7977$2552
+ attribute \src "ls180.v:8023.7-8023.57"
+ cell $and $and$ls180.v:8023$2562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7977$2551_Y
+ connect \A $not$ls180.v:8023$2561_Y
connect \B \main_uart_rx_old_trigger
- connect \Y $and$ls180.v:7977$2552_Y
+ connect \Y $and$ls180.v:8023$2562_Y
end
- attribute \src "ls180.v:7987.8-7987.75"
- cell $and $and$ls180.v:7987$2553
+ attribute \src "ls180.v:8033.8-8033.75"
+ cell $and $and$ls180.v:8033$2563
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_syncfifo_we
connect \B \main_uart_tx_fifo_syncfifo_writable
- connect \Y $and$ls180.v:7987$2553_Y
+ connect \Y $and$ls180.v:8033$2563_Y
end
- attribute \src "ls180.v:7987.7-7987.107"
- cell $and $and$ls180.v:7987$2555
+ attribute \src "ls180.v:8033.7-8033.107"
+ cell $and $and$ls180.v:8033$2565
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7987$2553_Y
- connect \B $not$ls180.v:7987$2554_Y
- connect \Y $and$ls180.v:7987$2555_Y
+ connect \A $and$ls180.v:8033$2563_Y
+ connect \B $not$ls180.v:8033$2564_Y
+ connect \Y $and$ls180.v:8033$2565_Y
end
- attribute \src "ls180.v:7993.8-7993.75"
- cell $and $and$ls180.v:7993$2558
+ attribute \src "ls180.v:8039.8-8039.75"
+ cell $and $and$ls180.v:8039$2568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_syncfifo_we
connect \B \main_uart_tx_fifo_syncfifo_writable
- connect \Y $and$ls180.v:7993$2558_Y
+ connect \Y $and$ls180.v:8039$2568_Y
end
- attribute \src "ls180.v:7993.7-7993.107"
- cell $and $and$ls180.v:7993$2560
+ attribute \src "ls180.v:8039.7-8039.107"
+ cell $and $and$ls180.v:8039$2570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:7993$2558_Y
- connect \B $not$ls180.v:7993$2559_Y
- connect \Y $and$ls180.v:7993$2560_Y
+ connect \A $and$ls180.v:8039$2568_Y
+ connect \B $not$ls180.v:8039$2569_Y
+ connect \Y $and$ls180.v:8039$2570_Y
end
- attribute \src "ls180.v:8009.8-8009.75"
- cell $and $and$ls180.v:8009$2564
+ attribute \src "ls180.v:8055.8-8055.75"
+ cell $and $and$ls180.v:8055$2574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_syncfifo_we
connect \B \main_uart_rx_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8009$2564_Y
+ connect \Y $and$ls180.v:8055$2574_Y
end
- attribute \src "ls180.v:8009.7-8009.107"
- cell $and $and$ls180.v:8009$2566
+ attribute \src "ls180.v:8055.7-8055.107"
+ cell $and $and$ls180.v:8055$2576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8009$2564_Y
- connect \B $not$ls180.v:8009$2565_Y
- connect \Y $and$ls180.v:8009$2566_Y
+ connect \A $and$ls180.v:8055$2574_Y
+ connect \B $not$ls180.v:8055$2575_Y
+ connect \Y $and$ls180.v:8055$2576_Y
end
- attribute \src "ls180.v:8015.8-8015.75"
- cell $and $and$ls180.v:8015$2569
+ attribute \src "ls180.v:8061.8-8061.75"
+ cell $and $and$ls180.v:8061$2579
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_syncfifo_we
connect \B \main_uart_rx_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8015$2569_Y
+ connect \Y $and$ls180.v:8061$2579_Y
end
- attribute \src "ls180.v:8015.7-8015.107"
- cell $and $and$ls180.v:8015$2571
+ attribute \src "ls180.v:8061.7-8061.107"
+ cell $and $and$ls180.v:8061$2581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8015$2569_Y
- connect \B $not$ls180.v:8015$2570_Y
- connect \Y $and$ls180.v:8015$2571_Y
+ connect \A $and$ls180.v:8061$2579_Y
+ connect \B $not$ls180.v:8061$2580_Y
+ connect \Y $and$ls180.v:8061$2581_Y
end
- attribute \src "ls180.v:8128.7-8128.96"
- cell $and $and$ls180.v:8128$2594
+ attribute \src "ls180.v:8174.7-8174.96"
+ cell $and $and$ls180.v:8174$2604
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_source_valid
connect \B \main_sdphy_cmdr_cmdr_converter_source_ready
- connect \Y $and$ls180.v:8128$2594_Y
+ connect \Y $and$ls180.v:8174$2604_Y
end
- attribute \src "ls180.v:8129.8-8129.93"
- cell $and $and$ls180.v:8129$2595
+ attribute \src "ls180.v:8175.8-8175.93"
+ cell $and $and$ls180.v:8175$2605
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
- connect \Y $and$ls180.v:8129$2595_Y
+ connect \Y $and$ls180.v:8175$2605_Y
end
- attribute \src "ls180.v:8137.8-8137.93"
- cell $and $and$ls180.v:8137$2596
+ attribute \src "ls180.v:8183.8-8183.93"
+ cell $and $and$ls180.v:8183$2606
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
- connect \Y $and$ls180.v:8137$2596_Y
+ connect \Y $and$ls180.v:8183$2606_Y
end
- attribute \src "ls180.v:8209.7-8209.98"
- cell $and $and$ls180.v:8209$2606
+ attribute \src "ls180.v:8255.7-8255.98"
+ cell $and $and$ls180.v:8255$2616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_source_valid
connect \B \main_sdphy_dataw_crcr_converter_source_ready
- connect \Y $and$ls180.v:8209$2606_Y
+ connect \Y $and$ls180.v:8255$2616_Y
end
- attribute \src "ls180.v:8210.8-8210.95"
- cell $and $and$ls180.v:8210$2607
+ attribute \src "ls180.v:8256.8-8256.95"
+ cell $and $and$ls180.v:8256$2617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_sink_valid
connect \B \main_sdphy_dataw_crcr_converter_sink_ready
- connect \Y $and$ls180.v:8210$2607_Y
+ connect \Y $and$ls180.v:8256$2617_Y
end
- attribute \src "ls180.v:8218.8-8218.95"
- cell $and $and$ls180.v:8218$2608
+ attribute \src "ls180.v:8264.8-8264.95"
+ cell $and $and$ls180.v:8264$2618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_sink_valid
connect \B \main_sdphy_dataw_crcr_converter_sink_ready
- connect \Y $and$ls180.v:8218$2608_Y
+ connect \Y $and$ls180.v:8264$2618_Y
end
- attribute \src "ls180.v:8288.7-8288.100"
- cell $and $and$ls180.v:8288$2618
+ attribute \src "ls180.v:8334.7-8334.100"
+ cell $and $and$ls180.v:8334$2628
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_source_valid
connect \B \main_sdphy_datar_datar_converter_source_ready
- connect \Y $and$ls180.v:8288$2618_Y
+ connect \Y $and$ls180.v:8334$2628_Y
end
- attribute \src "ls180.v:8289.8-8289.97"
- cell $and $and$ls180.v:8289$2619
+ attribute \src "ls180.v:8335.8-8335.97"
+ cell $and $and$ls180.v:8335$2629
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_sink_valid
connect \B \main_sdphy_datar_datar_converter_sink_ready
- connect \Y $and$ls180.v:8289$2619_Y
+ connect \Y $and$ls180.v:8335$2629_Y
end
- attribute \src "ls180.v:8297.8-8297.97"
- cell $and $and$ls180.v:8297$2620
+ attribute \src "ls180.v:8343.8-8343.97"
+ cell $and $and$ls180.v:8343$2630
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_sink_valid
connect \B \main_sdphy_datar_datar_converter_sink_ready
- connect \Y $and$ls180.v:8297$2620_Y
+ connect \Y $and$ls180.v:8343$2630_Y
end
- attribute \src "ls180.v:8388.7-8388.82"
- cell $and $and$ls180.v:8388$2626
+ attribute \src "ls180.v:8434.7-8434.82"
+ cell $and $and$ls180.v:8434$2636
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_ready
connect \B \main_sdcore_crc16_checker_sink_valid
- connect \Y $and$ls180.v:8388$2626_Y
+ connect \Y $and$ls180.v:8434$2636_Y
end
- attribute \src "ls180.v:8391.7-8391.82"
- cell $and $and$ls180.v:8391$2627
+ attribute \src "ls180.v:8437.7-8437.82"
+ cell $and $and$ls180.v:8437$2637
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_ready
connect \B \main_sdcore_crc16_checker_sink_valid
- connect \Y $and$ls180.v:8391$2627_Y
+ connect \Y $and$ls180.v:8437$2637_Y
end
- attribute \src "ls180.v:8394.7-8394.82"
- cell $and $and$ls180.v:8394$2628
+ attribute \src "ls180.v:8440.7-8440.82"
+ cell $and $and$ls180.v:8440$2638
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_ready
connect \B \main_sdcore_crc16_checker_sink_valid
- connect \Y $and$ls180.v:8394$2628_Y
+ connect \Y $and$ls180.v:8440$2638_Y
end
- attribute \src "ls180.v:8397.7-8397.82"
- cell $and $and$ls180.v:8397$2629
+ attribute \src "ls180.v:8443.7-8443.82"
+ cell $and $and$ls180.v:8443$2639
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_ready
connect \B \main_sdcore_crc16_checker_sink_valid
- connect \Y $and$ls180.v:8397$2629_Y
+ connect \Y $and$ls180.v:8443$2639_Y
end
- attribute \src "ls180.v:8400.7-8400.82"
- cell $and $and$ls180.v:8400$2630
+ attribute \src "ls180.v:8446.7-8446.82"
+ cell $and $and$ls180.v:8446$2640
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:8400$2630_Y
+ connect \Y $and$ls180.v:8446$2640_Y
end
- attribute \src "ls180.v:8405.7-8405.82"
- cell $and $and$ls180.v:8405$2631
+ attribute \src "ls180.v:8451.7-8451.82"
+ cell $and $and$ls180.v:8451$2641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:8405$2631_Y
+ connect \Y $and$ls180.v:8451$2641_Y
end
- attribute \src "ls180.v:8410.7-8410.82"
- cell $and $and$ls180.v:8410$2632
+ attribute \src "ls180.v:8456.7-8456.82"
+ cell $and $and$ls180.v:8456$2642
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:8410$2632_Y
+ connect \Y $and$ls180.v:8456$2642_Y
end
- attribute \src "ls180.v:8415.7-8415.82"
- cell $and $and$ls180.v:8415$2633
+ attribute \src "ls180.v:8461.7-8461.82"
+ cell $and $and$ls180.v:8461$2643
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:8415$2633_Y
+ connect \Y $and$ls180.v:8461$2643_Y
end
- attribute \src "ls180.v:8420.7-8420.82"
- cell $and $and$ls180.v:8420$2634
+ attribute \src "ls180.v:8466.7-8466.82"
+ cell $and $and$ls180.v:8466$2644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_sink_valid
connect \B \main_sdcore_crc16_checker_sink_ready
- connect \Y $and$ls180.v:8420$2634_Y
+ connect \Y $and$ls180.v:8466$2644_Y
end
- attribute \src "ls180.v:8485.8-8485.83"
- cell $and $and$ls180.v:8485$2637
+ attribute \src "ls180.v:8531.8-8531.83"
+ cell $and $and$ls180.v:8531$2647
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_syncfifo_we
connect \B \main_sdblock2mem_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8485$2637_Y
+ connect \Y $and$ls180.v:8531$2647_Y
end
- attribute \src "ls180.v:8485.7-8485.119"
- cell $and $and$ls180.v:8485$2639
+ attribute \src "ls180.v:8531.7-8531.119"
+ cell $and $and$ls180.v:8531$2649
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8485$2637_Y
- connect \B $not$ls180.v:8485$2638_Y
- connect \Y $and$ls180.v:8485$2639_Y
+ connect \A $and$ls180.v:8531$2647_Y
+ connect \B $not$ls180.v:8531$2648_Y
+ connect \Y $and$ls180.v:8531$2649_Y
end
- attribute \src "ls180.v:8491.8-8491.83"
- cell $and $and$ls180.v:8491$2642
+ attribute \src "ls180.v:8537.8-8537.83"
+ cell $and $and$ls180.v:8537$2652
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_syncfifo_we
connect \B \main_sdblock2mem_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8491$2642_Y
+ connect \Y $and$ls180.v:8537$2652_Y
end
- attribute \src "ls180.v:8491.7-8491.119"
- cell $and $and$ls180.v:8491$2644
+ attribute \src "ls180.v:8537.7-8537.119"
+ cell $and $and$ls180.v:8537$2654
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8491$2642_Y
- connect \B $not$ls180.v:8491$2643_Y
- connect \Y $and$ls180.v:8491$2644_Y
+ connect \A $and$ls180.v:8537$2652_Y
+ connect \B $not$ls180.v:8537$2653_Y
+ connect \Y $and$ls180.v:8537$2654_Y
end
- attribute \src "ls180.v:8511.7-8511.88"
- cell $and $and$ls180.v:8511$2651
+ attribute \src "ls180.v:8557.7-8557.88"
+ cell $and $and$ls180.v:8557$2661
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_source_valid
connect \B \main_sdblock2mem_converter_source_ready
- connect \Y $and$ls180.v:8511$2651_Y
+ connect \Y $and$ls180.v:8557$2661_Y
end
- attribute \src "ls180.v:8512.8-8512.85"
- cell $and $and$ls180.v:8512$2652
+ attribute \src "ls180.v:8558.8-8558.85"
+ cell $and $and$ls180.v:8558$2662
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_sink_valid
connect \B \main_sdblock2mem_converter_sink_ready
- connect \Y $and$ls180.v:8512$2652_Y
+ connect \Y $and$ls180.v:8558$2662_Y
end
- attribute \src "ls180.v:8520.8-8520.85"
- cell $and $and$ls180.v:8520$2653
+ attribute \src "ls180.v:8566.8-8566.85"
+ cell $and $and$ls180.v:8566$2663
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_sink_valid
connect \B \main_sdblock2mem_converter_sink_ready
- connect \Y $and$ls180.v:8520$2653_Y
+ connect \Y $and$ls180.v:8566$2663_Y
end
- attribute \src "ls180.v:8564.7-8564.88"
- cell $and $and$ls180.v:8564$2657
+ attribute \src "ls180.v:8610.7-8610.88"
+ cell $and $and$ls180.v:8610$2667
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_converter_source_valid
connect \B \main_sdmem2block_converter_source_ready
- connect \Y $and$ls180.v:8564$2657_Y
+ connect \Y $and$ls180.v:8610$2667_Y
end
- attribute \src "ls180.v:8571.8-8571.83"
- cell $and $and$ls180.v:8571$2659
+ attribute \src "ls180.v:8617.8-8617.83"
+ cell $and $and$ls180.v:8617$2669
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_syncfifo_we
connect \B \main_sdmem2block_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8571$2659_Y
+ connect \Y $and$ls180.v:8617$2669_Y
end
- attribute \src "ls180.v:8571.7-8571.119"
- cell $and $and$ls180.v:8571$2661
+ attribute \src "ls180.v:8617.7-8617.119"
+ cell $and $and$ls180.v:8617$2671
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8571$2659_Y
- connect \B $not$ls180.v:8571$2660_Y
- connect \Y $and$ls180.v:8571$2661_Y
+ connect \A $and$ls180.v:8617$2669_Y
+ connect \B $not$ls180.v:8617$2670_Y
+ connect \Y $and$ls180.v:8617$2671_Y
end
- attribute \src "ls180.v:8577.8-8577.83"
- cell $and $and$ls180.v:8577$2664
+ attribute \src "ls180.v:8623.8-8623.83"
+ cell $and $and$ls180.v:8623$2674
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_syncfifo_we
connect \B \main_sdmem2block_fifo_syncfifo_writable
- connect \Y $and$ls180.v:8577$2664_Y
+ connect \Y $and$ls180.v:8623$2674_Y
end
- attribute \src "ls180.v:8577.7-8577.119"
- cell $and $and$ls180.v:8577$2666
+ attribute \src "ls180.v:8623.7-8623.119"
+ cell $and $and$ls180.v:8623$2676
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:8577$2664_Y
- connect \B $not$ls180.v:8577$2665_Y
- connect \Y $and$ls180.v:8577$2666_Y
+ connect \A $and$ls180.v:8623$2674_Y
+ connect \B $not$ls180.v:8623$2675_Y
+ connect \Y $and$ls180.v:8623$2676_Y
end
- attribute \src "ls180.v:2763.42-2763.101"
- cell $eq $eq$ls180.v:2763$18
+ attribute \src "ls180.v:2794.42-2794.101"
+ cell $eq $eq$ls180.v:2794$18
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface0_converted_interface_sel
connect \B 1'0
- connect \Y $eq$ls180.v:2763$18_Y
+ connect \Y $eq$ls180.v:2794$18_Y
end
- attribute \src "ls180.v:2770.11-2770.54"
- cell $eq $eq$ls180.v:2770$23
+ attribute \src "ls180.v:2801.11-2801.54"
+ cell $eq $eq$ls180.v:2801$23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter0_counter
connect \B 1'1
- connect \Y $eq$ls180.v:2770$23_Y
+ connect \Y $eq$ls180.v:2801$23_Y
end
- attribute \src "ls180.v:2823.42-2823.101"
- cell $eq $eq$ls180.v:2823$29
+ attribute \src "ls180.v:2854.42-2854.101"
+ cell $eq $eq$ls180.v:2854$29
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface1_converted_interface_sel
connect \B 1'0
- connect \Y $eq$ls180.v:2823$29_Y
+ connect \Y $eq$ls180.v:2854$29_Y
end
- attribute \src "ls180.v:2830.11-2830.54"
- cell $eq $eq$ls180.v:2830$34
+ attribute \src "ls180.v:2861.11-2861.54"
+ cell $eq $eq$ls180.v:2861$34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter1_counter
connect \B 1'1
- connect \Y $eq$ls180.v:2830$34_Y
+ connect \Y $eq$ls180.v:2861$34_Y
end
- attribute \src "ls180.v:2883.42-2883.101"
- cell $eq $eq$ls180.v:2883$40
+ attribute \src "ls180.v:2914.42-2914.101"
+ cell $eq $eq$ls180.v:2914$40
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface2_converted_interface_sel
connect \B 1'0
- connect \Y $eq$ls180.v:2883$40_Y
+ connect \Y $eq$ls180.v:2914$40_Y
end
- attribute \src "ls180.v:2890.11-2890.54"
- cell $eq $eq$ls180.v:2890$45
+ attribute \src "ls180.v:2921.11-2921.54"
+ cell $eq $eq$ls180.v:2921$45
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter2_counter
connect \B 1'1
- connect \Y $eq$ls180.v:2890$45_Y
+ connect \Y $eq$ls180.v:2921$45_Y
end
- attribute \src "ls180.v:3076.34-3076.65"
- cell $eq $eq$ls180.v:3076$73
+ attribute \src "ls180.v:3107.34-3107.65"
+ cell $eq $eq$ls180.v:3107$73
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_timer_count1
connect \B 1'0
- connect \Y $eq$ls180.v:3076$73_Y
+ connect \Y $eq$ls180.v:3107$73_Y
end
- attribute \src "ls180.v:3080.68-3080.102"
- cell $eq $eq$ls180.v:3080$76
+ attribute \src "ls180.v:3111.68-3111.102"
+ cell $eq $eq$ls180.v:3111$76
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_count
connect \B 1'0
- connect \Y $eq$ls180.v:3080$76_Y
+ connect \Y $eq$ls180.v:3111$76_Y
end
- attribute \src "ls180.v:3124.43-3124.134"
- cell $eq $eq$ls180.v:3124$81
+ attribute \src "ls180.v:3155.43-3155.134"
+ cell $eq $eq$ls180.v:3155$81
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_row
connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
- connect \Y $eq$ls180.v:3124$81_Y
+ connect \Y $eq$ls180.v:3155$81_Y
end
- attribute \src "ls180.v:3141.47-3141.88"
- cell $eq $eq$ls180.v:3141$94
+ attribute \src "ls180.v:3172.47-3172.88"
+ cell $eq $eq$ls180.v:3172$94
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_row_close
connect \B 1'0
- connect \Y $eq$ls180.v:3141$94_Y
+ connect \Y $eq$ls180.v:3172$94_Y
end
- attribute \src "ls180.v:3281.43-3281.134"
- cell $eq $eq$ls180.v:3281$111
+ attribute \src "ls180.v:3312.43-3312.134"
+ cell $eq $eq$ls180.v:3312$111
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_row
connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
- connect \Y $eq$ls180.v:3281$111_Y
+ connect \Y $eq$ls180.v:3312$111_Y
end
- attribute \src "ls180.v:3298.47-3298.88"
- cell $eq $eq$ls180.v:3298$124
+ attribute \src "ls180.v:3329.47-3329.88"
+ cell $eq $eq$ls180.v:3329$124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_row_close
connect \B 1'0
- connect \Y $eq$ls180.v:3298$124_Y
+ connect \Y $eq$ls180.v:3329$124_Y
end
- attribute \src "ls180.v:3438.43-3438.134"
- cell $eq $eq$ls180.v:3438$141
+ attribute \src "ls180.v:3469.43-3469.134"
+ cell $eq $eq$ls180.v:3469$141
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_row
connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
- connect \Y $eq$ls180.v:3438$141_Y
+ connect \Y $eq$ls180.v:3469$141_Y
end
- attribute \src "ls180.v:3455.47-3455.88"
- cell $eq $eq$ls180.v:3455$154
+ attribute \src "ls180.v:3486.47-3486.88"
+ cell $eq $eq$ls180.v:3486$154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_row_close
connect \B 1'0
- connect \Y $eq$ls180.v:3455$154_Y
+ connect \Y $eq$ls180.v:3486$154_Y
end
- attribute \src "ls180.v:3595.43-3595.134"
- cell $eq $eq$ls180.v:3595$171
+ attribute \src "ls180.v:3626.43-3626.134"
+ cell $eq $eq$ls180.v:3626$171
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_row
connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
- connect \Y $eq$ls180.v:3595$171_Y
+ connect \Y $eq$ls180.v:3626$171_Y
end
- attribute \src "ls180.v:3612.47-3612.88"
- cell $eq $eq$ls180.v:3612$184
+ attribute \src "ls180.v:3643.47-3643.88"
+ cell $eq $eq$ls180.v:3643$184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_row_close
connect \B 1'0
- connect \Y $eq$ls180.v:3612$184_Y
+ connect \Y $eq$ls180.v:3643$184_Y
end
- attribute \src "ls180.v:3749.32-3749.56"
- cell $eq $eq$ls180.v:3749$231
+ attribute \src "ls180.v:3780.32-3780.56"
+ cell $eq $eq$ls180.v:3780$231
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_time0
connect \B 1'0
- connect \Y $eq$ls180.v:3749$231_Y
+ connect \Y $eq$ls180.v:3780$231_Y
end
- attribute \src "ls180.v:3750.32-3750.56"
- cell $eq $eq$ls180.v:3750$232
+ attribute \src "ls180.v:3781.32-3781.56"
+ cell $eq $eq$ls180.v:3781$232
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_time1
connect \B 1'0
- connect \Y $eq$ls180.v:3750$232_Y
+ connect \Y $eq$ls180.v:3781$232_Y
end
- attribute \src "ls180.v:3761.339-3761.418"
- cell $eq $eq$ls180.v:3761$246
+ attribute \src "ls180.v:3792.339-3792.418"
+ cell $eq $eq$ls180.v:3792$246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_is_read
connect \B \main_sdram_choose_cmd_want_reads
- connect \Y $eq$ls180.v:3761$246_Y
+ connect \Y $eq$ls180.v:3792$246_Y
end
- attribute \src "ls180.v:3761.423-3761.504"
- cell $eq $eq$ls180.v:3761$247
+ attribute \src "ls180.v:3792.423-3792.504"
+ cell $eq $eq$ls180.v:3792$247
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_is_write
connect \B \main_sdram_choose_cmd_want_writes
- connect \Y $eq$ls180.v:3761$247_Y
+ connect \Y $eq$ls180.v:3792$247_Y
end
- attribute \src "ls180.v:3762.339-3762.418"
- cell $eq $eq$ls180.v:3762$259
+ attribute \src "ls180.v:3793.339-3793.418"
+ cell $eq $eq$ls180.v:3793$259
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_is_read
connect \B \main_sdram_choose_cmd_want_reads
- connect \Y $eq$ls180.v:3762$259_Y
+ connect \Y $eq$ls180.v:3793$259_Y
end
- attribute \src "ls180.v:3762.423-3762.504"
- cell $eq $eq$ls180.v:3762$260
+ attribute \src "ls180.v:3793.423-3793.504"
+ cell $eq $eq$ls180.v:3793$260
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_is_write
connect \B \main_sdram_choose_cmd_want_writes
- connect \Y $eq$ls180.v:3762$260_Y
+ connect \Y $eq$ls180.v:3793$260_Y
end
- attribute \src "ls180.v:3763.339-3763.418"
- cell $eq $eq$ls180.v:3763$272
+ attribute \src "ls180.v:3794.339-3794.418"
+ cell $eq $eq$ls180.v:3794$272
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_is_read
connect \B \main_sdram_choose_cmd_want_reads
- connect \Y $eq$ls180.v:3763$272_Y
+ connect \Y $eq$ls180.v:3794$272_Y
end
- attribute \src "ls180.v:3763.423-3763.504"
- cell $eq $eq$ls180.v:3763$273
+ attribute \src "ls180.v:3794.423-3794.504"
+ cell $eq $eq$ls180.v:3794$273
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_is_write
connect \B \main_sdram_choose_cmd_want_writes
- connect \Y $eq$ls180.v:3763$273_Y
+ connect \Y $eq$ls180.v:3794$273_Y
end
- attribute \src "ls180.v:3764.339-3764.418"
- cell $eq $eq$ls180.v:3764$285
+ attribute \src "ls180.v:3795.339-3795.418"
+ cell $eq $eq$ls180.v:3795$285
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_is_read
connect \B \main_sdram_choose_cmd_want_reads
- connect \Y $eq$ls180.v:3764$285_Y
+ connect \Y $eq$ls180.v:3795$285_Y
end
- attribute \src "ls180.v:3764.423-3764.504"
- cell $eq $eq$ls180.v:3764$286
+ attribute \src "ls180.v:3795.423-3795.504"
+ cell $eq $eq$ls180.v:3795$286
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_is_write
connect \B \main_sdram_choose_cmd_want_writes
- connect \Y $eq$ls180.v:3764$286_Y
+ connect \Y $eq$ls180.v:3795$286_Y
end
- attribute \src "ls180.v:3794.339-3794.418"
- cell $eq $eq$ls180.v:3794$304
+ attribute \src "ls180.v:3825.339-3825.418"
+ cell $eq $eq$ls180.v:3825$304
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_is_read
connect \B \main_sdram_choose_req_want_reads
- connect \Y $eq$ls180.v:3794$304_Y
+ connect \Y $eq$ls180.v:3825$304_Y
end
- attribute \src "ls180.v:3794.423-3794.504"
- cell $eq $eq$ls180.v:3794$305
+ attribute \src "ls180.v:3825.423-3825.504"
+ cell $eq $eq$ls180.v:3825$305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_is_write
connect \B \main_sdram_choose_req_want_writes
- connect \Y $eq$ls180.v:3794$305_Y
+ connect \Y $eq$ls180.v:3825$305_Y
end
- attribute \src "ls180.v:3795.339-3795.418"
- cell $eq $eq$ls180.v:3795$317
+ attribute \src "ls180.v:3826.339-3826.418"
+ cell $eq $eq$ls180.v:3826$317
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_is_read
connect \B \main_sdram_choose_req_want_reads
- connect \Y $eq$ls180.v:3795$317_Y
+ connect \Y $eq$ls180.v:3826$317_Y
end
- attribute \src "ls180.v:3795.423-3795.504"
- cell $eq $eq$ls180.v:3795$318
+ attribute \src "ls180.v:3826.423-3826.504"
+ cell $eq $eq$ls180.v:3826$318
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_is_write
connect \B \main_sdram_choose_req_want_writes
- connect \Y $eq$ls180.v:3795$318_Y
+ connect \Y $eq$ls180.v:3826$318_Y
end
- attribute \src "ls180.v:3796.339-3796.418"
- cell $eq $eq$ls180.v:3796$330
+ attribute \src "ls180.v:3827.339-3827.418"
+ cell $eq $eq$ls180.v:3827$330
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_is_read
connect \B \main_sdram_choose_req_want_reads
- connect \Y $eq$ls180.v:3796$330_Y
+ connect \Y $eq$ls180.v:3827$330_Y
end
- attribute \src "ls180.v:3796.423-3796.504"
- cell $eq $eq$ls180.v:3796$331
+ attribute \src "ls180.v:3827.423-3827.504"
+ cell $eq $eq$ls180.v:3827$331
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_is_write
connect \B \main_sdram_choose_req_want_writes
- connect \Y $eq$ls180.v:3796$331_Y
+ connect \Y $eq$ls180.v:3827$331_Y
end
- attribute \src "ls180.v:3797.339-3797.418"
- cell $eq $eq$ls180.v:3797$343
+ attribute \src "ls180.v:3828.339-3828.418"
+ cell $eq $eq$ls180.v:3828$343
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_is_read
connect \B \main_sdram_choose_req_want_reads
- connect \Y $eq$ls180.v:3797$343_Y
+ connect \Y $eq$ls180.v:3828$343_Y
end
- attribute \src "ls180.v:3797.423-3797.504"
- cell $eq $eq$ls180.v:3797$344
+ attribute \src "ls180.v:3828.423-3828.504"
+ cell $eq $eq$ls180.v:3828$344
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_is_write
connect \B \main_sdram_choose_req_want_writes
- connect \Y $eq$ls180.v:3797$344_Y
+ connect \Y $eq$ls180.v:3828$344_Y
end
- attribute \src "ls180.v:3826.78-3826.113"
- cell $eq $eq$ls180.v:3826$353
+ attribute \src "ls180.v:3857.78-3857.113"
+ cell $eq $eq$ls180.v:3857$353
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3826$353_Y
+ connect \Y $eq$ls180.v:3857$353_Y
end
- attribute \src "ls180.v:3829.78-3829.113"
- cell $eq $eq$ls180.v:3829$356
+ attribute \src "ls180.v:3860.78-3860.113"
+ cell $eq $eq$ls180.v:3860$356
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3829$356_Y
+ connect \Y $eq$ls180.v:3860$356_Y
end
- attribute \src "ls180.v:3835.78-3835.113"
- cell $eq $eq$ls180.v:3835$360
+ attribute \src "ls180.v:3866.78-3866.113"
+ cell $eq $eq$ls180.v:3866$360
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_grant
connect \B 1'1
- connect \Y $eq$ls180.v:3835$360_Y
+ connect \Y $eq$ls180.v:3866$360_Y
end
- attribute \src "ls180.v:3838.78-3838.113"
- cell $eq $eq$ls180.v:3838$363
+ attribute \src "ls180.v:3869.78-3869.113"
+ cell $eq $eq$ls180.v:3869$363
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_grant
connect \B 1'1
- connect \Y $eq$ls180.v:3838$363_Y
+ connect \Y $eq$ls180.v:3869$363_Y
end
- attribute \src "ls180.v:3844.78-3844.113"
- cell $eq $eq$ls180.v:3844$367
+ attribute \src "ls180.v:3875.78-3875.113"
+ cell $eq $eq$ls180.v:3875$367
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_grant
connect \B 2'10
- connect \Y $eq$ls180.v:3844$367_Y
+ connect \Y $eq$ls180.v:3875$367_Y
end
- attribute \src "ls180.v:3847.78-3847.113"
- cell $eq $eq$ls180.v:3847$370
+ attribute \src "ls180.v:3878.78-3878.113"
+ cell $eq $eq$ls180.v:3878$370
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_grant
connect \B 2'10
- connect \Y $eq$ls180.v:3847$370_Y
+ connect \Y $eq$ls180.v:3878$370_Y
end
- attribute \src "ls180.v:3853.78-3853.113"
- cell $eq $eq$ls180.v:3853$374
+ attribute \src "ls180.v:3884.78-3884.113"
+ cell $eq $eq$ls180.v:3884$374
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_grant
connect \B 2'11
- connect \Y $eq$ls180.v:3853$374_Y
+ connect \Y $eq$ls180.v:3884$374_Y
end
- attribute \src "ls180.v:3856.78-3856.113"
- cell $eq $eq$ls180.v:3856$377
+ attribute \src "ls180.v:3887.78-3887.113"
+ cell $eq $eq$ls180.v:3887$377
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_grant
connect \B 2'11
- connect \Y $eq$ls180.v:3856$377_Y
+ connect \Y $eq$ls180.v:3887$377_Y
end
- attribute \src "ls180.v:3937.42-3937.82"
- cell $eq $eq$ls180.v:3937$400
+ attribute \src "ls180.v:3968.42-3968.82"
+ cell $eq $eq$ls180.v:3968$400
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 1'0
- connect \Y $eq$ls180.v:3937$400_Y
+ connect \Y $eq$ls180.v:3968$400_Y
end
- attribute \src "ls180.v:3937.145-3937.178"
- cell $eq $eq$ls180.v:3937$401
+ attribute \src "ls180.v:3968.145-3968.178"
+ cell $eq $eq$ls180.v:3968$401
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3937$401_Y
+ connect \Y $eq$ls180.v:3968$401_Y
end
- attribute \src "ls180.v:3937.220-3937.253"
- cell $eq $eq$ls180.v:3937$404
+ attribute \src "ls180.v:3968.220-3968.253"
+ cell $eq $eq$ls180.v:3968$404
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3937$404_Y
+ connect \Y $eq$ls180.v:3968$404_Y
end
- attribute \src "ls180.v:3937.295-3937.328"
- cell $eq $eq$ls180.v:3937$407
+ attribute \src "ls180.v:3968.295-3968.328"
+ cell $eq $eq$ls180.v:3968$407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3937$407_Y
+ connect \Y $eq$ls180.v:3968$407_Y
end
- attribute \src "ls180.v:3942.42-3942.82"
- cell $eq $eq$ls180.v:3942$416
+ attribute \src "ls180.v:3973.42-3973.82"
+ cell $eq $eq$ls180.v:3973$416
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 1'1
- connect \Y $eq$ls180.v:3942$416_Y
+ connect \Y $eq$ls180.v:3973$416_Y
end
- attribute \src "ls180.v:3942.145-3942.178"
- cell $eq $eq$ls180.v:3942$417
+ attribute \src "ls180.v:3973.145-3973.178"
+ cell $eq $eq$ls180.v:3973$417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3942$417_Y
+ connect \Y $eq$ls180.v:3973$417_Y
end
- attribute \src "ls180.v:3942.220-3942.253"
- cell $eq $eq$ls180.v:3942$420
+ attribute \src "ls180.v:3973.220-3973.253"
+ cell $eq $eq$ls180.v:3973$420
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3942$420_Y
+ connect \Y $eq$ls180.v:3973$420_Y
end
- attribute \src "ls180.v:3942.295-3942.328"
- cell $eq $eq$ls180.v:3942$423
+ attribute \src "ls180.v:3973.295-3973.328"
+ cell $eq $eq$ls180.v:3973$423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3942$423_Y
+ connect \Y $eq$ls180.v:3973$423_Y
end
- attribute \src "ls180.v:3947.42-3947.82"
- cell $eq $eq$ls180.v:3947$432
+ attribute \src "ls180.v:3978.42-3978.82"
+ cell $eq $eq$ls180.v:3978$432
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 2'10
- connect \Y $eq$ls180.v:3947$432_Y
+ connect \Y $eq$ls180.v:3978$432_Y
end
- attribute \src "ls180.v:3947.145-3947.178"
- cell $eq $eq$ls180.v:3947$433
+ attribute \src "ls180.v:3978.145-3978.178"
+ cell $eq $eq$ls180.v:3978$433
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3947$433_Y
+ connect \Y $eq$ls180.v:3978$433_Y
end
- attribute \src "ls180.v:3947.220-3947.253"
- cell $eq $eq$ls180.v:3947$436
+ attribute \src "ls180.v:3978.220-3978.253"
+ cell $eq $eq$ls180.v:3978$436
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3947$436_Y
+ connect \Y $eq$ls180.v:3978$436_Y
end
- attribute \src "ls180.v:3947.295-3947.328"
- cell $eq $eq$ls180.v:3947$439
+ attribute \src "ls180.v:3978.295-3978.328"
+ cell $eq $eq$ls180.v:3978$439
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3947$439_Y
+ connect \Y $eq$ls180.v:3978$439_Y
end
- attribute \src "ls180.v:3952.42-3952.82"
- cell $eq $eq$ls180.v:3952$448
+ attribute \src "ls180.v:3983.42-3983.82"
+ cell $eq $eq$ls180.v:3983$448
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 2'11
- connect \Y $eq$ls180.v:3952$448_Y
+ connect \Y $eq$ls180.v:3983$448_Y
end
- attribute \src "ls180.v:3952.145-3952.178"
- cell $eq $eq$ls180.v:3952$449
+ attribute \src "ls180.v:3983.145-3983.178"
+ cell $eq $eq$ls180.v:3983$449
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3952$449_Y
+ connect \Y $eq$ls180.v:3983$449_Y
end
- attribute \src "ls180.v:3952.220-3952.253"
- cell $eq $eq$ls180.v:3952$452
+ attribute \src "ls180.v:3983.220-3983.253"
+ cell $eq $eq$ls180.v:3983$452
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3952$452_Y
+ connect \Y $eq$ls180.v:3983$452_Y
end
- attribute \src "ls180.v:3952.295-3952.328"
- cell $eq $eq$ls180.v:3952$455
+ attribute \src "ls180.v:3983.295-3983.328"
+ cell $eq $eq$ls180.v:3983$455
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3952$455_Y
+ connect \Y $eq$ls180.v:3983$455_Y
end
- attribute \src "ls180.v:3957.44-3957.77"
- cell $eq $eq$ls180.v:3957$464
+ attribute \src "ls180.v:3988.44-3988.77"
+ cell $eq $eq$ls180.v:3988$464
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$464_Y
+ connect \Y $eq$ls180.v:3988$464_Y
end
- attribute \src "ls180.v:3957.83-3957.123"
- cell $eq $eq$ls180.v:3957$465
+ attribute \src "ls180.v:3988.83-3988.123"
+ cell $eq $eq$ls180.v:3988$465
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 1'0
- connect \Y $eq$ls180.v:3957$465_Y
+ connect \Y $eq$ls180.v:3988$465_Y
end
- attribute \src "ls180.v:3957.186-3957.219"
- cell $eq $eq$ls180.v:3957$466
+ attribute \src "ls180.v:3988.186-3988.219"
+ cell $eq $eq$ls180.v:3988$466
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$466_Y
+ connect \Y $eq$ls180.v:3988$466_Y
end
- attribute \src "ls180.v:3957.261-3957.294"
- cell $eq $eq$ls180.v:3957$469
+ attribute \src "ls180.v:3988.261-3988.294"
+ cell $eq $eq$ls180.v:3988$469
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$469_Y
+ connect \Y $eq$ls180.v:3988$469_Y
end
- attribute \src "ls180.v:3957.336-3957.369"
- cell $eq $eq$ls180.v:3957$472
+ attribute \src "ls180.v:3988.336-3988.369"
+ cell $eq $eq$ls180.v:3988$472
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$472_Y
+ connect \Y $eq$ls180.v:3988$472_Y
end
- attribute \src "ls180.v:3957.418-3957.451"
- cell $eq $eq$ls180.v:3957$480
+ attribute \src "ls180.v:3988.418-3988.451"
+ cell $eq $eq$ls180.v:3988$480
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$480_Y
+ connect \Y $eq$ls180.v:3988$480_Y
end
- attribute \src "ls180.v:3957.457-3957.497"
- cell $eq $eq$ls180.v:3957$481
+ attribute \src "ls180.v:3988.457-3988.497"
+ cell $eq $eq$ls180.v:3988$481
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 1'1
- connect \Y $eq$ls180.v:3957$481_Y
+ connect \Y $eq$ls180.v:3988$481_Y
end
- attribute \src "ls180.v:3957.560-3957.593"
- cell $eq $eq$ls180.v:3957$482
+ attribute \src "ls180.v:3988.560-3988.593"
+ cell $eq $eq$ls180.v:3988$482
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$482_Y
+ connect \Y $eq$ls180.v:3988$482_Y
end
- attribute \src "ls180.v:3957.635-3957.668"
- cell $eq $eq$ls180.v:3957$485
+ attribute \src "ls180.v:3988.635-3988.668"
+ cell $eq $eq$ls180.v:3988$485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$485_Y
+ connect \Y $eq$ls180.v:3988$485_Y
end
- attribute \src "ls180.v:3957.710-3957.743"
- cell $eq $eq$ls180.v:3957$488
+ attribute \src "ls180.v:3988.710-3988.743"
+ cell $eq $eq$ls180.v:3988$488
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$488_Y
+ connect \Y $eq$ls180.v:3988$488_Y
end
- attribute \src "ls180.v:3957.792-3957.825"
- cell $eq $eq$ls180.v:3957$496
+ attribute \src "ls180.v:3988.792-3988.825"
+ cell $eq $eq$ls180.v:3988$496
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$496_Y
+ connect \Y $eq$ls180.v:3988$496_Y
end
- attribute \src "ls180.v:3957.831-3957.871"
- cell $eq $eq$ls180.v:3957$497
+ attribute \src "ls180.v:3988.831-3988.871"
+ cell $eq $eq$ls180.v:3988$497
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 2'10
- connect \Y $eq$ls180.v:3957$497_Y
+ connect \Y $eq$ls180.v:3988$497_Y
end
- attribute \src "ls180.v:3957.934-3957.967"
- cell $eq $eq$ls180.v:3957$498
+ attribute \src "ls180.v:3988.934-3988.967"
+ cell $eq $eq$ls180.v:3988$498
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$498_Y
+ connect \Y $eq$ls180.v:3988$498_Y
end
- attribute \src "ls180.v:3957.1009-3957.1042"
- cell $eq $eq$ls180.v:3957$501
+ attribute \src "ls180.v:3988.1009-3988.1042"
+ cell $eq $eq$ls180.v:3988$501
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$501_Y
+ connect \Y $eq$ls180.v:3988$501_Y
end
- attribute \src "ls180.v:3957.1084-3957.1117"
- cell $eq $eq$ls180.v:3957$504
+ attribute \src "ls180.v:3988.1084-3988.1117"
+ cell $eq $eq$ls180.v:3988$504
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$504_Y
+ connect \Y $eq$ls180.v:3988$504_Y
end
- attribute \src "ls180.v:3957.1166-3957.1199"
- cell $eq $eq$ls180.v:3957$512
+ attribute \src "ls180.v:3988.1166-3988.1199"
+ cell $eq $eq$ls180.v:3988$512
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$512_Y
+ connect \Y $eq$ls180.v:3988$512_Y
end
- attribute \src "ls180.v:3957.1205-3957.1245"
- cell $eq $eq$ls180.v:3957$513
+ attribute \src "ls180.v:3988.1205-3988.1245"
+ cell $eq $eq$ls180.v:3988$513
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 2'11
- connect \Y $eq$ls180.v:3957$513_Y
+ connect \Y $eq$ls180.v:3988$513_Y
end
- attribute \src "ls180.v:3957.1308-3957.1341"
- cell $eq $eq$ls180.v:3957$514
+ attribute \src "ls180.v:3988.1308-3988.1341"
+ cell $eq $eq$ls180.v:3988$514
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$514_Y
+ connect \Y $eq$ls180.v:3988$514_Y
end
- attribute \src "ls180.v:3957.1383-3957.1416"
- cell $eq $eq$ls180.v:3957$517
+ attribute \src "ls180.v:3988.1383-3988.1416"
+ cell $eq $eq$ls180.v:3988$517
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$517_Y
+ connect \Y $eq$ls180.v:3988$517_Y
end
- attribute \src "ls180.v:3957.1458-3957.1491"
- cell $eq $eq$ls180.v:3957$520
+ attribute \src "ls180.v:3988.1458-3988.1491"
+ cell $eq $eq$ls180.v:3988$520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3957$520_Y
+ connect \Y $eq$ls180.v:3988$520_Y
end
- attribute \src "ls180.v:4016.29-4016.57"
- cell $eq $eq$ls180.v:4016$533
+ attribute \src "ls180.v:4047.29-4047.57"
+ cell $eq $eq$ls180.v:4047$533
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_sel
connect \B 1'0
- connect \Y $eq$ls180.v:4016$533_Y
+ connect \Y $eq$ls180.v:4047$533_Y
end
- attribute \src "ls180.v:4023.11-4023.41"
- cell $eq $eq$ls180.v:4023$538
+ attribute \src "ls180.v:4054.11-4054.41"
+ cell $eq $eq$ls180.v:4054$538
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_converter_counter
connect \B 1'1
- connect \Y $eq$ls180.v:4023$538_Y
+ connect \Y $eq$ls180.v:4054$538_Y
end
- attribute \src "ls180.v:4180.36-4180.111"
- cell $eq $eq$ls180.v:4180$603
+ attribute \src "ls180.v:4211.36-4211.111"
+ cell $eq $eq$ls180.v:4211$603
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \main_spi_master_clk_divider1
- connect \B $sub$ls180.v:4180$602_Y
- connect \Y $eq$ls180.v:4180$603_Y
+ connect \B $sub$ls180.v:4211$602_Y
+ connect \Y $eq$ls180.v:4211$603_Y
end
- attribute \src "ls180.v:4181.36-4181.105"
- cell $eq $eq$ls180.v:4181$605
+ attribute \src "ls180.v:4212.36-4212.105"
+ cell $eq $eq$ls180.v:4212$605
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \main_spi_master_clk_divider1
- connect \B $sub$ls180.v:4181$604_Y
- connect \Y $eq$ls180.v:4181$605_Y
+ connect \B $sub$ls180.v:4212$604_Y
+ connect \Y $eq$ls180.v:4212$605_Y
end
- attribute \src "ls180.v:4208.10-4208.67"
- cell $eq $eq$ls180.v:4208$609
+ attribute \src "ls180.v:4239.10-4239.67"
+ cell $eq $eq$ls180.v:4239$609
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
connect \A \main_spi_master_count
- connect \B $sub$ls180.v:4208$608_Y
- connect \Y $eq$ls180.v:4208$609_Y
+ connect \B $sub$ls180.v:4239$608_Y
+ connect \Y $eq$ls180.v:4239$609_Y
end
- attribute \src "ls180.v:4308.10-4308.40"
- cell $eq $eq$ls180.v:4308$636
+ attribute \src "ls180.v:4343.10-4343.40"
+ cell $eq $eq$ls180.v:4343$636
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_init_count
connect \B 7'1001111
- connect \Y $eq$ls180.v:4308$636_Y
+ connect \Y $eq$ls180.v:4343$636_Y
end
- attribute \src "ls180.v:4365.10-4365.39"
- cell $eq $eq$ls180.v:4365$639
+ attribute \src "ls180.v:4400.10-4400.39"
+ cell $eq $eq$ls180.v:4400$639
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdw_count
connect \B 3'111
- connect \Y $eq$ls180.v:4365$639_Y
+ connect \Y $eq$ls180.v:4400$639_Y
end
- attribute \src "ls180.v:4382.10-4382.39"
- cell $eq $eq$ls180.v:4382$641
+ attribute \src "ls180.v:4417.10-4417.39"
+ cell $eq $eq$ls180.v:4417$641
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdw_count
connect \B 3'111
- connect \Y $eq$ls180.v:4382$641_Y
+ connect \Y $eq$ls180.v:4417$641_Y
end
- attribute \src "ls180.v:4410.38-4410.88"
- cell $eq $eq$ls180.v:4410$643
+ attribute \src "ls180.v:4445.38-4445.88"
+ cell $eq $eq$ls180.v:4445$643
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i
connect \B 1'0
- connect \Y $eq$ls180.v:4410$643_Y
+ connect \Y $eq$ls180.v:4445$643_Y
end
- attribute \src "ls180.v:4460.9-4460.40"
- cell $eq $eq$ls180.v:4460$653
+ attribute \src "ls180.v:4495.9-4495.40"
+ cell $eq $eq$ls180.v:4495$653
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_timeout
connect \B 1'0
- connect \Y $eq$ls180.v:4460$653_Y
+ connect \Y $eq$ls180.v:4495$653_Y
end
- attribute \src "ls180.v:4469.36-4469.105"
- cell $eq $eq$ls180.v:4469$655
+ attribute \src "ls180.v:4504.36-4504.105"
+ cell $eq $eq$ls180.v:4504$655
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_count
- connect \B $sub$ls180.v:4469$654_Y
- connect \Y $eq$ls180.v:4469$655_Y
+ connect \B $sub$ls180.v:4504$654_Y
+ connect \Y $eq$ls180.v:4504$655_Y
end
- attribute \src "ls180.v:4488.9-4488.40"
- cell $eq $eq$ls180.v:4488$659
+ attribute \src "ls180.v:4523.9-4523.40"
+ cell $eq $eq$ls180.v:4523$659
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_timeout
connect \B 1'0
- connect \Y $eq$ls180.v:4488$659_Y
+ connect \Y $eq$ls180.v:4523$659_Y
end
- attribute \src "ls180.v:4500.10-4500.39"
- cell $eq $eq$ls180.v:4500$661
+ attribute \src "ls180.v:4535.10-4535.39"
+ cell $eq $eq$ls180.v:4535$661
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_count
connect \B 3'111
- connect \Y $eq$ls180.v:4500$661_Y
+ connect \Y $eq$ls180.v:4535$661_Y
end
- attribute \src "ls180.v:4537.39-4537.94"
- cell $eq $eq$ls180.v:4537$665
+ attribute \src "ls180.v:4572.39-4572.94"
+ cell $eq $eq$ls180.v:4572$665
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0]
connect \B 1'0
- connect \Y $eq$ls180.v:4537$665_Y
+ connect \Y $eq$ls180.v:4572$665_Y
end
- attribute \src "ls180.v:4574.32-4574.89"
- cell $eq $eq$ls180.v:4574$674
+ attribute \src "ls180.v:4609.32-4609.89"
+ cell $eq $eq$ls180.v:4609$674
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_source_source_payload_data0
connect \B 3'101
- connect \Y $eq$ls180.v:4574$674_Y
+ connect \Y $eq$ls180.v:4609$674_Y
end
- attribute \src "ls180.v:4622.10-4622.40"
- cell $eq $eq$ls180.v:4622$678
+ attribute \src "ls180.v:4657.10-4657.40"
+ cell $eq $eq$ls180.v:4657$678
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_count
connect \B 1'1
- connect \Y $eq$ls180.v:4622$678_Y
+ connect \Y $eq$ls180.v:4657$678_Y
end
- attribute \src "ls180.v:4671.40-4671.98"
- cell $eq $eq$ls180.v:4671$680
+ attribute \src "ls180.v:4706.40-4706.98"
+ cell $eq $eq$ls180.v:4706$680
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_pads_in_payload_data_i
connect \B 1'0
- connect \Y $eq$ls180.v:4671$680_Y
+ connect \Y $eq$ls180.v:4706$680_Y
end
- attribute \src "ls180.v:4722.9-4722.41"
- cell $eq $eq$ls180.v:4722$690
+ attribute \src "ls180.v:4757.9-4757.41"
+ cell $eq $eq$ls180.v:4757$690
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_timeout
connect \B 1'0
- connect \Y $eq$ls180.v:4722$690_Y
+ connect \Y $eq$ls180.v:4757$690_Y
end
- attribute \src "ls180.v:4731.37-4731.123"
- cell $eq $eq$ls180.v:4731$693
+ attribute \src "ls180.v:4766.37-4766.123"
+ cell $eq $eq$ls180.v:4766$693
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \B_WIDTH 10
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_count
- connect \B $sub$ls180.v:4731$692_Y
- connect \Y $eq$ls180.v:4731$693_Y
+ connect \B $sub$ls180.v:4766$692_Y
+ connect \Y $eq$ls180.v:4766$693_Y
end
- attribute \src "ls180.v:4754.9-4754.41"
- cell $eq $eq$ls180.v:4754$696
+ attribute \src "ls180.v:4789.9-4789.41"
+ cell $eq $eq$ls180.v:4789$696
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_timeout
connect \B 1'0
- connect \Y $eq$ls180.v:4754$696_Y
+ connect \Y $eq$ls180.v:4789$696_Y
end
- attribute \src "ls180.v:4764.10-4764.41"
- cell $eq $eq$ls180.v:4764$698
+ attribute \src "ls180.v:4799.10-4799.41"
+ cell $eq $eq$ls180.v:4799$698
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_count
connect \B 6'100111
- connect \Y $eq$ls180.v:4764$698_Y
+ connect \Y $eq$ls180.v:4799$698_Y
end
- attribute \src "ls180.v:4933.9-4933.47"
- cell $eq $eq$ls180.v:4933$880
+ attribute \src "ls180.v:4968.9-4968.47"
+ cell $eq $eq$ls180.v:4968$880
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_cnt
connect \B 3'111
- connect \Y $eq$ls180.v:4933$880_Y
+ connect \Y $eq$ls180.v:4968$880_Y
end
- attribute \src "ls180.v:4963.10-4963.48"
- cell $eq $eq$ls180.v:4963$881
+ attribute \src "ls180.v:4998.10-4998.48"
+ cell $eq $eq$ls180.v:4998$881
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_cnt
connect \B 3'111
- connect \Y $eq$ls180.v:4963$881_Y
+ connect \Y $eq$ls180.v:4998$881_Y
end
- attribute \src "ls180.v:4994.10-4994.78"
- cell $eq $eq$ls180.v:4994$886
+ attribute \src "ls180.v:5029.10-5029.78"
+ cell $eq $eq$ls180.v:5029$886
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_fifo0
connect \B \main_sdcore_crc16_checker_crctmp0
- connect \Y $eq$ls180.v:4994$886_Y
+ connect \Y $eq$ls180.v:5029$886_Y
end
- attribute \src "ls180.v:4994.83-4994.151"
- cell $eq $eq$ls180.v:4994$887
+ attribute \src "ls180.v:5029.83-5029.151"
+ cell $eq $eq$ls180.v:5029$887
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_fifo1
connect \B \main_sdcore_crc16_checker_crctmp1
- connect \Y $eq$ls180.v:4994$887_Y
+ connect \Y $eq$ls180.v:5029$887_Y
end
- attribute \src "ls180.v:4994.157-4994.225"
- cell $eq $eq$ls180.v:4994$889
+ attribute \src "ls180.v:5029.157-5029.225"
+ cell $eq $eq$ls180.v:5029$889
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_fifo2
connect \B \main_sdcore_crc16_checker_crctmp2
- connect \Y $eq$ls180.v:4994$889_Y
+ connect \Y $eq$ls180.v:5029$889_Y
end
- attribute \src "ls180.v:4994.231-4994.299"
- cell $eq $eq$ls180.v:4994$891
+ attribute \src "ls180.v:5029.231-5029.299"
+ cell $eq $eq$ls180.v:5029$891
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_fifo3
connect \B \main_sdcore_crc16_checker_crctmp3
- connect \Y $eq$ls180.v:4994$891_Y
+ connect \Y $eq$ls180.v:5029$891_Y
end
- attribute \src "ls180.v:5002.7-5002.44"
- cell $eq $eq$ls180.v:5002$895
+ attribute \src "ls180.v:5037.7-5037.44"
+ cell $eq $eq$ls180.v:5037$895
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 3'111
- connect \Y $eq$ls180.v:5002$895_Y
+ connect \Y $eq$ls180.v:5037$895_Y
end
- attribute \src "ls180.v:5012.7-5012.44"
- cell $eq $eq$ls180.v:5012$898
+ attribute \src "ls180.v:5047.7-5047.44"
+ cell $eq $eq$ls180.v:5047$898
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 3'111
- connect \Y $eq$ls180.v:5012$898_Y
+ connect \Y $eq$ls180.v:5047$898_Y
end
- attribute \src "ls180.v:5022.7-5022.44"
- cell $eq $eq$ls180.v:5022$901
+ attribute \src "ls180.v:5057.7-5057.44"
+ cell $eq $eq$ls180.v:5057$901
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 3'111
- connect \Y $eq$ls180.v:5022$901_Y
+ connect \Y $eq$ls180.v:5057$901_Y
end
- attribute \src "ls180.v:5032.7-5032.44"
- cell $eq $eq$ls180.v:5032$904
+ attribute \src "ls180.v:5067.7-5067.44"
+ cell $eq $eq$ls180.v:5067$904
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 3'111
- connect \Y $eq$ls180.v:5032$904_Y
+ connect \Y $eq$ls180.v:5067$904_Y
end
- attribute \src "ls180.v:5156.36-5156.64"
- cell $eq $eq$ls180.v:5156$955
+ attribute \src "ls180.v:5191.36-5191.64"
+ cell $eq $eq$ls180.v:5191$955
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_cmd_type
connect \B 1'0
- connect \Y $eq$ls180.v:5156$955_Y
+ connect \Y $eq$ls180.v:5191$955_Y
end
- attribute \src "ls180.v:5162.10-5162.39"
- cell $eq $eq$ls180.v:5162$958
+ attribute \src "ls180.v:5197.10-5197.39"
+ cell $eq $eq$ls180.v:5197$958
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_cmd_count
connect \B 3'101
- connect \Y $eq$ls180.v:5162$958_Y
+ connect \Y $eq$ls180.v:5197$958_Y
end
- attribute \src "ls180.v:5163.11-5163.39"
- cell $eq $eq$ls180.v:5163$959
+ attribute \src "ls180.v:5198.11-5198.39"
+ cell $eq $eq$ls180.v:5198$959
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_cmd_type
connect \B 1'0
- connect \Y $eq$ls180.v:5163$959_Y
+ connect \Y $eq$ls180.v:5198$959_Y
end
- attribute \src "ls180.v:5175.34-5175.63"
- cell $eq $eq$ls180.v:5175$960
+ attribute \src "ls180.v:5210.34-5210.63"
+ cell $eq $eq$ls180.v:5210$960
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_data_type
connect \B 1'0
- connect \Y $eq$ls180.v:5175$960_Y
+ connect \Y $eq$ls180.v:5210$960_Y
end
- attribute \src "ls180.v:5176.9-5176.37"
- cell $eq $eq$ls180.v:5176$961
+ attribute \src "ls180.v:5211.9-5211.37"
+ cell $eq $eq$ls180.v:5211$961
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_cmd_type
connect \B 2'10
- connect \Y $eq$ls180.v:5176$961_Y
+ connect \Y $eq$ls180.v:5211$961_Y
end
- attribute \src "ls180.v:5183.10-5183.55"
- cell $eq $eq$ls180.v:5183$962
+ attribute \src "ls180.v:5218.10-5218.55"
+ cell $eq $eq$ls180.v:5218$962
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_source_payload_status
connect \B 1'1
- connect \Y $eq$ls180.v:5183$962_Y
+ connect \Y $eq$ls180.v:5218$962_Y
end
- attribute \src "ls180.v:5189.12-5189.41"
- cell $eq $eq$ls180.v:5189$963
+ attribute \src "ls180.v:5224.12-5224.41"
+ cell $eq $eq$ls180.v:5224$963
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_data_type
connect \B 2'10
- connect \Y $eq$ls180.v:5189$963_Y
+ connect \Y $eq$ls180.v:5224$963_Y
end
- attribute \src "ls180.v:5192.13-5192.42"
- cell $eq $eq$ls180.v:5192$964
+ attribute \src "ls180.v:5227.13-5227.42"
+ cell $eq $eq$ls180.v:5227$964
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_data_type
connect \B 1'1
- connect \Y $eq$ls180.v:5192$964_Y
+ connect \Y $eq$ls180.v:5227$964_Y
end
- attribute \src "ls180.v:5214.10-5214.76"
- cell $eq $eq$ls180.v:5214$969
+ attribute \src "ls180.v:5249.10-5249.76"
+ cell $eq $eq$ls180.v:5249$969
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_sdcore_data_count
- connect \B $sub$ls180.v:5214$968_Y
- connect \Y $eq$ls180.v:5214$969_Y
+ connect \B $sub$ls180.v:5249$968_Y
+ connect \Y $eq$ls180.v:5249$969_Y
end
- attribute \src "ls180.v:5229.35-5229.101"
- cell $eq $eq$ls180.v:5229$972
+ attribute \src "ls180.v:5264.35-5264.101"
+ cell $eq $eq$ls180.v:5264$972
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_sdcore_data_count
- connect \B $sub$ls180.v:5229$971_Y
- connect \Y $eq$ls180.v:5229$972_Y
+ connect \B $sub$ls180.v:5264$971_Y
+ connect \Y $eq$ls180.v:5264$972_Y
end
- attribute \src "ls180.v:5231.10-5231.56"
- cell $eq $eq$ls180.v:5231$973
+ attribute \src "ls180.v:5266.10-5266.56"
+ cell $eq $eq$ls180.v:5266$973
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_source_payload_status
connect \B 1'0
- connect \Y $eq$ls180.v:5231$973_Y
+ connect \Y $eq$ls180.v:5266$973_Y
end
- attribute \src "ls180.v:5240.12-5240.78"
- cell $eq $eq$ls180.v:5240$977
+ attribute \src "ls180.v:5275.12-5275.78"
+ cell $eq $eq$ls180.v:5275$977
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_sdcore_data_count
- connect \B $sub$ls180.v:5240$976_Y
- connect \Y $eq$ls180.v:5240$977_Y
+ connect \B $sub$ls180.v:5275$976_Y
+ connect \Y $eq$ls180.v:5275$977_Y
end
- attribute \src "ls180.v:5247.11-5247.57"
- cell $eq $eq$ls180.v:5247$978
+ attribute \src "ls180.v:5282.11-5282.57"
+ cell $eq $eq$ls180.v:5282$978
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_source_payload_status
connect \B 1'1
- connect \Y $eq$ls180.v:5247$978_Y
+ connect \Y $eq$ls180.v:5282$978_Y
end
- attribute \src "ls180.v:5364.10-5364.105"
- cell $eq $eq$ls180.v:5364$995
+ attribute \src "ls180.v:5399.10-5399.105"
+ cell $eq $eq$ls180.v:5399$995
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_wishbonedmawriter_offset
- connect \B $sub$ls180.v:5364$994_Y
- connect \Y $eq$ls180.v:5364$995_Y
+ connect \B $sub$ls180.v:5399$994_Y
+ connect \Y $eq$ls180.v:5399$995_Y
end
- attribute \src "ls180.v:5454.39-5454.106"
- cell $eq $eq$ls180.v:5454$1001
+ attribute \src "ls180.v:5489.39-5489.106"
+ cell $eq $eq$ls180.v:5489$1001
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_dma_offset
- connect \B $sub$ls180.v:5454$1000_Y
- connect \Y $eq$ls180.v:5454$1001_Y
+ connect \B $sub$ls180.v:5489$1000_Y
+ connect \Y $eq$ls180.v:5489$1001_Y
end
- attribute \src "ls180.v:5484.44-5484.82"
- cell $eq $eq$ls180.v:5484$1004
+ attribute \src "ls180.v:5519.44-5519.82"
+ cell $eq $eq$ls180.v:5519$1004
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_converter_mux
connect \B 1'0
- connect \Y $eq$ls180.v:5484$1004_Y
+ connect \Y $eq$ls180.v:5519$1004_Y
end
- attribute \src "ls180.v:5485.43-5485.81"
- cell $eq $eq$ls180.v:5485$1005
+ attribute \src "ls180.v:5520.43-5520.81"
+ cell $eq $eq$ls180.v:5520$1005
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_converter_mux
connect \B 2'11
- connect \Y $eq$ls180.v:5485$1005_Y
+ connect \Y $eq$ls180.v:5520$1005_Y
end
- attribute \src "ls180.v:5542.32-5542.99"
- cell $eq $eq$ls180.v:5542$1018
+ attribute \src "ls180.v:5577.32-5577.99"
+ cell $eq $eq$ls180.v:5577$1018
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \libresocsim_clk_divider1
- connect \B $sub$ls180.v:5542$1017_Y
- connect \Y $eq$ls180.v:5542$1018_Y
+ connect \B $sub$ls180.v:5577$1017_Y
+ connect \Y $eq$ls180.v:5577$1018_Y
end
- attribute \src "ls180.v:5543.32-5543.93"
- cell $eq $eq$ls180.v:5543$1020
+ attribute \src "ls180.v:5578.32-5578.93"
+ cell $eq $eq$ls180.v:5578$1020
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \libresocsim_clk_divider1
- connect \B $sub$ls180.v:5543$1019_Y
- connect \Y $eq$ls180.v:5543$1020_Y
+ connect \B $sub$ls180.v:5578$1019_Y
+ connect \Y $eq$ls180.v:5578$1020_Y
end
- attribute \src "ls180.v:5571.10-5571.59"
- cell $eq $eq$ls180.v:5571$1024
+ attribute \src "ls180.v:5606.10-5606.59"
+ cell $eq $eq$ls180.v:5606$1024
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
connect \A \libresocsim_count
- connect \B $sub$ls180.v:5571$1023_Y
- connect \Y $eq$ls180.v:5571$1024_Y
+ connect \B $sub$ls180.v:5606$1023_Y
+ connect \Y $eq$ls180.v:5606$1024_Y
end
- attribute \src "ls180.v:5644.85-5644.106"
- cell $eq $eq$ls180.v:5644$1029
+ attribute \src "ls180.v:5679.85-5679.106"
+ cell $eq $eq$ls180.v:5679$1029
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 1'0
- connect \Y $eq$ls180.v:5644$1029_Y
+ connect \Y $eq$ls180.v:5679$1029_Y
end
- attribute \src "ls180.v:5645.85-5645.106"
- cell $eq $eq$ls180.v:5645$1031
+ attribute \src "ls180.v:5680.85-5680.106"
+ cell $eq $eq$ls180.v:5680$1031
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 1'1
- connect \Y $eq$ls180.v:5645$1031_Y
+ connect \Y $eq$ls180.v:5680$1031_Y
end
- attribute \src "ls180.v:5646.85-5646.106"
- cell $eq $eq$ls180.v:5646$1033
+ attribute \src "ls180.v:5681.85-5681.106"
+ cell $eq $eq$ls180.v:5681$1033
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 2'10
- connect \Y $eq$ls180.v:5646$1033_Y
+ connect \Y $eq$ls180.v:5681$1033_Y
end
- attribute \src "ls180.v:5647.57-5647.78"
- cell $eq $eq$ls180.v:5647$1035
+ attribute \src "ls180.v:5682.57-5682.78"
+ cell $eq $eq$ls180.v:5682$1035
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 2'11
- connect \Y $eq$ls180.v:5647$1035_Y
+ connect \Y $eq$ls180.v:5682$1035_Y
end
- attribute \src "ls180.v:5648.57-5648.78"
- cell $eq $eq$ls180.v:5648$1037
+ attribute \src "ls180.v:5683.57-5683.78"
+ cell $eq $eq$ls180.v:5683$1037
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 3'100
- connect \Y $eq$ls180.v:5648$1037_Y
+ connect \Y $eq$ls180.v:5683$1037_Y
end
- attribute \src "ls180.v:5649.85-5649.106"
- cell $eq $eq$ls180.v:5649$1039
+ attribute \src "ls180.v:5684.85-5684.106"
+ cell $eq $eq$ls180.v:5684$1039
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 1'0
- connect \Y $eq$ls180.v:5649$1039_Y
+ connect \Y $eq$ls180.v:5684$1039_Y
end
- attribute \src "ls180.v:5650.85-5650.106"
- cell $eq $eq$ls180.v:5650$1041
+ attribute \src "ls180.v:5685.85-5685.106"
+ cell $eq $eq$ls180.v:5685$1041
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 1'1
- connect \Y $eq$ls180.v:5650$1041_Y
+ connect \Y $eq$ls180.v:5685$1041_Y
end
- attribute \src "ls180.v:5651.85-5651.106"
- cell $eq $eq$ls180.v:5651$1043
+ attribute \src "ls180.v:5686.85-5686.106"
+ cell $eq $eq$ls180.v:5686$1043
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 2'10
- connect \Y $eq$ls180.v:5651$1043_Y
+ connect \Y $eq$ls180.v:5686$1043_Y
end
- attribute \src "ls180.v:5652.57-5652.78"
- cell $eq $eq$ls180.v:5652$1045
+ attribute \src "ls180.v:5687.57-5687.78"
+ cell $eq $eq$ls180.v:5687$1045
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 2'11
- connect \Y $eq$ls180.v:5652$1045_Y
+ connect \Y $eq$ls180.v:5687$1045_Y
end
- attribute \src "ls180.v:5653.57-5653.78"
- cell $eq $eq$ls180.v:5653$1047
+ attribute \src "ls180.v:5688.57-5688.78"
+ cell $eq $eq$ls180.v:5688$1047
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_grant
connect \B 3'100
- connect \Y $eq$ls180.v:5653$1047_Y
+ connect \Y $eq$ls180.v:5688$1047_Y
end
- attribute \src "ls180.v:5657.27-5657.59"
- cell $eq $eq$ls180.v:5657$1050
+ attribute \src "ls180.v:5692.27-5692.59"
+ cell $eq $eq$ls180.v:5692$1050
parameter \A_SIGNED 0
parameter \A_WIDTH 23
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_adr [29:7]
connect \B 1'0
- connect \Y $eq$ls180.v:5657$1050_Y
+ connect \Y $eq$ls180.v:5692$1050_Y
end
- attribute \src "ls180.v:5658.27-5658.68"
- cell $eq $eq$ls180.v:5658$1051
+ attribute \src "ls180.v:5693.27-5693.68"
+ cell $eq $eq$ls180.v:5693$1051
parameter \A_SIGNED 0
parameter \A_WIDTH 27
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_adr [29:3]
connect \B 27'110000000000000100000000000
- connect \Y $eq$ls180.v:5658$1051_Y
+ connect \Y $eq$ls180.v:5693$1051_Y
end
- attribute \src "ls180.v:5659.27-5659.66"
- cell $eq $eq$ls180.v:5659$1052
+ attribute \src "ls180.v:5694.27-5694.66"
+ cell $eq $eq$ls180.v:5694$1052
parameter \A_SIGNED 0
parameter \A_WIDTH 20
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_adr [29:10]
connect \B 20'11000000000000010001
- connect \Y $eq$ls180.v:5659$1052_Y
+ connect \Y $eq$ls180.v:5694$1052_Y
end
- attribute \src "ls180.v:5660.27-5660.61"
- cell $eq $eq$ls180.v:5660$1053
+ attribute \src "ls180.v:5695.27-5695.61"
+ cell $eq $eq$ls180.v:5695$1053
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_adr [29:23]
connect \B 7'1001000
- connect \Y $eq$ls180.v:5660$1053_Y
+ connect \Y $eq$ls180.v:5695$1053_Y
end
- attribute \src "ls180.v:5661.27-5661.65"
- cell $eq $eq$ls180.v:5661$1054
+ attribute \src "ls180.v:5696.27-5696.65"
+ cell $eq $eq$ls180.v:5696$1054
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_shared_adr [29:14]
connect \B 16'1100000000000000
- connect \Y $eq$ls180.v:5661$1054_Y
+ connect \Y $eq$ls180.v:5696$1054_Y
end
- attribute \src "ls180.v:5717.24-5717.45"
- cell $eq $eq$ls180.v:5717$1081
+ attribute \src "ls180.v:5752.24-5752.45"
+ cell $eq $eq$ls180.v:5752$1081
parameter \A_SIGNED 0
parameter \A_WIDTH 20
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_count
connect \B 1'0
- connect \Y $eq$ls180.v:5717$1081_Y
+ connect \Y $eq$ls180.v:5752$1081_Y
end
- attribute \src "ls180.v:5718.32-5718.77"
- cell $eq $eq$ls180.v:5718$1082
+ attribute \src "ls180.v:5753.32-5753.77"
+ cell $eq $eq$ls180.v:5753$1082
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [13:9]
connect \B 1'0
- connect \Y $eq$ls180.v:5718$1082_Y
+ connect \Y $eq$ls180.v:5753$1082_Y
end
- attribute \src "ls180.v:5720.97-5720.141"
- cell $eq $eq$ls180.v:5720$1084
+ attribute \src "ls180.v:5755.97-5755.141"
+ cell $eq $eq$ls180.v:5755$1084
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5720$1084_Y
+ connect \Y $eq$ls180.v:5755$1084_Y
end
- attribute \src "ls180.v:5721.100-5721.144"
- cell $eq $eq$ls180.v:5721$1088
+ attribute \src "ls180.v:5756.100-5756.144"
+ cell $eq $eq$ls180.v:5756$1088
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5721$1088_Y
+ connect \Y $eq$ls180.v:5756$1088_Y
end
- attribute \src "ls180.v:5723.99-5723.143"
- cell $eq $eq$ls180.v:5723$1091
+ attribute \src "ls180.v:5758.99-5758.143"
+ cell $eq $eq$ls180.v:5758$1091
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5723$1091_Y
+ connect \Y $eq$ls180.v:5758$1091_Y
end
- attribute \src "ls180.v:5724.102-5724.146"
- cell $eq $eq$ls180.v:5724$1095
+ attribute \src "ls180.v:5759.102-5759.146"
+ cell $eq $eq$ls180.v:5759$1095
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5724$1095_Y
+ connect \Y $eq$ls180.v:5759$1095_Y
end
- attribute \src "ls180.v:5726.99-5726.143"
- cell $eq $eq$ls180.v:5726$1098
+ attribute \src "ls180.v:5761.99-5761.143"
+ cell $eq $eq$ls180.v:5761$1098
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5726$1098_Y
+ connect \Y $eq$ls180.v:5761$1098_Y
end
- attribute \src "ls180.v:5727.102-5727.146"
- cell $eq $eq$ls180.v:5727$1102
+ attribute \src "ls180.v:5762.102-5762.146"
+ cell $eq $eq$ls180.v:5762$1102
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5727$1102_Y
+ connect \Y $eq$ls180.v:5762$1102_Y
end
- attribute \src "ls180.v:5729.99-5729.143"
- cell $eq $eq$ls180.v:5729$1105
+ attribute \src "ls180.v:5764.99-5764.143"
+ cell $eq $eq$ls180.v:5764$1105
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5729$1105_Y
+ connect \Y $eq$ls180.v:5764$1105_Y
end
- attribute \src "ls180.v:5730.102-5730.146"
- cell $eq $eq$ls180.v:5730$1109
+ attribute \src "ls180.v:5765.102-5765.146"
+ cell $eq $eq$ls180.v:5765$1109
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5730$1109_Y
+ connect \Y $eq$ls180.v:5765$1109_Y
end
- attribute \src "ls180.v:5732.99-5732.143"
- cell $eq $eq$ls180.v:5732$1112
+ attribute \src "ls180.v:5767.99-5767.143"
+ cell $eq $eq$ls180.v:5767$1112
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5732$1112_Y
+ connect \Y $eq$ls180.v:5767$1112_Y
end
- attribute \src "ls180.v:5733.102-5733.146"
- cell $eq $eq$ls180.v:5733$1116
+ attribute \src "ls180.v:5768.102-5768.146"
+ cell $eq $eq$ls180.v:5768$1116
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5733$1116_Y
+ connect \Y $eq$ls180.v:5768$1116_Y
end
- attribute \src "ls180.v:5735.102-5735.146"
- cell $eq $eq$ls180.v:5735$1119
+ attribute \src "ls180.v:5770.102-5770.146"
+ cell $eq $eq$ls180.v:5770$1119
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5735$1119_Y
+ connect \Y $eq$ls180.v:5770$1119_Y
end
- attribute \src "ls180.v:5736.105-5736.149"
- cell $eq $eq$ls180.v:5736$1123
+ attribute \src "ls180.v:5771.105-5771.149"
+ cell $eq $eq$ls180.v:5771$1123
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5736$1123_Y
+ connect \Y $eq$ls180.v:5771$1123_Y
end
- attribute \src "ls180.v:5738.102-5738.146"
- cell $eq $eq$ls180.v:5738$1126
+ attribute \src "ls180.v:5773.102-5773.146"
+ cell $eq $eq$ls180.v:5773$1126
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5738$1126_Y
+ connect \Y $eq$ls180.v:5773$1126_Y
end
- attribute \src "ls180.v:5739.105-5739.149"
- cell $eq $eq$ls180.v:5739$1130
+ attribute \src "ls180.v:5774.105-5774.149"
+ cell $eq $eq$ls180.v:5774$1130
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5739$1130_Y
+ connect \Y $eq$ls180.v:5774$1130_Y
end
- attribute \src "ls180.v:5741.102-5741.146"
- cell $eq $eq$ls180.v:5741$1133
+ attribute \src "ls180.v:5776.102-5776.146"
+ cell $eq $eq$ls180.v:5776$1133
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5741$1133_Y
+ connect \Y $eq$ls180.v:5776$1133_Y
end
- attribute \src "ls180.v:5742.105-5742.149"
- cell $eq $eq$ls180.v:5742$1137
+ attribute \src "ls180.v:5777.105-5777.149"
+ cell $eq $eq$ls180.v:5777$1137
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5742$1137_Y
+ connect \Y $eq$ls180.v:5777$1137_Y
end
- attribute \src "ls180.v:5744.102-5744.146"
- cell $eq $eq$ls180.v:5744$1140
+ attribute \src "ls180.v:5779.102-5779.146"
+ cell $eq $eq$ls180.v:5779$1140
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5744$1140_Y
+ connect \Y $eq$ls180.v:5779$1140_Y
end
- attribute \src "ls180.v:5745.105-5745.149"
- cell $eq $eq$ls180.v:5745$1144
+ attribute \src "ls180.v:5780.105-5780.149"
+ cell $eq $eq$ls180.v:5780$1144
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5745$1144_Y
+ connect \Y $eq$ls180.v:5780$1144_Y
end
- attribute \src "ls180.v:5756.32-5756.77"
- cell $eq $eq$ls180.v:5756$1146
+ attribute \src "ls180.v:5791.32-5791.77"
+ cell $eq $eq$ls180.v:5791$1146
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [13:9]
connect \B 3'110
- connect \Y $eq$ls180.v:5756$1146_Y
+ connect \Y $eq$ls180.v:5791$1146_Y
end
- attribute \src "ls180.v:5758.94-5758.138"
- cell $eq $eq$ls180.v:5758$1148
+ attribute \src "ls180.v:5793.94-5793.138"
+ cell $eq $eq$ls180.v:5793$1148
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5758$1148_Y
+ connect \Y $eq$ls180.v:5793$1148_Y
end
- attribute \src "ls180.v:5759.97-5759.141"
- cell $eq $eq$ls180.v:5759$1152
+ attribute \src "ls180.v:5794.97-5794.141"
+ cell $eq $eq$ls180.v:5794$1152
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5759$1152_Y
+ connect \Y $eq$ls180.v:5794$1152_Y
end
- attribute \src "ls180.v:5761.94-5761.138"
- cell $eq $eq$ls180.v:5761$1155
+ attribute \src "ls180.v:5796.94-5796.138"
+ cell $eq $eq$ls180.v:5796$1155
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5761$1155_Y
+ connect \Y $eq$ls180.v:5796$1155_Y
end
- attribute \src "ls180.v:5762.97-5762.141"
- cell $eq $eq$ls180.v:5762$1159
+ attribute \src "ls180.v:5797.97-5797.141"
+ cell $eq $eq$ls180.v:5797$1159
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5762$1159_Y
+ connect \Y $eq$ls180.v:5797$1159_Y
end
- attribute \src "ls180.v:5764.94-5764.138"
- cell $eq $eq$ls180.v:5764$1162
+ attribute \src "ls180.v:5799.94-5799.138"
+ cell $eq $eq$ls180.v:5799$1162
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5764$1162_Y
+ connect \Y $eq$ls180.v:5799$1162_Y
end
- attribute \src "ls180.v:5765.97-5765.141"
- cell $eq $eq$ls180.v:5765$1166
+ attribute \src "ls180.v:5800.97-5800.141"
+ cell $eq $eq$ls180.v:5800$1166
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5765$1166_Y
+ connect \Y $eq$ls180.v:5800$1166_Y
end
- attribute \src "ls180.v:5767.94-5767.138"
- cell $eq $eq$ls180.v:5767$1169
+ attribute \src "ls180.v:5802.94-5802.138"
+ cell $eq $eq$ls180.v:5802$1169
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5767$1169_Y
+ connect \Y $eq$ls180.v:5802$1169_Y
end
- attribute \src "ls180.v:5768.97-5768.141"
- cell $eq $eq$ls180.v:5768$1173
+ attribute \src "ls180.v:5803.97-5803.141"
+ cell $eq $eq$ls180.v:5803$1173
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5768$1173_Y
+ connect \Y $eq$ls180.v:5803$1173_Y
end
- attribute \src "ls180.v:5770.95-5770.139"
- cell $eq $eq$ls180.v:5770$1176
+ attribute \src "ls180.v:5805.95-5805.139"
+ cell $eq $eq$ls180.v:5805$1176
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5770$1176_Y
+ connect \Y $eq$ls180.v:5805$1176_Y
end
- attribute \src "ls180.v:5771.98-5771.142"
- cell $eq $eq$ls180.v:5771$1180
+ attribute \src "ls180.v:5806.98-5806.142"
+ cell $eq $eq$ls180.v:5806$1180
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5771$1180_Y
+ connect \Y $eq$ls180.v:5806$1180_Y
end
- attribute \src "ls180.v:5773.95-5773.139"
- cell $eq $eq$ls180.v:5773$1183
+ attribute \src "ls180.v:5808.95-5808.139"
+ cell $eq $eq$ls180.v:5808$1183
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5773$1183_Y
+ connect \Y $eq$ls180.v:5808$1183_Y
end
- attribute \src "ls180.v:5774.98-5774.142"
- cell $eq $eq$ls180.v:5774$1187
+ attribute \src "ls180.v:5809.98-5809.142"
+ cell $eq $eq$ls180.v:5809$1187
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5774$1187_Y
+ connect \Y $eq$ls180.v:5809$1187_Y
end
- attribute \src "ls180.v:5782.32-5782.77"
- cell $eq $eq$ls180.v:5782$1189
+ attribute \src "ls180.v:5817.32-5817.78"
+ cell $eq $eq$ls180.v:5817$1189
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
connect \A \builder_interface2_bank_bus_adr [13:9]
+ connect \B 4'1010
+ connect \Y $eq$ls180.v:5817$1189_Y
+ end
+ attribute \src "ls180.v:5819.93-5819.135"
+ cell $eq $eq$ls180.v:5819$1191
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface2_bank_bus_adr [0]
+ connect \B 1'0
+ connect \Y $eq$ls180.v:5819$1191_Y
+ end
+ attribute \src "ls180.v:5820.96-5820.138"
+ cell $eq $eq$ls180.v:5820$1195
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface2_bank_bus_adr [0]
+ connect \B 1'0
+ connect \Y $eq$ls180.v:5820$1195_Y
+ end
+ attribute \src "ls180.v:5822.92-5822.134"
+ cell $eq $eq$ls180.v:5822$1198
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface2_bank_bus_adr [0]
+ connect \B 1'1
+ connect \Y $eq$ls180.v:5822$1198_Y
+ end
+ attribute \src "ls180.v:5823.95-5823.137"
+ cell $eq $eq$ls180.v:5823$1202
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface2_bank_bus_adr [0]
+ connect \B 1'1
+ connect \Y $eq$ls180.v:5823$1202_Y
+ end
+ attribute \src "ls180.v:5831.32-5831.77"
+ cell $eq $eq$ls180.v:5831$1204
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface3_bank_bus_adr [13:9]
connect \B 4'1000
- connect \Y $eq$ls180.v:5782$1189_Y
+ connect \Y $eq$ls180.v:5831$1204_Y
end
- attribute \src "ls180.v:5784.98-5784.142"
- cell $eq $eq$ls180.v:5784$1191
+ attribute \src "ls180.v:5833.98-5833.142"
+ cell $eq $eq$ls180.v:5833$1206
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5784$1191_Y
+ connect \Y $eq$ls180.v:5833$1206_Y
end
- attribute \src "ls180.v:5785.101-5785.145"
- cell $eq $eq$ls180.v:5785$1195
+ attribute \src "ls180.v:5834.101-5834.145"
+ cell $eq $eq$ls180.v:5834$1210
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5785$1195_Y
+ connect \Y $eq$ls180.v:5834$1210_Y
end
- attribute \src "ls180.v:5787.97-5787.141"
- cell $eq $eq$ls180.v:5787$1198
+ attribute \src "ls180.v:5836.97-5836.141"
+ cell $eq $eq$ls180.v:5836$1213
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5787$1198_Y
+ connect \Y $eq$ls180.v:5836$1213_Y
end
- attribute \src "ls180.v:5788.100-5788.144"
- cell $eq $eq$ls180.v:5788$1202
+ attribute \src "ls180.v:5837.100-5837.144"
+ cell $eq $eq$ls180.v:5837$1217
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5788$1202_Y
+ connect \Y $eq$ls180.v:5837$1217_Y
end
- attribute \src "ls180.v:5790.97-5790.141"
- cell $eq $eq$ls180.v:5790$1205
+ attribute \src "ls180.v:5839.97-5839.141"
+ cell $eq $eq$ls180.v:5839$1220
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5790$1205_Y
+ connect \Y $eq$ls180.v:5839$1220_Y
end
- attribute \src "ls180.v:5791.100-5791.144"
- cell $eq $eq$ls180.v:5791$1209
+ attribute \src "ls180.v:5840.100-5840.144"
+ cell $eq $eq$ls180.v:5840$1224
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5791$1209_Y
+ connect \Y $eq$ls180.v:5840$1224_Y
end
- attribute \src "ls180.v:5793.97-5793.141"
- cell $eq $eq$ls180.v:5793$1212
+ attribute \src "ls180.v:5842.97-5842.141"
+ cell $eq $eq$ls180.v:5842$1227
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5793$1212_Y
+ connect \Y $eq$ls180.v:5842$1227_Y
end
- attribute \src "ls180.v:5794.100-5794.144"
- cell $eq $eq$ls180.v:5794$1216
+ attribute \src "ls180.v:5843.100-5843.144"
+ cell $eq $eq$ls180.v:5843$1231
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5794$1216_Y
+ connect \Y $eq$ls180.v:5843$1231_Y
end
- attribute \src "ls180.v:5796.97-5796.141"
- cell $eq $eq$ls180.v:5796$1219
+ attribute \src "ls180.v:5845.97-5845.141"
+ cell $eq $eq$ls180.v:5845$1234
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5796$1219_Y
+ connect \Y $eq$ls180.v:5845$1234_Y
end
- attribute \src "ls180.v:5797.100-5797.144"
- cell $eq $eq$ls180.v:5797$1223
+ attribute \src "ls180.v:5846.100-5846.144"
+ cell $eq $eq$ls180.v:5846$1238
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5797$1223_Y
+ connect \Y $eq$ls180.v:5846$1238_Y
end
- attribute \src "ls180.v:5799.98-5799.142"
- cell $eq $eq$ls180.v:5799$1226
+ attribute \src "ls180.v:5848.98-5848.142"
+ cell $eq $eq$ls180.v:5848$1241
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5799$1226_Y
+ connect \Y $eq$ls180.v:5848$1241_Y
end
- attribute \src "ls180.v:5800.101-5800.145"
- cell $eq $eq$ls180.v:5800$1230
+ attribute \src "ls180.v:5849.101-5849.145"
+ cell $eq $eq$ls180.v:5849$1245
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5800$1230_Y
+ connect \Y $eq$ls180.v:5849$1245_Y
end
- attribute \src "ls180.v:5802.98-5802.142"
- cell $eq $eq$ls180.v:5802$1233
+ attribute \src "ls180.v:5851.98-5851.142"
+ cell $eq $eq$ls180.v:5851$1248
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5802$1233_Y
+ connect \Y $eq$ls180.v:5851$1248_Y
end
- attribute \src "ls180.v:5803.101-5803.145"
- cell $eq $eq$ls180.v:5803$1237
+ attribute \src "ls180.v:5852.101-5852.145"
+ cell $eq $eq$ls180.v:5852$1252
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5803$1237_Y
+ connect \Y $eq$ls180.v:5852$1252_Y
end
- attribute \src "ls180.v:5805.98-5805.142"
- cell $eq $eq$ls180.v:5805$1240
+ attribute \src "ls180.v:5854.98-5854.142"
+ cell $eq $eq$ls180.v:5854$1255
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5805$1240_Y
+ connect \Y $eq$ls180.v:5854$1255_Y
end
- attribute \src "ls180.v:5806.101-5806.145"
- cell $eq $eq$ls180.v:5806$1244
+ attribute \src "ls180.v:5855.101-5855.145"
+ cell $eq $eq$ls180.v:5855$1259
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5806$1244_Y
+ connect \Y $eq$ls180.v:5855$1259_Y
end
- attribute \src "ls180.v:5808.98-5808.142"
- cell $eq $eq$ls180.v:5808$1247
+ attribute \src "ls180.v:5857.98-5857.142"
+ cell $eq $eq$ls180.v:5857$1262
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5808$1247_Y
+ connect \Y $eq$ls180.v:5857$1262_Y
end
- attribute \src "ls180.v:5809.101-5809.145"
- cell $eq $eq$ls180.v:5809$1251
+ attribute \src "ls180.v:5858.101-5858.145"
+ cell $eq $eq$ls180.v:5858$1266
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_adr [3:0]
+ connect \A \builder_interface3_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5809$1251_Y
+ connect \Y $eq$ls180.v:5858$1266_Y
end
- attribute \src "ls180.v:5819.32-5819.77"
- cell $eq $eq$ls180.v:5819$1253
+ attribute \src "ls180.v:5868.32-5868.77"
+ cell $eq $eq$ls180.v:5868$1268
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [13:9]
+ connect \A \builder_interface4_bank_bus_adr [13:9]
connect \B 4'1001
- connect \Y $eq$ls180.v:5819$1253_Y
+ connect \Y $eq$ls180.v:5868$1268_Y
end
- attribute \src "ls180.v:5821.98-5821.142"
- cell $eq $eq$ls180.v:5821$1255
+ attribute \src "ls180.v:5870.98-5870.142"
+ cell $eq $eq$ls180.v:5870$1270
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5821$1255_Y
+ connect \Y $eq$ls180.v:5870$1270_Y
end
- attribute \src "ls180.v:5822.101-5822.145"
- cell $eq $eq$ls180.v:5822$1259
+ attribute \src "ls180.v:5871.101-5871.145"
+ cell $eq $eq$ls180.v:5871$1274
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5822$1259_Y
+ connect \Y $eq$ls180.v:5871$1274_Y
end
- attribute \src "ls180.v:5824.97-5824.141"
- cell $eq $eq$ls180.v:5824$1262
+ attribute \src "ls180.v:5873.97-5873.141"
+ cell $eq $eq$ls180.v:5873$1277
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5824$1262_Y
+ connect \Y $eq$ls180.v:5873$1277_Y
end
- attribute \src "ls180.v:5825.100-5825.144"
- cell $eq $eq$ls180.v:5825$1266
+ attribute \src "ls180.v:5874.100-5874.144"
+ cell $eq $eq$ls180.v:5874$1281
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5825$1266_Y
+ connect \Y $eq$ls180.v:5874$1281_Y
end
- attribute \src "ls180.v:5827.97-5827.141"
- cell $eq $eq$ls180.v:5827$1269
+ attribute \src "ls180.v:5876.97-5876.141"
+ cell $eq $eq$ls180.v:5876$1284
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5827$1269_Y
+ connect \Y $eq$ls180.v:5876$1284_Y
end
- attribute \src "ls180.v:5828.100-5828.144"
- cell $eq $eq$ls180.v:5828$1273
+ attribute \src "ls180.v:5877.100-5877.144"
+ cell $eq $eq$ls180.v:5877$1288
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5828$1273_Y
+ connect \Y $eq$ls180.v:5877$1288_Y
end
- attribute \src "ls180.v:5830.97-5830.141"
- cell $eq $eq$ls180.v:5830$1276
+ attribute \src "ls180.v:5879.97-5879.141"
+ cell $eq $eq$ls180.v:5879$1291
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5830$1276_Y
+ connect \Y $eq$ls180.v:5879$1291_Y
end
- attribute \src "ls180.v:5831.100-5831.144"
- cell $eq $eq$ls180.v:5831$1280
+ attribute \src "ls180.v:5880.100-5880.144"
+ cell $eq $eq$ls180.v:5880$1295
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5831$1280_Y
+ connect \Y $eq$ls180.v:5880$1295_Y
end
- attribute \src "ls180.v:5833.97-5833.141"
- cell $eq $eq$ls180.v:5833$1283
+ attribute \src "ls180.v:5882.97-5882.141"
+ cell $eq $eq$ls180.v:5882$1298
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5833$1283_Y
+ connect \Y $eq$ls180.v:5882$1298_Y
end
- attribute \src "ls180.v:5834.100-5834.144"
- cell $eq $eq$ls180.v:5834$1287
+ attribute \src "ls180.v:5883.100-5883.144"
+ cell $eq $eq$ls180.v:5883$1302
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5834$1287_Y
+ connect \Y $eq$ls180.v:5883$1302_Y
end
- attribute \src "ls180.v:5836.98-5836.142"
- cell $eq $eq$ls180.v:5836$1290
+ attribute \src "ls180.v:5885.98-5885.142"
+ cell $eq $eq$ls180.v:5885$1305
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5836$1290_Y
+ connect \Y $eq$ls180.v:5885$1305_Y
end
- attribute \src "ls180.v:5837.101-5837.145"
- cell $eq $eq$ls180.v:5837$1294
+ attribute \src "ls180.v:5886.101-5886.145"
+ cell $eq $eq$ls180.v:5886$1309
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5837$1294_Y
+ connect \Y $eq$ls180.v:5886$1309_Y
end
- attribute \src "ls180.v:5839.98-5839.142"
- cell $eq $eq$ls180.v:5839$1297
+ attribute \src "ls180.v:5888.98-5888.142"
+ cell $eq $eq$ls180.v:5888$1312
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5839$1297_Y
+ connect \Y $eq$ls180.v:5888$1312_Y
end
- attribute \src "ls180.v:5840.101-5840.145"
- cell $eq $eq$ls180.v:5840$1301
+ attribute \src "ls180.v:5889.101-5889.145"
+ cell $eq $eq$ls180.v:5889$1316
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5840$1301_Y
+ connect \Y $eq$ls180.v:5889$1316_Y
end
- attribute \src "ls180.v:5842.98-5842.142"
- cell $eq $eq$ls180.v:5842$1304
+ attribute \src "ls180.v:5891.98-5891.142"
+ cell $eq $eq$ls180.v:5891$1319
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5842$1304_Y
+ connect \Y $eq$ls180.v:5891$1319_Y
end
- attribute \src "ls180.v:5843.101-5843.145"
- cell $eq $eq$ls180.v:5843$1308
+ attribute \src "ls180.v:5892.101-5892.145"
+ cell $eq $eq$ls180.v:5892$1323
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5843$1308_Y
+ connect \Y $eq$ls180.v:5892$1323_Y
end
- attribute \src "ls180.v:5845.98-5845.142"
- cell $eq $eq$ls180.v:5845$1311
+ attribute \src "ls180.v:5894.98-5894.142"
+ cell $eq $eq$ls180.v:5894$1326
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5845$1311_Y
+ connect \Y $eq$ls180.v:5894$1326_Y
end
- attribute \src "ls180.v:5846.101-5846.145"
- cell $eq $eq$ls180.v:5846$1315
+ attribute \src "ls180.v:5895.101-5895.145"
+ cell $eq $eq$ls180.v:5895$1330
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_adr [3:0]
+ connect \A \builder_interface4_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5846$1315_Y
+ connect \Y $eq$ls180.v:5895$1330_Y
end
- attribute \src "ls180.v:5856.32-5856.78"
- cell $eq $eq$ls180.v:5856$1317
+ attribute \src "ls180.v:5905.32-5905.78"
+ cell $eq $eq$ls180.v:5905$1332
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [13:9]
- connect \B 4'1100
- connect \Y $eq$ls180.v:5856$1317_Y
+ connect \A \builder_interface5_bank_bus_adr [13:9]
+ connect \B 4'1101
+ connect \Y $eq$ls180.v:5905$1332_Y
end
- attribute \src "ls180.v:5858.100-5858.144"
- cell $eq $eq$ls180.v:5858$1319
+ attribute \src "ls180.v:5907.100-5907.144"
+ cell $eq $eq$ls180.v:5907$1334
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5858$1319_Y
+ connect \Y $eq$ls180.v:5907$1334_Y
end
- attribute \src "ls180.v:5859.103-5859.147"
- cell $eq $eq$ls180.v:5859$1323
+ attribute \src "ls180.v:5908.103-5908.147"
+ cell $eq $eq$ls180.v:5908$1338
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5859$1323_Y
+ connect \Y $eq$ls180.v:5908$1338_Y
end
- attribute \src "ls180.v:5861.100-5861.144"
- cell $eq $eq$ls180.v:5861$1326
+ attribute \src "ls180.v:5910.100-5910.144"
+ cell $eq $eq$ls180.v:5910$1341
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5861$1326_Y
+ connect \Y $eq$ls180.v:5910$1341_Y
end
- attribute \src "ls180.v:5862.103-5862.147"
- cell $eq $eq$ls180.v:5862$1330
+ attribute \src "ls180.v:5911.103-5911.147"
+ cell $eq $eq$ls180.v:5911$1345
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5862$1330_Y
+ connect \Y $eq$ls180.v:5911$1345_Y
end
- attribute \src "ls180.v:5864.100-5864.144"
- cell $eq $eq$ls180.v:5864$1333
+ attribute \src "ls180.v:5913.100-5913.144"
+ cell $eq $eq$ls180.v:5913$1348
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5864$1333_Y
+ connect \Y $eq$ls180.v:5913$1348_Y
end
- attribute \src "ls180.v:5865.103-5865.147"
- cell $eq $eq$ls180.v:5865$1337
+ attribute \src "ls180.v:5914.103-5914.147"
+ cell $eq $eq$ls180.v:5914$1352
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5865$1337_Y
+ connect \Y $eq$ls180.v:5914$1352_Y
end
- attribute \src "ls180.v:5867.100-5867.144"
- cell $eq $eq$ls180.v:5867$1340
+ attribute \src "ls180.v:5916.100-5916.144"
+ cell $eq $eq$ls180.v:5916$1355
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5867$1340_Y
+ connect \Y $eq$ls180.v:5916$1355_Y
end
- attribute \src "ls180.v:5868.103-5868.147"
- cell $eq $eq$ls180.v:5868$1344
+ attribute \src "ls180.v:5917.103-5917.147"
+ cell $eq $eq$ls180.v:5917$1359
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5868$1344_Y
+ connect \Y $eq$ls180.v:5917$1359_Y
end
- attribute \src "ls180.v:5870.100-5870.144"
- cell $eq $eq$ls180.v:5870$1347
+ attribute \src "ls180.v:5919.100-5919.144"
+ cell $eq $eq$ls180.v:5919$1362
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5870$1347_Y
+ connect \Y $eq$ls180.v:5919$1362_Y
end
- attribute \src "ls180.v:5871.103-5871.147"
- cell $eq $eq$ls180.v:5871$1351
+ attribute \src "ls180.v:5920.103-5920.147"
+ cell $eq $eq$ls180.v:5920$1366
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5871$1351_Y
+ connect \Y $eq$ls180.v:5920$1366_Y
end
- attribute \src "ls180.v:5873.100-5873.144"
- cell $eq $eq$ls180.v:5873$1354
+ attribute \src "ls180.v:5922.100-5922.144"
+ cell $eq $eq$ls180.v:5922$1369
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5873$1354_Y
+ connect \Y $eq$ls180.v:5922$1369_Y
end
- attribute \src "ls180.v:5874.103-5874.147"
- cell $eq $eq$ls180.v:5874$1358
+ attribute \src "ls180.v:5923.103-5923.147"
+ cell $eq $eq$ls180.v:5923$1373
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5874$1358_Y
+ connect \Y $eq$ls180.v:5923$1373_Y
end
- attribute \src "ls180.v:5876.100-5876.144"
- cell $eq $eq$ls180.v:5876$1361
+ attribute \src "ls180.v:5925.100-5925.144"
+ cell $eq $eq$ls180.v:5925$1376
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5876$1361_Y
+ connect \Y $eq$ls180.v:5925$1376_Y
end
- attribute \src "ls180.v:5877.103-5877.147"
- cell $eq $eq$ls180.v:5877$1365
+ attribute \src "ls180.v:5926.103-5926.147"
+ cell $eq $eq$ls180.v:5926$1380
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5877$1365_Y
+ connect \Y $eq$ls180.v:5926$1380_Y
end
- attribute \src "ls180.v:5879.100-5879.144"
- cell $eq $eq$ls180.v:5879$1368
+ attribute \src "ls180.v:5928.100-5928.144"
+ cell $eq $eq$ls180.v:5928$1383
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5879$1368_Y
+ connect \Y $eq$ls180.v:5928$1383_Y
end
- attribute \src "ls180.v:5880.103-5880.147"
- cell $eq $eq$ls180.v:5880$1372
+ attribute \src "ls180.v:5929.103-5929.147"
+ cell $eq $eq$ls180.v:5929$1387
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5880$1372_Y
+ connect \Y $eq$ls180.v:5929$1387_Y
end
- attribute \src "ls180.v:5882.102-5882.146"
- cell $eq $eq$ls180.v:5882$1375
+ attribute \src "ls180.v:5931.102-5931.146"
+ cell $eq $eq$ls180.v:5931$1390
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5882$1375_Y
+ connect \Y $eq$ls180.v:5931$1390_Y
end
- attribute \src "ls180.v:5883.105-5883.149"
- cell $eq $eq$ls180.v:5883$1379
+ attribute \src "ls180.v:5932.105-5932.149"
+ cell $eq $eq$ls180.v:5932$1394
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5883$1379_Y
+ connect \Y $eq$ls180.v:5932$1394_Y
end
- attribute \src "ls180.v:5885.102-5885.146"
- cell $eq $eq$ls180.v:5885$1382
+ attribute \src "ls180.v:5934.102-5934.146"
+ cell $eq $eq$ls180.v:5934$1397
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:5885$1382_Y
+ connect \Y $eq$ls180.v:5934$1397_Y
end
- attribute \src "ls180.v:5886.105-5886.149"
- cell $eq $eq$ls180.v:5886$1386
+ attribute \src "ls180.v:5935.105-5935.149"
+ cell $eq $eq$ls180.v:5935$1401
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:5886$1386_Y
+ connect \Y $eq$ls180.v:5935$1401_Y
end
- attribute \src "ls180.v:5888.102-5888.147"
- cell $eq $eq$ls180.v:5888$1389
+ attribute \src "ls180.v:5937.102-5937.147"
+ cell $eq $eq$ls180.v:5937$1404
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:5888$1389_Y
+ connect \Y $eq$ls180.v:5937$1404_Y
end
- attribute \src "ls180.v:5889.105-5889.150"
- cell $eq $eq$ls180.v:5889$1393
+ attribute \src "ls180.v:5938.105-5938.150"
+ cell $eq $eq$ls180.v:5938$1408
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:5889$1393_Y
+ connect \Y $eq$ls180.v:5938$1408_Y
end
- attribute \src "ls180.v:5891.102-5891.147"
- cell $eq $eq$ls180.v:5891$1396
+ attribute \src "ls180.v:5940.102-5940.147"
+ cell $eq $eq$ls180.v:5940$1411
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:5891$1396_Y
+ connect \Y $eq$ls180.v:5940$1411_Y
end
- attribute \src "ls180.v:5892.105-5892.150"
- cell $eq $eq$ls180.v:5892$1400
+ attribute \src "ls180.v:5941.105-5941.150"
+ cell $eq $eq$ls180.v:5941$1415
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:5892$1400_Y
+ connect \Y $eq$ls180.v:5941$1415_Y
end
- attribute \src "ls180.v:5894.102-5894.147"
- cell $eq $eq$ls180.v:5894$1403
+ attribute \src "ls180.v:5943.102-5943.147"
+ cell $eq $eq$ls180.v:5943$1418
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:5894$1403_Y
+ connect \Y $eq$ls180.v:5943$1418_Y
end
- attribute \src "ls180.v:5895.105-5895.150"
- cell $eq $eq$ls180.v:5895$1407
+ attribute \src "ls180.v:5944.105-5944.150"
+ cell $eq $eq$ls180.v:5944$1422
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:5895$1407_Y
+ connect \Y $eq$ls180.v:5944$1422_Y
end
- attribute \src "ls180.v:5897.99-5897.144"
- cell $eq $eq$ls180.v:5897$1410
+ attribute \src "ls180.v:5946.99-5946.144"
+ cell $eq $eq$ls180.v:5946$1425
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:5897$1410_Y
+ connect \Y $eq$ls180.v:5946$1425_Y
end
- attribute \src "ls180.v:5898.102-5898.147"
- cell $eq $eq$ls180.v:5898$1414
+ attribute \src "ls180.v:5947.102-5947.147"
+ cell $eq $eq$ls180.v:5947$1429
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:5898$1414_Y
+ connect \Y $eq$ls180.v:5947$1429_Y
end
- attribute \src "ls180.v:5900.100-5900.145"
- cell $eq $eq$ls180.v:5900$1417
+ attribute \src "ls180.v:5949.100-5949.145"
+ cell $eq $eq$ls180.v:5949$1432
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:5900$1417_Y
+ connect \Y $eq$ls180.v:5949$1432_Y
end
- attribute \src "ls180.v:5901.103-5901.148"
- cell $eq $eq$ls180.v:5901$1421
+ attribute \src "ls180.v:5950.103-5950.148"
+ cell $eq $eq$ls180.v:5950$1436
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_adr [3:0]
+ connect \A \builder_interface5_bank_bus_adr [3:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:5901$1421_Y
+ connect \Y $eq$ls180.v:5950$1436_Y
end
- attribute \src "ls180.v:5918.32-5918.78"
- cell $eq $eq$ls180.v:5918$1423
+ attribute \src "ls180.v:5967.32-5967.78"
+ cell $eq $eq$ls180.v:5967$1438
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [13:9]
- connect \B 4'1011
- connect \Y $eq$ls180.v:5918$1423_Y
+ connect \A \builder_interface6_bank_bus_adr [13:9]
+ connect \B 4'1100
+ connect \Y $eq$ls180.v:5967$1438_Y
end
- attribute \src "ls180.v:5920.104-5920.148"
- cell $eq $eq$ls180.v:5920$1425
+ attribute \src "ls180.v:5969.104-5969.148"
+ cell $eq $eq$ls180.v:5969$1440
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5920$1425_Y
+ connect \Y $eq$ls180.v:5969$1440_Y
end
- attribute \src "ls180.v:5921.107-5921.151"
- cell $eq $eq$ls180.v:5921$1429
+ attribute \src "ls180.v:5970.107-5970.151"
+ cell $eq $eq$ls180.v:5970$1444
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 1'0
- connect \Y $eq$ls180.v:5921$1429_Y
+ connect \Y $eq$ls180.v:5970$1444_Y
end
- attribute \src "ls180.v:5923.104-5923.148"
- cell $eq $eq$ls180.v:5923$1432
+ attribute \src "ls180.v:5972.104-5972.148"
+ cell $eq $eq$ls180.v:5972$1447
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5923$1432_Y
+ connect \Y $eq$ls180.v:5972$1447_Y
end
- attribute \src "ls180.v:5924.107-5924.151"
- cell $eq $eq$ls180.v:5924$1436
+ attribute \src "ls180.v:5973.107-5973.151"
+ cell $eq $eq$ls180.v:5973$1451
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 1'1
- connect \Y $eq$ls180.v:5924$1436_Y
+ connect \Y $eq$ls180.v:5973$1451_Y
end
- attribute \src "ls180.v:5926.104-5926.148"
- cell $eq $eq$ls180.v:5926$1439
+ attribute \src "ls180.v:5975.104-5975.148"
+ cell $eq $eq$ls180.v:5975$1454
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5926$1439_Y
+ connect \Y $eq$ls180.v:5975$1454_Y
end
- attribute \src "ls180.v:5927.107-5927.151"
- cell $eq $eq$ls180.v:5927$1443
+ attribute \src "ls180.v:5976.107-5976.151"
+ cell $eq $eq$ls180.v:5976$1458
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 2'10
- connect \Y $eq$ls180.v:5927$1443_Y
+ connect \Y $eq$ls180.v:5976$1458_Y
end
- attribute \src "ls180.v:5929.104-5929.148"
- cell $eq $eq$ls180.v:5929$1446
+ attribute \src "ls180.v:5978.104-5978.148"
+ cell $eq $eq$ls180.v:5978$1461
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5929$1446_Y
+ connect \Y $eq$ls180.v:5978$1461_Y
end
- attribute \src "ls180.v:5930.107-5930.151"
- cell $eq $eq$ls180.v:5930$1450
+ attribute \src "ls180.v:5979.107-5979.151"
+ cell $eq $eq$ls180.v:5979$1465
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 2'11
- connect \Y $eq$ls180.v:5930$1450_Y
+ connect \Y $eq$ls180.v:5979$1465_Y
end
- attribute \src "ls180.v:5932.103-5932.147"
- cell $eq $eq$ls180.v:5932$1453
+ attribute \src "ls180.v:5981.103-5981.147"
+ cell $eq $eq$ls180.v:5981$1468
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5932$1453_Y
+ connect \Y $eq$ls180.v:5981$1468_Y
end
- attribute \src "ls180.v:5933.106-5933.150"
- cell $eq $eq$ls180.v:5933$1457
+ attribute \src "ls180.v:5982.106-5982.150"
+ cell $eq $eq$ls180.v:5982$1472
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'100
- connect \Y $eq$ls180.v:5933$1457_Y
+ connect \Y $eq$ls180.v:5982$1472_Y
end
- attribute \src "ls180.v:5935.103-5935.147"
- cell $eq $eq$ls180.v:5935$1460
+ attribute \src "ls180.v:5984.103-5984.147"
+ cell $eq $eq$ls180.v:5984$1475
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5935$1460_Y
+ connect \Y $eq$ls180.v:5984$1475_Y
end
- attribute \src "ls180.v:5936.106-5936.150"
- cell $eq $eq$ls180.v:5936$1464
+ attribute \src "ls180.v:5985.106-5985.150"
+ cell $eq $eq$ls180.v:5985$1479
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'101
- connect \Y $eq$ls180.v:5936$1464_Y
+ connect \Y $eq$ls180.v:5985$1479_Y
end
- attribute \src "ls180.v:5938.103-5938.147"
- cell $eq $eq$ls180.v:5938$1467
+ attribute \src "ls180.v:5987.103-5987.147"
+ cell $eq $eq$ls180.v:5987$1482
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5938$1467_Y
+ connect \Y $eq$ls180.v:5987$1482_Y
end
- attribute \src "ls180.v:5939.106-5939.150"
- cell $eq $eq$ls180.v:5939$1471
+ attribute \src "ls180.v:5988.106-5988.150"
+ cell $eq $eq$ls180.v:5988$1486
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'110
- connect \Y $eq$ls180.v:5939$1471_Y
+ connect \Y $eq$ls180.v:5988$1486_Y
end
- attribute \src "ls180.v:5941.103-5941.147"
- cell $eq $eq$ls180.v:5941$1474
+ attribute \src "ls180.v:5990.103-5990.147"
+ cell $eq $eq$ls180.v:5990$1489
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5941$1474_Y
+ connect \Y $eq$ls180.v:5990$1489_Y
end
- attribute \src "ls180.v:5942.106-5942.150"
- cell $eq $eq$ls180.v:5942$1478
+ attribute \src "ls180.v:5991.106-5991.150"
+ cell $eq $eq$ls180.v:5991$1493
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 3'111
- connect \Y $eq$ls180.v:5942$1478_Y
+ connect \Y $eq$ls180.v:5991$1493_Y
end
- attribute \src "ls180.v:5944.94-5944.138"
- cell $eq $eq$ls180.v:5944$1481
+ attribute \src "ls180.v:5993.94-5993.138"
+ cell $eq $eq$ls180.v:5993$1496
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5944$1481_Y
+ connect \Y $eq$ls180.v:5993$1496_Y
end
- attribute \src "ls180.v:5945.97-5945.141"
- cell $eq $eq$ls180.v:5945$1485
+ attribute \src "ls180.v:5994.97-5994.141"
+ cell $eq $eq$ls180.v:5994$1500
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:5945$1485_Y
+ connect \Y $eq$ls180.v:5994$1500_Y
end
- attribute \src "ls180.v:5947.105-5947.149"
- cell $eq $eq$ls180.v:5947$1488
+ attribute \src "ls180.v:5996.105-5996.149"
+ cell $eq $eq$ls180.v:5996$1503
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:5947$1488_Y
+ connect \Y $eq$ls180.v:5996$1503_Y
end
- attribute \src "ls180.v:5948.108-5948.152"
- cell $eq $eq$ls180.v:5948$1492
+ attribute \src "ls180.v:5997.108-5997.152"
+ cell $eq $eq$ls180.v:5997$1507
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:5948$1492_Y
+ connect \Y $eq$ls180.v:5997$1507_Y
end
- attribute \src "ls180.v:5950.105-5950.150"
- cell $eq $eq$ls180.v:5950$1495
+ attribute \src "ls180.v:5999.105-5999.150"
+ cell $eq $eq$ls180.v:5999$1510
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:5950$1495_Y
+ connect \Y $eq$ls180.v:5999$1510_Y
end
- attribute \src "ls180.v:5951.108-5951.153"
- cell $eq $eq$ls180.v:5951$1499
+ attribute \src "ls180.v:6000.108-6000.153"
+ cell $eq $eq$ls180.v:6000$1514
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:5951$1499_Y
+ connect \Y $eq$ls180.v:6000$1514_Y
end
- attribute \src "ls180.v:5953.105-5953.150"
- cell $eq $eq$ls180.v:5953$1502
+ attribute \src "ls180.v:6002.105-6002.150"
+ cell $eq $eq$ls180.v:6002$1517
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:5953$1502_Y
+ connect \Y $eq$ls180.v:6002$1517_Y
end
- attribute \src "ls180.v:5954.108-5954.153"
- cell $eq $eq$ls180.v:5954$1506
+ attribute \src "ls180.v:6003.108-6003.153"
+ cell $eq $eq$ls180.v:6003$1521
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:5954$1506_Y
+ connect \Y $eq$ls180.v:6003$1521_Y
end
- attribute \src "ls180.v:5956.105-5956.150"
- cell $eq $eq$ls180.v:5956$1509
+ attribute \src "ls180.v:6005.105-6005.150"
+ cell $eq $eq$ls180.v:6005$1524
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:5956$1509_Y
+ connect \Y $eq$ls180.v:6005$1524_Y
end
- attribute \src "ls180.v:5957.108-5957.153"
- cell $eq $eq$ls180.v:5957$1513
+ attribute \src "ls180.v:6006.108-6006.153"
+ cell $eq $eq$ls180.v:6006$1528
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:5957$1513_Y
+ connect \Y $eq$ls180.v:6006$1528_Y
end
- attribute \src "ls180.v:5959.105-5959.150"
- cell $eq $eq$ls180.v:5959$1516
+ attribute \src "ls180.v:6008.105-6008.150"
+ cell $eq $eq$ls180.v:6008$1531
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:5959$1516_Y
+ connect \Y $eq$ls180.v:6008$1531_Y
end
- attribute \src "ls180.v:5960.108-5960.153"
- cell $eq $eq$ls180.v:5960$1520
+ attribute \src "ls180.v:6009.108-6009.153"
+ cell $eq $eq$ls180.v:6009$1535
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:5960$1520_Y
+ connect \Y $eq$ls180.v:6009$1535_Y
end
- attribute \src "ls180.v:5962.105-5962.150"
- cell $eq $eq$ls180.v:5962$1523
+ attribute \src "ls180.v:6011.105-6011.150"
+ cell $eq $eq$ls180.v:6011$1538
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:5962$1523_Y
+ connect \Y $eq$ls180.v:6011$1538_Y
end
- attribute \src "ls180.v:5963.108-5963.153"
- cell $eq $eq$ls180.v:5963$1527
+ attribute \src "ls180.v:6012.108-6012.153"
+ cell $eq $eq$ls180.v:6012$1542
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:5963$1527_Y
+ connect \Y $eq$ls180.v:6012$1542_Y
end
- attribute \src "ls180.v:5965.104-5965.149"
- cell $eq $eq$ls180.v:5965$1530
+ attribute \src "ls180.v:6014.104-6014.149"
+ cell $eq $eq$ls180.v:6014$1545
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:5965$1530_Y
+ connect \Y $eq$ls180.v:6014$1545_Y
end
- attribute \src "ls180.v:5966.107-5966.152"
- cell $eq $eq$ls180.v:5966$1534
+ attribute \src "ls180.v:6015.107-6015.152"
+ cell $eq $eq$ls180.v:6015$1549
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:5966$1534_Y
+ connect \Y $eq$ls180.v:6015$1549_Y
end
- attribute \src "ls180.v:5968.104-5968.149"
- cell $eq $eq$ls180.v:5968$1537
+ attribute \src "ls180.v:6017.104-6017.149"
+ cell $eq $eq$ls180.v:6017$1552
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:5968$1537_Y
+ connect \Y $eq$ls180.v:6017$1552_Y
end
- attribute \src "ls180.v:5969.107-5969.152"
- cell $eq $eq$ls180.v:5969$1541
+ attribute \src "ls180.v:6018.107-6018.152"
+ cell $eq $eq$ls180.v:6018$1556
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:5969$1541_Y
+ connect \Y $eq$ls180.v:6018$1556_Y
end
- attribute \src "ls180.v:5971.104-5971.149"
- cell $eq $eq$ls180.v:5971$1544
+ attribute \src "ls180.v:6020.104-6020.149"
+ cell $eq $eq$ls180.v:6020$1559
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10001
- connect \Y $eq$ls180.v:5971$1544_Y
+ connect \Y $eq$ls180.v:6020$1559_Y
end
- attribute \src "ls180.v:5972.107-5972.152"
- cell $eq $eq$ls180.v:5972$1548
+ attribute \src "ls180.v:6021.107-6021.152"
+ cell $eq $eq$ls180.v:6021$1563
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10001
- connect \Y $eq$ls180.v:5972$1548_Y
+ connect \Y $eq$ls180.v:6021$1563_Y
end
- attribute \src "ls180.v:5974.104-5974.149"
- cell $eq $eq$ls180.v:5974$1551
+ attribute \src "ls180.v:6023.104-6023.149"
+ cell $eq $eq$ls180.v:6023$1566
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10010
- connect \Y $eq$ls180.v:5974$1551_Y
+ connect \Y $eq$ls180.v:6023$1566_Y
end
- attribute \src "ls180.v:5975.107-5975.152"
- cell $eq $eq$ls180.v:5975$1555
+ attribute \src "ls180.v:6024.107-6024.152"
+ cell $eq $eq$ls180.v:6024$1570
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10010
- connect \Y $eq$ls180.v:5975$1555_Y
+ connect \Y $eq$ls180.v:6024$1570_Y
end
- attribute \src "ls180.v:5977.104-5977.149"
- cell $eq $eq$ls180.v:5977$1558
+ attribute \src "ls180.v:6026.104-6026.149"
+ cell $eq $eq$ls180.v:6026$1573
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10011
- connect \Y $eq$ls180.v:5977$1558_Y
+ connect \Y $eq$ls180.v:6026$1573_Y
end
- attribute \src "ls180.v:5978.107-5978.152"
- cell $eq $eq$ls180.v:5978$1562
+ attribute \src "ls180.v:6027.107-6027.152"
+ cell $eq $eq$ls180.v:6027$1577
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10011
- connect \Y $eq$ls180.v:5978$1562_Y
+ connect \Y $eq$ls180.v:6027$1577_Y
end
- attribute \src "ls180.v:5980.104-5980.149"
- cell $eq $eq$ls180.v:5980$1565
+ attribute \src "ls180.v:6029.104-6029.149"
+ cell $eq $eq$ls180.v:6029$1580
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10100
- connect \Y $eq$ls180.v:5980$1565_Y
+ connect \Y $eq$ls180.v:6029$1580_Y
end
- attribute \src "ls180.v:5981.107-5981.152"
- cell $eq $eq$ls180.v:5981$1569
+ attribute \src "ls180.v:6030.107-6030.152"
+ cell $eq $eq$ls180.v:6030$1584
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10100
- connect \Y $eq$ls180.v:5981$1569_Y
+ connect \Y $eq$ls180.v:6030$1584_Y
end
- attribute \src "ls180.v:5983.104-5983.149"
- cell $eq $eq$ls180.v:5983$1572
+ attribute \src "ls180.v:6032.104-6032.149"
+ cell $eq $eq$ls180.v:6032$1587
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10101
- connect \Y $eq$ls180.v:5983$1572_Y
+ connect \Y $eq$ls180.v:6032$1587_Y
end
- attribute \src "ls180.v:5984.107-5984.152"
- cell $eq $eq$ls180.v:5984$1576
+ attribute \src "ls180.v:6033.107-6033.152"
+ cell $eq $eq$ls180.v:6033$1591
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10101
- connect \Y $eq$ls180.v:5984$1576_Y
+ connect \Y $eq$ls180.v:6033$1591_Y
end
- attribute \src "ls180.v:5986.104-5986.149"
- cell $eq $eq$ls180.v:5986$1579
+ attribute \src "ls180.v:6035.104-6035.149"
+ cell $eq $eq$ls180.v:6035$1594
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10110
- connect \Y $eq$ls180.v:5986$1579_Y
+ connect \Y $eq$ls180.v:6035$1594_Y
end
- attribute \src "ls180.v:5987.107-5987.152"
- cell $eq $eq$ls180.v:5987$1583
+ attribute \src "ls180.v:6036.107-6036.152"
+ cell $eq $eq$ls180.v:6036$1598
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10110
- connect \Y $eq$ls180.v:5987$1583_Y
+ connect \Y $eq$ls180.v:6036$1598_Y
end
- attribute \src "ls180.v:5989.104-5989.149"
- cell $eq $eq$ls180.v:5989$1586
+ attribute \src "ls180.v:6038.104-6038.149"
+ cell $eq $eq$ls180.v:6038$1601
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10111
- connect \Y $eq$ls180.v:5989$1586_Y
+ connect \Y $eq$ls180.v:6038$1601_Y
end
- attribute \src "ls180.v:5990.107-5990.152"
- cell $eq $eq$ls180.v:5990$1590
+ attribute \src "ls180.v:6039.107-6039.152"
+ cell $eq $eq$ls180.v:6039$1605
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'10111
- connect \Y $eq$ls180.v:5990$1590_Y
+ connect \Y $eq$ls180.v:6039$1605_Y
end
- attribute \src "ls180.v:5992.104-5992.149"
- cell $eq $eq$ls180.v:5992$1593
+ attribute \src "ls180.v:6041.104-6041.149"
+ cell $eq $eq$ls180.v:6041$1608
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11000
- connect \Y $eq$ls180.v:5992$1593_Y
+ connect \Y $eq$ls180.v:6041$1608_Y
end
- attribute \src "ls180.v:5993.107-5993.152"
- cell $eq $eq$ls180.v:5993$1597
+ attribute \src "ls180.v:6042.107-6042.152"
+ cell $eq $eq$ls180.v:6042$1612
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11000
- connect \Y $eq$ls180.v:5993$1597_Y
+ connect \Y $eq$ls180.v:6042$1612_Y
end
- attribute \src "ls180.v:5995.100-5995.145"
- cell $eq $eq$ls180.v:5995$1600
+ attribute \src "ls180.v:6044.100-6044.145"
+ cell $eq $eq$ls180.v:6044$1615
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11001
- connect \Y $eq$ls180.v:5995$1600_Y
+ connect \Y $eq$ls180.v:6044$1615_Y
end
- attribute \src "ls180.v:5996.103-5996.148"
- cell $eq $eq$ls180.v:5996$1604
+ attribute \src "ls180.v:6045.103-6045.148"
+ cell $eq $eq$ls180.v:6045$1619
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11001
- connect \Y $eq$ls180.v:5996$1604_Y
+ connect \Y $eq$ls180.v:6045$1619_Y
end
- attribute \src "ls180.v:5998.101-5998.146"
- cell $eq $eq$ls180.v:5998$1607
+ attribute \src "ls180.v:6047.101-6047.146"
+ cell $eq $eq$ls180.v:6047$1622
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11010
- connect \Y $eq$ls180.v:5998$1607_Y
+ connect \Y $eq$ls180.v:6047$1622_Y
end
- attribute \src "ls180.v:5999.104-5999.149"
- cell $eq $eq$ls180.v:5999$1611
+ attribute \src "ls180.v:6048.104-6048.149"
+ cell $eq $eq$ls180.v:6048$1626
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11010
- connect \Y $eq$ls180.v:5999$1611_Y
+ connect \Y $eq$ls180.v:6048$1626_Y
end
- attribute \src "ls180.v:6001.104-6001.149"
- cell $eq $eq$ls180.v:6001$1614
+ attribute \src "ls180.v:6050.104-6050.149"
+ cell $eq $eq$ls180.v:6050$1629
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11011
- connect \Y $eq$ls180.v:6001$1614_Y
+ connect \Y $eq$ls180.v:6050$1629_Y
end
- attribute \src "ls180.v:6002.107-6002.152"
- cell $eq $eq$ls180.v:6002$1618
+ attribute \src "ls180.v:6051.107-6051.152"
+ cell $eq $eq$ls180.v:6051$1633
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11011
- connect \Y $eq$ls180.v:6002$1618_Y
+ connect \Y $eq$ls180.v:6051$1633_Y
end
- attribute \src "ls180.v:6004.104-6004.149"
- cell $eq $eq$ls180.v:6004$1621
+ attribute \src "ls180.v:6053.104-6053.149"
+ cell $eq $eq$ls180.v:6053$1636
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11100
- connect \Y $eq$ls180.v:6004$1621_Y
+ connect \Y $eq$ls180.v:6053$1636_Y
end
- attribute \src "ls180.v:6005.107-6005.152"
- cell $eq $eq$ls180.v:6005$1625
+ attribute \src "ls180.v:6054.107-6054.152"
+ cell $eq $eq$ls180.v:6054$1640
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11100
- connect \Y $eq$ls180.v:6005$1625_Y
+ connect \Y $eq$ls180.v:6054$1640_Y
end
- attribute \src "ls180.v:6007.103-6007.148"
- cell $eq $eq$ls180.v:6007$1628
+ attribute \src "ls180.v:6056.103-6056.148"
+ cell $eq $eq$ls180.v:6056$1643
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11101
- connect \Y $eq$ls180.v:6007$1628_Y
+ connect \Y $eq$ls180.v:6056$1643_Y
end
- attribute \src "ls180.v:6008.106-6008.151"
- cell $eq $eq$ls180.v:6008$1632
+ attribute \src "ls180.v:6057.106-6057.151"
+ cell $eq $eq$ls180.v:6057$1647
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11101
- connect \Y $eq$ls180.v:6008$1632_Y
+ connect \Y $eq$ls180.v:6057$1647_Y
end
- attribute \src "ls180.v:6010.103-6010.148"
- cell $eq $eq$ls180.v:6010$1635
+ attribute \src "ls180.v:6059.103-6059.148"
+ cell $eq $eq$ls180.v:6059$1650
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11110
- connect \Y $eq$ls180.v:6010$1635_Y
+ connect \Y $eq$ls180.v:6059$1650_Y
end
- attribute \src "ls180.v:6011.106-6011.151"
- cell $eq $eq$ls180.v:6011$1639
+ attribute \src "ls180.v:6060.106-6060.151"
+ cell $eq $eq$ls180.v:6060$1654
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11110
- connect \Y $eq$ls180.v:6011$1639_Y
+ connect \Y $eq$ls180.v:6060$1654_Y
end
- attribute \src "ls180.v:6013.103-6013.148"
- cell $eq $eq$ls180.v:6013$1642
+ attribute \src "ls180.v:6062.103-6062.148"
+ cell $eq $eq$ls180.v:6062$1657
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11111
- connect \Y $eq$ls180.v:6013$1642_Y
+ connect \Y $eq$ls180.v:6062$1657_Y
end
- attribute \src "ls180.v:6014.106-6014.151"
- cell $eq $eq$ls180.v:6014$1646
+ attribute \src "ls180.v:6063.106-6063.151"
+ cell $eq $eq$ls180.v:6063$1661
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 5'11111
- connect \Y $eq$ls180.v:6014$1646_Y
+ connect \Y $eq$ls180.v:6063$1661_Y
end
- attribute \src "ls180.v:6016.103-6016.148"
- cell $eq $eq$ls180.v:6016$1649
+ attribute \src "ls180.v:6065.103-6065.148"
+ cell $eq $eq$ls180.v:6065$1664
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 6'100000
- connect \Y $eq$ls180.v:6016$1649_Y
+ connect \Y $eq$ls180.v:6065$1664_Y
end
- attribute \src "ls180.v:6017.106-6017.151"
- cell $eq $eq$ls180.v:6017$1653
+ attribute \src "ls180.v:6066.106-6066.151"
+ cell $eq $eq$ls180.v:6066$1668
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_adr [5:0]
+ connect \A \builder_interface6_bank_bus_adr [5:0]
connect \B 6'100000
- connect \Y $eq$ls180.v:6017$1653_Y
+ connect \Y $eq$ls180.v:6066$1668_Y
end
- attribute \src "ls180.v:6053.32-6053.78"
- cell $eq $eq$ls180.v:6053$1655
+ attribute \src "ls180.v:6102.32-6102.78"
+ cell $eq $eq$ls180.v:6102$1670
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [13:9]
- connect \B 4'1101
- connect \Y $eq$ls180.v:6053$1655_Y
+ connect \A \builder_interface7_bank_bus_adr [13:9]
+ connect \B 4'1110
+ connect \Y $eq$ls180.v:6102$1670_Y
end
- attribute \src "ls180.v:6055.100-6055.144"
- cell $eq $eq$ls180.v:6055$1657
+ attribute \src "ls180.v:6104.100-6104.144"
+ cell $eq $eq$ls180.v:6104$1672
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6055$1657_Y
+ connect \Y $eq$ls180.v:6104$1672_Y
end
- attribute \src "ls180.v:6056.103-6056.147"
- cell $eq $eq$ls180.v:6056$1661
+ attribute \src "ls180.v:6105.103-6105.147"
+ cell $eq $eq$ls180.v:6105$1676
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6056$1661_Y
+ connect \Y $eq$ls180.v:6105$1676_Y
end
- attribute \src "ls180.v:6058.100-6058.144"
- cell $eq $eq$ls180.v:6058$1664
+ attribute \src "ls180.v:6107.100-6107.144"
+ cell $eq $eq$ls180.v:6107$1679
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6058$1664_Y
+ connect \Y $eq$ls180.v:6107$1679_Y
end
- attribute \src "ls180.v:6059.103-6059.147"
- cell $eq $eq$ls180.v:6059$1668
+ attribute \src "ls180.v:6108.103-6108.147"
+ cell $eq $eq$ls180.v:6108$1683
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6059$1668_Y
+ connect \Y $eq$ls180.v:6108$1683_Y
end
- attribute \src "ls180.v:6061.100-6061.144"
- cell $eq $eq$ls180.v:6061$1671
+ attribute \src "ls180.v:6110.100-6110.144"
+ cell $eq $eq$ls180.v:6110$1686
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6061$1671_Y
+ connect \Y $eq$ls180.v:6110$1686_Y
end
- attribute \src "ls180.v:6062.103-6062.147"
- cell $eq $eq$ls180.v:6062$1675
+ attribute \src "ls180.v:6111.103-6111.147"
+ cell $eq $eq$ls180.v:6111$1690
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6062$1675_Y
+ connect \Y $eq$ls180.v:6111$1690_Y
end
- attribute \src "ls180.v:6064.100-6064.144"
- cell $eq $eq$ls180.v:6064$1678
+ attribute \src "ls180.v:6113.100-6113.144"
+ cell $eq $eq$ls180.v:6113$1693
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6064$1678_Y
+ connect \Y $eq$ls180.v:6113$1693_Y
end
- attribute \src "ls180.v:6065.103-6065.147"
- cell $eq $eq$ls180.v:6065$1682
+ attribute \src "ls180.v:6114.103-6114.147"
+ cell $eq $eq$ls180.v:6114$1697
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6065$1682_Y
+ connect \Y $eq$ls180.v:6114$1697_Y
end
- attribute \src "ls180.v:6067.100-6067.144"
- cell $eq $eq$ls180.v:6067$1685
+ attribute \src "ls180.v:6116.100-6116.144"
+ cell $eq $eq$ls180.v:6116$1700
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6067$1685_Y
+ connect \Y $eq$ls180.v:6116$1700_Y
end
- attribute \src "ls180.v:6068.103-6068.147"
- cell $eq $eq$ls180.v:6068$1689
+ attribute \src "ls180.v:6117.103-6117.147"
+ cell $eq $eq$ls180.v:6117$1704
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6068$1689_Y
+ connect \Y $eq$ls180.v:6117$1704_Y
end
- attribute \src "ls180.v:6070.100-6070.144"
- cell $eq $eq$ls180.v:6070$1692
+ attribute \src "ls180.v:6119.100-6119.144"
+ cell $eq $eq$ls180.v:6119$1707
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6070$1692_Y
+ connect \Y $eq$ls180.v:6119$1707_Y
end
- attribute \src "ls180.v:6071.103-6071.147"
- cell $eq $eq$ls180.v:6071$1696
+ attribute \src "ls180.v:6120.103-6120.147"
+ cell $eq $eq$ls180.v:6120$1711
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6071$1696_Y
+ connect \Y $eq$ls180.v:6120$1711_Y
end
- attribute \src "ls180.v:6073.100-6073.144"
- cell $eq $eq$ls180.v:6073$1699
+ attribute \src "ls180.v:6122.100-6122.144"
+ cell $eq $eq$ls180.v:6122$1714
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6073$1699_Y
+ connect \Y $eq$ls180.v:6122$1714_Y
end
- attribute \src "ls180.v:6074.103-6074.147"
- cell $eq $eq$ls180.v:6074$1703
+ attribute \src "ls180.v:6123.103-6123.147"
+ cell $eq $eq$ls180.v:6123$1718
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6074$1703_Y
+ connect \Y $eq$ls180.v:6123$1718_Y
end
- attribute \src "ls180.v:6076.100-6076.144"
- cell $eq $eq$ls180.v:6076$1706
+ attribute \src "ls180.v:6125.100-6125.144"
+ cell $eq $eq$ls180.v:6125$1721
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6076$1706_Y
+ connect \Y $eq$ls180.v:6125$1721_Y
end
- attribute \src "ls180.v:6077.103-6077.147"
- cell $eq $eq$ls180.v:6077$1710
+ attribute \src "ls180.v:6126.103-6126.147"
+ cell $eq $eq$ls180.v:6126$1725
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6077$1710_Y
+ connect \Y $eq$ls180.v:6126$1725_Y
end
- attribute \src "ls180.v:6079.102-6079.146"
- cell $eq $eq$ls180.v:6079$1713
+ attribute \src "ls180.v:6128.102-6128.146"
+ cell $eq $eq$ls180.v:6128$1728
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6079$1713_Y
+ connect \Y $eq$ls180.v:6128$1728_Y
end
- attribute \src "ls180.v:6080.105-6080.149"
- cell $eq $eq$ls180.v:6080$1717
+ attribute \src "ls180.v:6129.105-6129.149"
+ cell $eq $eq$ls180.v:6129$1732
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6080$1717_Y
+ connect \Y $eq$ls180.v:6129$1732_Y
end
- attribute \src "ls180.v:6082.102-6082.146"
- cell $eq $eq$ls180.v:6082$1720
+ attribute \src "ls180.v:6131.102-6131.146"
+ cell $eq $eq$ls180.v:6131$1735
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6082$1720_Y
+ connect \Y $eq$ls180.v:6131$1735_Y
end
- attribute \src "ls180.v:6083.105-6083.149"
- cell $eq $eq$ls180.v:6083$1724
+ attribute \src "ls180.v:6132.105-6132.149"
+ cell $eq $eq$ls180.v:6132$1739
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6083$1724_Y
+ connect \Y $eq$ls180.v:6132$1739_Y
end
- attribute \src "ls180.v:6085.102-6085.147"
- cell $eq $eq$ls180.v:6085$1727
+ attribute \src "ls180.v:6134.102-6134.147"
+ cell $eq $eq$ls180.v:6134$1742
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:6085$1727_Y
+ connect \Y $eq$ls180.v:6134$1742_Y
end
- attribute \src "ls180.v:6086.105-6086.150"
- cell $eq $eq$ls180.v:6086$1731
+ attribute \src "ls180.v:6135.105-6135.150"
+ cell $eq $eq$ls180.v:6135$1746
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:6086$1731_Y
+ connect \Y $eq$ls180.v:6135$1746_Y
end
- attribute \src "ls180.v:6088.102-6088.147"
- cell $eq $eq$ls180.v:6088$1734
+ attribute \src "ls180.v:6137.102-6137.147"
+ cell $eq $eq$ls180.v:6137$1749
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:6088$1734_Y
+ connect \Y $eq$ls180.v:6137$1749_Y
end
- attribute \src "ls180.v:6089.105-6089.150"
- cell $eq $eq$ls180.v:6089$1738
+ attribute \src "ls180.v:6138.105-6138.150"
+ cell $eq $eq$ls180.v:6138$1753
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:6089$1738_Y
+ connect \Y $eq$ls180.v:6138$1753_Y
end
- attribute \src "ls180.v:6091.102-6091.147"
- cell $eq $eq$ls180.v:6091$1741
+ attribute \src "ls180.v:6140.102-6140.147"
+ cell $eq $eq$ls180.v:6140$1756
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:6091$1741_Y
+ connect \Y $eq$ls180.v:6140$1756_Y
end
- attribute \src "ls180.v:6092.105-6092.150"
- cell $eq $eq$ls180.v:6092$1745
+ attribute \src "ls180.v:6141.105-6141.150"
+ cell $eq $eq$ls180.v:6141$1760
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:6092$1745_Y
+ connect \Y $eq$ls180.v:6141$1760_Y
end
- attribute \src "ls180.v:6094.99-6094.144"
- cell $eq $eq$ls180.v:6094$1748
+ attribute \src "ls180.v:6143.99-6143.144"
+ cell $eq $eq$ls180.v:6143$1763
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:6094$1748_Y
+ connect \Y $eq$ls180.v:6143$1763_Y
end
- attribute \src "ls180.v:6095.102-6095.147"
- cell $eq $eq$ls180.v:6095$1752
+ attribute \src "ls180.v:6144.102-6144.147"
+ cell $eq $eq$ls180.v:6144$1767
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:6095$1752_Y
+ connect \Y $eq$ls180.v:6144$1767_Y
end
- attribute \src "ls180.v:6097.100-6097.145"
- cell $eq $eq$ls180.v:6097$1755
+ attribute \src "ls180.v:6146.100-6146.145"
+ cell $eq $eq$ls180.v:6146$1770
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:6097$1755_Y
+ connect \Y $eq$ls180.v:6146$1770_Y
end
- attribute \src "ls180.v:6098.103-6098.148"
- cell $eq $eq$ls180.v:6098$1759
+ attribute \src "ls180.v:6147.103-6147.148"
+ cell $eq $eq$ls180.v:6147$1774
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:6098$1759_Y
+ connect \Y $eq$ls180.v:6147$1774_Y
end
- attribute \src "ls180.v:6100.102-6100.147"
- cell $eq $eq$ls180.v:6100$1762
+ attribute \src "ls180.v:6149.102-6149.147"
+ cell $eq $eq$ls180.v:6149$1777
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:6100$1762_Y
+ connect \Y $eq$ls180.v:6149$1777_Y
end
- attribute \src "ls180.v:6101.105-6101.150"
- cell $eq $eq$ls180.v:6101$1766
+ attribute \src "ls180.v:6150.105-6150.150"
+ cell $eq $eq$ls180.v:6150$1781
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:6101$1766_Y
+ connect \Y $eq$ls180.v:6150$1781_Y
end
- attribute \src "ls180.v:6103.102-6103.147"
- cell $eq $eq$ls180.v:6103$1769
+ attribute \src "ls180.v:6152.102-6152.147"
+ cell $eq $eq$ls180.v:6152$1784
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:6103$1769_Y
+ connect \Y $eq$ls180.v:6152$1784_Y
end
- attribute \src "ls180.v:6104.105-6104.150"
- cell $eq $eq$ls180.v:6104$1773
+ attribute \src "ls180.v:6153.105-6153.150"
+ cell $eq $eq$ls180.v:6153$1788
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:6104$1773_Y
+ connect \Y $eq$ls180.v:6153$1788_Y
end
- attribute \src "ls180.v:6106.102-6106.147"
- cell $eq $eq$ls180.v:6106$1776
+ attribute \src "ls180.v:6155.102-6155.147"
+ cell $eq $eq$ls180.v:6155$1791
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 5'10001
- connect \Y $eq$ls180.v:6106$1776_Y
+ connect \Y $eq$ls180.v:6155$1791_Y
end
- attribute \src "ls180.v:6107.105-6107.150"
- cell $eq $eq$ls180.v:6107$1780
+ attribute \src "ls180.v:6156.105-6156.150"
+ cell $eq $eq$ls180.v:6156$1795
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 5'10001
- connect \Y $eq$ls180.v:6107$1780_Y
+ connect \Y $eq$ls180.v:6156$1795_Y
end
- attribute \src "ls180.v:6109.102-6109.147"
- cell $eq $eq$ls180.v:6109$1783
+ attribute \src "ls180.v:6158.102-6158.147"
+ cell $eq $eq$ls180.v:6158$1798
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 5'10010
- connect \Y $eq$ls180.v:6109$1783_Y
+ connect \Y $eq$ls180.v:6158$1798_Y
end
- attribute \src "ls180.v:6110.105-6110.150"
- cell $eq $eq$ls180.v:6110$1787
+ attribute \src "ls180.v:6159.105-6159.150"
+ cell $eq $eq$ls180.v:6159$1802
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_adr [4:0]
+ connect \A \builder_interface7_bank_bus_adr [4:0]
connect \B 5'10010
- connect \Y $eq$ls180.v:6110$1787_Y
+ connect \Y $eq$ls180.v:6159$1802_Y
end
- attribute \src "ls180.v:6132.32-6132.78"
- cell $eq $eq$ls180.v:6132$1789
+ attribute \src "ls180.v:6181.32-6181.78"
+ cell $eq $eq$ls180.v:6181$1804
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface7_bank_bus_adr [13:9]
- connect \B 4'1010
- connect \Y $eq$ls180.v:6132$1789_Y
+ connect \A \builder_interface8_bank_bus_adr [13:9]
+ connect \B 4'1011
+ connect \Y $eq$ls180.v:6181$1804_Y
end
- attribute \src "ls180.v:6134.102-6134.146"
- cell $eq $eq$ls180.v:6134$1791
+ attribute \src "ls180.v:6183.102-6183.146"
+ cell $eq $eq$ls180.v:6183$1806
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface7_bank_bus_adr [1:0]
+ connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6134$1791_Y
+ connect \Y $eq$ls180.v:6183$1806_Y
end
- attribute \src "ls180.v:6135.105-6135.149"
- cell $eq $eq$ls180.v:6135$1795
+ attribute \src "ls180.v:6184.105-6184.149"
+ cell $eq $eq$ls180.v:6184$1810
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface7_bank_bus_adr [1:0]
+ connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6135$1795_Y
+ connect \Y $eq$ls180.v:6184$1810_Y
end
- attribute \src "ls180.v:6137.107-6137.151"
- cell $eq $eq$ls180.v:6137$1798
+ attribute \src "ls180.v:6186.107-6186.151"
+ cell $eq $eq$ls180.v:6186$1813
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface7_bank_bus_adr [1:0]
+ connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6137$1798_Y
+ connect \Y $eq$ls180.v:6186$1813_Y
end
- attribute \src "ls180.v:6138.110-6138.154"
- cell $eq $eq$ls180.v:6138$1802
+ attribute \src "ls180.v:6187.110-6187.154"
+ cell $eq $eq$ls180.v:6187$1817
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface7_bank_bus_adr [1:0]
+ connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6138$1802_Y
+ connect \Y $eq$ls180.v:6187$1817_Y
end
- attribute \src "ls180.v:6140.107-6140.151"
- cell $eq $eq$ls180.v:6140$1805
+ attribute \src "ls180.v:6189.107-6189.151"
+ cell $eq $eq$ls180.v:6189$1820
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface7_bank_bus_adr [1:0]
+ connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6140$1805_Y
+ connect \Y $eq$ls180.v:6189$1820_Y
end
- attribute \src "ls180.v:6141.110-6141.154"
- cell $eq $eq$ls180.v:6141$1809
+ attribute \src "ls180.v:6190.110-6190.154"
+ cell $eq $eq$ls180.v:6190$1824
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface7_bank_bus_adr [1:0]
+ connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6141$1809_Y
+ connect \Y $eq$ls180.v:6190$1824_Y
end
- attribute \src "ls180.v:6143.100-6143.144"
- cell $eq $eq$ls180.v:6143$1812
+ attribute \src "ls180.v:6192.100-6192.144"
+ cell $eq $eq$ls180.v:6192$1827
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface7_bank_bus_adr [1:0]
+ connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6143$1812_Y
+ connect \Y $eq$ls180.v:6192$1827_Y
end
- attribute \src "ls180.v:6144.103-6144.147"
- cell $eq $eq$ls180.v:6144$1816
+ attribute \src "ls180.v:6193.103-6193.147"
+ cell $eq $eq$ls180.v:6193$1831
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface7_bank_bus_adr [1:0]
+ connect \A \builder_interface8_bank_bus_adr [1:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6144$1816_Y
+ connect \Y $eq$ls180.v:6193$1831_Y
end
- attribute \src "ls180.v:6149.32-6149.77"
- cell $eq $eq$ls180.v:6149$1818
+ attribute \src "ls180.v:6198.32-6198.77"
+ cell $eq $eq$ls180.v:6198$1833
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [13:9]
+ connect \A \builder_interface9_bank_bus_adr [13:9]
connect \B 2'11
- connect \Y $eq$ls180.v:6149$1818_Y
+ connect \Y $eq$ls180.v:6198$1833_Y
end
- attribute \src "ls180.v:6151.104-6151.148"
- cell $eq $eq$ls180.v:6151$1820
+ attribute \src "ls180.v:6200.104-6200.148"
+ cell $eq $eq$ls180.v:6200$1835
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6151$1820_Y
+ connect \Y $eq$ls180.v:6200$1835_Y
end
- attribute \src "ls180.v:6152.107-6152.151"
- cell $eq $eq$ls180.v:6152$1824
+ attribute \src "ls180.v:6201.107-6201.151"
+ cell $eq $eq$ls180.v:6201$1839
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6152$1824_Y
+ connect \Y $eq$ls180.v:6201$1839_Y
end
- attribute \src "ls180.v:6154.108-6154.152"
- cell $eq $eq$ls180.v:6154$1827
+ attribute \src "ls180.v:6203.108-6203.152"
+ cell $eq $eq$ls180.v:6203$1842
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6154$1827_Y
+ connect \Y $eq$ls180.v:6203$1842_Y
end
- attribute \src "ls180.v:6155.111-6155.155"
- cell $eq $eq$ls180.v:6155$1831
+ attribute \src "ls180.v:6204.111-6204.155"
+ cell $eq $eq$ls180.v:6204$1846
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6155$1831_Y
+ connect \Y $eq$ls180.v:6204$1846_Y
end
- attribute \src "ls180.v:6157.98-6157.142"
- cell $eq $eq$ls180.v:6157$1834
+ attribute \src "ls180.v:6206.98-6206.142"
+ cell $eq $eq$ls180.v:6206$1849
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6157$1834_Y
+ connect \Y $eq$ls180.v:6206$1849_Y
end
- attribute \src "ls180.v:6158.101-6158.145"
- cell $eq $eq$ls180.v:6158$1838
+ attribute \src "ls180.v:6207.101-6207.145"
+ cell $eq $eq$ls180.v:6207$1853
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6158$1838_Y
+ connect \Y $eq$ls180.v:6207$1853_Y
end
- attribute \src "ls180.v:6160.108-6160.152"
- cell $eq $eq$ls180.v:6160$1841
+ attribute \src "ls180.v:6209.108-6209.152"
+ cell $eq $eq$ls180.v:6209$1856
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6160$1841_Y
+ connect \Y $eq$ls180.v:6209$1856_Y
end
- attribute \src "ls180.v:6161.111-6161.155"
- cell $eq $eq$ls180.v:6161$1845
+ attribute \src "ls180.v:6210.111-6210.155"
+ cell $eq $eq$ls180.v:6210$1860
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6161$1845_Y
+ connect \Y $eq$ls180.v:6210$1860_Y
end
- attribute \src "ls180.v:6163.108-6163.152"
- cell $eq $eq$ls180.v:6163$1848
+ attribute \src "ls180.v:6212.108-6212.152"
+ cell $eq $eq$ls180.v:6212$1863
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6163$1848_Y
+ connect \Y $eq$ls180.v:6212$1863_Y
end
- attribute \src "ls180.v:6164.111-6164.155"
- cell $eq $eq$ls180.v:6164$1852
+ attribute \src "ls180.v:6213.111-6213.155"
+ cell $eq $eq$ls180.v:6213$1867
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6164$1852_Y
+ connect \Y $eq$ls180.v:6213$1867_Y
end
- attribute \src "ls180.v:6166.109-6166.153"
- cell $eq $eq$ls180.v:6166$1855
+ attribute \src "ls180.v:6215.109-6215.153"
+ cell $eq $eq$ls180.v:6215$1870
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6166$1855_Y
+ connect \Y $eq$ls180.v:6215$1870_Y
end
- attribute \src "ls180.v:6167.112-6167.156"
- cell $eq $eq$ls180.v:6167$1859
+ attribute \src "ls180.v:6216.112-6216.156"
+ cell $eq $eq$ls180.v:6216$1874
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6167$1859_Y
+ connect \Y $eq$ls180.v:6216$1874_Y
end
- attribute \src "ls180.v:6169.107-6169.151"
- cell $eq $eq$ls180.v:6169$1862
+ attribute \src "ls180.v:6218.107-6218.151"
+ cell $eq $eq$ls180.v:6218$1877
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6169$1862_Y
+ connect \Y $eq$ls180.v:6218$1877_Y
end
- attribute \src "ls180.v:6170.110-6170.154"
- cell $eq $eq$ls180.v:6170$1866
+ attribute \src "ls180.v:6219.110-6219.154"
+ cell $eq $eq$ls180.v:6219$1881
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6170$1866_Y
+ connect \Y $eq$ls180.v:6219$1881_Y
end
- attribute \src "ls180.v:6172.107-6172.151"
- cell $eq $eq$ls180.v:6172$1869
+ attribute \src "ls180.v:6221.107-6221.151"
+ cell $eq $eq$ls180.v:6221$1884
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6172$1869_Y
+ connect \Y $eq$ls180.v:6221$1884_Y
end
- attribute \src "ls180.v:6173.110-6173.154"
- cell $eq $eq$ls180.v:6173$1873
+ attribute \src "ls180.v:6222.110-6222.154"
+ cell $eq $eq$ls180.v:6222$1888
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6173$1873_Y
+ connect \Y $eq$ls180.v:6222$1888_Y
end
- attribute \src "ls180.v:6175.107-6175.151"
- cell $eq $eq$ls180.v:6175$1876
+ attribute \src "ls180.v:6224.107-6224.151"
+ cell $eq $eq$ls180.v:6224$1891
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6175$1876_Y
+ connect \Y $eq$ls180.v:6224$1891_Y
end
- attribute \src "ls180.v:6176.110-6176.154"
- cell $eq $eq$ls180.v:6176$1880
+ attribute \src "ls180.v:6225.110-6225.154"
+ cell $eq $eq$ls180.v:6225$1895
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6176$1880_Y
+ connect \Y $eq$ls180.v:6225$1895_Y
end
- attribute \src "ls180.v:6178.107-6178.151"
- cell $eq $eq$ls180.v:6178$1883
+ attribute \src "ls180.v:6227.107-6227.151"
+ cell $eq $eq$ls180.v:6227$1898
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6178$1883_Y
+ connect \Y $eq$ls180.v:6227$1898_Y
end
- attribute \src "ls180.v:6179.110-6179.154"
- cell $eq $eq$ls180.v:6179$1887
+ attribute \src "ls180.v:6228.110-6228.154"
+ cell $eq $eq$ls180.v:6228$1902
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_adr [3:0]
+ connect \A \builder_interface9_bank_bus_adr [3:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6179$1887_Y
+ connect \Y $eq$ls180.v:6228$1902_Y
end
- attribute \src "ls180.v:6194.32-6194.77"
- cell $eq $eq$ls180.v:6194$1889
+ attribute \src "ls180.v:6243.33-6243.79"
+ cell $eq $eq$ls180.v:6243$1904
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [13:9]
+ connect \A \builder_interface10_bank_bus_adr [13:9]
connect \B 3'111
- connect \Y $eq$ls180.v:6194$1889_Y
+ connect \Y $eq$ls180.v:6243$1904_Y
end
- attribute \src "ls180.v:6196.99-6196.143"
- cell $eq $eq$ls180.v:6196$1891
+ attribute \src "ls180.v:6245.102-6245.147"
+ cell $eq $eq$ls180.v:6245$1906
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6196$1891_Y
+ connect \Y $eq$ls180.v:6245$1906_Y
end
- attribute \src "ls180.v:6197.102-6197.146"
- cell $eq $eq$ls180.v:6197$1895
+ attribute \src "ls180.v:6246.105-6246.150"
+ cell $eq $eq$ls180.v:6246$1910
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6197$1895_Y
+ connect \Y $eq$ls180.v:6246$1910_Y
end
- attribute \src "ls180.v:6199.99-6199.143"
- cell $eq $eq$ls180.v:6199$1898
+ attribute \src "ls180.v:6248.102-6248.147"
+ cell $eq $eq$ls180.v:6248$1913
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6199$1898_Y
+ connect \Y $eq$ls180.v:6248$1913_Y
end
- attribute \src "ls180.v:6200.102-6200.146"
- cell $eq $eq$ls180.v:6200$1902
+ attribute \src "ls180.v:6249.105-6249.150"
+ cell $eq $eq$ls180.v:6249$1917
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6200$1902_Y
+ connect \Y $eq$ls180.v:6249$1917_Y
end
- attribute \src "ls180.v:6202.97-6202.141"
- cell $eq $eq$ls180.v:6202$1905
+ attribute \src "ls180.v:6251.100-6251.145"
+ cell $eq $eq$ls180.v:6251$1920
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6202$1905_Y
+ connect \Y $eq$ls180.v:6251$1920_Y
end
- attribute \src "ls180.v:6203.100-6203.144"
- cell $eq $eq$ls180.v:6203$1909
+ attribute \src "ls180.v:6252.103-6252.148"
+ cell $eq $eq$ls180.v:6252$1924
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6203$1909_Y
+ connect \Y $eq$ls180.v:6252$1924_Y
end
- attribute \src "ls180.v:6205.96-6205.140"
- cell $eq $eq$ls180.v:6205$1912
+ attribute \src "ls180.v:6254.99-6254.144"
+ cell $eq $eq$ls180.v:6254$1927
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6205$1912_Y
+ connect \Y $eq$ls180.v:6254$1927_Y
end
- attribute \src "ls180.v:6206.99-6206.143"
- cell $eq $eq$ls180.v:6206$1916
+ attribute \src "ls180.v:6255.102-6255.147"
+ cell $eq $eq$ls180.v:6255$1931
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6206$1916_Y
+ connect \Y $eq$ls180.v:6255$1931_Y
end
- attribute \src "ls180.v:6208.95-6208.139"
- cell $eq $eq$ls180.v:6208$1919
+ attribute \src "ls180.v:6257.98-6257.143"
+ cell $eq $eq$ls180.v:6257$1934
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6208$1919_Y
+ connect \Y $eq$ls180.v:6257$1934_Y
end
- attribute \src "ls180.v:6209.98-6209.142"
- cell $eq $eq$ls180.v:6209$1923
+ attribute \src "ls180.v:6258.101-6258.146"
+ cell $eq $eq$ls180.v:6258$1938
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6209$1923_Y
+ connect \Y $eq$ls180.v:6258$1938_Y
end
- attribute \src "ls180.v:6211.94-6211.138"
- cell $eq $eq$ls180.v:6211$1926
+ attribute \src "ls180.v:6260.97-6260.142"
+ cell $eq $eq$ls180.v:6260$1941
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6211$1926_Y
+ connect \Y $eq$ls180.v:6260$1941_Y
end
- attribute \src "ls180.v:6212.97-6212.141"
- cell $eq $eq$ls180.v:6212$1930
+ attribute \src "ls180.v:6261.100-6261.145"
+ cell $eq $eq$ls180.v:6261$1945
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6212$1930_Y
+ connect \Y $eq$ls180.v:6261$1945_Y
end
- attribute \src "ls180.v:6214.100-6214.144"
- cell $eq $eq$ls180.v:6214$1933
+ attribute \src "ls180.v:6263.103-6263.148"
+ cell $eq $eq$ls180.v:6263$1948
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6214$1933_Y
+ connect \Y $eq$ls180.v:6263$1948_Y
end
- attribute \src "ls180.v:6215.103-6215.147"
- cell $eq $eq$ls180.v:6215$1937
+ attribute \src "ls180.v:6264.106-6264.151"
+ cell $eq $eq$ls180.v:6264$1952
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface9_bank_bus_adr [2:0]
+ connect \A \builder_interface10_bank_bus_adr [2:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6215$1937_Y
+ connect \Y $eq$ls180.v:6264$1952_Y
end
- attribute \src "ls180.v:6234.33-6234.80"
- cell $eq $eq$ls180.v:6234$1940
+ attribute \src "ls180.v:6283.33-6283.80"
+ cell $eq $eq$ls180.v:6283$1955
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [13:9]
- connect \B 4'1110
- connect \Y $eq$ls180.v:6234$1940_Y
+ connect \A \builder_interface11_bank_bus_adr [13:9]
+ connect \B 4'1111
+ connect \Y $eq$ls180.v:6283$1955_Y
end
- attribute \src "ls180.v:6236.102-6236.147"
- cell $eq $eq$ls180.v:6236$1942
+ attribute \src "ls180.v:6285.102-6285.147"
+ cell $eq $eq$ls180.v:6285$1957
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6236$1942_Y
+ connect \Y $eq$ls180.v:6285$1957_Y
end
- attribute \src "ls180.v:6237.105-6237.150"
- cell $eq $eq$ls180.v:6237$1946
+ attribute \src "ls180.v:6286.105-6286.150"
+ cell $eq $eq$ls180.v:6286$1961
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6237$1946_Y
+ connect \Y $eq$ls180.v:6286$1961_Y
end
- attribute \src "ls180.v:6239.102-6239.147"
- cell $eq $eq$ls180.v:6239$1949
+ attribute \src "ls180.v:6288.102-6288.147"
+ cell $eq $eq$ls180.v:6288$1964
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6239$1949_Y
+ connect \Y $eq$ls180.v:6288$1964_Y
end
- attribute \src "ls180.v:6240.105-6240.150"
- cell $eq $eq$ls180.v:6240$1953
+ attribute \src "ls180.v:6289.105-6289.150"
+ cell $eq $eq$ls180.v:6289$1968
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6240$1953_Y
+ connect \Y $eq$ls180.v:6289$1968_Y
end
- attribute \src "ls180.v:6242.100-6242.145"
- cell $eq $eq$ls180.v:6242$1956
+ attribute \src "ls180.v:6291.100-6291.145"
+ cell $eq $eq$ls180.v:6291$1971
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6242$1956_Y
+ connect \Y $eq$ls180.v:6291$1971_Y
end
- attribute \src "ls180.v:6243.103-6243.148"
- cell $eq $eq$ls180.v:6243$1960
+ attribute \src "ls180.v:6292.103-6292.148"
+ cell $eq $eq$ls180.v:6292$1975
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6243$1960_Y
+ connect \Y $eq$ls180.v:6292$1975_Y
end
- attribute \src "ls180.v:6245.99-6245.144"
- cell $eq $eq$ls180.v:6245$1963
+ attribute \src "ls180.v:6294.99-6294.144"
+ cell $eq $eq$ls180.v:6294$1978
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6245$1963_Y
+ connect \Y $eq$ls180.v:6294$1978_Y
end
- attribute \src "ls180.v:6246.102-6246.147"
- cell $eq $eq$ls180.v:6246$1967
+ attribute \src "ls180.v:6295.102-6295.147"
+ cell $eq $eq$ls180.v:6295$1982
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6246$1967_Y
+ connect \Y $eq$ls180.v:6295$1982_Y
end
- attribute \src "ls180.v:6248.98-6248.143"
- cell $eq $eq$ls180.v:6248$1970
+ attribute \src "ls180.v:6297.98-6297.143"
+ cell $eq $eq$ls180.v:6297$1985
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6248$1970_Y
+ connect \Y $eq$ls180.v:6297$1985_Y
end
- attribute \src "ls180.v:6249.101-6249.146"
- cell $eq $eq$ls180.v:6249$1974
+ attribute \src "ls180.v:6298.101-6298.146"
+ cell $eq $eq$ls180.v:6298$1989
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6249$1974_Y
+ connect \Y $eq$ls180.v:6298$1989_Y
end
- attribute \src "ls180.v:6251.97-6251.142"
- cell $eq $eq$ls180.v:6251$1977
+ attribute \src "ls180.v:6300.97-6300.142"
+ cell $eq $eq$ls180.v:6300$1992
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6251$1977_Y
+ connect \Y $eq$ls180.v:6300$1992_Y
end
- attribute \src "ls180.v:6252.100-6252.145"
- cell $eq $eq$ls180.v:6252$1981
+ attribute \src "ls180.v:6301.100-6301.145"
+ cell $eq $eq$ls180.v:6301$1996
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6252$1981_Y
+ connect \Y $eq$ls180.v:6301$1996_Y
end
- attribute \src "ls180.v:6254.103-6254.148"
- cell $eq $eq$ls180.v:6254$1984
+ attribute \src "ls180.v:6303.103-6303.148"
+ cell $eq $eq$ls180.v:6303$1999
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6254$1984_Y
+ connect \Y $eq$ls180.v:6303$1999_Y
end
- attribute \src "ls180.v:6255.106-6255.151"
- cell $eq $eq$ls180.v:6255$1988
+ attribute \src "ls180.v:6304.106-6304.151"
+ cell $eq $eq$ls180.v:6304$2003
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6255$1988_Y
+ connect \Y $eq$ls180.v:6304$2003_Y
end
- attribute \src "ls180.v:6257.106-6257.151"
- cell $eq $eq$ls180.v:6257$1991
+ attribute \src "ls180.v:6306.106-6306.151"
+ cell $eq $eq$ls180.v:6306$2006
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6257$1991_Y
+ connect \Y $eq$ls180.v:6306$2006_Y
end
- attribute \src "ls180.v:6258.109-6258.154"
- cell $eq $eq$ls180.v:6258$1995
+ attribute \src "ls180.v:6307.109-6307.154"
+ cell $eq $eq$ls180.v:6307$2010
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6258$1995_Y
+ connect \Y $eq$ls180.v:6307$2010_Y
end
- attribute \src "ls180.v:6260.106-6260.151"
- cell $eq $eq$ls180.v:6260$1998
+ attribute \src "ls180.v:6309.106-6309.151"
+ cell $eq $eq$ls180.v:6309$2013
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6260$1998_Y
+ connect \Y $eq$ls180.v:6309$2013_Y
end
- attribute \src "ls180.v:6261.109-6261.154"
- cell $eq $eq$ls180.v:6261$2002
+ attribute \src "ls180.v:6310.109-6310.154"
+ cell $eq $eq$ls180.v:6310$2017
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_adr [3:0]
+ connect \A \builder_interface11_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6261$2002_Y
+ connect \Y $eq$ls180.v:6310$2017_Y
end
- attribute \src "ls180.v:6282.33-6282.79"
- cell $eq $eq$ls180.v:6282$2005
+ attribute \src "ls180.v:6331.33-6331.79"
+ cell $eq $eq$ls180.v:6331$2020
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [13:9]
+ connect \A \builder_interface12_bank_bus_adr [13:9]
connect \B 2'10
- connect \Y $eq$ls180.v:6282$2005_Y
+ connect \Y $eq$ls180.v:6331$2020_Y
end
- attribute \src "ls180.v:6284.99-6284.144"
- cell $eq $eq$ls180.v:6284$2007
+ attribute \src "ls180.v:6333.99-6333.144"
+ cell $eq $eq$ls180.v:6333$2022
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6284$2007_Y
+ connect \Y $eq$ls180.v:6333$2022_Y
end
- attribute \src "ls180.v:6285.102-6285.147"
- cell $eq $eq$ls180.v:6285$2011
+ attribute \src "ls180.v:6334.102-6334.147"
+ cell $eq $eq$ls180.v:6334$2026
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6285$2011_Y
+ connect \Y $eq$ls180.v:6334$2026_Y
end
- attribute \src "ls180.v:6287.99-6287.144"
- cell $eq $eq$ls180.v:6287$2014
+ attribute \src "ls180.v:6336.99-6336.144"
+ cell $eq $eq$ls180.v:6336$2029
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6287$2014_Y
+ connect \Y $eq$ls180.v:6336$2029_Y
end
- attribute \src "ls180.v:6288.102-6288.147"
- cell $eq $eq$ls180.v:6288$2018
+ attribute \src "ls180.v:6337.102-6337.147"
+ cell $eq $eq$ls180.v:6337$2033
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6288$2018_Y
+ connect \Y $eq$ls180.v:6337$2033_Y
end
- attribute \src "ls180.v:6290.99-6290.144"
- cell $eq $eq$ls180.v:6290$2021
+ attribute \src "ls180.v:6339.99-6339.144"
+ cell $eq $eq$ls180.v:6339$2036
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6290$2021_Y
+ connect \Y $eq$ls180.v:6339$2036_Y
end
- attribute \src "ls180.v:6291.102-6291.147"
- cell $eq $eq$ls180.v:6291$2025
+ attribute \src "ls180.v:6340.102-6340.147"
+ cell $eq $eq$ls180.v:6340$2040
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6291$2025_Y
+ connect \Y $eq$ls180.v:6340$2040_Y
end
- attribute \src "ls180.v:6293.99-6293.144"
- cell $eq $eq$ls180.v:6293$2028
+ attribute \src "ls180.v:6342.99-6342.144"
+ cell $eq $eq$ls180.v:6342$2043
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6293$2028_Y
+ connect \Y $eq$ls180.v:6342$2043_Y
end
- attribute \src "ls180.v:6294.102-6294.147"
- cell $eq $eq$ls180.v:6294$2032
+ attribute \src "ls180.v:6343.102-6343.147"
+ cell $eq $eq$ls180.v:6343$2047
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6294$2032_Y
+ connect \Y $eq$ls180.v:6343$2047_Y
end
- attribute \src "ls180.v:6296.101-6296.146"
- cell $eq $eq$ls180.v:6296$2035
+ attribute \src "ls180.v:6345.101-6345.146"
+ cell $eq $eq$ls180.v:6345$2050
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6296$2035_Y
+ connect \Y $eq$ls180.v:6345$2050_Y
end
- attribute \src "ls180.v:6297.104-6297.149"
- cell $eq $eq$ls180.v:6297$2039
+ attribute \src "ls180.v:6346.104-6346.149"
+ cell $eq $eq$ls180.v:6346$2054
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6297$2039_Y
+ connect \Y $eq$ls180.v:6346$2054_Y
end
- attribute \src "ls180.v:6299.101-6299.146"
- cell $eq $eq$ls180.v:6299$2042
+ attribute \src "ls180.v:6348.101-6348.146"
+ cell $eq $eq$ls180.v:6348$2057
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6299$2042_Y
+ connect \Y $eq$ls180.v:6348$2057_Y
end
- attribute \src "ls180.v:6300.104-6300.149"
- cell $eq $eq$ls180.v:6300$2046
+ attribute \src "ls180.v:6349.104-6349.149"
+ cell $eq $eq$ls180.v:6349$2061
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6300$2046_Y
+ connect \Y $eq$ls180.v:6349$2061_Y
end
- attribute \src "ls180.v:6302.101-6302.146"
- cell $eq $eq$ls180.v:6302$2049
+ attribute \src "ls180.v:6351.101-6351.146"
+ cell $eq $eq$ls180.v:6351$2064
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6302$2049_Y
+ connect \Y $eq$ls180.v:6351$2064_Y
end
- attribute \src "ls180.v:6303.104-6303.149"
- cell $eq $eq$ls180.v:6303$2053
+ attribute \src "ls180.v:6352.104-6352.149"
+ cell $eq $eq$ls180.v:6352$2068
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6303$2053_Y
+ connect \Y $eq$ls180.v:6352$2068_Y
end
- attribute \src "ls180.v:6305.101-6305.146"
- cell $eq $eq$ls180.v:6305$2056
+ attribute \src "ls180.v:6354.101-6354.146"
+ cell $eq $eq$ls180.v:6354$2071
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6305$2056_Y
+ connect \Y $eq$ls180.v:6354$2071_Y
end
- attribute \src "ls180.v:6306.104-6306.149"
- cell $eq $eq$ls180.v:6306$2060
+ attribute \src "ls180.v:6355.104-6355.149"
+ cell $eq $eq$ls180.v:6355$2075
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6306$2060_Y
+ connect \Y $eq$ls180.v:6355$2075_Y
end
- attribute \src "ls180.v:6308.97-6308.142"
- cell $eq $eq$ls180.v:6308$2063
+ attribute \src "ls180.v:6357.97-6357.142"
+ cell $eq $eq$ls180.v:6357$2078
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6308$2063_Y
+ connect \Y $eq$ls180.v:6357$2078_Y
end
- attribute \src "ls180.v:6309.100-6309.145"
- cell $eq $eq$ls180.v:6309$2067
+ attribute \src "ls180.v:6358.100-6358.145"
+ cell $eq $eq$ls180.v:6358$2082
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:6309$2067_Y
+ connect \Y $eq$ls180.v:6358$2082_Y
end
- attribute \src "ls180.v:6311.107-6311.152"
- cell $eq $eq$ls180.v:6311$2070
+ attribute \src "ls180.v:6360.107-6360.152"
+ cell $eq $eq$ls180.v:6360$2085
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6311$2070_Y
+ connect \Y $eq$ls180.v:6360$2085_Y
end
- attribute \src "ls180.v:6312.110-6312.155"
- cell $eq $eq$ls180.v:6312$2074
+ attribute \src "ls180.v:6361.110-6361.155"
+ cell $eq $eq$ls180.v:6361$2089
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:6312$2074_Y
+ connect \Y $eq$ls180.v:6361$2089_Y
end
- attribute \src "ls180.v:6314.100-6314.146"
- cell $eq $eq$ls180.v:6314$2077
+ attribute \src "ls180.v:6363.100-6363.146"
+ cell $eq $eq$ls180.v:6363$2092
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:6314$2077_Y
+ connect \Y $eq$ls180.v:6363$2092_Y
end
- attribute \src "ls180.v:6315.103-6315.149"
- cell $eq $eq$ls180.v:6315$2081
+ attribute \src "ls180.v:6364.103-6364.149"
+ cell $eq $eq$ls180.v:6364$2096
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:6315$2081_Y
+ connect \Y $eq$ls180.v:6364$2096_Y
end
- attribute \src "ls180.v:6317.100-6317.146"
- cell $eq $eq$ls180.v:6317$2084
+ attribute \src "ls180.v:6366.100-6366.146"
+ cell $eq $eq$ls180.v:6366$2099
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:6317$2084_Y
+ connect \Y $eq$ls180.v:6366$2099_Y
end
- attribute \src "ls180.v:6318.103-6318.149"
- cell $eq $eq$ls180.v:6318$2088
+ attribute \src "ls180.v:6367.103-6367.149"
+ cell $eq $eq$ls180.v:6367$2103
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:6318$2088_Y
+ connect \Y $eq$ls180.v:6367$2103_Y
end
- attribute \src "ls180.v:6320.100-6320.146"
- cell $eq $eq$ls180.v:6320$2091
+ attribute \src "ls180.v:6369.100-6369.146"
+ cell $eq $eq$ls180.v:6369$2106
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:6320$2091_Y
+ connect \Y $eq$ls180.v:6369$2106_Y
end
- attribute \src "ls180.v:6321.103-6321.149"
- cell $eq $eq$ls180.v:6321$2095
+ attribute \src "ls180.v:6370.103-6370.149"
+ cell $eq $eq$ls180.v:6370$2110
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:6321$2095_Y
+ connect \Y $eq$ls180.v:6370$2110_Y
end
- attribute \src "ls180.v:6323.100-6323.146"
- cell $eq $eq$ls180.v:6323$2098
+ attribute \src "ls180.v:6372.100-6372.146"
+ cell $eq $eq$ls180.v:6372$2113
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:6323$2098_Y
+ connect \Y $eq$ls180.v:6372$2113_Y
end
- attribute \src "ls180.v:6324.103-6324.149"
- cell $eq $eq$ls180.v:6324$2102
+ attribute \src "ls180.v:6373.103-6373.149"
+ cell $eq $eq$ls180.v:6373$2117
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:6324$2102_Y
+ connect \Y $eq$ls180.v:6373$2117_Y
end
- attribute \src "ls180.v:6326.112-6326.158"
- cell $eq $eq$ls180.v:6326$2105
+ attribute \src "ls180.v:6375.112-6375.158"
+ cell $eq $eq$ls180.v:6375$2120
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:6326$2105_Y
+ connect \Y $eq$ls180.v:6375$2120_Y
end
- attribute \src "ls180.v:6327.115-6327.161"
- cell $eq $eq$ls180.v:6327$2109
+ attribute \src "ls180.v:6376.115-6376.161"
+ cell $eq $eq$ls180.v:6376$2124
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:6327$2109_Y
+ connect \Y $eq$ls180.v:6376$2124_Y
end
- attribute \src "ls180.v:6329.113-6329.159"
- cell $eq $eq$ls180.v:6329$2112
+ attribute \src "ls180.v:6378.113-6378.159"
+ cell $eq $eq$ls180.v:6378$2127
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:6329$2112_Y
+ connect \Y $eq$ls180.v:6378$2127_Y
end
- attribute \src "ls180.v:6330.116-6330.162"
- cell $eq $eq$ls180.v:6330$2116
+ attribute \src "ls180.v:6379.116-6379.162"
+ cell $eq $eq$ls180.v:6379$2131
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:6330$2116_Y
+ connect \Y $eq$ls180.v:6379$2131_Y
end
- attribute \src "ls180.v:6332.104-6332.150"
- cell $eq $eq$ls180.v:6332$2119
+ attribute \src "ls180.v:6381.104-6381.150"
+ cell $eq $eq$ls180.v:6381$2134
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:6332$2119_Y
+ connect \Y $eq$ls180.v:6381$2134_Y
end
- attribute \src "ls180.v:6333.107-6333.153"
- cell $eq $eq$ls180.v:6333$2123
+ attribute \src "ls180.v:6382.107-6382.153"
+ cell $eq $eq$ls180.v:6382$2138
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_adr [4:0]
+ connect \A \builder_interface12_bank_bus_adr [4:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:6333$2123_Y
+ connect \Y $eq$ls180.v:6382$2138_Y
end
- attribute \src "ls180.v:6350.33-6350.79"
- cell $eq $eq$ls180.v:6350$2125
+ attribute \src "ls180.v:6399.33-6399.79"
+ cell $eq $eq$ls180.v:6399$2140
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [13:9]
+ connect \A \builder_interface13_bank_bus_adr [13:9]
connect \B 3'101
- connect \Y $eq$ls180.v:6350$2125_Y
+ connect \Y $eq$ls180.v:6399$2140_Y
end
- attribute \src "ls180.v:6352.90-6352.135"
- cell $eq $eq$ls180.v:6352$2127
+ attribute \src "ls180.v:6401.90-6401.135"
+ cell $eq $eq$ls180.v:6401$2142
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6352$2127_Y
+ connect \Y $eq$ls180.v:6401$2142_Y
end
- attribute \src "ls180.v:6353.93-6353.138"
- cell $eq $eq$ls180.v:6353$2131
+ attribute \src "ls180.v:6402.93-6402.138"
+ cell $eq $eq$ls180.v:6402$2146
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6353$2131_Y
+ connect \Y $eq$ls180.v:6402$2146_Y
end
- attribute \src "ls180.v:6355.100-6355.145"
- cell $eq $eq$ls180.v:6355$2134
+ attribute \src "ls180.v:6404.100-6404.145"
+ cell $eq $eq$ls180.v:6404$2149
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6355$2134_Y
+ connect \Y $eq$ls180.v:6404$2149_Y
end
- attribute \src "ls180.v:6356.103-6356.148"
- cell $eq $eq$ls180.v:6356$2138
+ attribute \src "ls180.v:6405.103-6405.148"
+ cell $eq $eq$ls180.v:6405$2153
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6356$2138_Y
+ connect \Y $eq$ls180.v:6405$2153_Y
end
- attribute \src "ls180.v:6358.101-6358.146"
- cell $eq $eq$ls180.v:6358$2141
+ attribute \src "ls180.v:6407.101-6407.146"
+ cell $eq $eq$ls180.v:6407$2156
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6358$2141_Y
+ connect \Y $eq$ls180.v:6407$2156_Y
end
- attribute \src "ls180.v:6359.104-6359.149"
- cell $eq $eq$ls180.v:6359$2145
+ attribute \src "ls180.v:6408.104-6408.149"
+ cell $eq $eq$ls180.v:6408$2160
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6359$2145_Y
+ connect \Y $eq$ls180.v:6408$2160_Y
end
- attribute \src "ls180.v:6361.105-6361.150"
- cell $eq $eq$ls180.v:6361$2148
+ attribute \src "ls180.v:6410.105-6410.150"
+ cell $eq $eq$ls180.v:6410$2163
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6361$2148_Y
+ connect \Y $eq$ls180.v:6410$2163_Y
end
- attribute \src "ls180.v:6362.108-6362.153"
- cell $eq $eq$ls180.v:6362$2152
+ attribute \src "ls180.v:6411.108-6411.153"
+ cell $eq $eq$ls180.v:6411$2167
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6362$2152_Y
+ connect \Y $eq$ls180.v:6411$2167_Y
end
- attribute \src "ls180.v:6364.106-6364.151"
- cell $eq $eq$ls180.v:6364$2155
+ attribute \src "ls180.v:6413.106-6413.151"
+ cell $eq $eq$ls180.v:6413$2170
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6364$2155_Y
+ connect \Y $eq$ls180.v:6413$2170_Y
end
- attribute \src "ls180.v:6365.109-6365.154"
- cell $eq $eq$ls180.v:6365$2159
+ attribute \src "ls180.v:6414.109-6414.154"
+ cell $eq $eq$ls180.v:6414$2174
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:6365$2159_Y
+ connect \Y $eq$ls180.v:6414$2174_Y
end
- attribute \src "ls180.v:6367.104-6367.149"
- cell $eq $eq$ls180.v:6367$2162
+ attribute \src "ls180.v:6416.104-6416.149"
+ cell $eq $eq$ls180.v:6416$2177
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6367$2162_Y
+ connect \Y $eq$ls180.v:6416$2177_Y
end
- attribute \src "ls180.v:6368.107-6368.152"
- cell $eq $eq$ls180.v:6368$2166
+ attribute \src "ls180.v:6417.107-6417.152"
+ cell $eq $eq$ls180.v:6417$2181
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:6368$2166_Y
+ connect \Y $eq$ls180.v:6417$2181_Y
end
- attribute \src "ls180.v:6370.101-6370.146"
- cell $eq $eq$ls180.v:6370$2169
+ attribute \src "ls180.v:6419.101-6419.146"
+ cell $eq $eq$ls180.v:6419$2184
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6370$2169_Y
+ connect \Y $eq$ls180.v:6419$2184_Y
end
- attribute \src "ls180.v:6371.104-6371.149"
- cell $eq $eq$ls180.v:6371$2173
+ attribute \src "ls180.v:6420.104-6420.149"
+ cell $eq $eq$ls180.v:6420$2188
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'110
- connect \Y $eq$ls180.v:6371$2173_Y
+ connect \Y $eq$ls180.v:6420$2188_Y
end
- attribute \src "ls180.v:6373.100-6373.145"
- cell $eq $eq$ls180.v:6373$2176
+ attribute \src "ls180.v:6422.100-6422.145"
+ cell $eq $eq$ls180.v:6422$2191
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6373$2176_Y
+ connect \Y $eq$ls180.v:6422$2191_Y
end
- attribute \src "ls180.v:6374.103-6374.148"
- cell $eq $eq$ls180.v:6374$2180
+ attribute \src "ls180.v:6423.103-6423.148"
+ cell $eq $eq$ls180.v:6423$2195
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface12_bank_bus_adr [2:0]
+ connect \A \builder_interface13_bank_bus_adr [2:0]
connect \B 3'111
- connect \Y $eq$ls180.v:6374$2180_Y
+ connect \Y $eq$ls180.v:6423$2195_Y
end
- attribute \src "ls180.v:6384.33-6384.79"
- cell $eq $eq$ls180.v:6384$2182
+ attribute \src "ls180.v:6433.33-6433.79"
+ cell $eq $eq$ls180.v:6433$2197
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
- connect \A \builder_interface13_bank_bus_adr [13:9]
+ connect \A \builder_interface14_bank_bus_adr [13:9]
connect \B 3'100
- connect \Y $eq$ls180.v:6384$2182_Y
+ connect \Y $eq$ls180.v:6433$2197_Y
end
- attribute \src "ls180.v:6386.106-6386.151"
- cell $eq $eq$ls180.v:6386$2184
+ attribute \src "ls180.v:6435.106-6435.151"
+ cell $eq $eq$ls180.v:6435$2199
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface13_bank_bus_adr [1:0]
+ connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6386$2184_Y
+ connect \Y $eq$ls180.v:6435$2199_Y
end
- attribute \src "ls180.v:6387.109-6387.154"
- cell $eq $eq$ls180.v:6387$2188
+ attribute \src "ls180.v:6436.109-6436.154"
+ cell $eq $eq$ls180.v:6436$2203
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface13_bank_bus_adr [1:0]
+ connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:6387$2188_Y
+ connect \Y $eq$ls180.v:6436$2203_Y
end
- attribute \src "ls180.v:6389.106-6389.151"
- cell $eq $eq$ls180.v:6389$2191
+ attribute \src "ls180.v:6438.106-6438.151"
+ cell $eq $eq$ls180.v:6438$2206
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface13_bank_bus_adr [1:0]
+ connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6389$2191_Y
+ connect \Y $eq$ls180.v:6438$2206_Y
end
- attribute \src "ls180.v:6390.109-6390.154"
- cell $eq $eq$ls180.v:6390$2195
+ attribute \src "ls180.v:6439.109-6439.154"
+ cell $eq $eq$ls180.v:6439$2210
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface13_bank_bus_adr [1:0]
+ connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:6390$2195_Y
+ connect \Y $eq$ls180.v:6439$2210_Y
end
- attribute \src "ls180.v:6392.106-6392.151"
- cell $eq $eq$ls180.v:6392$2198
+ attribute \src "ls180.v:6441.106-6441.151"
+ cell $eq $eq$ls180.v:6441$2213
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface13_bank_bus_adr [1:0]
+ connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6392$2198_Y
+ connect \Y $eq$ls180.v:6441$2213_Y
end
- attribute \src "ls180.v:6393.109-6393.154"
- cell $eq $eq$ls180.v:6393$2202
+ attribute \src "ls180.v:6442.109-6442.154"
+ cell $eq $eq$ls180.v:6442$2217
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface13_bank_bus_adr [1:0]
+ connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:6393$2202_Y
+ connect \Y $eq$ls180.v:6442$2217_Y
end
- attribute \src "ls180.v:6395.106-6395.151"
- cell $eq $eq$ls180.v:6395$2205
+ attribute \src "ls180.v:6444.106-6444.151"
+ cell $eq $eq$ls180.v:6444$2220
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface13_bank_bus_adr [1:0]
+ connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6395$2205_Y
+ connect \Y $eq$ls180.v:6444$2220_Y
end
- attribute \src "ls180.v:6396.109-6396.154"
- cell $eq $eq$ls180.v:6396$2209
+ attribute \src "ls180.v:6445.109-6445.154"
+ cell $eq $eq$ls180.v:6445$2224
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A \builder_interface13_bank_bus_adr [1:0]
+ connect \A \builder_interface14_bank_bus_adr [1:0]
connect \B 2'11
- connect \Y $eq$ls180.v:6396$2209_Y
+ connect \Y $eq$ls180.v:6445$2224_Y
end
- attribute \src "ls180.v:6774.41-6774.81"
- cell $eq $eq$ls180.v:6774$2245
+ attribute \src "ls180.v:6826.41-6826.81"
+ cell $eq $eq$ls180.v:6826$2261
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 1'0
- connect \Y $eq$ls180.v:6774$2245_Y
+ connect \Y $eq$ls180.v:6826$2261_Y
end
- attribute \src "ls180.v:6774.144-6774.177"
- cell $eq $eq$ls180.v:6774$2246
+ attribute \src "ls180.v:6826.144-6826.177"
+ cell $eq $eq$ls180.v:6826$2262
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6774$2246_Y
+ connect \Y $eq$ls180.v:6826$2262_Y
end
- attribute \src "ls180.v:6774.219-6774.252"
- cell $eq $eq$ls180.v:6774$2249
+ attribute \src "ls180.v:6826.219-6826.252"
+ cell $eq $eq$ls180.v:6826$2265
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6774$2249_Y
+ connect \Y $eq$ls180.v:6826$2265_Y
end
- attribute \src "ls180.v:6774.294-6774.327"
- cell $eq $eq$ls180.v:6774$2252
+ attribute \src "ls180.v:6826.294-6826.327"
+ cell $eq $eq$ls180.v:6826$2268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6774$2252_Y
+ connect \Y $eq$ls180.v:6826$2268_Y
end
- attribute \src "ls180.v:6798.41-6798.81"
- cell $eq $eq$ls180.v:6798$2261
+ attribute \src "ls180.v:6850.41-6850.81"
+ cell $eq $eq$ls180.v:6850$2277
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 1'1
- connect \Y $eq$ls180.v:6798$2261_Y
+ connect \Y $eq$ls180.v:6850$2277_Y
end
- attribute \src "ls180.v:6798.144-6798.177"
- cell $eq $eq$ls180.v:6798$2262
+ attribute \src "ls180.v:6850.144-6850.177"
+ cell $eq $eq$ls180.v:6850$2278
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6798$2262_Y
+ connect \Y $eq$ls180.v:6850$2278_Y
end
- attribute \src "ls180.v:6798.219-6798.252"
- cell $eq $eq$ls180.v:6798$2265
+ attribute \src "ls180.v:6850.219-6850.252"
+ cell $eq $eq$ls180.v:6850$2281
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6798$2265_Y
+ connect \Y $eq$ls180.v:6850$2281_Y
end
- attribute \src "ls180.v:6798.294-6798.327"
- cell $eq $eq$ls180.v:6798$2268
+ attribute \src "ls180.v:6850.294-6850.327"
+ cell $eq $eq$ls180.v:6850$2284
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6798$2268_Y
+ connect \Y $eq$ls180.v:6850$2284_Y
end
- attribute \src "ls180.v:6822.41-6822.81"
- cell $eq $eq$ls180.v:6822$2277
+ attribute \src "ls180.v:6874.41-6874.81"
+ cell $eq $eq$ls180.v:6874$2293
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 2'10
- connect \Y $eq$ls180.v:6822$2277_Y
+ connect \Y $eq$ls180.v:6874$2293_Y
end
- attribute \src "ls180.v:6822.144-6822.177"
- cell $eq $eq$ls180.v:6822$2278
+ attribute \src "ls180.v:6874.144-6874.177"
+ cell $eq $eq$ls180.v:6874$2294
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6822$2278_Y
+ connect \Y $eq$ls180.v:6874$2294_Y
end
- attribute \src "ls180.v:6822.219-6822.252"
- cell $eq $eq$ls180.v:6822$2281
+ attribute \src "ls180.v:6874.219-6874.252"
+ cell $eq $eq$ls180.v:6874$2297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6822$2281_Y
+ connect \Y $eq$ls180.v:6874$2297_Y
end
- attribute \src "ls180.v:6822.294-6822.327"
- cell $eq $eq$ls180.v:6822$2284
+ attribute \src "ls180.v:6874.294-6874.327"
+ cell $eq $eq$ls180.v:6874$2300
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6822$2284_Y
+ connect \Y $eq$ls180.v:6874$2300_Y
end
- attribute \src "ls180.v:6846.41-6846.81"
- cell $eq $eq$ls180.v:6846$2293
+ attribute \src "ls180.v:6898.41-6898.81"
+ cell $eq $eq$ls180.v:6898$2309
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_addr [10:9]
connect \B 2'11
- connect \Y $eq$ls180.v:6846$2293_Y
+ connect \Y $eq$ls180.v:6898$2309_Y
end
- attribute \src "ls180.v:6846.144-6846.177"
- cell $eq $eq$ls180.v:6846$2294
+ attribute \src "ls180.v:6898.144-6898.177"
+ cell $eq $eq$ls180.v:6898$2310
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6846$2294_Y
+ connect \Y $eq$ls180.v:6898$2310_Y
end
- attribute \src "ls180.v:6846.219-6846.252"
- cell $eq $eq$ls180.v:6846$2297
+ attribute \src "ls180.v:6898.219-6898.252"
+ cell $eq $eq$ls180.v:6898$2313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6846$2297_Y
+ connect \Y $eq$ls180.v:6898$2313_Y
end
- attribute \src "ls180.v:6846.294-6846.327"
- cell $eq $eq$ls180.v:6846$2300
+ attribute \src "ls180.v:6898.294-6898.327"
+ cell $eq $eq$ls180.v:6898$2316
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:6846$2300_Y
+ connect \Y $eq$ls180.v:6898$2316_Y
end
- attribute \src "ls180.v:7445.8-7445.38"
- cell $eq $eq$ls180.v:7445$2409
+ attribute \src "ls180.v:7491.8-7491.38"
+ cell $eq $eq$ls180.v:7491$2419
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_value
connect \B 1'0
- connect \Y $eq$ls180.v:7445$2409_Y
+ connect \Y $eq$ls180.v:7491$2419_Y
end
- attribute \src "ls180.v:7476.8-7476.42"
- cell $eq $eq$ls180.v:7476$2417
+ attribute \src "ls180.v:7522.8-7522.42"
+ cell $eq $eq$ls180.v:7522$2427
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_postponer_count
connect \B 1'0
- connect \Y $eq$ls180.v:7476$2417_Y
+ connect \Y $eq$ls180.v:7522$2427_Y
end
- attribute \src "ls180.v:7496.38-7496.74"
- cell $eq $eq$ls180.v:7496$2420
+ attribute \src "ls180.v:7542.38-7542.74"
+ cell $eq $eq$ls180.v:7542$2430
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_counter
connect \B 1'0
- connect \Y $eq$ls180.v:7496$2420_Y
+ connect \Y $eq$ls180.v:7542$2430_Y
end
- attribute \src "ls180.v:7503.7-7503.43"
- cell $eq $eq$ls180.v:7503$2422
+ attribute \src "ls180.v:7549.7-7549.43"
+ cell $eq $eq$ls180.v:7549$2432
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_counter
connect \B 2'10
- connect \Y $eq$ls180.v:7503$2422_Y
+ connect \Y $eq$ls180.v:7549$2432_Y
end
- attribute \src "ls180.v:7510.7-7510.43"
- cell $eq $eq$ls180.v:7510$2423
+ attribute \src "ls180.v:7556.7-7556.43"
+ cell $eq $eq$ls180.v:7556$2433
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_counter
connect \B 4'1000
- connect \Y $eq$ls180.v:7510$2423_Y
+ connect \Y $eq$ls180.v:7556$2433_Y
end
- attribute \src "ls180.v:7518.7-7518.43"
- cell $eq $eq$ls180.v:7518$2424
+ attribute \src "ls180.v:7564.7-7564.43"
+ cell $eq $eq$ls180.v:7564$2434
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_counter
connect \B 4'1000
- connect \Y $eq$ls180.v:7518$2424_Y
+ connect \Y $eq$ls180.v:7564$2434_Y
end
- attribute \src "ls180.v:7570.9-7570.54"
- cell $eq $eq$ls180.v:7570$2442
+ attribute \src "ls180.v:7616.9-7616.54"
+ cell $eq $eq$ls180.v:7616$2452
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_twtpcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:7570$2442_Y
+ connect \Y $eq$ls180.v:7616$2452_Y
end
- attribute \src "ls180.v:7616.9-7616.54"
- cell $eq $eq$ls180.v:7616$2458
+ attribute \src "ls180.v:7662.9-7662.54"
+ cell $eq $eq$ls180.v:7662$2468
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_twtpcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:7616$2458_Y
+ connect \Y $eq$ls180.v:7662$2468_Y
end
- attribute \src "ls180.v:7662.9-7662.54"
- cell $eq $eq$ls180.v:7662$2474
+ attribute \src "ls180.v:7708.9-7708.54"
+ cell $eq $eq$ls180.v:7708$2484
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_twtpcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:7662$2474_Y
+ connect \Y $eq$ls180.v:7708$2484_Y
end
- attribute \src "ls180.v:7708.9-7708.54"
- cell $eq $eq$ls180.v:7708$2490
+ attribute \src "ls180.v:7754.9-7754.54"
+ cell $eq $eq$ls180.v:7754$2500
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_twtpcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:7708$2490_Y
+ connect \Y $eq$ls180.v:7754$2500_Y
end
- attribute \src "ls180.v:7858.9-7858.41"
- cell $eq $eq$ls180.v:7858$2502
+ attribute \src "ls180.v:7904.9-7904.41"
+ cell $eq $eq$ls180.v:7904$2512
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_tccdcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:7858$2502_Y
+ connect \Y $eq$ls180.v:7904$2512_Y
end
- attribute \src "ls180.v:7873.9-7873.41"
- cell $eq $eq$ls180.v:7873$2505
+ attribute \src "ls180.v:7919.9-7919.41"
+ cell $eq $eq$ls180.v:7919$2515
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_twtrcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:7873$2505_Y
+ connect \Y $eq$ls180.v:7919$2515_Y
end
- attribute \src "ls180.v:7879.49-7879.82"
- cell $eq $eq$ls180.v:7879$2506
+ attribute \src "ls180.v:7925.49-7925.82"
+ cell $eq $eq$ls180.v:7925$2516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7879$2506_Y
+ connect \Y $eq$ls180.v:7925$2516_Y
end
- attribute \src "ls180.v:7879.131-7879.164"
- cell $eq $eq$ls180.v:7879$2509
+ attribute \src "ls180.v:7925.131-7925.164"
+ cell $eq $eq$ls180.v:7925$2519
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7879$2509_Y
+ connect \Y $eq$ls180.v:7925$2519_Y
end
- attribute \src "ls180.v:7879.213-7879.246"
- cell $eq $eq$ls180.v:7879$2512
+ attribute \src "ls180.v:7925.213-7925.246"
+ cell $eq $eq$ls180.v:7925$2522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7879$2512_Y
+ connect \Y $eq$ls180.v:7925$2522_Y
end
- attribute \src "ls180.v:7879.295-7879.328"
- cell $eq $eq$ls180.v:7879$2515
+ attribute \src "ls180.v:7925.295-7925.328"
+ cell $eq $eq$ls180.v:7925$2525
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7879$2515_Y
+ connect \Y $eq$ls180.v:7925$2525_Y
end
- attribute \src "ls180.v:7880.50-7880.83"
- cell $eq $eq$ls180.v:7880$2518
+ attribute \src "ls180.v:7926.50-7926.83"
+ cell $eq $eq$ls180.v:7926$2528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7880$2518_Y
+ connect \Y $eq$ls180.v:7926$2528_Y
end
- attribute \src "ls180.v:7880.132-7880.165"
- cell $eq $eq$ls180.v:7880$2521
+ attribute \src "ls180.v:7926.132-7926.165"
+ cell $eq $eq$ls180.v:7926$2531
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7880$2521_Y
+ connect \Y $eq$ls180.v:7926$2531_Y
end
- attribute \src "ls180.v:7880.214-7880.247"
- cell $eq $eq$ls180.v:7880$2524
+ attribute \src "ls180.v:7926.214-7926.247"
+ cell $eq $eq$ls180.v:7926$2534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7880$2524_Y
+ connect \Y $eq$ls180.v:7926$2534_Y
end
- attribute \src "ls180.v:7880.296-7880.329"
- cell $eq $eq$ls180.v:7880$2527
+ attribute \src "ls180.v:7926.296-7926.329"
+ cell $eq $eq$ls180.v:7926$2537
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:7880$2527_Y
+ connect \Y $eq$ls180.v:7926$2537_Y
end
- attribute \src "ls180.v:7915.9-7915.33"
- cell $eq $eq$ls180.v:7915$2539
+ attribute \src "ls180.v:7961.9-7961.42"
+ cell $eq $eq$ls180.v:7961$2549
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \main_tx_bitcount
+ connect \A \main_uart_phy_tx_bitcount
connect \B 4'1000
- connect \Y $eq$ls180.v:7915$2539_Y
+ connect \Y $eq$ls180.v:7961$2549_Y
end
- attribute \src "ls180.v:7918.10-7918.34"
- cell $eq $eq$ls180.v:7918$2540
+ attribute \src "ls180.v:7964.10-7964.43"
+ cell $eq $eq$ls180.v:7964$2550
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \main_tx_bitcount
+ connect \A \main_uart_phy_tx_bitcount
connect \B 4'1001
- connect \Y $eq$ls180.v:7918$2540_Y
+ connect \Y $eq$ls180.v:7964$2550_Y
end
- attribute \src "ls180.v:7944.9-7944.33"
- cell $eq $eq$ls180.v:7944$2546
+ attribute \src "ls180.v:7990.9-7990.42"
+ cell $eq $eq$ls180.v:7990$2556
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_rx_bitcount
+ connect \A \main_uart_phy_rx_bitcount
connect \B 1'0
- connect \Y $eq$ls180.v:7944$2546_Y
+ connect \Y $eq$ls180.v:7990$2556_Y
end
- attribute \src "ls180.v:7949.10-7949.34"
- cell $eq $eq$ls180.v:7949$2547
+ attribute \src "ls180.v:7995.10-7995.43"
+ cell $eq $eq$ls180.v:7995$2557
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
- connect \A \main_rx_bitcount
+ connect \A \main_uart_phy_rx_bitcount
connect \B 4'1001
- connect \Y $eq$ls180.v:7949$2547_Y
+ connect \Y $eq$ls180.v:7995$2557_Y
end
- attribute \src "ls180.v:8121.9-8121.53"
- cell $eq $eq$ls180.v:8121$2591
+ attribute \src "ls180.v:8167.9-8167.53"
+ cell $eq $eq$ls180.v:8167$2601
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_demux
connect \B 3'111
- connect \Y $eq$ls180.v:8121$2591_Y
+ connect \Y $eq$ls180.v:8167$2601_Y
end
- attribute \src "ls180.v:8202.9-8202.54"
- cell $eq $eq$ls180.v:8202$2603
+ attribute \src "ls180.v:8248.9-8248.54"
+ cell $eq $eq$ls180.v:8248$2613
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_demux
connect \B 3'111
- connect \Y $eq$ls180.v:8202$2603_Y
+ connect \Y $eq$ls180.v:8248$2613_Y
end
- attribute \src "ls180.v:8281.9-8281.55"
- cell $eq $eq$ls180.v:8281$2615
+ attribute \src "ls180.v:8327.9-8327.55"
+ cell $eq $eq$ls180.v:8327$2625
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_demux
connect \B 1'1
- connect \Y $eq$ls180.v:8281$2615_Y
+ connect \Y $eq$ls180.v:8327$2625_Y
end
- attribute \src "ls180.v:8504.9-8504.49"
- cell $eq $eq$ls180.v:8504$2648
+ attribute \src "ls180.v:8550.9-8550.49"
+ cell $eq $eq$ls180.v:8550$2658
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_demux
connect \B 2'11
- connect \Y $eq$ls180.v:8504$2648_Y
+ connect \Y $eq$ls180.v:8550$2658_Y
end
- attribute \src "ls180.v:8080.8-8080.54"
- cell $ge $ge$ls180.v:8080$2583
+ attribute \src "ls180.v:8126.8-8126.54"
+ cell $ge $ge$ls180.v:8126$2593
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_pwm0_counter
- connect \B $sub$ls180.v:8080$2582_Y
- connect \Y $ge$ls180.v:8080$2583_Y
+ connect \B $sub$ls180.v:8126$2592_Y
+ connect \Y $ge$ls180.v:8126$2593_Y
end
- attribute \src "ls180.v:8094.8-8094.54"
- cell $ge $ge$ls180.v:8094$2587
+ attribute \src "ls180.v:8140.8-8140.54"
+ cell $ge $ge$ls180.v:8140$2597
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \main_pwm1_counter
- connect \B $sub$ls180.v:8094$2586_Y
- connect \Y $ge$ls180.v:8094$2587_Y
+ connect \B $sub$ls180.v:8140$2596_Y
+ connect \Y $ge$ls180.v:8140$2597_Y
end
- attribute \src "ls180.v:5041.47-5041.83"
- cell $gt $gt$ls180.v:5041$906
+ attribute \src "ls180.v:5076.47-5076.83"
+ cell $gt $gt$ls180.v:5076$906
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 3'111
- connect \Y $gt$ls180.v:5041$906_Y
+ connect \Y $gt$ls180.v:5076$906_Y
end
- attribute \src "ls180.v:5047.7-5047.43"
- cell $lt $lt$ls180.v:5047$909
+ attribute \src "ls180.v:5082.7-5082.43"
+ cell $lt $lt$ls180.v:5082$909
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 4'1000
- connect \Y $lt$ls180.v:5047$909_Y
+ connect \Y $lt$ls180.v:5082$909_Y
end
- attribute \src "ls180.v:8075.8-8075.43"
- cell $lt $lt$ls180.v:8075$2581
+ attribute \src "ls180.v:8121.8-8121.43"
+ cell $lt $lt$ls180.v:8121$2591
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_pwm0_counter
connect \B \main_pwm0_width
- connect \Y $lt$ls180.v:8075$2581_Y
+ connect \Y $lt$ls180.v:8121$2591_Y
end
- attribute \src "ls180.v:8089.8-8089.43"
- cell $lt $lt$ls180.v:8089$2585
+ attribute \src "ls180.v:8135.8-8135.43"
+ cell $lt $lt$ls180.v:8135$2595
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_pwm1_counter
connect \B \main_pwm1_width
- connect \Y $lt$ls180.v:8089$2585_Y
+ connect \Y $lt$ls180.v:8135$2595_Y
end
- attribute \src "ls180.v:9989.33-9989.36"
- cell $memrd $memrd$\mem$ls180.v:9989$2695
+ attribute \src "ls180.v:10052.33-10052.36"
+ cell $memrd $memrd$\mem$ls180.v:10052$2705
parameter \ABITS 7
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 32
connect \ADDR \memadr
connect \CLK 1'x
- connect \DATA $memrd$\mem$ls180.v:9989$2695_DATA
+ connect \DATA $memrd$\mem$ls180.v:10052$2705_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10000.12-10000.19"
- cell $memrd $memrd$\storage$ls180.v:10000$2700
+ attribute \src "ls180.v:10063.12-10063.19"
+ cell $memrd $memrd$\storage$ls180.v:10063$2710
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage$ls180.v:10000$2700_DATA
+ connect \DATA $memrd$\storage$ls180.v:10063$2710_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10007.68-10007.75"
- cell $memrd $memrd$\storage$ls180.v:10007$2702
+ attribute \src "ls180.v:10070.68-10070.75"
+ cell $memrd $memrd$\storage$ls180.v:10070$2712
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage$ls180.v:10007$2702_DATA
+ connect \DATA $memrd$\storage$ls180.v:10070$2712_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10014.14-10014.23"
- cell $memrd $memrd$\storage_1$ls180.v:10014$2707
+ attribute \src "ls180.v:10077.14-10077.23"
+ cell $memrd $memrd$\storage_1$ls180.v:10077$2717
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_1$ls180.v:10014$2707_DATA
+ connect \DATA $memrd$\storage_1$ls180.v:10077$2717_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10021.68-10021.77"
- cell $memrd $memrd$\storage_1$ls180.v:10021$2709
+ attribute \src "ls180.v:10084.68-10084.77"
+ cell $memrd $memrd$\storage_1$ls180.v:10084$2719
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_1$ls180.v:10021$2709_DATA
+ connect \DATA $memrd$\storage_1$ls180.v:10084$2719_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10028.14-10028.23"
- cell $memrd $memrd$\storage_2$ls180.v:10028$2714
+ attribute \src "ls180.v:10091.14-10091.23"
+ cell $memrd $memrd$\storage_2$ls180.v:10091$2724
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_2$ls180.v:10028$2714_DATA
+ connect \DATA $memrd$\storage_2$ls180.v:10091$2724_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10035.68-10035.77"
- cell $memrd $memrd$\storage_2$ls180.v:10035$2716
+ attribute \src "ls180.v:10098.68-10098.77"
+ cell $memrd $memrd$\storage_2$ls180.v:10098$2726
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_2$ls180.v:10035$2716_DATA
+ connect \DATA $memrd$\storage_2$ls180.v:10098$2726_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10042.14-10042.23"
- cell $memrd $memrd$\storage_3$ls180.v:10042$2721
+ attribute \src "ls180.v:10105.14-10105.23"
+ cell $memrd $memrd$\storage_3$ls180.v:10105$2731
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_3$ls180.v:10042$2721_DATA
+ connect \DATA $memrd$\storage_3$ls180.v:10105$2731_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10049.68-10049.77"
- cell $memrd $memrd$\storage_3$ls180.v:10049$2723
+ attribute \src "ls180.v:10112.68-10112.77"
+ cell $memrd $memrd$\storage_3$ls180.v:10112$2733
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_3$ls180.v:10049$2723_DATA
+ connect \DATA $memrd$\storage_3$ls180.v:10112$2733_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10057.14-10057.23"
- cell $memrd $memrd$\storage_4$ls180.v:10057$2728
+ attribute \src "ls180.v:10120.14-10120.23"
+ cell $memrd $memrd$\storage_4$ls180.v:10120$2738
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_uart_tx_fifo_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_4$ls180.v:10057$2728_DATA
+ connect \DATA $memrd$\storage_4$ls180.v:10120$2738_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10062.15-10062.24"
- cell $memrd $memrd$\storage_4$ls180.v:10062$2730
+ attribute \src "ls180.v:10125.15-10125.24"
+ cell $memrd $memrd$\storage_4$ls180.v:10125$2740
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_uart_tx_fifo_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_4$ls180.v:10062$2730_DATA
+ connect \DATA $memrd$\storage_4$ls180.v:10125$2740_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10074.14-10074.23"
- cell $memrd $memrd$\storage_5$ls180.v:10074$2735
+ attribute \src "ls180.v:10137.14-10137.23"
+ cell $memrd $memrd$\storage_5$ls180.v:10137$2745
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_uart_rx_fifo_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_5$ls180.v:10074$2735_DATA
+ connect \DATA $memrd$\storage_5$ls180.v:10137$2745_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10079.15-10079.24"
- cell $memrd $memrd$\storage_5$ls180.v:10079$2737
+ attribute \src "ls180.v:10142.15-10142.24"
+ cell $memrd $memrd$\storage_5$ls180.v:10142$2747
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_uart_rx_fifo_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_5$ls180.v:10079$2737_DATA
+ connect \DATA $memrd$\storage_5$ls180.v:10142$2747_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10090.14-10090.23"
- cell $memrd $memrd$\storage_6$ls180.v:10090$2742
+ attribute \src "ls180.v:10153.14-10153.23"
+ cell $memrd $memrd$\storage_6$ls180.v:10153$2752
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_sdblock2mem_fifo_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_6$ls180.v:10090$2742_DATA
+ connect \DATA $memrd$\storage_6$ls180.v:10153$2752_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10097.45-10097.54"
- cell $memrd $memrd$\storage_6$ls180.v:10097$2744
+ attribute \src "ls180.v:10160.45-10160.54"
+ cell $memrd $memrd$\storage_6$ls180.v:10160$2754
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_sdblock2mem_fifo_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_6$ls180.v:10097$2744_DATA
+ connect \DATA $memrd$\storage_6$ls180.v:10160$2754_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10104.14-10104.23"
- cell $memrd $memrd$\storage_7$ls180.v:10104$2749
+ attribute \src "ls180.v:10167.14-10167.23"
+ cell $memrd $memrd$\storage_7$ls180.v:10167$2759
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_sdmem2block_fifo_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_7$ls180.v:10104$2749_DATA
+ connect \DATA $memrd$\storage_7$ls180.v:10167$2759_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:10111.45-10111.54"
- cell $memrd $memrd$\storage_7$ls180.v:10111$2751
+ attribute \src "ls180.v:10174.45-10174.54"
+ cell $memrd $memrd$\storage_7$ls180.v:10174$2761
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \main_sdmem2block_fifo_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_7$ls180.v:10111$2751_DATA
+ connect \DATA $memrd$\storage_7$ls180.v:10174$2761_DATA
connect \EN 1'x
end
attribute \src "ls180.v:0.0-0.0"
- cell $memwr $memwr$\mem$ls180.v:0$2753
+ cell $memwr $memwr$\mem$ls180.v:0$2763
parameter \ABITS 7
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
- parameter \PRIORITY 2753
+ parameter \PRIORITY 2763
parameter \WIDTH 32
- connect \ADDR $memwr$\mem$ls180.v:9979$1_ADDR
+ connect \ADDR $memwr$\mem$ls180.v:10042$1_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\mem$ls180.v:9979$1_DATA
- connect \EN $memwr$\mem$ls180.v:9979$1_EN
+ connect \DATA $memwr$\mem$ls180.v:10042$1_DATA
+ connect \EN $memwr$\mem$ls180.v:10042$1_EN
end
attribute \src "ls180.v:0.0-0.0"
- cell $memwr $memwr$\mem$ls180.v:0$2754
+ cell $memwr $memwr$\mem$ls180.v:0$2764
parameter \ABITS 7
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
- parameter \PRIORITY 2754
+ parameter \PRIORITY 2764
parameter \WIDTH 32
- connect \ADDR $memwr$\mem$ls180.v:9981$2_ADDR
+ connect \ADDR $memwr$\mem$ls180.v:10044$2_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\mem$ls180.v:9981$2_DATA
- connect \EN $memwr$\mem$ls180.v:9981$2_EN
+ connect \DATA $memwr$\mem$ls180.v:10044$2_DATA
+ connect \EN $memwr$\mem$ls180.v:10044$2_EN
end
attribute \src "ls180.v:0.0-0.0"
- cell $memwr $memwr$\mem$ls180.v:0$2755
+ cell $memwr $memwr$\mem$ls180.v:0$2765
parameter \ABITS 7
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
- parameter \PRIORITY 2755
+ parameter \PRIORITY 2765
parameter \WIDTH 32
- connect \ADDR $memwr$\mem$ls180.v:9983$3_ADDR
+ connect \ADDR $memwr$\mem$ls180.v:10046$3_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\mem$ls180.v:9983$3_DATA
- connect \EN $memwr$\mem$ls180.v:9983$3_EN
+ connect \DATA $memwr$\mem$ls180.v:10046$3_DATA
+ connect \EN $memwr$\mem$ls180.v:10046$3_EN
end
attribute \src "ls180.v:0.0-0.0"
- cell $memwr $memwr$\mem$ls180.v:0$2756
+ cell $memwr $memwr$\mem$ls180.v:0$2766
parameter \ABITS 7
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
- parameter \PRIORITY 2756
+ parameter \PRIORITY 2766
parameter \WIDTH 32
- connect \ADDR $memwr$\mem$ls180.v:9985$4_ADDR
+ connect \ADDR $memwr$\mem$ls180.v:10048$4_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\mem$ls180.v:9985$4_DATA
- connect \EN $memwr$\mem$ls180.v:9985$4_EN
+ connect \DATA $memwr$\mem$ls180.v:10048$4_DATA
+ connect \EN $memwr$\mem$ls180.v:10048$4_EN
end
attribute \src "ls180.v:0.0-0.0"
- cell $memwr $memwr$\storage$ls180.v:0$2757
+ cell $memwr $memwr$\storage$ls180.v:0$2767
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\storage"
- parameter \PRIORITY 2757
+ parameter \PRIORITY 2767
parameter \WIDTH 25
- connect \ADDR $memwr$\storage$ls180.v:9999$5_ADDR
+ connect \ADDR $memwr$\storage$ls180.v:10062$5_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage$ls180.v:9999$5_DATA
- connect \EN $memwr$\storage$ls180.v:9999$5_EN
+ connect \DATA $memwr$\storage$ls180.v:10062$5_DATA
+ connect \EN $memwr$\storage$ls180.v:10062$5_EN
end
attribute \src "ls180.v:0.0-0.0"
- cell $memwr $memwr$\storage_1$ls180.v:0$2758
+ cell $memwr $memwr$\storage_1$ls180.v:0$2768
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\storage_1"
- parameter \PRIORITY 2758
+ parameter \PRIORITY 2768
parameter \WIDTH 25
- connect \ADDR $memwr$\storage_1$ls180.v:10013$6_ADDR
+ connect \ADDR $memwr$\storage_1$ls180.v:10076$6_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_1$ls180.v:10013$6_DATA
- connect \EN $memwr$\storage_1$ls180.v:10013$6_EN
+ connect \DATA $memwr$\storage_1$ls180.v:10076$6_DATA
+ connect \EN $memwr$\storage_1$ls180.v:10076$6_EN
end
attribute \src "ls180.v:0.0-0.0"
- cell $memwr $memwr$\storage_2$ls180.v:0$2759
+ cell $memwr $memwr$\storage_2$ls180.v:0$2769
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\storage_2"
- parameter \PRIORITY 2759
+ parameter \PRIORITY 2769
parameter \WIDTH 25
- connect \ADDR $memwr$\storage_2$ls180.v:10027$7_ADDR
+ connect \ADDR $memwr$\storage_2$ls180.v:10090$7_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_2$ls180.v:10027$7_DATA
- connect \EN $memwr$\storage_2$ls180.v:10027$7_EN
+ connect \DATA $memwr$\storage_2$ls180.v:10090$7_DATA
+ connect \EN $memwr$\storage_2$ls180.v:10090$7_EN
end
attribute \src "ls180.v:0.0-0.0"
- cell $memwr $memwr$\storage_3$ls180.v:0$2760
+ cell $memwr $memwr$\storage_3$ls180.v:0$2770
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\storage_3"
- parameter \PRIORITY 2760
+ parameter \PRIORITY 2770
parameter \WIDTH 25
- connect \ADDR $memwr$\storage_3$ls180.v:10041$8_ADDR
+ connect \ADDR $memwr$\storage_3$ls180.v:10104$8_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_3$ls180.v:10041$8_DATA
- connect \EN $memwr$\storage_3$ls180.v:10041$8_EN
+ connect \DATA $memwr$\storage_3$ls180.v:10104$8_DATA
+ connect \EN $memwr$\storage_3$ls180.v:10104$8_EN
end
attribute \src "ls180.v:0.0-0.0"
- cell $memwr $memwr$\storage_4$ls180.v:0$2761
+ cell $memwr $memwr$\storage_4$ls180.v:0$2771
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\storage_4"
- parameter \PRIORITY 2761
+ parameter \PRIORITY 2771
parameter \WIDTH 10
- connect \ADDR $memwr$\storage_4$ls180.v:10056$9_ADDR
+ connect \ADDR $memwr$\storage_4$ls180.v:10119$9_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_4$ls180.v:10056$9_DATA
- connect \EN $memwr$\storage_4$ls180.v:10056$9_EN
+ connect \DATA $memwr$\storage_4$ls180.v:10119$9_DATA
+ connect \EN $memwr$\storage_4$ls180.v:10119$9_EN
end
attribute \src "ls180.v:0.0-0.0"
- cell $memwr $memwr$\storage_5$ls180.v:0$2762
+ cell $memwr $memwr$\storage_5$ls180.v:0$2772
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\storage_5"
- parameter \PRIORITY 2762
+ parameter \PRIORITY 2772
parameter \WIDTH 10
- connect \ADDR $memwr$\storage_5$ls180.v:10073$10_ADDR
+ connect \ADDR $memwr$\storage_5$ls180.v:10136$10_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_5$ls180.v:10073$10_DATA
- connect \EN $memwr$\storage_5$ls180.v:10073$10_EN
+ connect \DATA $memwr$\storage_5$ls180.v:10136$10_DATA
+ connect \EN $memwr$\storage_5$ls180.v:10136$10_EN
end
attribute \src "ls180.v:0.0-0.0"
- cell $memwr $memwr$\storage_6$ls180.v:0$2763
+ cell $memwr $memwr$\storage_6$ls180.v:0$2773
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\storage_6"
- parameter \PRIORITY 2763
+ parameter \PRIORITY 2773
parameter \WIDTH 10
- connect \ADDR $memwr$\storage_6$ls180.v:10089$11_ADDR
+ connect \ADDR $memwr$\storage_6$ls180.v:10152$11_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_6$ls180.v:10089$11_DATA
- connect \EN $memwr$\storage_6$ls180.v:10089$11_EN
+ connect \DATA $memwr$\storage_6$ls180.v:10152$11_DATA
+ connect \EN $memwr$\storage_6$ls180.v:10152$11_EN
end
attribute \src "ls180.v:0.0-0.0"
- cell $memwr $memwr$\storage_7$ls180.v:0$2764
+ cell $memwr $memwr$\storage_7$ls180.v:0$2774
parameter \ABITS 5
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\storage_7"
- parameter \PRIORITY 2764
+ parameter \PRIORITY 2774
parameter \WIDTH 10
- connect \ADDR $memwr$\storage_7$ls180.v:10103$12_ADDR
+ connect \ADDR $memwr$\storage_7$ls180.v:10166$12_ADDR
connect \CLK 1'x
- connect \DATA $memwr$\storage_7$ls180.v:10103$12_DATA
- connect \EN $memwr$\storage_7$ls180.v:10103$12_EN
+ connect \DATA $memwr$\storage_7$ls180.v:10166$12_DATA
+ connect \EN $memwr$\storage_7$ls180.v:10166$12_EN
end
- attribute \src "ls180.v:2918.41-2918.71"
- cell $ne $ne$ls180.v:2918$60
+ attribute \src "ls180.v:2949.41-2949.71"
+ cell $ne $ne$ls180.v:2949$60
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_value
connect \B 1'0
- connect \Y $ne$ls180.v:2918$60_Y
+ connect \Y $ne$ls180.v:2949$60_Y
end
- attribute \src "ls180.v:3079.70-3079.104"
- cell $ne $ne$ls180.v:3079$74
+ attribute \src "ls180.v:3110.70-3110.104"
+ cell $ne $ne$ls180.v:3110$74
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_count
connect \B 1'0
- connect \Y $ne$ls180.v:3079$74_Y
+ connect \Y $ne$ls180.v:3110$74_Y
end
- attribute \src "ls180.v:3140.8-3140.142"
- cell $ne $ne$ls180.v:3140$93
+ attribute \src "ls180.v:3171.8-3171.142"
+ cell $ne $ne$ls180.v:3171$93
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9]
connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
- connect \Y $ne$ls180.v:3140$93_Y
+ connect \Y $ne$ls180.v:3171$93_Y
end
- attribute \src "ls180.v:3172.75-3172.133"
- cell $ne $ne$ls180.v:3172$100
+ attribute \src "ls180.v:3203.75-3203.133"
+ cell $ne $ne$ls180.v:3203$100
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
connect \B 4'1000
- connect \Y $ne$ls180.v:3172$100_Y
+ connect \Y $ne$ls180.v:3203$100_Y
end
- attribute \src "ls180.v:3173.75-3173.133"
- cell $ne $ne$ls180.v:3173$101
+ attribute \src "ls180.v:3204.75-3204.133"
+ cell $ne $ne$ls180.v:3204$101
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
connect \B 1'0
- connect \Y $ne$ls180.v:3173$101_Y
+ connect \Y $ne$ls180.v:3204$101_Y
end
- attribute \src "ls180.v:3297.8-3297.142"
- cell $ne $ne$ls180.v:3297$123
+ attribute \src "ls180.v:3328.8-3328.142"
+ cell $ne $ne$ls180.v:3328$123
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9]
connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
- connect \Y $ne$ls180.v:3297$123_Y
+ connect \Y $ne$ls180.v:3328$123_Y
end
- attribute \src "ls180.v:3329.75-3329.133"
- cell $ne $ne$ls180.v:3329$130
+ attribute \src "ls180.v:3360.75-3360.133"
+ cell $ne $ne$ls180.v:3360$130
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
connect \B 4'1000
- connect \Y $ne$ls180.v:3329$130_Y
+ connect \Y $ne$ls180.v:3360$130_Y
end
- attribute \src "ls180.v:3330.75-3330.133"
- cell $ne $ne$ls180.v:3330$131
+ attribute \src "ls180.v:3361.75-3361.133"
+ cell $ne $ne$ls180.v:3361$131
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
connect \B 1'0
- connect \Y $ne$ls180.v:3330$131_Y
+ connect \Y $ne$ls180.v:3361$131_Y
end
- attribute \src "ls180.v:3454.8-3454.142"
- cell $ne $ne$ls180.v:3454$153
+ attribute \src "ls180.v:3485.8-3485.142"
+ cell $ne $ne$ls180.v:3485$153
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9]
connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
- connect \Y $ne$ls180.v:3454$153_Y
+ connect \Y $ne$ls180.v:3485$153_Y
end
- attribute \src "ls180.v:3486.75-3486.133"
- cell $ne $ne$ls180.v:3486$160
+ attribute \src "ls180.v:3517.75-3517.133"
+ cell $ne $ne$ls180.v:3517$160
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
connect \B 4'1000
- connect \Y $ne$ls180.v:3486$160_Y
+ connect \Y $ne$ls180.v:3517$160_Y
end
- attribute \src "ls180.v:3487.75-3487.133"
- cell $ne $ne$ls180.v:3487$161
+ attribute \src "ls180.v:3518.75-3518.133"
+ cell $ne $ne$ls180.v:3518$161
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
connect \B 1'0
- connect \Y $ne$ls180.v:3487$161_Y
+ connect \Y $ne$ls180.v:3518$161_Y
end
- attribute \src "ls180.v:3611.8-3611.142"
- cell $ne $ne$ls180.v:3611$183
+ attribute \src "ls180.v:3642.8-3642.142"
+ cell $ne $ne$ls180.v:3642$183
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9]
connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
- connect \Y $ne$ls180.v:3611$183_Y
+ connect \Y $ne$ls180.v:3642$183_Y
end
- attribute \src "ls180.v:3643.75-3643.133"
- cell $ne $ne$ls180.v:3643$190
+ attribute \src "ls180.v:3674.75-3674.133"
+ cell $ne $ne$ls180.v:3674$190
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
connect \B 4'1000
- connect \Y $ne$ls180.v:3643$190_Y
+ connect \Y $ne$ls180.v:3674$190_Y
end
- attribute \src "ls180.v:3644.75-3644.133"
- cell $ne $ne$ls180.v:3644$191
+ attribute \src "ls180.v:3675.75-3675.133"
+ cell $ne $ne$ls180.v:3675$191
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
connect \B 1'0
- connect \Y $ne$ls180.v:3644$191_Y
+ connect \Y $ne$ls180.v:3675$191_Y
end
- attribute \src "ls180.v:4136.47-4136.80"
- cell $ne $ne$ls180.v:4136$589
+ attribute \src "ls180.v:4167.47-4167.80"
+ cell $ne $ne$ls180.v:4167$589
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_level0
connect \B 5'10000
- connect \Y $ne$ls180.v:4136$589_Y
+ connect \Y $ne$ls180.v:4167$589_Y
end
- attribute \src "ls180.v:4137.47-4137.79"
- cell $ne $ne$ls180.v:4137$590
+ attribute \src "ls180.v:4168.47-4168.79"
+ cell $ne $ne$ls180.v:4168$590
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_level0
connect \B 1'0
- connect \Y $ne$ls180.v:4137$590_Y
+ connect \Y $ne$ls180.v:4168$590_Y
end
- attribute \src "ls180.v:4166.47-4166.80"
- cell $ne $ne$ls180.v:4166$600
+ attribute \src "ls180.v:4197.47-4197.80"
+ cell $ne $ne$ls180.v:4197$600
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_level0
connect \B 5'10000
- connect \Y $ne$ls180.v:4166$600_Y
+ connect \Y $ne$ls180.v:4197$600_Y
end
- attribute \src "ls180.v:4167.47-4167.79"
- cell $ne $ne$ls180.v:4167$601
+ attribute \src "ls180.v:4198.47-4198.79"
+ cell $ne $ne$ls180.v:4198$601
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_level0
connect \B 1'0
- connect \Y $ne$ls180.v:4167$601_Y
+ connect \Y $ne$ls180.v:4198$601_Y
end
- attribute \src "ls180.v:4573.32-4573.89"
- cell $ne $ne$ls180.v:4573$673
+ attribute \src "ls180.v:4608.32-4608.89"
+ cell $ne $ne$ls180.v:4608$673
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_source_source_payload_data0
connect \B 3'101
- connect \Y $ne$ls180.v:4573$673_Y
+ connect \Y $ne$ls180.v:4608$673_Y
end
- attribute \src "ls180.v:5220.10-5220.56"
- cell $ne $ne$ls180.v:5220$970
+ attribute \src "ls180.v:5255.10-5255.56"
+ cell $ne $ne$ls180.v:5255$970
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_source_payload_status
connect \B 2'10
- connect \Y $ne$ls180.v:5220$970_Y
+ connect \Y $ne$ls180.v:5255$970_Y
end
- attribute \src "ls180.v:5325.51-5325.87"
- cell $ne $ne$ls180.v:5325$984
+ attribute \src "ls180.v:5360.51-5360.87"
+ cell $ne $ne$ls180.v:5360$984
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_level
connect \B 6'100000
- connect \Y $ne$ls180.v:5325$984_Y
+ connect \Y $ne$ls180.v:5360$984_Y
end
- attribute \src "ls180.v:5326.51-5326.86"
- cell $ne $ne$ls180.v:5326$985
+ attribute \src "ls180.v:5361.51-5361.86"
+ cell $ne $ne$ls180.v:5361$985
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_level
connect \B 1'0
- connect \Y $ne$ls180.v:5326$985_Y
+ connect \Y $ne$ls180.v:5361$985_Y
end
- attribute \src "ls180.v:5533.51-5533.87"
- cell $ne $ne$ls180.v:5533$1015
+ attribute \src "ls180.v:5568.51-5568.87"
+ cell $ne $ne$ls180.v:5568$1015
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_level
connect \B 6'100000
- connect \Y $ne$ls180.v:5533$1015_Y
+ connect \Y $ne$ls180.v:5568$1015_Y
end
- attribute \src "ls180.v:5534.51-5534.86"
- cell $ne $ne$ls180.v:5534$1016
+ attribute \src "ls180.v:5569.51-5569.86"
+ cell $ne $ne$ls180.v:5569$1016
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_level
connect \B 1'0
- connect \Y $ne$ls180.v:5534$1016_Y
+ connect \Y $ne$ls180.v:5569$1016_Y
end
- attribute \src "ls180.v:5624.79-5624.119"
- cell $ne $ne$ls180.v:5624$1027
+ attribute \src "ls180.v:5659.79-5659.119"
+ cell $ne $ne$ls180.v:5659$1027
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \builder_libresocsim_wishbone_sel
connect \B 1'0
- connect \Y $ne$ls180.v:5624$1027_Y
+ connect \Y $ne$ls180.v:5659$1027_Y
end
- attribute \src "ls180.v:7435.7-7435.52"
- cell $ne $ne$ls180.v:7435$2404
+ attribute \src "ls180.v:7481.7-7481.52"
+ cell $ne $ne$ls180.v:7481$2414
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_bus_errors
connect \B 32'11111111111111111111111111111111
- connect \Y $ne$ls180.v:7435$2404_Y
+ connect \Y $ne$ls180.v:7481$2414_Y
end
- attribute \src "ls180.v:7485.9-7485.43"
- cell $ne $ne$ls180.v:7485$2418
+ attribute \src "ls180.v:7531.9-7531.43"
+ cell $ne $ne$ls180.v:7531$2428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_count
connect \B 1'0
- connect \Y $ne$ls180.v:7485$2418_Y
+ connect \Y $ne$ls180.v:7531$2428_Y
end
- attribute \src "ls180.v:7521.8-7521.44"
- cell $ne $ne$ls180.v:7521$2425
+ attribute \src "ls180.v:7567.8-7567.44"
+ cell $ne $ne$ls180.v:7567$2435
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_counter
connect \B 1'0
- connect \Y $ne$ls180.v:7521$2425_Y
+ connect \Y $ne$ls180.v:7567$2435_Y
end
- attribute \src "ls180.v:8424.9-8424.47"
- cell $ne $ne$ls180.v:8424$2635
+ attribute \src "ls180.v:8470.9-8470.47"
+ cell $ne $ne$ls180.v:8470$2645
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_cnt
connect \B 4'1010
- connect \Y $ne$ls180.v:8424$2635_Y
+ connect \Y $ne$ls180.v:8470$2645_Y
end
- attribute \src "ls180.v:2726.45-2726.80"
- cell $not $not$ls180.v:2726$14
+ attribute \src "ls180.v:2757.45-2757.80"
+ cell $not $not$ls180.v:2757$14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_ibus_cyc
- connect \Y $not$ls180.v:2726$14_Y
+ connect \Y $not$ls180.v:2757$14_Y
end
- attribute \src "ls180.v:2765.61-2765.94"
- cell $not $not$ls180.v:2765$19
+ attribute \src "ls180.v:2796.61-2796.94"
+ cell $not $not$ls180.v:2796$19
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter0_skip
- connect \Y $not$ls180.v:2765$19_Y
+ connect \Y $not$ls180.v:2796$19_Y
end
- attribute \src "ls180.v:2766.61-2766.94"
- cell $not $not$ls180.v:2766$20
+ attribute \src "ls180.v:2797.61-2797.94"
+ cell $not $not$ls180.v:2797$20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter0_skip
- connect \Y $not$ls180.v:2766$20_Y
+ connect \Y $not$ls180.v:2797$20_Y
end
- attribute \src "ls180.v:2786.45-2786.80"
- cell $not $not$ls180.v:2786$25
+ attribute \src "ls180.v:2817.45-2817.80"
+ cell $not $not$ls180.v:2817$25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_dbus_cyc
- connect \Y $not$ls180.v:2786$25_Y
+ connect \Y $not$ls180.v:2817$25_Y
end
- attribute \src "ls180.v:2825.61-2825.94"
- cell $not $not$ls180.v:2825$30
+ attribute \src "ls180.v:2856.61-2856.94"
+ cell $not $not$ls180.v:2856$30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter1_skip
- connect \Y $not$ls180.v:2825$30_Y
+ connect \Y $not$ls180.v:2856$30_Y
end
- attribute \src "ls180.v:2826.61-2826.94"
- cell $not $not$ls180.v:2826$31
+ attribute \src "ls180.v:2857.61-2857.94"
+ cell $not $not$ls180.v:2857$31
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter1_skip
- connect \Y $not$ls180.v:2826$31_Y
+ connect \Y $not$ls180.v:2857$31_Y
end
- attribute \src "ls180.v:2846.45-2846.83"
- cell $not $not$ls180.v:2846$36
+ attribute \src "ls180.v:2877.45-2877.83"
+ cell $not $not$ls180.v:2877$36
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_libresoc_jtag_wb_cyc
- connect \Y $not$ls180.v:2846$36_Y
+ connect \Y $not$ls180.v:2877$36_Y
end
- attribute \src "ls180.v:2885.61-2885.94"
- cell $not $not$ls180.v:2885$41
+ attribute \src "ls180.v:2916.61-2916.94"
+ cell $not $not$ls180.v:2916$41
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter2_skip
- connect \Y $not$ls180.v:2885$41_Y
+ connect \Y $not$ls180.v:2916$41_Y
end
- attribute \src "ls180.v:2886.61-2886.94"
- cell $not $not$ls180.v:2886$42
+ attribute \src "ls180.v:2917.61-2917.94"
+ cell $not $not$ls180.v:2917$42
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_converter2_skip
- connect \Y $not$ls180.v:2886$42_Y
+ connect \Y $not$ls180.v:2917$42_Y
end
- attribute \src "ls180.v:3028.34-3028.64"
- cell $not $not$ls180.v:3028$66
+ attribute \src "ls180.v:3059.34-3059.64"
+ cell $not $not$ls180.v:3059$66
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_command_storage [0]
- connect \Y $not$ls180.v:3028$66_Y
+ connect \Y $not$ls180.v:3059$66_Y
end
- attribute \src "ls180.v:3029.31-3029.61"
- cell $not $not$ls180.v:3029$67
+ attribute \src "ls180.v:3060.31-3060.61"
+ cell $not $not$ls180.v:3060$67
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_command_storage [1]
- connect \Y $not$ls180.v:3029$67_Y
+ connect \Y $not$ls180.v:3060$67_Y
end
- attribute \src "ls180.v:3030.32-3030.62"
- cell $not $not$ls180.v:3030$68
+ attribute \src "ls180.v:3061.32-3061.62"
+ cell $not $not$ls180.v:3061$68
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_command_storage [2]
- connect \Y $not$ls180.v:3030$68_Y
+ connect \Y $not$ls180.v:3061$68_Y
end
- attribute \src "ls180.v:3031.32-3031.62"
- cell $not $not$ls180.v:3031$69
+ attribute \src "ls180.v:3062.32-3062.62"
+ cell $not $not$ls180.v:3062$69
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_command_storage [3]
- connect \Y $not$ls180.v:3031$69_Y
+ connect \Y $not$ls180.v:3062$69_Y
end
- attribute \src "ls180.v:3073.33-3073.56"
- cell $not $not$ls180.v:3073$72
+ attribute \src "ls180.v:3104.33-3104.56"
+ cell $not $not$ls180.v:3104$72
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_timer_done0
- connect \Y $not$ls180.v:3073$72_Y
+ connect \Y $not$ls180.v:3104$72_Y
end
- attribute \src "ls180.v:3174.58-3174.106"
- cell $not $not$ls180.v:3174$102
+ attribute \src "ls180.v:3205.58-3205.106"
+ cell $not $not$ls180.v:3205$102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid
- connect \Y $not$ls180.v:3174$102_Y
+ connect \Y $not$ls180.v:3205$102_Y
end
- attribute \src "ls180.v:3228.9-3228.45"
- cell $not $not$ls180.v:3228$107
+ attribute \src "ls180.v:3259.9-3259.45"
+ cell $not $not$ls180.v:3259$107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_refresh_req
- connect \Y $not$ls180.v:3228$107_Y
+ connect \Y $not$ls180.v:3259$107_Y
end
- attribute \src "ls180.v:3331.58-3331.106"
- cell $not $not$ls180.v:3331$132
+ attribute \src "ls180.v:3362.58-3362.106"
+ cell $not $not$ls180.v:3362$132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid
- connect \Y $not$ls180.v:3331$132_Y
+ connect \Y $not$ls180.v:3362$132_Y
end
- attribute \src "ls180.v:3385.9-3385.45"
- cell $not $not$ls180.v:3385$137
+ attribute \src "ls180.v:3416.9-3416.45"
+ cell $not $not$ls180.v:3416$137
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_refresh_req
- connect \Y $not$ls180.v:3385$137_Y
+ connect \Y $not$ls180.v:3416$137_Y
end
- attribute \src "ls180.v:3488.58-3488.106"
- cell $not $not$ls180.v:3488$162
+ attribute \src "ls180.v:3519.58-3519.106"
+ cell $not $not$ls180.v:3519$162
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid
- connect \Y $not$ls180.v:3488$162_Y
+ connect \Y $not$ls180.v:3519$162_Y
end
- attribute \src "ls180.v:3542.9-3542.45"
- cell $not $not$ls180.v:3542$167
+ attribute \src "ls180.v:3573.9-3573.45"
+ cell $not $not$ls180.v:3573$167
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_refresh_req
- connect \Y $not$ls180.v:3542$167_Y
+ connect \Y $not$ls180.v:3573$167_Y
end
- attribute \src "ls180.v:3645.58-3645.106"
- cell $not $not$ls180.v:3645$192
+ attribute \src "ls180.v:3676.58-3676.106"
+ cell $not $not$ls180.v:3676$192
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid
- connect \Y $not$ls180.v:3645$192_Y
+ connect \Y $not$ls180.v:3676$192_Y
end
- attribute \src "ls180.v:3699.9-3699.45"
- cell $not $not$ls180.v:3699$197
+ attribute \src "ls180.v:3730.9-3730.45"
+ cell $not $not$ls180.v:3730$197
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_refresh_req
- connect \Y $not$ls180.v:3699$197_Y
+ connect \Y $not$ls180.v:3730$197_Y
end
- attribute \src "ls180.v:3741.149-3741.187"
- cell $not $not$ls180.v:3741$200
+ attribute \src "ls180.v:3772.149-3772.187"
+ cell $not $not$ls180.v:3772$200
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_cas
- connect \Y $not$ls180.v:3741$200_Y
+ connect \Y $not$ls180.v:3772$200_Y
end
- attribute \src "ls180.v:3741.193-3741.230"
- cell $not $not$ls180.v:3741$202
+ attribute \src "ls180.v:3772.193-3772.230"
+ cell $not $not$ls180.v:3772$202
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_we
- connect \Y $not$ls180.v:3741$202_Y
+ connect \Y $not$ls180.v:3772$202_Y
end
- attribute \src "ls180.v:3742.149-3742.187"
- cell $not $not$ls180.v:3742$206
+ attribute \src "ls180.v:3773.149-3773.187"
+ cell $not $not$ls180.v:3773$206
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_cas
- connect \Y $not$ls180.v:3742$206_Y
+ connect \Y $not$ls180.v:3773$206_Y
end
- attribute \src "ls180.v:3742.193-3742.230"
- cell $not $not$ls180.v:3742$208
+ attribute \src "ls180.v:3773.193-3773.230"
+ cell $not $not$ls180.v:3773$208
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_we
- connect \Y $not$ls180.v:3742$208_Y
+ connect \Y $not$ls180.v:3773$208_Y
end
- attribute \src "ls180.v:3758.43-3758.73"
- cell $not $not$ls180.v:3758$236
+ attribute \src "ls180.v:3789.43-3789.73"
+ cell $not $not$ls180.v:3789$236
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \main_sdram_interface_wdata_we
- connect \Y $not$ls180.v:3758$236_Y
+ connect \Y $not$ls180.v:3789$236_Y
end
- attribute \src "ls180.v:3761.205-3761.245"
- cell $not $not$ls180.v:3761$239
+ attribute \src "ls180.v:3792.205-3792.245"
+ cell $not $not$ls180.v:3792$239
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_cas
- connect \Y $not$ls180.v:3761$239_Y
+ connect \Y $not$ls180.v:3792$239_Y
end
- attribute \src "ls180.v:3761.251-3761.290"
- cell $not $not$ls180.v:3761$241
+ attribute \src "ls180.v:3792.251-3792.290"
+ cell $not $not$ls180.v:3792$241
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_we
- connect \Y $not$ls180.v:3761$241_Y
+ connect \Y $not$ls180.v:3792$241_Y
end
- attribute \src "ls180.v:3761.159-3761.292"
- cell $not $not$ls180.v:3761$243
+ attribute \src "ls180.v:3792.159-3792.292"
+ cell $not $not$ls180.v:3792$243
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3761$242_Y
- connect \Y $not$ls180.v:3761$243_Y
+ connect \A $and$ls180.v:3792$242_Y
+ connect \Y $not$ls180.v:3792$243_Y
end
- attribute \src "ls180.v:3762.205-3762.245"
- cell $not $not$ls180.v:3762$252
+ attribute \src "ls180.v:3793.205-3793.245"
+ cell $not $not$ls180.v:3793$252
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_cas
- connect \Y $not$ls180.v:3762$252_Y
+ connect \Y $not$ls180.v:3793$252_Y
end
- attribute \src "ls180.v:3762.251-3762.290"
- cell $not $not$ls180.v:3762$254
+ attribute \src "ls180.v:3793.251-3793.290"
+ cell $not $not$ls180.v:3793$254
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_we
- connect \Y $not$ls180.v:3762$254_Y
+ connect \Y $not$ls180.v:3793$254_Y
end
- attribute \src "ls180.v:3762.159-3762.292"
- cell $not $not$ls180.v:3762$256
+ attribute \src "ls180.v:3793.159-3793.292"
+ cell $not $not$ls180.v:3793$256
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3762$255_Y
- connect \Y $not$ls180.v:3762$256_Y
+ connect \A $and$ls180.v:3793$255_Y
+ connect \Y $not$ls180.v:3793$256_Y
end
- attribute \src "ls180.v:3763.205-3763.245"
- cell $not $not$ls180.v:3763$265
+ attribute \src "ls180.v:3794.205-3794.245"
+ cell $not $not$ls180.v:3794$265
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_cas
- connect \Y $not$ls180.v:3763$265_Y
+ connect \Y $not$ls180.v:3794$265_Y
end
- attribute \src "ls180.v:3763.251-3763.290"
- cell $not $not$ls180.v:3763$267
+ attribute \src "ls180.v:3794.251-3794.290"
+ cell $not $not$ls180.v:3794$267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_we
- connect \Y $not$ls180.v:3763$267_Y
+ connect \Y $not$ls180.v:3794$267_Y
end
- attribute \src "ls180.v:3763.159-3763.292"
- cell $not $not$ls180.v:3763$269
+ attribute \src "ls180.v:3794.159-3794.292"
+ cell $not $not$ls180.v:3794$269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3763$268_Y
- connect \Y $not$ls180.v:3763$269_Y
+ connect \A $and$ls180.v:3794$268_Y
+ connect \Y $not$ls180.v:3794$269_Y
end
- attribute \src "ls180.v:3764.205-3764.245"
- cell $not $not$ls180.v:3764$278
+ attribute \src "ls180.v:3795.205-3795.245"
+ cell $not $not$ls180.v:3795$278
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_cas
- connect \Y $not$ls180.v:3764$278_Y
+ connect \Y $not$ls180.v:3795$278_Y
end
- attribute \src "ls180.v:3764.251-3764.290"
- cell $not $not$ls180.v:3764$280
+ attribute \src "ls180.v:3795.251-3795.290"
+ cell $not $not$ls180.v:3795$280
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_we
- connect \Y $not$ls180.v:3764$280_Y
+ connect \Y $not$ls180.v:3795$280_Y
end
- attribute \src "ls180.v:3764.159-3764.292"
- cell $not $not$ls180.v:3764$282
+ attribute \src "ls180.v:3795.159-3795.292"
+ cell $not $not$ls180.v:3795$282
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3764$281_Y
- connect \Y $not$ls180.v:3764$282_Y
+ connect \A $and$ls180.v:3795$281_Y
+ connect \Y $not$ls180.v:3795$282_Y
end
- attribute \src "ls180.v:3791.71-3791.103"
- cell $not $not$ls180.v:3791$293
+ attribute \src "ls180.v:3822.71-3822.103"
+ cell $not $not$ls180.v:3822$293
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_cmd_valid
- connect \Y $not$ls180.v:3791$293_Y
+ connect \Y $not$ls180.v:3822$293_Y
end
- attribute \src "ls180.v:3794.205-3794.245"
- cell $not $not$ls180.v:3794$297
+ attribute \src "ls180.v:3825.205-3825.245"
+ cell $not $not$ls180.v:3825$297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_cas
- connect \Y $not$ls180.v:3794$297_Y
+ connect \Y $not$ls180.v:3825$297_Y
end
- attribute \src "ls180.v:3794.251-3794.290"
- cell $not $not$ls180.v:3794$299
+ attribute \src "ls180.v:3825.251-3825.290"
+ cell $not $not$ls180.v:3825$299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_payload_we
- connect \Y $not$ls180.v:3794$299_Y
+ connect \Y $not$ls180.v:3825$299_Y
end
- attribute \src "ls180.v:3794.159-3794.292"
- cell $not $not$ls180.v:3794$301
+ attribute \src "ls180.v:3825.159-3825.292"
+ cell $not $not$ls180.v:3825$301
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3794$300_Y
- connect \Y $not$ls180.v:3794$301_Y
+ connect \A $and$ls180.v:3825$300_Y
+ connect \Y $not$ls180.v:3825$301_Y
end
- attribute \src "ls180.v:3795.205-3795.245"
- cell $not $not$ls180.v:3795$310
+ attribute \src "ls180.v:3826.205-3826.245"
+ cell $not $not$ls180.v:3826$310
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_cas
- connect \Y $not$ls180.v:3795$310_Y
+ connect \Y $not$ls180.v:3826$310_Y
end
- attribute \src "ls180.v:3795.251-3795.290"
- cell $not $not$ls180.v:3795$312
+ attribute \src "ls180.v:3826.251-3826.290"
+ cell $not $not$ls180.v:3826$312
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_payload_we
- connect \Y $not$ls180.v:3795$312_Y
+ connect \Y $not$ls180.v:3826$312_Y
end
- attribute \src "ls180.v:3795.159-3795.292"
- cell $not $not$ls180.v:3795$314
+ attribute \src "ls180.v:3826.159-3826.292"
+ cell $not $not$ls180.v:3826$314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3795$313_Y
- connect \Y $not$ls180.v:3795$314_Y
+ connect \A $and$ls180.v:3826$313_Y
+ connect \Y $not$ls180.v:3826$314_Y
end
- attribute \src "ls180.v:3796.205-3796.245"
- cell $not $not$ls180.v:3796$323
+ attribute \src "ls180.v:3827.205-3827.245"
+ cell $not $not$ls180.v:3827$323
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_cas
- connect \Y $not$ls180.v:3796$323_Y
+ connect \Y $not$ls180.v:3827$323_Y
end
- attribute \src "ls180.v:3796.251-3796.290"
- cell $not $not$ls180.v:3796$325
+ attribute \src "ls180.v:3827.251-3827.290"
+ cell $not $not$ls180.v:3827$325
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_payload_we
- connect \Y $not$ls180.v:3796$325_Y
+ connect \Y $not$ls180.v:3827$325_Y
end
- attribute \src "ls180.v:3796.159-3796.292"
- cell $not $not$ls180.v:3796$327
+ attribute \src "ls180.v:3827.159-3827.292"
+ cell $not $not$ls180.v:3827$327
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3796$326_Y
- connect \Y $not$ls180.v:3796$327_Y
+ connect \A $and$ls180.v:3827$326_Y
+ connect \Y $not$ls180.v:3827$327_Y
end
- attribute \src "ls180.v:3797.205-3797.245"
- cell $not $not$ls180.v:3797$336
+ attribute \src "ls180.v:3828.205-3828.245"
+ cell $not $not$ls180.v:3828$336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_cas
- connect \Y $not$ls180.v:3797$336_Y
+ connect \Y $not$ls180.v:3828$336_Y
end
- attribute \src "ls180.v:3797.251-3797.290"
- cell $not $not$ls180.v:3797$338
+ attribute \src "ls180.v:3828.251-3828.290"
+ cell $not $not$ls180.v:3828$338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_payload_we
- connect \Y $not$ls180.v:3797$338_Y
+ connect \Y $not$ls180.v:3828$338_Y
end
- attribute \src "ls180.v:3797.159-3797.292"
- cell $not $not$ls180.v:3797$340
+ attribute \src "ls180.v:3828.159-3828.292"
+ cell $not $not$ls180.v:3828$340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3797$339_Y
- connect \Y $not$ls180.v:3797$340_Y
+ connect \A $and$ls180.v:3828$339_Y
+ connect \Y $not$ls180.v:3828$340_Y
end
- attribute \src "ls180.v:3860.71-3860.103"
- cell $not $not$ls180.v:3860$379
+ attribute \src "ls180.v:3891.71-3891.103"
+ cell $not $not$ls180.v:3891$379
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_valid
- connect \Y $not$ls180.v:3860$379_Y
+ connect \Y $not$ls180.v:3891$379_Y
end
- attribute \src "ls180.v:3881.112-3881.150"
- cell $not $not$ls180.v:3881$382
+ attribute \src "ls180.v:3912.112-3912.150"
+ cell $not $not$ls180.v:3912$382
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_cas
- connect \Y $not$ls180.v:3881$382_Y
+ connect \Y $not$ls180.v:3912$382_Y
end
- attribute \src "ls180.v:3881.156-3881.193"
- cell $not $not$ls180.v:3881$384
+ attribute \src "ls180.v:3912.156-3912.193"
+ cell $not $not$ls180.v:3912$384
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_we
- connect \Y $not$ls180.v:3881$384_Y
+ connect \Y $not$ls180.v:3912$384_Y
end
- attribute \src "ls180.v:3881.68-3881.195"
- cell $not $not$ls180.v:3881$386
+ attribute \src "ls180.v:3912.68-3912.195"
+ cell $not $not$ls180.v:3912$386
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3881$385_Y
- connect \Y $not$ls180.v:3881$386_Y
+ connect \A $and$ls180.v:3912$385_Y
+ connect \Y $not$ls180.v:3912$386_Y
end
- attribute \src "ls180.v:3889.11-3889.38"
- cell $not $not$ls180.v:3889$389
+ attribute \src "ls180.v:3920.11-3920.38"
+ cell $not $not$ls180.v:3920$389
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_write_available
- connect \Y $not$ls180.v:3889$389_Y
+ connect \Y $not$ls180.v:3920$389_Y
end
- attribute \src "ls180.v:3919.112-3919.150"
- cell $not $not$ls180.v:3919$391
+ attribute \src "ls180.v:3950.112-3950.150"
+ cell $not $not$ls180.v:3950$391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_cas
- connect \Y $not$ls180.v:3919$391_Y
+ connect \Y $not$ls180.v:3950$391_Y
end
- attribute \src "ls180.v:3919.156-3919.193"
- cell $not $not$ls180.v:3919$393
+ attribute \src "ls180.v:3950.156-3950.193"
+ cell $not $not$ls180.v:3950$393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_we
- connect \Y $not$ls180.v:3919$393_Y
+ connect \Y $not$ls180.v:3950$393_Y
end
- attribute \src "ls180.v:3919.68-3919.195"
- cell $not $not$ls180.v:3919$395
+ attribute \src "ls180.v:3950.68-3950.195"
+ cell $not $not$ls180.v:3950$395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3919$394_Y
- connect \Y $not$ls180.v:3919$395_Y
+ connect \A $and$ls180.v:3950$394_Y
+ connect \Y $not$ls180.v:3950$395_Y
end
- attribute \src "ls180.v:3927.11-3927.37"
- cell $not $not$ls180.v:3927$398
+ attribute \src "ls180.v:3958.11-3958.37"
+ cell $not $not$ls180.v:3958$398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_read_available
- connect \Y $not$ls180.v:3927$398_Y
+ connect \Y $not$ls180.v:3958$398_Y
end
- attribute \src "ls180.v:3937.87-3937.331"
- cell $not $not$ls180.v:3937$410
+ attribute \src "ls180.v:3968.87-3968.331"
+ cell $not $not$ls180.v:3968$410
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3937$409_Y
- connect \Y $not$ls180.v:3937$410_Y
+ connect \A $or$ls180.v:3968$409_Y
+ connect \Y $not$ls180.v:3968$410_Y
end
- attribute \src "ls180.v:3938.35-3938.68"
- cell $not $not$ls180.v:3938$413
+ attribute \src "ls180.v:3969.35-3969.68"
+ cell $not $not$ls180.v:3969$413
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_valid
- connect \Y $not$ls180.v:3938$413_Y
+ connect \Y $not$ls180.v:3969$413_Y
end
- attribute \src "ls180.v:3938.73-3938.105"
- cell $not $not$ls180.v:3938$414
+ attribute \src "ls180.v:3969.73-3969.105"
+ cell $not $not$ls180.v:3969$414
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank0_lock
- connect \Y $not$ls180.v:3938$414_Y
+ connect \Y $not$ls180.v:3969$414_Y
end
- attribute \src "ls180.v:3942.87-3942.331"
- cell $not $not$ls180.v:3942$426
+ attribute \src "ls180.v:3973.87-3973.331"
+ cell $not $not$ls180.v:3973$426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3942$425_Y
- connect \Y $not$ls180.v:3942$426_Y
+ connect \A $or$ls180.v:3973$425_Y
+ connect \Y $not$ls180.v:3973$426_Y
end
- attribute \src "ls180.v:3943.35-3943.68"
- cell $not $not$ls180.v:3943$429
+ attribute \src "ls180.v:3974.35-3974.68"
+ cell $not $not$ls180.v:3974$429
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_valid
- connect \Y $not$ls180.v:3943$429_Y
+ connect \Y $not$ls180.v:3974$429_Y
end
- attribute \src "ls180.v:3943.73-3943.105"
- cell $not $not$ls180.v:3943$430
+ attribute \src "ls180.v:3974.73-3974.105"
+ cell $not $not$ls180.v:3974$430
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank1_lock
- connect \Y $not$ls180.v:3943$430_Y
+ connect \Y $not$ls180.v:3974$430_Y
end
- attribute \src "ls180.v:3947.87-3947.331"
- cell $not $not$ls180.v:3947$442
+ attribute \src "ls180.v:3978.87-3978.331"
+ cell $not $not$ls180.v:3978$442
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3947$441_Y
- connect \Y $not$ls180.v:3947$442_Y
+ connect \A $or$ls180.v:3978$441_Y
+ connect \Y $not$ls180.v:3978$442_Y
end
- attribute \src "ls180.v:3948.35-3948.68"
- cell $not $not$ls180.v:3948$445
+ attribute \src "ls180.v:3979.35-3979.68"
+ cell $not $not$ls180.v:3979$445
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_valid
- connect \Y $not$ls180.v:3948$445_Y
+ connect \Y $not$ls180.v:3979$445_Y
end
- attribute \src "ls180.v:3948.73-3948.105"
- cell $not $not$ls180.v:3948$446
+ attribute \src "ls180.v:3979.73-3979.105"
+ cell $not $not$ls180.v:3979$446
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank2_lock
- connect \Y $not$ls180.v:3948$446_Y
+ connect \Y $not$ls180.v:3979$446_Y
end
- attribute \src "ls180.v:3952.87-3952.331"
- cell $not $not$ls180.v:3952$458
+ attribute \src "ls180.v:3983.87-3983.331"
+ cell $not $not$ls180.v:3983$458
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3952$457_Y
- connect \Y $not$ls180.v:3952$458_Y
+ connect \A $or$ls180.v:3983$457_Y
+ connect \Y $not$ls180.v:3983$458_Y
end
- attribute \src "ls180.v:3953.35-3953.68"
- cell $not $not$ls180.v:3953$461
+ attribute \src "ls180.v:3984.35-3984.68"
+ cell $not $not$ls180.v:3984$461
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_valid
- connect \Y $not$ls180.v:3953$461_Y
+ connect \Y $not$ls180.v:3984$461_Y
end
- attribute \src "ls180.v:3953.73-3953.105"
- cell $not $not$ls180.v:3953$462
+ attribute \src "ls180.v:3984.73-3984.105"
+ cell $not $not$ls180.v:3984$462
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_interface_bank3_lock
- connect \Y $not$ls180.v:3953$462_Y
+ connect \Y $not$ls180.v:3984$462_Y
end
- attribute \src "ls180.v:3957.128-3957.372"
- cell $not $not$ls180.v:3957$475
+ attribute \src "ls180.v:3988.128-3988.372"
+ cell $not $not$ls180.v:3988$475
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$474_Y
- connect \Y $not$ls180.v:3957$475_Y
+ connect \A $or$ls180.v:3988$474_Y
+ connect \Y $not$ls180.v:3988$475_Y
end
- attribute \src "ls180.v:3957.502-3957.746"
- cell $not $not$ls180.v:3957$491
+ attribute \src "ls180.v:3988.502-3988.746"
+ cell $not $not$ls180.v:3988$491
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$490_Y
- connect \Y $not$ls180.v:3957$491_Y
+ connect \A $or$ls180.v:3988$490_Y
+ connect \Y $not$ls180.v:3988$491_Y
end
- attribute \src "ls180.v:3957.876-3957.1120"
- cell $not $not$ls180.v:3957$507
+ attribute \src "ls180.v:3988.876-3988.1120"
+ cell $not $not$ls180.v:3988$507
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$506_Y
- connect \Y $not$ls180.v:3957$507_Y
+ connect \A $or$ls180.v:3988$506_Y
+ connect \Y $not$ls180.v:3988$507_Y
end
- attribute \src "ls180.v:3957.1250-3957.1494"
- cell $not $not$ls180.v:3957$523
+ attribute \src "ls180.v:3988.1250-3988.1494"
+ cell $not $not$ls180.v:3988$523
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$522_Y
- connect \Y $not$ls180.v:3957$523_Y
+ connect \A $or$ls180.v:3988$522_Y
+ connect \Y $not$ls180.v:3988$523_Y
end
- attribute \src "ls180.v:3979.32-3979.50"
- cell $not $not$ls180.v:3979$529
+ attribute \src "ls180.v:4010.32-4010.50"
+ cell $not $not$ls180.v:4010$529
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_wb_sdram_cyc
- connect \Y $not$ls180.v:3979$529_Y
+ connect \Y $not$ls180.v:4010$529_Y
end
- attribute \src "ls180.v:4018.30-4018.50"
- cell $not $not$ls180.v:4018$534
+ attribute \src "ls180.v:4049.30-4049.50"
+ cell $not $not$ls180.v:4049$534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_converter_skip
- connect \Y $not$ls180.v:4018$534_Y
+ connect \Y $not$ls180.v:4049$534_Y
end
- attribute \src "ls180.v:4019.30-4019.50"
- cell $not $not$ls180.v:4019$535
+ attribute \src "ls180.v:4050.30-4050.50"
+ cell $not $not$ls180.v:4050$535
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_converter_skip
- connect \Y $not$ls180.v:4019$535_Y
+ connect \Y $not$ls180.v:4050$535_Y
end
- attribute \src "ls180.v:4044.27-4044.48"
- cell $not $not$ls180.v:4044$541
+ attribute \src "ls180.v:4075.27-4075.48"
+ cell $not $not$ls180.v:4075$541
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_cyc
- connect \Y $not$ls180.v:4044$541_Y
+ connect \Y $not$ls180.v:4075$541_Y
end
- attribute \src "ls180.v:4045.30-4045.50"
- cell $not $not$ls180.v:4045$542
+ attribute \src "ls180.v:4076.30-4076.50"
+ cell $not $not$ls180.v:4076$542
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_we
- connect \Y $not$ls180.v:4045$542_Y
+ connect \Y $not$ls180.v:4076$542_Y
end
- attribute \src "ls180.v:4046.80-4046.98"
- cell $not $not$ls180.v:4046$544
+ attribute \src "ls180.v:4077.80-4077.98"
+ cell $not $not$ls180.v:4077$544
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_cmd_consumed
- connect \Y $not$ls180.v:4046$544_Y
+ connect \Y $not$ls180.v:4077$544_Y
end
- attribute \src "ls180.v:4047.107-4047.127"
- cell $not $not$ls180.v:4047$548
+ attribute \src "ls180.v:4078.107-4078.127"
+ cell $not $not$ls180.v:4078$548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_wdata_consumed
- connect \Y $not$ls180.v:4047$548_Y
+ connect \Y $not$ls180.v:4078$548_Y
end
- attribute \src "ls180.v:4048.78-4048.103"
- cell $not $not$ls180.v:4048$551
+ attribute \src "ls180.v:4079.78-4079.103"
+ cell $not $not$ls180.v:4079$551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_port_cmd_payload_we
- connect \Y $not$ls180.v:4048$551_Y
+ connect \Y $not$ls180.v:4079$551_Y
end
- attribute \src "ls180.v:4049.91-4049.111"
- cell $not $not$ls180.v:4049$554
+ attribute \src "ls180.v:4080.91-4080.111"
+ cell $not $not$ls180.v:4080$554
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_we
- connect \Y $not$ls180.v:4049$554_Y
+ connect \Y $not$ls180.v:4080$554_Y
end
- attribute \src "ls180.v:4065.35-4065.64"
- cell $not $not$ls180.v:4065$563
+ attribute \src "ls180.v:4096.35-4096.64"
+ cell $not $not$ls180.v:4096$563
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_sink_ready
- connect \Y $not$ls180.v:4065$563_Y
+ connect \Y $not$ls180.v:4096$563_Y
end
- attribute \src "ls180.v:4066.36-4066.67"
- cell $not $not$ls180.v:4066$564
+ attribute \src "ls180.v:4097.36-4097.67"
+ cell $not $not$ls180.v:4097$564
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_source_valid
- connect \Y $not$ls180.v:4066$564_Y
+ connect \Y $not$ls180.v:4097$564_Y
end
- attribute \src "ls180.v:4072.32-4072.61"
- cell $not $not$ls180.v:4072$565
+ attribute \src "ls180.v:4103.32-4103.61"
+ cell $not $not$ls180.v:4103$565
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_sink_ready
- connect \Y $not$ls180.v:4072$565_Y
+ connect \Y $not$ls180.v:4103$565_Y
end
- attribute \src "ls180.v:4078.36-4078.67"
- cell $not $not$ls180.v:4078$566
+ attribute \src "ls180.v:4109.36-4109.67"
+ cell $not $not$ls180.v:4109$566
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_source_valid
- connect \Y $not$ls180.v:4078$566_Y
+ connect \Y $not$ls180.v:4109$566_Y
end
- attribute \src "ls180.v:4079.35-4079.64"
- cell $not $not$ls180.v:4079$567
+ attribute \src "ls180.v:4110.35-4110.64"
+ cell $not $not$ls180.v:4110$567
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_sink_ready
- connect \Y $not$ls180.v:4079$567_Y
+ connect \Y $not$ls180.v:4110$567_Y
end
- attribute \src "ls180.v:4082.32-4082.63"
- cell $not $not$ls180.v:4082$570
+ attribute \src "ls180.v:4113.32-4113.63"
+ cell $not $not$ls180.v:4113$570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_source_valid
- connect \Y $not$ls180.v:4082$570_Y
+ connect \Y $not$ls180.v:4113$570_Y
end
- attribute \src "ls180.v:4120.81-4120.108"
- cell $not $not$ls180.v:4120$580
+ attribute \src "ls180.v:4151.81-4151.108"
+ cell $not $not$ls180.v:4151$580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_readable
- connect \Y $not$ls180.v:4120$580_Y
+ connect \Y $not$ls180.v:4151$580_Y
end
- attribute \src "ls180.v:4150.81-4150.108"
- cell $not $not$ls180.v:4150$591
+ attribute \src "ls180.v:4181.81-4181.108"
+ cell $not $not$ls180.v:4181$591
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_readable
- connect \Y $not$ls180.v:4150$591_Y
+ connect \Y $not$ls180.v:4181$591_Y
end
- attribute \src "ls180.v:4287.60-4287.85"
- cell $not $not$ls180.v:4287$632
+ attribute \src "ls180.v:4322.60-4322.85"
+ cell $not $not$ls180.v:4322$632
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_clocker_clk_d
- connect \Y $not$ls180.v:4287$632_Y
+ connect \Y $not$ls180.v:4322$632_Y
end
- attribute \src "ls180.v:4428.54-4428.96"
- cell $not $not$ls180.v:4428$646
+ attribute \src "ls180.v:4463.54-4463.96"
+ cell $not $not$ls180.v:4463$646
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all
- connect \Y $not$ls180.v:4428$646_Y
+ connect \Y $not$ls180.v:4463$646_Y
end
- attribute \src "ls180.v:4431.48-4431.86"
- cell $not $not$ls180.v:4431$649
+ attribute \src "ls180.v:4466.48-4466.86"
+ cell $not $not$ls180.v:4466$649
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_buf_source_valid
- connect \Y $not$ls180.v:4431$649_Y
+ connect \Y $not$ls180.v:4466$649_Y
end
- attribute \src "ls180.v:4555.55-4555.98"
- cell $not $not$ls180.v:4555$667
+ attribute \src "ls180.v:4590.55-4590.98"
+ cell $not $not$ls180.v:4590$667
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_strobe_all
- connect \Y $not$ls180.v:4555$667_Y
+ connect \Y $not$ls180.v:4590$667_Y
end
- attribute \src "ls180.v:4558.49-4558.88"
- cell $not $not$ls180.v:4558$670
+ attribute \src "ls180.v:4593.49-4593.88"
+ cell $not $not$ls180.v:4593$670
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_buf_source_valid
- connect \Y $not$ls180.v:4558$670_Y
+ connect \Y $not$ls180.v:4593$670_Y
end
- attribute \src "ls180.v:4608.30-4608.58"
- cell $not $not$ls180.v:4608$676
+ attribute \src "ls180.v:4643.30-4643.58"
+ cell $not $not$ls180.v:4643$676
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_sink_valid
- connect \Y $not$ls180.v:4608$676_Y
+ connect \Y $not$ls180.v:4643$676_Y
end
- attribute \src "ls180.v:4689.56-4689.100"
- cell $not $not$ls180.v:4689$682
+ attribute \src "ls180.v:4724.56-4724.100"
+ cell $not $not$ls180.v:4724$682
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_strobe_all
- connect \Y $not$ls180.v:4689$682_Y
+ connect \Y $not$ls180.v:4724$682_Y
end
- attribute \src "ls180.v:4692.50-4692.90"
- cell $not $not$ls180.v:4692$685
+ attribute \src "ls180.v:4727.50-4727.90"
+ cell $not $not$ls180.v:4727$685
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_buf_source_valid
- connect \Y $not$ls180.v:4692$685_Y
+ connect \Y $not$ls180.v:4727$685_Y
end
- attribute \src "ls180.v:4808.42-4808.74"
- cell $not $not$ls180.v:4808$701
+ attribute \src "ls180.v:4843.42-4843.74"
+ cell $not $not$ls180.v:4843$701
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_valid
- connect \Y $not$ls180.v:4808$701_Y
+ connect \Y $not$ls180.v:4843$701_Y
end
- attribute \src "ls180.v:5332.50-5332.88"
- cell $not $not$ls180.v:5332$986
+ attribute \src "ls180.v:5367.50-5367.88"
+ cell $not $not$ls180.v:5367$986
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_strobe_all
- connect \Y $not$ls180.v:5332$986_Y
+ connect \Y $not$ls180.v:5367$986_Y
end
- attribute \src "ls180.v:5344.52-5344.102"
- cell $not $not$ls180.v:5344$989
+ attribute \src "ls180.v:5379.52-5379.102"
+ cell $not $not$ls180.v:5379$989
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage
- connect \Y $not$ls180.v:5344$989_Y
+ connect \Y $not$ls180.v:5379$989_Y
end
- attribute \src "ls180.v:5403.38-5403.74"
- cell $not $not$ls180.v:5403$996
+ attribute \src "ls180.v:5438.38-5438.74"
+ cell $not $not$ls180.v:5438$996
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_dma_enable_storage
- connect \Y $not$ls180.v:5403$996_Y
+ connect \Y $not$ls180.v:5438$996_Y
end
- attribute \src "ls180.v:5704.69-5704.88"
- cell $not $not$ls180.v:5704$1065
+ attribute \src "ls180.v:5739.69-5739.88"
+ cell $not $not$ls180.v:5739$1065
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_shared_ack
- connect \Y $not$ls180.v:5704$1065_Y
+ connect \Y $not$ls180.v:5739$1065_Y
end
- attribute \src "ls180.v:5721.63-5721.94"
- cell $not $not$ls180.v:5721$1086
+ attribute \src "ls180.v:5756.63-5756.94"
+ cell $not $not$ls180.v:5756$1086
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5721$1086_Y
+ connect \Y $not$ls180.v:5756$1086_Y
end
- attribute \src "ls180.v:5724.65-5724.96"
- cell $not $not$ls180.v:5724$1093
+ attribute \src "ls180.v:5759.65-5759.96"
+ cell $not $not$ls180.v:5759$1093
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5724$1093_Y
+ connect \Y $not$ls180.v:5759$1093_Y
end
- attribute \src "ls180.v:5727.65-5727.96"
- cell $not $not$ls180.v:5727$1100
+ attribute \src "ls180.v:5762.65-5762.96"
+ cell $not $not$ls180.v:5762$1100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5727$1100_Y
+ connect \Y $not$ls180.v:5762$1100_Y
end
- attribute \src "ls180.v:5730.65-5730.96"
- cell $not $not$ls180.v:5730$1107
+ attribute \src "ls180.v:5765.65-5765.96"
+ cell $not $not$ls180.v:5765$1107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5730$1107_Y
+ connect \Y $not$ls180.v:5765$1107_Y
end
- attribute \src "ls180.v:5733.65-5733.96"
- cell $not $not$ls180.v:5733$1114
+ attribute \src "ls180.v:5768.65-5768.96"
+ cell $not $not$ls180.v:5768$1114
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5733$1114_Y
+ connect \Y $not$ls180.v:5768$1114_Y
end
- attribute \src "ls180.v:5736.68-5736.99"
- cell $not $not$ls180.v:5736$1121
+ attribute \src "ls180.v:5771.68-5771.99"
+ cell $not $not$ls180.v:5771$1121
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5736$1121_Y
+ connect \Y $not$ls180.v:5771$1121_Y
end
- attribute \src "ls180.v:5739.68-5739.99"
- cell $not $not$ls180.v:5739$1128
+ attribute \src "ls180.v:5774.68-5774.99"
+ cell $not $not$ls180.v:5774$1128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5739$1128_Y
+ connect \Y $not$ls180.v:5774$1128_Y
end
- attribute \src "ls180.v:5742.68-5742.99"
- cell $not $not$ls180.v:5742$1135
+ attribute \src "ls180.v:5777.68-5777.99"
+ cell $not $not$ls180.v:5777$1135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5742$1135_Y
+ connect \Y $not$ls180.v:5777$1135_Y
end
- attribute \src "ls180.v:5745.68-5745.99"
- cell $not $not$ls180.v:5745$1142
+ attribute \src "ls180.v:5780.68-5780.99"
+ cell $not $not$ls180.v:5780$1142
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface0_bank_bus_we
- connect \Y $not$ls180.v:5745$1142_Y
+ connect \Y $not$ls180.v:5780$1142_Y
end
- attribute \src "ls180.v:5759.60-5759.91"
- cell $not $not$ls180.v:5759$1150
+ attribute \src "ls180.v:5794.60-5794.91"
+ cell $not $not$ls180.v:5794$1150
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_we
- connect \Y $not$ls180.v:5759$1150_Y
+ connect \Y $not$ls180.v:5794$1150_Y
end
- attribute \src "ls180.v:5762.60-5762.91"
- cell $not $not$ls180.v:5762$1157
+ attribute \src "ls180.v:5797.60-5797.91"
+ cell $not $not$ls180.v:5797$1157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_we
- connect \Y $not$ls180.v:5762$1157_Y
+ connect \Y $not$ls180.v:5797$1157_Y
end
- attribute \src "ls180.v:5765.60-5765.91"
- cell $not $not$ls180.v:5765$1164
+ attribute \src "ls180.v:5800.60-5800.91"
+ cell $not $not$ls180.v:5800$1164
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_we
- connect \Y $not$ls180.v:5765$1164_Y
+ connect \Y $not$ls180.v:5800$1164_Y
end
- attribute \src "ls180.v:5768.60-5768.91"
- cell $not $not$ls180.v:5768$1171
+ attribute \src "ls180.v:5803.60-5803.91"
+ cell $not $not$ls180.v:5803$1171
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_we
- connect \Y $not$ls180.v:5768$1171_Y
+ connect \Y $not$ls180.v:5803$1171_Y
end
- attribute \src "ls180.v:5771.61-5771.92"
- cell $not $not$ls180.v:5771$1178
+ attribute \src "ls180.v:5806.61-5806.92"
+ cell $not $not$ls180.v:5806$1178
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_we
- connect \Y $not$ls180.v:5771$1178_Y
+ connect \Y $not$ls180.v:5806$1178_Y
end
- attribute \src "ls180.v:5774.61-5774.92"
- cell $not $not$ls180.v:5774$1185
+ attribute \src "ls180.v:5809.61-5809.92"
+ cell $not $not$ls180.v:5809$1185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface1_bank_bus_we
- connect \Y $not$ls180.v:5774$1185_Y
- end
- attribute \src "ls180.v:5785.64-5785.95"
- cell $not $not$ls180.v:5785$1193
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_we
- connect \Y $not$ls180.v:5785$1193_Y
+ connect \Y $not$ls180.v:5809$1185_Y
end
- attribute \src "ls180.v:5788.63-5788.94"
- cell $not $not$ls180.v:5788$1200
+ attribute \src "ls180.v:5820.59-5820.90"
+ cell $not $not$ls180.v:5820$1193
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface2_bank_bus_we
- connect \Y $not$ls180.v:5788$1200_Y
+ connect \Y $not$ls180.v:5820$1193_Y
end
- attribute \src "ls180.v:5791.63-5791.94"
- cell $not $not$ls180.v:5791$1207
+ attribute \src "ls180.v:5823.58-5823.89"
+ cell $not $not$ls180.v:5823$1200
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface2_bank_bus_we
- connect \Y $not$ls180.v:5791$1207_Y
+ connect \Y $not$ls180.v:5823$1200_Y
end
- attribute \src "ls180.v:5794.63-5794.94"
- cell $not $not$ls180.v:5794$1214
+ attribute \src "ls180.v:5834.64-5834.95"
+ cell $not $not$ls180.v:5834$1208
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_we
- connect \Y $not$ls180.v:5794$1214_Y
- end
- attribute \src "ls180.v:5797.63-5797.94"
- cell $not $not$ls180.v:5797$1221
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_we
- connect \Y $not$ls180.v:5797$1221_Y
- end
- attribute \src "ls180.v:5800.64-5800.95"
- cell $not $not$ls180.v:5800$1228
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_we
- connect \Y $not$ls180.v:5800$1228_Y
+ connect \A \builder_interface3_bank_bus_we
+ connect \Y $not$ls180.v:5834$1208_Y
end
- attribute \src "ls180.v:5803.64-5803.95"
- cell $not $not$ls180.v:5803$1235
+ attribute \src "ls180.v:5837.63-5837.94"
+ cell $not $not$ls180.v:5837$1215
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_we
- connect \Y $not$ls180.v:5803$1235_Y
+ connect \A \builder_interface3_bank_bus_we
+ connect \Y $not$ls180.v:5837$1215_Y
end
- attribute \src "ls180.v:5806.64-5806.95"
- cell $not $not$ls180.v:5806$1242
+ attribute \src "ls180.v:5840.63-5840.94"
+ cell $not $not$ls180.v:5840$1222
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_we
- connect \Y $not$ls180.v:5806$1242_Y
+ connect \A \builder_interface3_bank_bus_we
+ connect \Y $not$ls180.v:5840$1222_Y
end
- attribute \src "ls180.v:5809.64-5809.95"
- cell $not $not$ls180.v:5809$1249
+ attribute \src "ls180.v:5843.63-5843.94"
+ cell $not $not$ls180.v:5843$1229
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface2_bank_bus_we
- connect \Y $not$ls180.v:5809$1249_Y
+ connect \A \builder_interface3_bank_bus_we
+ connect \Y $not$ls180.v:5843$1229_Y
end
- attribute \src "ls180.v:5822.64-5822.95"
- cell $not $not$ls180.v:5822$1257
+ attribute \src "ls180.v:5846.63-5846.94"
+ cell $not $not$ls180.v:5846$1236
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5822$1257_Y
+ connect \Y $not$ls180.v:5846$1236_Y
end
- attribute \src "ls180.v:5825.63-5825.94"
- cell $not $not$ls180.v:5825$1264
+ attribute \src "ls180.v:5849.64-5849.95"
+ cell $not $not$ls180.v:5849$1243
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5825$1264_Y
+ connect \Y $not$ls180.v:5849$1243_Y
end
- attribute \src "ls180.v:5828.63-5828.94"
- cell $not $not$ls180.v:5828$1271
+ attribute \src "ls180.v:5852.64-5852.95"
+ cell $not $not$ls180.v:5852$1250
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5828$1271_Y
+ connect \Y $not$ls180.v:5852$1250_Y
end
- attribute \src "ls180.v:5831.63-5831.94"
- cell $not $not$ls180.v:5831$1278
+ attribute \src "ls180.v:5855.64-5855.95"
+ cell $not $not$ls180.v:5855$1257
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5831$1278_Y
+ connect \Y $not$ls180.v:5855$1257_Y
end
- attribute \src "ls180.v:5834.63-5834.94"
- cell $not $not$ls180.v:5834$1285
+ attribute \src "ls180.v:5858.64-5858.95"
+ cell $not $not$ls180.v:5858$1264
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5834$1285_Y
+ connect \Y $not$ls180.v:5858$1264_Y
end
- attribute \src "ls180.v:5837.64-5837.95"
- cell $not $not$ls180.v:5837$1292
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5837$1292_Y
- end
- attribute \src "ls180.v:5840.64-5840.95"
- cell $not $not$ls180.v:5840$1299
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5840$1299_Y
- end
- attribute \src "ls180.v:5843.64-5843.95"
- cell $not $not$ls180.v:5843$1306
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5843$1306_Y
- end
- attribute \src "ls180.v:5846.64-5846.95"
- cell $not $not$ls180.v:5846$1313
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \builder_interface3_bank_bus_we
- connect \Y $not$ls180.v:5846$1313_Y
- end
- attribute \src "ls180.v:5859.66-5859.97"
- cell $not $not$ls180.v:5859$1321
+ attribute \src "ls180.v:5871.64-5871.95"
+ cell $not $not$ls180.v:5871$1272
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5859$1321_Y
+ connect \Y $not$ls180.v:5871$1272_Y
end
- attribute \src "ls180.v:5862.66-5862.97"
- cell $not $not$ls180.v:5862$1328
+ attribute \src "ls180.v:5874.63-5874.94"
+ cell $not $not$ls180.v:5874$1279
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5862$1328_Y
+ connect \Y $not$ls180.v:5874$1279_Y
end
- attribute \src "ls180.v:5865.66-5865.97"
- cell $not $not$ls180.v:5865$1335
+ attribute \src "ls180.v:5877.63-5877.94"
+ cell $not $not$ls180.v:5877$1286
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5865$1335_Y
+ connect \Y $not$ls180.v:5877$1286_Y
end
- attribute \src "ls180.v:5868.66-5868.97"
- cell $not $not$ls180.v:5868$1342
+ attribute \src "ls180.v:5880.63-5880.94"
+ cell $not $not$ls180.v:5880$1293
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5868$1342_Y
+ connect \Y $not$ls180.v:5880$1293_Y
end
- attribute \src "ls180.v:5871.66-5871.97"
- cell $not $not$ls180.v:5871$1349
+ attribute \src "ls180.v:5883.63-5883.94"
+ cell $not $not$ls180.v:5883$1300
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5871$1349_Y
+ connect \Y $not$ls180.v:5883$1300_Y
end
- attribute \src "ls180.v:5874.66-5874.97"
- cell $not $not$ls180.v:5874$1356
+ attribute \src "ls180.v:5886.64-5886.95"
+ cell $not $not$ls180.v:5886$1307
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5874$1356_Y
+ connect \Y $not$ls180.v:5886$1307_Y
end
- attribute \src "ls180.v:5877.66-5877.97"
- cell $not $not$ls180.v:5877$1363
+ attribute \src "ls180.v:5889.64-5889.95"
+ cell $not $not$ls180.v:5889$1314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5877$1363_Y
+ connect \Y $not$ls180.v:5889$1314_Y
end
- attribute \src "ls180.v:5880.66-5880.97"
- cell $not $not$ls180.v:5880$1370
+ attribute \src "ls180.v:5892.64-5892.95"
+ cell $not $not$ls180.v:5892$1321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5880$1370_Y
+ connect \Y $not$ls180.v:5892$1321_Y
end
- attribute \src "ls180.v:5883.68-5883.99"
- cell $not $not$ls180.v:5883$1377
+ attribute \src "ls180.v:5895.64-5895.95"
+ cell $not $not$ls180.v:5895$1328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5883$1377_Y
+ connect \Y $not$ls180.v:5895$1328_Y
end
- attribute \src "ls180.v:5886.68-5886.99"
- cell $not $not$ls180.v:5886$1384
+ attribute \src "ls180.v:5908.66-5908.97"
+ cell $not $not$ls180.v:5908$1336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5886$1384_Y
+ connect \A \builder_interface5_bank_bus_we
+ connect \Y $not$ls180.v:5908$1336_Y
end
- attribute \src "ls180.v:5889.68-5889.99"
- cell $not $not$ls180.v:5889$1391
+ attribute \src "ls180.v:5911.66-5911.97"
+ cell $not $not$ls180.v:5911$1343
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5889$1391_Y
+ connect \A \builder_interface5_bank_bus_we
+ connect \Y $not$ls180.v:5911$1343_Y
end
- attribute \src "ls180.v:5892.68-5892.99"
- cell $not $not$ls180.v:5892$1398
+ attribute \src "ls180.v:5914.66-5914.97"
+ cell $not $not$ls180.v:5914$1350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5892$1398_Y
+ connect \A \builder_interface5_bank_bus_we
+ connect \Y $not$ls180.v:5914$1350_Y
end
- attribute \src "ls180.v:5895.68-5895.99"
- cell $not $not$ls180.v:5895$1405
+ attribute \src "ls180.v:5917.66-5917.97"
+ cell $not $not$ls180.v:5917$1357
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5895$1405_Y
+ connect \A \builder_interface5_bank_bus_we
+ connect \Y $not$ls180.v:5917$1357_Y
end
- attribute \src "ls180.v:5898.65-5898.96"
- cell $not $not$ls180.v:5898$1412
+ attribute \src "ls180.v:5920.66-5920.97"
+ cell $not $not$ls180.v:5920$1364
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5898$1412_Y
+ connect \A \builder_interface5_bank_bus_we
+ connect \Y $not$ls180.v:5920$1364_Y
end
- attribute \src "ls180.v:5901.66-5901.97"
- cell $not $not$ls180.v:5901$1419
+ attribute \src "ls180.v:5923.66-5923.97"
+ cell $not $not$ls180.v:5923$1371
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface4_bank_bus_we
- connect \Y $not$ls180.v:5901$1419_Y
+ connect \A \builder_interface5_bank_bus_we
+ connect \Y $not$ls180.v:5923$1371_Y
end
- attribute \src "ls180.v:5921.70-5921.101"
- cell $not $not$ls180.v:5921$1427
+ attribute \src "ls180.v:5926.66-5926.97"
+ cell $not $not$ls180.v:5926$1378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5921$1427_Y
+ connect \Y $not$ls180.v:5926$1378_Y
end
- attribute \src "ls180.v:5924.70-5924.101"
- cell $not $not$ls180.v:5924$1434
+ attribute \src "ls180.v:5929.66-5929.97"
+ cell $not $not$ls180.v:5929$1385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5924$1434_Y
+ connect \Y $not$ls180.v:5929$1385_Y
end
- attribute \src "ls180.v:5927.70-5927.101"
- cell $not $not$ls180.v:5927$1441
+ attribute \src "ls180.v:5932.68-5932.99"
+ cell $not $not$ls180.v:5932$1392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5927$1441_Y
+ connect \Y $not$ls180.v:5932$1392_Y
end
- attribute \src "ls180.v:5930.70-5930.101"
- cell $not $not$ls180.v:5930$1448
+ attribute \src "ls180.v:5935.68-5935.99"
+ cell $not $not$ls180.v:5935$1399
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5930$1448_Y
+ connect \Y $not$ls180.v:5935$1399_Y
end
- attribute \src "ls180.v:5933.69-5933.100"
- cell $not $not$ls180.v:5933$1455
+ attribute \src "ls180.v:5938.68-5938.99"
+ cell $not $not$ls180.v:5938$1406
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5933$1455_Y
+ connect \Y $not$ls180.v:5938$1406_Y
end
- attribute \src "ls180.v:5936.69-5936.100"
- cell $not $not$ls180.v:5936$1462
+ attribute \src "ls180.v:5941.68-5941.99"
+ cell $not $not$ls180.v:5941$1413
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5936$1462_Y
+ connect \Y $not$ls180.v:5941$1413_Y
end
- attribute \src "ls180.v:5939.69-5939.100"
- cell $not $not$ls180.v:5939$1469
+ attribute \src "ls180.v:5944.68-5944.99"
+ cell $not $not$ls180.v:5944$1420
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5939$1469_Y
+ connect \Y $not$ls180.v:5944$1420_Y
end
- attribute \src "ls180.v:5942.69-5942.100"
- cell $not $not$ls180.v:5942$1476
+ attribute \src "ls180.v:5947.65-5947.96"
+ cell $not $not$ls180.v:5947$1427
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5942$1476_Y
+ connect \Y $not$ls180.v:5947$1427_Y
end
- attribute \src "ls180.v:5945.60-5945.91"
- cell $not $not$ls180.v:5945$1483
+ attribute \src "ls180.v:5950.66-5950.97"
+ cell $not $not$ls180.v:5950$1434
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5945$1483_Y
+ connect \Y $not$ls180.v:5950$1434_Y
end
- attribute \src "ls180.v:5948.71-5948.102"
- cell $not $not$ls180.v:5948$1490
+ attribute \src "ls180.v:5970.70-5970.101"
+ cell $not $not$ls180.v:5970$1442
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5948$1490_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:5970$1442_Y
end
- attribute \src "ls180.v:5951.71-5951.102"
- cell $not $not$ls180.v:5951$1497
+ attribute \src "ls180.v:5973.70-5973.101"
+ cell $not $not$ls180.v:5973$1449
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5951$1497_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:5973$1449_Y
end
- attribute \src "ls180.v:5954.71-5954.102"
- cell $not $not$ls180.v:5954$1504
+ attribute \src "ls180.v:5976.70-5976.101"
+ cell $not $not$ls180.v:5976$1456
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5954$1504_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:5976$1456_Y
end
- attribute \src "ls180.v:5957.71-5957.102"
- cell $not $not$ls180.v:5957$1511
+ attribute \src "ls180.v:5979.70-5979.101"
+ cell $not $not$ls180.v:5979$1463
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5957$1511_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:5979$1463_Y
end
- attribute \src "ls180.v:5960.71-5960.102"
- cell $not $not$ls180.v:5960$1518
+ attribute \src "ls180.v:5982.69-5982.100"
+ cell $not $not$ls180.v:5982$1470
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5960$1518_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:5982$1470_Y
end
- attribute \src "ls180.v:5963.71-5963.102"
- cell $not $not$ls180.v:5963$1525
+ attribute \src "ls180.v:5985.69-5985.100"
+ cell $not $not$ls180.v:5985$1477
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5963$1525_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:5985$1477_Y
end
- attribute \src "ls180.v:5966.70-5966.101"
- cell $not $not$ls180.v:5966$1532
+ attribute \src "ls180.v:5988.69-5988.100"
+ cell $not $not$ls180.v:5988$1484
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5966$1532_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:5988$1484_Y
end
- attribute \src "ls180.v:5969.70-5969.101"
- cell $not $not$ls180.v:5969$1539
+ attribute \src "ls180.v:5991.69-5991.100"
+ cell $not $not$ls180.v:5991$1491
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5969$1539_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:5991$1491_Y
end
- attribute \src "ls180.v:5972.70-5972.101"
- cell $not $not$ls180.v:5972$1546
+ attribute \src "ls180.v:5994.60-5994.91"
+ cell $not $not$ls180.v:5994$1498
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5972$1546_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:5994$1498_Y
end
- attribute \src "ls180.v:5975.70-5975.101"
- cell $not $not$ls180.v:5975$1553
+ attribute \src "ls180.v:5997.71-5997.102"
+ cell $not $not$ls180.v:5997$1505
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5975$1553_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:5997$1505_Y
end
- attribute \src "ls180.v:5978.70-5978.101"
- cell $not $not$ls180.v:5978$1560
+ attribute \src "ls180.v:6000.71-6000.102"
+ cell $not $not$ls180.v:6000$1512
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5978$1560_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6000$1512_Y
end
- attribute \src "ls180.v:5981.70-5981.101"
- cell $not $not$ls180.v:5981$1567
+ attribute \src "ls180.v:6003.71-6003.102"
+ cell $not $not$ls180.v:6003$1519
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5981$1567_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6003$1519_Y
end
- attribute \src "ls180.v:5984.70-5984.101"
- cell $not $not$ls180.v:5984$1574
+ attribute \src "ls180.v:6006.71-6006.102"
+ cell $not $not$ls180.v:6006$1526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5984$1574_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6006$1526_Y
end
- attribute \src "ls180.v:5987.70-5987.101"
- cell $not $not$ls180.v:5987$1581
+ attribute \src "ls180.v:6009.71-6009.102"
+ cell $not $not$ls180.v:6009$1533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5987$1581_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6009$1533_Y
end
- attribute \src "ls180.v:5990.70-5990.101"
- cell $not $not$ls180.v:5990$1588
+ attribute \src "ls180.v:6012.71-6012.102"
+ cell $not $not$ls180.v:6012$1540
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5990$1588_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6012$1540_Y
end
- attribute \src "ls180.v:5993.70-5993.101"
- cell $not $not$ls180.v:5993$1595
+ attribute \src "ls180.v:6015.70-6015.101"
+ cell $not $not$ls180.v:6015$1547
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5993$1595_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6015$1547_Y
end
- attribute \src "ls180.v:5996.66-5996.97"
- cell $not $not$ls180.v:5996$1602
+ attribute \src "ls180.v:6018.70-6018.101"
+ cell $not $not$ls180.v:6018$1554
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5996$1602_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6018$1554_Y
end
- attribute \src "ls180.v:5999.67-5999.98"
- cell $not $not$ls180.v:5999$1609
+ attribute \src "ls180.v:6021.70-6021.101"
+ cell $not $not$ls180.v:6021$1561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:5999$1609_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6021$1561_Y
end
- attribute \src "ls180.v:6002.70-6002.101"
- cell $not $not$ls180.v:6002$1616
+ attribute \src "ls180.v:6024.70-6024.101"
+ cell $not $not$ls180.v:6024$1568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:6002$1616_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6024$1568_Y
end
- attribute \src "ls180.v:6005.70-6005.101"
- cell $not $not$ls180.v:6005$1623
+ attribute \src "ls180.v:6027.70-6027.101"
+ cell $not $not$ls180.v:6027$1575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:6005$1623_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6027$1575_Y
end
- attribute \src "ls180.v:6008.69-6008.100"
- cell $not $not$ls180.v:6008$1630
+ attribute \src "ls180.v:6030.70-6030.101"
+ cell $not $not$ls180.v:6030$1582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:6008$1630_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6030$1582_Y
end
- attribute \src "ls180.v:6011.69-6011.100"
- cell $not $not$ls180.v:6011$1637
+ attribute \src "ls180.v:6033.70-6033.101"
+ cell $not $not$ls180.v:6033$1589
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:6011$1637_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6033$1589_Y
end
- attribute \src "ls180.v:6014.69-6014.100"
- cell $not $not$ls180.v:6014$1644
+ attribute \src "ls180.v:6036.70-6036.101"
+ cell $not $not$ls180.v:6036$1596
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:6014$1644_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6036$1596_Y
end
- attribute \src "ls180.v:6017.69-6017.100"
- cell $not $not$ls180.v:6017$1651
+ attribute \src "ls180.v:6039.70-6039.101"
+ cell $not $not$ls180.v:6039$1603
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface5_bank_bus_we
- connect \Y $not$ls180.v:6017$1651_Y
+ connect \A \builder_interface6_bank_bus_we
+ connect \Y $not$ls180.v:6039$1603_Y
end
- attribute \src "ls180.v:6056.66-6056.97"
- cell $not $not$ls180.v:6056$1659
+ attribute \src "ls180.v:6042.70-6042.101"
+ cell $not $not$ls180.v:6042$1610
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6056$1659_Y
+ connect \Y $not$ls180.v:6042$1610_Y
end
- attribute \src "ls180.v:6059.66-6059.97"
- cell $not $not$ls180.v:6059$1666
+ attribute \src "ls180.v:6045.66-6045.97"
+ cell $not $not$ls180.v:6045$1617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6059$1666_Y
+ connect \Y $not$ls180.v:6045$1617_Y
end
- attribute \src "ls180.v:6062.66-6062.97"
- cell $not $not$ls180.v:6062$1673
+ attribute \src "ls180.v:6048.67-6048.98"
+ cell $not $not$ls180.v:6048$1624
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6062$1673_Y
+ connect \Y $not$ls180.v:6048$1624_Y
end
- attribute \src "ls180.v:6065.66-6065.97"
- cell $not $not$ls180.v:6065$1680
+ attribute \src "ls180.v:6051.70-6051.101"
+ cell $not $not$ls180.v:6051$1631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6065$1680_Y
+ connect \Y $not$ls180.v:6051$1631_Y
end
- attribute \src "ls180.v:6068.66-6068.97"
- cell $not $not$ls180.v:6068$1687
+ attribute \src "ls180.v:6054.70-6054.101"
+ cell $not $not$ls180.v:6054$1638
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6068$1687_Y
+ connect \Y $not$ls180.v:6054$1638_Y
end
- attribute \src "ls180.v:6071.66-6071.97"
- cell $not $not$ls180.v:6071$1694
+ attribute \src "ls180.v:6057.69-6057.100"
+ cell $not $not$ls180.v:6057$1645
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6071$1694_Y
+ connect \Y $not$ls180.v:6057$1645_Y
end
- attribute \src "ls180.v:6074.66-6074.97"
- cell $not $not$ls180.v:6074$1701
+ attribute \src "ls180.v:6060.69-6060.100"
+ cell $not $not$ls180.v:6060$1652
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6074$1701_Y
+ connect \Y $not$ls180.v:6060$1652_Y
end
- attribute \src "ls180.v:6077.66-6077.97"
- cell $not $not$ls180.v:6077$1708
+ attribute \src "ls180.v:6063.69-6063.100"
+ cell $not $not$ls180.v:6063$1659
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6077$1708_Y
+ connect \Y $not$ls180.v:6063$1659_Y
end
- attribute \src "ls180.v:6080.68-6080.99"
- cell $not $not$ls180.v:6080$1715
+ attribute \src "ls180.v:6066.69-6066.100"
+ cell $not $not$ls180.v:6066$1666
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6080$1715_Y
+ connect \Y $not$ls180.v:6066$1666_Y
end
- attribute \src "ls180.v:6083.68-6083.99"
- cell $not $not$ls180.v:6083$1722
+ attribute \src "ls180.v:6105.66-6105.97"
+ cell $not $not$ls180.v:6105$1674
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6083$1722_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6105$1674_Y
end
- attribute \src "ls180.v:6086.68-6086.99"
- cell $not $not$ls180.v:6086$1729
+ attribute \src "ls180.v:6108.66-6108.97"
+ cell $not $not$ls180.v:6108$1681
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6086$1729_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6108$1681_Y
end
- attribute \src "ls180.v:6089.68-6089.99"
- cell $not $not$ls180.v:6089$1736
+ attribute \src "ls180.v:6111.66-6111.97"
+ cell $not $not$ls180.v:6111$1688
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6089$1736_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6111$1688_Y
end
- attribute \src "ls180.v:6092.68-6092.99"
- cell $not $not$ls180.v:6092$1743
+ attribute \src "ls180.v:6114.66-6114.97"
+ cell $not $not$ls180.v:6114$1695
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6092$1743_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6114$1695_Y
end
- attribute \src "ls180.v:6095.65-6095.96"
- cell $not $not$ls180.v:6095$1750
+ attribute \src "ls180.v:6117.66-6117.97"
+ cell $not $not$ls180.v:6117$1702
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6095$1750_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6117$1702_Y
end
- attribute \src "ls180.v:6098.66-6098.97"
- cell $not $not$ls180.v:6098$1757
+ attribute \src "ls180.v:6120.66-6120.97"
+ cell $not $not$ls180.v:6120$1709
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6098$1757_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6120$1709_Y
end
- attribute \src "ls180.v:6101.68-6101.99"
- cell $not $not$ls180.v:6101$1764
+ attribute \src "ls180.v:6123.66-6123.97"
+ cell $not $not$ls180.v:6123$1716
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6101$1764_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6123$1716_Y
end
- attribute \src "ls180.v:6104.68-6104.99"
- cell $not $not$ls180.v:6104$1771
+ attribute \src "ls180.v:6126.66-6126.97"
+ cell $not $not$ls180.v:6126$1723
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6104$1771_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6126$1723_Y
end
- attribute \src "ls180.v:6107.68-6107.99"
- cell $not $not$ls180.v:6107$1778
+ attribute \src "ls180.v:6129.68-6129.99"
+ cell $not $not$ls180.v:6129$1730
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6107$1778_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6129$1730_Y
end
- attribute \src "ls180.v:6110.68-6110.99"
- cell $not $not$ls180.v:6110$1785
+ attribute \src "ls180.v:6132.68-6132.99"
+ cell $not $not$ls180.v:6132$1737
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface6_bank_bus_we
- connect \Y $not$ls180.v:6110$1785_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6132$1737_Y
end
attribute \src "ls180.v:6135.68-6135.99"
- cell $not $not$ls180.v:6135$1793
+ cell $not $not$ls180.v:6135$1744
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6135$1793_Y
+ connect \Y $not$ls180.v:6135$1744_Y
end
- attribute \src "ls180.v:6138.73-6138.104"
- cell $not $not$ls180.v:6138$1800
+ attribute \src "ls180.v:6138.68-6138.99"
+ cell $not $not$ls180.v:6138$1751
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6138$1800_Y
+ connect \Y $not$ls180.v:6138$1751_Y
end
- attribute \src "ls180.v:6141.73-6141.104"
- cell $not $not$ls180.v:6141$1807
+ attribute \src "ls180.v:6141.68-6141.99"
+ cell $not $not$ls180.v:6141$1758
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6141$1807_Y
+ connect \Y $not$ls180.v:6141$1758_Y
end
- attribute \src "ls180.v:6144.66-6144.97"
- cell $not $not$ls180.v:6144$1814
+ attribute \src "ls180.v:6144.65-6144.96"
+ cell $not $not$ls180.v:6144$1765
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface7_bank_bus_we
- connect \Y $not$ls180.v:6144$1814_Y
+ connect \Y $not$ls180.v:6144$1765_Y
end
- attribute \src "ls180.v:6152.70-6152.101"
- cell $not $not$ls180.v:6152$1822
+ attribute \src "ls180.v:6147.66-6147.97"
+ cell $not $not$ls180.v:6147$1772
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6152$1822_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6147$1772_Y
end
- attribute \src "ls180.v:6155.74-6155.105"
- cell $not $not$ls180.v:6155$1829
+ attribute \src "ls180.v:6150.68-6150.99"
+ cell $not $not$ls180.v:6150$1779
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6155$1829_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6150$1779_Y
end
- attribute \src "ls180.v:6158.64-6158.95"
- cell $not $not$ls180.v:6158$1836
+ attribute \src "ls180.v:6153.68-6153.99"
+ cell $not $not$ls180.v:6153$1786
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6158$1836_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6153$1786_Y
end
- attribute \src "ls180.v:6161.74-6161.105"
- cell $not $not$ls180.v:6161$1843
+ attribute \src "ls180.v:6156.68-6156.99"
+ cell $not $not$ls180.v:6156$1793
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6161$1843_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6156$1793_Y
end
- attribute \src "ls180.v:6164.74-6164.105"
- cell $not $not$ls180.v:6164$1850
+ attribute \src "ls180.v:6159.68-6159.99"
+ cell $not $not$ls180.v:6159$1800
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6164$1850_Y
+ connect \A \builder_interface7_bank_bus_we
+ connect \Y $not$ls180.v:6159$1800_Y
end
- attribute \src "ls180.v:6167.75-6167.106"
- cell $not $not$ls180.v:6167$1857
+ attribute \src "ls180.v:6184.68-6184.99"
+ cell $not $not$ls180.v:6184$1808
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6167$1857_Y
+ connect \Y $not$ls180.v:6184$1808_Y
end
- attribute \src "ls180.v:6170.73-6170.104"
- cell $not $not$ls180.v:6170$1864
+ attribute \src "ls180.v:6187.73-6187.104"
+ cell $not $not$ls180.v:6187$1815
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6170$1864_Y
+ connect \Y $not$ls180.v:6187$1815_Y
end
- attribute \src "ls180.v:6173.73-6173.104"
- cell $not $not$ls180.v:6173$1871
+ attribute \src "ls180.v:6190.73-6190.104"
+ cell $not $not$ls180.v:6190$1822
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6173$1871_Y
+ connect \Y $not$ls180.v:6190$1822_Y
end
- attribute \src "ls180.v:6176.73-6176.104"
- cell $not $not$ls180.v:6176$1878
+ attribute \src "ls180.v:6193.66-6193.97"
+ cell $not $not$ls180.v:6193$1829
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6176$1878_Y
+ connect \Y $not$ls180.v:6193$1829_Y
end
- attribute \src "ls180.v:6179.73-6179.104"
- cell $not $not$ls180.v:6179$1885
+ attribute \src "ls180.v:6201.70-6201.101"
+ cell $not $not$ls180.v:6201$1837
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface8_bank_bus_we
- connect \Y $not$ls180.v:6179$1885_Y
+ connect \A \builder_interface9_bank_bus_we
+ connect \Y $not$ls180.v:6201$1837_Y
end
- attribute \src "ls180.v:6197.65-6197.96"
- cell $not $not$ls180.v:6197$1893
+ attribute \src "ls180.v:6204.74-6204.105"
+ cell $not $not$ls180.v:6204$1844
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6197$1893_Y
+ connect \Y $not$ls180.v:6204$1844_Y
end
- attribute \src "ls180.v:6200.65-6200.96"
- cell $not $not$ls180.v:6200$1900
+ attribute \src "ls180.v:6207.64-6207.95"
+ cell $not $not$ls180.v:6207$1851
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6200$1900_Y
+ connect \Y $not$ls180.v:6207$1851_Y
end
- attribute \src "ls180.v:6203.63-6203.94"
- cell $not $not$ls180.v:6203$1907
+ attribute \src "ls180.v:6210.74-6210.105"
+ cell $not $not$ls180.v:6210$1858
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6203$1907_Y
+ connect \Y $not$ls180.v:6210$1858_Y
end
- attribute \src "ls180.v:6206.62-6206.93"
- cell $not $not$ls180.v:6206$1914
+ attribute \src "ls180.v:6213.74-6213.105"
+ cell $not $not$ls180.v:6213$1865
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6206$1914_Y
+ connect \Y $not$ls180.v:6213$1865_Y
end
- attribute \src "ls180.v:6209.61-6209.92"
- cell $not $not$ls180.v:6209$1921
+ attribute \src "ls180.v:6216.75-6216.106"
+ cell $not $not$ls180.v:6216$1872
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6209$1921_Y
+ connect \Y $not$ls180.v:6216$1872_Y
end
- attribute \src "ls180.v:6212.60-6212.91"
- cell $not $not$ls180.v:6212$1928
+ attribute \src "ls180.v:6219.73-6219.104"
+ cell $not $not$ls180.v:6219$1879
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6212$1928_Y
+ connect \Y $not$ls180.v:6219$1879_Y
end
- attribute \src "ls180.v:6215.66-6215.97"
- cell $not $not$ls180.v:6215$1935
+ attribute \src "ls180.v:6222.73-6222.104"
+ cell $not $not$ls180.v:6222$1886
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface9_bank_bus_we
- connect \Y $not$ls180.v:6215$1935_Y
+ connect \Y $not$ls180.v:6222$1886_Y
end
- attribute \src "ls180.v:6237.67-6237.99"
- cell $not $not$ls180.v:6237$1944
+ attribute \src "ls180.v:6225.73-6225.104"
+ cell $not $not$ls180.v:6225$1893
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6237$1944_Y
+ connect \A \builder_interface9_bank_bus_we
+ connect \Y $not$ls180.v:6225$1893_Y
end
- attribute \src "ls180.v:6240.67-6240.99"
- cell $not $not$ls180.v:6240$1951
+ attribute \src "ls180.v:6228.73-6228.104"
+ cell $not $not$ls180.v:6228$1900
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6240$1951_Y
+ connect \A \builder_interface9_bank_bus_we
+ connect \Y $not$ls180.v:6228$1900_Y
end
- attribute \src "ls180.v:6243.65-6243.97"
- cell $not $not$ls180.v:6243$1958
+ attribute \src "ls180.v:6246.67-6246.99"
+ cell $not $not$ls180.v:6246$1908
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6243$1958_Y
+ connect \Y $not$ls180.v:6246$1908_Y
end
- attribute \src "ls180.v:6246.64-6246.96"
- cell $not $not$ls180.v:6246$1965
+ attribute \src "ls180.v:6249.67-6249.99"
+ cell $not $not$ls180.v:6249$1915
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6246$1965_Y
+ connect \Y $not$ls180.v:6249$1915_Y
end
- attribute \src "ls180.v:6249.63-6249.95"
- cell $not $not$ls180.v:6249$1972
+ attribute \src "ls180.v:6252.65-6252.97"
+ cell $not $not$ls180.v:6252$1922
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6249$1972_Y
+ connect \Y $not$ls180.v:6252$1922_Y
end
- attribute \src "ls180.v:6252.62-6252.94"
- cell $not $not$ls180.v:6252$1979
+ attribute \src "ls180.v:6255.64-6255.96"
+ cell $not $not$ls180.v:6255$1929
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6252$1979_Y
+ connect \Y $not$ls180.v:6255$1929_Y
end
- attribute \src "ls180.v:6255.68-6255.100"
- cell $not $not$ls180.v:6255$1986
+ attribute \src "ls180.v:6258.63-6258.95"
+ cell $not $not$ls180.v:6258$1936
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6255$1986_Y
+ connect \Y $not$ls180.v:6258$1936_Y
end
- attribute \src "ls180.v:6258.71-6258.103"
- cell $not $not$ls180.v:6258$1993
+ attribute \src "ls180.v:6261.62-6261.94"
+ cell $not $not$ls180.v:6261$1943
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6258$1993_Y
+ connect \Y $not$ls180.v:6261$1943_Y
end
- attribute \src "ls180.v:6261.71-6261.103"
- cell $not $not$ls180.v:6261$2000
+ attribute \src "ls180.v:6264.68-6264.100"
+ cell $not $not$ls180.v:6264$1950
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface10_bank_bus_we
- connect \Y $not$ls180.v:6261$2000_Y
+ connect \Y $not$ls180.v:6264$1950_Y
end
- attribute \src "ls180.v:6285.64-6285.96"
- cell $not $not$ls180.v:6285$2009
+ attribute \src "ls180.v:6286.67-6286.99"
+ cell $not $not$ls180.v:6286$1959
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6285$2009_Y
+ connect \Y $not$ls180.v:6286$1959_Y
end
- attribute \src "ls180.v:6288.64-6288.96"
- cell $not $not$ls180.v:6288$2016
+ attribute \src "ls180.v:6289.67-6289.99"
+ cell $not $not$ls180.v:6289$1966
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6288$2016_Y
+ connect \Y $not$ls180.v:6289$1966_Y
end
- attribute \src "ls180.v:6291.64-6291.96"
- cell $not $not$ls180.v:6291$2023
+ attribute \src "ls180.v:6292.65-6292.97"
+ cell $not $not$ls180.v:6292$1973
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6291$2023_Y
+ connect \Y $not$ls180.v:6292$1973_Y
end
- attribute \src "ls180.v:6294.64-6294.96"
- cell $not $not$ls180.v:6294$2030
+ attribute \src "ls180.v:6295.64-6295.96"
+ cell $not $not$ls180.v:6295$1980
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6294$2030_Y
+ connect \Y $not$ls180.v:6295$1980_Y
end
- attribute \src "ls180.v:6297.66-6297.98"
- cell $not $not$ls180.v:6297$2037
+ attribute \src "ls180.v:6298.63-6298.95"
+ cell $not $not$ls180.v:6298$1987
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6297$2037_Y
+ connect \Y $not$ls180.v:6298$1987_Y
end
- attribute \src "ls180.v:6300.66-6300.98"
- cell $not $not$ls180.v:6300$2044
+ attribute \src "ls180.v:6301.62-6301.94"
+ cell $not $not$ls180.v:6301$1994
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6300$2044_Y
+ connect \Y $not$ls180.v:6301$1994_Y
end
- attribute \src "ls180.v:6303.66-6303.98"
- cell $not $not$ls180.v:6303$2051
+ attribute \src "ls180.v:6304.68-6304.100"
+ cell $not $not$ls180.v:6304$2001
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6303$2051_Y
+ connect \Y $not$ls180.v:6304$2001_Y
end
- attribute \src "ls180.v:6306.66-6306.98"
- cell $not $not$ls180.v:6306$2058
+ attribute \src "ls180.v:6307.71-6307.103"
+ cell $not $not$ls180.v:6307$2008
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6306$2058_Y
+ connect \Y $not$ls180.v:6307$2008_Y
end
- attribute \src "ls180.v:6309.62-6309.94"
- cell $not $not$ls180.v:6309$2065
+ attribute \src "ls180.v:6310.71-6310.103"
+ cell $not $not$ls180.v:6310$2015
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6309$2065_Y
+ connect \Y $not$ls180.v:6310$2015_Y
end
- attribute \src "ls180.v:6312.72-6312.104"
- cell $not $not$ls180.v:6312$2072
+ attribute \src "ls180.v:6334.64-6334.96"
+ cell $not $not$ls180.v:6334$2024
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6312$2072_Y
+ connect \A \builder_interface12_bank_bus_we
+ connect \Y $not$ls180.v:6334$2024_Y
end
- attribute \src "ls180.v:6315.65-6315.97"
- cell $not $not$ls180.v:6315$2079
+ attribute \src "ls180.v:6337.64-6337.96"
+ cell $not $not$ls180.v:6337$2031
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6315$2079_Y
+ connect \A \builder_interface12_bank_bus_we
+ connect \Y $not$ls180.v:6337$2031_Y
end
- attribute \src "ls180.v:6318.65-6318.97"
- cell $not $not$ls180.v:6318$2086
+ attribute \src "ls180.v:6340.64-6340.96"
+ cell $not $not$ls180.v:6340$2038
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6318$2086_Y
+ connect \A \builder_interface12_bank_bus_we
+ connect \Y $not$ls180.v:6340$2038_Y
end
- attribute \src "ls180.v:6321.65-6321.97"
- cell $not $not$ls180.v:6321$2093
+ attribute \src "ls180.v:6343.64-6343.96"
+ cell $not $not$ls180.v:6343$2045
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6321$2093_Y
+ connect \A \builder_interface12_bank_bus_we
+ connect \Y $not$ls180.v:6343$2045_Y
end
- attribute \src "ls180.v:6324.65-6324.97"
- cell $not $not$ls180.v:6324$2100
+ attribute \src "ls180.v:6346.66-6346.98"
+ cell $not $not$ls180.v:6346$2052
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6324$2100_Y
+ connect \A \builder_interface12_bank_bus_we
+ connect \Y $not$ls180.v:6346$2052_Y
end
- attribute \src "ls180.v:6327.77-6327.109"
- cell $not $not$ls180.v:6327$2107
+ attribute \src "ls180.v:6349.66-6349.98"
+ cell $not $not$ls180.v:6349$2059
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6327$2107_Y
+ connect \A \builder_interface12_bank_bus_we
+ connect \Y $not$ls180.v:6349$2059_Y
end
- attribute \src "ls180.v:6330.78-6330.110"
- cell $not $not$ls180.v:6330$2114
+ attribute \src "ls180.v:6352.66-6352.98"
+ cell $not $not$ls180.v:6352$2066
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6330$2114_Y
+ connect \A \builder_interface12_bank_bus_we
+ connect \Y $not$ls180.v:6352$2066_Y
end
- attribute \src "ls180.v:6333.69-6333.101"
- cell $not $not$ls180.v:6333$2121
+ attribute \src "ls180.v:6355.66-6355.98"
+ cell $not $not$ls180.v:6355$2073
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \builder_interface11_bank_bus_we
- connect \Y $not$ls180.v:6333$2121_Y
+ connect \A \builder_interface12_bank_bus_we
+ connect \Y $not$ls180.v:6355$2073_Y
end
- attribute \src "ls180.v:6353.55-6353.87"
- cell $not $not$ls180.v:6353$2129
+ attribute \src "ls180.v:6358.62-6358.94"
+ cell $not $not$ls180.v:6358$2080
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6353$2129_Y
+ connect \Y $not$ls180.v:6358$2080_Y
end
- attribute \src "ls180.v:6356.65-6356.97"
- cell $not $not$ls180.v:6356$2136
+ attribute \src "ls180.v:6361.72-6361.104"
+ cell $not $not$ls180.v:6361$2087
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6356$2136_Y
+ connect \Y $not$ls180.v:6361$2087_Y
end
- attribute \src "ls180.v:6359.66-6359.98"
- cell $not $not$ls180.v:6359$2143
+ attribute \src "ls180.v:6364.65-6364.97"
+ cell $not $not$ls180.v:6364$2094
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6359$2143_Y
+ connect \Y $not$ls180.v:6364$2094_Y
end
- attribute \src "ls180.v:6362.70-6362.102"
- cell $not $not$ls180.v:6362$2150
+ attribute \src "ls180.v:6367.65-6367.97"
+ cell $not $not$ls180.v:6367$2101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6362$2150_Y
+ connect \Y $not$ls180.v:6367$2101_Y
end
- attribute \src "ls180.v:6365.71-6365.103"
- cell $not $not$ls180.v:6365$2157
+ attribute \src "ls180.v:6370.65-6370.97"
+ cell $not $not$ls180.v:6370$2108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6365$2157_Y
+ connect \Y $not$ls180.v:6370$2108_Y
end
- attribute \src "ls180.v:6368.69-6368.101"
- cell $not $not$ls180.v:6368$2164
+ attribute \src "ls180.v:6373.65-6373.97"
+ cell $not $not$ls180.v:6373$2115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6368$2164_Y
+ connect \Y $not$ls180.v:6373$2115_Y
end
- attribute \src "ls180.v:6371.66-6371.98"
- cell $not $not$ls180.v:6371$2171
+ attribute \src "ls180.v:6376.77-6376.109"
+ cell $not $not$ls180.v:6376$2122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6371$2171_Y
+ connect \Y $not$ls180.v:6376$2122_Y
end
- attribute \src "ls180.v:6374.65-6374.97"
- cell $not $not$ls180.v:6374$2178
+ attribute \src "ls180.v:6379.78-6379.110"
+ cell $not $not$ls180.v:6379$2129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface12_bank_bus_we
- connect \Y $not$ls180.v:6374$2178_Y
+ connect \Y $not$ls180.v:6379$2129_Y
end
- attribute \src "ls180.v:6387.71-6387.103"
- cell $not $not$ls180.v:6387$2186
+ attribute \src "ls180.v:6382.69-6382.101"
+ cell $not $not$ls180.v:6382$2136
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface12_bank_bus_we
+ connect \Y $not$ls180.v:6382$2136_Y
+ end
+ attribute \src "ls180.v:6402.55-6402.87"
+ cell $not $not$ls180.v:6402$2144
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_we
- connect \Y $not$ls180.v:6387$2186_Y
+ connect \Y $not$ls180.v:6402$2144_Y
end
- attribute \src "ls180.v:6390.71-6390.103"
- cell $not $not$ls180.v:6390$2193
+ attribute \src "ls180.v:6405.65-6405.97"
+ cell $not $not$ls180.v:6405$2151
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_we
- connect \Y $not$ls180.v:6390$2193_Y
+ connect \Y $not$ls180.v:6405$2151_Y
end
- attribute \src "ls180.v:6393.71-6393.103"
- cell $not $not$ls180.v:6393$2200
+ attribute \src "ls180.v:6408.66-6408.98"
+ cell $not $not$ls180.v:6408$2158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_we
- connect \Y $not$ls180.v:6393$2200_Y
+ connect \Y $not$ls180.v:6408$2158_Y
end
- attribute \src "ls180.v:6396.71-6396.103"
- cell $not $not$ls180.v:6396$2207
+ attribute \src "ls180.v:6411.70-6411.102"
+ cell $not $not$ls180.v:6411$2165
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_interface13_bank_bus_we
- connect \Y $not$ls180.v:6396$2207_Y
+ connect \Y $not$ls180.v:6411$2165_Y
+ end
+ attribute \src "ls180.v:6414.71-6414.103"
+ cell $not $not$ls180.v:6414$2172
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface13_bank_bus_we
+ connect \Y $not$ls180.v:6414$2172_Y
+ end
+ attribute \src "ls180.v:6417.69-6417.101"
+ cell $not $not$ls180.v:6417$2179
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface13_bank_bus_we
+ connect \Y $not$ls180.v:6417$2179_Y
+ end
+ attribute \src "ls180.v:6420.66-6420.98"
+ cell $not $not$ls180.v:6420$2186
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface13_bank_bus_we
+ connect \Y $not$ls180.v:6420$2186_Y
+ end
+ attribute \src "ls180.v:6423.65-6423.97"
+ cell $not $not$ls180.v:6423$2193
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface13_bank_bus_we
+ connect \Y $not$ls180.v:6423$2193_Y
+ end
+ attribute \src "ls180.v:6436.71-6436.103"
+ cell $not $not$ls180.v:6436$2201
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface14_bank_bus_we
+ connect \Y $not$ls180.v:6436$2201_Y
+ end
+ attribute \src "ls180.v:6439.71-6439.103"
+ cell $not $not$ls180.v:6439$2208
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface14_bank_bus_we
+ connect \Y $not$ls180.v:6439$2208_Y
+ end
+ attribute \src "ls180.v:6442.71-6442.103"
+ cell $not $not$ls180.v:6442$2215
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface14_bank_bus_we
+ connect \Y $not$ls180.v:6442$2215_Y
+ end
+ attribute \src "ls180.v:6445.71-6445.103"
+ cell $not $not$ls180.v:6445$2222
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \builder_interface14_bank_bus_we
+ connect \Y $not$ls180.v:6445$2222_Y
end
- attribute \src "ls180.v:6774.86-6774.330"
- cell $not $not$ls180.v:6774$2255
+ attribute \src "ls180.v:6826.86-6826.330"
+ cell $not $not$ls180.v:6826$2271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6774$2254_Y
- connect \Y $not$ls180.v:6774$2255_Y
+ connect \A $or$ls180.v:6826$2270_Y
+ connect \Y $not$ls180.v:6826$2271_Y
end
- attribute \src "ls180.v:6798.86-6798.330"
- cell $not $not$ls180.v:6798$2271
+ attribute \src "ls180.v:6850.86-6850.330"
+ cell $not $not$ls180.v:6850$2287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6798$2270_Y
- connect \Y $not$ls180.v:6798$2271_Y
+ connect \A $or$ls180.v:6850$2286_Y
+ connect \Y $not$ls180.v:6850$2287_Y
end
- attribute \src "ls180.v:6822.86-6822.330"
- cell $not $not$ls180.v:6822$2287
+ attribute \src "ls180.v:6874.86-6874.330"
+ cell $not $not$ls180.v:6874$2303
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6822$2286_Y
- connect \Y $not$ls180.v:6822$2287_Y
+ connect \A $or$ls180.v:6874$2302_Y
+ connect \Y $not$ls180.v:6874$2303_Y
end
- attribute \src "ls180.v:6846.86-6846.330"
- cell $not $not$ls180.v:6846$2303
+ attribute \src "ls180.v:6898.86-6898.330"
+ cell $not $not$ls180.v:6898$2319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6846$2302_Y
- connect \Y $not$ls180.v:6846$2303_Y
+ connect \A $or$ls180.v:6898$2318_Y
+ connect \Y $not$ls180.v:6898$2319_Y
end
- attribute \src "ls180.v:7344.18-7344.42"
- cell $not $not$ls180.v:7344$2356
+ attribute \src "ls180.v:7396.18-7396.42"
+ cell $not $not$ls180.v:7396$2372
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_clocker_clk0
- connect \Y $not$ls180.v:7344$2356_Y
+ connect \Y $not$ls180.v:7396$2372_Y
end
- attribute \src "ls180.v:7441.72-7441.101"
- cell $not $not$ls180.v:7441$2407
+ attribute \src "ls180.v:7487.72-7487.101"
+ cell $not $not$ls180.v:7487$2417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_ack
- connect \Y $not$ls180.v:7441$2407_Y
+ connect \Y $not$ls180.v:7487$2417_Y
end
- attribute \src "ls180.v:7460.8-7460.38"
- cell $not $not$ls180.v:7460$2411
+ attribute \src "ls180.v:7506.8-7506.38"
+ cell $not $not$ls180.v:7506$2421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_libresocsim_zero_trigger
- connect \Y $not$ls180.v:7460$2411_Y
+ connect \Y $not$ls180.v:7506$2421_Y
end
- attribute \src "ls180.v:7468.32-7468.55"
- cell $not $not$ls180.v:7468$2413
+ attribute \src "ls180.v:7514.32-7514.55"
+ cell $not $not$ls180.v:7514$2423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_timer_done0
- connect \Y $not$ls180.v:7468$2413_Y
+ connect \Y $not$ls180.v:7514$2423_Y
end
- attribute \src "ls180.v:7538.136-7538.189"
- cell $not $not$ls180.v:7538$2428
+ attribute \src "ls180.v:7584.136-7584.189"
+ cell $not $not$ls180.v:7584$2438
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7538$2428_Y
+ connect \Y $not$ls180.v:7584$2438_Y
end
- attribute \src "ls180.v:7544.136-7544.189"
- cell $not $not$ls180.v:7544$2433
+ attribute \src "ls180.v:7590.136-7590.189"
+ cell $not $not$ls180.v:7590$2443
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7544$2433_Y
+ connect \Y $not$ls180.v:7590$2443_Y
end
- attribute \src "ls180.v:7545.8-7545.61"
- cell $not $not$ls180.v:7545$2435
+ attribute \src "ls180.v:7591.8-7591.61"
+ cell $not $not$ls180.v:7591$2445
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
- connect \Y $not$ls180.v:7545$2435_Y
+ connect \Y $not$ls180.v:7591$2445_Y
end
- attribute \src "ls180.v:7553.8-7553.56"
- cell $not $not$ls180.v:7553$2438
+ attribute \src "ls180.v:7599.8-7599.56"
+ cell $not $not$ls180.v:7599$2448
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid
- connect \Y $not$ls180.v:7553$2438_Y
+ connect \Y $not$ls180.v:7599$2448_Y
end
- attribute \src "ls180.v:7568.8-7568.46"
- cell $not $not$ls180.v:7568$2440
+ attribute \src "ls180.v:7614.8-7614.46"
+ cell $not $not$ls180.v:7614$2450
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_twtpcon_ready
- connect \Y $not$ls180.v:7568$2440_Y
+ connect \Y $not$ls180.v:7614$2450_Y
end
- attribute \src "ls180.v:7584.136-7584.189"
- cell $not $not$ls180.v:7584$2444
+ attribute \src "ls180.v:7630.136-7630.189"
+ cell $not $not$ls180.v:7630$2454
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7584$2444_Y
+ connect \Y $not$ls180.v:7630$2454_Y
end
- attribute \src "ls180.v:7590.136-7590.189"
- cell $not $not$ls180.v:7590$2449
+ attribute \src "ls180.v:7636.136-7636.189"
+ cell $not $not$ls180.v:7636$2459
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7590$2449_Y
+ connect \Y $not$ls180.v:7636$2459_Y
end
- attribute \src "ls180.v:7591.8-7591.61"
- cell $not $not$ls180.v:7591$2451
+ attribute \src "ls180.v:7637.8-7637.61"
+ cell $not $not$ls180.v:7637$2461
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
- connect \Y $not$ls180.v:7591$2451_Y
+ connect \Y $not$ls180.v:7637$2461_Y
end
- attribute \src "ls180.v:7599.8-7599.56"
- cell $not $not$ls180.v:7599$2454
+ attribute \src "ls180.v:7645.8-7645.56"
+ cell $not $not$ls180.v:7645$2464
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid
- connect \Y $not$ls180.v:7599$2454_Y
+ connect \Y $not$ls180.v:7645$2464_Y
end
- attribute \src "ls180.v:7614.8-7614.46"
- cell $not $not$ls180.v:7614$2456
+ attribute \src "ls180.v:7660.8-7660.46"
+ cell $not $not$ls180.v:7660$2466
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_twtpcon_ready
- connect \Y $not$ls180.v:7614$2456_Y
+ connect \Y $not$ls180.v:7660$2466_Y
end
- attribute \src "ls180.v:7630.136-7630.189"
- cell $not $not$ls180.v:7630$2460
+ attribute \src "ls180.v:7676.136-7676.189"
+ cell $not $not$ls180.v:7676$2470
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7630$2460_Y
+ connect \Y $not$ls180.v:7676$2470_Y
end
- attribute \src "ls180.v:7636.136-7636.189"
- cell $not $not$ls180.v:7636$2465
+ attribute \src "ls180.v:7682.136-7682.189"
+ cell $not $not$ls180.v:7682$2475
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7636$2465_Y
+ connect \Y $not$ls180.v:7682$2475_Y
end
- attribute \src "ls180.v:7637.8-7637.61"
- cell $not $not$ls180.v:7637$2467
+ attribute \src "ls180.v:7683.8-7683.61"
+ cell $not $not$ls180.v:7683$2477
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
- connect \Y $not$ls180.v:7637$2467_Y
+ connect \Y $not$ls180.v:7683$2477_Y
end
- attribute \src "ls180.v:7645.8-7645.56"
- cell $not $not$ls180.v:7645$2470
+ attribute \src "ls180.v:7691.8-7691.56"
+ cell $not $not$ls180.v:7691$2480
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid
- connect \Y $not$ls180.v:7645$2470_Y
+ connect \Y $not$ls180.v:7691$2480_Y
end
- attribute \src "ls180.v:7660.8-7660.46"
- cell $not $not$ls180.v:7660$2472
+ attribute \src "ls180.v:7706.8-7706.46"
+ cell $not $not$ls180.v:7706$2482
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_twtpcon_ready
- connect \Y $not$ls180.v:7660$2472_Y
+ connect \Y $not$ls180.v:7706$2482_Y
end
- attribute \src "ls180.v:7676.136-7676.189"
- cell $not $not$ls180.v:7676$2476
+ attribute \src "ls180.v:7722.136-7722.189"
+ cell $not $not$ls180.v:7722$2486
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7676$2476_Y
+ connect \Y $not$ls180.v:7722$2486_Y
end
- attribute \src "ls180.v:7682.136-7682.189"
- cell $not $not$ls180.v:7682$2481
+ attribute \src "ls180.v:7728.136-7728.189"
+ cell $not $not$ls180.v:7728$2491
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:7682$2481_Y
+ connect \Y $not$ls180.v:7728$2491_Y
end
- attribute \src "ls180.v:7683.8-7683.61"
- cell $not $not$ls180.v:7683$2483
+ attribute \src "ls180.v:7729.8-7729.61"
+ cell $not $not$ls180.v:7729$2493
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
- connect \Y $not$ls180.v:7683$2483_Y
+ connect \Y $not$ls180.v:7729$2493_Y
end
- attribute \src "ls180.v:7691.8-7691.56"
- cell $not $not$ls180.v:7691$2486
+ attribute \src "ls180.v:7737.8-7737.56"
+ cell $not $not$ls180.v:7737$2496
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid
- connect \Y $not$ls180.v:7691$2486_Y
+ connect \Y $not$ls180.v:7737$2496_Y
end
- attribute \src "ls180.v:7706.8-7706.46"
- cell $not $not$ls180.v:7706$2488
+ attribute \src "ls180.v:7752.8-7752.46"
+ cell $not $not$ls180.v:7752$2498
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_twtpcon_ready
- connect \Y $not$ls180.v:7706$2488_Y
+ connect \Y $not$ls180.v:7752$2498_Y
end
- attribute \src "ls180.v:7714.7-7714.22"
- cell $not $not$ls180.v:7714$2491
+ attribute \src "ls180.v:7760.7-7760.22"
+ cell $not $not$ls180.v:7760$2501
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_en0
- connect \Y $not$ls180.v:7714$2491_Y
+ connect \Y $not$ls180.v:7760$2501_Y
end
- attribute \src "ls180.v:7717.8-7717.29"
- cell $not $not$ls180.v:7717$2492
+ attribute \src "ls180.v:7763.8-7763.29"
+ cell $not $not$ls180.v:7763$2502
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_max_time0
- connect \Y $not$ls180.v:7717$2492_Y
+ connect \Y $not$ls180.v:7763$2502_Y
end
- attribute \src "ls180.v:7721.7-7721.22"
- cell $not $not$ls180.v:7721$2494
+ attribute \src "ls180.v:7767.7-7767.22"
+ cell $not $not$ls180.v:7767$2504
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_en1
- connect \Y $not$ls180.v:7721$2494_Y
+ connect \Y $not$ls180.v:7767$2504_Y
end
- attribute \src "ls180.v:7724.8-7724.29"
- cell $not $not$ls180.v:7724$2495
+ attribute \src "ls180.v:7770.8-7770.29"
+ cell $not $not$ls180.v:7770$2505
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_max_time1
- connect \Y $not$ls180.v:7724$2495_Y
+ connect \Y $not$ls180.v:7770$2505_Y
end
- attribute \src "ls180.v:7843.30-7843.60"
- cell $not $not$ls180.v:7843$2497
+ attribute \src "ls180.v:7889.30-7889.60"
+ cell $not $not$ls180.v:7889$2507
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_sync_rhs_array_muxed2
- connect \Y $not$ls180.v:7843$2497_Y
+ connect \Y $not$ls180.v:7889$2507_Y
end
- attribute \src "ls180.v:7844.30-7844.60"
- cell $not $not$ls180.v:7844$2498
+ attribute \src "ls180.v:7890.30-7890.60"
+ cell $not $not$ls180.v:7890$2508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_sync_rhs_array_muxed3
- connect \Y $not$ls180.v:7844$2498_Y
+ connect \Y $not$ls180.v:7890$2508_Y
end
- attribute \src "ls180.v:7845.29-7845.59"
- cell $not $not$ls180.v:7845$2499
+ attribute \src "ls180.v:7891.29-7891.59"
+ cell $not $not$ls180.v:7891$2509
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_sync_rhs_array_muxed4
- connect \Y $not$ls180.v:7845$2499_Y
+ connect \Y $not$ls180.v:7891$2509_Y
end
- attribute \src "ls180.v:7856.8-7856.33"
- cell $not $not$ls180.v:7856$2500
+ attribute \src "ls180.v:7902.8-7902.33"
+ cell $not $not$ls180.v:7902$2510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_tccdcon_ready
- connect \Y $not$ls180.v:7856$2500_Y
+ connect \Y $not$ls180.v:7902$2510_Y
end
- attribute \src "ls180.v:7871.8-7871.33"
- cell $not $not$ls180.v:7871$2503
+ attribute \src "ls180.v:7917.8-7917.33"
+ cell $not $not$ls180.v:7917$2513
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_twtrcon_ready
- connect \Y $not$ls180.v:7871$2503_Y
+ connect \Y $not$ls180.v:7917$2513_Y
end
- attribute \src "ls180.v:7907.27-7907.40"
- cell $not $not$ls180.v:7907$2533
+ attribute \src "ls180.v:7953.36-7953.58"
+ cell $not $not$ls180.v:7953$2543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_tx_busy
- connect \Y $not$ls180.v:7907$2533_Y
+ connect \A \main_uart_phy_tx_busy
+ connect \Y $not$ls180.v:7953$2543_Y
end
- attribute \src "ls180.v:7907.46-7907.62"
- cell $not $not$ls180.v:7907$2535
+ attribute \src "ls180.v:7953.64-7953.89"
+ cell $not $not$ls180.v:7953$2545
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_sink_ready
- connect \Y $not$ls180.v:7907$2535_Y
+ connect \A \main_uart_phy_sink_ready
+ connect \Y $not$ls180.v:7953$2545_Y
end
- attribute \src "ls180.v:7936.7-7936.20"
- cell $not $not$ls180.v:7936$2542
+ attribute \src "ls180.v:7982.7-7982.29"
+ cell $not $not$ls180.v:7982$2552
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_rx_busy
- connect \Y $not$ls180.v:7936$2542_Y
+ connect \A \main_uart_phy_rx_busy
+ connect \Y $not$ls180.v:7982$2552_Y
end
- attribute \src "ls180.v:7937.9-7937.17"
- cell $not $not$ls180.v:7937$2543
+ attribute \src "ls180.v:7983.9-7983.26"
+ cell $not $not$ls180.v:7983$2553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_rx
- connect \Y $not$ls180.v:7937$2543_Y
+ connect \A \main_uart_phy_rx
+ connect \Y $not$ls180.v:7983$2553_Y
end
- attribute \src "ls180.v:7970.8-7970.29"
- cell $not $not$ls180.v:7970$2549
+ attribute \src "ls180.v:8016.8-8016.29"
+ cell $not $not$ls180.v:8016$2559
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_trigger
- connect \Y $not$ls180.v:7970$2549_Y
+ connect \Y $not$ls180.v:8016$2559_Y
end
- attribute \src "ls180.v:7977.8-7977.29"
- cell $not $not$ls180.v:7977$2551
+ attribute \src "ls180.v:8023.8-8023.29"
+ cell $not $not$ls180.v:8023$2561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_trigger
- connect \Y $not$ls180.v:7977$2551_Y
+ connect \Y $not$ls180.v:8023$2561_Y
end
- attribute \src "ls180.v:7987.80-7987.106"
- cell $not $not$ls180.v:7987$2554
+ attribute \src "ls180.v:8033.80-8033.106"
+ cell $not $not$ls180.v:8033$2564
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_replace
- connect \Y $not$ls180.v:7987$2554_Y
+ connect \Y $not$ls180.v:8033$2564_Y
end
- attribute \src "ls180.v:7993.80-7993.106"
- cell $not $not$ls180.v:7993$2559
+ attribute \src "ls180.v:8039.80-8039.106"
+ cell $not $not$ls180.v:8039$2569
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_replace
- connect \Y $not$ls180.v:7993$2559_Y
+ connect \Y $not$ls180.v:8039$2569_Y
end
- attribute \src "ls180.v:7994.8-7994.34"
- cell $not $not$ls180.v:7994$2561
+ attribute \src "ls180.v:8040.8-8040.34"
+ cell $not $not$ls180.v:8040$2571
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_do_read
- connect \Y $not$ls180.v:7994$2561_Y
+ connect \Y $not$ls180.v:8040$2571_Y
end
- attribute \src "ls180.v:8009.80-8009.106"
- cell $not $not$ls180.v:8009$2565
+ attribute \src "ls180.v:8055.80-8055.106"
+ cell $not $not$ls180.v:8055$2575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_replace
- connect \Y $not$ls180.v:8009$2565_Y
+ connect \Y $not$ls180.v:8055$2575_Y
end
- attribute \src "ls180.v:8015.80-8015.106"
- cell $not $not$ls180.v:8015$2570
+ attribute \src "ls180.v:8061.80-8061.106"
+ cell $not $not$ls180.v:8061$2580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_replace
- connect \Y $not$ls180.v:8015$2570_Y
+ connect \Y $not$ls180.v:8061$2580_Y
end
- attribute \src "ls180.v:8016.8-8016.34"
- cell $not $not$ls180.v:8016$2572
+ attribute \src "ls180.v:8062.8-8062.34"
+ cell $not $not$ls180.v:8062$2582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_do_read
- connect \Y $not$ls180.v:8016$2572_Y
+ connect \Y $not$ls180.v:8062$2582_Y
end
- attribute \src "ls180.v:8047.23-8047.42"
- cell $not $not$ls180.v:8047$2576
+ attribute \src "ls180.v:8093.23-8093.42"
+ cell $not $not$ls180.v:8093$2586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_spi_master_cs
- connect \Y $not$ls180.v:8047$2576_Y
+ connect \Y $not$ls180.v:8093$2586_Y
end
- attribute \src "ls180.v:8047.47-8047.73"
- cell $not $not$ls180.v:8047$2577
+ attribute \src "ls180.v:8093.47-8093.73"
+ cell $not $not$ls180.v:8093$2587
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_spi_master_cs_enable
- connect \Y $not$ls180.v:8047$2577_Y
+ connect \Y $not$ls180.v:8093$2587_Y
end
- attribute \src "ls180.v:8101.7-8101.31"
- cell $not $not$ls180.v:8101$2588
+ attribute \src "ls180.v:8147.7-8147.31"
+ cell $not $not$ls180.v:8147$2598
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_clocker_stop
- connect \Y $not$ls180.v:8101$2588_Y
+ connect \Y $not$ls180.v:8147$2598_Y
end
- attribute \src "ls180.v:8173.8-8173.46"
- cell $not $not$ls180.v:8173$2600
+ attribute \src "ls180.v:8219.8-8219.46"
+ cell $not $not$ls180.v:8219$2610
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_buf_source_valid
- connect \Y $not$ls180.v:8173$2600_Y
+ connect \Y $not$ls180.v:8219$2610_Y
end
- attribute \src "ls180.v:8254.8-8254.47"
- cell $not $not$ls180.v:8254$2612
+ attribute \src "ls180.v:8300.8-8300.47"
+ cell $not $not$ls180.v:8300$2622
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_buf_source_valid
- connect \Y $not$ls180.v:8254$2612_Y
+ connect \Y $not$ls180.v:8300$2622_Y
end
- attribute \src "ls180.v:8315.8-8315.48"
- cell $not $not$ls180.v:8315$2624
+ attribute \src "ls180.v:8361.8-8361.48"
+ cell $not $not$ls180.v:8361$2634
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_buf_source_valid
- connect \Y $not$ls180.v:8315$2624_Y
+ connect \Y $not$ls180.v:8361$2634_Y
end
- attribute \src "ls180.v:8485.88-8485.118"
- cell $not $not$ls180.v:8485$2638
+ attribute \src "ls180.v:8531.88-8531.118"
+ cell $not $not$ls180.v:8531$2648
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_replace
- connect \Y $not$ls180.v:8485$2638_Y
+ connect \Y $not$ls180.v:8531$2648_Y
end
- attribute \src "ls180.v:8491.88-8491.118"
- cell $not $not$ls180.v:8491$2643
+ attribute \src "ls180.v:8537.88-8537.118"
+ cell $not $not$ls180.v:8537$2653
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_replace
- connect \Y $not$ls180.v:8491$2643_Y
+ connect \Y $not$ls180.v:8537$2653_Y
end
- attribute \src "ls180.v:8492.8-8492.38"
- cell $not $not$ls180.v:8492$2645
+ attribute \src "ls180.v:8538.8-8538.38"
+ cell $not $not$ls180.v:8538$2655
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_do_read
- connect \Y $not$ls180.v:8492$2645_Y
+ connect \Y $not$ls180.v:8538$2655_Y
end
- attribute \src "ls180.v:8571.88-8571.118"
- cell $not $not$ls180.v:8571$2660
+ attribute \src "ls180.v:8617.88-8617.118"
+ cell $not $not$ls180.v:8617$2670
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_replace
- connect \Y $not$ls180.v:8571$2660_Y
+ connect \Y $not$ls180.v:8617$2670_Y
end
- attribute \src "ls180.v:8577.88-8577.118"
- cell $not $not$ls180.v:8577$2665
+ attribute \src "ls180.v:8623.88-8623.118"
+ cell $not $not$ls180.v:8623$2675
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_replace
- connect \Y $not$ls180.v:8577$2665_Y
+ connect \Y $not$ls180.v:8623$2675_Y
end
- attribute \src "ls180.v:8578.8-8578.38"
- cell $not $not$ls180.v:8578$2667
+ attribute \src "ls180.v:8624.8-8624.38"
+ cell $not $not$ls180.v:8624$2677
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_do_read
- connect \Y $not$ls180.v:8578$2667_Y
+ connect \Y $not$ls180.v:8624$2677_Y
end
- attribute \src "ls180.v:8595.22-8595.37"
- cell $not $not$ls180.v:8595$2671
+ attribute \src "ls180.v:8641.22-8641.37"
+ cell $not $not$ls180.v:8641$2681
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_cs
- connect \Y $not$ls180.v:8595$2671_Y
+ connect \Y $not$ls180.v:8641$2681_Y
end
- attribute \src "ls180.v:8595.42-8595.64"
- cell $not $not$ls180.v:8595$2672
+ attribute \src "ls180.v:8641.42-8641.64"
+ cell $not $not$ls180.v:8641$2682
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_cs_enable
- connect \Y $not$ls180.v:8595$2672_Y
+ connect \Y $not$ls180.v:8641$2682_Y
end
- attribute \src "ls180.v:8633.9-8633.28"
- cell $not $not$ls180.v:8633$2675
+ attribute \src "ls180.v:8679.9-8679.28"
+ cell $not $not$ls180.v:8679$2685
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_request [0]
- connect \Y $not$ls180.v:8633$2675_Y
+ connect \Y $not$ls180.v:8679$2685_Y
end
- attribute \src "ls180.v:8652.9-8652.28"
- cell $not $not$ls180.v:8652$2676
+ attribute \src "ls180.v:8698.9-8698.28"
+ cell $not $not$ls180.v:8698$2686
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_request [1]
- connect \Y $not$ls180.v:8652$2676_Y
+ connect \Y $not$ls180.v:8698$2686_Y
end
- attribute \src "ls180.v:8671.9-8671.28"
- cell $not $not$ls180.v:8671$2677
+ attribute \src "ls180.v:8717.9-8717.28"
+ cell $not $not$ls180.v:8717$2687
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_request [2]
- connect \Y $not$ls180.v:8671$2677_Y
+ connect \Y $not$ls180.v:8717$2687_Y
end
- attribute \src "ls180.v:8690.9-8690.28"
- cell $not $not$ls180.v:8690$2678
+ attribute \src "ls180.v:8736.9-8736.28"
+ cell $not $not$ls180.v:8736$2688
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_request [3]
- connect \Y $not$ls180.v:8690$2678_Y
+ connect \Y $not$ls180.v:8736$2688_Y
end
- attribute \src "ls180.v:8709.9-8709.28"
- cell $not $not$ls180.v:8709$2679
+ attribute \src "ls180.v:8755.9-8755.28"
+ cell $not $not$ls180.v:8755$2689
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_request [4]
- connect \Y $not$ls180.v:8709$2679_Y
+ connect \Y $not$ls180.v:8755$2689_Y
end
- attribute \src "ls180.v:8730.8-8730.21"
- cell $not $not$ls180.v:8730$2680
+ attribute \src "ls180.v:8776.8-8776.21"
+ cell $not $not$ls180.v:8776$2690
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_done
- connect \Y $not$ls180.v:8730$2680_Y
+ connect \Y $not$ls180.v:8776$2690_Y
end
- attribute \src "ls180.v:10195.8-10195.51"
- cell $or $or$ls180.v:10195$2752
+ attribute \src "ls180.v:10259.8-10259.51"
+ cell $or $or$ls180.v:10259$2762
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sys_rst_1
connect \B \main_libresocsim_libresoc_reset
- connect \Y $or$ls180.v:10195$2752_Y
+ connect \Y $or$ls180.v:10259$2762_Y
end
- attribute \src "ls180.v:2767.10-2767.96"
- cell $or $or$ls180.v:2767$21
+ attribute \src "ls180.v:2798.10-2798.96"
+ cell $or $or$ls180.v:2798$21
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface0_converted_interface_ack
connect \B \main_libresocsim_converter0_skip
- connect \Y $or$ls180.v:2767$21_Y
+ connect \Y $or$ls180.v:2798$21_Y
end
- attribute \src "ls180.v:2827.10-2827.96"
- cell $or $or$ls180.v:2827$32
+ attribute \src "ls180.v:2858.10-2858.96"
+ cell $or $or$ls180.v:2858$32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface1_converted_interface_ack
connect \B \main_libresocsim_converter1_skip
- connect \Y $or$ls180.v:2827$32_Y
+ connect \Y $or$ls180.v:2858$32_Y
end
- attribute \src "ls180.v:2887.10-2887.96"
- cell $or $or$ls180.v:2887$43
+ attribute \src "ls180.v:2918.10-2918.96"
+ cell $or $or$ls180.v:2918$43
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_interface2_converted_interface_ack
connect \B \main_libresocsim_converter2_skip
- connect \Y $or$ls180.v:2887$43_Y
+ connect \Y $or$ls180.v:2918$43_Y
end
- attribute \src "ls180.v:3079.39-3079.105"
- cell $or $or$ls180.v:3079$75
+ attribute \src "ls180.v:3110.39-3110.105"
+ cell $or $or$ls180.v:3110$75
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_start0
- connect \B $ne$ls180.v:3079$74_Y
- connect \Y $or$ls180.v:3079$75_Y
+ connect \B $ne$ls180.v:3110$74_Y
+ connect \Y $or$ls180.v:3110$75_Y
end
- attribute \src "ls180.v:3122.59-3122.140"
- cell $or $or$ls180.v:3122$79
+ attribute \src "ls180.v:3153.59-3153.140"
+ cell $or $or$ls180.v:3153$79
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_req_wdata_ready
connect \B \main_sdram_bankmachine0_req_rdata_valid
- connect \Y $or$ls180.v:3122$79_Y
+ connect \Y $or$ls180.v:3153$79_Y
end
- attribute \src "ls180.v:3123.44-3123.151"
- cell $or $or$ls180.v:3123$80
+ attribute \src "ls180.v:3154.44-3154.151"
+ cell $or $or$ls180.v:3154$80
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid
- connect \Y $or$ls180.v:3123$80_Y
+ connect \Y $or$ls180.v:3154$80_Y
end
- attribute \src "ls180.v:3131.45-3131.170"
- cell $or $or$ls180.v:3131$84
+ attribute \src "ls180.v:3162.45-3162.170"
+ cell $or $or$ls180.v:3162$84
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \B_WIDTH 13
parameter \Y_WIDTH 13
- connect \A $sshl$ls180.v:3131$83_Y
+ connect \A $sshl$ls180.v:3162$83_Y
connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] }
- connect \Y $or$ls180.v:3131$84_Y
+ connect \Y $or$ls180.v:3162$84_Y
end
- attribute \src "ls180.v:3168.127-3168.245"
- cell $or $or$ls180.v:3168$97
+ attribute \src "ls180.v:3199.127-3199.245"
+ cell $or $or$ls180.v:3199$97
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
- connect \Y $or$ls180.v:3168$97_Y
+ connect \Y $or$ls180.v:3199$97_Y
end
- attribute \src "ls180.v:3174.57-3174.157"
- cell $or $or$ls180.v:3174$103
+ attribute \src "ls180.v:3205.57-3205.157"
+ cell $or $or$ls180.v:3205$103
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3174$102_Y
+ connect \A $not$ls180.v:3205$102_Y
connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready
- connect \Y $or$ls180.v:3174$103_Y
+ connect \Y $or$ls180.v:3205$103_Y
end
- attribute \src "ls180.v:3279.59-3279.140"
- cell $or $or$ls180.v:3279$109
+ attribute \src "ls180.v:3310.59-3310.140"
+ cell $or $or$ls180.v:3310$109
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_req_wdata_ready
connect \B \main_sdram_bankmachine1_req_rdata_valid
- connect \Y $or$ls180.v:3279$109_Y
+ connect \Y $or$ls180.v:3310$109_Y
end
- attribute \src "ls180.v:3280.44-3280.151"
- cell $or $or$ls180.v:3280$110
+ attribute \src "ls180.v:3311.44-3311.151"
+ cell $or $or$ls180.v:3311$110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid
- connect \Y $or$ls180.v:3280$110_Y
+ connect \Y $or$ls180.v:3311$110_Y
end
- attribute \src "ls180.v:3288.45-3288.170"
- cell $or $or$ls180.v:3288$114
+ attribute \src "ls180.v:3319.45-3319.170"
+ cell $or $or$ls180.v:3319$114
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \B_WIDTH 13
parameter \Y_WIDTH 13
- connect \A $sshl$ls180.v:3288$113_Y
+ connect \A $sshl$ls180.v:3319$113_Y
connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] }
- connect \Y $or$ls180.v:3288$114_Y
+ connect \Y $or$ls180.v:3319$114_Y
end
- attribute \src "ls180.v:3325.127-3325.245"
- cell $or $or$ls180.v:3325$127
+ attribute \src "ls180.v:3356.127-3356.245"
+ cell $or $or$ls180.v:3356$127
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
- connect \Y $or$ls180.v:3325$127_Y
+ connect \Y $or$ls180.v:3356$127_Y
end
- attribute \src "ls180.v:3331.57-3331.157"
- cell $or $or$ls180.v:3331$133
+ attribute \src "ls180.v:3362.57-3362.157"
+ cell $or $or$ls180.v:3362$133
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3331$132_Y
+ connect \A $not$ls180.v:3362$132_Y
connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready
- connect \Y $or$ls180.v:3331$133_Y
+ connect \Y $or$ls180.v:3362$133_Y
end
- attribute \src "ls180.v:3436.59-3436.140"
- cell $or $or$ls180.v:3436$139
+ attribute \src "ls180.v:3467.59-3467.140"
+ cell $or $or$ls180.v:3467$139
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_req_wdata_ready
connect \B \main_sdram_bankmachine2_req_rdata_valid
- connect \Y $or$ls180.v:3436$139_Y
+ connect \Y $or$ls180.v:3467$139_Y
end
- attribute \src "ls180.v:3437.44-3437.151"
- cell $or $or$ls180.v:3437$140
+ attribute \src "ls180.v:3468.44-3468.151"
+ cell $or $or$ls180.v:3468$140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid
- connect \Y $or$ls180.v:3437$140_Y
+ connect \Y $or$ls180.v:3468$140_Y
end
- attribute \src "ls180.v:3445.45-3445.170"
- cell $or $or$ls180.v:3445$144
+ attribute \src "ls180.v:3476.45-3476.170"
+ cell $or $or$ls180.v:3476$144
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \B_WIDTH 13
parameter \Y_WIDTH 13
- connect \A $sshl$ls180.v:3445$143_Y
+ connect \A $sshl$ls180.v:3476$143_Y
connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] }
- connect \Y $or$ls180.v:3445$144_Y
+ connect \Y $or$ls180.v:3476$144_Y
end
- attribute \src "ls180.v:3482.127-3482.245"
- cell $or $or$ls180.v:3482$157
+ attribute \src "ls180.v:3513.127-3513.245"
+ cell $or $or$ls180.v:3513$157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
- connect \Y $or$ls180.v:3482$157_Y
+ connect \Y $or$ls180.v:3513$157_Y
end
- attribute \src "ls180.v:3488.57-3488.157"
- cell $or $or$ls180.v:3488$163
+ attribute \src "ls180.v:3519.57-3519.157"
+ cell $or $or$ls180.v:3519$163
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3488$162_Y
+ connect \A $not$ls180.v:3519$162_Y
connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready
- connect \Y $or$ls180.v:3488$163_Y
+ connect \Y $or$ls180.v:3519$163_Y
end
- attribute \src "ls180.v:3593.59-3593.140"
- cell $or $or$ls180.v:3593$169
+ attribute \src "ls180.v:3624.59-3624.140"
+ cell $or $or$ls180.v:3624$169
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_req_wdata_ready
connect \B \main_sdram_bankmachine3_req_rdata_valid
- connect \Y $or$ls180.v:3593$169_Y
+ connect \Y $or$ls180.v:3624$169_Y
end
- attribute \src "ls180.v:3594.44-3594.151"
- cell $or $or$ls180.v:3594$170
+ attribute \src "ls180.v:3625.44-3625.151"
+ cell $or $or$ls180.v:3625$170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid
connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid
- connect \Y $or$ls180.v:3594$170_Y
+ connect \Y $or$ls180.v:3625$170_Y
end
- attribute \src "ls180.v:3602.45-3602.170"
- cell $or $or$ls180.v:3602$174
+ attribute \src "ls180.v:3633.45-3633.170"
+ cell $or $or$ls180.v:3633$174
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \B_WIDTH 13
parameter \Y_WIDTH 13
- connect \A $sshl$ls180.v:3602$173_Y
+ connect \A $sshl$ls180.v:3633$173_Y
connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] }
- connect \Y $or$ls180.v:3602$174_Y
+ connect \Y $or$ls180.v:3633$174_Y
end
- attribute \src "ls180.v:3639.127-3639.245"
- cell $or $or$ls180.v:3639$187
+ attribute \src "ls180.v:3670.127-3670.245"
+ cell $or $or$ls180.v:3670$187
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
- connect \Y $or$ls180.v:3639$187_Y
+ connect \Y $or$ls180.v:3670$187_Y
end
- attribute \src "ls180.v:3645.57-3645.157"
- cell $or $or$ls180.v:3645$193
+ attribute \src "ls180.v:3676.57-3676.157"
+ cell $or $or$ls180.v:3676$193
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3645$192_Y
+ connect \A $not$ls180.v:3676$192_Y
connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready
- connect \Y $or$ls180.v:3645$193_Y
+ connect \Y $or$ls180.v:3676$193_Y
end
- attribute \src "ls180.v:3744.107-3744.193"
- cell $or $or$ls180.v:3744$213
+ attribute \src "ls180.v:3775.107-3775.193"
+ cell $or $or$ls180.v:3775$213
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_payload_is_write
connect \B \main_sdram_choose_req_cmd_payload_is_read
- connect \Y $or$ls180.v:3744$213_Y
+ connect \Y $or$ls180.v:3775$213_Y
end
- attribute \src "ls180.v:3747.39-3747.204"
- cell $or $or$ls180.v:3747$219
+ attribute \src "ls180.v:3778.39-3778.204"
+ cell $or $or$ls180.v:3778$219
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3747$217_Y
- connect \B $and$ls180.v:3747$218_Y
- connect \Y $or$ls180.v:3747$219_Y
+ connect \A $and$ls180.v:3778$217_Y
+ connect \B $and$ls180.v:3778$218_Y
+ connect \Y $or$ls180.v:3778$219_Y
end
- attribute \src "ls180.v:3747.38-3747.289"
- cell $or $or$ls180.v:3747$221
+ attribute \src "ls180.v:3778.38-3778.289"
+ cell $or $or$ls180.v:3778$221
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3747$219_Y
- connect \B $and$ls180.v:3747$220_Y
- connect \Y $or$ls180.v:3747$221_Y
+ connect \A $or$ls180.v:3778$219_Y
+ connect \B $and$ls180.v:3778$220_Y
+ connect \Y $or$ls180.v:3778$221_Y
end
- attribute \src "ls180.v:3747.37-3747.374"
- cell $or $or$ls180.v:3747$223
+ attribute \src "ls180.v:3778.37-3778.374"
+ cell $or $or$ls180.v:3778$223
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3747$221_Y
- connect \B $and$ls180.v:3747$222_Y
- connect \Y $or$ls180.v:3747$223_Y
+ connect \A $or$ls180.v:3778$221_Y
+ connect \B $and$ls180.v:3778$222_Y
+ connect \Y $or$ls180.v:3778$223_Y
end
- attribute \src "ls180.v:3748.40-3748.207"
- cell $or $or$ls180.v:3748$226
+ attribute \src "ls180.v:3779.40-3779.207"
+ cell $or $or$ls180.v:3779$226
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3748$224_Y
- connect \B $and$ls180.v:3748$225_Y
- connect \Y $or$ls180.v:3748$226_Y
+ connect \A $and$ls180.v:3779$224_Y
+ connect \B $and$ls180.v:3779$225_Y
+ connect \Y $or$ls180.v:3779$226_Y
end
- attribute \src "ls180.v:3748.39-3748.293"
- cell $or $or$ls180.v:3748$228
+ attribute \src "ls180.v:3779.39-3779.293"
+ cell $or $or$ls180.v:3779$228
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3748$226_Y
- connect \B $and$ls180.v:3748$227_Y
- connect \Y $or$ls180.v:3748$228_Y
+ connect \A $or$ls180.v:3779$226_Y
+ connect \B $and$ls180.v:3779$227_Y
+ connect \Y $or$ls180.v:3779$228_Y
end
- attribute \src "ls180.v:3748.38-3748.379"
- cell $or $or$ls180.v:3748$230
+ attribute \src "ls180.v:3779.38-3779.379"
+ cell $or $or$ls180.v:3779$230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3748$228_Y
- connect \B $and$ls180.v:3748$229_Y
- connect \Y $or$ls180.v:3748$230_Y
+ connect \A $or$ls180.v:3779$228_Y
+ connect \B $and$ls180.v:3779$229_Y
+ connect \Y $or$ls180.v:3779$230_Y
end
- attribute \src "ls180.v:3761.158-3761.332"
- cell $or $or$ls180.v:3761$244
+ attribute \src "ls180.v:3792.158-3792.332"
+ cell $or $or$ls180.v:3792$244
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3761$243_Y
+ connect \A $not$ls180.v:3792$243_Y
connect \B \main_sdram_choose_cmd_want_activates
- connect \Y $or$ls180.v:3761$244_Y
+ connect \Y $or$ls180.v:3792$244_Y
end
- attribute \src "ls180.v:3761.75-3761.506"
- cell $or $or$ls180.v:3761$249
+ attribute \src "ls180.v:3792.75-3792.506"
+ cell $or $or$ls180.v:3792$249
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3761$245_Y
- connect \B $and$ls180.v:3761$248_Y
- connect \Y $or$ls180.v:3761$249_Y
+ connect \A $and$ls180.v:3792$245_Y
+ connect \B $and$ls180.v:3792$248_Y
+ connect \Y $or$ls180.v:3792$249_Y
end
- attribute \src "ls180.v:3762.158-3762.332"
- cell $or $or$ls180.v:3762$257
+ attribute \src "ls180.v:3793.158-3793.332"
+ cell $or $or$ls180.v:3793$257
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3762$256_Y
+ connect \A $not$ls180.v:3793$256_Y
connect \B \main_sdram_choose_cmd_want_activates
- connect \Y $or$ls180.v:3762$257_Y
+ connect \Y $or$ls180.v:3793$257_Y
end
- attribute \src "ls180.v:3762.75-3762.506"
- cell $or $or$ls180.v:3762$262
+ attribute \src "ls180.v:3793.75-3793.506"
+ cell $or $or$ls180.v:3793$262
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3762$258_Y
- connect \B $and$ls180.v:3762$261_Y
- connect \Y $or$ls180.v:3762$262_Y
+ connect \A $and$ls180.v:3793$258_Y
+ connect \B $and$ls180.v:3793$261_Y
+ connect \Y $or$ls180.v:3793$262_Y
end
- attribute \src "ls180.v:3763.158-3763.332"
- cell $or $or$ls180.v:3763$270
+ attribute \src "ls180.v:3794.158-3794.332"
+ cell $or $or$ls180.v:3794$270
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3763$269_Y
+ connect \A $not$ls180.v:3794$269_Y
connect \B \main_sdram_choose_cmd_want_activates
- connect \Y $or$ls180.v:3763$270_Y
+ connect \Y $or$ls180.v:3794$270_Y
end
- attribute \src "ls180.v:3763.75-3763.506"
- cell $or $or$ls180.v:3763$275
+ attribute \src "ls180.v:3794.75-3794.506"
+ cell $or $or$ls180.v:3794$275
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3763$271_Y
- connect \B $and$ls180.v:3763$274_Y
- connect \Y $or$ls180.v:3763$275_Y
+ connect \A $and$ls180.v:3794$271_Y
+ connect \B $and$ls180.v:3794$274_Y
+ connect \Y $or$ls180.v:3794$275_Y
end
- attribute \src "ls180.v:3764.158-3764.332"
- cell $or $or$ls180.v:3764$283
+ attribute \src "ls180.v:3795.158-3795.332"
+ cell $or $or$ls180.v:3795$283
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3764$282_Y
+ connect \A $not$ls180.v:3795$282_Y
connect \B \main_sdram_choose_cmd_want_activates
- connect \Y $or$ls180.v:3764$283_Y
+ connect \Y $or$ls180.v:3795$283_Y
end
- attribute \src "ls180.v:3764.75-3764.506"
- cell $or $or$ls180.v:3764$288
+ attribute \src "ls180.v:3795.75-3795.506"
+ cell $or $or$ls180.v:3795$288
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3764$284_Y
- connect \B $and$ls180.v:3764$287_Y
- connect \Y $or$ls180.v:3764$288_Y
+ connect \A $and$ls180.v:3795$284_Y
+ connect \B $and$ls180.v:3795$287_Y
+ connect \Y $or$ls180.v:3795$288_Y
end
- attribute \src "ls180.v:3791.36-3791.104"
- cell $or $or$ls180.v:3791$294
+ attribute \src "ls180.v:3822.36-3822.104"
+ cell $or $or$ls180.v:3822$294
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_cmd_cmd_ready
- connect \B $not$ls180.v:3791$293_Y
- connect \Y $or$ls180.v:3791$294_Y
+ connect \B $not$ls180.v:3822$293_Y
+ connect \Y $or$ls180.v:3822$294_Y
end
- attribute \src "ls180.v:3794.158-3794.332"
- cell $or $or$ls180.v:3794$302
+ attribute \src "ls180.v:3825.158-3825.332"
+ cell $or $or$ls180.v:3825$302
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3794$301_Y
+ connect \A $not$ls180.v:3825$301_Y
connect \B \main_sdram_choose_req_want_activates
- connect \Y $or$ls180.v:3794$302_Y
+ connect \Y $or$ls180.v:3825$302_Y
end
- attribute \src "ls180.v:3794.75-3794.506"
- cell $or $or$ls180.v:3794$307
+ attribute \src "ls180.v:3825.75-3825.506"
+ cell $or $or$ls180.v:3825$307
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3794$303_Y
- connect \B $and$ls180.v:3794$306_Y
- connect \Y $or$ls180.v:3794$307_Y
+ connect \A $and$ls180.v:3825$303_Y
+ connect \B $and$ls180.v:3825$306_Y
+ connect \Y $or$ls180.v:3825$307_Y
end
- attribute \src "ls180.v:3795.158-3795.332"
- cell $or $or$ls180.v:3795$315
+ attribute \src "ls180.v:3826.158-3826.332"
+ cell $or $or$ls180.v:3826$315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3795$314_Y
+ connect \A $not$ls180.v:3826$314_Y
connect \B \main_sdram_choose_req_want_activates
- connect \Y $or$ls180.v:3795$315_Y
+ connect \Y $or$ls180.v:3826$315_Y
end
- attribute \src "ls180.v:3795.75-3795.506"
- cell $or $or$ls180.v:3795$320
+ attribute \src "ls180.v:3826.75-3826.506"
+ cell $or $or$ls180.v:3826$320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3795$316_Y
- connect \B $and$ls180.v:3795$319_Y
- connect \Y $or$ls180.v:3795$320_Y
+ connect \A $and$ls180.v:3826$316_Y
+ connect \B $and$ls180.v:3826$319_Y
+ connect \Y $or$ls180.v:3826$320_Y
end
- attribute \src "ls180.v:3796.158-3796.332"
- cell $or $or$ls180.v:3796$328
+ attribute \src "ls180.v:3827.158-3827.332"
+ cell $or $or$ls180.v:3827$328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3796$327_Y
+ connect \A $not$ls180.v:3827$327_Y
connect \B \main_sdram_choose_req_want_activates
- connect \Y $or$ls180.v:3796$328_Y
+ connect \Y $or$ls180.v:3827$328_Y
end
- attribute \src "ls180.v:3796.75-3796.506"
- cell $or $or$ls180.v:3796$333
+ attribute \src "ls180.v:3827.75-3827.506"
+ cell $or $or$ls180.v:3827$333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3796$329_Y
- connect \B $and$ls180.v:3796$332_Y
- connect \Y $or$ls180.v:3796$333_Y
+ connect \A $and$ls180.v:3827$329_Y
+ connect \B $and$ls180.v:3827$332_Y
+ connect \Y $or$ls180.v:3827$333_Y
end
- attribute \src "ls180.v:3797.158-3797.332"
- cell $or $or$ls180.v:3797$341
+ attribute \src "ls180.v:3828.158-3828.332"
+ cell $or $or$ls180.v:3828$341
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3797$340_Y
+ connect \A $not$ls180.v:3828$340_Y
connect \B \main_sdram_choose_req_want_activates
- connect \Y $or$ls180.v:3797$341_Y
+ connect \Y $or$ls180.v:3828$341_Y
end
- attribute \src "ls180.v:3797.75-3797.506"
- cell $or $or$ls180.v:3797$346
+ attribute \src "ls180.v:3828.75-3828.506"
+ cell $or $or$ls180.v:3828$346
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3797$342_Y
- connect \B $and$ls180.v:3797$345_Y
- connect \Y $or$ls180.v:3797$346_Y
+ connect \A $and$ls180.v:3828$342_Y
+ connect \B $and$ls180.v:3828$345_Y
+ connect \Y $or$ls180.v:3828$346_Y
end
- attribute \src "ls180.v:3860.36-3860.104"
- cell $or $or$ls180.v:3860$380
+ attribute \src "ls180.v:3891.36-3891.104"
+ cell $or $or$ls180.v:3891$380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdram_choose_req_cmd_ready
- connect \B $not$ls180.v:3860$379_Y
- connect \Y $or$ls180.v:3860$380_Y
+ connect \B $not$ls180.v:3891$379_Y
+ connect \Y $or$ls180.v:3891$380_Y
end
- attribute \src "ls180.v:3881.67-3881.221"
- cell $or $or$ls180.v:3881$387
+ attribute \src "ls180.v:3912.67-3912.221"
+ cell $or $or$ls180.v:3912$387
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3881$386_Y
+ connect \A $not$ls180.v:3912$386_Y
connect \B \main_sdram_ras_allowed
- connect \Y $or$ls180.v:3881$387_Y
+ connect \Y $or$ls180.v:3912$387_Y
end
- attribute \src "ls180.v:3889.10-3889.62"
- cell $or $or$ls180.v:3889$390
+ attribute \src "ls180.v:3920.10-3920.62"
+ cell $or $or$ls180.v:3920$390
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3889$389_Y
+ connect \A $not$ls180.v:3920$389_Y
connect \B \main_sdram_max_time1
- connect \Y $or$ls180.v:3889$390_Y
+ connect \Y $or$ls180.v:3920$390_Y
end
- attribute \src "ls180.v:3919.67-3919.221"
- cell $or $or$ls180.v:3919$396
+ attribute \src "ls180.v:3950.67-3950.221"
+ cell $or $or$ls180.v:3950$396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3919$395_Y
+ connect \A $not$ls180.v:3950$395_Y
connect \B \main_sdram_ras_allowed
- connect \Y $or$ls180.v:3919$396_Y
+ connect \Y $or$ls180.v:3950$396_Y
end
- attribute \src "ls180.v:3927.10-3927.61"
- cell $or $or$ls180.v:3927$399
+ attribute \src "ls180.v:3958.10-3958.61"
+ cell $or $or$ls180.v:3958$399
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:3927$398_Y
+ connect \A $not$ls180.v:3958$398_Y
connect \B \main_sdram_max_time0
- connect \Y $or$ls180.v:3927$399_Y
+ connect \Y $or$ls180.v:3958$399_Y
end
- attribute \src "ls180.v:3937.91-3937.180"
- cell $or $or$ls180.v:3937$403
+ attribute \src "ls180.v:3968.91-3968.180"
+ cell $or $or$ls180.v:3968$403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked0
- connect \B $and$ls180.v:3937$402_Y
- connect \Y $or$ls180.v:3937$403_Y
+ connect \B $and$ls180.v:3968$402_Y
+ connect \Y $or$ls180.v:3968$403_Y
end
- attribute \src "ls180.v:3937.90-3937.255"
- cell $or $or$ls180.v:3937$406
+ attribute \src "ls180.v:3968.90-3968.255"
+ cell $or $or$ls180.v:3968$406
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3937$403_Y
- connect \B $and$ls180.v:3937$405_Y
- connect \Y $or$ls180.v:3937$406_Y
+ connect \A $or$ls180.v:3968$403_Y
+ connect \B $and$ls180.v:3968$405_Y
+ connect \Y $or$ls180.v:3968$406_Y
end
- attribute \src "ls180.v:3937.89-3937.330"
- cell $or $or$ls180.v:3937$409
+ attribute \src "ls180.v:3968.89-3968.330"
+ cell $or $or$ls180.v:3968$409
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3937$406_Y
- connect \B $and$ls180.v:3937$408_Y
- connect \Y $or$ls180.v:3937$409_Y
+ connect \A $or$ls180.v:3968$406_Y
+ connect \B $and$ls180.v:3968$408_Y
+ connect \Y $or$ls180.v:3968$409_Y
end
- attribute \src "ls180.v:3942.91-3942.180"
- cell $or $or$ls180.v:3942$419
+ attribute \src "ls180.v:3973.91-3973.180"
+ cell $or $or$ls180.v:3973$419
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked1
- connect \B $and$ls180.v:3942$418_Y
- connect \Y $or$ls180.v:3942$419_Y
+ connect \B $and$ls180.v:3973$418_Y
+ connect \Y $or$ls180.v:3973$419_Y
end
- attribute \src "ls180.v:3942.90-3942.255"
- cell $or $or$ls180.v:3942$422
+ attribute \src "ls180.v:3973.90-3973.255"
+ cell $or $or$ls180.v:3973$422
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3942$419_Y
- connect \B $and$ls180.v:3942$421_Y
- connect \Y $or$ls180.v:3942$422_Y
+ connect \A $or$ls180.v:3973$419_Y
+ connect \B $and$ls180.v:3973$421_Y
+ connect \Y $or$ls180.v:3973$422_Y
end
- attribute \src "ls180.v:3942.89-3942.330"
- cell $or $or$ls180.v:3942$425
+ attribute \src "ls180.v:3973.89-3973.330"
+ cell $or $or$ls180.v:3973$425
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3942$422_Y
- connect \B $and$ls180.v:3942$424_Y
- connect \Y $or$ls180.v:3942$425_Y
+ connect \A $or$ls180.v:3973$422_Y
+ connect \B $and$ls180.v:3973$424_Y
+ connect \Y $or$ls180.v:3973$425_Y
end
- attribute \src "ls180.v:3947.91-3947.180"
- cell $or $or$ls180.v:3947$435
+ attribute \src "ls180.v:3978.91-3978.180"
+ cell $or $or$ls180.v:3978$435
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked2
- connect \B $and$ls180.v:3947$434_Y
- connect \Y $or$ls180.v:3947$435_Y
+ connect \B $and$ls180.v:3978$434_Y
+ connect \Y $or$ls180.v:3978$435_Y
end
- attribute \src "ls180.v:3947.90-3947.255"
- cell $or $or$ls180.v:3947$438
+ attribute \src "ls180.v:3978.90-3978.255"
+ cell $or $or$ls180.v:3978$438
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3947$435_Y
- connect \B $and$ls180.v:3947$437_Y
- connect \Y $or$ls180.v:3947$438_Y
+ connect \A $or$ls180.v:3978$435_Y
+ connect \B $and$ls180.v:3978$437_Y
+ connect \Y $or$ls180.v:3978$438_Y
end
- attribute \src "ls180.v:3947.89-3947.330"
- cell $or $or$ls180.v:3947$441
+ attribute \src "ls180.v:3978.89-3978.330"
+ cell $or $or$ls180.v:3978$441
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3947$438_Y
- connect \B $and$ls180.v:3947$440_Y
- connect \Y $or$ls180.v:3947$441_Y
+ connect \A $or$ls180.v:3978$438_Y
+ connect \B $and$ls180.v:3978$440_Y
+ connect \Y $or$ls180.v:3978$441_Y
end
- attribute \src "ls180.v:3952.91-3952.180"
- cell $or $or$ls180.v:3952$451
+ attribute \src "ls180.v:3983.91-3983.180"
+ cell $or $or$ls180.v:3983$451
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked3
- connect \B $and$ls180.v:3952$450_Y
- connect \Y $or$ls180.v:3952$451_Y
+ connect \B $and$ls180.v:3983$450_Y
+ connect \Y $or$ls180.v:3983$451_Y
end
- attribute \src "ls180.v:3952.90-3952.255"
- cell $or $or$ls180.v:3952$454
+ attribute \src "ls180.v:3983.90-3983.255"
+ cell $or $or$ls180.v:3983$454
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3952$451_Y
- connect \B $and$ls180.v:3952$453_Y
- connect \Y $or$ls180.v:3952$454_Y
+ connect \A $or$ls180.v:3983$451_Y
+ connect \B $and$ls180.v:3983$453_Y
+ connect \Y $or$ls180.v:3983$454_Y
end
- attribute \src "ls180.v:3952.89-3952.330"
- cell $or $or$ls180.v:3952$457
+ attribute \src "ls180.v:3983.89-3983.330"
+ cell $or $or$ls180.v:3983$457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3952$454_Y
- connect \B $and$ls180.v:3952$456_Y
- connect \Y $or$ls180.v:3952$457_Y
+ connect \A $or$ls180.v:3983$454_Y
+ connect \B $and$ls180.v:3983$456_Y
+ connect \Y $or$ls180.v:3983$457_Y
end
- attribute \src "ls180.v:3957.132-3957.221"
- cell $or $or$ls180.v:3957$468
+ attribute \src "ls180.v:3988.132-3988.221"
+ cell $or $or$ls180.v:3988$468
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked0
- connect \B $and$ls180.v:3957$467_Y
- connect \Y $or$ls180.v:3957$468_Y
+ connect \B $and$ls180.v:3988$467_Y
+ connect \Y $or$ls180.v:3988$468_Y
end
- attribute \src "ls180.v:3957.131-3957.296"
- cell $or $or$ls180.v:3957$471
+ attribute \src "ls180.v:3988.131-3988.296"
+ cell $or $or$ls180.v:3988$471
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$468_Y
- connect \B $and$ls180.v:3957$470_Y
- connect \Y $or$ls180.v:3957$471_Y
+ connect \A $or$ls180.v:3988$468_Y
+ connect \B $and$ls180.v:3988$470_Y
+ connect \Y $or$ls180.v:3988$471_Y
end
- attribute \src "ls180.v:3957.130-3957.371"
- cell $or $or$ls180.v:3957$474
+ attribute \src "ls180.v:3988.130-3988.371"
+ cell $or $or$ls180.v:3988$474
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$471_Y
- connect \B $and$ls180.v:3957$473_Y
- connect \Y $or$ls180.v:3957$474_Y
+ connect \A $or$ls180.v:3988$471_Y
+ connect \B $and$ls180.v:3988$473_Y
+ connect \Y $or$ls180.v:3988$474_Y
end
- attribute \src "ls180.v:3957.34-3957.411"
- cell $or $or$ls180.v:3957$479
+ attribute \src "ls180.v:3988.34-3988.411"
+ cell $or $or$ls180.v:3988$479
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A 1'0
- connect \B $and$ls180.v:3957$478_Y
- connect \Y $or$ls180.v:3957$479_Y
+ connect \B $and$ls180.v:3988$478_Y
+ connect \Y $or$ls180.v:3988$479_Y
end
- attribute \src "ls180.v:3957.506-3957.595"
- cell $or $or$ls180.v:3957$484
+ attribute \src "ls180.v:3988.506-3988.595"
+ cell $or $or$ls180.v:3988$484
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked1
- connect \B $and$ls180.v:3957$483_Y
- connect \Y $or$ls180.v:3957$484_Y
+ connect \B $and$ls180.v:3988$483_Y
+ connect \Y $or$ls180.v:3988$484_Y
end
- attribute \src "ls180.v:3957.505-3957.670"
- cell $or $or$ls180.v:3957$487
+ attribute \src "ls180.v:3988.505-3988.670"
+ cell $or $or$ls180.v:3988$487
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$484_Y
- connect \B $and$ls180.v:3957$486_Y
- connect \Y $or$ls180.v:3957$487_Y
+ connect \A $or$ls180.v:3988$484_Y
+ connect \B $and$ls180.v:3988$486_Y
+ connect \Y $or$ls180.v:3988$487_Y
end
- attribute \src "ls180.v:3957.504-3957.745"
- cell $or $or$ls180.v:3957$490
+ attribute \src "ls180.v:3988.504-3988.745"
+ cell $or $or$ls180.v:3988$490
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$487_Y
- connect \B $and$ls180.v:3957$489_Y
- connect \Y $or$ls180.v:3957$490_Y
+ connect \A $or$ls180.v:3988$487_Y
+ connect \B $and$ls180.v:3988$489_Y
+ connect \Y $or$ls180.v:3988$490_Y
end
- attribute \src "ls180.v:3957.33-3957.785"
- cell $or $or$ls180.v:3957$495
+ attribute \src "ls180.v:3988.33-3988.785"
+ cell $or $or$ls180.v:3988$495
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$479_Y
- connect \B $and$ls180.v:3957$494_Y
- connect \Y $or$ls180.v:3957$495_Y
+ connect \A $or$ls180.v:3988$479_Y
+ connect \B $and$ls180.v:3988$494_Y
+ connect \Y $or$ls180.v:3988$495_Y
end
- attribute \src "ls180.v:3957.880-3957.969"
- cell $or $or$ls180.v:3957$500
+ attribute \src "ls180.v:3988.880-3988.969"
+ cell $or $or$ls180.v:3988$500
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked2
- connect \B $and$ls180.v:3957$499_Y
- connect \Y $or$ls180.v:3957$500_Y
+ connect \B $and$ls180.v:3988$499_Y
+ connect \Y $or$ls180.v:3988$500_Y
end
- attribute \src "ls180.v:3957.879-3957.1044"
- cell $or $or$ls180.v:3957$503
+ attribute \src "ls180.v:3988.879-3988.1044"
+ cell $or $or$ls180.v:3988$503
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$500_Y
- connect \B $and$ls180.v:3957$502_Y
- connect \Y $or$ls180.v:3957$503_Y
+ connect \A $or$ls180.v:3988$500_Y
+ connect \B $and$ls180.v:3988$502_Y
+ connect \Y $or$ls180.v:3988$503_Y
end
- attribute \src "ls180.v:3957.878-3957.1119"
- cell $or $or$ls180.v:3957$506
+ attribute \src "ls180.v:3988.878-3988.1119"
+ cell $or $or$ls180.v:3988$506
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$503_Y
- connect \B $and$ls180.v:3957$505_Y
- connect \Y $or$ls180.v:3957$506_Y
+ connect \A $or$ls180.v:3988$503_Y
+ connect \B $and$ls180.v:3988$505_Y
+ connect \Y $or$ls180.v:3988$506_Y
end
- attribute \src "ls180.v:3957.32-3957.1159"
- cell $or $or$ls180.v:3957$511
+ attribute \src "ls180.v:3988.32-3988.1159"
+ cell $or $or$ls180.v:3988$511
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$495_Y
- connect \B $and$ls180.v:3957$510_Y
- connect \Y $or$ls180.v:3957$511_Y
+ connect \A $or$ls180.v:3988$495_Y
+ connect \B $and$ls180.v:3988$510_Y
+ connect \Y $or$ls180.v:3988$511_Y
end
- attribute \src "ls180.v:3957.1254-3957.1343"
- cell $or $or$ls180.v:3957$516
+ attribute \src "ls180.v:3988.1254-3988.1343"
+ cell $or $or$ls180.v:3988$516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked3
- connect \B $and$ls180.v:3957$515_Y
- connect \Y $or$ls180.v:3957$516_Y
+ connect \B $and$ls180.v:3988$515_Y
+ connect \Y $or$ls180.v:3988$516_Y
end
- attribute \src "ls180.v:3957.1253-3957.1418"
- cell $or $or$ls180.v:3957$519
+ attribute \src "ls180.v:3988.1253-3988.1418"
+ cell $or $or$ls180.v:3988$519
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$516_Y
- connect \B $and$ls180.v:3957$518_Y
- connect \Y $or$ls180.v:3957$519_Y
+ connect \A $or$ls180.v:3988$516_Y
+ connect \B $and$ls180.v:3988$518_Y
+ connect \Y $or$ls180.v:3988$519_Y
end
- attribute \src "ls180.v:3957.1252-3957.1493"
- cell $or $or$ls180.v:3957$522
+ attribute \src "ls180.v:3988.1252-3988.1493"
+ cell $or $or$ls180.v:3988$522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$519_Y
- connect \B $and$ls180.v:3957$521_Y
- connect \Y $or$ls180.v:3957$522_Y
+ connect \A $or$ls180.v:3988$519_Y
+ connect \B $and$ls180.v:3988$521_Y
+ connect \Y $or$ls180.v:3988$522_Y
end
- attribute \src "ls180.v:3957.31-3957.1533"
- cell $or $or$ls180.v:3957$527
+ attribute \src "ls180.v:3988.31-3988.1533"
+ cell $or $or$ls180.v:3988$527
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3957$511_Y
- connect \B $and$ls180.v:3957$526_Y
- connect \Y $or$ls180.v:3957$527_Y
+ connect \A $or$ls180.v:3988$511_Y
+ connect \B $and$ls180.v:3988$526_Y
+ connect \Y $or$ls180.v:3988$527_Y
end
- attribute \src "ls180.v:4020.10-4020.52"
- cell $or $or$ls180.v:4020$536
+ attribute \src "ls180.v:4051.10-4051.52"
+ cell $or $or$ls180.v:4051$536
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_ack
connect \B \main_converter_skip
- connect \Y $or$ls180.v:4020$536_Y
+ connect \Y $or$ls180.v:4051$536_Y
end
- attribute \src "ls180.v:4047.35-4047.74"
- cell $or $or$ls180.v:4047$546
+ attribute \src "ls180.v:4078.35-4078.74"
+ cell $or $or$ls180.v:4078$546
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_valid
connect \B \main_cmd_consumed
- connect \Y $or$ls180.v:4047$546_Y
+ connect \Y $or$ls180.v:4078$546_Y
end
- attribute \src "ls180.v:4048.34-4048.73"
- cell $or $or$ls180.v:4048$550
+ attribute \src "ls180.v:4079.34-4079.73"
+ cell $or $or$ls180.v:4079$550
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_port_cmd_valid
connect \B \main_cmd_consumed
- connect \Y $or$ls180.v:4048$550_Y
+ connect \Y $or$ls180.v:4079$550_Y
end
- attribute \src "ls180.v:4049.48-4049.130"
- cell $or $or$ls180.v:4049$556
+ attribute \src "ls180.v:4080.48-4080.130"
+ cell $or $or$ls180.v:4080$556
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4049$553_Y
- connect \B $and$ls180.v:4049$555_Y
- connect \Y $or$ls180.v:4049$556_Y
+ connect \A $and$ls180.v:4080$553_Y
+ connect \B $and$ls180.v:4080$555_Y
+ connect \Y $or$ls180.v:4080$556_Y
end
- attribute \src "ls180.v:4050.24-4050.87"
- cell $or $or$ls180.v:4050$559
+ attribute \src "ls180.v:4081.24-4081.87"
+ cell $or $or$ls180.v:4081$559
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4050$558_Y
+ connect \A $and$ls180.v:4081$558_Y
connect \B \main_cmd_consumed
- connect \Y $or$ls180.v:4050$559_Y
+ connect \Y $or$ls180.v:4081$559_Y
end
- attribute \src "ls180.v:4051.26-4051.95"
- cell $or $or$ls180.v:4051$561
+ attribute \src "ls180.v:4082.26-4082.95"
+ cell $or $or$ls180.v:4082$561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4051$560_Y
+ connect \A $and$ls180.v:4082$560_Y
connect \B \main_wdata_consumed
- connect \Y $or$ls180.v:4051$561_Y
+ connect \Y $or$ls180.v:4082$561_Y
end
- attribute \src "ls180.v:4081.42-4081.89"
- cell $or $or$ls180.v:4081$569
+ attribute \src "ls180.v:4112.42-4112.89"
+ cell $or $or$ls180.v:4112$569
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_uart_rx_clear
- connect \B $and$ls180.v:4081$568_Y
- connect \Y $or$ls180.v:4081$569_Y
+ connect \B $and$ls180.v:4112$568_Y
+ connect \Y $or$ls180.v:4112$569_Y
end
- attribute \src "ls180.v:4105.25-4105.174"
- cell $or $or$ls180.v:4105$579
+ attribute \src "ls180.v:4136.25-4136.174"
+ cell $or $or$ls180.v:4136$579
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4105$577_Y
- connect \B $and$ls180.v:4105$578_Y
- connect \Y $or$ls180.v:4105$579_Y
+ connect \A $and$ls180.v:4136$577_Y
+ connect \B $and$ls180.v:4136$578_Y
+ connect \Y $or$ls180.v:4136$579_Y
end
- attribute \src "ls180.v:4120.80-4120.132"
- cell $or $or$ls180.v:4120$581
+ attribute \src "ls180.v:4151.80-4151.132"
+ cell $or $or$ls180.v:4151$581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4120$580_Y
+ connect \A $not$ls180.v:4151$580_Y
connect \B \main_uart_tx_fifo_re
- connect \Y $or$ls180.v:4120$581_Y
+ connect \Y $or$ls180.v:4151$581_Y
end
- attribute \src "ls180.v:4131.72-4131.135"
- cell $or $or$ls180.v:4131$586
+ attribute \src "ls180.v:4162.72-4162.135"
+ cell $or $or$ls180.v:4162$586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_tx_fifo_syncfifo_writable
connect \B \main_uart_tx_fifo_replace
- connect \Y $or$ls180.v:4131$586_Y
+ connect \Y $or$ls180.v:4162$586_Y
end
- attribute \src "ls180.v:4150.80-4150.132"
- cell $or $or$ls180.v:4150$592
+ attribute \src "ls180.v:4181.80-4181.132"
+ cell $or $or$ls180.v:4181$592
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4150$591_Y
+ connect \A $not$ls180.v:4181$591_Y
connect \B \main_uart_rx_fifo_re
- connect \Y $or$ls180.v:4150$592_Y
+ connect \Y $or$ls180.v:4181$592_Y
end
- attribute \src "ls180.v:4161.72-4161.135"
- cell $or $or$ls180.v:4161$597
+ attribute \src "ls180.v:4192.72-4192.135"
+ cell $or $or$ls180.v:4192$597
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_uart_rx_fifo_syncfifo_writable
connect \B \main_uart_rx_fifo_replace
- connect \Y $or$ls180.v:4161$597_Y
+ connect \Y $or$ls180.v:4192$597_Y
end
- attribute \src "ls180.v:4232.36-4232.111"
- cell $or $or$ls180.v:4232$610
+ attribute \src "ls180.v:4267.36-4267.111"
+ cell $or $or$ls180.v:4267$610
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_init_pads_out_payload_clk
connect \B \main_sdphy_cmdw_pads_out_payload_clk
- connect \Y $or$ls180.v:4232$610_Y
+ connect \Y $or$ls180.v:4267$610_Y
end
- attribute \src "ls180.v:4232.35-4232.151"
- cell $or $or$ls180.v:4232$611
+ attribute \src "ls180.v:4267.35-4267.151"
+ cell $or $or$ls180.v:4267$611
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4232$610_Y
+ connect \A $or$ls180.v:4267$610_Y
connect \B \main_sdphy_cmdr_pads_out_payload_clk
- connect \Y $or$ls180.v:4232$611_Y
+ connect \Y $or$ls180.v:4267$611_Y
end
- attribute \src "ls180.v:4232.34-4232.192"
- cell $or $or$ls180.v:4232$612
+ attribute \src "ls180.v:4267.34-4267.192"
+ cell $or $or$ls180.v:4267$612
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4232$611_Y
+ connect \A $or$ls180.v:4267$611_Y
connect \B \main_sdphy_dataw_pads_out_payload_clk
- connect \Y $or$ls180.v:4232$612_Y
+ connect \Y $or$ls180.v:4267$612_Y
end
- attribute \src "ls180.v:4232.33-4232.233"
- cell $or $or$ls180.v:4232$613
+ attribute \src "ls180.v:4267.33-4267.233"
+ cell $or $or$ls180.v:4267$613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4232$612_Y
+ connect \A $or$ls180.v:4267$612_Y
connect \B \main_sdphy_datar_pads_out_payload_clk
- connect \Y $or$ls180.v:4232$613_Y
+ connect \Y $or$ls180.v:4267$613_Y
end
- attribute \src "ls180.v:4233.39-4233.120"
- cell $or $or$ls180.v:4233$614
+ attribute \src "ls180.v:4268.39-4268.120"
+ cell $or $or$ls180.v:4268$614
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_init_pads_out_payload_cmd_oe
connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe
- connect \Y $or$ls180.v:4233$614_Y
+ connect \Y $or$ls180.v:4268$614_Y
end
- attribute \src "ls180.v:4233.38-4233.163"
- cell $or $or$ls180.v:4233$615
+ attribute \src "ls180.v:4268.38-4268.163"
+ cell $or $or$ls180.v:4268$615
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4233$614_Y
+ connect \A $or$ls180.v:4268$614_Y
connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe
- connect \Y $or$ls180.v:4233$615_Y
+ connect \Y $or$ls180.v:4268$615_Y
end
- attribute \src "ls180.v:4233.37-4233.207"
- cell $or $or$ls180.v:4233$616
+ attribute \src "ls180.v:4268.37-4268.207"
+ cell $or $or$ls180.v:4268$616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4233$615_Y
+ connect \A $or$ls180.v:4268$615_Y
connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe
- connect \Y $or$ls180.v:4233$616_Y
+ connect \Y $or$ls180.v:4268$616_Y
end
- attribute \src "ls180.v:4233.36-4233.251"
- cell $or $or$ls180.v:4233$617
+ attribute \src "ls180.v:4268.36-4268.251"
+ cell $or $or$ls180.v:4268$617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4233$616_Y
+ connect \A $or$ls180.v:4268$616_Y
connect \B \main_sdphy_datar_pads_out_payload_cmd_oe
- connect \Y $or$ls180.v:4233$617_Y
+ connect \Y $or$ls180.v:4268$617_Y
end
- attribute \src "ls180.v:4234.38-4234.117"
- cell $or $or$ls180.v:4234$618
+ attribute \src "ls180.v:4269.38-4269.117"
+ cell $or $or$ls180.v:4269$618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_init_pads_out_payload_cmd_o
connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o
- connect \Y $or$ls180.v:4234$618_Y
+ connect \Y $or$ls180.v:4269$618_Y
end
- attribute \src "ls180.v:4234.37-4234.159"
- cell $or $or$ls180.v:4234$619
+ attribute \src "ls180.v:4269.37-4269.159"
+ cell $or $or$ls180.v:4269$619
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4234$618_Y
+ connect \A $or$ls180.v:4269$618_Y
connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o
- connect \Y $or$ls180.v:4234$619_Y
+ connect \Y $or$ls180.v:4269$619_Y
end
- attribute \src "ls180.v:4234.36-4234.202"
- cell $or $or$ls180.v:4234$620
+ attribute \src "ls180.v:4269.36-4269.202"
+ cell $or $or$ls180.v:4269$620
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4234$619_Y
+ connect \A $or$ls180.v:4269$619_Y
connect \B \main_sdphy_dataw_pads_out_payload_cmd_o
- connect \Y $or$ls180.v:4234$620_Y
+ connect \Y $or$ls180.v:4269$620_Y
end
- attribute \src "ls180.v:4234.35-4234.245"
- cell $or $or$ls180.v:4234$621
+ attribute \src "ls180.v:4269.35-4269.245"
+ cell $or $or$ls180.v:4269$621
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4234$620_Y
+ connect \A $or$ls180.v:4269$620_Y
connect \B \main_sdphy_datar_pads_out_payload_cmd_o
- connect \Y $or$ls180.v:4234$621_Y
+ connect \Y $or$ls180.v:4269$621_Y
end
- attribute \src "ls180.v:4235.40-4235.123"
- cell $or $or$ls180.v:4235$622
+ attribute \src "ls180.v:4270.40-4270.123"
+ cell $or $or$ls180.v:4270$622
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_init_pads_out_payload_data_oe
connect \B \main_sdphy_cmdw_pads_out_payload_data_oe
- connect \Y $or$ls180.v:4235$622_Y
+ connect \Y $or$ls180.v:4270$622_Y
end
- attribute \src "ls180.v:4235.39-4235.167"
- cell $or $or$ls180.v:4235$623
+ attribute \src "ls180.v:4270.39-4270.167"
+ cell $or $or$ls180.v:4270$623
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4235$622_Y
+ connect \A $or$ls180.v:4270$622_Y
connect \B \main_sdphy_cmdr_pads_out_payload_data_oe
- connect \Y $or$ls180.v:4235$623_Y
+ connect \Y $or$ls180.v:4270$623_Y
end
- attribute \src "ls180.v:4235.38-4235.212"
- cell $or $or$ls180.v:4235$624
+ attribute \src "ls180.v:4270.38-4270.212"
+ cell $or $or$ls180.v:4270$624
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4235$623_Y
+ connect \A $or$ls180.v:4270$623_Y
connect \B \main_sdphy_dataw_pads_out_payload_data_oe
- connect \Y $or$ls180.v:4235$624_Y
+ connect \Y $or$ls180.v:4270$624_Y
end
- attribute \src "ls180.v:4235.37-4235.257"
- cell $or $or$ls180.v:4235$625
+ attribute \src "ls180.v:4270.37-4270.257"
+ cell $or $or$ls180.v:4270$625
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4235$624_Y
+ connect \A $or$ls180.v:4270$624_Y
connect \B \main_sdphy_datar_pads_out_payload_data_oe
- connect \Y $or$ls180.v:4235$625_Y
+ connect \Y $or$ls180.v:4270$625_Y
end
- attribute \src "ls180.v:4236.39-4236.120"
- cell $or $or$ls180.v:4236$626
+ attribute \src "ls180.v:4271.39-4271.120"
+ cell $or $or$ls180.v:4271$626
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdphy_init_pads_out_payload_data_o
connect \B \main_sdphy_cmdw_pads_out_payload_data_o
- connect \Y $or$ls180.v:4236$626_Y
+ connect \Y $or$ls180.v:4271$626_Y
end
- attribute \src "ls180.v:4236.38-4236.163"
- cell $or $or$ls180.v:4236$627
+ attribute \src "ls180.v:4271.38-4271.163"
+ cell $or $or$ls180.v:4271$627
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $or$ls180.v:4236$626_Y
+ connect \A $or$ls180.v:4271$626_Y
connect \B \main_sdphy_cmdr_pads_out_payload_data_o
- connect \Y $or$ls180.v:4236$627_Y
+ connect \Y $or$ls180.v:4271$627_Y
end
- attribute \src "ls180.v:4236.37-4236.207"
- cell $or $or$ls180.v:4236$628
+ attribute \src "ls180.v:4271.37-4271.207"
+ cell $or $or$ls180.v:4271$628
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $or$ls180.v:4236$627_Y
+ connect \A $or$ls180.v:4271$627_Y
connect \B \main_sdphy_dataw_pads_out_payload_data_o
- connect \Y $or$ls180.v:4236$628_Y
+ connect \Y $or$ls180.v:4271$628_Y
end
- attribute \src "ls180.v:4236.36-4236.251"
- cell $or $or$ls180.v:4236$629
+ attribute \src "ls180.v:4271.36-4271.251"
+ cell $or $or$ls180.v:4271$629
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $or$ls180.v:4236$628_Y
+ connect \A $or$ls180.v:4271$628_Y
connect \B \main_sdphy_datar_pads_out_payload_data_o
- connect \Y $or$ls180.v:4236$629_Y
+ connect \Y $or$ls180.v:4271$629_Y
end
- attribute \src "ls180.v:4257.35-4257.80"
- cell $or $or$ls180.v:4257$630
+ attribute \src "ls180.v:4292.35-4292.80"
+ cell $or $or$ls180.v:4292$630
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_stop
connect \B \main_sdphy_datar_stop
- connect \Y $or$ls180.v:4257$630_Y
+ connect \Y $or$ls180.v:4292$630_Y
end
- attribute \src "ls180.v:4411.91-4411.144"
- cell $or $or$ls180.v:4411$644
+ attribute \src "ls180.v:4446.91-4446.144"
+ cell $or $or$ls180.v:4446$644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_start
connect \B \main_sdphy_cmdr_cmdr_run
- connect \Y $or$ls180.v:4411$644_Y
+ connect \Y $or$ls180.v:4446$644_Y
end
- attribute \src "ls180.v:4428.53-4428.143"
- cell $or $or$ls180.v:4428$647
+ attribute \src "ls180.v:4463.53-4463.143"
+ cell $or $or$ls180.v:4463$647
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4428$646_Y
+ connect \A $not$ls180.v:4463$646_Y
connect \B \main_sdphy_cmdr_cmdr_converter_source_ready
- connect \Y $or$ls180.v:4428$647_Y
+ connect \Y $or$ls180.v:4463$647_Y
end
- attribute \src "ls180.v:4431.47-4431.127"
- cell $or $or$ls180.v:4431$650
+ attribute \src "ls180.v:4466.47-4466.127"
+ cell $or $or$ls180.v:4466$650
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4431$649_Y
+ connect \A $not$ls180.v:4466$649_Y
connect \B \main_sdphy_cmdr_cmdr_buf_source_ready
- connect \Y $or$ls180.v:4431$650_Y
+ connect \Y $or$ls180.v:4466$650_Y
end
- attribute \src "ls180.v:4555.54-4555.146"
- cell $or $or$ls180.v:4555$668
+ attribute \src "ls180.v:4590.54-4590.146"
+ cell $or $or$ls180.v:4590$668
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4555$667_Y
+ connect \A $not$ls180.v:4590$667_Y
connect \B \main_sdphy_dataw_crcr_converter_source_ready
- connect \Y $or$ls180.v:4555$668_Y
+ connect \Y $or$ls180.v:4590$668_Y
end
- attribute \src "ls180.v:4558.48-4558.130"
- cell $or $or$ls180.v:4558$671
+ attribute \src "ls180.v:4593.48-4593.130"
+ cell $or $or$ls180.v:4593$671
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4558$670_Y
+ connect \A $not$ls180.v:4593$670_Y
connect \B \main_sdphy_dataw_crcr_buf_source_ready
- connect \Y $or$ls180.v:4558$671_Y
+ connect \Y $or$ls180.v:4593$671_Y
end
- attribute \src "ls180.v:4689.55-4689.149"
- cell $or $or$ls180.v:4689$683
+ attribute \src "ls180.v:4724.55-4724.149"
+ cell $or $or$ls180.v:4724$683
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4689$682_Y
+ connect \A $not$ls180.v:4724$682_Y
connect \B \main_sdphy_datar_datar_converter_source_ready
- connect \Y $or$ls180.v:4689$683_Y
+ connect \Y $or$ls180.v:4724$683_Y
end
- attribute \src "ls180.v:4692.49-4692.133"
- cell $or $or$ls180.v:4692$686
+ attribute \src "ls180.v:4727.49-4727.133"
+ cell $or $or$ls180.v:4727$686
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4692$685_Y
+ connect \A $not$ls180.v:4727$685_Y
connect \B \main_sdphy_datar_datar_buf_source_ready
- connect \Y $or$ls180.v:4692$686_Y
+ connect \Y $or$ls180.v:4727$686_Y
end
- attribute \src "ls180.v:5321.80-5321.151"
- cell $or $or$ls180.v:5321$981
+ attribute \src "ls180.v:5356.80-5356.151"
+ cell $or $or$ls180.v:5356$981
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_fifo_syncfifo_writable
connect \B \main_sdblock2mem_fifo_replace
- connect \Y $or$ls180.v:5321$981_Y
+ connect \Y $or$ls180.v:5356$981_Y
end
- attribute \src "ls180.v:5332.49-5332.131"
- cell $or $or$ls180.v:5332$987
+ attribute \src "ls180.v:5367.49-5367.131"
+ cell $or $or$ls180.v:5367$987
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:5332$986_Y
+ connect \A $not$ls180.v:5367$986_Y
connect \B \main_sdblock2mem_converter_source_ready
- connect \Y $or$ls180.v:5332$987_Y
+ connect \Y $or$ls180.v:5367$987_Y
end
- attribute \src "ls180.v:5529.80-5529.151"
- cell $or $or$ls180.v:5529$1012
+ attribute \src "ls180.v:5564.80-5564.151"
+ cell $or $or$ls180.v:5564$1012
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdmem2block_fifo_syncfifo_writable
connect \B \main_sdmem2block_fifo_replace
- connect \Y $or$ls180.v:5529$1012_Y
+ connect \Y $or$ls180.v:5564$1012_Y
end
- attribute \src "ls180.v:5703.33-5703.102"
- cell $or $or$ls180.v:5703$1060
+ attribute \src "ls180.v:5738.33-5738.102"
+ cell $or $or$ls180.v:5738$1060
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_err
connect \B \main_libresocsim_libresoc_xics_icp_err
- connect \Y $or$ls180.v:5703$1060_Y
+ connect \Y $or$ls180.v:5738$1060_Y
end
- attribute \src "ls180.v:5703.32-5703.144"
- cell $or $or$ls180.v:5703$1061
+ attribute \src "ls180.v:5738.32-5738.144"
+ cell $or $or$ls180.v:5738$1061
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:5703$1060_Y
+ connect \A $or$ls180.v:5738$1060_Y
connect \B \main_libresocsim_libresoc_xics_ics_err
- connect \Y $or$ls180.v:5703$1061_Y
+ connect \Y $or$ls180.v:5738$1061_Y
end
- attribute \src "ls180.v:5703.31-5703.165"
- cell $or $or$ls180.v:5703$1062
+ attribute \src "ls180.v:5738.31-5738.165"
+ cell $or $or$ls180.v:5738$1062
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:5703$1061_Y
+ connect \A $or$ls180.v:5738$1061_Y
connect \B \main_wb_sdram_err
- connect \Y $or$ls180.v:5703$1062_Y
+ connect \Y $or$ls180.v:5738$1062_Y
end
- attribute \src "ls180.v:5703.30-5703.201"
- cell $or $or$ls180.v:5703$1063
+ attribute \src "ls180.v:5738.30-5738.201"
+ cell $or $or$ls180.v:5738$1063
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:5703$1062_Y
+ connect \A $or$ls180.v:5738$1062_Y
connect \B \builder_libresocsim_wishbone_err
- connect \Y $or$ls180.v:5703$1063_Y
+ connect \Y $or$ls180.v:5738$1063_Y
end
- attribute \src "ls180.v:5709.28-5709.97"
- cell $or $or$ls180.v:5709$1068
+ attribute \src "ls180.v:5744.28-5744.97"
+ cell $or $or$ls180.v:5744$1068
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_libresocsim_ram_bus_ack
connect \B \main_libresocsim_libresoc_xics_icp_ack
- connect \Y $or$ls180.v:5709$1068_Y
+ connect \Y $or$ls180.v:5744$1068_Y
end
- attribute \src "ls180.v:5709.27-5709.139"
- cell $or $or$ls180.v:5709$1069
+ attribute \src "ls180.v:5744.27-5744.139"
+ cell $or $or$ls180.v:5744$1069
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:5709$1068_Y
+ connect \A $or$ls180.v:5744$1068_Y
connect \B \main_libresocsim_libresoc_xics_ics_ack
- connect \Y $or$ls180.v:5709$1069_Y
+ connect \Y $or$ls180.v:5744$1069_Y
end
- attribute \src "ls180.v:5709.26-5709.160"
- cell $or $or$ls180.v:5709$1070
+ attribute \src "ls180.v:5744.26-5744.160"
+ cell $or $or$ls180.v:5744$1070
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:5709$1069_Y
+ connect \A $or$ls180.v:5744$1069_Y
connect \B \main_wb_sdram_ack
- connect \Y $or$ls180.v:5709$1070_Y
+ connect \Y $or$ls180.v:5744$1070_Y
end
- attribute \src "ls180.v:5709.25-5709.196"
- cell $or $or$ls180.v:5709$1071
+ attribute \src "ls180.v:5744.25-5744.196"
+ cell $or $or$ls180.v:5744$1071
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:5709$1070_Y
+ connect \A $or$ls180.v:5744$1070_Y
connect \B \builder_libresocsim_wishbone_ack
- connect \Y $or$ls180.v:5709$1071_Y
+ connect \Y $or$ls180.v:5744$1071_Y
end
- attribute \src "ls180.v:5710.30-5710.169"
- cell $or $or$ls180.v:5710$1074
+ attribute \src "ls180.v:5745.30-5745.169"
+ cell $or $or$ls180.v:5745$1074
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 32
- connect \A $and$ls180.v:5710$1072_Y
- connect \B $and$ls180.v:5710$1073_Y
- connect \Y $or$ls180.v:5710$1074_Y
+ connect \A $and$ls180.v:5745$1072_Y
+ connect \B $and$ls180.v:5745$1073_Y
+ connect \Y $or$ls180.v:5745$1074_Y
end
- attribute \src "ls180.v:5710.29-5710.246"
- cell $or $or$ls180.v:5710$1076
+ attribute \src "ls180.v:5745.29-5745.246"
+ cell $or $or$ls180.v:5745$1076
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 32
- connect \A $or$ls180.v:5710$1074_Y
- connect \B $and$ls180.v:5710$1075_Y
- connect \Y $or$ls180.v:5710$1076_Y
+ connect \A $or$ls180.v:5745$1074_Y
+ connect \B $and$ls180.v:5745$1075_Y
+ connect \Y $or$ls180.v:5745$1076_Y
end
- attribute \src "ls180.v:5710.28-5710.302"
- cell $or $or$ls180.v:5710$1078
+ attribute \src "ls180.v:5745.28-5745.302"
+ cell $or $or$ls180.v:5745$1078
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 32
- connect \A $or$ls180.v:5710$1076_Y
- connect \B $and$ls180.v:5710$1077_Y
- connect \Y $or$ls180.v:5710$1078_Y
+ connect \A $or$ls180.v:5745$1076_Y
+ connect \B $and$ls180.v:5745$1077_Y
+ connect \Y $or$ls180.v:5745$1078_Y
end
- attribute \src "ls180.v:5710.27-5710.373"
- cell $or $or$ls180.v:5710$1080
+ attribute \src "ls180.v:5745.27-5745.373"
+ cell $or $or$ls180.v:5745$1080
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 32
- connect \A $or$ls180.v:5710$1078_Y
- connect \B $and$ls180.v:5710$1079_Y
- connect \Y $or$ls180.v:5710$1080_Y
+ connect \A $or$ls180.v:5745$1078_Y
+ connect \B $and$ls180.v:5745$1079_Y
+ connect \Y $or$ls180.v:5745$1080_Y
end
- attribute \src "ls180.v:6447.54-6447.123"
- cell $or $or$ls180.v:6447$2211
+ attribute \src "ls180.v:6499.55-6499.124"
+ cell $or $or$ls180.v:6499$2226
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \builder_interface0_bank_bus_dat_r
connect \B \builder_interface1_bank_bus_dat_r
- connect \Y $or$ls180.v:6447$2211_Y
+ connect \Y $or$ls180.v:6499$2226_Y
end
- attribute \src "ls180.v:6447.53-6447.160"
- cell $or $or$ls180.v:6447$2212
+ attribute \src "ls180.v:6499.54-6499.161"
+ cell $or $or$ls180.v:6499$2227
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6447$2211_Y
+ connect \A $or$ls180.v:6499$2226_Y
connect \B \builder_interface2_bank_bus_dat_r
- connect \Y $or$ls180.v:6447$2212_Y
+ connect \Y $or$ls180.v:6499$2227_Y
end
- attribute \src "ls180.v:6447.52-6447.197"
- cell $or $or$ls180.v:6447$2213
+ attribute \src "ls180.v:6499.53-6499.198"
+ cell $or $or$ls180.v:6499$2228
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6447$2212_Y
+ connect \A $or$ls180.v:6499$2227_Y
connect \B \builder_interface3_bank_bus_dat_r
- connect \Y $or$ls180.v:6447$2213_Y
+ connect \Y $or$ls180.v:6499$2228_Y
end
- attribute \src "ls180.v:6447.51-6447.234"
- cell $or $or$ls180.v:6447$2214
+ attribute \src "ls180.v:6499.52-6499.235"
+ cell $or $or$ls180.v:6499$2229
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6447$2213_Y
+ connect \A $or$ls180.v:6499$2228_Y
connect \B \builder_interface4_bank_bus_dat_r
- connect \Y $or$ls180.v:6447$2214_Y
+ connect \Y $or$ls180.v:6499$2229_Y
end
- attribute \src "ls180.v:6447.50-6447.271"
- cell $or $or$ls180.v:6447$2215
+ attribute \src "ls180.v:6499.51-6499.272"
+ cell $or $or$ls180.v:6499$2230
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6447$2214_Y
+ connect \A $or$ls180.v:6499$2229_Y
connect \B \builder_interface5_bank_bus_dat_r
- connect \Y $or$ls180.v:6447$2215_Y
+ connect \Y $or$ls180.v:6499$2230_Y
end
- attribute \src "ls180.v:6447.49-6447.308"
- cell $or $or$ls180.v:6447$2216
+ attribute \src "ls180.v:6499.50-6499.309"
+ cell $or $or$ls180.v:6499$2231
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6447$2215_Y
+ connect \A $or$ls180.v:6499$2230_Y
connect \B \builder_interface6_bank_bus_dat_r
- connect \Y $or$ls180.v:6447$2216_Y
+ connect \Y $or$ls180.v:6499$2231_Y
end
- attribute \src "ls180.v:6447.48-6447.345"
- cell $or $or$ls180.v:6447$2217
+ attribute \src "ls180.v:6499.49-6499.346"
+ cell $or $or$ls180.v:6499$2232
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6447$2216_Y
+ connect \A $or$ls180.v:6499$2231_Y
connect \B \builder_interface7_bank_bus_dat_r
- connect \Y $or$ls180.v:6447$2217_Y
+ connect \Y $or$ls180.v:6499$2232_Y
end
- attribute \src "ls180.v:6447.47-6447.382"
- cell $or $or$ls180.v:6447$2218
+ attribute \src "ls180.v:6499.48-6499.383"
+ cell $or $or$ls180.v:6499$2233
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6447$2217_Y
+ connect \A $or$ls180.v:6499$2232_Y
connect \B \builder_interface8_bank_bus_dat_r
- connect \Y $or$ls180.v:6447$2218_Y
+ connect \Y $or$ls180.v:6499$2233_Y
end
- attribute \src "ls180.v:6447.46-6447.419"
- cell $or $or$ls180.v:6447$2219
+ attribute \src "ls180.v:6499.47-6499.420"
+ cell $or $or$ls180.v:6499$2234
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6447$2218_Y
+ connect \A $or$ls180.v:6499$2233_Y
connect \B \builder_interface9_bank_bus_dat_r
- connect \Y $or$ls180.v:6447$2219_Y
+ connect \Y $or$ls180.v:6499$2234_Y
end
- attribute \src "ls180.v:6447.45-6447.457"
- cell $or $or$ls180.v:6447$2220
+ attribute \src "ls180.v:6499.46-6499.458"
+ cell $or $or$ls180.v:6499$2235
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6447$2219_Y
+ connect \A $or$ls180.v:6499$2234_Y
connect \B \builder_interface10_bank_bus_dat_r
- connect \Y $or$ls180.v:6447$2220_Y
+ connect \Y $or$ls180.v:6499$2235_Y
end
- attribute \src "ls180.v:6447.44-6447.495"
- cell $or $or$ls180.v:6447$2221
+ attribute \src "ls180.v:6499.45-6499.496"
+ cell $or $or$ls180.v:6499$2236
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6447$2220_Y
+ connect \A $or$ls180.v:6499$2235_Y
connect \B \builder_interface11_bank_bus_dat_r
- connect \Y $or$ls180.v:6447$2221_Y
+ connect \Y $or$ls180.v:6499$2236_Y
end
- attribute \src "ls180.v:6447.43-6447.533"
- cell $or $or$ls180.v:6447$2222
+ attribute \src "ls180.v:6499.44-6499.534"
+ cell $or $or$ls180.v:6499$2237
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6447$2221_Y
+ connect \A $or$ls180.v:6499$2236_Y
connect \B \builder_interface12_bank_bus_dat_r
- connect \Y $or$ls180.v:6447$2222_Y
+ connect \Y $or$ls180.v:6499$2237_Y
end
- attribute \src "ls180.v:6447.42-6447.571"
- cell $or $or$ls180.v:6447$2223
+ attribute \src "ls180.v:6499.43-6499.572"
+ cell $or $or$ls180.v:6499$2238
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:6447$2222_Y
+ connect \A $or$ls180.v:6499$2237_Y
connect \B \builder_interface13_bank_bus_dat_r
- connect \Y $or$ls180.v:6447$2223_Y
+ connect \Y $or$ls180.v:6499$2238_Y
end
- attribute \src "ls180.v:6774.90-6774.179"
- cell $or $or$ls180.v:6774$2248
+ attribute \src "ls180.v:6499.42-6499.610"
+ cell $or $or$ls180.v:6499$2239
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 8
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 8
+ parameter \Y_WIDTH 8
+ connect \A $or$ls180.v:6499$2238_Y
+ connect \B \builder_interface14_bank_bus_dat_r
+ connect \Y $or$ls180.v:6499$2239_Y
+ end
+ attribute \src "ls180.v:6826.90-6826.179"
+ cell $or $or$ls180.v:6826$2264
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked0
- connect \B $and$ls180.v:6774$2247_Y
- connect \Y $or$ls180.v:6774$2248_Y
+ connect \B $and$ls180.v:6826$2263_Y
+ connect \Y $or$ls180.v:6826$2264_Y
end
- attribute \src "ls180.v:6774.89-6774.254"
- cell $or $or$ls180.v:6774$2251
+ attribute \src "ls180.v:6826.89-6826.254"
+ cell $or $or$ls180.v:6826$2267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6774$2248_Y
- connect \B $and$ls180.v:6774$2250_Y
- connect \Y $or$ls180.v:6774$2251_Y
+ connect \A $or$ls180.v:6826$2264_Y
+ connect \B $and$ls180.v:6826$2266_Y
+ connect \Y $or$ls180.v:6826$2267_Y
end
- attribute \src "ls180.v:6774.88-6774.329"
- cell $or $or$ls180.v:6774$2254
+ attribute \src "ls180.v:6826.88-6826.329"
+ cell $or $or$ls180.v:6826$2270
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6774$2251_Y
- connect \B $and$ls180.v:6774$2253_Y
- connect \Y $or$ls180.v:6774$2254_Y
+ connect \A $or$ls180.v:6826$2267_Y
+ connect \B $and$ls180.v:6826$2269_Y
+ connect \Y $or$ls180.v:6826$2270_Y
end
- attribute \src "ls180.v:6798.90-6798.179"
- cell $or $or$ls180.v:6798$2264
+ attribute \src "ls180.v:6850.90-6850.179"
+ cell $or $or$ls180.v:6850$2280
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked1
- connect \B $and$ls180.v:6798$2263_Y
- connect \Y $or$ls180.v:6798$2264_Y
+ connect \B $and$ls180.v:6850$2279_Y
+ connect \Y $or$ls180.v:6850$2280_Y
end
- attribute \src "ls180.v:6798.89-6798.254"
- cell $or $or$ls180.v:6798$2267
+ attribute \src "ls180.v:6850.89-6850.254"
+ cell $or $or$ls180.v:6850$2283
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6798$2264_Y
- connect \B $and$ls180.v:6798$2266_Y
- connect \Y $or$ls180.v:6798$2267_Y
+ connect \A $or$ls180.v:6850$2280_Y
+ connect \B $and$ls180.v:6850$2282_Y
+ connect \Y $or$ls180.v:6850$2283_Y
end
- attribute \src "ls180.v:6798.88-6798.329"
- cell $or $or$ls180.v:6798$2270
+ attribute \src "ls180.v:6850.88-6850.329"
+ cell $or $or$ls180.v:6850$2286
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6798$2267_Y
- connect \B $and$ls180.v:6798$2269_Y
- connect \Y $or$ls180.v:6798$2270_Y
+ connect \A $or$ls180.v:6850$2283_Y
+ connect \B $and$ls180.v:6850$2285_Y
+ connect \Y $or$ls180.v:6850$2286_Y
end
- attribute \src "ls180.v:6822.90-6822.179"
- cell $or $or$ls180.v:6822$2280
+ attribute \src "ls180.v:6874.90-6874.179"
+ cell $or $or$ls180.v:6874$2296
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked2
- connect \B $and$ls180.v:6822$2279_Y
- connect \Y $or$ls180.v:6822$2280_Y
+ connect \B $and$ls180.v:6874$2295_Y
+ connect \Y $or$ls180.v:6874$2296_Y
end
- attribute \src "ls180.v:6822.89-6822.254"
- cell $or $or$ls180.v:6822$2283
+ attribute \src "ls180.v:6874.89-6874.254"
+ cell $or $or$ls180.v:6874$2299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6822$2280_Y
- connect \B $and$ls180.v:6822$2282_Y
- connect \Y $or$ls180.v:6822$2283_Y
+ connect \A $or$ls180.v:6874$2296_Y
+ connect \B $and$ls180.v:6874$2298_Y
+ connect \Y $or$ls180.v:6874$2299_Y
end
- attribute \src "ls180.v:6822.88-6822.329"
- cell $or $or$ls180.v:6822$2286
+ attribute \src "ls180.v:6874.88-6874.329"
+ cell $or $or$ls180.v:6874$2302
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6822$2283_Y
- connect \B $and$ls180.v:6822$2285_Y
- connect \Y $or$ls180.v:6822$2286_Y
+ connect \A $or$ls180.v:6874$2299_Y
+ connect \B $and$ls180.v:6874$2301_Y
+ connect \Y $or$ls180.v:6874$2302_Y
end
- attribute \src "ls180.v:6846.90-6846.179"
- cell $or $or$ls180.v:6846$2296
+ attribute \src "ls180.v:6898.90-6898.179"
+ cell $or $or$ls180.v:6898$2312
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \builder_locked3
- connect \B $and$ls180.v:6846$2295_Y
- connect \Y $or$ls180.v:6846$2296_Y
+ connect \B $and$ls180.v:6898$2311_Y
+ connect \Y $or$ls180.v:6898$2312_Y
end
- attribute \src "ls180.v:6846.89-6846.254"
- cell $or $or$ls180.v:6846$2299
+ attribute \src "ls180.v:6898.89-6898.254"
+ cell $or $or$ls180.v:6898$2315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6846$2296_Y
- connect \B $and$ls180.v:6846$2298_Y
- connect \Y $or$ls180.v:6846$2299_Y
+ connect \A $or$ls180.v:6898$2312_Y
+ connect \B $and$ls180.v:6898$2314_Y
+ connect \Y $or$ls180.v:6898$2315_Y
end
- attribute \src "ls180.v:6846.88-6846.329"
- cell $or $or$ls180.v:6846$2302
+ attribute \src "ls180.v:6898.88-6898.329"
+ cell $or $or$ls180.v:6898$2318
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:6846$2299_Y
- connect \B $and$ls180.v:6846$2301_Y
- connect \Y $or$ls180.v:6846$2302_Y
+ connect \A $or$ls180.v:6898$2315_Y
+ connect \B $and$ls180.v:6898$2317_Y
+ connect \Y $or$ls180.v:6898$2318_Y
end
- attribute \src "ls180.v:7360.20-7360.71"
- cell $or $or$ls180.v:7360$2359
+ attribute \src "ls180.v:7412.20-7412.71"
+ cell $or $or$ls180.v:7412$2375
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [0]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7360$2359_Y
+ connect \Y $or$ls180.v:7412$2375_Y
end
- attribute \src "ls180.v:7361.20-7361.71"
- cell $or $or$ls180.v:7361$2360
+ attribute \src "ls180.v:7413.20-7413.71"
+ cell $or $or$ls180.v:7413$2376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [1]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7361$2360_Y
+ connect \Y $or$ls180.v:7413$2376_Y
end
- attribute \src "ls180.v:7362.20-7362.71"
- cell $or $or$ls180.v:7362$2361
+ attribute \src "ls180.v:7414.20-7414.71"
+ cell $or $or$ls180.v:7414$2377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [2]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7362$2361_Y
+ connect \Y $or$ls180.v:7414$2377_Y
end
- attribute \src "ls180.v:7363.20-7363.71"
- cell $or $or$ls180.v:7363$2362
+ attribute \src "ls180.v:7415.20-7415.71"
+ cell $or $or$ls180.v:7415$2378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [3]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7363$2362_Y
+ connect \Y $or$ls180.v:7415$2378_Y
end
- attribute \src "ls180.v:7364.20-7364.71"
- cell $or $or$ls180.v:7364$2363
+ attribute \src "ls180.v:7416.20-7416.71"
+ cell $or $or$ls180.v:7416$2379
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [4]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7364$2363_Y
+ connect \Y $or$ls180.v:7416$2379_Y
end
- attribute \src "ls180.v:7365.20-7365.71"
- cell $or $or$ls180.v:7365$2364
+ attribute \src "ls180.v:7417.20-7417.71"
+ cell $or $or$ls180.v:7417$2380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [5]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7365$2364_Y
+ connect \Y $or$ls180.v:7417$2380_Y
end
- attribute \src "ls180.v:7366.20-7366.71"
- cell $or $or$ls180.v:7366$2365
+ attribute \src "ls180.v:7418.20-7418.71"
+ cell $or $or$ls180.v:7418$2381
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [6]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7366$2365_Y
+ connect \Y $or$ls180.v:7418$2381_Y
end
- attribute \src "ls180.v:7367.20-7367.71"
- cell $or $or$ls180.v:7367$2366
+ attribute \src "ls180.v:7419.20-7419.71"
+ cell $or $or$ls180.v:7419$2382
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [7]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7367$2366_Y
+ connect \Y $or$ls180.v:7419$2382_Y
end
- attribute \src "ls180.v:7368.20-7368.71"
- cell $or $or$ls180.v:7368$2367
+ attribute \src "ls180.v:7420.20-7420.71"
+ cell $or $or$ls180.v:7420$2383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [8]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7368$2367_Y
+ connect \Y $or$ls180.v:7420$2383_Y
end
- attribute \src "ls180.v:7369.20-7369.71"
- cell $or $or$ls180.v:7369$2368
+ attribute \src "ls180.v:7421.20-7421.71"
+ cell $or $or$ls180.v:7421$2384
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [9]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7369$2368_Y
+ connect \Y $or$ls180.v:7421$2384_Y
end
- attribute \src "ls180.v:7370.21-7370.73"
- cell $or $or$ls180.v:7370$2369
+ attribute \src "ls180.v:7422.21-7422.73"
+ cell $or $or$ls180.v:7422$2385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [10]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7370$2369_Y
+ connect \Y $or$ls180.v:7422$2385_Y
end
- attribute \src "ls180.v:7371.21-7371.73"
- cell $or $or$ls180.v:7371$2370
+ attribute \src "ls180.v:7423.21-7423.73"
+ cell $or $or$ls180.v:7423$2386
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [11]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7371$2370_Y
+ connect \Y $or$ls180.v:7423$2386_Y
end
- attribute \src "ls180.v:7372.21-7372.73"
- cell $or $or$ls180.v:7372$2371
+ attribute \src "ls180.v:7424.21-7424.73"
+ cell $or $or$ls180.v:7424$2387
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [12]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7372$2371_Y
+ connect \Y $or$ls180.v:7424$2387_Y
end
- attribute \src "ls180.v:7373.21-7373.73"
- cell $or $or$ls180.v:7373$2372
+ attribute \src "ls180.v:7425.21-7425.73"
+ cell $or $or$ls180.v:7425$2388
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [13]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7373$2372_Y
+ connect \Y $or$ls180.v:7425$2388_Y
end
- attribute \src "ls180.v:7374.21-7374.73"
- cell $or $or$ls180.v:7374$2373
+ attribute \src "ls180.v:7426.21-7426.73"
+ cell $or $or$ls180.v:7426$2389
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [14]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7374$2373_Y
+ connect \Y $or$ls180.v:7426$2389_Y
end
- attribute \src "ls180.v:7375.21-7375.73"
- cell $or $or$ls180.v:7375$2374
+ attribute \src "ls180.v:7427.21-7427.73"
+ cell $or $or$ls180.v:7427$2390
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [15]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7375$2374_Y
+ connect \Y $or$ls180.v:7427$2390_Y
end
- attribute \src "ls180.v:7376.21-7376.73"
- cell $or $or$ls180.v:7376$2375
+ attribute \src "ls180.v:7428.21-7428.73"
+ cell $or $or$ls180.v:7428$2391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [16]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7376$2375_Y
+ connect \Y $or$ls180.v:7428$2391_Y
end
- attribute \src "ls180.v:7377.21-7377.73"
- cell $or $or$ls180.v:7377$2376
+ attribute \src "ls180.v:7429.21-7429.73"
+ cell $or $or$ls180.v:7429$2392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [17]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7377$2376_Y
+ connect \Y $or$ls180.v:7429$2392_Y
end
- attribute \src "ls180.v:7378.21-7378.73"
- cell $or $or$ls180.v:7378$2377
+ attribute \src "ls180.v:7430.21-7430.73"
+ cell $or $or$ls180.v:7430$2393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [18]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7378$2377_Y
+ connect \Y $or$ls180.v:7430$2393_Y
end
- attribute \src "ls180.v:7379.21-7379.73"
- cell $or $or$ls180.v:7379$2378
+ attribute \src "ls180.v:7431.21-7431.73"
+ cell $or $or$ls180.v:7431$2394
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [19]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7379$2378_Y
+ connect \Y $or$ls180.v:7431$2394_Y
end
- attribute \src "ls180.v:7380.21-7380.73"
- cell $or $or$ls180.v:7380$2379
+ attribute \src "ls180.v:7432.21-7432.73"
+ cell $or $or$ls180.v:7432$2395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [20]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7380$2379_Y
+ connect \Y $or$ls180.v:7432$2395_Y
end
- attribute \src "ls180.v:7381.21-7381.73"
- cell $or $or$ls180.v:7381$2380
+ attribute \src "ls180.v:7433.21-7433.73"
+ cell $or $or$ls180.v:7433$2396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [21]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7381$2380_Y
+ connect \Y $or$ls180.v:7433$2396_Y
end
- attribute \src "ls180.v:7382.21-7382.73"
- cell $or $or$ls180.v:7382$2381
+ attribute \src "ls180.v:7434.21-7434.73"
+ cell $or $or$ls180.v:7434$2397
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [22]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7382$2381_Y
+ connect \Y $or$ls180.v:7434$2397_Y
end
- attribute \src "ls180.v:7383.21-7383.73"
- cell $or $or$ls180.v:7383$2382
+ attribute \src "ls180.v:7435.21-7435.73"
+ cell $or $or$ls180.v:7435$2398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [23]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7383$2382_Y
+ connect \Y $or$ls180.v:7435$2398_Y
end
- attribute \src "ls180.v:7384.21-7384.73"
- cell $or $or$ls180.v:7384$2383
+ attribute \src "ls180.v:7436.21-7436.73"
+ cell $or $or$ls180.v:7436$2399
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [24]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7384$2383_Y
+ connect \Y $or$ls180.v:7436$2399_Y
end
- attribute \src "ls180.v:7385.21-7385.73"
- cell $or $or$ls180.v:7385$2384
+ attribute \src "ls180.v:7437.21-7437.73"
+ cell $or $or$ls180.v:7437$2400
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [25]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7385$2384_Y
+ connect \Y $or$ls180.v:7437$2400_Y
end
- attribute \src "ls180.v:7386.21-7386.73"
- cell $or $or$ls180.v:7386$2385
+ attribute \src "ls180.v:7438.21-7438.73"
+ cell $or $or$ls180.v:7438$2401
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [26]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7386$2385_Y
+ connect \Y $or$ls180.v:7438$2401_Y
end
- attribute \src "ls180.v:7387.21-7387.73"
- cell $or $or$ls180.v:7387$2386
+ attribute \src "ls180.v:7439.21-7439.73"
+ cell $or $or$ls180.v:7439$2402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [27]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7387$2386_Y
+ connect \Y $or$ls180.v:7439$2402_Y
end
- attribute \src "ls180.v:7388.21-7388.73"
- cell $or $or$ls180.v:7388$2387
+ attribute \src "ls180.v:7440.21-7440.73"
+ cell $or $or$ls180.v:7440$2403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [28]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7388$2387_Y
+ connect \Y $or$ls180.v:7440$2403_Y
end
- attribute \src "ls180.v:7389.21-7389.73"
- cell $or $or$ls180.v:7389$2388
+ attribute \src "ls180.v:7441.21-7441.73"
+ cell $or $or$ls180.v:7441$2404
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [29]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7389$2388_Y
+ connect \Y $or$ls180.v:7441$2404_Y
end
- attribute \src "ls180.v:7390.21-7390.73"
- cell $or $or$ls180.v:7390$2389
+ attribute \src "ls180.v:7442.21-7442.73"
+ cell $or $or$ls180.v:7442$2405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [30]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7390$2389_Y
+ connect \Y $or$ls180.v:7442$2405_Y
end
- attribute \src "ls180.v:7391.21-7391.73"
- cell $or $or$ls180.v:7391$2390
+ attribute \src "ls180.v:7443.21-7443.73"
+ cell $or $or$ls180.v:7443$2406
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [31]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7391$2390_Y
+ connect \Y $or$ls180.v:7443$2406_Y
end
- attribute \src "ls180.v:7392.21-7392.73"
- cell $or $or$ls180.v:7392$2391
+ attribute \src "ls180.v:7444.21-7444.73"
+ cell $or $or$ls180.v:7444$2407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [32]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7392$2391_Y
+ connect \Y $or$ls180.v:7444$2407_Y
end
- attribute \src "ls180.v:7393.21-7393.73"
- cell $or $or$ls180.v:7393$2392
+ attribute \src "ls180.v:7445.21-7445.73"
+ cell $or $or$ls180.v:7445$2408
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [33]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7393$2392_Y
+ connect \Y $or$ls180.v:7445$2408_Y
end
- attribute \src "ls180.v:7394.21-7394.73"
- cell $or $or$ls180.v:7394$2393
+ attribute \src "ls180.v:7446.21-7446.73"
+ cell $or $or$ls180.v:7446$2409
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [34]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7394$2393_Y
+ connect \Y $or$ls180.v:7446$2409_Y
end
- attribute \src "ls180.v:7395.21-7395.73"
- cell $or $or$ls180.v:7395$2394
+ attribute \src "ls180.v:7447.21-7447.73"
+ cell $or $or$ls180.v:7447$2410
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_nc [35]
connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7395$2394_Y
- end
- attribute \src "ls180.v:7396.21-7396.73"
- cell $or $or$ls180.v:7396$2395
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \main_nc [36]
- connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7396$2395_Y
+ connect \Y $or$ls180.v:7447$2410_Y
end
- attribute \src "ls180.v:7397.21-7397.73"
- cell $or $or$ls180.v:7397$2396
+ attribute \src "ls180.v:7448.7-7448.93"
+ cell $or $or$ls180.v:7448$2411
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_nc [37]
- connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7397$2396_Y
- end
- attribute \src "ls180.v:7398.21-7398.73"
- cell $or $or$ls180.v:7398$2397
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \main_nc [38]
- connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7398$2397_Y
+ connect \A \main_libresocsim_interface0_converted_interface_ack
+ connect \B \main_libresocsim_converter0_skip
+ connect \Y $or$ls180.v:7448$2411_Y
end
- attribute \src "ls180.v:7399.21-7399.73"
- cell $or $or$ls180.v:7399$2398
+ attribute \src "ls180.v:7459.7-7459.93"
+ cell $or $or$ls180.v:7459$2412
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_nc [39]
- connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7399$2398_Y
+ connect \A \main_libresocsim_interface1_converted_interface_ack
+ connect \B \main_libresocsim_converter1_skip
+ connect \Y $or$ls180.v:7459$2412_Y
end
- attribute \src "ls180.v:7400.21-7400.73"
- cell $or $or$ls180.v:7400$2399
+ attribute \src "ls180.v:7470.7-7470.93"
+ cell $or $or$ls180.v:7470$2413
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_nc [40]
- connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7400$2399_Y
+ connect \A \main_libresocsim_interface2_converted_interface_ack
+ connect \B \main_libresocsim_converter2_skip
+ connect \Y $or$ls180.v:7470$2413_Y
end
- attribute \src "ls180.v:7401.21-7401.73"
- cell $or $or$ls180.v:7401$2400
+ attribute \src "ls180.v:7599.7-7599.107"
+ cell $or $or$ls180.v:7599$2449
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_nc [41]
- connect \B \main_libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:7401$2400_Y
+ connect \A $not$ls180.v:7599$2448_Y
+ connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready
+ connect \Y $or$ls180.v:7599$2449_Y
end
- attribute \src "ls180.v:7402.7-7402.93"
- cell $or $or$ls180.v:7402$2401
+ attribute \src "ls180.v:7645.7-7645.107"
+ cell $or $or$ls180.v:7645$2465
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_libresocsim_interface0_converted_interface_ack
- connect \B \main_libresocsim_converter0_skip
- connect \Y $or$ls180.v:7402$2401_Y
+ connect \A $not$ls180.v:7645$2464_Y
+ connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready
+ connect \Y $or$ls180.v:7645$2465_Y
end
- attribute \src "ls180.v:7413.7-7413.93"
- cell $or $or$ls180.v:7413$2402
+ attribute \src "ls180.v:7691.7-7691.107"
+ cell $or $or$ls180.v:7691$2481
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_libresocsim_interface1_converted_interface_ack
- connect \B \main_libresocsim_converter1_skip
- connect \Y $or$ls180.v:7413$2402_Y
+ connect \A $not$ls180.v:7691$2480_Y
+ connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready
+ connect \Y $or$ls180.v:7691$2481_Y
end
- attribute \src "ls180.v:7424.7-7424.93"
- cell $or $or$ls180.v:7424$2403
+ attribute \src "ls180.v:7737.7-7737.107"
+ cell $or $or$ls180.v:7737$2497
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \main_libresocsim_interface2_converted_interface_ack
- connect \B \main_libresocsim_converter2_skip
- connect \Y $or$ls180.v:7424$2403_Y
+ connect \A $not$ls180.v:7737$2496_Y
+ connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready
+ connect \Y $or$ls180.v:7737$2497_Y
end
- attribute \src "ls180.v:7553.7-7553.107"
- cell $or $or$ls180.v:7553$2439
+ attribute \src "ls180.v:7925.40-7925.125"
+ cell $or $or$ls180.v:7925$2518
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7553$2438_Y
- connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready
- connect \Y $or$ls180.v:7553$2439_Y
+ connect \A 1'0
+ connect \B $and$ls180.v:7925$2517_Y
+ connect \Y $or$ls180.v:7925$2518_Y
end
- attribute \src "ls180.v:7599.7-7599.107"
- cell $or $or$ls180.v:7599$2455
+ attribute \src "ls180.v:7925.39-7925.207"
+ cell $or $or$ls180.v:7925$2521
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7599$2454_Y
- connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready
- connect \Y $or$ls180.v:7599$2455_Y
+ connect \A $or$ls180.v:7925$2518_Y
+ connect \B $and$ls180.v:7925$2520_Y
+ connect \Y $or$ls180.v:7925$2521_Y
end
- attribute \src "ls180.v:7645.7-7645.107"
- cell $or $or$ls180.v:7645$2471
+ attribute \src "ls180.v:7925.38-7925.289"
+ cell $or $or$ls180.v:7925$2524
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7645$2470_Y
- connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready
- connect \Y $or$ls180.v:7645$2471_Y
+ connect \A $or$ls180.v:7925$2521_Y
+ connect \B $and$ls180.v:7925$2523_Y
+ connect \Y $or$ls180.v:7925$2524_Y
end
- attribute \src "ls180.v:7691.7-7691.107"
- cell $or $or$ls180.v:7691$2487
+ attribute \src "ls180.v:7925.37-7925.371"
+ cell $or $or$ls180.v:7925$2527
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:7691$2486_Y
- connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready
- connect \Y $or$ls180.v:7691$2487_Y
+ connect \A $or$ls180.v:7925$2524_Y
+ connect \B $and$ls180.v:7925$2526_Y
+ connect \Y $or$ls180.v:7925$2527_Y
end
- attribute \src "ls180.v:7879.40-7879.125"
- cell $or $or$ls180.v:7879$2508
+ attribute \src "ls180.v:7926.41-7926.126"
+ cell $or $or$ls180.v:7926$2530
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A 1'0
- connect \B $and$ls180.v:7879$2507_Y
- connect \Y $or$ls180.v:7879$2508_Y
+ connect \B $and$ls180.v:7926$2529_Y
+ connect \Y $or$ls180.v:7926$2530_Y
end
- attribute \src "ls180.v:7879.39-7879.207"
- cell $or $or$ls180.v:7879$2511
+ attribute \src "ls180.v:7926.40-7926.208"
+ cell $or $or$ls180.v:7926$2533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:7879$2508_Y
- connect \B $and$ls180.v:7879$2510_Y
- connect \Y $or$ls180.v:7879$2511_Y
+ connect \A $or$ls180.v:7926$2530_Y
+ connect \B $and$ls180.v:7926$2532_Y
+ connect \Y $or$ls180.v:7926$2533_Y
end
- attribute \src "ls180.v:7879.38-7879.289"
- cell $or $or$ls180.v:7879$2514
+ attribute \src "ls180.v:7926.39-7926.290"
+ cell $or $or$ls180.v:7926$2536
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:7879$2511_Y
- connect \B $and$ls180.v:7879$2513_Y
- connect \Y $or$ls180.v:7879$2514_Y
+ connect \A $or$ls180.v:7926$2533_Y
+ connect \B $and$ls180.v:7926$2535_Y
+ connect \Y $or$ls180.v:7926$2536_Y
end
- attribute \src "ls180.v:7879.37-7879.371"
- cell $or $or$ls180.v:7879$2517
+ attribute \src "ls180.v:7926.38-7926.372"
+ cell $or $or$ls180.v:7926$2539
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:7879$2514_Y
- connect \B $and$ls180.v:7879$2516_Y
- connect \Y $or$ls180.v:7879$2517_Y
+ connect \A $or$ls180.v:7926$2536_Y
+ connect \B $and$ls180.v:7926$2538_Y
+ connect \Y $or$ls180.v:7926$2539_Y
end
- attribute \src "ls180.v:7880.41-7880.126"
- cell $or $or$ls180.v:7880$2520
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A 1'0
- connect \B $and$ls180.v:7880$2519_Y
- connect \Y $or$ls180.v:7880$2520_Y
- end
- attribute \src "ls180.v:7880.40-7880.208"
- cell $or $or$ls180.v:7880$2523
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $or$ls180.v:7880$2520_Y
- connect \B $and$ls180.v:7880$2522_Y
- connect \Y $or$ls180.v:7880$2523_Y
- end
- attribute \src "ls180.v:7880.39-7880.290"
- cell $or $or$ls180.v:7880$2526
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $or$ls180.v:7880$2523_Y
- connect \B $and$ls180.v:7880$2525_Y
- connect \Y $or$ls180.v:7880$2526_Y
- end
- attribute \src "ls180.v:7880.38-7880.372"
- cell $or $or$ls180.v:7880$2529
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $or$ls180.v:7880$2526_Y
- connect \B $and$ls180.v:7880$2528_Y
- connect \Y $or$ls180.v:7880$2529_Y
- end
- attribute \src "ls180.v:7884.7-7884.49"
- cell $or $or$ls180.v:7884$2530
+ attribute \src "ls180.v:7930.7-7930.49"
+ cell $or $or$ls180.v:7930$2540
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_litedram_wb_ack
connect \B \main_converter_skip
- connect \Y $or$ls180.v:7884$2530_Y
+ connect \Y $or$ls180.v:7930$2540_Y
end
- attribute \src "ls180.v:8047.22-8047.74"
- cell $or $or$ls180.v:8047$2578
+ attribute \src "ls180.v:8093.22-8093.74"
+ cell $or $or$ls180.v:8093$2588
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:8047$2576_Y
- connect \B $not$ls180.v:8047$2577_Y
- connect \Y $or$ls180.v:8047$2578_Y
+ connect \A $not$ls180.v:8093$2586_Y
+ connect \B $not$ls180.v:8093$2587_Y
+ connect \Y $or$ls180.v:8093$2588_Y
end
- attribute \src "ls180.v:8115.32-8115.85"
- cell $or $or$ls180.v:8115$2590
+ attribute \src "ls180.v:8161.32-8161.85"
+ cell $or $or$ls180.v:8161$2600
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_start
connect \B \main_sdphy_cmdr_cmdr_run
- connect \Y $or$ls180.v:8115$2590_Y
+ connect \Y $or$ls180.v:8161$2600_Y
end
- attribute \src "ls180.v:8121.8-8121.97"
- cell $or $or$ls180.v:8121$2592
+ attribute \src "ls180.v:8167.8-8167.97"
+ cell $or $or$ls180.v:8167$2602
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:8121$2591_Y
+ connect \A $eq$ls180.v:8167$2601_Y
connect \B \main_sdphy_cmdr_cmdr_converter_sink_last
- connect \Y $or$ls180.v:8121$2592_Y
+ connect \Y $or$ls180.v:8167$2602_Y
end
- attribute \src "ls180.v:8138.52-8138.139"
- cell $or $or$ls180.v:8138$2597
+ attribute \src "ls180.v:8184.52-8184.139"
+ cell $or $or$ls180.v:8184$2607
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_sink_first
connect \B \main_sdphy_cmdr_cmdr_converter_source_first
- connect \Y $or$ls180.v:8138$2597_Y
+ connect \Y $or$ls180.v:8184$2607_Y
end
- attribute \src "ls180.v:8139.51-8139.136"
- cell $or $or$ls180.v:8139$2598
+ attribute \src "ls180.v:8185.51-8185.136"
+ cell $or $or$ls180.v:8185$2608
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_cmdr_cmdr_converter_sink_last
connect \B \main_sdphy_cmdr_cmdr_converter_source_last
- connect \Y $or$ls180.v:8139$2598_Y
+ connect \Y $or$ls180.v:8185$2608_Y
end
- attribute \src "ls180.v:8173.7-8173.87"
- cell $or $or$ls180.v:8173$2601
+ attribute \src "ls180.v:8219.7-8219.87"
+ cell $or $or$ls180.v:8219$2611
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:8173$2600_Y
+ connect \A $not$ls180.v:8219$2610_Y
connect \B \main_sdphy_cmdr_cmdr_buf_source_ready
- connect \Y $or$ls180.v:8173$2601_Y
+ connect \Y $or$ls180.v:8219$2611_Y
end
- attribute \src "ls180.v:8196.33-8196.88"
- cell $or $or$ls180.v:8196$2602
+ attribute \src "ls180.v:8242.33-8242.88"
+ cell $or $or$ls180.v:8242$2612
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_start
connect \B \main_sdphy_dataw_crcr_run
- connect \Y $or$ls180.v:8196$2602_Y
+ connect \Y $or$ls180.v:8242$2612_Y
end
- attribute \src "ls180.v:8202.8-8202.99"
- cell $or $or$ls180.v:8202$2604
+ attribute \src "ls180.v:8248.8-8248.99"
+ cell $or $or$ls180.v:8248$2614
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:8202$2603_Y
+ connect \A $eq$ls180.v:8248$2613_Y
connect \B \main_sdphy_dataw_crcr_converter_sink_last
- connect \Y $or$ls180.v:8202$2604_Y
+ connect \Y $or$ls180.v:8248$2614_Y
end
- attribute \src "ls180.v:8219.53-8219.142"
- cell $or $or$ls180.v:8219$2609
+ attribute \src "ls180.v:8265.53-8265.142"
+ cell $or $or$ls180.v:8265$2619
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_sink_first
connect \B \main_sdphy_dataw_crcr_converter_source_first
- connect \Y $or$ls180.v:8219$2609_Y
+ connect \Y $or$ls180.v:8265$2619_Y
end
- attribute \src "ls180.v:8220.52-8220.139"
- cell $or $or$ls180.v:8220$2610
+ attribute \src "ls180.v:8266.52-8266.139"
+ cell $or $or$ls180.v:8266$2620
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_dataw_crcr_converter_sink_last
connect \B \main_sdphy_dataw_crcr_converter_source_last
- connect \Y $or$ls180.v:8220$2610_Y
+ connect \Y $or$ls180.v:8266$2620_Y
end
- attribute \src "ls180.v:8254.7-8254.89"
- cell $or $or$ls180.v:8254$2613
+ attribute \src "ls180.v:8300.7-8300.89"
+ cell $or $or$ls180.v:8300$2623
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:8254$2612_Y
+ connect \A $not$ls180.v:8300$2622_Y
connect \B \main_sdphy_dataw_crcr_buf_source_ready
- connect \Y $or$ls180.v:8254$2613_Y
+ connect \Y $or$ls180.v:8300$2623_Y
end
- attribute \src "ls180.v:8275.34-8275.91"
- cell $or $or$ls180.v:8275$2614
+ attribute \src "ls180.v:8321.34-8321.91"
+ cell $or $or$ls180.v:8321$2624
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_start
connect \B \main_sdphy_datar_datar_run
- connect \Y $or$ls180.v:8275$2614_Y
+ connect \Y $or$ls180.v:8321$2624_Y
end
- attribute \src "ls180.v:8281.8-8281.101"
- cell $or $or$ls180.v:8281$2616
+ attribute \src "ls180.v:8327.8-8327.101"
+ cell $or $or$ls180.v:8327$2626
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:8281$2615_Y
+ connect \A $eq$ls180.v:8327$2625_Y
connect \B \main_sdphy_datar_datar_converter_sink_last
- connect \Y $or$ls180.v:8281$2616_Y
+ connect \Y $or$ls180.v:8327$2626_Y
end
- attribute \src "ls180.v:8298.54-8298.145"
- cell $or $or$ls180.v:8298$2621
+ attribute \src "ls180.v:8344.54-8344.145"
+ cell $or $or$ls180.v:8344$2631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_sink_first
connect \B \main_sdphy_datar_datar_converter_source_first
- connect \Y $or$ls180.v:8298$2621_Y
+ connect \Y $or$ls180.v:8344$2631_Y
end
- attribute \src "ls180.v:8299.53-8299.142"
- cell $or $or$ls180.v:8299$2622
+ attribute \src "ls180.v:8345.53-8345.142"
+ cell $or $or$ls180.v:8345$2632
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdphy_datar_datar_converter_sink_last
connect \B \main_sdphy_datar_datar_converter_source_last
- connect \Y $or$ls180.v:8299$2622_Y
+ connect \Y $or$ls180.v:8345$2632_Y
end
- attribute \src "ls180.v:8315.7-8315.91"
- cell $or $or$ls180.v:8315$2625
+ attribute \src "ls180.v:8361.7-8361.91"
+ cell $or $or$ls180.v:8361$2635
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:8315$2624_Y
+ connect \A $not$ls180.v:8361$2634_Y
connect \B \main_sdphy_datar_datar_buf_source_ready
- connect \Y $or$ls180.v:8315$2625_Y
+ connect \Y $or$ls180.v:8361$2635_Y
end
- attribute \src "ls180.v:8504.8-8504.89"
- cell $or $or$ls180.v:8504$2649
+ attribute \src "ls180.v:8550.8-8550.89"
+ cell $or $or$ls180.v:8550$2659
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:8504$2648_Y
+ connect \A $eq$ls180.v:8550$2658_Y
connect \B \main_sdblock2mem_converter_sink_last
- connect \Y $or$ls180.v:8504$2649_Y
+ connect \Y $or$ls180.v:8550$2659_Y
end
- attribute \src "ls180.v:8521.48-8521.127"
- cell $or $or$ls180.v:8521$2654
+ attribute \src "ls180.v:8567.48-8567.127"
+ cell $or $or$ls180.v:8567$2664
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_sink_first
connect \B \main_sdblock2mem_converter_source_first
- connect \Y $or$ls180.v:8521$2654_Y
+ connect \Y $or$ls180.v:8567$2664_Y
end
- attribute \src "ls180.v:8522.47-8522.124"
- cell $or $or$ls180.v:8522$2655
+ attribute \src "ls180.v:8568.47-8568.124"
+ cell $or $or$ls180.v:8568$2665
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdblock2mem_converter_sink_last
connect \B \main_sdblock2mem_converter_source_last
- connect \Y $or$ls180.v:8522$2655_Y
+ connect \Y $or$ls180.v:8568$2665_Y
end
- attribute \src "ls180.v:8595.21-8595.65"
- cell $or $or$ls180.v:8595$2673
+ attribute \src "ls180.v:8641.21-8641.65"
+ cell $or $or$ls180.v:8641$2683
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:8595$2671_Y
- connect \B $not$ls180.v:8595$2672_Y
- connect \Y $or$ls180.v:8595$2673_Y
+ connect \A $not$ls180.v:8641$2681_Y
+ connect \B $not$ls180.v:8641$2682_Y
+ connect \Y $or$ls180.v:8641$2683_Y
end
- attribute \src "ls180.v:3131.46-3131.94"
- cell $sshl $sshl$ls180.v:3131$83
+ attribute \src "ls180.v:3162.46-3162.94"
+ cell $sshl $sshl$ls180.v:3162$83
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 13
connect \A \main_sdram_bankmachine0_auto_precharge
connect \B 4'1010
- connect \Y $sshl$ls180.v:3131$83_Y
+ connect \Y $sshl$ls180.v:3162$83_Y
end
- attribute \src "ls180.v:3288.46-3288.94"
- cell $sshl $sshl$ls180.v:3288$113
+ attribute \src "ls180.v:3319.46-3319.94"
+ cell $sshl $sshl$ls180.v:3319$113
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 13
connect \A \main_sdram_bankmachine1_auto_precharge
connect \B 4'1010
- connect \Y $sshl$ls180.v:3288$113_Y
+ connect \Y $sshl$ls180.v:3319$113_Y
end
- attribute \src "ls180.v:3445.46-3445.94"
- cell $sshl $sshl$ls180.v:3445$143
+ attribute \src "ls180.v:3476.46-3476.94"
+ cell $sshl $sshl$ls180.v:3476$143
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 13
connect \A \main_sdram_bankmachine2_auto_precharge
connect \B 4'1010
- connect \Y $sshl$ls180.v:3445$143_Y
+ connect \Y $sshl$ls180.v:3476$143_Y
end
- attribute \src "ls180.v:3602.46-3602.94"
- cell $sshl $sshl$ls180.v:3602$173
+ attribute \src "ls180.v:3633.46-3633.94"
+ cell $sshl $sshl$ls180.v:3633$173
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 13
connect \A \main_sdram_bankmachine3_auto_precharge
connect \B 4'1010
- connect \Y $sshl$ls180.v:3602$173_Y
+ connect \Y $sshl$ls180.v:3633$173_Y
end
- attribute \src "ls180.v:3162.63-3162.122"
- cell $sub $sub$ls180.v:3162$96
+ attribute \src "ls180.v:3193.63-3193.122"
+ cell $sub $sub$ls180.v:3193$96
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $sub$ls180.v:3162$96_Y
+ connect \Y $sub$ls180.v:3193$96_Y
end
- attribute \src "ls180.v:3319.63-3319.122"
- cell $sub $sub$ls180.v:3319$126
+ attribute \src "ls180.v:3350.63-3350.122"
+ cell $sub $sub$ls180.v:3350$126
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $sub$ls180.v:3319$126_Y
+ connect \Y $sub$ls180.v:3350$126_Y
end
- attribute \src "ls180.v:3476.63-3476.122"
- cell $sub $sub$ls180.v:3476$156
+ attribute \src "ls180.v:3507.63-3507.122"
+ cell $sub $sub$ls180.v:3507$156
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $sub$ls180.v:3476$156_Y
+ connect \Y $sub$ls180.v:3507$156_Y
end
- attribute \src "ls180.v:3633.63-3633.122"
- cell $sub $sub$ls180.v:3633$186
+ attribute \src "ls180.v:3664.63-3664.122"
+ cell $sub $sub$ls180.v:3664$186
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $sub$ls180.v:3633$186_Y
+ connect \Y $sub$ls180.v:3664$186_Y
end
- attribute \src "ls180.v:4039.38-4039.75"
- cell $sub $sub$ls180.v:4039$540
+ attribute \src "ls180.v:4070.38-4070.75"
+ cell $sub $sub$ls180.v:4070$540
parameter \A_SIGNED 0
parameter \A_WIDTH 30
parameter \B_SIGNED 0
parameter \Y_WIDTH 31
connect \A \main_litedram_wb_adr
connect \B 31'1001000000000000000000000000000
- connect \Y $sub$ls180.v:4039$540_Y
+ connect \Y $sub$ls180.v:4070$540_Y
end
- attribute \src "ls180.v:4125.36-4125.68"
- cell $sub $sub$ls180.v:4125$585
+ attribute \src "ls180.v:4156.36-4156.68"
+ cell $sub $sub$ls180.v:4156$585
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_tx_fifo_produce
connect \B 1'1
- connect \Y $sub$ls180.v:4125$585_Y
+ connect \Y $sub$ls180.v:4156$585_Y
end
- attribute \src "ls180.v:4155.36-4155.68"
- cell $sub $sub$ls180.v:4155$596
+ attribute \src "ls180.v:4186.36-4186.68"
+ cell $sub $sub$ls180.v:4186$596
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_uart_rx_fifo_produce
connect \B 1'1
- connect \Y $sub$ls180.v:4155$596_Y
+ connect \Y $sub$ls180.v:4186$596_Y
end
- attribute \src "ls180.v:4180.69-4180.110"
- cell $sub $sub$ls180.v:4180$602
+ attribute \src "ls180.v:4211.69-4211.110"
+ cell $sub $sub$ls180.v:4211$602
parameter \A_SIGNED 0
parameter \A_WIDTH 15
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \main_spi_master_clk_divider0 [15:1]
connect \B 1'1
- connect \Y $sub$ls180.v:4180$602_Y
+ connect \Y $sub$ls180.v:4211$602_Y
end
- attribute \src "ls180.v:4181.69-4181.104"
- cell $sub $sub$ls180.v:4181$604
+ attribute \src "ls180.v:4212.69-4212.104"
+ cell $sub $sub$ls180.v:4212$604
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \main_spi_master_clk_divider0
connect \B 1'1
- connect \Y $sub$ls180.v:4181$604_Y
+ connect \Y $sub$ls180.v:4212$604_Y
end
- attribute \src "ls180.v:4208.36-4208.66"
- cell $sub $sub$ls180.v:4208$608
+ attribute \src "ls180.v:4239.36-4239.66"
+ cell $sub $sub$ls180.v:4239$608
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_spi_master_length0
connect \B 1'1
- connect \Y $sub$ls180.v:4208$608_Y
+ connect \Y $sub$ls180.v:4239$608_Y
end
- attribute \src "ls180.v:4458.60-4458.90"
- cell $sub $sub$ls180.v:4458$652
+ attribute \src "ls180.v:4493.60-4493.90"
+ cell $sub $sub$ls180.v:4493$652
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdphy_cmdr_timeout
connect \B 1'1
- connect \Y $sub$ls180.v:4458$652_Y
+ connect \Y $sub$ls180.v:4493$652_Y
end
- attribute \src "ls180.v:4469.62-4469.104"
- cell $sub $sub$ls180.v:4469$654
+ attribute \src "ls180.v:4504.62-4504.104"
+ cell $sub $sub$ls180.v:4504$654
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \main_sdphy_cmdr_sink_payload_length
connect \B 1'1
- connect \Y $sub$ls180.v:4469$654_Y
+ connect \Y $sub$ls180.v:4504$654_Y
end
- attribute \src "ls180.v:4486.60-4486.90"
- cell $sub $sub$ls180.v:4486$658
+ attribute \src "ls180.v:4521.60-4521.90"
+ cell $sub $sub$ls180.v:4521$658
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdphy_cmdr_timeout
connect \B 1'1
- connect \Y $sub$ls180.v:4486$658_Y
+ connect \Y $sub$ls180.v:4521$658_Y
end
- attribute \src "ls180.v:4715.62-4715.93"
- cell $sub $sub$ls180.v:4715$688
+ attribute \src "ls180.v:4750.62-4750.93"
+ cell $sub $sub$ls180.v:4750$688
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdphy_datar_timeout
connect \B 1'1
- connect \Y $sub$ls180.v:4715$688_Y
+ connect \Y $sub$ls180.v:4750$688_Y
end
- attribute \src "ls180.v:4720.62-4720.93"
- cell $sub $sub$ls180.v:4720$689
+ attribute \src "ls180.v:4755.62-4755.93"
+ cell $sub $sub$ls180.v:4755$689
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdphy_datar_timeout
connect \B 1'1
- connect \Y $sub$ls180.v:4720$689_Y
+ connect \Y $sub$ls180.v:4755$689_Y
end
- attribute \src "ls180.v:4731.64-4731.122"
- cell $sub $sub$ls180.v:4731$692
+ attribute \src "ls180.v:4766.64-4766.122"
+ cell $sub $sub$ls180.v:4766$692
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 10
- connect \A $add$ls180.v:4731$691_Y
+ connect \A $add$ls180.v:4766$691_Y
connect \B 1'1
- connect \Y $sub$ls180.v:4731$692_Y
+ connect \Y $sub$ls180.v:4766$692_Y
end
- attribute \src "ls180.v:4752.62-4752.93"
- cell $sub $sub$ls180.v:4752$695
+ attribute \src "ls180.v:4787.62-4787.93"
+ cell $sub $sub$ls180.v:4787$695
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdphy_datar_timeout
connect \B 1'1
- connect \Y $sub$ls180.v:4752$695_Y
+ connect \Y $sub$ls180.v:4787$695_Y
end
- attribute \src "ls180.v:5214.37-5214.75"
- cell $sub $sub$ls180.v:5214$968
+ attribute \src "ls180.v:5249.37-5249.75"
+ cell $sub $sub$ls180.v:5249$968
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdcore_block_count_storage
connect \B 1'1
- connect \Y $sub$ls180.v:5214$968_Y
+ connect \Y $sub$ls180.v:5249$968_Y
end
- attribute \src "ls180.v:5229.62-5229.100"
- cell $sub $sub$ls180.v:5229$971
+ attribute \src "ls180.v:5264.62-5264.100"
+ cell $sub $sub$ls180.v:5264$971
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdcore_block_count_storage
connect \B 1'1
- connect \Y $sub$ls180.v:5229$971_Y
+ connect \Y $sub$ls180.v:5264$971_Y
end
- attribute \src "ls180.v:5240.39-5240.77"
- cell $sub $sub$ls180.v:5240$976
+ attribute \src "ls180.v:5275.39-5275.77"
+ cell $sub $sub$ls180.v:5275$976
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdcore_block_count_storage
connect \B 1'1
- connect \Y $sub$ls180.v:5240$976_Y
+ connect \Y $sub$ls180.v:5275$976_Y
end
- attribute \src "ls180.v:5315.40-5315.76"
- cell $sub $sub$ls180.v:5315$980
+ attribute \src "ls180.v:5350.40-5350.76"
+ cell $sub $sub$ls180.v:5350$980
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdblock2mem_fifo_produce
connect \B 1'1
- connect \Y $sub$ls180.v:5315$980_Y
+ connect \Y $sub$ls180.v:5350$980_Y
end
- attribute \src "ls180.v:5364.56-5364.104"
- cell $sub $sub$ls180.v:5364$994
+ attribute \src "ls180.v:5399.56-5399.104"
+ cell $sub $sub$ls180.v:5399$994
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdblock2mem_wishbonedmawriter_length
connect \B 1'1
- connect \Y $sub$ls180.v:5364$994_Y
+ connect \Y $sub$ls180.v:5399$994_Y
end
- attribute \src "ls180.v:5454.71-5454.105"
- cell $sub $sub$ls180.v:5454$1000
+ attribute \src "ls180.v:5489.71-5489.105"
+ cell $sub $sub$ls180.v:5489$1000
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_sdmem2block_dma_length
connect \B 1'1
- connect \Y $sub$ls180.v:5454$1000_Y
+ connect \Y $sub$ls180.v:5489$1000_Y
end
- attribute \src "ls180.v:5523.40-5523.76"
- cell $sub $sub$ls180.v:5523$1011
+ attribute \src "ls180.v:5558.40-5558.76"
+ cell $sub $sub$ls180.v:5558$1011
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdmem2block_fifo_produce
connect \B 1'1
- connect \Y $sub$ls180.v:5523$1011_Y
+ connect \Y $sub$ls180.v:5558$1011_Y
end
- attribute \src "ls180.v:5542.61-5542.98"
- cell $sub $sub$ls180.v:5542$1017
+ attribute \src "ls180.v:5577.61-5577.98"
+ cell $sub $sub$ls180.v:5577$1017
parameter \A_SIGNED 0
parameter \A_WIDTH 15
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \libresocsim_clk_divider0 [15:1]
connect \B 1'1
- connect \Y $sub$ls180.v:5542$1017_Y
+ connect \Y $sub$ls180.v:5577$1017_Y
end
- attribute \src "ls180.v:5543.61-5543.92"
- cell $sub $sub$ls180.v:5543$1019
+ attribute \src "ls180.v:5578.61-5578.92"
+ cell $sub $sub$ls180.v:5578$1019
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \libresocsim_clk_divider0
connect \B 1'1
- connect \Y $sub$ls180.v:5543$1019_Y
+ connect \Y $sub$ls180.v:5578$1019_Y
end
- attribute \src "ls180.v:5571.32-5571.58"
- cell $sub $sub$ls180.v:5571$1023
+ attribute \src "ls180.v:5606.32-5606.58"
+ cell $sub $sub$ls180.v:5606$1023
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \libresocsim_length0
connect \B 1'1
- connect \Y $sub$ls180.v:5571$1023_Y
+ connect \Y $sub$ls180.v:5606$1023_Y
end
- attribute \src "ls180.v:7448.31-7448.60"
- cell $sub $sub$ls180.v:7448$2410
+ attribute \src "ls180.v:7494.31-7494.60"
+ cell $sub $sub$ls180.v:7494$2420
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_libresocsim_value
connect \B 1'1
- connect \Y $sub$ls180.v:7448$2410_Y
+ connect \Y $sub$ls180.v:7494$2420_Y
end
- attribute \src "ls180.v:7469.31-7469.61"
- cell $sub $sub$ls180.v:7469$2415
+ attribute \src "ls180.v:7515.31-7515.61"
+ cell $sub $sub$ls180.v:7515$2425
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \main_sdram_timer_count1
connect \B 1'1
- connect \Y $sub$ls180.v:7469$2415_Y
+ connect \Y $sub$ls180.v:7515$2425_Y
end
- attribute \src "ls180.v:7475.34-7475.67"
- cell $sub $sub$ls180.v:7475$2416
+ attribute \src "ls180.v:7521.34-7521.67"
+ cell $sub $sub$ls180.v:7521$2426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_postponer_count
connect \B 1'1
- connect \Y $sub$ls180.v:7475$2416_Y
+ connect \Y $sub$ls180.v:7521$2426_Y
end
- attribute \src "ls180.v:7486.36-7486.69"
- cell $sub $sub$ls180.v:7486$2419
+ attribute \src "ls180.v:7532.36-7532.69"
+ cell $sub $sub$ls180.v:7532$2429
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_sequencer_count
connect \B 1'1
- connect \Y $sub$ls180.v:7486$2419_Y
+ connect \Y $sub$ls180.v:7532$2429_Y
end
- attribute \src "ls180.v:7550.59-7550.116"
- cell $sub $sub$ls180.v:7550$2437
+ attribute \src "ls180.v:7596.59-7596.116"
+ cell $sub $sub$ls180.v:7596$2447
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $sub$ls180.v:7550$2437_Y
+ connect \Y $sub$ls180.v:7596$2447_Y
end
- attribute \src "ls180.v:7569.46-7569.90"
- cell $sub $sub$ls180.v:7569$2441
+ attribute \src "ls180.v:7615.46-7615.90"
+ cell $sub $sub$ls180.v:7615$2451
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine0_twtpcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:7569$2441_Y
+ connect \Y $sub$ls180.v:7615$2451_Y
end
- attribute \src "ls180.v:7596.59-7596.116"
- cell $sub $sub$ls180.v:7596$2453
+ attribute \src "ls180.v:7642.59-7642.116"
+ cell $sub $sub$ls180.v:7642$2463
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $sub$ls180.v:7596$2453_Y
+ connect \Y $sub$ls180.v:7642$2463_Y
end
- attribute \src "ls180.v:7615.46-7615.90"
- cell $sub $sub$ls180.v:7615$2457
+ attribute \src "ls180.v:7661.46-7661.90"
+ cell $sub $sub$ls180.v:7661$2467
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine1_twtpcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:7615$2457_Y
+ connect \Y $sub$ls180.v:7661$2467_Y
end
- attribute \src "ls180.v:7642.59-7642.116"
- cell $sub $sub$ls180.v:7642$2469
+ attribute \src "ls180.v:7688.59-7688.116"
+ cell $sub $sub$ls180.v:7688$2479
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $sub$ls180.v:7642$2469_Y
+ connect \Y $sub$ls180.v:7688$2479_Y
end
- attribute \src "ls180.v:7661.46-7661.90"
- cell $sub $sub$ls180.v:7661$2473
+ attribute \src "ls180.v:7707.46-7707.90"
+ cell $sub $sub$ls180.v:7707$2483
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine2_twtpcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:7661$2473_Y
+ connect \Y $sub$ls180.v:7707$2483_Y
end
- attribute \src "ls180.v:7688.59-7688.116"
- cell $sub $sub$ls180.v:7688$2485
+ attribute \src "ls180.v:7734.59-7734.116"
+ cell $sub $sub$ls180.v:7734$2495
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $sub$ls180.v:7688$2485_Y
+ connect \Y $sub$ls180.v:7734$2495_Y
end
- attribute \src "ls180.v:7707.46-7707.90"
- cell $sub $sub$ls180.v:7707$2489
+ attribute \src "ls180.v:7753.46-7753.90"
+ cell $sub $sub$ls180.v:7753$2499
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_bankmachine3_twtpcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:7707$2489_Y
+ connect \Y $sub$ls180.v:7753$2499_Y
end
- attribute \src "ls180.v:7718.25-7718.48"
- cell $sub $sub$ls180.v:7718$2493
+ attribute \src "ls180.v:7764.25-7764.48"
+ cell $sub $sub$ls180.v:7764$2503
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_sdram_time0
connect \B 1'1
- connect \Y $sub$ls180.v:7718$2493_Y
+ connect \Y $sub$ls180.v:7764$2503_Y
end
- attribute \src "ls180.v:7725.25-7725.48"
- cell $sub $sub$ls180.v:7725$2496
+ attribute \src "ls180.v:7771.25-7771.48"
+ cell $sub $sub$ls180.v:7771$2506
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \main_sdram_time1
connect \B 1'1
- connect \Y $sub$ls180.v:7725$2496_Y
+ connect \Y $sub$ls180.v:7771$2506_Y
end
- attribute \src "ls180.v:7857.33-7857.64"
- cell $sub $sub$ls180.v:7857$2501
+ attribute \src "ls180.v:7903.33-7903.64"
+ cell $sub $sub$ls180.v:7903$2511
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdram_tccdcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:7857$2501_Y
+ connect \Y $sub$ls180.v:7903$2511_Y
end
- attribute \src "ls180.v:7872.33-7872.64"
- cell $sub $sub$ls180.v:7872$2504
+ attribute \src "ls180.v:7918.33-7918.64"
+ cell $sub $sub$ls180.v:7918$2514
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_sdram_twtrcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:7872$2504_Y
+ connect \Y $sub$ls180.v:7918$2514_Y
end
- attribute \src "ls180.v:7999.33-7999.64"
- cell $sub $sub$ls180.v:7999$2563
+ attribute \src "ls180.v:8045.33-8045.64"
+ cell $sub $sub$ls180.v:8045$2573
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_uart_tx_fifo_level0
connect \B 1'1
- connect \Y $sub$ls180.v:7999$2563_Y
+ connect \Y $sub$ls180.v:8045$2573_Y
end
- attribute \src "ls180.v:8021.33-8021.64"
- cell $sub $sub$ls180.v:8021$2574
+ attribute \src "ls180.v:8067.33-8067.64"
+ cell $sub $sub$ls180.v:8067$2584
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \main_uart_rx_fifo_level0
connect \B 1'1
- connect \Y $sub$ls180.v:8021$2574_Y
+ connect \Y $sub$ls180.v:8067$2584_Y
end
- attribute \src "ls180.v:8056.33-8056.64"
- cell $sub $sub$ls180.v:8056$2579
+ attribute \src "ls180.v:8102.33-8102.64"
+ cell $sub $sub$ls180.v:8102$2589
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \main_spi_master_mosi_sel
connect \B 1'1
- connect \Y $sub$ls180.v:8056$2579_Y
+ connect \Y $sub$ls180.v:8102$2589_Y
end
- attribute \src "ls180.v:8080.30-8080.53"
- cell $sub $sub$ls180.v:8080$2582
+ attribute \src "ls180.v:8126.30-8126.53"
+ cell $sub $sub$ls180.v:8126$2592
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_pwm0_period
connect \B 1'1
- connect \Y $sub$ls180.v:8080$2582_Y
+ connect \Y $sub$ls180.v:8126$2592_Y
end
- attribute \src "ls180.v:8094.30-8094.53"
- cell $sub $sub$ls180.v:8094$2586
+ attribute \src "ls180.v:8140.30-8140.53"
+ cell $sub $sub$ls180.v:8140$2596
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \main_pwm1_period
connect \B 1'1
- connect \Y $sub$ls180.v:8094$2586_Y
+ connect \Y $sub$ls180.v:8140$2596_Y
end
- attribute \src "ls180.v:8497.36-8497.70"
- cell $sub $sub$ls180.v:8497$2647
+ attribute \src "ls180.v:8543.36-8543.70"
+ cell $sub $sub$ls180.v:8543$2657
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \main_sdblock2mem_fifo_level
connect \B 1'1
- connect \Y $sub$ls180.v:8497$2647_Y
+ connect \Y $sub$ls180.v:8543$2657_Y
end
- attribute \src "ls180.v:8583.36-8583.70"
- cell $sub $sub$ls180.v:8583$2669
+ attribute \src "ls180.v:8629.36-8629.70"
+ cell $sub $sub$ls180.v:8629$2679
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \main_sdmem2block_fifo_level
connect \B 1'1
- connect \Y $sub$ls180.v:8583$2669_Y
+ connect \Y $sub$ls180.v:8629$2679_Y
end
- attribute \src "ls180.v:8604.29-8604.56"
- cell $sub $sub$ls180.v:8604$2674
+ attribute \src "ls180.v:8650.29-8650.56"
+ cell $sub $sub$ls180.v:8650$2684
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \libresocsim_mosi_sel
connect \B 1'1
- connect \Y $sub$ls180.v:8604$2674_Y
+ connect \Y $sub$ls180.v:8650$2684_Y
end
- attribute \src "ls180.v:8731.22-8731.42"
- cell $sub $sub$ls180.v:8731$2681
+ attribute \src "ls180.v:8777.22-8777.42"
+ cell $sub $sub$ls180.v:8777$2691
parameter \A_SIGNED 0
parameter \A_WIDTH 20
parameter \B_SIGNED 0
parameter \Y_WIDTH 20
connect \A \builder_count
connect \B 1'1
- connect \Y $sub$ls180.v:8731$2681_Y
+ connect \Y $sub$ls180.v:8777$2691_Y
end
- attribute \src "ls180.v:4812.353-4812.425"
- cell $xor $xor$ls180.v:4812$702
+ attribute \src "ls180.v:4847.353-4847.425"
+ cell $xor $xor$ls180.v:4847$702
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [39]
connect \B \main_sdcore_crc7_inserter_crcreg0 [6]
- connect \Y $xor$ls180.v:4812$702_Y
+ connect \Y $xor$ls180.v:4847$702_Y
end
- attribute \src "ls180.v:4812.200-4812.272"
- cell $xor $xor$ls180.v:4812$703
+ attribute \src "ls180.v:4847.200-4847.272"
+ cell $xor $xor$ls180.v:4847$703
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [39]
connect \B \main_sdcore_crc7_inserter_crcreg0 [6]
- connect \Y $xor$ls180.v:4812$703_Y
+ connect \Y $xor$ls180.v:4847$703_Y
end
- attribute \src "ls180.v:4812.160-4812.273"
- cell $xor $xor$ls180.v:4812$704
+ attribute \src "ls180.v:4847.160-4847.273"
+ cell $xor $xor$ls180.v:4847$704
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg0 [2]
- connect \B $xor$ls180.v:4812$703_Y
- connect \Y $xor$ls180.v:4812$704_Y
+ connect \B $xor$ls180.v:4847$703_Y
+ connect \Y $xor$ls180.v:4847$704_Y
end
- attribute \src "ls180.v:4813.353-4813.425"
- cell $xor $xor$ls180.v:4813$705
+ attribute \src "ls180.v:4848.353-4848.425"
+ cell $xor $xor$ls180.v:4848$705
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [38]
connect \B \main_sdcore_crc7_inserter_crcreg1 [6]
- connect \Y $xor$ls180.v:4813$705_Y
+ connect \Y $xor$ls180.v:4848$705_Y
end
- attribute \src "ls180.v:4813.200-4813.272"
- cell $xor $xor$ls180.v:4813$706
+ attribute \src "ls180.v:4848.200-4848.272"
+ cell $xor $xor$ls180.v:4848$706
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [38]
connect \B \main_sdcore_crc7_inserter_crcreg1 [6]
- connect \Y $xor$ls180.v:4813$706_Y
+ connect \Y $xor$ls180.v:4848$706_Y
end
- attribute \src "ls180.v:4813.160-4813.273"
- cell $xor $xor$ls180.v:4813$707
+ attribute \src "ls180.v:4848.160-4848.273"
+ cell $xor $xor$ls180.v:4848$707
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg1 [2]
- connect \B $xor$ls180.v:4813$706_Y
- connect \Y $xor$ls180.v:4813$707_Y
+ connect \B $xor$ls180.v:4848$706_Y
+ connect \Y $xor$ls180.v:4848$707_Y
end
- attribute \src "ls180.v:4814.353-4814.425"
- cell $xor $xor$ls180.v:4814$708
+ attribute \src "ls180.v:4849.353-4849.425"
+ cell $xor $xor$ls180.v:4849$708
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [37]
connect \B \main_sdcore_crc7_inserter_crcreg2 [6]
- connect \Y $xor$ls180.v:4814$708_Y
+ connect \Y $xor$ls180.v:4849$708_Y
end
- attribute \src "ls180.v:4814.200-4814.272"
- cell $xor $xor$ls180.v:4814$709
+ attribute \src "ls180.v:4849.200-4849.272"
+ cell $xor $xor$ls180.v:4849$709
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [37]
connect \B \main_sdcore_crc7_inserter_crcreg2 [6]
- connect \Y $xor$ls180.v:4814$709_Y
+ connect \Y $xor$ls180.v:4849$709_Y
end
- attribute \src "ls180.v:4814.160-4814.273"
- cell $xor $xor$ls180.v:4814$710
+ attribute \src "ls180.v:4849.160-4849.273"
+ cell $xor $xor$ls180.v:4849$710
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg2 [2]
- connect \B $xor$ls180.v:4814$709_Y
- connect \Y $xor$ls180.v:4814$710_Y
+ connect \B $xor$ls180.v:4849$709_Y
+ connect \Y $xor$ls180.v:4849$710_Y
end
- attribute \src "ls180.v:4815.353-4815.425"
- cell $xor $xor$ls180.v:4815$711
+ attribute \src "ls180.v:4850.353-4850.425"
+ cell $xor $xor$ls180.v:4850$711
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [36]
connect \B \main_sdcore_crc7_inserter_crcreg3 [6]
- connect \Y $xor$ls180.v:4815$711_Y
+ connect \Y $xor$ls180.v:4850$711_Y
end
- attribute \src "ls180.v:4815.200-4815.272"
- cell $xor $xor$ls180.v:4815$712
+ attribute \src "ls180.v:4850.200-4850.272"
+ cell $xor $xor$ls180.v:4850$712
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [36]
connect \B \main_sdcore_crc7_inserter_crcreg3 [6]
- connect \Y $xor$ls180.v:4815$712_Y
+ connect \Y $xor$ls180.v:4850$712_Y
end
- attribute \src "ls180.v:4815.160-4815.273"
- cell $xor $xor$ls180.v:4815$713
+ attribute \src "ls180.v:4850.160-4850.273"
+ cell $xor $xor$ls180.v:4850$713
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg3 [2]
- connect \B $xor$ls180.v:4815$712_Y
- connect \Y $xor$ls180.v:4815$713_Y
+ connect \B $xor$ls180.v:4850$712_Y
+ connect \Y $xor$ls180.v:4850$713_Y
end
- attribute \src "ls180.v:4816.353-4816.425"
- cell $xor $xor$ls180.v:4816$714
+ attribute \src "ls180.v:4851.353-4851.425"
+ cell $xor $xor$ls180.v:4851$714
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [35]
connect \B \main_sdcore_crc7_inserter_crcreg4 [6]
- connect \Y $xor$ls180.v:4816$714_Y
+ connect \Y $xor$ls180.v:4851$714_Y
end
- attribute \src "ls180.v:4816.200-4816.272"
- cell $xor $xor$ls180.v:4816$715
+ attribute \src "ls180.v:4851.200-4851.272"
+ cell $xor $xor$ls180.v:4851$715
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [35]
connect \B \main_sdcore_crc7_inserter_crcreg4 [6]
- connect \Y $xor$ls180.v:4816$715_Y
+ connect \Y $xor$ls180.v:4851$715_Y
end
- attribute \src "ls180.v:4816.160-4816.273"
- cell $xor $xor$ls180.v:4816$716
+ attribute \src "ls180.v:4851.160-4851.273"
+ cell $xor $xor$ls180.v:4851$716
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg4 [2]
- connect \B $xor$ls180.v:4816$715_Y
- connect \Y $xor$ls180.v:4816$716_Y
+ connect \B $xor$ls180.v:4851$715_Y
+ connect \Y $xor$ls180.v:4851$716_Y
end
- attribute \src "ls180.v:4817.353-4817.425"
- cell $xor $xor$ls180.v:4817$717
+ attribute \src "ls180.v:4852.353-4852.425"
+ cell $xor $xor$ls180.v:4852$717
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [34]
connect \B \main_sdcore_crc7_inserter_crcreg5 [6]
- connect \Y $xor$ls180.v:4817$717_Y
+ connect \Y $xor$ls180.v:4852$717_Y
end
- attribute \src "ls180.v:4817.200-4817.272"
- cell $xor $xor$ls180.v:4817$718
+ attribute \src "ls180.v:4852.200-4852.272"
+ cell $xor $xor$ls180.v:4852$718
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [34]
connect \B \main_sdcore_crc7_inserter_crcreg5 [6]
- connect \Y $xor$ls180.v:4817$718_Y
+ connect \Y $xor$ls180.v:4852$718_Y
end
- attribute \src "ls180.v:4817.160-4817.273"
- cell $xor $xor$ls180.v:4817$719
+ attribute \src "ls180.v:4852.160-4852.273"
+ cell $xor $xor$ls180.v:4852$719
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg5 [2]
- connect \B $xor$ls180.v:4817$718_Y
- connect \Y $xor$ls180.v:4817$719_Y
+ connect \B $xor$ls180.v:4852$718_Y
+ connect \Y $xor$ls180.v:4852$719_Y
end
- attribute \src "ls180.v:4818.353-4818.425"
- cell $xor $xor$ls180.v:4818$720
+ attribute \src "ls180.v:4853.353-4853.425"
+ cell $xor $xor$ls180.v:4853$720
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [33]
connect \B \main_sdcore_crc7_inserter_crcreg6 [6]
- connect \Y $xor$ls180.v:4818$720_Y
+ connect \Y $xor$ls180.v:4853$720_Y
end
- attribute \src "ls180.v:4818.200-4818.272"
- cell $xor $xor$ls180.v:4818$721
+ attribute \src "ls180.v:4853.200-4853.272"
+ cell $xor $xor$ls180.v:4853$721
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [33]
connect \B \main_sdcore_crc7_inserter_crcreg6 [6]
- connect \Y $xor$ls180.v:4818$721_Y
+ connect \Y $xor$ls180.v:4853$721_Y
end
- attribute \src "ls180.v:4818.160-4818.273"
- cell $xor $xor$ls180.v:4818$722
+ attribute \src "ls180.v:4853.160-4853.273"
+ cell $xor $xor$ls180.v:4853$722
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg6 [2]
- connect \B $xor$ls180.v:4818$721_Y
- connect \Y $xor$ls180.v:4818$722_Y
+ connect \B $xor$ls180.v:4853$721_Y
+ connect \Y $xor$ls180.v:4853$722_Y
end
- attribute \src "ls180.v:4819.353-4819.425"
- cell $xor $xor$ls180.v:4819$723
+ attribute \src "ls180.v:4854.353-4854.425"
+ cell $xor $xor$ls180.v:4854$723
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [32]
connect \B \main_sdcore_crc7_inserter_crcreg7 [6]
- connect \Y $xor$ls180.v:4819$723_Y
+ connect \Y $xor$ls180.v:4854$723_Y
end
- attribute \src "ls180.v:4819.200-4819.272"
- cell $xor $xor$ls180.v:4819$724
+ attribute \src "ls180.v:4854.200-4854.272"
+ cell $xor $xor$ls180.v:4854$724
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [32]
connect \B \main_sdcore_crc7_inserter_crcreg7 [6]
- connect \Y $xor$ls180.v:4819$724_Y
+ connect \Y $xor$ls180.v:4854$724_Y
end
- attribute \src "ls180.v:4819.160-4819.273"
- cell $xor $xor$ls180.v:4819$725
+ attribute \src "ls180.v:4854.160-4854.273"
+ cell $xor $xor$ls180.v:4854$725
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg7 [2]
- connect \B $xor$ls180.v:4819$724_Y
- connect \Y $xor$ls180.v:4819$725_Y
+ connect \B $xor$ls180.v:4854$724_Y
+ connect \Y $xor$ls180.v:4854$725_Y
end
- attribute \src "ls180.v:4820.353-4820.425"
- cell $xor $xor$ls180.v:4820$726
+ attribute \src "ls180.v:4855.353-4855.425"
+ cell $xor $xor$ls180.v:4855$726
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [31]
connect \B \main_sdcore_crc7_inserter_crcreg8 [6]
- connect \Y $xor$ls180.v:4820$726_Y
+ connect \Y $xor$ls180.v:4855$726_Y
end
- attribute \src "ls180.v:4820.200-4820.272"
- cell $xor $xor$ls180.v:4820$727
+ attribute \src "ls180.v:4855.200-4855.272"
+ cell $xor $xor$ls180.v:4855$727
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [31]
connect \B \main_sdcore_crc7_inserter_crcreg8 [6]
- connect \Y $xor$ls180.v:4820$727_Y
+ connect \Y $xor$ls180.v:4855$727_Y
end
- attribute \src "ls180.v:4820.160-4820.273"
- cell $xor $xor$ls180.v:4820$728
+ attribute \src "ls180.v:4855.160-4855.273"
+ cell $xor $xor$ls180.v:4855$728
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg8 [2]
- connect \B $xor$ls180.v:4820$727_Y
- connect \Y $xor$ls180.v:4820$728_Y
+ connect \B $xor$ls180.v:4855$727_Y
+ connect \Y $xor$ls180.v:4855$728_Y
end
- attribute \src "ls180.v:4821.354-4821.426"
- cell $xor $xor$ls180.v:4821$729
+ attribute \src "ls180.v:4856.354-4856.426"
+ cell $xor $xor$ls180.v:4856$729
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [30]
connect \B \main_sdcore_crc7_inserter_crcreg9 [6]
- connect \Y $xor$ls180.v:4821$729_Y
+ connect \Y $xor$ls180.v:4856$729_Y
end
- attribute \src "ls180.v:4821.201-4821.273"
- cell $xor $xor$ls180.v:4821$730
+ attribute \src "ls180.v:4856.201-4856.273"
+ cell $xor $xor$ls180.v:4856$730
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [30]
connect \B \main_sdcore_crc7_inserter_crcreg9 [6]
- connect \Y $xor$ls180.v:4821$730_Y
+ connect \Y $xor$ls180.v:4856$730_Y
end
- attribute \src "ls180.v:4821.161-4821.274"
- cell $xor $xor$ls180.v:4821$731
+ attribute \src "ls180.v:4856.161-4856.274"
+ cell $xor $xor$ls180.v:4856$731
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg9 [2]
- connect \B $xor$ls180.v:4821$730_Y
- connect \Y $xor$ls180.v:4821$731_Y
+ connect \B $xor$ls180.v:4856$730_Y
+ connect \Y $xor$ls180.v:4856$731_Y
end
- attribute \src "ls180.v:4822.361-4822.434"
- cell $xor $xor$ls180.v:4822$732
+ attribute \src "ls180.v:4857.361-4857.434"
+ cell $xor $xor$ls180.v:4857$732
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [29]
connect \B \main_sdcore_crc7_inserter_crcreg10 [6]
- connect \Y $xor$ls180.v:4822$732_Y
+ connect \Y $xor$ls180.v:4857$732_Y
end
- attribute \src "ls180.v:4822.205-4822.278"
- cell $xor $xor$ls180.v:4822$733
+ attribute \src "ls180.v:4857.205-4857.278"
+ cell $xor $xor$ls180.v:4857$733
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [29]
connect \B \main_sdcore_crc7_inserter_crcreg10 [6]
- connect \Y $xor$ls180.v:4822$733_Y
+ connect \Y $xor$ls180.v:4857$733_Y
end
- attribute \src "ls180.v:4822.164-4822.279"
- cell $xor $xor$ls180.v:4822$734
+ attribute \src "ls180.v:4857.164-4857.279"
+ cell $xor $xor$ls180.v:4857$734
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg10 [2]
- connect \B $xor$ls180.v:4822$733_Y
- connect \Y $xor$ls180.v:4822$734_Y
+ connect \B $xor$ls180.v:4857$733_Y
+ connect \Y $xor$ls180.v:4857$734_Y
end
- attribute \src "ls180.v:4823.361-4823.434"
- cell $xor $xor$ls180.v:4823$735
+ attribute \src "ls180.v:4858.361-4858.434"
+ cell $xor $xor$ls180.v:4858$735
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [28]
connect \B \main_sdcore_crc7_inserter_crcreg11 [6]
- connect \Y $xor$ls180.v:4823$735_Y
+ connect \Y $xor$ls180.v:4858$735_Y
end
- attribute \src "ls180.v:4823.205-4823.278"
- cell $xor $xor$ls180.v:4823$736
+ attribute \src "ls180.v:4858.205-4858.278"
+ cell $xor $xor$ls180.v:4858$736
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [28]
connect \B \main_sdcore_crc7_inserter_crcreg11 [6]
- connect \Y $xor$ls180.v:4823$736_Y
+ connect \Y $xor$ls180.v:4858$736_Y
end
- attribute \src "ls180.v:4823.164-4823.279"
- cell $xor $xor$ls180.v:4823$737
+ attribute \src "ls180.v:4858.164-4858.279"
+ cell $xor $xor$ls180.v:4858$737
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg11 [2]
- connect \B $xor$ls180.v:4823$736_Y
- connect \Y $xor$ls180.v:4823$737_Y
+ connect \B $xor$ls180.v:4858$736_Y
+ connect \Y $xor$ls180.v:4858$737_Y
end
- attribute \src "ls180.v:4824.361-4824.434"
- cell $xor $xor$ls180.v:4824$738
+ attribute \src "ls180.v:4859.361-4859.434"
+ cell $xor $xor$ls180.v:4859$738
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [27]
connect \B \main_sdcore_crc7_inserter_crcreg12 [6]
- connect \Y $xor$ls180.v:4824$738_Y
+ connect \Y $xor$ls180.v:4859$738_Y
end
- attribute \src "ls180.v:4824.205-4824.278"
- cell $xor $xor$ls180.v:4824$739
+ attribute \src "ls180.v:4859.205-4859.278"
+ cell $xor $xor$ls180.v:4859$739
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [27]
connect \B \main_sdcore_crc7_inserter_crcreg12 [6]
- connect \Y $xor$ls180.v:4824$739_Y
+ connect \Y $xor$ls180.v:4859$739_Y
end
- attribute \src "ls180.v:4824.164-4824.279"
- cell $xor $xor$ls180.v:4824$740
+ attribute \src "ls180.v:4859.164-4859.279"
+ cell $xor $xor$ls180.v:4859$740
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg12 [2]
- connect \B $xor$ls180.v:4824$739_Y
- connect \Y $xor$ls180.v:4824$740_Y
+ connect \B $xor$ls180.v:4859$739_Y
+ connect \Y $xor$ls180.v:4859$740_Y
end
- attribute \src "ls180.v:4825.361-4825.434"
- cell $xor $xor$ls180.v:4825$741
+ attribute \src "ls180.v:4860.361-4860.434"
+ cell $xor $xor$ls180.v:4860$741
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [26]
connect \B \main_sdcore_crc7_inserter_crcreg13 [6]
- connect \Y $xor$ls180.v:4825$741_Y
+ connect \Y $xor$ls180.v:4860$741_Y
end
- attribute \src "ls180.v:4825.205-4825.278"
- cell $xor $xor$ls180.v:4825$742
+ attribute \src "ls180.v:4860.205-4860.278"
+ cell $xor $xor$ls180.v:4860$742
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [26]
connect \B \main_sdcore_crc7_inserter_crcreg13 [6]
- connect \Y $xor$ls180.v:4825$742_Y
+ connect \Y $xor$ls180.v:4860$742_Y
end
- attribute \src "ls180.v:4825.164-4825.279"
- cell $xor $xor$ls180.v:4825$743
+ attribute \src "ls180.v:4860.164-4860.279"
+ cell $xor $xor$ls180.v:4860$743
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg13 [2]
- connect \B $xor$ls180.v:4825$742_Y
- connect \Y $xor$ls180.v:4825$743_Y
+ connect \B $xor$ls180.v:4860$742_Y
+ connect \Y $xor$ls180.v:4860$743_Y
end
- attribute \src "ls180.v:4826.361-4826.434"
- cell $xor $xor$ls180.v:4826$744
+ attribute \src "ls180.v:4861.361-4861.434"
+ cell $xor $xor$ls180.v:4861$744
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [25]
connect \B \main_sdcore_crc7_inserter_crcreg14 [6]
- connect \Y $xor$ls180.v:4826$744_Y
+ connect \Y $xor$ls180.v:4861$744_Y
end
- attribute \src "ls180.v:4826.205-4826.278"
- cell $xor $xor$ls180.v:4826$745
+ attribute \src "ls180.v:4861.205-4861.278"
+ cell $xor $xor$ls180.v:4861$745
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [25]
connect \B \main_sdcore_crc7_inserter_crcreg14 [6]
- connect \Y $xor$ls180.v:4826$745_Y
+ connect \Y $xor$ls180.v:4861$745_Y
end
- attribute \src "ls180.v:4826.164-4826.279"
- cell $xor $xor$ls180.v:4826$746
+ attribute \src "ls180.v:4861.164-4861.279"
+ cell $xor $xor$ls180.v:4861$746
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg14 [2]
- connect \B $xor$ls180.v:4826$745_Y
- connect \Y $xor$ls180.v:4826$746_Y
+ connect \B $xor$ls180.v:4861$745_Y
+ connect \Y $xor$ls180.v:4861$746_Y
end
- attribute \src "ls180.v:4827.361-4827.434"
- cell $xor $xor$ls180.v:4827$747
+ attribute \src "ls180.v:4862.361-4862.434"
+ cell $xor $xor$ls180.v:4862$747
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [24]
connect \B \main_sdcore_crc7_inserter_crcreg15 [6]
- connect \Y $xor$ls180.v:4827$747_Y
+ connect \Y $xor$ls180.v:4862$747_Y
end
- attribute \src "ls180.v:4827.205-4827.278"
- cell $xor $xor$ls180.v:4827$748
+ attribute \src "ls180.v:4862.205-4862.278"
+ cell $xor $xor$ls180.v:4862$748
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [24]
connect \B \main_sdcore_crc7_inserter_crcreg15 [6]
- connect \Y $xor$ls180.v:4827$748_Y
+ connect \Y $xor$ls180.v:4862$748_Y
end
- attribute \src "ls180.v:4827.164-4827.279"
- cell $xor $xor$ls180.v:4827$749
+ attribute \src "ls180.v:4862.164-4862.279"
+ cell $xor $xor$ls180.v:4862$749
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg15 [2]
- connect \B $xor$ls180.v:4827$748_Y
- connect \Y $xor$ls180.v:4827$749_Y
+ connect \B $xor$ls180.v:4862$748_Y
+ connect \Y $xor$ls180.v:4862$749_Y
end
- attribute \src "ls180.v:4828.361-4828.434"
- cell $xor $xor$ls180.v:4828$750
+ attribute \src "ls180.v:4863.361-4863.434"
+ cell $xor $xor$ls180.v:4863$750
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [23]
connect \B \main_sdcore_crc7_inserter_crcreg16 [6]
- connect \Y $xor$ls180.v:4828$750_Y
+ connect \Y $xor$ls180.v:4863$750_Y
end
- attribute \src "ls180.v:4828.205-4828.278"
- cell $xor $xor$ls180.v:4828$751
+ attribute \src "ls180.v:4863.205-4863.278"
+ cell $xor $xor$ls180.v:4863$751
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [23]
connect \B \main_sdcore_crc7_inserter_crcreg16 [6]
- connect \Y $xor$ls180.v:4828$751_Y
+ connect \Y $xor$ls180.v:4863$751_Y
end
- attribute \src "ls180.v:4828.164-4828.279"
- cell $xor $xor$ls180.v:4828$752
+ attribute \src "ls180.v:4863.164-4863.279"
+ cell $xor $xor$ls180.v:4863$752
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg16 [2]
- connect \B $xor$ls180.v:4828$751_Y
- connect \Y $xor$ls180.v:4828$752_Y
+ connect \B $xor$ls180.v:4863$751_Y
+ connect \Y $xor$ls180.v:4863$752_Y
end
- attribute \src "ls180.v:4829.361-4829.434"
- cell $xor $xor$ls180.v:4829$753
+ attribute \src "ls180.v:4864.361-4864.434"
+ cell $xor $xor$ls180.v:4864$753
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [22]
connect \B \main_sdcore_crc7_inserter_crcreg17 [6]
- connect \Y $xor$ls180.v:4829$753_Y
+ connect \Y $xor$ls180.v:4864$753_Y
end
- attribute \src "ls180.v:4829.205-4829.278"
- cell $xor $xor$ls180.v:4829$754
+ attribute \src "ls180.v:4864.205-4864.278"
+ cell $xor $xor$ls180.v:4864$754
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [22]
connect \B \main_sdcore_crc7_inserter_crcreg17 [6]
- connect \Y $xor$ls180.v:4829$754_Y
+ connect \Y $xor$ls180.v:4864$754_Y
end
- attribute \src "ls180.v:4829.164-4829.279"
- cell $xor $xor$ls180.v:4829$755
+ attribute \src "ls180.v:4864.164-4864.279"
+ cell $xor $xor$ls180.v:4864$755
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg17 [2]
- connect \B $xor$ls180.v:4829$754_Y
- connect \Y $xor$ls180.v:4829$755_Y
+ connect \B $xor$ls180.v:4864$754_Y
+ connect \Y $xor$ls180.v:4864$755_Y
end
- attribute \src "ls180.v:4830.361-4830.434"
- cell $xor $xor$ls180.v:4830$756
+ attribute \src "ls180.v:4865.361-4865.434"
+ cell $xor $xor$ls180.v:4865$756
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [21]
connect \B \main_sdcore_crc7_inserter_crcreg18 [6]
- connect \Y $xor$ls180.v:4830$756_Y
+ connect \Y $xor$ls180.v:4865$756_Y
end
- attribute \src "ls180.v:4830.205-4830.278"
- cell $xor $xor$ls180.v:4830$757
+ attribute \src "ls180.v:4865.205-4865.278"
+ cell $xor $xor$ls180.v:4865$757
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [21]
connect \B \main_sdcore_crc7_inserter_crcreg18 [6]
- connect \Y $xor$ls180.v:4830$757_Y
+ connect \Y $xor$ls180.v:4865$757_Y
end
- attribute \src "ls180.v:4830.164-4830.279"
- cell $xor $xor$ls180.v:4830$758
+ attribute \src "ls180.v:4865.164-4865.279"
+ cell $xor $xor$ls180.v:4865$758
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg18 [2]
- connect \B $xor$ls180.v:4830$757_Y
- connect \Y $xor$ls180.v:4830$758_Y
+ connect \B $xor$ls180.v:4865$757_Y
+ connect \Y $xor$ls180.v:4865$758_Y
end
- attribute \src "ls180.v:4831.361-4831.434"
- cell $xor $xor$ls180.v:4831$759
+ attribute \src "ls180.v:4866.361-4866.434"
+ cell $xor $xor$ls180.v:4866$759
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [20]
connect \B \main_sdcore_crc7_inserter_crcreg19 [6]
- connect \Y $xor$ls180.v:4831$759_Y
+ connect \Y $xor$ls180.v:4866$759_Y
end
- attribute \src "ls180.v:4831.205-4831.278"
- cell $xor $xor$ls180.v:4831$760
+ attribute \src "ls180.v:4866.205-4866.278"
+ cell $xor $xor$ls180.v:4866$760
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [20]
connect \B \main_sdcore_crc7_inserter_crcreg19 [6]
- connect \Y $xor$ls180.v:4831$760_Y
+ connect \Y $xor$ls180.v:4866$760_Y
end
- attribute \src "ls180.v:4831.164-4831.279"
- cell $xor $xor$ls180.v:4831$761
+ attribute \src "ls180.v:4866.164-4866.279"
+ cell $xor $xor$ls180.v:4866$761
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg19 [2]
- connect \B $xor$ls180.v:4831$760_Y
- connect \Y $xor$ls180.v:4831$761_Y
+ connect \B $xor$ls180.v:4866$760_Y
+ connect \Y $xor$ls180.v:4866$761_Y
end
- attribute \src "ls180.v:4832.361-4832.434"
- cell $xor $xor$ls180.v:4832$762
+ attribute \src "ls180.v:4867.361-4867.434"
+ cell $xor $xor$ls180.v:4867$762
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [19]
connect \B \main_sdcore_crc7_inserter_crcreg20 [6]
- connect \Y $xor$ls180.v:4832$762_Y
+ connect \Y $xor$ls180.v:4867$762_Y
end
- attribute \src "ls180.v:4832.205-4832.278"
- cell $xor $xor$ls180.v:4832$763
+ attribute \src "ls180.v:4867.205-4867.278"
+ cell $xor $xor$ls180.v:4867$763
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [19]
connect \B \main_sdcore_crc7_inserter_crcreg20 [6]
- connect \Y $xor$ls180.v:4832$763_Y
+ connect \Y $xor$ls180.v:4867$763_Y
end
- attribute \src "ls180.v:4832.164-4832.279"
- cell $xor $xor$ls180.v:4832$764
+ attribute \src "ls180.v:4867.164-4867.279"
+ cell $xor $xor$ls180.v:4867$764
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg20 [2]
- connect \B $xor$ls180.v:4832$763_Y
- connect \Y $xor$ls180.v:4832$764_Y
+ connect \B $xor$ls180.v:4867$763_Y
+ connect \Y $xor$ls180.v:4867$764_Y
end
- attribute \src "ls180.v:4833.361-4833.434"
- cell $xor $xor$ls180.v:4833$765
+ attribute \src "ls180.v:4868.361-4868.434"
+ cell $xor $xor$ls180.v:4868$765
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [18]
connect \B \main_sdcore_crc7_inserter_crcreg21 [6]
- connect \Y $xor$ls180.v:4833$765_Y
+ connect \Y $xor$ls180.v:4868$765_Y
end
- attribute \src "ls180.v:4833.205-4833.278"
- cell $xor $xor$ls180.v:4833$766
+ attribute \src "ls180.v:4868.205-4868.278"
+ cell $xor $xor$ls180.v:4868$766
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [18]
connect \B \main_sdcore_crc7_inserter_crcreg21 [6]
- connect \Y $xor$ls180.v:4833$766_Y
+ connect \Y $xor$ls180.v:4868$766_Y
end
- attribute \src "ls180.v:4833.164-4833.279"
- cell $xor $xor$ls180.v:4833$767
+ attribute \src "ls180.v:4868.164-4868.279"
+ cell $xor $xor$ls180.v:4868$767
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg21 [2]
- connect \B $xor$ls180.v:4833$766_Y
- connect \Y $xor$ls180.v:4833$767_Y
+ connect \B $xor$ls180.v:4868$766_Y
+ connect \Y $xor$ls180.v:4868$767_Y
end
- attribute \src "ls180.v:4834.361-4834.434"
- cell $xor $xor$ls180.v:4834$768
+ attribute \src "ls180.v:4869.361-4869.434"
+ cell $xor $xor$ls180.v:4869$768
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [17]
connect \B \main_sdcore_crc7_inserter_crcreg22 [6]
- connect \Y $xor$ls180.v:4834$768_Y
+ connect \Y $xor$ls180.v:4869$768_Y
end
- attribute \src "ls180.v:4834.205-4834.278"
- cell $xor $xor$ls180.v:4834$769
+ attribute \src "ls180.v:4869.205-4869.278"
+ cell $xor $xor$ls180.v:4869$769
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [17]
connect \B \main_sdcore_crc7_inserter_crcreg22 [6]
- connect \Y $xor$ls180.v:4834$769_Y
+ connect \Y $xor$ls180.v:4869$769_Y
end
- attribute \src "ls180.v:4834.164-4834.279"
- cell $xor $xor$ls180.v:4834$770
+ attribute \src "ls180.v:4869.164-4869.279"
+ cell $xor $xor$ls180.v:4869$770
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg22 [2]
- connect \B $xor$ls180.v:4834$769_Y
- connect \Y $xor$ls180.v:4834$770_Y
+ connect \B $xor$ls180.v:4869$769_Y
+ connect \Y $xor$ls180.v:4869$770_Y
end
- attribute \src "ls180.v:4835.361-4835.434"
- cell $xor $xor$ls180.v:4835$771
+ attribute \src "ls180.v:4870.361-4870.434"
+ cell $xor $xor$ls180.v:4870$771
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [16]
connect \B \main_sdcore_crc7_inserter_crcreg23 [6]
- connect \Y $xor$ls180.v:4835$771_Y
+ connect \Y $xor$ls180.v:4870$771_Y
end
- attribute \src "ls180.v:4835.205-4835.278"
- cell $xor $xor$ls180.v:4835$772
+ attribute \src "ls180.v:4870.205-4870.278"
+ cell $xor $xor$ls180.v:4870$772
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [16]
connect \B \main_sdcore_crc7_inserter_crcreg23 [6]
- connect \Y $xor$ls180.v:4835$772_Y
+ connect \Y $xor$ls180.v:4870$772_Y
end
- attribute \src "ls180.v:4835.164-4835.279"
- cell $xor $xor$ls180.v:4835$773
+ attribute \src "ls180.v:4870.164-4870.279"
+ cell $xor $xor$ls180.v:4870$773
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg23 [2]
- connect \B $xor$ls180.v:4835$772_Y
- connect \Y $xor$ls180.v:4835$773_Y
+ connect \B $xor$ls180.v:4870$772_Y
+ connect \Y $xor$ls180.v:4870$773_Y
end
- attribute \src "ls180.v:4836.361-4836.434"
- cell $xor $xor$ls180.v:4836$774
+ attribute \src "ls180.v:4871.361-4871.434"
+ cell $xor $xor$ls180.v:4871$774
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [15]
connect \B \main_sdcore_crc7_inserter_crcreg24 [6]
- connect \Y $xor$ls180.v:4836$774_Y
+ connect \Y $xor$ls180.v:4871$774_Y
end
- attribute \src "ls180.v:4836.205-4836.278"
- cell $xor $xor$ls180.v:4836$775
+ attribute \src "ls180.v:4871.205-4871.278"
+ cell $xor $xor$ls180.v:4871$775
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [15]
connect \B \main_sdcore_crc7_inserter_crcreg24 [6]
- connect \Y $xor$ls180.v:4836$775_Y
+ connect \Y $xor$ls180.v:4871$775_Y
end
- attribute \src "ls180.v:4836.164-4836.279"
- cell $xor $xor$ls180.v:4836$776
+ attribute \src "ls180.v:4871.164-4871.279"
+ cell $xor $xor$ls180.v:4871$776
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg24 [2]
- connect \B $xor$ls180.v:4836$775_Y
- connect \Y $xor$ls180.v:4836$776_Y
+ connect \B $xor$ls180.v:4871$775_Y
+ connect \Y $xor$ls180.v:4871$776_Y
end
- attribute \src "ls180.v:4837.361-4837.434"
- cell $xor $xor$ls180.v:4837$777
+ attribute \src "ls180.v:4872.361-4872.434"
+ cell $xor $xor$ls180.v:4872$777
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [14]
connect \B \main_sdcore_crc7_inserter_crcreg25 [6]
- connect \Y $xor$ls180.v:4837$777_Y
+ connect \Y $xor$ls180.v:4872$777_Y
end
- attribute \src "ls180.v:4837.205-4837.278"
- cell $xor $xor$ls180.v:4837$778
+ attribute \src "ls180.v:4872.205-4872.278"
+ cell $xor $xor$ls180.v:4872$778
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [14]
connect \B \main_sdcore_crc7_inserter_crcreg25 [6]
- connect \Y $xor$ls180.v:4837$778_Y
+ connect \Y $xor$ls180.v:4872$778_Y
end
- attribute \src "ls180.v:4837.164-4837.279"
- cell $xor $xor$ls180.v:4837$779
+ attribute \src "ls180.v:4872.164-4872.279"
+ cell $xor $xor$ls180.v:4872$779
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg25 [2]
- connect \B $xor$ls180.v:4837$778_Y
- connect \Y $xor$ls180.v:4837$779_Y
+ connect \B $xor$ls180.v:4872$778_Y
+ connect \Y $xor$ls180.v:4872$779_Y
end
- attribute \src "ls180.v:4838.361-4838.434"
- cell $xor $xor$ls180.v:4838$780
+ attribute \src "ls180.v:4873.361-4873.434"
+ cell $xor $xor$ls180.v:4873$780
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [13]
connect \B \main_sdcore_crc7_inserter_crcreg26 [6]
- connect \Y $xor$ls180.v:4838$780_Y
+ connect \Y $xor$ls180.v:4873$780_Y
end
- attribute \src "ls180.v:4838.205-4838.278"
- cell $xor $xor$ls180.v:4838$781
+ attribute \src "ls180.v:4873.205-4873.278"
+ cell $xor $xor$ls180.v:4873$781
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [13]
connect \B \main_sdcore_crc7_inserter_crcreg26 [6]
- connect \Y $xor$ls180.v:4838$781_Y
+ connect \Y $xor$ls180.v:4873$781_Y
end
- attribute \src "ls180.v:4838.164-4838.279"
- cell $xor $xor$ls180.v:4838$782
+ attribute \src "ls180.v:4873.164-4873.279"
+ cell $xor $xor$ls180.v:4873$782
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg26 [2]
- connect \B $xor$ls180.v:4838$781_Y
- connect \Y $xor$ls180.v:4838$782_Y
+ connect \B $xor$ls180.v:4873$781_Y
+ connect \Y $xor$ls180.v:4873$782_Y
end
- attribute \src "ls180.v:4839.361-4839.434"
- cell $xor $xor$ls180.v:4839$783
+ attribute \src "ls180.v:4874.361-4874.434"
+ cell $xor $xor$ls180.v:4874$783
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [12]
connect \B \main_sdcore_crc7_inserter_crcreg27 [6]
- connect \Y $xor$ls180.v:4839$783_Y
+ connect \Y $xor$ls180.v:4874$783_Y
end
- attribute \src "ls180.v:4839.205-4839.278"
- cell $xor $xor$ls180.v:4839$784
+ attribute \src "ls180.v:4874.205-4874.278"
+ cell $xor $xor$ls180.v:4874$784
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [12]
connect \B \main_sdcore_crc7_inserter_crcreg27 [6]
- connect \Y $xor$ls180.v:4839$784_Y
+ connect \Y $xor$ls180.v:4874$784_Y
end
- attribute \src "ls180.v:4839.164-4839.279"
- cell $xor $xor$ls180.v:4839$785
+ attribute \src "ls180.v:4874.164-4874.279"
+ cell $xor $xor$ls180.v:4874$785
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg27 [2]
- connect \B $xor$ls180.v:4839$784_Y
- connect \Y $xor$ls180.v:4839$785_Y
+ connect \B $xor$ls180.v:4874$784_Y
+ connect \Y $xor$ls180.v:4874$785_Y
end
- attribute \src "ls180.v:4840.361-4840.434"
- cell $xor $xor$ls180.v:4840$786
+ attribute \src "ls180.v:4875.361-4875.434"
+ cell $xor $xor$ls180.v:4875$786
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [11]
connect \B \main_sdcore_crc7_inserter_crcreg28 [6]
- connect \Y $xor$ls180.v:4840$786_Y
+ connect \Y $xor$ls180.v:4875$786_Y
end
- attribute \src "ls180.v:4840.205-4840.278"
- cell $xor $xor$ls180.v:4840$787
+ attribute \src "ls180.v:4875.205-4875.278"
+ cell $xor $xor$ls180.v:4875$787
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [11]
connect \B \main_sdcore_crc7_inserter_crcreg28 [6]
- connect \Y $xor$ls180.v:4840$787_Y
+ connect \Y $xor$ls180.v:4875$787_Y
end
- attribute \src "ls180.v:4840.164-4840.279"
- cell $xor $xor$ls180.v:4840$788
+ attribute \src "ls180.v:4875.164-4875.279"
+ cell $xor $xor$ls180.v:4875$788
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg28 [2]
- connect \B $xor$ls180.v:4840$787_Y
- connect \Y $xor$ls180.v:4840$788_Y
+ connect \B $xor$ls180.v:4875$787_Y
+ connect \Y $xor$ls180.v:4875$788_Y
end
- attribute \src "ls180.v:4841.361-4841.434"
- cell $xor $xor$ls180.v:4841$789
+ attribute \src "ls180.v:4876.361-4876.434"
+ cell $xor $xor$ls180.v:4876$789
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [10]
connect \B \main_sdcore_crc7_inserter_crcreg29 [6]
- connect \Y $xor$ls180.v:4841$789_Y
+ connect \Y $xor$ls180.v:4876$789_Y
end
- attribute \src "ls180.v:4841.205-4841.278"
- cell $xor $xor$ls180.v:4841$790
+ attribute \src "ls180.v:4876.205-4876.278"
+ cell $xor $xor$ls180.v:4876$790
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [10]
connect \B \main_sdcore_crc7_inserter_crcreg29 [6]
- connect \Y $xor$ls180.v:4841$790_Y
+ connect \Y $xor$ls180.v:4876$790_Y
end
- attribute \src "ls180.v:4841.164-4841.279"
- cell $xor $xor$ls180.v:4841$791
+ attribute \src "ls180.v:4876.164-4876.279"
+ cell $xor $xor$ls180.v:4876$791
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg29 [2]
- connect \B $xor$ls180.v:4841$790_Y
- connect \Y $xor$ls180.v:4841$791_Y
+ connect \B $xor$ls180.v:4876$790_Y
+ connect \Y $xor$ls180.v:4876$791_Y
end
- attribute \src "ls180.v:4842.360-4842.432"
- cell $xor $xor$ls180.v:4842$792
+ attribute \src "ls180.v:4877.360-4877.432"
+ cell $xor $xor$ls180.v:4877$792
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [9]
connect \B \main_sdcore_crc7_inserter_crcreg30 [6]
- connect \Y $xor$ls180.v:4842$792_Y
+ connect \Y $xor$ls180.v:4877$792_Y
end
- attribute \src "ls180.v:4842.205-4842.277"
- cell $xor $xor$ls180.v:4842$793
+ attribute \src "ls180.v:4877.205-4877.277"
+ cell $xor $xor$ls180.v:4877$793
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [9]
connect \B \main_sdcore_crc7_inserter_crcreg30 [6]
- connect \Y $xor$ls180.v:4842$793_Y
+ connect \Y $xor$ls180.v:4877$793_Y
end
- attribute \src "ls180.v:4842.164-4842.278"
- cell $xor $xor$ls180.v:4842$794
+ attribute \src "ls180.v:4877.164-4877.278"
+ cell $xor $xor$ls180.v:4877$794
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg30 [2]
- connect \B $xor$ls180.v:4842$793_Y
- connect \Y $xor$ls180.v:4842$794_Y
+ connect \B $xor$ls180.v:4877$793_Y
+ connect \Y $xor$ls180.v:4877$794_Y
end
- attribute \src "ls180.v:4843.360-4843.432"
- cell $xor $xor$ls180.v:4843$795
+ attribute \src "ls180.v:4878.360-4878.432"
+ cell $xor $xor$ls180.v:4878$795
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [8]
connect \B \main_sdcore_crc7_inserter_crcreg31 [6]
- connect \Y $xor$ls180.v:4843$795_Y
+ connect \Y $xor$ls180.v:4878$795_Y
end
- attribute \src "ls180.v:4843.205-4843.277"
- cell $xor $xor$ls180.v:4843$796
+ attribute \src "ls180.v:4878.205-4878.277"
+ cell $xor $xor$ls180.v:4878$796
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [8]
connect \B \main_sdcore_crc7_inserter_crcreg31 [6]
- connect \Y $xor$ls180.v:4843$796_Y
+ connect \Y $xor$ls180.v:4878$796_Y
end
- attribute \src "ls180.v:4843.164-4843.278"
- cell $xor $xor$ls180.v:4843$797
+ attribute \src "ls180.v:4878.164-4878.278"
+ cell $xor $xor$ls180.v:4878$797
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg31 [2]
- connect \B $xor$ls180.v:4843$796_Y
- connect \Y $xor$ls180.v:4843$797_Y
+ connect \B $xor$ls180.v:4878$796_Y
+ connect \Y $xor$ls180.v:4878$797_Y
end
- attribute \src "ls180.v:4844.360-4844.432"
- cell $xor $xor$ls180.v:4844$798
+ attribute \src "ls180.v:4879.360-4879.432"
+ cell $xor $xor$ls180.v:4879$798
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [7]
connect \B \main_sdcore_crc7_inserter_crcreg32 [6]
- connect \Y $xor$ls180.v:4844$798_Y
+ connect \Y $xor$ls180.v:4879$798_Y
end
- attribute \src "ls180.v:4844.205-4844.277"
- cell $xor $xor$ls180.v:4844$799
+ attribute \src "ls180.v:4879.205-4879.277"
+ cell $xor $xor$ls180.v:4879$799
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [7]
connect \B \main_sdcore_crc7_inserter_crcreg32 [6]
- connect \Y $xor$ls180.v:4844$799_Y
+ connect \Y $xor$ls180.v:4879$799_Y
end
- attribute \src "ls180.v:4844.164-4844.278"
- cell $xor $xor$ls180.v:4844$800
+ attribute \src "ls180.v:4879.164-4879.278"
+ cell $xor $xor$ls180.v:4879$800
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg32 [2]
- connect \B $xor$ls180.v:4844$799_Y
- connect \Y $xor$ls180.v:4844$800_Y
+ connect \B $xor$ls180.v:4879$799_Y
+ connect \Y $xor$ls180.v:4879$800_Y
end
- attribute \src "ls180.v:4845.360-4845.432"
- cell $xor $xor$ls180.v:4845$801
+ attribute \src "ls180.v:4880.360-4880.432"
+ cell $xor $xor$ls180.v:4880$801
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [6]
connect \B \main_sdcore_crc7_inserter_crcreg33 [6]
- connect \Y $xor$ls180.v:4845$801_Y
+ connect \Y $xor$ls180.v:4880$801_Y
end
- attribute \src "ls180.v:4845.205-4845.277"
- cell $xor $xor$ls180.v:4845$802
+ attribute \src "ls180.v:4880.205-4880.277"
+ cell $xor $xor$ls180.v:4880$802
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [6]
connect \B \main_sdcore_crc7_inserter_crcreg33 [6]
- connect \Y $xor$ls180.v:4845$802_Y
+ connect \Y $xor$ls180.v:4880$802_Y
end
- attribute \src "ls180.v:4845.164-4845.278"
- cell $xor $xor$ls180.v:4845$803
+ attribute \src "ls180.v:4880.164-4880.278"
+ cell $xor $xor$ls180.v:4880$803
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg33 [2]
- connect \B $xor$ls180.v:4845$802_Y
- connect \Y $xor$ls180.v:4845$803_Y
+ connect \B $xor$ls180.v:4880$802_Y
+ connect \Y $xor$ls180.v:4880$803_Y
end
- attribute \src "ls180.v:4846.360-4846.432"
- cell $xor $xor$ls180.v:4846$804
+ attribute \src "ls180.v:4881.360-4881.432"
+ cell $xor $xor$ls180.v:4881$804
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [5]
connect \B \main_sdcore_crc7_inserter_crcreg34 [6]
- connect \Y $xor$ls180.v:4846$804_Y
+ connect \Y $xor$ls180.v:4881$804_Y
end
- attribute \src "ls180.v:4846.205-4846.277"
- cell $xor $xor$ls180.v:4846$805
+ attribute \src "ls180.v:4881.205-4881.277"
+ cell $xor $xor$ls180.v:4881$805
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [5]
connect \B \main_sdcore_crc7_inserter_crcreg34 [6]
- connect \Y $xor$ls180.v:4846$805_Y
+ connect \Y $xor$ls180.v:4881$805_Y
end
- attribute \src "ls180.v:4846.164-4846.278"
- cell $xor $xor$ls180.v:4846$806
+ attribute \src "ls180.v:4881.164-4881.278"
+ cell $xor $xor$ls180.v:4881$806
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg34 [2]
- connect \B $xor$ls180.v:4846$805_Y
- connect \Y $xor$ls180.v:4846$806_Y
+ connect \B $xor$ls180.v:4881$805_Y
+ connect \Y $xor$ls180.v:4881$806_Y
end
- attribute \src "ls180.v:4847.360-4847.432"
- cell $xor $xor$ls180.v:4847$807
+ attribute \src "ls180.v:4882.360-4882.432"
+ cell $xor $xor$ls180.v:4882$807
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [4]
connect \B \main_sdcore_crc7_inserter_crcreg35 [6]
- connect \Y $xor$ls180.v:4847$807_Y
+ connect \Y $xor$ls180.v:4882$807_Y
end
- attribute \src "ls180.v:4847.205-4847.277"
- cell $xor $xor$ls180.v:4847$808
+ attribute \src "ls180.v:4882.205-4882.277"
+ cell $xor $xor$ls180.v:4882$808
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [4]
connect \B \main_sdcore_crc7_inserter_crcreg35 [6]
- connect \Y $xor$ls180.v:4847$808_Y
+ connect \Y $xor$ls180.v:4882$808_Y
end
- attribute \src "ls180.v:4847.164-4847.278"
- cell $xor $xor$ls180.v:4847$809
+ attribute \src "ls180.v:4882.164-4882.278"
+ cell $xor $xor$ls180.v:4882$809
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg35 [2]
- connect \B $xor$ls180.v:4847$808_Y
- connect \Y $xor$ls180.v:4847$809_Y
+ connect \B $xor$ls180.v:4882$808_Y
+ connect \Y $xor$ls180.v:4882$809_Y
end
- attribute \src "ls180.v:4848.360-4848.432"
- cell $xor $xor$ls180.v:4848$810
+ attribute \src "ls180.v:4883.360-4883.432"
+ cell $xor $xor$ls180.v:4883$810
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [3]
connect \B \main_sdcore_crc7_inserter_crcreg36 [6]
- connect \Y $xor$ls180.v:4848$810_Y
+ connect \Y $xor$ls180.v:4883$810_Y
end
- attribute \src "ls180.v:4848.205-4848.277"
- cell $xor $xor$ls180.v:4848$811
+ attribute \src "ls180.v:4883.205-4883.277"
+ cell $xor $xor$ls180.v:4883$811
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [3]
connect \B \main_sdcore_crc7_inserter_crcreg36 [6]
- connect \Y $xor$ls180.v:4848$811_Y
+ connect \Y $xor$ls180.v:4883$811_Y
end
- attribute \src "ls180.v:4848.164-4848.278"
- cell $xor $xor$ls180.v:4848$812
+ attribute \src "ls180.v:4883.164-4883.278"
+ cell $xor $xor$ls180.v:4883$812
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg36 [2]
- connect \B $xor$ls180.v:4848$811_Y
- connect \Y $xor$ls180.v:4848$812_Y
+ connect \B $xor$ls180.v:4883$811_Y
+ connect \Y $xor$ls180.v:4883$812_Y
end
- attribute \src "ls180.v:4849.360-4849.432"
- cell $xor $xor$ls180.v:4849$813
+ attribute \src "ls180.v:4884.360-4884.432"
+ cell $xor $xor$ls180.v:4884$813
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [2]
connect \B \main_sdcore_crc7_inserter_crcreg37 [6]
- connect \Y $xor$ls180.v:4849$813_Y
+ connect \Y $xor$ls180.v:4884$813_Y
end
- attribute \src "ls180.v:4849.205-4849.277"
- cell $xor $xor$ls180.v:4849$814
+ attribute \src "ls180.v:4884.205-4884.277"
+ cell $xor $xor$ls180.v:4884$814
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [2]
connect \B \main_sdcore_crc7_inserter_crcreg37 [6]
- connect \Y $xor$ls180.v:4849$814_Y
+ connect \Y $xor$ls180.v:4884$814_Y
end
- attribute \src "ls180.v:4849.164-4849.278"
- cell $xor $xor$ls180.v:4849$815
+ attribute \src "ls180.v:4884.164-4884.278"
+ cell $xor $xor$ls180.v:4884$815
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg37 [2]
- connect \B $xor$ls180.v:4849$814_Y
- connect \Y $xor$ls180.v:4849$815_Y
+ connect \B $xor$ls180.v:4884$814_Y
+ connect \Y $xor$ls180.v:4884$815_Y
end
- attribute \src "ls180.v:4850.360-4850.432"
- cell $xor $xor$ls180.v:4850$816
+ attribute \src "ls180.v:4885.360-4885.432"
+ cell $xor $xor$ls180.v:4885$816
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [1]
connect \B \main_sdcore_crc7_inserter_crcreg38 [6]
- connect \Y $xor$ls180.v:4850$816_Y
+ connect \Y $xor$ls180.v:4885$816_Y
end
- attribute \src "ls180.v:4850.205-4850.277"
- cell $xor $xor$ls180.v:4850$817
+ attribute \src "ls180.v:4885.205-4885.277"
+ cell $xor $xor$ls180.v:4885$817
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [1]
connect \B \main_sdcore_crc7_inserter_crcreg38 [6]
- connect \Y $xor$ls180.v:4850$817_Y
+ connect \Y $xor$ls180.v:4885$817_Y
end
- attribute \src "ls180.v:4850.164-4850.278"
- cell $xor $xor$ls180.v:4850$818
+ attribute \src "ls180.v:4885.164-4885.278"
+ cell $xor $xor$ls180.v:4885$818
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg38 [2]
- connect \B $xor$ls180.v:4850$817_Y
- connect \Y $xor$ls180.v:4850$818_Y
+ connect \B $xor$ls180.v:4885$817_Y
+ connect \Y $xor$ls180.v:4885$818_Y
end
- attribute \src "ls180.v:4851.360-4851.432"
- cell $xor $xor$ls180.v:4851$819
+ attribute \src "ls180.v:4886.360-4886.432"
+ cell $xor $xor$ls180.v:4886$819
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [0]
connect \B \main_sdcore_crc7_inserter_crcreg39 [6]
- connect \Y $xor$ls180.v:4851$819_Y
+ connect \Y $xor$ls180.v:4886$819_Y
end
- attribute \src "ls180.v:4851.205-4851.277"
- cell $xor $xor$ls180.v:4851$820
+ attribute \src "ls180.v:4886.205-4886.277"
+ cell $xor $xor$ls180.v:4886$820
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_val [0]
connect \B \main_sdcore_crc7_inserter_crcreg39 [6]
- connect \Y $xor$ls180.v:4851$820_Y
+ connect \Y $xor$ls180.v:4886$820_Y
end
- attribute \src "ls180.v:4851.164-4851.278"
- cell $xor $xor$ls180.v:4851$821
+ attribute \src "ls180.v:4886.164-4886.278"
+ cell $xor $xor$ls180.v:4886$821
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc7_inserter_crcreg39 [2]
- connect \B $xor$ls180.v:4851$820_Y
- connect \Y $xor$ls180.v:4851$821_Y
+ connect \B $xor$ls180.v:4886$820_Y
+ connect \Y $xor$ls180.v:4886$821_Y
end
- attribute \src "ls180.v:4872.899-4872.983"
- cell $xor $xor$ls180.v:4872$835
+ attribute \src "ls180.v:4907.899-4907.983"
+ cell $xor $xor$ls180.v:4907$835
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_val [1]
connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15]
- connect \Y $xor$ls180.v:4872$835_Y
+ connect \Y $xor$ls180.v:4907$835_Y
end
- attribute \src "ls180.v:4872.634-4872.718"
- cell $xor $xor$ls180.v:4872$836
+ attribute \src "ls180.v:4907.634-4907.718"
+ cell $xor $xor$ls180.v:4907$836
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_val [1]
connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15]
- connect \Y $xor$ls180.v:4872$836_Y
+ connect \Y $xor$ls180.v:4907$836_Y
end
- attribute \src "ls180.v:4872.588-4872.719"
- cell $xor $xor$ls180.v:4872$837
+ attribute \src "ls180.v:4907.588-4907.719"
+ cell $xor $xor$ls180.v:4907$837
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4]
- connect \B $xor$ls180.v:4872$836_Y
- connect \Y $xor$ls180.v:4872$837_Y
+ connect \B $xor$ls180.v:4907$836_Y
+ connect \Y $xor$ls180.v:4907$837_Y
end
- attribute \src "ls180.v:4872.234-4872.318"
- cell $xor $xor$ls180.v:4872$838
+ attribute \src "ls180.v:4907.234-4907.318"
+ cell $xor $xor$ls180.v:4907$838
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_val [1]
connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15]
- connect \Y $xor$ls180.v:4872$838_Y
+ connect \Y $xor$ls180.v:4907$838_Y
end
- attribute \src "ls180.v:4872.187-4872.319"
- cell $xor $xor$ls180.v:4872$839
+ attribute \src "ls180.v:4907.187-4907.319"
+ cell $xor $xor$ls180.v:4907$839
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11]
- connect \B $xor$ls180.v:4872$838_Y
- connect \Y $xor$ls180.v:4872$839_Y
+ connect \B $xor$ls180.v:4907$838_Y
+ connect \Y $xor$ls180.v:4907$839_Y
end
- attribute \src "ls180.v:4873.899-4873.983"
- cell $xor $xor$ls180.v:4873$840
+ attribute \src "ls180.v:4908.899-4908.983"
+ cell $xor $xor$ls180.v:4908$840
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_val [0]
connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15]
- connect \Y $xor$ls180.v:4873$840_Y
+ connect \Y $xor$ls180.v:4908$840_Y
end
- attribute \src "ls180.v:4873.634-4873.718"
- cell $xor $xor$ls180.v:4873$841
+ attribute \src "ls180.v:4908.634-4908.718"
+ cell $xor $xor$ls180.v:4908$841
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_val [0]
connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15]
- connect \Y $xor$ls180.v:4873$841_Y
+ connect \Y $xor$ls180.v:4908$841_Y
end
- attribute \src "ls180.v:4873.588-4873.719"
- cell $xor $xor$ls180.v:4873$842
+ attribute \src "ls180.v:4908.588-4908.719"
+ cell $xor $xor$ls180.v:4908$842
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4]
- connect \B $xor$ls180.v:4873$841_Y
- connect \Y $xor$ls180.v:4873$842_Y
+ connect \B $xor$ls180.v:4908$841_Y
+ connect \Y $xor$ls180.v:4908$842_Y
end
- attribute \src "ls180.v:4873.234-4873.318"
- cell $xor $xor$ls180.v:4873$843
+ attribute \src "ls180.v:4908.234-4908.318"
+ cell $xor $xor$ls180.v:4908$843
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_val [0]
connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15]
- connect \Y $xor$ls180.v:4873$843_Y
+ connect \Y $xor$ls180.v:4908$843_Y
end
- attribute \src "ls180.v:4873.187-4873.319"
- cell $xor $xor$ls180.v:4873$844
+ attribute \src "ls180.v:4908.187-4908.319"
+ cell $xor $xor$ls180.v:4908$844
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11]
- connect \B $xor$ls180.v:4873$843_Y
- connect \Y $xor$ls180.v:4873$844_Y
+ connect \B $xor$ls180.v:4908$843_Y
+ connect \Y $xor$ls180.v:4908$844_Y
end
- attribute \src "ls180.v:4882.899-4882.983"
- cell $xor $xor$ls180.v:4882$846
+ attribute \src "ls180.v:4917.899-4917.983"
+ cell $xor $xor$ls180.v:4917$846
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_val [1]
connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15]
- connect \Y $xor$ls180.v:4882$846_Y
+ connect \Y $xor$ls180.v:4917$846_Y
end
- attribute \src "ls180.v:4882.634-4882.718"
- cell $xor $xor$ls180.v:4882$847
+ attribute \src "ls180.v:4917.634-4917.718"
+ cell $xor $xor$ls180.v:4917$847
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_val [1]
connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15]
- connect \Y $xor$ls180.v:4882$847_Y
+ connect \Y $xor$ls180.v:4917$847_Y
end
- attribute \src "ls180.v:4882.588-4882.719"
- cell $xor $xor$ls180.v:4882$848
+ attribute \src "ls180.v:4917.588-4917.719"
+ cell $xor $xor$ls180.v:4917$848
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4]
- connect \B $xor$ls180.v:4882$847_Y
- connect \Y $xor$ls180.v:4882$848_Y
+ connect \B $xor$ls180.v:4917$847_Y
+ connect \Y $xor$ls180.v:4917$848_Y
end
- attribute \src "ls180.v:4882.234-4882.318"
- cell $xor $xor$ls180.v:4882$849
+ attribute \src "ls180.v:4917.234-4917.318"
+ cell $xor $xor$ls180.v:4917$849
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_val [1]
connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15]
- connect \Y $xor$ls180.v:4882$849_Y
+ connect \Y $xor$ls180.v:4917$849_Y
end
- attribute \src "ls180.v:4882.187-4882.319"
- cell $xor $xor$ls180.v:4882$850
+ attribute \src "ls180.v:4917.187-4917.319"
+ cell $xor $xor$ls180.v:4917$850
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11]
- connect \B $xor$ls180.v:4882$849_Y
- connect \Y $xor$ls180.v:4882$850_Y
+ connect \B $xor$ls180.v:4917$849_Y
+ connect \Y $xor$ls180.v:4917$850_Y
end
- attribute \src "ls180.v:4883.899-4883.983"
- cell $xor $xor$ls180.v:4883$851
+ attribute \src "ls180.v:4918.899-4918.983"
+ cell $xor $xor$ls180.v:4918$851
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_val [0]
connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15]
- connect \Y $xor$ls180.v:4883$851_Y
+ connect \Y $xor$ls180.v:4918$851_Y
end
- attribute \src "ls180.v:4883.634-4883.718"
- cell $xor $xor$ls180.v:4883$852
+ attribute \src "ls180.v:4918.634-4918.718"
+ cell $xor $xor$ls180.v:4918$852
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_val [0]
connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15]
- connect \Y $xor$ls180.v:4883$852_Y
+ connect \Y $xor$ls180.v:4918$852_Y
end
- attribute \src "ls180.v:4883.588-4883.719"
- cell $xor $xor$ls180.v:4883$853
+ attribute \src "ls180.v:4918.588-4918.719"
+ cell $xor $xor$ls180.v:4918$853
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4]
- connect \B $xor$ls180.v:4883$852_Y
- connect \Y $xor$ls180.v:4883$853_Y
+ connect \B $xor$ls180.v:4918$852_Y
+ connect \Y $xor$ls180.v:4918$853_Y
end
- attribute \src "ls180.v:4883.234-4883.318"
- cell $xor $xor$ls180.v:4883$854
+ attribute \src "ls180.v:4918.234-4918.318"
+ cell $xor $xor$ls180.v:4918$854
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_val [0]
connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15]
- connect \Y $xor$ls180.v:4883$854_Y
+ connect \Y $xor$ls180.v:4918$854_Y
end
- attribute \src "ls180.v:4883.187-4883.319"
- cell $xor $xor$ls180.v:4883$855
+ attribute \src "ls180.v:4918.187-4918.319"
+ cell $xor $xor$ls180.v:4918$855
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11]
- connect \B $xor$ls180.v:4883$854_Y
- connect \Y $xor$ls180.v:4883$855_Y
+ connect \B $xor$ls180.v:4918$854_Y
+ connect \Y $xor$ls180.v:4918$855_Y
end
- attribute \src "ls180.v:4892.899-4892.983"
- cell $xor $xor$ls180.v:4892$857
+ attribute \src "ls180.v:4927.899-4927.983"
+ cell $xor $xor$ls180.v:4927$857
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_val [1]
connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15]
- connect \Y $xor$ls180.v:4892$857_Y
+ connect \Y $xor$ls180.v:4927$857_Y
end
- attribute \src "ls180.v:4892.634-4892.718"
- cell $xor $xor$ls180.v:4892$858
+ attribute \src "ls180.v:4927.634-4927.718"
+ cell $xor $xor$ls180.v:4927$858
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_val [1]
connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15]
- connect \Y $xor$ls180.v:4892$858_Y
+ connect \Y $xor$ls180.v:4927$858_Y
end
- attribute \src "ls180.v:4892.588-4892.719"
- cell $xor $xor$ls180.v:4892$859
+ attribute \src "ls180.v:4927.588-4927.719"
+ cell $xor $xor$ls180.v:4927$859
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4]
- connect \B $xor$ls180.v:4892$858_Y
- connect \Y $xor$ls180.v:4892$859_Y
+ connect \B $xor$ls180.v:4927$858_Y
+ connect \Y $xor$ls180.v:4927$859_Y
end
- attribute \src "ls180.v:4892.234-4892.318"
- cell $xor $xor$ls180.v:4892$860
+ attribute \src "ls180.v:4927.234-4927.318"
+ cell $xor $xor$ls180.v:4927$860
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_val [1]
connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15]
- connect \Y $xor$ls180.v:4892$860_Y
+ connect \Y $xor$ls180.v:4927$860_Y
end
- attribute \src "ls180.v:4892.187-4892.319"
- cell $xor $xor$ls180.v:4892$861
+ attribute \src "ls180.v:4927.187-4927.319"
+ cell $xor $xor$ls180.v:4927$861
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11]
- connect \B $xor$ls180.v:4892$860_Y
- connect \Y $xor$ls180.v:4892$861_Y
+ connect \B $xor$ls180.v:4927$860_Y
+ connect \Y $xor$ls180.v:4927$861_Y
end
- attribute \src "ls180.v:4893.899-4893.983"
- cell $xor $xor$ls180.v:4893$862
+ attribute \src "ls180.v:4928.899-4928.983"
+ cell $xor $xor$ls180.v:4928$862
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_val [0]
connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15]
- connect \Y $xor$ls180.v:4893$862_Y
+ connect \Y $xor$ls180.v:4928$862_Y
end
- attribute \src "ls180.v:4893.634-4893.718"
- cell $xor $xor$ls180.v:4893$863
+ attribute \src "ls180.v:4928.634-4928.718"
+ cell $xor $xor$ls180.v:4928$863
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_val [0]
connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15]
- connect \Y $xor$ls180.v:4893$863_Y
+ connect \Y $xor$ls180.v:4928$863_Y
end
- attribute \src "ls180.v:4893.588-4893.719"
- cell $xor $xor$ls180.v:4893$864
+ attribute \src "ls180.v:4928.588-4928.719"
+ cell $xor $xor$ls180.v:4928$864
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4]
- connect \B $xor$ls180.v:4893$863_Y
- connect \Y $xor$ls180.v:4893$864_Y
+ connect \B $xor$ls180.v:4928$863_Y
+ connect \Y $xor$ls180.v:4928$864_Y
end
- attribute \src "ls180.v:4893.234-4893.318"
- cell $xor $xor$ls180.v:4893$865
+ attribute \src "ls180.v:4928.234-4928.318"
+ cell $xor $xor$ls180.v:4928$865
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_val [0]
connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15]
- connect \Y $xor$ls180.v:4893$865_Y
+ connect \Y $xor$ls180.v:4928$865_Y
end
- attribute \src "ls180.v:4893.187-4893.319"
- cell $xor $xor$ls180.v:4893$866
+ attribute \src "ls180.v:4928.187-4928.319"
+ cell $xor $xor$ls180.v:4928$866
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11]
- connect \B $xor$ls180.v:4893$865_Y
- connect \Y $xor$ls180.v:4893$866_Y
+ connect \B $xor$ls180.v:4928$865_Y
+ connect \Y $xor$ls180.v:4928$866_Y
end
- attribute \src "ls180.v:4902.899-4902.983"
- cell $xor $xor$ls180.v:4902$868
+ attribute \src "ls180.v:4937.899-4937.983"
+ cell $xor $xor$ls180.v:4937$868
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_val [1]
connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15]
- connect \Y $xor$ls180.v:4902$868_Y
+ connect \Y $xor$ls180.v:4937$868_Y
end
- attribute \src "ls180.v:4902.634-4902.718"
- cell $xor $xor$ls180.v:4902$869
+ attribute \src "ls180.v:4937.634-4937.718"
+ cell $xor $xor$ls180.v:4937$869
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_val [1]
connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15]
- connect \Y $xor$ls180.v:4902$869_Y
+ connect \Y $xor$ls180.v:4937$869_Y
end
- attribute \src "ls180.v:4902.588-4902.719"
- cell $xor $xor$ls180.v:4902$870
+ attribute \src "ls180.v:4937.588-4937.719"
+ cell $xor $xor$ls180.v:4937$870
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4]
- connect \B $xor$ls180.v:4902$869_Y
- connect \Y $xor$ls180.v:4902$870_Y
+ connect \B $xor$ls180.v:4937$869_Y
+ connect \Y $xor$ls180.v:4937$870_Y
end
- attribute \src "ls180.v:4902.234-4902.318"
- cell $xor $xor$ls180.v:4902$871
+ attribute \src "ls180.v:4937.234-4937.318"
+ cell $xor $xor$ls180.v:4937$871
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_val [1]
connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15]
- connect \Y $xor$ls180.v:4902$871_Y
+ connect \Y $xor$ls180.v:4937$871_Y
end
- attribute \src "ls180.v:4902.187-4902.319"
- cell $xor $xor$ls180.v:4902$872
+ attribute \src "ls180.v:4937.187-4937.319"
+ cell $xor $xor$ls180.v:4937$872
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11]
- connect \B $xor$ls180.v:4902$871_Y
- connect \Y $xor$ls180.v:4902$872_Y
+ connect \B $xor$ls180.v:4937$871_Y
+ connect \Y $xor$ls180.v:4937$872_Y
end
- attribute \src "ls180.v:4903.899-4903.983"
- cell $xor $xor$ls180.v:4903$873
+ attribute \src "ls180.v:4938.899-4938.983"
+ cell $xor $xor$ls180.v:4938$873
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_val [0]
connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15]
- connect \Y $xor$ls180.v:4903$873_Y
+ connect \Y $xor$ls180.v:4938$873_Y
end
- attribute \src "ls180.v:4903.634-4903.718"
- cell $xor $xor$ls180.v:4903$874
+ attribute \src "ls180.v:4938.634-4938.718"
+ cell $xor $xor$ls180.v:4938$874
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_val [0]
connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15]
- connect \Y $xor$ls180.v:4903$874_Y
+ connect \Y $xor$ls180.v:4938$874_Y
end
- attribute \src "ls180.v:4903.588-4903.719"
- cell $xor $xor$ls180.v:4903$875
+ attribute \src "ls180.v:4938.588-4938.719"
+ cell $xor $xor$ls180.v:4938$875
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4]
- connect \B $xor$ls180.v:4903$874_Y
- connect \Y $xor$ls180.v:4903$875_Y
+ connect \B $xor$ls180.v:4938$874_Y
+ connect \Y $xor$ls180.v:4938$875_Y
end
- attribute \src "ls180.v:4903.234-4903.318"
- cell $xor $xor$ls180.v:4903$876
+ attribute \src "ls180.v:4938.234-4938.318"
+ cell $xor $xor$ls180.v:4938$876
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_val [0]
connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15]
- connect \Y $xor$ls180.v:4903$876_Y
+ connect \Y $xor$ls180.v:4938$876_Y
end
- attribute \src "ls180.v:4903.187-4903.319"
- cell $xor $xor$ls180.v:4903$877
+ attribute \src "ls180.v:4938.187-4938.319"
+ cell $xor $xor$ls180.v:4938$877
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11]
- connect \B $xor$ls180.v:4903$876_Y
- connect \Y $xor$ls180.v:4903$877_Y
+ connect \B $xor$ls180.v:4938$876_Y
+ connect \Y $xor$ls180.v:4938$877_Y
end
- attribute \src "ls180.v:5054.879-5054.961"
- cell $xor $xor$ls180.v:5054$910
+ attribute \src "ls180.v:5089.879-5089.961"
+ cell $xor $xor$ls180.v:5089$910
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_val [1]
connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15]
- connect \Y $xor$ls180.v:5054$910_Y
+ connect \Y $xor$ls180.v:5089$910_Y
end
- attribute \src "ls180.v:5054.620-5054.702"
- cell $xor $xor$ls180.v:5054$911
+ attribute \src "ls180.v:5089.620-5089.702"
+ cell $xor $xor$ls180.v:5089$911
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_val [1]
connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15]
- connect \Y $xor$ls180.v:5054$911_Y
+ connect \Y $xor$ls180.v:5089$911_Y
end
- attribute \src "ls180.v:5054.575-5054.703"
- cell $xor $xor$ls180.v:5054$912
+ attribute \src "ls180.v:5089.575-5089.703"
+ cell $xor $xor$ls180.v:5089$912
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4]
- connect \B $xor$ls180.v:5054$911_Y
- connect \Y $xor$ls180.v:5054$912_Y
+ connect \B $xor$ls180.v:5089$911_Y
+ connect \Y $xor$ls180.v:5089$912_Y
end
- attribute \src "ls180.v:5054.229-5054.311"
- cell $xor $xor$ls180.v:5054$913
+ attribute \src "ls180.v:5089.229-5089.311"
+ cell $xor $xor$ls180.v:5089$913
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_val [1]
connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15]
- connect \Y $xor$ls180.v:5054$913_Y
+ connect \Y $xor$ls180.v:5089$913_Y
end
- attribute \src "ls180.v:5054.183-5054.312"
- cell $xor $xor$ls180.v:5054$914
+ attribute \src "ls180.v:5089.183-5089.312"
+ cell $xor $xor$ls180.v:5089$914
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11]
- connect \B $xor$ls180.v:5054$913_Y
- connect \Y $xor$ls180.v:5054$914_Y
+ connect \B $xor$ls180.v:5089$913_Y
+ connect \Y $xor$ls180.v:5089$914_Y
end
- attribute \src "ls180.v:5055.879-5055.961"
- cell $xor $xor$ls180.v:5055$915
+ attribute \src "ls180.v:5090.879-5090.961"
+ cell $xor $xor$ls180.v:5090$915
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_val [0]
connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15]
- connect \Y $xor$ls180.v:5055$915_Y
+ connect \Y $xor$ls180.v:5090$915_Y
end
- attribute \src "ls180.v:5055.620-5055.702"
- cell $xor $xor$ls180.v:5055$916
+ attribute \src "ls180.v:5090.620-5090.702"
+ cell $xor $xor$ls180.v:5090$916
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_val [0]
connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15]
- connect \Y $xor$ls180.v:5055$916_Y
+ connect \Y $xor$ls180.v:5090$916_Y
end
- attribute \src "ls180.v:5055.575-5055.703"
- cell $xor $xor$ls180.v:5055$917
+ attribute \src "ls180.v:5090.575-5090.703"
+ cell $xor $xor$ls180.v:5090$917
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4]
- connect \B $xor$ls180.v:5055$916_Y
- connect \Y $xor$ls180.v:5055$917_Y
+ connect \B $xor$ls180.v:5090$916_Y
+ connect \Y $xor$ls180.v:5090$917_Y
end
- attribute \src "ls180.v:5055.229-5055.311"
- cell $xor $xor$ls180.v:5055$918
+ attribute \src "ls180.v:5090.229-5090.311"
+ cell $xor $xor$ls180.v:5090$918
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_val [0]
connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15]
- connect \Y $xor$ls180.v:5055$918_Y
+ connect \Y $xor$ls180.v:5090$918_Y
end
- attribute \src "ls180.v:5055.183-5055.312"
- cell $xor $xor$ls180.v:5055$919
+ attribute \src "ls180.v:5090.183-5090.312"
+ cell $xor $xor$ls180.v:5090$919
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11]
- connect \B $xor$ls180.v:5055$918_Y
- connect \Y $xor$ls180.v:5055$919_Y
+ connect \B $xor$ls180.v:5090$918_Y
+ connect \Y $xor$ls180.v:5090$919_Y
end
- attribute \src "ls180.v:5064.879-5064.961"
- cell $xor $xor$ls180.v:5064$921
+ attribute \src "ls180.v:5099.879-5099.961"
+ cell $xor $xor$ls180.v:5099$921
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_val [1]
connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15]
- connect \Y $xor$ls180.v:5064$921_Y
+ connect \Y $xor$ls180.v:5099$921_Y
end
- attribute \src "ls180.v:5064.620-5064.702"
- cell $xor $xor$ls180.v:5064$922
+ attribute \src "ls180.v:5099.620-5099.702"
+ cell $xor $xor$ls180.v:5099$922
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_val [1]
connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15]
- connect \Y $xor$ls180.v:5064$922_Y
+ connect \Y $xor$ls180.v:5099$922_Y
end
- attribute \src "ls180.v:5064.575-5064.703"
- cell $xor $xor$ls180.v:5064$923
+ attribute \src "ls180.v:5099.575-5099.703"
+ cell $xor $xor$ls180.v:5099$923
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4]
- connect \B $xor$ls180.v:5064$922_Y
- connect \Y $xor$ls180.v:5064$923_Y
+ connect \B $xor$ls180.v:5099$922_Y
+ connect \Y $xor$ls180.v:5099$923_Y
end
- attribute \src "ls180.v:5064.229-5064.311"
- cell $xor $xor$ls180.v:5064$924
+ attribute \src "ls180.v:5099.229-5099.311"
+ cell $xor $xor$ls180.v:5099$924
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_val [1]
connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15]
- connect \Y $xor$ls180.v:5064$924_Y
+ connect \Y $xor$ls180.v:5099$924_Y
end
- attribute \src "ls180.v:5064.183-5064.312"
- cell $xor $xor$ls180.v:5064$925
+ attribute \src "ls180.v:5099.183-5099.312"
+ cell $xor $xor$ls180.v:5099$925
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11]
- connect \B $xor$ls180.v:5064$924_Y
- connect \Y $xor$ls180.v:5064$925_Y
+ connect \B $xor$ls180.v:5099$924_Y
+ connect \Y $xor$ls180.v:5099$925_Y
end
- attribute \src "ls180.v:5065.879-5065.961"
- cell $xor $xor$ls180.v:5065$926
+ attribute \src "ls180.v:5100.879-5100.961"
+ cell $xor $xor$ls180.v:5100$926
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_val [0]
connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15]
- connect \Y $xor$ls180.v:5065$926_Y
+ connect \Y $xor$ls180.v:5100$926_Y
end
- attribute \src "ls180.v:5065.620-5065.702"
- cell $xor $xor$ls180.v:5065$927
+ attribute \src "ls180.v:5100.620-5100.702"
+ cell $xor $xor$ls180.v:5100$927
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_val [0]
connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15]
- connect \Y $xor$ls180.v:5065$927_Y
+ connect \Y $xor$ls180.v:5100$927_Y
end
- attribute \src "ls180.v:5065.575-5065.703"
- cell $xor $xor$ls180.v:5065$928
+ attribute \src "ls180.v:5100.575-5100.703"
+ cell $xor $xor$ls180.v:5100$928
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4]
- connect \B $xor$ls180.v:5065$927_Y
- connect \Y $xor$ls180.v:5065$928_Y
+ connect \B $xor$ls180.v:5100$927_Y
+ connect \Y $xor$ls180.v:5100$928_Y
end
- attribute \src "ls180.v:5065.229-5065.311"
- cell $xor $xor$ls180.v:5065$929
+ attribute \src "ls180.v:5100.229-5100.311"
+ cell $xor $xor$ls180.v:5100$929
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_val [0]
connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15]
- connect \Y $xor$ls180.v:5065$929_Y
+ connect \Y $xor$ls180.v:5100$929_Y
end
- attribute \src "ls180.v:5065.183-5065.312"
- cell $xor $xor$ls180.v:5065$930
+ attribute \src "ls180.v:5100.183-5100.312"
+ cell $xor $xor$ls180.v:5100$930
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11]
- connect \B $xor$ls180.v:5065$929_Y
- connect \Y $xor$ls180.v:5065$930_Y
+ connect \B $xor$ls180.v:5100$929_Y
+ connect \Y $xor$ls180.v:5100$930_Y
end
- attribute \src "ls180.v:5074.879-5074.961"
- cell $xor $xor$ls180.v:5074$932
+ attribute \src "ls180.v:5109.879-5109.961"
+ cell $xor $xor$ls180.v:5109$932
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_val [1]
connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15]
- connect \Y $xor$ls180.v:5074$932_Y
+ connect \Y $xor$ls180.v:5109$932_Y
end
- attribute \src "ls180.v:5074.620-5074.702"
- cell $xor $xor$ls180.v:5074$933
+ attribute \src "ls180.v:5109.620-5109.702"
+ cell $xor $xor$ls180.v:5109$933
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_val [1]
connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15]
- connect \Y $xor$ls180.v:5074$933_Y
+ connect \Y $xor$ls180.v:5109$933_Y
end
- attribute \src "ls180.v:5074.575-5074.703"
- cell $xor $xor$ls180.v:5074$934
+ attribute \src "ls180.v:5109.575-5109.703"
+ cell $xor $xor$ls180.v:5109$934
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4]
- connect \B $xor$ls180.v:5074$933_Y
- connect \Y $xor$ls180.v:5074$934_Y
+ connect \B $xor$ls180.v:5109$933_Y
+ connect \Y $xor$ls180.v:5109$934_Y
end
- attribute \src "ls180.v:5074.229-5074.311"
- cell $xor $xor$ls180.v:5074$935
+ attribute \src "ls180.v:5109.229-5109.311"
+ cell $xor $xor$ls180.v:5109$935
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_val [1]
connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15]
- connect \Y $xor$ls180.v:5074$935_Y
+ connect \Y $xor$ls180.v:5109$935_Y
end
- attribute \src "ls180.v:5074.183-5074.312"
- cell $xor $xor$ls180.v:5074$936
+ attribute \src "ls180.v:5109.183-5109.312"
+ cell $xor $xor$ls180.v:5109$936
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11]
- connect \B $xor$ls180.v:5074$935_Y
- connect \Y $xor$ls180.v:5074$936_Y
+ connect \B $xor$ls180.v:5109$935_Y
+ connect \Y $xor$ls180.v:5109$936_Y
end
- attribute \src "ls180.v:5075.879-5075.961"
- cell $xor $xor$ls180.v:5075$937
+ attribute \src "ls180.v:5110.879-5110.961"
+ cell $xor $xor$ls180.v:5110$937
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_val [0]
connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
- connect \Y $xor$ls180.v:5075$937_Y
+ connect \Y $xor$ls180.v:5110$937_Y
end
- attribute \src "ls180.v:5075.620-5075.702"
- cell $xor $xor$ls180.v:5075$938
+ attribute \src "ls180.v:5110.620-5110.702"
+ cell $xor $xor$ls180.v:5110$938
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_val [0]
connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
- connect \Y $xor$ls180.v:5075$938_Y
+ connect \Y $xor$ls180.v:5110$938_Y
end
- attribute \src "ls180.v:5075.575-5075.703"
- cell $xor $xor$ls180.v:5075$939
+ attribute \src "ls180.v:5110.575-5110.703"
+ cell $xor $xor$ls180.v:5110$939
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4]
- connect \B $xor$ls180.v:5075$938_Y
- connect \Y $xor$ls180.v:5075$939_Y
+ connect \B $xor$ls180.v:5110$938_Y
+ connect \Y $xor$ls180.v:5110$939_Y
end
- attribute \src "ls180.v:5075.229-5075.311"
- cell $xor $xor$ls180.v:5075$940
+ attribute \src "ls180.v:5110.229-5110.311"
+ cell $xor $xor$ls180.v:5110$940
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_val [0]
connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
- connect \Y $xor$ls180.v:5075$940_Y
+ connect \Y $xor$ls180.v:5110$940_Y
end
- attribute \src "ls180.v:5075.183-5075.312"
- cell $xor $xor$ls180.v:5075$941
+ attribute \src "ls180.v:5110.183-5110.312"
+ cell $xor $xor$ls180.v:5110$941
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11]
- connect \B $xor$ls180.v:5075$940_Y
- connect \Y $xor$ls180.v:5075$941_Y
+ connect \B $xor$ls180.v:5110$940_Y
+ connect \Y $xor$ls180.v:5110$941_Y
end
- attribute \src "ls180.v:5084.879-5084.961"
- cell $xor $xor$ls180.v:5084$943
+ attribute \src "ls180.v:5119.879-5119.961"
+ cell $xor $xor$ls180.v:5119$943
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_val [1]
connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15]
- connect \Y $xor$ls180.v:5084$943_Y
+ connect \Y $xor$ls180.v:5119$943_Y
end
- attribute \src "ls180.v:5084.620-5084.702"
- cell $xor $xor$ls180.v:5084$944
+ attribute \src "ls180.v:5119.620-5119.702"
+ cell $xor $xor$ls180.v:5119$944
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_val [1]
connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15]
- connect \Y $xor$ls180.v:5084$944_Y
+ connect \Y $xor$ls180.v:5119$944_Y
end
- attribute \src "ls180.v:5084.575-5084.703"
- cell $xor $xor$ls180.v:5084$945
+ attribute \src "ls180.v:5119.575-5119.703"
+ cell $xor $xor$ls180.v:5119$945
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4]
- connect \B $xor$ls180.v:5084$944_Y
- connect \Y $xor$ls180.v:5084$945_Y
+ connect \B $xor$ls180.v:5119$944_Y
+ connect \Y $xor$ls180.v:5119$945_Y
end
- attribute \src "ls180.v:5084.229-5084.311"
- cell $xor $xor$ls180.v:5084$946
+ attribute \src "ls180.v:5119.229-5119.311"
+ cell $xor $xor$ls180.v:5119$946
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_val [1]
connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15]
- connect \Y $xor$ls180.v:5084$946_Y
+ connect \Y $xor$ls180.v:5119$946_Y
end
- attribute \src "ls180.v:5084.183-5084.312"
- cell $xor $xor$ls180.v:5084$947
+ attribute \src "ls180.v:5119.183-5119.312"
+ cell $xor $xor$ls180.v:5119$947
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11]
- connect \B $xor$ls180.v:5084$946_Y
- connect \Y $xor$ls180.v:5084$947_Y
+ connect \B $xor$ls180.v:5119$946_Y
+ connect \Y $xor$ls180.v:5119$947_Y
end
- attribute \src "ls180.v:5085.879-5085.961"
- cell $xor $xor$ls180.v:5085$948
+ attribute \src "ls180.v:5120.879-5120.961"
+ cell $xor $xor$ls180.v:5120$948
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_val [0]
connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15]
- connect \Y $xor$ls180.v:5085$948_Y
+ connect \Y $xor$ls180.v:5120$948_Y
end
- attribute \src "ls180.v:5085.620-5085.702"
- cell $xor $xor$ls180.v:5085$949
+ attribute \src "ls180.v:5120.620-5120.702"
+ cell $xor $xor$ls180.v:5120$949
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_val [0]
connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15]
- connect \Y $xor$ls180.v:5085$949_Y
+ connect \Y $xor$ls180.v:5120$949_Y
end
- attribute \src "ls180.v:5085.575-5085.703"
- cell $xor $xor$ls180.v:5085$950
+ attribute \src "ls180.v:5120.575-5120.703"
+ cell $xor $xor$ls180.v:5120$950
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4]
- connect \B $xor$ls180.v:5085$949_Y
- connect \Y $xor$ls180.v:5085$950_Y
+ connect \B $xor$ls180.v:5120$949_Y
+ connect \Y $xor$ls180.v:5120$950_Y
end
- attribute \src "ls180.v:5085.229-5085.311"
- cell $xor $xor$ls180.v:5085$951
+ attribute \src "ls180.v:5120.229-5120.311"
+ cell $xor $xor$ls180.v:5120$951
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_val [0]
connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15]
- connect \Y $xor$ls180.v:5085$951_Y
+ connect \Y $xor$ls180.v:5120$951_Y
end
- attribute \src "ls180.v:5085.183-5085.312"
- cell $xor $xor$ls180.v:5085$952
+ attribute \src "ls180.v:5120.183-5120.312"
+ cell $xor $xor$ls180.v:5120$952
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11]
- connect \B $xor$ls180.v:5085$951_Y
- connect \Y $xor$ls180.v:5085$952_Y
+ connect \B $xor$ls180.v:5120$951_Y
+ connect \Y $xor$ls180.v:5120$952_Y
end
attribute \module_not_derived 1
- attribute \src "ls180.v:10113.13-10280.2"
+ attribute \src "ls180.v:10176.13-10345.2"
cell \test_issuer \test_issuer
connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck
connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi
connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms
connect \busy_o \main_libresocsim_libresoc0
connect \clk \sys_clk_1
+ connect \clk_sel_i \main_libresocsim_libresoc_clk_sel
connect \core_bigendian_i 1'0
connect \dbus__ack \main_libresocsim_libresoc_dbus_ack
connect \dbus__adr \main_libresocsim_libresoc_dbus_adr
connect \pc_i 1'0
connect \pc_i_ok 1'0
connect \pc_o \main_libresocsim_libresoc2
- connect \rst $or$ls180.v:10195$2752_Y
+ connect \pll_48_o \main_libresocsim_libresoc_pll_48_o
+ connect \rst $or$ls180.v:10259$2762_Y
connect \uart_rx__core__i \main_libresocsim_libresoc_constraintmanager0_uart0_rx
connect \uart_rx__pad__i \main_libresocsim_libresoc_constraintmanager1_uart0_rx
connect \uart_tx__core__o \main_libresocsim_libresoc_constraintmanager0_uart0_tx
connect \uart_tx__pad__o \main_libresocsim_libresoc_constraintmanager1_uart0_tx
end
attribute \src "ls180.v:0.0-0.0"
- process $proc$ls180.v:0$3701
+ process $proc$ls180.v:0$3714
+ sync always
+ sync init
+ end
+ attribute \src "ls180.v:1001.11-1001.43"
+ process $proc$ls180.v:1001$3156
+ assign { } { }
+ assign $1\main_spi_master_mosi_data[7:0] 8'00000000
+ sync always
+ sync init
+ update \main_spi_master_mosi_data $1\main_spi_master_mosi_data[7:0]
+ end
+ attribute \src "ls180.v:1002.11-1002.42"
+ process $proc$ls180.v:1002$3157
+ assign { } { }
+ assign $1\main_spi_master_mosi_sel[2:0] 3'000
sync always
sync init
+ update \main_spi_master_mosi_sel $1\main_spi_master_mosi_sel[2:0]
end
- attribute \src "ls180.v:10003.1-10004.4"
- process $proc$ls180.v:10003$2701
+ attribute \src "ls180.v:1003.11-1003.43"
+ process $proc$ls180.v:1003$3158
+ assign { } { }
+ assign $1\main_spi_master_miso_data[7:0] 8'00000000
+ sync always
+ sync init
+ update \main_spi_master_miso_data $1\main_spi_master_miso_data[7:0]
+ end
+ attribute \src "ls180.v:10040.1-10050.4"
+ process $proc$ls180.v:10040$2692
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $0$memwr$\mem$ls180.v:10048$4_ADDR[6:0]$2702 7'xxxxxxx
+ assign $0$memwr$\mem$ls180.v:10048$4_DATA[31:0]$2703 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\mem$ls180.v:10048$4_EN[31:0]$2704 0
+ assign $0$memwr$\mem$ls180.v:10046$3_ADDR[6:0]$2699 7'xxxxxxx
+ assign $0$memwr$\mem$ls180.v:10046$3_DATA[31:0]$2700 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\mem$ls180.v:10046$3_EN[31:0]$2701 0
+ assign $0$memwr$\mem$ls180.v:10044$2_ADDR[6:0]$2696 7'xxxxxxx
+ assign $0$memwr$\mem$ls180.v:10044$2_DATA[31:0]$2697 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\mem$ls180.v:10044$2_EN[31:0]$2698 0
+ assign $0$memwr$\mem$ls180.v:10042$1_ADDR[6:0]$2693 7'xxxxxxx
+ assign $0$memwr$\mem$ls180.v:10042$1_DATA[31:0]$2694 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\mem$ls180.v:10042$1_EN[31:0]$2695 0
+ assign $0\memadr[6:0] \main_libresocsim_adr
+ attribute \src "ls180.v:10041.2-10042.65"
+ switch \main_libresocsim_we [0]
+ attribute \src "ls180.v:10041.6-10041.28"
+ case 1'1
+ assign $0$memwr$\mem$ls180.v:10042$1_ADDR[6:0]$2693 \main_libresocsim_adr
+ assign $0$memwr$\mem$ls180.v:10042$1_DATA[31:0]$2694 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] }
+ assign $0$memwr$\mem$ls180.v:10042$1_EN[31:0]$2695 255
+ case
+ end
+ attribute \src "ls180.v:10043.2-10044.67"
+ switch \main_libresocsim_we [1]
+ attribute \src "ls180.v:10043.6-10043.28"
+ case 1'1
+ assign $0$memwr$\mem$ls180.v:10044$2_ADDR[6:0]$2696 \main_libresocsim_adr
+ assign $0$memwr$\mem$ls180.v:10044$2_DATA[31:0]$2697 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx }
+ assign $0$memwr$\mem$ls180.v:10044$2_EN[31:0]$2698 65280
+ case
+ end
+ attribute \src "ls180.v:10045.2-10046.69"
+ switch \main_libresocsim_we [2]
+ attribute \src "ls180.v:10045.6-10045.28"
+ case 1'1
+ assign $0$memwr$\mem$ls180.v:10046$3_ADDR[6:0]$2699 \main_libresocsim_adr
+ assign $0$memwr$\mem$ls180.v:10046$3_DATA[31:0]$2700 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
+ assign $0$memwr$\mem$ls180.v:10046$3_EN[31:0]$2701 16711680
+ case
+ end
+ attribute \src "ls180.v:10047.2-10048.69"
+ switch \main_libresocsim_we [3]
+ attribute \src "ls180.v:10047.6-10047.28"
+ case 1'1
+ assign $0$memwr$\mem$ls180.v:10048$4_ADDR[6:0]$2702 \main_libresocsim_adr
+ assign $0$memwr$\mem$ls180.v:10048$4_DATA[31:0]$2703 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
+ assign $0$memwr$\mem$ls180.v:10048$4_EN[31:0]$2704 32'11111111000000000000000000000000
+ case
+ end
sync posedge \sys_clk_1
+ update \memadr $0\memadr[6:0]
+ update $memwr$\mem$ls180.v:10042$1_ADDR $0$memwr$\mem$ls180.v:10042$1_ADDR[6:0]$2693
+ update $memwr$\mem$ls180.v:10042$1_DATA $0$memwr$\mem$ls180.v:10042$1_DATA[31:0]$2694
+ update $memwr$\mem$ls180.v:10042$1_EN $0$memwr$\mem$ls180.v:10042$1_EN[31:0]$2695
+ update $memwr$\mem$ls180.v:10044$2_ADDR $0$memwr$\mem$ls180.v:10044$2_ADDR[6:0]$2696
+ update $memwr$\mem$ls180.v:10044$2_DATA $0$memwr$\mem$ls180.v:10044$2_DATA[31:0]$2697
+ update $memwr$\mem$ls180.v:10044$2_EN $0$memwr$\mem$ls180.v:10044$2_EN[31:0]$2698
+ update $memwr$\mem$ls180.v:10046$3_ADDR $0$memwr$\mem$ls180.v:10046$3_ADDR[6:0]$2699
+ update $memwr$\mem$ls180.v:10046$3_DATA $0$memwr$\mem$ls180.v:10046$3_DATA[31:0]$2700
+ update $memwr$\mem$ls180.v:10046$3_EN $0$memwr$\mem$ls180.v:10046$3_EN[31:0]$2701
+ update $memwr$\mem$ls180.v:10048$4_ADDR $0$memwr$\mem$ls180.v:10048$4_ADDR[6:0]$2702
+ update $memwr$\mem$ls180.v:10048$4_DATA $0$memwr$\mem$ls180.v:10048$4_DATA[31:0]$2703
+ update $memwr$\mem$ls180.v:10048$4_EN $0$memwr$\mem$ls180.v:10048$4_EN[31:0]$2704
end
- attribute \src "ls180.v:1001.12-1001.37"
- process $proc$ls180.v:1001$3150
+ attribute \src "ls180.v:1005.12-1005.30"
+ process $proc$ls180.v:1005$3159
assign { } { }
- assign $1\main_pwm0_counter[31:0] 0
+ assign $1\main_dummy[35:0] 36'000000000000000000000000000000000000
sync always
sync init
- update \main_pwm0_counter $1\main_pwm0_counter[31:0]
+ update \main_dummy $1\main_dummy[35:0]
end
- attribute \src "ls180.v:10011.1-10015.4"
- process $proc$ls180.v:10011$2703
+ attribute \src "ls180.v:10060.1-10064.4"
+ process $proc$ls180.v:10060$2706
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 3'xxx
- assign $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 25'xxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 25'0000000000000000000000000
- assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10014$2707_DATA
- attribute \src "ls180.v:10012.2-10013.131"
- switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:10012.6-10012.60"
+ assign $0$memwr$\storage$ls180.v:10062$5_ADDR[2:0]$2707 3'xxx
+ assign $0$memwr$\storage$ls180.v:10062$5_DATA[24:0]$2708 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\storage$ls180.v:10062$5_EN[24:0]$2709 25'0000000000000000000000000
+ assign $0\memdat[24:0] $memrd$\storage$ls180.v:10063$2710_DATA
+ attribute \src "ls180.v:10061.2-10062.129"
+ switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
+ attribute \src "ls180.v:10061.6-10061.60"
case 1'1
- assign $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
- assign $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
- assign $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 25'1111111111111111111111111
+ assign $0$memwr$\storage$ls180.v:10062$5_ADDR[2:0]$2707 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
+ assign $0$memwr$\storage$ls180.v:10062$5_DATA[24:0]$2708 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
+ assign $0$memwr$\storage$ls180.v:10062$5_EN[24:0]$2709 25'1111111111111111111111111
case
end
sync posedge \sys_clk_1
- update \memdat_1 $0\memdat_1[24:0]
- update $memwr$\storage_1$ls180.v:10013$6_ADDR $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704
- update $memwr$\storage_1$ls180.v:10013$6_DATA $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705
- update $memwr$\storage_1$ls180.v:10013$6_EN $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706
+ update \memdat $0\memdat[24:0]
+ update $memwr$\storage$ls180.v:10062$5_ADDR $0$memwr$\storage$ls180.v:10062$5_ADDR[2:0]$2707
+ update $memwr$\storage$ls180.v:10062$5_DATA $0$memwr$\storage$ls180.v:10062$5_DATA[24:0]$2708
+ update $memwr$\storage$ls180.v:10062$5_EN $0$memwr$\storage$ls180.v:10062$5_EN[24:0]$2709
end
- attribute \src "ls180.v:10017.1-10018.4"
- process $proc$ls180.v:10017$2708
+ attribute \src "ls180.v:10066.1-10067.4"
+ process $proc$ls180.v:10066$2711
sync posedge \sys_clk_1
end
- attribute \src "ls180.v:1002.5-1002.36"
- process $proc$ls180.v:1002$3151
+ attribute \src "ls180.v:10074.1-10078.4"
+ process $proc$ls180.v:10074$2713
assign { } { }
- assign $1\main_pwm0_enable_storage[0:0] 1'0
- sync always
- sync init
- update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0]
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $0$memwr$\storage_1$ls180.v:10076$6_ADDR[2:0]$2714 3'xxx
+ assign $0$memwr$\storage_1$ls180.v:10076$6_DATA[24:0]$2715 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\storage_1$ls180.v:10076$6_EN[24:0]$2716 25'0000000000000000000000000
+ assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10077$2717_DATA
+ attribute \src "ls180.v:10075.2-10076.131"
+ switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
+ attribute \src "ls180.v:10075.6-10075.60"
+ case 1'1
+ assign $0$memwr$\storage_1$ls180.v:10076$6_ADDR[2:0]$2714 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
+ assign $0$memwr$\storage_1$ls180.v:10076$6_DATA[24:0]$2715 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
+ assign $0$memwr$\storage_1$ls180.v:10076$6_EN[24:0]$2716 25'1111111111111111111111111
+ case
+ end
+ sync posedge \sys_clk_1
+ update \memdat_1 $0\memdat_1[24:0]
+ update $memwr$\storage_1$ls180.v:10076$6_ADDR $0$memwr$\storage_1$ls180.v:10076$6_ADDR[2:0]$2714
+ update $memwr$\storage_1$ls180.v:10076$6_DATA $0$memwr$\storage_1$ls180.v:10076$6_DATA[24:0]$2715
+ update $memwr$\storage_1$ls180.v:10076$6_EN $0$memwr$\storage_1$ls180.v:10076$6_EN[24:0]$2716
+ end
+ attribute \src "ls180.v:10080.1-10081.4"
+ process $proc$ls180.v:10080$2718
+ sync posedge \sys_clk_1
end
- attribute \src "ls180.v:10025.1-10029.4"
- process $proc$ls180.v:10025$2710
+ attribute \src "ls180.v:10088.1-10092.4"
+ process $proc$ls180.v:10088$2720
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 3'xxx
- assign $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 25'xxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 25'0000000000000000000000000
- assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10028$2714_DATA
- attribute \src "ls180.v:10026.2-10027.131"
+ assign $0$memwr$\storage_2$ls180.v:10090$7_ADDR[2:0]$2721 3'xxx
+ assign $0$memwr$\storage_2$ls180.v:10090$7_DATA[24:0]$2722 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\storage_2$ls180.v:10090$7_EN[24:0]$2723 25'0000000000000000000000000
+ assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10091$2724_DATA
+ attribute \src "ls180.v:10089.2-10090.131"
switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:10026.6-10026.60"
+ attribute \src "ls180.v:10089.6-10089.60"
case 1'1
- assign $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
- assign $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
- assign $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 25'1111111111111111111111111
+ assign $0$memwr$\storage_2$ls180.v:10090$7_ADDR[2:0]$2721 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
+ assign $0$memwr$\storage_2$ls180.v:10090$7_DATA[24:0]$2722 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
+ assign $0$memwr$\storage_2$ls180.v:10090$7_EN[24:0]$2723 25'1111111111111111111111111
case
end
sync posedge \sys_clk_1
update \memdat_2 $0\memdat_2[24:0]
- update $memwr$\storage_2$ls180.v:10027$7_ADDR $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711
- update $memwr$\storage_2$ls180.v:10027$7_DATA $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712
- update $memwr$\storage_2$ls180.v:10027$7_EN $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713
+ update $memwr$\storage_2$ls180.v:10090$7_ADDR $0$memwr$\storage_2$ls180.v:10090$7_ADDR[2:0]$2721
+ update $memwr$\storage_2$ls180.v:10090$7_DATA $0$memwr$\storage_2$ls180.v:10090$7_DATA[24:0]$2722
+ update $memwr$\storage_2$ls180.v:10090$7_EN $0$memwr$\storage_2$ls180.v:10090$7_EN[24:0]$2723
end
- attribute \src "ls180.v:1003.5-1003.31"
- process $proc$ls180.v:1003$3152
+ attribute \src "ls180.v:1009.12-1009.37"
+ process $proc$ls180.v:1009$3160
assign { } { }
- assign $1\main_pwm0_enable_re[0:0] 1'0
+ assign $1\main_pwm0_counter[31:0] 0
sync always
sync init
- update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0]
+ update \main_pwm0_counter $1\main_pwm0_counter[31:0]
end
- attribute \src "ls180.v:10031.1-10032.4"
- process $proc$ls180.v:10031$2715
+ attribute \src "ls180.v:10094.1-10095.4"
+ process $proc$ls180.v:10094$2725
sync posedge \sys_clk_1
end
- attribute \src "ls180.v:10039.1-10043.4"
- process $proc$ls180.v:10039$2717
+ attribute \src "ls180.v:1010.5-1010.36"
+ process $proc$ls180.v:1010$3161
+ assign { } { }
+ assign $1\main_pwm0_enable_storage[0:0] 1'0
+ sync always
+ sync init
+ update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0]
+ end
+ attribute \src "ls180.v:10102.1-10106.4"
+ process $proc$ls180.v:10102$2727
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 3'xxx
- assign $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 25'xxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 25'0000000000000000000000000
- assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10042$2721_DATA
- attribute \src "ls180.v:10040.2-10041.131"
+ assign $0$memwr$\storage_3$ls180.v:10104$8_ADDR[2:0]$2728 3'xxx
+ assign $0$memwr$\storage_3$ls180.v:10104$8_DATA[24:0]$2729 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $0$memwr$\storage_3$ls180.v:10104$8_EN[24:0]$2730 25'0000000000000000000000000
+ assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10105$2731_DATA
+ attribute \src "ls180.v:10103.2-10104.131"
switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:10040.6-10040.60"
+ attribute \src "ls180.v:10103.6-10103.60"
case 1'1
- assign $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
- assign $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
- assign $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 25'1111111111111111111111111
+ assign $0$memwr$\storage_3$ls180.v:10104$8_ADDR[2:0]$2728 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
+ assign $0$memwr$\storage_3$ls180.v:10104$8_DATA[24:0]$2729 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
+ assign $0$memwr$\storage_3$ls180.v:10104$8_EN[24:0]$2730 25'1111111111111111111111111
case
end
sync posedge \sys_clk_1
update \memdat_3 $0\memdat_3[24:0]
- update $memwr$\storage_3$ls180.v:10041$8_ADDR $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718
- update $memwr$\storage_3$ls180.v:10041$8_DATA $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719
- update $memwr$\storage_3$ls180.v:10041$8_EN $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720
+ update $memwr$\storage_3$ls180.v:10104$8_ADDR $0$memwr$\storage_3$ls180.v:10104$8_ADDR[2:0]$2728
+ update $memwr$\storage_3$ls180.v:10104$8_DATA $0$memwr$\storage_3$ls180.v:10104$8_DATA[24:0]$2729
+ update $memwr$\storage_3$ls180.v:10104$8_EN $0$memwr$\storage_3$ls180.v:10104$8_EN[24:0]$2730
end
- attribute \src "ls180.v:1004.12-1004.43"
- process $proc$ls180.v:1004$3153
- assign { } { }
- assign $1\main_pwm0_width_storage[31:0] 0
- sync always
- sync init
- update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0]
- end
- attribute \src "ls180.v:10045.1-10046.4"
- process $proc$ls180.v:10045$2722
+ attribute \src "ls180.v:10108.1-10109.4"
+ process $proc$ls180.v:10108$2732
sync posedge \sys_clk_1
end
- attribute \src "ls180.v:1005.5-1005.30"
- process $proc$ls180.v:1005$3154
+ attribute \src "ls180.v:1011.5-1011.31"
+ process $proc$ls180.v:1011$3162
assign { } { }
- assign $1\main_pwm0_width_re[0:0] 1'0
+ assign $1\main_pwm0_enable_re[0:0] 1'0
sync always
sync init
- update \main_pwm0_width_re $1\main_pwm0_width_re[0:0]
+ update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0]
end
- attribute \src "ls180.v:10054.1-10058.4"
- process $proc$ls180.v:10054$2724
+ attribute \src "ls180.v:10117.1-10121.4"
+ process $proc$ls180.v:10117$2734
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 4'xxxx
- assign $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 10'xxxxxxxxxx
- assign $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 10'0000000000
- assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10057$2728_DATA
- attribute \src "ls180.v:10055.2-10056.77"
+ assign $0$memwr$\storage_4$ls180.v:10119$9_ADDR[3:0]$2735 4'xxxx
+ assign $0$memwr$\storage_4$ls180.v:10119$9_DATA[9:0]$2736 10'xxxxxxxxxx
+ assign $0$memwr$\storage_4$ls180.v:10119$9_EN[9:0]$2737 10'0000000000
+ assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10120$2738_DATA
+ attribute \src "ls180.v:10118.2-10119.77"
switch \main_uart_tx_fifo_wrport_we
- attribute \src "ls180.v:10055.6-10055.33"
+ attribute \src "ls180.v:10118.6-10118.33"
case 1'1
- assign $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 \main_uart_tx_fifo_wrport_adr
- assign $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 \main_uart_tx_fifo_wrport_dat_w
- assign $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 10'1111111111
+ assign $0$memwr$\storage_4$ls180.v:10119$9_ADDR[3:0]$2735 \main_uart_tx_fifo_wrport_adr
+ assign $0$memwr$\storage_4$ls180.v:10119$9_DATA[9:0]$2736 \main_uart_tx_fifo_wrport_dat_w
+ assign $0$memwr$\storage_4$ls180.v:10119$9_EN[9:0]$2737 10'1111111111
case
end
sync posedge \sys_clk_1
update \memdat_4 $0\memdat_4[9:0]
- update $memwr$\storage_4$ls180.v:10056$9_ADDR $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725
- update $memwr$\storage_4$ls180.v:10056$9_DATA $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726
- update $memwr$\storage_4$ls180.v:10056$9_EN $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727
+ update $memwr$\storage_4$ls180.v:10119$9_ADDR $0$memwr$\storage_4$ls180.v:10119$9_ADDR[3:0]$2735
+ update $memwr$\storage_4$ls180.v:10119$9_DATA $0$memwr$\storage_4$ls180.v:10119$9_DATA[9:0]$2736
+ update $memwr$\storage_4$ls180.v:10119$9_EN $0$memwr$\storage_4$ls180.v:10119$9_EN[9:0]$2737
end
- attribute \src "ls180.v:1006.12-1006.44"
- process $proc$ls180.v:1006$3155
+ attribute \src "ls180.v:1012.12-1012.43"
+ process $proc$ls180.v:1012$3163
assign { } { }
- assign $1\main_pwm0_period_storage[31:0] 0
+ assign $1\main_pwm0_width_storage[31:0] 0
sync always
sync init
- update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0]
+ update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0]
end
- attribute \src "ls180.v:10060.1-10063.4"
- process $proc$ls180.v:10060$2729
+ attribute \src "ls180.v:10123.1-10126.4"
+ process $proc$ls180.v:10123$2739
assign $0\memdat_5[9:0] \memdat_5
- attribute \src "ls180.v:10061.2-10062.55"
+ attribute \src "ls180.v:10124.2-10125.55"
switch \main_uart_tx_fifo_rdport_re
- attribute \src "ls180.v:10061.6-10061.33"
+ attribute \src "ls180.v:10124.6-10124.33"
case 1'1
- assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10062$2730_DATA
+ assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10125$2740_DATA
case
end
sync posedge \sys_clk_1
update \memdat_5 $0\memdat_5[9:0]
end
- attribute \src "ls180.v:1007.5-1007.31"
- process $proc$ls180.v:1007$3156
+ attribute \src "ls180.v:1013.5-1013.30"
+ process $proc$ls180.v:1013$3164
assign { } { }
- assign $1\main_pwm0_period_re[0:0] 1'0
+ assign $1\main_pwm0_width_re[0:0] 1'0
sync always
sync init
- update \main_pwm0_period_re $1\main_pwm0_period_re[0:0]
+ update \main_pwm0_width_re $1\main_pwm0_width_re[0:0]
end
- attribute \src "ls180.v:10071.1-10075.4"
- process $proc$ls180.v:10071$2731
+ attribute \src "ls180.v:10134.1-10138.4"
+ process $proc$ls180.v:10134$2741
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 4'xxxx
- assign $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 10'xxxxxxxxxx
- assign $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 10'0000000000
- assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10074$2735_DATA
- attribute \src "ls180.v:10072.2-10073.77"
+ assign $0$memwr$\storage_5$ls180.v:10136$10_ADDR[3:0]$2742 4'xxxx
+ assign $0$memwr$\storage_5$ls180.v:10136$10_DATA[9:0]$2743 10'xxxxxxxxxx
+ assign $0$memwr$\storage_5$ls180.v:10136$10_EN[9:0]$2744 10'0000000000
+ assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10137$2745_DATA
+ attribute \src "ls180.v:10135.2-10136.77"
switch \main_uart_rx_fifo_wrport_we
- attribute \src "ls180.v:10072.6-10072.33"
+ attribute \src "ls180.v:10135.6-10135.33"
case 1'1
- assign $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 \main_uart_rx_fifo_wrport_adr
- assign $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 \main_uart_rx_fifo_wrport_dat_w
- assign $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 10'1111111111
+ assign $0$memwr$\storage_5$ls180.v:10136$10_ADDR[3:0]$2742 \main_uart_rx_fifo_wrport_adr
+ assign $0$memwr$\storage_5$ls180.v:10136$10_DATA[9:0]$2743 \main_uart_rx_fifo_wrport_dat_w
+ assign $0$memwr$\storage_5$ls180.v:10136$10_EN[9:0]$2744 10'1111111111
case
end
sync posedge \sys_clk_1
update \memdat_6 $0\memdat_6[9:0]
- update $memwr$\storage_5$ls180.v:10073$10_ADDR $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732
- update $memwr$\storage_5$ls180.v:10073$10_DATA $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733
- update $memwr$\storage_5$ls180.v:10073$10_EN $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734
+ update $memwr$\storage_5$ls180.v:10136$10_ADDR $0$memwr$\storage_5$ls180.v:10136$10_ADDR[3:0]$2742
+ update $memwr$\storage_5$ls180.v:10136$10_DATA $0$memwr$\storage_5$ls180.v:10136$10_DATA[9:0]$2743
+ update $memwr$\storage_5$ls180.v:10136$10_EN $0$memwr$\storage_5$ls180.v:10136$10_EN[9:0]$2744
+ end
+ attribute \src "ls180.v:1014.12-1014.44"
+ process $proc$ls180.v:1014$3165
+ assign { } { }
+ assign $1\main_pwm0_period_storage[31:0] 0
+ sync always
+ sync init
+ update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0]
end
- attribute \src "ls180.v:10077.1-10080.4"
- process $proc$ls180.v:10077$2736
+ attribute \src "ls180.v:10140.1-10143.4"
+ process $proc$ls180.v:10140$2746
assign $0\memdat_7[9:0] \memdat_7
- attribute \src "ls180.v:10078.2-10079.55"
+ attribute \src "ls180.v:10141.2-10142.55"
switch \main_uart_rx_fifo_rdport_re
- attribute \src "ls180.v:10078.6-10078.33"
+ attribute \src "ls180.v:10141.6-10141.33"
case 1'1
- assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10079$2737_DATA
+ assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10142$2747_DATA
case
end
sync posedge \sys_clk_1
update \memdat_7 $0\memdat_7[9:0]
end
- attribute \src "ls180.v:10087.1-10091.4"
- process $proc$ls180.v:10087$2738
+ attribute \src "ls180.v:1015.5-1015.31"
+ process $proc$ls180.v:1015$3166
assign { } { }
+ assign $1\main_pwm0_period_re[0:0] 1'0
+ sync always
+ sync init
+ update \main_pwm0_period_re $1\main_pwm0_period_re[0:0]
+ end
+ attribute \src "ls180.v:10150.1-10154.4"
+ process $proc$ls180.v:10150$2748
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 5'xxxxx
- assign $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 10'xxxxxxxxxx
- assign $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 10'0000000000
- assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10090$2742_DATA
- attribute \src "ls180.v:10088.2-10089.85"
+ assign { } { }
+ assign $0$memwr$\storage_6$ls180.v:10152$11_ADDR[4:0]$2749 5'xxxxx
+ assign $0$memwr$\storage_6$ls180.v:10152$11_DATA[9:0]$2750 10'xxxxxxxxxx
+ assign $0$memwr$\storage_6$ls180.v:10152$11_EN[9:0]$2751 10'0000000000
+ assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10153$2752_DATA
+ attribute \src "ls180.v:10151.2-10152.85"
switch \main_sdblock2mem_fifo_wrport_we
- attribute \src "ls180.v:10088.6-10088.37"
+ attribute \src "ls180.v:10151.6-10151.37"
case 1'1
- assign $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 \main_sdblock2mem_fifo_wrport_adr
- assign $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 \main_sdblock2mem_fifo_wrport_dat_w
- assign $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 10'1111111111
+ assign $0$memwr$\storage_6$ls180.v:10152$11_ADDR[4:0]$2749 \main_sdblock2mem_fifo_wrport_adr
+ assign $0$memwr$\storage_6$ls180.v:10152$11_DATA[9:0]$2750 \main_sdblock2mem_fifo_wrport_dat_w
+ assign $0$memwr$\storage_6$ls180.v:10152$11_EN[9:0]$2751 10'1111111111
case
end
sync posedge \sys_clk_1
update \memdat_8 $0\memdat_8[9:0]
- update $memwr$\storage_6$ls180.v:10089$11_ADDR $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739
- update $memwr$\storage_6$ls180.v:10089$11_DATA $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740
- update $memwr$\storage_6$ls180.v:10089$11_EN $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741
+ update $memwr$\storage_6$ls180.v:10152$11_ADDR $0$memwr$\storage_6$ls180.v:10152$11_ADDR[4:0]$2749
+ update $memwr$\storage_6$ls180.v:10152$11_DATA $0$memwr$\storage_6$ls180.v:10152$11_DATA[9:0]$2750
+ update $memwr$\storage_6$ls180.v:10152$11_EN $0$memwr$\storage_6$ls180.v:10152$11_EN[9:0]$2751
end
- attribute \src "ls180.v:10093.1-10094.4"
- process $proc$ls180.v:10093$2743
+ attribute \src "ls180.v:10156.1-10157.4"
+ process $proc$ls180.v:10156$2753
sync posedge \sys_clk_1
end
- attribute \src "ls180.v:10101.1-10105.4"
- process $proc$ls180.v:10101$2745
+ attribute \src "ls180.v:10164.1-10168.4"
+ process $proc$ls180.v:10164$2755
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 5'xxxxx
- assign $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 10'xxxxxxxxxx
- assign $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 10'0000000000
- assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10104$2749_DATA
- attribute \src "ls180.v:10102.2-10103.85"
+ assign $0$memwr$\storage_7$ls180.v:10166$12_ADDR[4:0]$2756 5'xxxxx
+ assign $0$memwr$\storage_7$ls180.v:10166$12_DATA[9:0]$2757 10'xxxxxxxxxx
+ assign $0$memwr$\storage_7$ls180.v:10166$12_EN[9:0]$2758 10'0000000000
+ assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10167$2759_DATA
+ attribute \src "ls180.v:10165.2-10166.85"
switch \main_sdmem2block_fifo_wrport_we
- attribute \src "ls180.v:10102.6-10102.37"
+ attribute \src "ls180.v:10165.6-10165.37"
case 1'1
- assign $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 \main_sdmem2block_fifo_wrport_adr
- assign $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 \main_sdmem2block_fifo_wrport_dat_w
- assign $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 10'1111111111
+ assign $0$memwr$\storage_7$ls180.v:10166$12_ADDR[4:0]$2756 \main_sdmem2block_fifo_wrport_adr
+ assign $0$memwr$\storage_7$ls180.v:10166$12_DATA[9:0]$2757 \main_sdmem2block_fifo_wrport_dat_w
+ assign $0$memwr$\storage_7$ls180.v:10166$12_EN[9:0]$2758 10'1111111111
case
end
sync posedge \sys_clk_1
update \memdat_9 $0\memdat_9[9:0]
- update $memwr$\storage_7$ls180.v:10103$12_ADDR $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746
- update $memwr$\storage_7$ls180.v:10103$12_DATA $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747
- update $memwr$\storage_7$ls180.v:10103$12_EN $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748
+ update $memwr$\storage_7$ls180.v:10166$12_ADDR $0$memwr$\storage_7$ls180.v:10166$12_ADDR[4:0]$2756
+ update $memwr$\storage_7$ls180.v:10166$12_DATA $0$memwr$\storage_7$ls180.v:10166$12_DATA[9:0]$2757
+ update $memwr$\storage_7$ls180.v:10166$12_EN $0$memwr$\storage_7$ls180.v:10166$12_EN[9:0]$2758
end
- attribute \src "ls180.v:10107.1-10108.4"
- process $proc$ls180.v:10107$2750
+ attribute \src "ls180.v:10170.1-10171.4"
+ process $proc$ls180.v:10170$2760
sync posedge \sys_clk_1
end
- attribute \src "ls180.v:1011.12-1011.37"
- process $proc$ls180.v:1011$3157
+ attribute \src "ls180.v:1019.12-1019.37"
+ process $proc$ls180.v:1019$3167
assign { } { }
assign $1\main_pwm1_counter[31:0] 0
sync always
sync init
update \main_pwm1_counter $1\main_pwm1_counter[31:0]
end
- attribute \src "ls180.v:1012.5-1012.36"
- process $proc$ls180.v:1012$3158
+ attribute \src "ls180.v:1020.5-1020.36"
+ process $proc$ls180.v:1020$3168
assign { } { }
assign $1\main_pwm1_enable_storage[0:0] 1'0
sync always
sync init
update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0]
end
- attribute \src "ls180.v:1013.5-1013.31"
- process $proc$ls180.v:1013$3159
+ attribute \src "ls180.v:1021.5-1021.31"
+ process $proc$ls180.v:1021$3169
assign { } { }
assign $1\main_pwm1_enable_re[0:0] 1'0
sync always
sync init
update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0]
end
- attribute \src "ls180.v:1014.12-1014.43"
- process $proc$ls180.v:1014$3160
+ attribute \src "ls180.v:1022.12-1022.43"
+ process $proc$ls180.v:1022$3170
assign { } { }
assign $1\main_pwm1_width_storage[31:0] 0
sync always
sync init
update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0]
end
- attribute \src "ls180.v:1015.5-1015.30"
- process $proc$ls180.v:1015$3161
+ attribute \src "ls180.v:1023.5-1023.30"
+ process $proc$ls180.v:1023$3171
assign { } { }
assign $1\main_pwm1_width_re[0:0] 1'0
sync always
sync init
update \main_pwm1_width_re $1\main_pwm1_width_re[0:0]
end
- attribute \src "ls180.v:1016.12-1016.44"
- process $proc$ls180.v:1016$3162
+ attribute \src "ls180.v:1024.12-1024.44"
+ process $proc$ls180.v:1024$3172
assign { } { }
assign $1\main_pwm1_period_storage[31:0] 0
sync always
sync init
update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0]
end
- attribute \src "ls180.v:1017.5-1017.31"
- process $proc$ls180.v:1017$3163
+ attribute \src "ls180.v:1025.5-1025.31"
+ process $proc$ls180.v:1025$3173
assign { } { }
assign $1\main_pwm1_period_re[0:0] 1'0
sync always
sync init
update \main_pwm1_period_re $1\main_pwm1_period_re[0:0]
end
- attribute \src "ls180.v:1020.11-1020.46"
- process $proc$ls180.v:1020$3164
+ attribute \src "ls180.v:1029.11-1029.34"
+ process $proc$ls180.v:1029$3174
+ assign { } { }
+ assign $1\main_i2c_storage[2:0] 3'000
+ sync always
+ sync init
+ update \main_i2c_storage $1\main_i2c_storage[2:0]
+ end
+ attribute \src "ls180.v:1030.5-1030.23"
+ process $proc$ls180.v:1030$3175
+ assign { } { }
+ assign $1\main_i2c_re[0:0] 1'0
+ sync always
+ sync init
+ update \main_i2c_re $1\main_i2c_re[0:0]
+ end
+ attribute \src "ls180.v:1036.11-1036.46"
+ process $proc$ls180.v:1036$3176
assign { } { }
assign $1\main_sdphy_clocker_storage[8:0] 9'100000000
sync always
sync init
update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0]
end
- attribute \src "ls180.v:1021.5-1021.33"
- process $proc$ls180.v:1021$3165
+ attribute \src "ls180.v:1037.5-1037.33"
+ process $proc$ls180.v:1037$3177
assign { } { }
assign $1\main_sdphy_clocker_re[0:0] 1'0
sync always
sync init
update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0]
end
- attribute \src "ls180.v:1023.5-1023.35"
- process $proc$ls180.v:1023$3166
+ attribute \src "ls180.v:1039.5-1039.35"
+ process $proc$ls180.v:1039$3178
assign { } { }
assign $1\main_sdphy_clocker_clk0[0:0] 1'0
sync always
sync init
update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0]
end
- attribute \src "ls180.v:1025.11-1025.41"
- process $proc$ls180.v:1025$3167
+ attribute \src "ls180.v:1041.11-1041.41"
+ process $proc$ls180.v:1041$3179
assign { } { }
assign $1\main_sdphy_clocker_clks[8:0] 9'000000000
sync always
sync init
update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0]
end
- attribute \src "ls180.v:1026.5-1026.35"
- process $proc$ls180.v:1026$3168
+ attribute \src "ls180.v:1042.5-1042.35"
+ process $proc$ls180.v:1042$3180
assign { } { }
assign $1\main_sdphy_clocker_clk1[0:0] 1'0
sync always
sync init
update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0]
end
- attribute \src "ls180.v:1027.5-1027.36"
- process $proc$ls180.v:1027$3169
+ attribute \src "ls180.v:1043.5-1043.36"
+ process $proc$ls180.v:1043$3181
assign { } { }
assign $1\main_sdphy_clocker_clk_d[0:0] 1'0
sync always
sync init
update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0]
end
- attribute \src "ls180.v:1031.5-1031.40"
- process $proc$ls180.v:1031$3170
+ attribute \src "ls180.v:1047.5-1047.40"
+ process $proc$ls180.v:1047$3182
assign { } { }
assign $0\main_sdphy_init_initialize_w[0:0] 1'0
sync always
update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0]
sync init
end
- attribute \src "ls180.v:1036.5-1036.48"
- process $proc$ls180.v:1036$3171
+ attribute \src "ls180.v:1052.5-1052.48"
+ process $proc$ls180.v:1052$3183
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0
sync always
sync init
update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0]
end
- attribute \src "ls180.v:1037.5-1037.50"
- process $proc$ls180.v:1037$3172
+ attribute \src "ls180.v:1053.5-1053.50"
+ process $proc$ls180.v:1053$3184
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
sync always
sync init
update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0]
end
- attribute \src "ls180.v:1038.5-1038.51"
- process $proc$ls180.v:1038$3173
+ attribute \src "ls180.v:1054.5-1054.51"
+ process $proc$ls180.v:1054$3185
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
sync always
sync init
update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
end
- attribute \src "ls180.v:1039.11-1039.57"
- process $proc$ls180.v:1039$3174
+ attribute \src "ls180.v:1055.11-1055.57"
+ process $proc$ls180.v:1055$3186
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
sync always
sync init
update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0]
end
- attribute \src "ls180.v:1040.5-1040.52"
- process $proc$ls180.v:1040$3175
+ attribute \src "ls180.v:1056.5-1056.52"
+ process $proc$ls180.v:1056$3187
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
sync always
sync init
update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0]
end
- attribute \src "ls180.v:1041.11-1041.39"
- process $proc$ls180.v:1041$3176
+ attribute \src "ls180.v:1057.11-1057.39"
+ process $proc$ls180.v:1057$3188
assign { } { }
assign $1\main_sdphy_init_count[7:0] 8'00000000
sync always
sync init
update \main_sdphy_init_count $1\main_sdphy_init_count[7:0]
end
- attribute \src "ls180.v:1046.5-1046.48"
- process $proc$ls180.v:1046$3177
+ attribute \src "ls180.v:1062.5-1062.48"
+ process $proc$ls180.v:1062$3189
assign { } { }
assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0]
end
- attribute \src "ls180.v:1047.5-1047.50"
- process $proc$ls180.v:1047$3178
+ attribute \src "ls180.v:1063.5-1063.50"
+ process $proc$ls180.v:1063$3190
assign { } { }
assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
end
- attribute \src "ls180.v:1048.5-1048.51"
- process $proc$ls180.v:1048$3179
+ attribute \src "ls180.v:1064.5-1064.51"
+ process $proc$ls180.v:1064$3191
assign { } { }
assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
end
- attribute \src "ls180.v:1049.11-1049.57"
- process $proc$ls180.v:1049$3180
+ attribute \src "ls180.v:1065.11-1065.57"
+ process $proc$ls180.v:1065$3192
assign { } { }
assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0]
sync init
end
- attribute \src "ls180.v:1050.5-1050.52"
- process $proc$ls180.v:1050$3181
+ attribute \src "ls180.v:1066.5-1066.52"
+ process $proc$ls180.v:1066$3193
assign { } { }
assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0]
sync init
end
- attribute \src "ls180.v:1051.5-1051.38"
- process $proc$ls180.v:1051$3182
+ attribute \src "ls180.v:1067.5-1067.38"
+ process $proc$ls180.v:1067$3194
assign { } { }
assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0]
end
- attribute \src "ls180.v:1052.5-1052.38"
- process $proc$ls180.v:1052$3183
+ attribute \src "ls180.v:1068.5-1068.38"
+ process $proc$ls180.v:1068$3195
assign { } { }
assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0]
end
- attribute \src "ls180.v:1053.5-1053.37"
- process $proc$ls180.v:1053$3184
+ attribute \src "ls180.v:1069.5-1069.37"
+ process $proc$ls180.v:1069$3196
assign { } { }
assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0]
end
- attribute \src "ls180.v:1054.11-1054.51"
- process $proc$ls180.v:1054$3185
+ attribute \src "ls180.v:1070.11-1070.51"
+ process $proc$ls180.v:1070$3197
assign { } { }
assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0]
end
- attribute \src "ls180.v:1055.5-1055.32"
- process $proc$ls180.v:1055$3186
+ attribute \src "ls180.v:1071.5-1071.32"
+ process $proc$ls180.v:1071$3198
assign { } { }
assign $1\main_sdphy_cmdw_done[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0]
end
- attribute \src "ls180.v:1056.11-1056.39"
- process $proc$ls180.v:1056$3187
+ attribute \src "ls180.v:1072.11-1072.39"
+ process $proc$ls180.v:1072$3199
assign { } { }
assign $1\main_sdphy_cmdw_count[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0]
end
- attribute \src "ls180.v:1059.5-1059.49"
- process $proc$ls180.v:1059$3188
+ attribute \src "ls180.v:1075.5-1075.49"
+ process $proc$ls180.v:1075$3200
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0]
sync init
end
- attribute \src "ls180.v:1060.5-1060.48"
- process $proc$ls180.v:1060$3189
+ attribute \src "ls180.v:1076.5-1076.48"
+ process $proc$ls180.v:1076$3201
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0]
sync init
end
- attribute \src "ls180.v:1061.5-1061.55"
- process $proc$ls180.v:1061$3190
+ attribute \src "ls180.v:1077.5-1077.55"
+ process $proc$ls180.v:1077$3202
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0]
sync init
end
- attribute \src "ls180.v:1063.5-1063.57"
- process $proc$ls180.v:1063$3191
+ attribute \src "ls180.v:1079.5-1079.57"
+ process $proc$ls180.v:1079$3203
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0]
sync init
end
- attribute \src "ls180.v:1064.5-1064.58"
- process $proc$ls180.v:1064$3192
+ attribute \src "ls180.v:1080.5-1080.58"
+ process $proc$ls180.v:1080$3204
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0]
sync init
end
- attribute \src "ls180.v:1066.11-1066.64"
- process $proc$ls180.v:1066$3193
+ attribute \src "ls180.v:1082.11-1082.64"
+ process $proc$ls180.v:1082$3205
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0]
sync init
end
- attribute \src "ls180.v:1067.5-1067.59"
- process $proc$ls180.v:1067$3194
+ attribute \src "ls180.v:1083.5-1083.59"
+ process $proc$ls180.v:1083$3206
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0]
sync init
end
- attribute \src "ls180.v:1069.5-1069.48"
- process $proc$ls180.v:1069$3195
+ attribute \src "ls180.v:1085.5-1085.48"
+ process $proc$ls180.v:1085$3207
assign { } { }
assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0]
end
- attribute \src "ls180.v:1070.5-1070.50"
- process $proc$ls180.v:1070$3196
+ attribute \src "ls180.v:1086.5-1086.50"
+ process $proc$ls180.v:1086$3208
assign { } { }
assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
end
- attribute \src "ls180.v:1071.5-1071.51"
- process $proc$ls180.v:1071$3197
+ attribute \src "ls180.v:1087.5-1087.51"
+ process $proc$ls180.v:1087$3209
assign { } { }
assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
end
- attribute \src "ls180.v:1072.11-1072.57"
- process $proc$ls180.v:1072$3198
+ attribute \src "ls180.v:1088.11-1088.57"
+ process $proc$ls180.v:1088$3210
assign { } { }
assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0]
sync init
end
- attribute \src "ls180.v:1073.5-1073.52"
- process $proc$ls180.v:1073$3199
+ attribute \src "ls180.v:1089.5-1089.52"
+ process $proc$ls180.v:1089$3211
assign { } { }
assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0]
sync init
end
- attribute \src "ls180.v:1074.5-1074.38"
- process $proc$ls180.v:1074$3200
+ attribute \src "ls180.v:1090.5-1090.38"
+ process $proc$ls180.v:1090$3212
assign { } { }
assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0]
end
- attribute \src "ls180.v:1075.5-1075.38"
- process $proc$ls180.v:1075$3201
+ attribute \src "ls180.v:1091.5-1091.38"
+ process $proc$ls180.v:1091$3213
assign { } { }
assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0]
end
- attribute \src "ls180.v:1076.5-1076.37"
- process $proc$ls180.v:1076$3202
+ attribute \src "ls180.v:1092.5-1092.37"
+ process $proc$ls180.v:1092$3214
assign { } { }
assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0]
end
- attribute \src "ls180.v:1077.11-1077.53"
- process $proc$ls180.v:1077$3203
+ attribute \src "ls180.v:1093.11-1093.53"
+ process $proc$ls180.v:1093$3215
assign { } { }
assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0]
end
- attribute \src "ls180.v:1078.5-1078.40"
- process $proc$ls180.v:1078$3204
+ attribute \src "ls180.v:1094.5-1094.40"
+ process $proc$ls180.v:1094$3216
assign { } { }
assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0]
end
- attribute \src "ls180.v:1079.5-1079.40"
- process $proc$ls180.v:1079$3205
+ attribute \src "ls180.v:1095.5-1095.40"
+ process $proc$ls180.v:1095$3217
assign { } { }
assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0]
end
- attribute \src "ls180.v:1080.5-1080.39"
- process $proc$ls180.v:1080$3206
+ attribute \src "ls180.v:1096.5-1096.39"
+ process $proc$ls180.v:1096$3218
assign { } { }
assign $1\main_sdphy_cmdr_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0]
end
- attribute \src "ls180.v:1081.11-1081.53"
- process $proc$ls180.v:1081$3207
+ attribute \src "ls180.v:1097.11-1097.53"
+ process $proc$ls180.v:1097$3219
assign { } { }
assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0]
end
- attribute \src "ls180.v:1082.11-1082.55"
- process $proc$ls180.v:1082$3208
+ attribute \src "ls180.v:1098.11-1098.55"
+ process $proc$ls180.v:1098$3220
assign { } { }
assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000
sync always
sync init
update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0]
end
- attribute \src "ls180.v:1083.12-1083.48"
- process $proc$ls180.v:1083$3209
+ attribute \src "ls180.v:1099.12-1099.48"
+ process $proc$ls180.v:1099$3221
assign { } { }
assign $1\main_sdphy_cmdr_timeout[31:0] 500000
sync always
sync init
update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0]
end
- attribute \src "ls180.v:1084.11-1084.39"
- process $proc$ls180.v:1084$3210
+ attribute \src "ls180.v:1100.11-1100.39"
+ process $proc$ls180.v:1100$3222
assign { } { }
assign $1\main_sdphy_cmdr_count[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0]
end
- attribute \src "ls180.v:1086.5-1086.46"
- process $proc$ls180.v:1086$3211
+ attribute \src "ls180.v:1102.5-1102.46"
+ process $proc$ls180.v:1102$3223
assign { } { }
assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0]
sync init
end
- attribute \src "ls180.v:1097.5-1097.53"
- process $proc$ls180.v:1097$3212
+ attribute \src "ls180.v:1113.5-1113.53"
+ process $proc$ls180.v:1113$3224
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
end
- attribute \src "ls180.v:110.5-110.49"
- process $proc$ls180.v:110$2775
- assign { } { }
- assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0]
- end
- attribute \src "ls180.v:1102.5-1102.36"
- process $proc$ls180.v:1102$3213
+ attribute \src "ls180.v:1118.5-1118.36"
+ process $proc$ls180.v:1118$3225
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0]
end
- attribute \src "ls180.v:1105.5-1105.53"
- process $proc$ls180.v:1105$3214
+ attribute \src "ls180.v:1121.5-1121.53"
+ process $proc$ls180.v:1121$3226
assign { } { }
assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:1106.5-1106.52"
- process $proc$ls180.v:1106$3215
+ attribute \src "ls180.v:1122.5-1122.52"
+ process $proc$ls180.v:1122$3227
assign { } { }
assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:1110.5-1110.55"
- process $proc$ls180.v:1110$3216
+ attribute \src "ls180.v:1126.5-1126.55"
+ process $proc$ls180.v:1126$3228
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
end
- attribute \src "ls180.v:1111.5-1111.54"
- process $proc$ls180.v:1111$3217
+ attribute \src "ls180.v:1127.5-1127.54"
+ process $proc$ls180.v:1127$3229
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
end
- attribute \src "ls180.v:1112.11-1112.68"
- process $proc$ls180.v:1112$3218
+ attribute \src "ls180.v:1128.11-1128.68"
+ process $proc$ls180.v:1128$3230
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
end
- attribute \src "ls180.v:1113.11-1113.81"
- process $proc$ls180.v:1113$3219
+ attribute \src "ls180.v:1129.11-1129.81"
+ process $proc$ls180.v:1129$3231
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000
sync always
sync init
update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
end
- attribute \src "ls180.v:1114.11-1114.54"
- process $proc$ls180.v:1114$3220
+ attribute \src "ls180.v:1130.11-1130.54"
+ process $proc$ls180.v:1130$3232
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
sync always
sync init
update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0]
end
- attribute \src "ls180.v:1116.5-1116.53"
- process $proc$ls180.v:1116$3221
+ attribute \src "ls180.v:1132.5-1132.53"
+ process $proc$ls180.v:1132$3233
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
end
- attribute \src "ls180.v:112.5-112.49"
- process $proc$ls180.v:112$2776
- assign { } { }
- assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0
- sync always
- update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0]
- sync init
- end
- attribute \src "ls180.v:1127.5-1127.49"
- process $proc$ls180.v:1127$3222
+ attribute \src "ls180.v:1143.5-1143.49"
+ process $proc$ls180.v:1143$3234
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
end
- attribute \src "ls180.v:1129.5-1129.49"
- process $proc$ls180.v:1129$3223
+ attribute \src "ls180.v:1145.5-1145.49"
+ process $proc$ls180.v:1145$3235
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
end
- attribute \src "ls180.v:1130.5-1130.48"
- process $proc$ls180.v:1130$3224
+ attribute \src "ls180.v:1146.5-1146.48"
+ process $proc$ls180.v:1146$3236
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
end
- attribute \src "ls180.v:1131.11-1131.62"
- process $proc$ls180.v:1131$3225
+ attribute \src "ls180.v:1147.11-1147.62"
+ process $proc$ls180.v:1147$3237
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
end
- attribute \src "ls180.v:1132.5-1132.38"
- process $proc$ls180.v:1132$3226
+ attribute \src "ls180.v:1148.5-1148.38"
+ process $proc$ls180.v:1148$3238
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0]
end
- attribute \src "ls180.v:1137.5-1137.49"
- process $proc$ls180.v:1137$3227
+ attribute \src "ls180.v:1153.5-1153.49"
+ process $proc$ls180.v:1153$3239
assign { } { }
assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0]
end
- attribute \src "ls180.v:1138.5-1138.51"
- process $proc$ls180.v:1138$3228
+ attribute \src "ls180.v:1154.5-1154.51"
+ process $proc$ls180.v:1154$3240
assign { } { }
assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0]
sync init
end
- attribute \src "ls180.v:1139.5-1139.52"
- process $proc$ls180.v:1139$3229
+ attribute \src "ls180.v:1155.5-1155.52"
+ process $proc$ls180.v:1155$3241
assign { } { }
assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0]
sync init
end
- attribute \src "ls180.v:1140.11-1140.58"
- process $proc$ls180.v:1140$3230
+ attribute \src "ls180.v:1156.11-1156.58"
+ process $proc$ls180.v:1156$3242
assign { } { }
assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
sync always
sync init
update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0]
end
- attribute \src "ls180.v:1141.5-1141.53"
- process $proc$ls180.v:1141$3231
+ attribute \src "ls180.v:1157.5-1157.53"
+ process $proc$ls180.v:1157$3243
assign { } { }
assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
end
- attribute \src "ls180.v:1142.5-1142.39"
- process $proc$ls180.v:1142$3232
+ attribute \src "ls180.v:1158.5-1158.39"
+ process $proc$ls180.v:1158$3244
assign { } { }
assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0]
end
- attribute \src "ls180.v:1143.5-1143.39"
- process $proc$ls180.v:1143$3233
+ attribute \src "ls180.v:1159.5-1159.39"
+ process $proc$ls180.v:1159$3245
assign { } { }
assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0]
end
- attribute \src "ls180.v:1144.5-1144.39"
- process $proc$ls180.v:1144$3234
+ attribute \src "ls180.v:116.5-116.49"
+ process $proc$ls180.v:116$2785
+ assign { } { }
+ assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0]
+ end
+ attribute \src "ls180.v:1160.5-1160.39"
+ process $proc$ls180.v:1160$3246
assign { } { }
assign $1\main_sdphy_dataw_sink_first[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0]
end
- attribute \src "ls180.v:1145.5-1145.38"
- process $proc$ls180.v:1145$3235
+ attribute \src "ls180.v:1161.5-1161.38"
+ process $proc$ls180.v:1161$3247
assign { } { }
assign $1\main_sdphy_dataw_sink_last[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0]
end
- attribute \src "ls180.v:1146.11-1146.52"
- process $proc$ls180.v:1146$3236
+ attribute \src "ls180.v:1162.11-1162.52"
+ process $proc$ls180.v:1162$3248
assign { } { }
assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0]
end
- attribute \src "ls180.v:1147.5-1147.33"
- process $proc$ls180.v:1147$3237
+ attribute \src "ls180.v:1163.5-1163.33"
+ process $proc$ls180.v:1163$3249
assign { } { }
assign $1\main_sdphy_dataw_stop[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0]
end
- attribute \src "ls180.v:1148.11-1148.40"
- process $proc$ls180.v:1148$3238
+ attribute \src "ls180.v:1164.11-1164.40"
+ process $proc$ls180.v:1164$3250
assign { } { }
assign $1\main_sdphy_dataw_count[7:0] 8'00000000
sync always
sync init
update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0]
end
- attribute \src "ls180.v:1149.5-1149.50"
- process $proc$ls180.v:1149$3239
+ attribute \src "ls180.v:1165.5-1165.50"
+ process $proc$ls180.v:1165$3251
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0]
sync init
end
- attribute \src "ls180.v:1151.5-1151.50"
- process $proc$ls180.v:1151$3240
+ attribute \src "ls180.v:1167.5-1167.50"
+ process $proc$ls180.v:1167$3252
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0]
sync init
end
- attribute \src "ls180.v:1152.5-1152.49"
- process $proc$ls180.v:1152$3241
+ attribute \src "ls180.v:1168.5-1168.49"
+ process $proc$ls180.v:1168$3253
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0]
sync init
end
- attribute \src "ls180.v:1153.5-1153.56"
- process $proc$ls180.v:1153$3242
+ attribute \src "ls180.v:1169.5-1169.56"
+ process $proc$ls180.v:1169$3254
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0]
sync init
end
- attribute \src "ls180.v:1154.5-1154.58"
- process $proc$ls180.v:1154$3243
+ attribute \src "ls180.v:1170.5-1170.58"
+ process $proc$ls180.v:1170$3255
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0]
sync init
end
- attribute \src "ls180.v:1155.5-1155.58"
- process $proc$ls180.v:1155$3244
+ attribute \src "ls180.v:1171.5-1171.58"
+ process $proc$ls180.v:1171$3256
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0]
sync init
end
- attribute \src "ls180.v:1156.5-1156.59"
- process $proc$ls180.v:1156$3245
+ attribute \src "ls180.v:1172.5-1172.59"
+ process $proc$ls180.v:1172$3257
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0]
sync init
end
- attribute \src "ls180.v:1157.11-1157.65"
- process $proc$ls180.v:1157$3246
+ attribute \src "ls180.v:1173.11-1173.65"
+ process $proc$ls180.v:1173$3258
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0]
sync init
end
- attribute \src "ls180.v:1158.11-1158.65"
- process $proc$ls180.v:1158$3247
+ attribute \src "ls180.v:1174.11-1174.65"
+ process $proc$ls180.v:1174$3259
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0]
sync init
end
- attribute \src "ls180.v:1159.5-1159.60"
- process $proc$ls180.v:1159$3248
+ attribute \src "ls180.v:1175.5-1175.60"
+ process $proc$ls180.v:1175$3260
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0]
sync init
end
- attribute \src "ls180.v:1160.5-1160.34"
- process $proc$ls180.v:1160$3249
+ attribute \src "ls180.v:1176.5-1176.34"
+ process $proc$ls180.v:1176$3261
assign { } { }
assign $1\main_sdphy_dataw_start[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0]
end
- attribute \src "ls180.v:1161.5-1161.34"
- process $proc$ls180.v:1161$3250
+ attribute \src "ls180.v:1177.5-1177.34"
+ process $proc$ls180.v:1177$3262
assign { } { }
assign $1\main_sdphy_dataw_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0]
end
- attribute \src "ls180.v:1162.5-1162.34"
- process $proc$ls180.v:1162$3251
+ attribute \src "ls180.v:1178.5-1178.34"
+ process $proc$ls180.v:1178$3263
assign { } { }
assign $1\main_sdphy_dataw_error[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0]
end
- attribute \src "ls180.v:1164.5-1164.47"
- process $proc$ls180.v:1164$3252
+ attribute \src "ls180.v:118.5-118.49"
+ process $proc$ls180.v:118$2786
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0
+ sync always
+ update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:1180.5-1180.47"
+ process $proc$ls180.v:1180$3264
assign { } { }
assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0]
sync init
end
- attribute \src "ls180.v:1175.5-1175.54"
- process $proc$ls180.v:1175$3253
+ attribute \src "ls180.v:1191.5-1191.54"
+ process $proc$ls180.v:1191$3265
assign { } { }
assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0]
end
- attribute \src "ls180.v:1180.5-1180.37"
- process $proc$ls180.v:1180$3254
+ attribute \src "ls180.v:1196.5-1196.37"
+ process $proc$ls180.v:1196$3266
assign { } { }
assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0]
end
- attribute \src "ls180.v:1183.5-1183.54"
- process $proc$ls180.v:1183$3255
+ attribute \src "ls180.v:1199.5-1199.54"
+ process $proc$ls180.v:1199$3267
assign { } { }
assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:1184.5-1184.53"
- process $proc$ls180.v:1184$3256
+ attribute \src "ls180.v:1200.5-1200.53"
+ process $proc$ls180.v:1200$3268
assign { } { }
assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:1188.5-1188.56"
- process $proc$ls180.v:1188$3257
+ attribute \src "ls180.v:1204.5-1204.56"
+ process $proc$ls180.v:1204$3269
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0]
end
- attribute \src "ls180.v:1189.5-1189.55"
- process $proc$ls180.v:1189$3258
+ attribute \src "ls180.v:1205.5-1205.55"
+ process $proc$ls180.v:1205$3270
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0]
end
- attribute \src "ls180.v:1190.11-1190.69"
- process $proc$ls180.v:1190$3259
+ attribute \src "ls180.v:1206.11-1206.69"
+ process $proc$ls180.v:1206$3271
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
end
- attribute \src "ls180.v:1191.11-1191.82"
- process $proc$ls180.v:1191$3260
+ attribute \src "ls180.v:1207.11-1207.82"
+ process $proc$ls180.v:1207$3272
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000
sync always
sync init
update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
end
- attribute \src "ls180.v:1192.11-1192.55"
- process $proc$ls180.v:1192$3261
+ attribute \src "ls180.v:1208.11-1208.55"
+ process $proc$ls180.v:1208$3273
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
sync always
sync init
update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0]
end
- attribute \src "ls180.v:1194.5-1194.54"
- process $proc$ls180.v:1194$3262
+ attribute \src "ls180.v:1210.5-1210.54"
+ process $proc$ls180.v:1210$3274
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
end
- attribute \src "ls180.v:120.5-120.65"
- process $proc$ls180.v:120$2777
- assign { } { }
- assign $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1
- sync always
- sync init
- update \main_libresocsim_libresoc_constraintmanager0_uart0_tx $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0]
- end
- attribute \src "ls180.v:1205.5-1205.50"
- process $proc$ls180.v:1205$3263
+ attribute \src "ls180.v:1221.5-1221.50"
+ process $proc$ls180.v:1221$3275
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0]
end
- attribute \src "ls180.v:1207.5-1207.50"
- process $proc$ls180.v:1207$3264
+ attribute \src "ls180.v:1223.5-1223.50"
+ process $proc$ls180.v:1223$3276
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0]
end
- attribute \src "ls180.v:1208.5-1208.49"
- process $proc$ls180.v:1208$3265
+ attribute \src "ls180.v:1224.5-1224.49"
+ process $proc$ls180.v:1224$3277
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0]
end
- attribute \src "ls180.v:1209.11-1209.63"
- process $proc$ls180.v:1209$3266
+ attribute \src "ls180.v:1225.11-1225.63"
+ process $proc$ls180.v:1225$3278
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
end
- attribute \src "ls180.v:1210.5-1210.39"
- process $proc$ls180.v:1210$3267
+ attribute \src "ls180.v:1226.5-1226.39"
+ process $proc$ls180.v:1226$3279
assign { } { }
assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0]
end
- attribute \src "ls180.v:1213.5-1213.50"
- process $proc$ls180.v:1213$3268
+ attribute \src "ls180.v:1229.5-1229.50"
+ process $proc$ls180.v:1229$3280
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0
sync always
update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0]
sync init
end
- attribute \src "ls180.v:1214.5-1214.49"
- process $proc$ls180.v:1214$3269
+ attribute \src "ls180.v:1230.5-1230.49"
+ process $proc$ls180.v:1230$3281
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0
sync always
update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0]
sync init
end
- attribute \src "ls180.v:1215.5-1215.56"
- process $proc$ls180.v:1215$3270
+ attribute \src "ls180.v:1231.5-1231.56"
+ process $proc$ls180.v:1231$3282
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0
sync always
update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0]
sync init
end
- attribute \src "ls180.v:1217.5-1217.58"
- process $proc$ls180.v:1217$3271
+ attribute \src "ls180.v:1233.5-1233.58"
+ process $proc$ls180.v:1233$3283
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0]
sync init
end
- attribute \src "ls180.v:1218.5-1218.59"
- process $proc$ls180.v:1218$3272
+ attribute \src "ls180.v:1234.5-1234.59"
+ process $proc$ls180.v:1234$3284
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0]
sync init
end
- attribute \src "ls180.v:1220.11-1220.65"
- process $proc$ls180.v:1220$3273
+ attribute \src "ls180.v:1236.11-1236.65"
+ process $proc$ls180.v:1236$3285
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0]
sync init
end
- attribute \src "ls180.v:1221.5-1221.60"
- process $proc$ls180.v:1221$3274
+ attribute \src "ls180.v:1237.5-1237.60"
+ process $proc$ls180.v:1237$3286
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0]
sync init
end
- attribute \src "ls180.v:1223.5-1223.49"
- process $proc$ls180.v:1223$3275
+ attribute \src "ls180.v:1239.5-1239.49"
+ process $proc$ls180.v:1239$3287
assign { } { }
assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0]
end
- attribute \src "ls180.v:1224.5-1224.51"
- process $proc$ls180.v:1224$3276
+ attribute \src "ls180.v:1240.5-1240.51"
+ process $proc$ls180.v:1240$3288
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0]
sync init
end
- attribute \src "ls180.v:1225.5-1225.52"
- process $proc$ls180.v:1225$3277
+ attribute \src "ls180.v:1241.5-1241.52"
+ process $proc$ls180.v:1241$3289
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0]
sync init
end
- attribute \src "ls180.v:1226.11-1226.58"
- process $proc$ls180.v:1226$3278
+ attribute \src "ls180.v:1242.11-1242.58"
+ process $proc$ls180.v:1242$3290
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0]
sync init
end
- attribute \src "ls180.v:1227.5-1227.53"
- process $proc$ls180.v:1227$3279
+ attribute \src "ls180.v:1243.5-1243.53"
+ process $proc$ls180.v:1243$3291
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0]
sync init
end
- attribute \src "ls180.v:1228.5-1228.39"
- process $proc$ls180.v:1228$3280
+ attribute \src "ls180.v:1244.5-1244.39"
+ process $proc$ls180.v:1244$3292
assign { } { }
assign $1\main_sdphy_datar_sink_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0]
end
- attribute \src "ls180.v:1229.5-1229.39"
- process $proc$ls180.v:1229$3281
+ attribute \src "ls180.v:1245.5-1245.39"
+ process $proc$ls180.v:1245$3293
assign { } { }
assign $1\main_sdphy_datar_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0]
end
- attribute \src "ls180.v:1230.5-1230.38"
- process $proc$ls180.v:1230$3282
+ attribute \src "ls180.v:1246.5-1246.38"
+ process $proc$ls180.v:1246$3294
assign { } { }
assign $1\main_sdphy_datar_sink_last[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0]
end
- attribute \src "ls180.v:1231.11-1231.61"
- process $proc$ls180.v:1231$3283
+ attribute \src "ls180.v:1247.11-1247.61"
+ process $proc$ls180.v:1247$3295
assign { } { }
assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000
sync always
sync init
update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0]
end
- attribute \src "ls180.v:1232.5-1232.41"
- process $proc$ls180.v:1232$3284
+ attribute \src "ls180.v:1248.5-1248.41"
+ process $proc$ls180.v:1248$3296
assign { } { }
assign $1\main_sdphy_datar_source_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0]
end
- attribute \src "ls180.v:1233.5-1233.41"
- process $proc$ls180.v:1233$3285
+ attribute \src "ls180.v:1249.5-1249.41"
+ process $proc$ls180.v:1249$3297
assign { } { }
assign $1\main_sdphy_datar_source_ready[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0]
end
- attribute \src "ls180.v:1234.5-1234.41"
- process $proc$ls180.v:1234$3286
+ attribute \src "ls180.v:1250.5-1250.41"
+ process $proc$ls180.v:1250$3298
assign { } { }
assign $0\main_sdphy_datar_source_first[0:0] 1'0
sync always
update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0]
sync init
end
- attribute \src "ls180.v:1235.5-1235.40"
- process $proc$ls180.v:1235$3287
+ attribute \src "ls180.v:1251.5-1251.40"
+ process $proc$ls180.v:1251$3299
assign { } { }
assign $1\main_sdphy_datar_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0]
end
- attribute \src "ls180.v:1236.11-1236.54"
- process $proc$ls180.v:1236$3288
+ attribute \src "ls180.v:1252.11-1252.54"
+ process $proc$ls180.v:1252$3300
assign { } { }
assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0]
end
- attribute \src "ls180.v:1237.11-1237.56"
- process $proc$ls180.v:1237$3289
+ attribute \src "ls180.v:1253.11-1253.56"
+ process $proc$ls180.v:1253$3301
assign { } { }
assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000
sync always
sync init
update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0]
end
- attribute \src "ls180.v:1238.5-1238.33"
- process $proc$ls180.v:1238$3290
+ attribute \src "ls180.v:1254.5-1254.33"
+ process $proc$ls180.v:1254$3302
assign { } { }
assign $1\main_sdphy_datar_stop[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0]
end
- attribute \src "ls180.v:1239.12-1239.49"
- process $proc$ls180.v:1239$3291
+ attribute \src "ls180.v:1255.12-1255.49"
+ process $proc$ls180.v:1255$3303
assign { } { }
assign $1\main_sdphy_datar_timeout[31:0] 500000
sync always
sync init
update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0]
end
- attribute \src "ls180.v:1240.11-1240.41"
- process $proc$ls180.v:1240$3292
+ attribute \src "ls180.v:1256.11-1256.41"
+ process $proc$ls180.v:1256$3304
assign { } { }
assign $1\main_sdphy_datar_count[9:0] 10'0000000000
sync always
sync init
update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0]
end
- attribute \src "ls180.v:1242.5-1242.48"
- process $proc$ls180.v:1242$3293
+ attribute \src "ls180.v:1258.5-1258.48"
+ process $proc$ls180.v:1258$3305
assign { } { }
assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0
sync always
update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0]
sync init
end
- attribute \src "ls180.v:1253.5-1253.55"
- process $proc$ls180.v:1253$3294
+ attribute \src "ls180.v:1269.5-1269.55"
+ process $proc$ls180.v:1269$3306
assign { } { }
assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0]
end
- attribute \src "ls180.v:1258.5-1258.38"
- process $proc$ls180.v:1258$3295
+ attribute \src "ls180.v:1274.5-1274.38"
+ process $proc$ls180.v:1274$3307
assign { } { }
assign $1\main_sdphy_datar_datar_run[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0]
end
- attribute \src "ls180.v:1261.5-1261.55"
- process $proc$ls180.v:1261$3296
+ attribute \src "ls180.v:1277.5-1277.55"
+ process $proc$ls180.v:1277$3308
assign { } { }
assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0
sync always
update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:1262.5-1262.54"
- process $proc$ls180.v:1262$3297
+ attribute \src "ls180.v:1278.5-1278.54"
+ process $proc$ls180.v:1278$3309
assign { } { }
assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0
sync always
update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:1266.5-1266.57"
- process $proc$ls180.v:1266$3298
+ attribute \src "ls180.v:128.5-128.65"
+ process $proc$ls180.v:128$2787
+ assign { } { }
+ assign $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1
+ sync always
+ sync init
+ update \main_libresocsim_libresoc_constraintmanager0_uart0_tx $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0]
+ end
+ attribute \src "ls180.v:1282.5-1282.57"
+ process $proc$ls180.v:1282$3310
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0]
end
- attribute \src "ls180.v:1267.5-1267.56"
- process $proc$ls180.v:1267$3299
+ attribute \src "ls180.v:1283.5-1283.56"
+ process $proc$ls180.v:1283$3311
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0]
end
- attribute \src "ls180.v:1268.11-1268.70"
- process $proc$ls180.v:1268$3300
+ attribute \src "ls180.v:1284.11-1284.70"
+ process $proc$ls180.v:1284$3312
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0]
end
- attribute \src "ls180.v:1269.11-1269.83"
- process $proc$ls180.v:1269$3301
+ attribute \src "ls180.v:1285.11-1285.83"
+ process $proc$ls180.v:1285$3313
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00
sync always
sync init
update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
end
- attribute \src "ls180.v:1270.5-1270.50"
- process $proc$ls180.v:1270$3302
+ attribute \src "ls180.v:1286.5-1286.50"
+ process $proc$ls180.v:1286$3314
assign { } { }
assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0]
end
- attribute \src "ls180.v:1272.5-1272.55"
- process $proc$ls180.v:1272$3303
+ attribute \src "ls180.v:1288.5-1288.55"
+ process $proc$ls180.v:1288$3315
assign { } { }
assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0]
end
- attribute \src "ls180.v:1283.5-1283.51"
- process $proc$ls180.v:1283$3304
+ attribute \src "ls180.v:1299.5-1299.51"
+ process $proc$ls180.v:1299$3316
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0]
end
- attribute \src "ls180.v:1285.5-1285.51"
- process $proc$ls180.v:1285$3305
+ attribute \src "ls180.v:1301.5-1301.51"
+ process $proc$ls180.v:1301$3317
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0]
end
- attribute \src "ls180.v:1286.5-1286.50"
- process $proc$ls180.v:1286$3306
+ attribute \src "ls180.v:1302.5-1302.50"
+ process $proc$ls180.v:1302$3318
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0]
end
- attribute \src "ls180.v:1287.11-1287.64"
- process $proc$ls180.v:1287$3307
+ attribute \src "ls180.v:1303.11-1303.64"
+ process $proc$ls180.v:1303$3319
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0]
end
- attribute \src "ls180.v:1288.5-1288.40"
- process $proc$ls180.v:1288$3308
+ attribute \src "ls180.v:1304.5-1304.40"
+ process $proc$ls180.v:1304$3320
assign { } { }
assign $1\main_sdphy_datar_datar_reset[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0]
end
- attribute \src "ls180.v:1290.5-1290.35"
- process $proc$ls180.v:1290$3309
+ attribute \src "ls180.v:1306.5-1306.35"
+ process $proc$ls180.v:1306$3321
assign { } { }
assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0
sync always
sync init
update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0]
end
- attribute \src "ls180.v:1293.11-1293.42"
- process $proc$ls180.v:1293$3310
+ attribute \src "ls180.v:1309.11-1309.42"
+ process $proc$ls180.v:1309$3322
assign { } { }
assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000
sync always
sync init
update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0]
end
- attribute \src "ls180.v:130.12-130.71"
- process $proc$ls180.v:130$2778
- assign { } { }
- assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
- sync always
- sync init
- update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0]
- end
- attribute \src "ls180.v:1306.12-1306.52"
- process $proc$ls180.v:1306$3311
+ attribute \src "ls180.v:1322.12-1322.52"
+ process $proc$ls180.v:1322$3323
assign { } { }
assign $1\main_sdcore_cmd_argument_storage[31:0] 0
sync always
sync init
update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0]
end
- attribute \src "ls180.v:1307.5-1307.39"
- process $proc$ls180.v:1307$3312
+ attribute \src "ls180.v:1323.5-1323.39"
+ process $proc$ls180.v:1323$3324
assign { } { }
assign $1\main_sdcore_cmd_argument_re[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0]
end
- attribute \src "ls180.v:1308.12-1308.51"
- process $proc$ls180.v:1308$3313
+ attribute \src "ls180.v:1324.12-1324.51"
+ process $proc$ls180.v:1324$3325
assign { } { }
assign $1\main_sdcore_cmd_command_storage[31:0] 0
sync always
sync init
update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0]
end
- attribute \src "ls180.v:1309.5-1309.38"
- process $proc$ls180.v:1309$3314
+ attribute \src "ls180.v:1325.5-1325.38"
+ process $proc$ls180.v:1325$3326
assign { } { }
assign $1\main_sdcore_cmd_command_re[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0]
end
- attribute \src "ls180.v:131.12-131.73"
- process $proc$ls180.v:131$2779
- assign { } { }
- assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0
- sync always
- sync init
- update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0]
- end
- attribute \src "ls180.v:1313.5-1313.34"
- process $proc$ls180.v:1313$3315
+ attribute \src "ls180.v:1329.5-1329.34"
+ process $proc$ls180.v:1329$3327
assign { } { }
assign $0\main_sdcore_cmd_send_w[0:0] 1'0
sync always
update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0]
sync init
end
- attribute \src "ls180.v:1314.13-1314.53"
- process $proc$ls180.v:1314$3316
+ attribute \src "ls180.v:1330.13-1330.53"
+ process $proc$ls180.v:1330$3328
assign { } { }
assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0]
end
- attribute \src "ls180.v:1320.11-1320.51"
- process $proc$ls180.v:1320$3317
+ attribute \src "ls180.v:1336.11-1336.51"
+ process $proc$ls180.v:1336$3329
assign { } { }
assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000
sync always
sync init
update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0]
end
- attribute \src "ls180.v:1321.5-1321.39"
- process $proc$ls180.v:1321$3318
+ attribute \src "ls180.v:1337.5-1337.39"
+ process $proc$ls180.v:1337$3330
assign { } { }
assign $1\main_sdcore_block_length_re[0:0] 1'0
sync always
sync init
update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0]
end
- attribute \src "ls180.v:1322.12-1322.51"
- process $proc$ls180.v:1322$3319
+ attribute \src "ls180.v:1338.12-1338.51"
+ process $proc$ls180.v:1338$3331
assign { } { }
assign $1\main_sdcore_block_count_storage[31:0] 0
sync always
sync init
update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0]
end
- attribute \src "ls180.v:1323.5-1323.38"
- process $proc$ls180.v:1323$3320
+ attribute \src "ls180.v:1339.5-1339.38"
+ process $proc$ls180.v:1339$3332
assign { } { }
assign $1\main_sdcore_block_count_re[0:0] 1'0
sync always
sync init
update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0]
end
- attribute \src "ls180.v:1324.11-1324.51"
- process $proc$ls180.v:1324$3321
+ attribute \src "ls180.v:1340.11-1340.51"
+ process $proc$ls180.v:1340$3333
assign { } { }
assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000
sync always
sync init
update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0]
end
- attribute \src "ls180.v:133.11-133.69"
- process $proc$ls180.v:133$2780
+ attribute \src "ls180.v:138.12-138.71"
+ process $proc$ls180.v:138$2788
assign { } { }
- assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
- sync always
- sync init
- update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0]
- end
- attribute \src "ls180.v:134.5-134.63"
- process $proc$ls180.v:134$2781
- assign { } { }
- assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0]
- end
- attribute \src "ls180.v:135.5-135.63"
- process $proc$ls180.v:135$2782
- assign { } { }
- assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
+ assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
sync always
sync init
- update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0]
+ update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0]
end
- attribute \src "ls180.v:1366.11-1366.47"
- process $proc$ls180.v:1366$3322
+ attribute \src "ls180.v:1382.11-1382.47"
+ process $proc$ls180.v:1382$3334
assign { } { }
assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000
sync always
sync init
update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0]
end
- attribute \src "ls180.v:137.5-137.62"
- process $proc$ls180.v:137$2783
+ attribute \src "ls180.v:1386.5-1386.49"
+ process $proc$ls180.v:1386$3335
assign { } { }
- assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
+ assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
sync always
sync init
- update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0]
+ update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0]
end
- attribute \src "ls180.v:1370.5-1370.49"
- process $proc$ls180.v:1370$3323
+ attribute \src "ls180.v:139.12-139.73"
+ process $proc$ls180.v:139$2789
assign { } { }
- assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
+ assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0
sync always
sync init
- update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0]
+ update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0]
end
- attribute \src "ls180.v:1374.5-1374.51"
- process $proc$ls180.v:1374$3324
+ attribute \src "ls180.v:1390.5-1390.51"
+ process $proc$ls180.v:1390$3336
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0]
end
- attribute \src "ls180.v:1375.5-1375.51"
- process $proc$ls180.v:1375$3325
+ attribute \src "ls180.v:1391.5-1391.51"
+ process $proc$ls180.v:1391$3337
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0]
end
- attribute \src "ls180.v:1376.5-1376.51"
- process $proc$ls180.v:1376$3326
+ attribute \src "ls180.v:1392.5-1392.51"
+ process $proc$ls180.v:1392$3338
assign { } { }
assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0]
sync init
end
- attribute \src "ls180.v:1377.5-1377.50"
- process $proc$ls180.v:1377$3327
+ attribute \src "ls180.v:1393.5-1393.50"
+ process $proc$ls180.v:1393$3339
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0]
end
- attribute \src "ls180.v:1378.11-1378.64"
- process $proc$ls180.v:1378$3328
+ attribute \src "ls180.v:1394.11-1394.64"
+ process $proc$ls180.v:1394$3340
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0]
end
- attribute \src "ls180.v:1379.11-1379.48"
- process $proc$ls180.v:1379$3329
+ attribute \src "ls180.v:1395.11-1395.48"
+ process $proc$ls180.v:1395$3341
assign { } { }
assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000
sync always
sync init
update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0]
end
- attribute \src "ls180.v:138.11-138.69"
- process $proc$ls180.v:138$2784
- assign { } { }
- assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000
- sync always
- update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0]
- sync init
- end
- attribute \src "ls180.v:1380.12-1380.59"
- process $proc$ls180.v:1380$3330
+ attribute \src "ls180.v:1396.12-1396.59"
+ process $proc$ls180.v:1396$3342
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
end
- attribute \src "ls180.v:1384.12-1384.55"
- process $proc$ls180.v:1384$3331
+ attribute \src "ls180.v:1400.12-1400.55"
+ process $proc$ls180.v:1400$3343
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0]
end
- attribute \src "ls180.v:1387.12-1387.59"
- process $proc$ls180.v:1387$3332
+ attribute \src "ls180.v:1403.12-1403.59"
+ process $proc$ls180.v:1403$3344
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
end
- attribute \src "ls180.v:139.11-139.69"
- process $proc$ls180.v:139$2785
+ attribute \src "ls180.v:1407.12-1407.55"
+ process $proc$ls180.v:1407$3345
assign { } { }
- assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00
+ assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000
sync always
- update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0]
sync init
+ update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
end
- attribute \src "ls180.v:1391.12-1391.55"
- process $proc$ls180.v:1391$3333
+ attribute \src "ls180.v:141.11-141.69"
+ process $proc$ls180.v:141$2790
assign { } { }
- assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000
+ assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
sync always
sync init
- update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
+ update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0]
end
- attribute \src "ls180.v:1394.12-1394.59"
- process $proc$ls180.v:1394$3334
+ attribute \src "ls180.v:1410.12-1410.59"
+ process $proc$ls180.v:1410$3346
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
end
- attribute \src "ls180.v:1398.12-1398.55"
- process $proc$ls180.v:1398$3335
+ attribute \src "ls180.v:1414.12-1414.55"
+ process $proc$ls180.v:1414$3347
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0]
end
- attribute \src "ls180.v:1401.12-1401.59"
- process $proc$ls180.v:1401$3336
+ attribute \src "ls180.v:1417.12-1417.59"
+ process $proc$ls180.v:1417$3348
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
end
- attribute \src "ls180.v:1405.12-1405.55"
- process $proc$ls180.v:1405$3337
+ attribute \src "ls180.v:142.5-142.63"
+ process $proc$ls180.v:142$2791
+ assign { } { }
+ assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0]
+ end
+ attribute \src "ls180.v:1421.12-1421.55"
+ process $proc$ls180.v:1421$3349
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0]
end
- attribute \src "ls180.v:1408.12-1408.54"
- process $proc$ls180.v:1408$3338
+ attribute \src "ls180.v:1424.12-1424.54"
+ process $proc$ls180.v:1424$3350
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0]
end
- attribute \src "ls180.v:1409.12-1409.54"
- process $proc$ls180.v:1409$3339
+ attribute \src "ls180.v:1425.12-1425.54"
+ process $proc$ls180.v:1425$3351
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0]
end
- attribute \src "ls180.v:141.5-141.44"
- process $proc$ls180.v:141$2786
- assign { } { }
- assign $1\main_libresocsim_converter0_skip[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0]
- end
- attribute \src "ls180.v:1410.12-1410.54"
- process $proc$ls180.v:1410$3340
+ attribute \src "ls180.v:1426.12-1426.54"
+ process $proc$ls180.v:1426$3352
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0]
end
- attribute \src "ls180.v:1411.12-1411.54"
- process $proc$ls180.v:1411$3341
+ attribute \src "ls180.v:1427.12-1427.54"
+ process $proc$ls180.v:1427$3353
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0]
end
- attribute \src "ls180.v:1412.5-1412.48"
- process $proc$ls180.v:1412$3342
+ attribute \src "ls180.v:1428.5-1428.48"
+ process $proc$ls180.v:1428$3354
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0]
end
- attribute \src "ls180.v:1413.5-1413.48"
- process $proc$ls180.v:1413$3343
+ attribute \src "ls180.v:1429.5-1429.48"
+ process $proc$ls180.v:1429$3355
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0]
end
- attribute \src "ls180.v:1414.5-1414.48"
- process $proc$ls180.v:1414$3344
+ attribute \src "ls180.v:143.5-143.63"
+ process $proc$ls180.v:143$2792
+ assign { } { }
+ assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0]
+ end
+ attribute \src "ls180.v:1430.5-1430.48"
+ process $proc$ls180.v:1430$3356
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0]
end
- attribute \src "ls180.v:1415.5-1415.47"
- process $proc$ls180.v:1415$3345
+ attribute \src "ls180.v:1431.5-1431.47"
+ process $proc$ls180.v:1431$3357
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0]
end
- attribute \src "ls180.v:1416.11-1416.61"
- process $proc$ls180.v:1416$3346
+ attribute \src "ls180.v:1432.11-1432.61"
+ process $proc$ls180.v:1432$3358
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0]
end
- attribute \src "ls180.v:1417.5-1417.50"
- process $proc$ls180.v:1417$3347
+ attribute \src "ls180.v:1433.5-1433.50"
+ process $proc$ls180.v:1433$3359
assign { } { }
assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0]
end
- attribute \src "ls180.v:1419.5-1419.50"
- process $proc$ls180.v:1419$3348
+ attribute \src "ls180.v:1435.5-1435.50"
+ process $proc$ls180.v:1435$3360
assign { } { }
assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0]
sync init
end
- attribute \src "ls180.v:142.5-142.47"
- process $proc$ls180.v:142$2787
- assign { } { }
- assign $1\main_libresocsim_converter0_counter[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0]
- end
- attribute \src "ls180.v:1422.11-1422.47"
- process $proc$ls180.v:1422$3349
+ attribute \src "ls180.v:1438.11-1438.47"
+ process $proc$ls180.v:1438$3361
assign { } { }
assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000
sync always
sync init
update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0]
end
- attribute \src "ls180.v:1423.11-1423.47"
- process $proc$ls180.v:1423$3350
+ attribute \src "ls180.v:1439.11-1439.47"
+ process $proc$ls180.v:1439$3362
assign { } { }
assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000
sync always
sync init
update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0]
end
- attribute \src "ls180.v:1424.12-1424.58"
- process $proc$ls180.v:1424$3351
+ attribute \src "ls180.v:1440.12-1440.58"
+ process $proc$ls180.v:1440$3363
assign { } { }
assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
end
- attribute \src "ls180.v:1428.12-1428.54"
- process $proc$ls180.v:1428$3352
+ attribute \src "ls180.v:1444.12-1444.54"
+ process $proc$ls180.v:1444$3364
assign { } { }
assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0]
end
- attribute \src "ls180.v:1429.5-1429.46"
- process $proc$ls180.v:1429$3353
+ attribute \src "ls180.v:1445.5-1445.46"
+ process $proc$ls180.v:1445$3365
assign { } { }
assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0]
end
- attribute \src "ls180.v:1431.12-1431.58"
- process $proc$ls180.v:1431$3354
+ attribute \src "ls180.v:1447.12-1447.58"
+ process $proc$ls180.v:1447$3366
assign { } { }
assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
end
- attribute \src "ls180.v:1435.12-1435.54"
- process $proc$ls180.v:1435$3355
+ attribute \src "ls180.v:145.5-145.62"
+ process $proc$ls180.v:145$2793
+ assign { } { }
+ assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0]
+ end
+ attribute \src "ls180.v:1451.12-1451.54"
+ process $proc$ls180.v:1451$3367
assign { } { }
assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0]
end
- attribute \src "ls180.v:1436.5-1436.46"
- process $proc$ls180.v:1436$3356
+ attribute \src "ls180.v:1452.5-1452.46"
+ process $proc$ls180.v:1452$3368
assign { } { }
assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0]
end
- attribute \src "ls180.v:1438.12-1438.58"
- process $proc$ls180.v:1438$3357
+ attribute \src "ls180.v:1454.12-1454.58"
+ process $proc$ls180.v:1454$3369
assign { } { }
assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
end
- attribute \src "ls180.v:144.12-144.53"
- process $proc$ls180.v:144$2788
- assign { } { }
- assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- sync always
- sync init
- update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0]
- end
- attribute \src "ls180.v:1442.12-1442.54"
- process $proc$ls180.v:1442$3358
+ attribute \src "ls180.v:1458.12-1458.54"
+ process $proc$ls180.v:1458$3370
assign { } { }
assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0]
end
- attribute \src "ls180.v:1443.5-1443.46"
- process $proc$ls180.v:1443$3359
+ attribute \src "ls180.v:1459.5-1459.46"
+ process $proc$ls180.v:1459$3371
assign { } { }
assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0]
end
- attribute \src "ls180.v:1445.12-1445.58"
- process $proc$ls180.v:1445$3360
+ attribute \src "ls180.v:146.11-146.69"
+ process $proc$ls180.v:146$2794
assign { } { }
- assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
+ assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000
sync always
+ update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0]
sync init
- update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
end
- attribute \src "ls180.v:1449.12-1449.54"
- process $proc$ls180.v:1449$3361
+ attribute \src "ls180.v:1461.12-1461.58"
+ process $proc$ls180.v:1461$3372
assign { } { }
- assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000
+ assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
sync always
sync init
- update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0]
+ update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
end
- attribute \src "ls180.v:145.12-145.71"
- process $proc$ls180.v:145$2789
+ attribute \src "ls180.v:1465.12-1465.54"
+ process $proc$ls180.v:1465$3373
assign { } { }
- assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
+ assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000
sync always
sync init
- update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0]
+ update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0]
end
- attribute \src "ls180.v:1450.5-1450.46"
- process $proc$ls180.v:1450$3362
+ attribute \src "ls180.v:1466.5-1466.46"
+ process $proc$ls180.v:1466$3374
assign { } { }
assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0]
end
- attribute \src "ls180.v:1452.12-1452.53"
- process $proc$ls180.v:1452$3363
+ attribute \src "ls180.v:1468.12-1468.53"
+ process $proc$ls180.v:1468$3375
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0]
end
- attribute \src "ls180.v:1453.12-1453.53"
- process $proc$ls180.v:1453$3364
+ attribute \src "ls180.v:1469.12-1469.53"
+ process $proc$ls180.v:1469$3376
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0]
end
- attribute \src "ls180.v:1454.12-1454.53"
- process $proc$ls180.v:1454$3365
+ attribute \src "ls180.v:147.11-147.69"
+ process $proc$ls180.v:147$2795
+ assign { } { }
+ assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00
+ sync always
+ update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0]
+ sync init
+ end
+ attribute \src "ls180.v:1470.12-1470.53"
+ process $proc$ls180.v:1470$3377
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0]
end
- attribute \src "ls180.v:1455.12-1455.53"
- process $proc$ls180.v:1455$3366
+ attribute \src "ls180.v:1471.12-1471.53"
+ process $proc$ls180.v:1471$3378
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0]
end
- attribute \src "ls180.v:1456.5-1456.43"
- process $proc$ls180.v:1456$3367
+ attribute \src "ls180.v:1472.5-1472.43"
+ process $proc$ls180.v:1472$3379
assign { } { }
assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0]
end
- attribute \src "ls180.v:1457.12-1457.51"
- process $proc$ls180.v:1457$3368
+ attribute \src "ls180.v:1473.12-1473.51"
+ process $proc$ls180.v:1473$3380
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0]
end
- attribute \src "ls180.v:1458.12-1458.51"
- process $proc$ls180.v:1458$3369
+ attribute \src "ls180.v:1474.12-1474.51"
+ process $proc$ls180.v:1474$3381
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0]
end
- attribute \src "ls180.v:1459.12-1459.51"
- process $proc$ls180.v:1459$3370
+ attribute \src "ls180.v:1475.12-1475.51"
+ process $proc$ls180.v:1475$3382
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0]
end
- attribute \src "ls180.v:146.12-146.73"
- process $proc$ls180.v:146$2790
- assign { } { }
- assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0
- sync always
- sync init
- update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0]
- end
- attribute \src "ls180.v:1460.12-1460.51"
- process $proc$ls180.v:1460$3371
+ attribute \src "ls180.v:1476.12-1476.51"
+ process $proc$ls180.v:1476$3383
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0]
end
- attribute \src "ls180.v:1462.11-1462.39"
- process $proc$ls180.v:1462$3372
+ attribute \src "ls180.v:1478.11-1478.39"
+ process $proc$ls180.v:1478$3384
assign { } { }
assign $1\main_sdcore_cmd_count[2:0] 3'000
sync always
sync init
update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0]
end
- attribute \src "ls180.v:1463.5-1463.32"
- process $proc$ls180.v:1463$3373
+ attribute \src "ls180.v:1479.5-1479.32"
+ process $proc$ls180.v:1479$3385
assign { } { }
assign $1\main_sdcore_cmd_done[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0]
end
- attribute \src "ls180.v:1464.5-1464.33"
- process $proc$ls180.v:1464$3374
+ attribute \src "ls180.v:1480.5-1480.33"
+ process $proc$ls180.v:1480$3386
assign { } { }
assign $1\main_sdcore_cmd_error[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0]
end
- attribute \src "ls180.v:1465.5-1465.35"
- process $proc$ls180.v:1465$3375
+ attribute \src "ls180.v:1481.5-1481.35"
+ process $proc$ls180.v:1481$3387
assign { } { }
assign $1\main_sdcore_cmd_timeout[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0]
end
- attribute \src "ls180.v:1467.12-1467.42"
- process $proc$ls180.v:1467$3376
+ attribute \src "ls180.v:1483.12-1483.42"
+ process $proc$ls180.v:1483$3388
assign { } { }
assign $1\main_sdcore_data_count[31:0] 0
sync always
sync init
update \main_sdcore_data_count $1\main_sdcore_data_count[31:0]
end
- attribute \src "ls180.v:1468.5-1468.33"
- process $proc$ls180.v:1468$3377
+ attribute \src "ls180.v:1484.5-1484.33"
+ process $proc$ls180.v:1484$3389
assign { } { }
assign $1\main_sdcore_data_done[0:0] 1'0
sync always
sync init
update \main_sdcore_data_done $1\main_sdcore_data_done[0:0]
end
- attribute \src "ls180.v:1469.5-1469.34"
- process $proc$ls180.v:1469$3378
+ attribute \src "ls180.v:1485.5-1485.34"
+ process $proc$ls180.v:1485$3390
assign { } { }
assign $1\main_sdcore_data_error[0:0] 1'0
sync always
sync init
update \main_sdcore_data_error $1\main_sdcore_data_error[0:0]
end
- attribute \src "ls180.v:1470.5-1470.36"
- process $proc$ls180.v:1470$3379
+ attribute \src "ls180.v:1486.5-1486.36"
+ process $proc$ls180.v:1486$3391
assign { } { }
assign $1\main_sdcore_data_timeout[0:0] 1'0
sync always
sync init
update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0]
end
- attribute \src "ls180.v:1479.11-1479.41"
- process $proc$ls180.v:1479$3380
+ attribute \src "ls180.v:149.5-149.44"
+ process $proc$ls180.v:149$2796
assign { } { }
- assign $0\main_interface0_bus_cti[2:0] 3'000
+ assign $1\main_libresocsim_converter0_skip[0:0] 1'0
sync always
- update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0]
sync init
+ update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0]
end
- attribute \src "ls180.v:148.11-148.69"
- process $proc$ls180.v:148$2791
+ attribute \src "ls180.v:1495.11-1495.41"
+ process $proc$ls180.v:1495$3392
assign { } { }
- assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000
+ assign $0\main_interface0_bus_cti[2:0] 3'000
sync always
+ update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0]
sync init
- update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0]
end
- attribute \src "ls180.v:1480.11-1480.41"
- process $proc$ls180.v:1480$3381
+ attribute \src "ls180.v:1496.11-1496.41"
+ process $proc$ls180.v:1496$3393
assign { } { }
assign $0\main_interface0_bus_bte[1:0] 2'00
sync always
update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0]
sync init
end
- attribute \src "ls180.v:149.5-149.63"
- process $proc$ls180.v:149$2792
+ attribute \src "ls180.v:150.5-150.47"
+ process $proc$ls180.v:150$2797
assign { } { }
- assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0
+ assign $1\main_libresocsim_converter0_counter[0:0] 1'0
sync always
sync init
- update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0]
+ update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0]
end
- attribute \src "ls180.v:150.5-150.63"
- process $proc$ls180.v:150$2793
+ attribute \src "ls180.v:1519.11-1519.45"
+ process $proc$ls180.v:1519$3394
assign { } { }
- assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
+ assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000
sync always
sync init
- update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0]
+ update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0]
end
- attribute \src "ls180.v:1503.11-1503.45"
- process $proc$ls180.v:1503$3382
+ attribute \src "ls180.v:152.12-152.53"
+ process $proc$ls180.v:152$2798
assign { } { }
- assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000
+ assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0]
+ update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0]
end
- attribute \src "ls180.v:1504.5-1504.41"
- process $proc$ls180.v:1504$3383
+ attribute \src "ls180.v:1520.5-1520.41"
+ process $proc$ls180.v:1520$3395
assign { } { }
assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0
sync always
update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0]
sync init
end
- attribute \src "ls180.v:1505.11-1505.47"
- process $proc$ls180.v:1505$3384
+ attribute \src "ls180.v:1521.11-1521.47"
+ process $proc$ls180.v:1521$3396
assign { } { }
assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000
sync always
sync init
update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0]
end
- attribute \src "ls180.v:1506.11-1506.47"
- process $proc$ls180.v:1506$3385
+ attribute \src "ls180.v:1522.11-1522.47"
+ process $proc$ls180.v:1522$3397
assign { } { }
assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000
sync always
sync init
update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0]
end
- attribute \src "ls180.v:1507.11-1507.50"
- process $proc$ls180.v:1507$3386
+ attribute \src "ls180.v:1523.11-1523.50"
+ process $proc$ls180.v:1523$3398
assign { } { }
assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000
sync always
sync init
update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0]
end
- attribute \src "ls180.v:152.5-152.62"
- process $proc$ls180.v:152$2794
+ attribute \src "ls180.v:153.12-153.71"
+ process $proc$ls180.v:153$2799
assign { } { }
- assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
+ assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
sync always
sync init
- update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0]
+ update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0]
+ end
+ attribute \src "ls180.v:154.12-154.73"
+ process $proc$ls180.v:154$2800
+ assign { } { }
+ assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0
+ sync always
+ sync init
+ update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0]
end
- attribute \src "ls180.v:1527.5-1527.51"
- process $proc$ls180.v:1527$3387
+ attribute \src "ls180.v:1543.5-1543.51"
+ process $proc$ls180.v:1543$3399
assign { } { }
assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0]
end
- attribute \src "ls180.v:1528.5-1528.50"
- process $proc$ls180.v:1528$3388
+ attribute \src "ls180.v:1544.5-1544.50"
+ process $proc$ls180.v:1544$3400
assign { } { }
assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0]
end
- attribute \src "ls180.v:1529.12-1529.66"
- process $proc$ls180.v:1529$3389
+ attribute \src "ls180.v:1545.12-1545.66"
+ process $proc$ls180.v:1545$3401
assign { } { }
assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0
sync always
sync init
update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0]
end
- attribute \src "ls180.v:153.11-153.69"
- process $proc$ls180.v:153$2795
- assign { } { }
- assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000
- sync always
- update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0]
- sync init
- end
- attribute \src "ls180.v:1530.11-1530.77"
- process $proc$ls180.v:1530$3390
+ attribute \src "ls180.v:1546.11-1546.77"
+ process $proc$ls180.v:1546$3402
assign { } { }
assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000
sync always
sync init
update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
end
- attribute \src "ls180.v:1531.11-1531.50"
- process $proc$ls180.v:1531$3391
+ attribute \src "ls180.v:1547.11-1547.50"
+ process $proc$ls180.v:1547$3403
assign { } { }
assign $1\main_sdblock2mem_converter_demux[1:0] 2'00
sync always
sync init
update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0]
end
- attribute \src "ls180.v:1533.5-1533.49"
- process $proc$ls180.v:1533$3392
+ attribute \src "ls180.v:1549.5-1549.49"
+ process $proc$ls180.v:1549$3404
assign { } { }
assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0]
end
- attribute \src "ls180.v:1539.5-1539.45"
- process $proc$ls180.v:1539$3393
+ attribute \src "ls180.v:1555.5-1555.45"
+ process $proc$ls180.v:1555$3405
assign { } { }
assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0]
end
- attribute \src "ls180.v:154.11-154.69"
- process $proc$ls180.v:154$2796
- assign { } { }
- assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00
- sync always
- update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0]
- sync init
- end
- attribute \src "ls180.v:1541.12-1541.62"
- process $proc$ls180.v:1541$3394
+ attribute \src "ls180.v:1557.12-1557.62"
+ process $proc$ls180.v:1557$3406
assign { } { }
assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0
sync always
sync init
update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0]
end
- attribute \src "ls180.v:1542.12-1542.60"
- process $proc$ls180.v:1542$3395
+ attribute \src "ls180.v:1558.12-1558.60"
+ process $proc$ls180.v:1558$3407
assign { } { }
assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0
sync always
sync init
update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0]
end
- attribute \src "ls180.v:1544.5-1544.57"
- process $proc$ls180.v:1544$3396
+ attribute \src "ls180.v:156.11-156.69"
+ process $proc$ls180.v:156$2801
+ assign { } { }
+ assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000
+ sync always
+ sync init
+ update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0]
+ end
+ attribute \src "ls180.v:1560.5-1560.57"
+ process $proc$ls180.v:1560$3408
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
end
- attribute \src "ls180.v:1548.12-1548.67"
- process $proc$ls180.v:1548$3397
+ attribute \src "ls180.v:1564.12-1564.67"
+ process $proc$ls180.v:1564$3409
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
end
- attribute \src "ls180.v:1549.5-1549.54"
- process $proc$ls180.v:1549$3398
+ attribute \src "ls180.v:1565.5-1565.54"
+ process $proc$ls180.v:1565$3410
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
end
- attribute \src "ls180.v:1550.12-1550.69"
- process $proc$ls180.v:1550$3399
+ attribute \src "ls180.v:1566.12-1566.69"
+ process $proc$ls180.v:1566$3411
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
end
- attribute \src "ls180.v:1551.5-1551.56"
- process $proc$ls180.v:1551$3400
+ attribute \src "ls180.v:1567.5-1567.56"
+ process $proc$ls180.v:1567$3412
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
end
- attribute \src "ls180.v:1552.5-1552.61"
- process $proc$ls180.v:1552$3401
+ attribute \src "ls180.v:1568.5-1568.61"
+ process $proc$ls180.v:1568$3413
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
end
- attribute \src "ls180.v:1553.5-1553.56"
- process $proc$ls180.v:1553$3402
+ attribute \src "ls180.v:1569.5-1569.56"
+ process $proc$ls180.v:1569$3414
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
end
- attribute \src "ls180.v:1554.5-1554.53"
- process $proc$ls180.v:1554$3403
+ attribute \src "ls180.v:157.5-157.63"
+ process $proc$ls180.v:157$2802
+ assign { } { }
+ assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0]
+ end
+ attribute \src "ls180.v:1570.5-1570.53"
+ process $proc$ls180.v:1570$3415
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0]
end
- attribute \src "ls180.v:1556.5-1556.59"
- process $proc$ls180.v:1556$3404
+ attribute \src "ls180.v:1572.5-1572.59"
+ process $proc$ls180.v:1572$3416
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
end
- attribute \src "ls180.v:1557.5-1557.54"
- process $proc$ls180.v:1557$3405
+ attribute \src "ls180.v:1573.5-1573.54"
+ process $proc$ls180.v:1573$3417
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
end
- attribute \src "ls180.v:1559.12-1559.61"
- process $proc$ls180.v:1559$3406
+ attribute \src "ls180.v:1575.12-1575.61"
+ process $proc$ls180.v:1575$3418
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0]
end
- attribute \src "ls180.v:156.5-156.44"
- process $proc$ls180.v:156$2797
- assign { } { }
- assign $1\main_libresocsim_converter1_skip[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0]
- end
- attribute \src "ls180.v:1562.12-1562.43"
- process $proc$ls180.v:1562$3407
+ attribute \src "ls180.v:1578.12-1578.43"
+ process $proc$ls180.v:1578$3419
assign { } { }
assign $1\main_interface1_bus_adr[31:0] 0
sync always
sync init
update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0]
end
- attribute \src "ls180.v:1563.12-1563.45"
- process $proc$ls180.v:1563$3408
+ attribute \src "ls180.v:1579.12-1579.45"
+ process $proc$ls180.v:1579$3420
assign { } { }
assign $0\main_interface1_bus_dat_w[31:0] 0
sync always
update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0]
sync init
end
- attribute \src "ls180.v:1565.11-1565.41"
- process $proc$ls180.v:1565$3409
+ attribute \src "ls180.v:158.5-158.63"
+ process $proc$ls180.v:158$2803
+ assign { } { }
+ assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0]
+ end
+ attribute \src "ls180.v:1581.11-1581.41"
+ process $proc$ls180.v:1581$3421
assign { } { }
assign $1\main_interface1_bus_sel[3:0] 4'0000
sync always
sync init
update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0]
end
- attribute \src "ls180.v:1566.5-1566.35"
- process $proc$ls180.v:1566$3410
+ attribute \src "ls180.v:1582.5-1582.35"
+ process $proc$ls180.v:1582$3422
assign { } { }
assign $1\main_interface1_bus_cyc[0:0] 1'0
sync always
sync init
update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0]
end
- attribute \src "ls180.v:1567.5-1567.35"
- process $proc$ls180.v:1567$3411
+ attribute \src "ls180.v:1583.5-1583.35"
+ process $proc$ls180.v:1583$3423
assign { } { }
assign $1\main_interface1_bus_stb[0:0] 1'0
sync always
sync init
update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0]
end
- attribute \src "ls180.v:1569.5-1569.34"
- process $proc$ls180.v:1569$3412
+ attribute \src "ls180.v:1585.5-1585.34"
+ process $proc$ls180.v:1585$3424
assign { } { }
assign $1\main_interface1_bus_we[0:0] 1'0
sync always
sync init
update \main_interface1_bus_we $1\main_interface1_bus_we[0:0]
end
- attribute \src "ls180.v:157.5-157.47"
- process $proc$ls180.v:157$2798
- assign { } { }
- assign $1\main_libresocsim_converter1_counter[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0]
- end
- attribute \src "ls180.v:1570.11-1570.41"
- process $proc$ls180.v:1570$3413
+ attribute \src "ls180.v:1586.11-1586.41"
+ process $proc$ls180.v:1586$3425
assign { } { }
assign $0\main_interface1_bus_cti[2:0] 3'000
sync always
update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0]
sync init
end
- attribute \src "ls180.v:1571.11-1571.41"
- process $proc$ls180.v:1571$3414
+ attribute \src "ls180.v:1587.11-1587.41"
+ process $proc$ls180.v:1587$3426
assign { } { }
assign $0\main_interface1_bus_bte[1:0] 2'00
sync always
update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0]
sync init
end
- attribute \src "ls180.v:1578.5-1578.43"
- process $proc$ls180.v:1578$3415
+ attribute \src "ls180.v:1594.5-1594.43"
+ process $proc$ls180.v:1594$3427
assign { } { }
assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0]
end
- attribute \src "ls180.v:1579.5-1579.43"
- process $proc$ls180.v:1579$3416
+ attribute \src "ls180.v:1595.5-1595.43"
+ process $proc$ls180.v:1595$3428
assign { } { }
assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0]
end
- attribute \src "ls180.v:1580.5-1580.42"
- process $proc$ls180.v:1580$3417
+ attribute \src "ls180.v:1596.5-1596.42"
+ process $proc$ls180.v:1596$3429
assign { } { }
assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0]
end
- attribute \src "ls180.v:1581.12-1581.61"
- process $proc$ls180.v:1581$3418
+ attribute \src "ls180.v:1597.12-1597.61"
+ process $proc$ls180.v:1597$3430
assign { } { }
assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0]
end
- attribute \src "ls180.v:1582.5-1582.45"
- process $proc$ls180.v:1582$3419
+ attribute \src "ls180.v:1598.5-1598.45"
+ process $proc$ls180.v:1598$3431
assign { } { }
assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0]
end
- attribute \src "ls180.v:1584.5-1584.45"
- process $proc$ls180.v:1584$3420
+ attribute \src "ls180.v:160.5-160.62"
+ process $proc$ls180.v:160$2804
+ assign { } { }
+ assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0]
+ end
+ attribute \src "ls180.v:1600.5-1600.45"
+ process $proc$ls180.v:1600$3432
assign { } { }
assign $0\main_sdmem2block_dma_source_first[0:0] 1'0
sync always
update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0]
sync init
end
- attribute \src "ls180.v:1585.5-1585.44"
- process $proc$ls180.v:1585$3421
+ attribute \src "ls180.v:1601.5-1601.44"
+ process $proc$ls180.v:1601$3433
assign { } { }
assign $1\main_sdmem2block_dma_source_last[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0]
end
- attribute \src "ls180.v:1586.12-1586.60"
- process $proc$ls180.v:1586$3422
+ attribute \src "ls180.v:1602.12-1602.60"
+ process $proc$ls180.v:1602$3434
assign { } { }
assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0]
end
- attribute \src "ls180.v:1587.12-1587.45"
- process $proc$ls180.v:1587$3423
+ attribute \src "ls180.v:1603.12-1603.45"
+ process $proc$ls180.v:1603$3435
assign { } { }
assign $1\main_sdmem2block_dma_data[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0]
end
- attribute \src "ls180.v:1588.12-1588.53"
- process $proc$ls180.v:1588$3424
+ attribute \src "ls180.v:1604.12-1604.53"
+ process $proc$ls180.v:1604$3436
assign { } { }
assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0]
end
- attribute \src "ls180.v:1589.5-1589.40"
- process $proc$ls180.v:1589$3425
+ attribute \src "ls180.v:1605.5-1605.40"
+ process $proc$ls180.v:1605$3437
assign { } { }
assign $1\main_sdmem2block_dma_base_re[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0]
end
- attribute \src "ls180.v:159.12-159.53"
- process $proc$ls180.v:159$2799
- assign { } { }
- assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- sync always
- sync init
- update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0]
- end
- attribute \src "ls180.v:1590.12-1590.55"
- process $proc$ls180.v:1590$3426
+ attribute \src "ls180.v:1606.12-1606.55"
+ process $proc$ls180.v:1606$3438
assign { } { }
assign $1\main_sdmem2block_dma_length_storage[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0]
end
- attribute \src "ls180.v:1591.5-1591.42"
- process $proc$ls180.v:1591$3427
+ attribute \src "ls180.v:1607.5-1607.42"
+ process $proc$ls180.v:1607$3439
assign { } { }
assign $1\main_sdmem2block_dma_length_re[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0]
end
- attribute \src "ls180.v:1592.5-1592.47"
- process $proc$ls180.v:1592$3428
+ attribute \src "ls180.v:1608.5-1608.47"
+ process $proc$ls180.v:1608$3440
assign { } { }
assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0]
end
- attribute \src "ls180.v:1593.5-1593.42"
- process $proc$ls180.v:1593$3429
+ attribute \src "ls180.v:1609.5-1609.42"
+ process $proc$ls180.v:1609$3441
assign { } { }
assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0]
end
- attribute \src "ls180.v:1594.5-1594.44"
- process $proc$ls180.v:1594$3430
+ attribute \src "ls180.v:161.11-161.69"
+ process $proc$ls180.v:161$2805
+ assign { } { }
+ assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000
+ sync always
+ update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0]
+ sync init
+ end
+ attribute \src "ls180.v:1610.5-1610.44"
+ process $proc$ls180.v:1610$3442
assign { } { }
assign $1\main_sdmem2block_dma_done_status[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0]
end
- attribute \src "ls180.v:1596.5-1596.45"
- process $proc$ls180.v:1596$3431
+ attribute \src "ls180.v:1612.5-1612.45"
+ process $proc$ls180.v:1612$3443
assign { } { }
assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0]
end
- attribute \src "ls180.v:1597.5-1597.40"
- process $proc$ls180.v:1597$3432
+ attribute \src "ls180.v:1613.5-1613.40"
+ process $proc$ls180.v:1613$3444
assign { } { }
assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0]
end
- attribute \src "ls180.v:160.12-160.71"
- process $proc$ls180.v:160$2800
- assign { } { }
- assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
- sync always
- sync init
- update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0]
- end
- attribute \src "ls180.v:1601.12-1601.47"
- process $proc$ls180.v:1601$3433
+ attribute \src "ls180.v:1617.12-1617.47"
+ process $proc$ls180.v:1617$3445
assign { } { }
assign $1\main_sdmem2block_dma_offset[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0]
end
- attribute \src "ls180.v:161.12-161.73"
- process $proc$ls180.v:161$2801
+ attribute \src "ls180.v:162.11-162.69"
+ process $proc$ls180.v:162$2806
assign { } { }
- assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0
+ assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00
sync always
+ update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0]
sync init
- update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0]
end
- attribute \src "ls180.v:1613.11-1613.64"
- process $proc$ls180.v:1613$3434
+ attribute \src "ls180.v:1629.11-1629.64"
+ process $proc$ls180.v:1629$3446
assign { } { }
assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000
sync always
sync init
update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0]
end
- attribute \src "ls180.v:1615.11-1615.48"
- process $proc$ls180.v:1615$3435
+ attribute \src "ls180.v:1631.11-1631.48"
+ process $proc$ls180.v:1631$3447
assign { } { }
assign $1\main_sdmem2block_converter_mux[1:0] 2'00
sync always
sync init
update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0]
end
- attribute \src "ls180.v:163.11-163.69"
- process $proc$ls180.v:163$2802
+ attribute \src "ls180.v:164.5-164.44"
+ process $proc$ls180.v:164$2807
assign { } { }
- assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000
+ assign $1\main_libresocsim_converter1_skip[0:0] 1'0
sync always
sync init
- update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0]
+ update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0]
end
- attribute \src "ls180.v:1639.11-1639.45"
- process $proc$ls180.v:1639$3436
+ attribute \src "ls180.v:165.5-165.47"
+ process $proc$ls180.v:165$2808
assign { } { }
- assign $1\main_sdmem2block_fifo_level[5:0] 6'000000
+ assign $1\main_libresocsim_converter1_counter[0:0] 1'0
sync always
sync init
- update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0]
+ update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0]
end
- attribute \src "ls180.v:164.5-164.63"
- process $proc$ls180.v:164$2803
+ attribute \src "ls180.v:1655.11-1655.45"
+ process $proc$ls180.v:1655$3448
assign { } { }
- assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0
+ assign $1\main_sdmem2block_fifo_level[5:0] 6'000000
sync always
sync init
- update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0]
+ update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0]
end
- attribute \src "ls180.v:1640.5-1640.41"
- process $proc$ls180.v:1640$3437
+ attribute \src "ls180.v:1656.5-1656.41"
+ process $proc$ls180.v:1656$3449
assign { } { }
assign $0\main_sdmem2block_fifo_replace[0:0] 1'0
sync always
update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0]
sync init
end
- attribute \src "ls180.v:1641.11-1641.47"
- process $proc$ls180.v:1641$3438
+ attribute \src "ls180.v:1657.11-1657.47"
+ process $proc$ls180.v:1657$3450
assign { } { }
assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000
sync always
sync init
update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0]
end
- attribute \src "ls180.v:1642.11-1642.47"
- process $proc$ls180.v:1642$3439
+ attribute \src "ls180.v:1658.11-1658.47"
+ process $proc$ls180.v:1658$3451
assign { } { }
assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000
sync always
sync init
update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0]
end
- attribute \src "ls180.v:1643.11-1643.50"
- process $proc$ls180.v:1643$3440
+ attribute \src "ls180.v:1659.11-1659.50"
+ process $proc$ls180.v:1659$3452
assign { } { }
assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000
sync always
sync init
update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0]
end
- attribute \src "ls180.v:165.5-165.63"
- process $proc$ls180.v:165$2804
+ attribute \src "ls180.v:167.12-167.53"
+ process $proc$ls180.v:167$2809
assign { } { }
- assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0
+ assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0]
+ update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0]
end
- attribute \src "ls180.v:1658.5-1658.29"
- process $proc$ls180.v:1658$3441
+ attribute \src "ls180.v:1674.5-1674.29"
+ process $proc$ls180.v:1674$3453
assign { } { }
assign $1\libresocsim_done0[0:0] 1'0
sync always
sync init
update \libresocsim_done0 $1\libresocsim_done0[0:0]
end
- attribute \src "ls180.v:1659.5-1659.27"
- process $proc$ls180.v:1659$3442
+ attribute \src "ls180.v:1675.5-1675.27"
+ process $proc$ls180.v:1675$3454
assign { } { }
assign $1\libresocsim_irq[0:0] 1'0
sync always
sync init
update \libresocsim_irq $1\libresocsim_irq[0:0]
end
- attribute \src "ls180.v:1661.11-1661.34"
- process $proc$ls180.v:1661$3443
+ attribute \src "ls180.v:1677.11-1677.34"
+ process $proc$ls180.v:1677$3455
assign { } { }
assign $1\libresocsim_miso[7:0] 8'00000000
sync always
sync init
update \libresocsim_miso $1\libresocsim_miso[7:0]
end
- attribute \src "ls180.v:1665.5-1665.30"
- process $proc$ls180.v:1665$3444
+ attribute \src "ls180.v:168.12-168.71"
+ process $proc$ls180.v:168$2810
+ assign { } { }
+ assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
+ sync always
+ sync init
+ update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0]
+ end
+ attribute \src "ls180.v:1681.5-1681.30"
+ process $proc$ls180.v:1681$3456
assign { } { }
assign $1\libresocsim_start1[0:0] 1'0
sync always
sync init
update \libresocsim_start1 $1\libresocsim_start1[0:0]
end
- attribute \src "ls180.v:1667.12-1667.47"
- process $proc$ls180.v:1667$3445
+ attribute \src "ls180.v:1683.12-1683.47"
+ process $proc$ls180.v:1683$3457
assign { } { }
assign $1\libresocsim_control_storage[15:0] 16'0000000000000000
sync always
sync init
update \libresocsim_control_storage $1\libresocsim_control_storage[15:0]
end
- attribute \src "ls180.v:1668.5-1668.34"
- process $proc$ls180.v:1668$3446
+ attribute \src "ls180.v:1684.5-1684.34"
+ process $proc$ls180.v:1684$3458
assign { } { }
assign $1\libresocsim_control_re[0:0] 1'0
sync always
sync init
update \libresocsim_control_re $1\libresocsim_control_re[0:0]
end
- attribute \src "ls180.v:167.5-167.62"
- process $proc$ls180.v:167$2805
- assign { } { }
- assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0]
- end
- attribute \src "ls180.v:1672.11-1672.42"
- process $proc$ls180.v:1672$3447
+ attribute \src "ls180.v:1688.11-1688.42"
+ process $proc$ls180.v:1688$3459
assign { } { }
assign $1\libresocsim_mosi_storage[7:0] 8'00000000
sync always
sync init
update \libresocsim_mosi_storage $1\libresocsim_mosi_storage[7:0]
end
- attribute \src "ls180.v:1673.5-1673.31"
- process $proc$ls180.v:1673$3448
+ attribute \src "ls180.v:1689.5-1689.31"
+ process $proc$ls180.v:1689$3460
assign { } { }
assign $1\libresocsim_mosi_re[0:0] 1'0
sync always
sync init
update \libresocsim_mosi_re $1\libresocsim_mosi_re[0:0]
end
- attribute \src "ls180.v:1677.5-1677.34"
- process $proc$ls180.v:1677$3449
+ attribute \src "ls180.v:169.12-169.73"
+ process $proc$ls180.v:169$2811
+ assign { } { }
+ assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0
+ sync always
+ sync init
+ update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0]
+ end
+ attribute \src "ls180.v:1693.5-1693.34"
+ process $proc$ls180.v:1693$3461
assign { } { }
assign $1\libresocsim_cs_storage[0:0] 1'1
sync always
sync init
update \libresocsim_cs_storage $1\libresocsim_cs_storage[0:0]
end
- attribute \src "ls180.v:1678.5-1678.29"
- process $proc$ls180.v:1678$3450
+ attribute \src "ls180.v:1694.5-1694.29"
+ process $proc$ls180.v:1694$3462
assign { } { }
assign $1\libresocsim_cs_re[0:0] 1'0
sync always
sync init
update \libresocsim_cs_re $1\libresocsim_cs_re[0:0]
end
- attribute \src "ls180.v:1679.5-1679.40"
- process $proc$ls180.v:1679$3451
+ attribute \src "ls180.v:1695.5-1695.40"
+ process $proc$ls180.v:1695$3463
assign { } { }
assign $1\libresocsim_loopback_storage[0:0] 1'0
sync always
sync init
update \libresocsim_loopback_storage $1\libresocsim_loopback_storage[0:0]
end
- attribute \src "ls180.v:168.11-168.69"
- process $proc$ls180.v:168$2806
- assign { } { }
- assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000
- sync always
- update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0]
- sync init
- end
- attribute \src "ls180.v:1680.5-1680.35"
- process $proc$ls180.v:1680$3452
+ attribute \src "ls180.v:1696.5-1696.35"
+ process $proc$ls180.v:1696$3464
assign { } { }
assign $1\libresocsim_loopback_re[0:0] 1'0
sync always
sync init
update \libresocsim_loopback_re $1\libresocsim_loopback_re[0:0]
end
- attribute \src "ls180.v:1681.5-1681.34"
- process $proc$ls180.v:1681$3453
+ attribute \src "ls180.v:1697.5-1697.34"
+ process $proc$ls180.v:1697$3465
assign { } { }
assign $1\libresocsim_clk_enable[0:0] 1'0
sync always
sync init
update \libresocsim_clk_enable $1\libresocsim_clk_enable[0:0]
end
- attribute \src "ls180.v:1682.5-1682.33"
- process $proc$ls180.v:1682$3454
+ attribute \src "ls180.v:1698.5-1698.33"
+ process $proc$ls180.v:1698$3466
assign { } { }
assign $1\libresocsim_cs_enable[0:0] 1'0
sync always
sync init
update \libresocsim_cs_enable $1\libresocsim_cs_enable[0:0]
end
- attribute \src "ls180.v:1683.11-1683.35"
- process $proc$ls180.v:1683$3455
+ attribute \src "ls180.v:1699.11-1699.35"
+ process $proc$ls180.v:1699$3467
assign { } { }
assign $1\libresocsim_count[2:0] 3'000
sync always
sync init
update \libresocsim_count $1\libresocsim_count[2:0]
end
- attribute \src "ls180.v:1684.5-1684.34"
- process $proc$ls180.v:1684$3456
+ attribute \src "ls180.v:1700.5-1700.34"
+ process $proc$ls180.v:1700$3468
assign { } { }
assign $1\libresocsim_mosi_latch[0:0] 1'0
sync always
sync init
update \libresocsim_mosi_latch $1\libresocsim_mosi_latch[0:0]
end
- attribute \src "ls180.v:1685.5-1685.34"
- process $proc$ls180.v:1685$3457
+ attribute \src "ls180.v:1701.5-1701.34"
+ process $proc$ls180.v:1701$3469
assign { } { }
assign $1\libresocsim_miso_latch[0:0] 1'0
sync always
sync init
update \libresocsim_miso_latch $1\libresocsim_miso_latch[0:0]
end
- attribute \src "ls180.v:1686.12-1686.44"
- process $proc$ls180.v:1686$3458
+ attribute \src "ls180.v:1702.12-1702.44"
+ process $proc$ls180.v:1702$3470
assign { } { }
assign $1\libresocsim_clk_divider1[15:0] 16'0000000000000000
sync always
sync init
update \libresocsim_clk_divider1 $1\libresocsim_clk_divider1[15:0]
end
- attribute \src "ls180.v:1689.11-1689.39"
- process $proc$ls180.v:1689$3459
+ attribute \src "ls180.v:1705.11-1705.39"
+ process $proc$ls180.v:1705$3471
assign { } { }
assign $1\libresocsim_mosi_data[7:0] 8'00000000
sync always
sync init
update \libresocsim_mosi_data $1\libresocsim_mosi_data[7:0]
end
- attribute \src "ls180.v:169.11-169.69"
- process $proc$ls180.v:169$2807
- assign { } { }
- assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00
- sync always
- update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0]
- sync init
- end
- attribute \src "ls180.v:1690.11-1690.38"
- process $proc$ls180.v:1690$3460
+ attribute \src "ls180.v:1706.11-1706.38"
+ process $proc$ls180.v:1706$3472
assign { } { }
assign $1\libresocsim_mosi_sel[2:0] 3'000
sync always
sync init
update \libresocsim_mosi_sel $1\libresocsim_mosi_sel[2:0]
end
- attribute \src "ls180.v:1691.11-1691.39"
- process $proc$ls180.v:1691$3461
+ attribute \src "ls180.v:1707.11-1707.39"
+ process $proc$ls180.v:1707$3473
assign { } { }
assign $1\libresocsim_miso_data[7:0] 8'00000000
sync always
sync init
update \libresocsim_miso_data $1\libresocsim_miso_data[7:0]
end
- attribute \src "ls180.v:1692.12-1692.41"
- process $proc$ls180.v:1692$3462
+ attribute \src "ls180.v:1708.12-1708.41"
+ process $proc$ls180.v:1708$3474
assign { } { }
assign $1\libresocsim_storage[15:0] 16'0000000001111101
sync always
sync init
update \libresocsim_storage $1\libresocsim_storage[15:0]
end
- attribute \src "ls180.v:1693.5-1693.26"
- process $proc$ls180.v:1693$3463
+ attribute \src "ls180.v:1709.5-1709.26"
+ process $proc$ls180.v:1709$3475
assign { } { }
assign $1\libresocsim_re[0:0] 1'0
sync always
sync init
update \libresocsim_re $1\libresocsim_re[0:0]
end
- attribute \src "ls180.v:1694.5-1694.36"
- process $proc$ls180.v:1694$3464
+ attribute \src "ls180.v:171.11-171.69"
+ process $proc$ls180.v:171$2812
+ assign { } { }
+ assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000
+ sync always
+ sync init
+ update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0]
+ end
+ attribute \src "ls180.v:1710.5-1710.36"
+ process $proc$ls180.v:1710$3476
assign { } { }
assign $1\builder_converter0_state[0:0] 1'0
sync always
sync init
update \builder_converter0_state $1\builder_converter0_state[0:0]
end
- attribute \src "ls180.v:1695.5-1695.41"
- process $proc$ls180.v:1695$3465
+ attribute \src "ls180.v:1711.5-1711.41"
+ process $proc$ls180.v:1711$3477
assign { } { }
assign $1\builder_converter0_next_state[0:0] 1'0
sync always
sync init
update \builder_converter0_next_state $1\builder_converter0_next_state[0:0]
end
- attribute \src "ls180.v:1696.5-1696.69"
- process $proc$ls180.v:1696$3466
+ attribute \src "ls180.v:1712.5-1712.69"
+ process $proc$ls180.v:1712$3478
assign { } { }
assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0]
end
- attribute \src "ls180.v:1697.5-1697.72"
- process $proc$ls180.v:1697$3467
+ attribute \src "ls180.v:1713.5-1713.72"
+ process $proc$ls180.v:1713$3479
assign { } { }
assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
end
- attribute \src "ls180.v:1698.5-1698.36"
- process $proc$ls180.v:1698$3468
+ attribute \src "ls180.v:1714.5-1714.36"
+ process $proc$ls180.v:1714$3480
assign { } { }
assign $1\builder_converter1_state[0:0] 1'0
sync always
sync init
update \builder_converter1_state $1\builder_converter1_state[0:0]
end
- attribute \src "ls180.v:1699.5-1699.41"
- process $proc$ls180.v:1699$3469
+ attribute \src "ls180.v:1715.5-1715.41"
+ process $proc$ls180.v:1715$3481
assign { } { }
assign $1\builder_converter1_next_state[0:0] 1'0
sync always
sync init
update \builder_converter1_next_state $1\builder_converter1_next_state[0:0]
end
- attribute \src "ls180.v:1700.5-1700.69"
- process $proc$ls180.v:1700$3470
+ attribute \src "ls180.v:1716.5-1716.69"
+ process $proc$ls180.v:1716$3482
assign { } { }
assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0]
end
- attribute \src "ls180.v:1701.5-1701.72"
- process $proc$ls180.v:1701$3471
+ attribute \src "ls180.v:1717.5-1717.72"
+ process $proc$ls180.v:1717$3483
assign { } { }
assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
end
- attribute \src "ls180.v:1702.5-1702.36"
- process $proc$ls180.v:1702$3472
+ attribute \src "ls180.v:1718.5-1718.36"
+ process $proc$ls180.v:1718$3484
assign { } { }
assign $1\builder_converter2_state[0:0] 1'0
sync always
sync init
update \builder_converter2_state $1\builder_converter2_state[0:0]
end
- attribute \src "ls180.v:1703.5-1703.41"
- process $proc$ls180.v:1703$3473
+ attribute \src "ls180.v:1719.5-1719.41"
+ process $proc$ls180.v:1719$3485
assign { } { }
assign $1\builder_converter2_next_state[0:0] 1'0
sync always
sync init
update \builder_converter2_next_state $1\builder_converter2_next_state[0:0]
end
- attribute \src "ls180.v:1704.5-1704.69"
- process $proc$ls180.v:1704$3474
+ attribute \src "ls180.v:172.5-172.63"
+ process $proc$ls180.v:172$2813
+ assign { } { }
+ assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0]
+ end
+ attribute \src "ls180.v:1720.5-1720.69"
+ process $proc$ls180.v:1720$3486
assign { } { }
assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0]
end
- attribute \src "ls180.v:1705.5-1705.72"
- process $proc$ls180.v:1705$3475
+ attribute \src "ls180.v:1721.5-1721.72"
+ process $proc$ls180.v:1721$3487
assign { } { }
assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0
sync always
sync init
update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
end
- attribute \src "ls180.v:1706.11-1706.41"
- process $proc$ls180.v:1706$3476
+ attribute \src "ls180.v:1722.11-1722.41"
+ process $proc$ls180.v:1722$3488
assign { } { }
assign $1\builder_refresher_state[1:0] 2'00
sync always
sync init
update \builder_refresher_state $1\builder_refresher_state[1:0]
end
- attribute \src "ls180.v:1707.11-1707.46"
- process $proc$ls180.v:1707$3477
+ attribute \src "ls180.v:1723.11-1723.46"
+ process $proc$ls180.v:1723$3489
assign { } { }
assign $1\builder_refresher_next_state[1:0] 2'00
sync always
sync init
update \builder_refresher_next_state $1\builder_refresher_next_state[1:0]
end
- attribute \src "ls180.v:1708.11-1708.44"
- process $proc$ls180.v:1708$3478
+ attribute \src "ls180.v:1724.11-1724.44"
+ process $proc$ls180.v:1724$3490
assign { } { }
assign $1\builder_bankmachine0_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0]
end
- attribute \src "ls180.v:1709.11-1709.49"
- process $proc$ls180.v:1709$3479
+ attribute \src "ls180.v:1725.11-1725.49"
+ process $proc$ls180.v:1725$3491
assign { } { }
assign $1\builder_bankmachine0_next_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0]
end
- attribute \src "ls180.v:171.5-171.44"
- process $proc$ls180.v:171$2808
- assign { } { }
- assign $1\main_libresocsim_converter2_skip[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0]
- end
- attribute \src "ls180.v:1710.11-1710.44"
- process $proc$ls180.v:1710$3480
+ attribute \src "ls180.v:1726.11-1726.44"
+ process $proc$ls180.v:1726$3492
assign { } { }
assign $1\builder_bankmachine1_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0]
end
- attribute \src "ls180.v:1711.11-1711.49"
- process $proc$ls180.v:1711$3481
+ attribute \src "ls180.v:1727.11-1727.49"
+ process $proc$ls180.v:1727$3493
assign { } { }
assign $1\builder_bankmachine1_next_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0]
end
- attribute \src "ls180.v:1712.11-1712.44"
- process $proc$ls180.v:1712$3482
+ attribute \src "ls180.v:1728.11-1728.44"
+ process $proc$ls180.v:1728$3494
assign { } { }
assign $1\builder_bankmachine2_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0]
end
- attribute \src "ls180.v:1713.11-1713.49"
- process $proc$ls180.v:1713$3483
+ attribute \src "ls180.v:1729.11-1729.49"
+ process $proc$ls180.v:1729$3495
assign { } { }
assign $1\builder_bankmachine2_next_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0]
end
- attribute \src "ls180.v:1714.11-1714.44"
- process $proc$ls180.v:1714$3484
+ attribute \src "ls180.v:173.5-173.63"
+ process $proc$ls180.v:173$2814
+ assign { } { }
+ assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0]
+ end
+ attribute \src "ls180.v:1730.11-1730.44"
+ process $proc$ls180.v:1730$3496
assign { } { }
assign $1\builder_bankmachine3_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0]
end
- attribute \src "ls180.v:1715.11-1715.49"
- process $proc$ls180.v:1715$3485
+ attribute \src "ls180.v:1731.11-1731.49"
+ process $proc$ls180.v:1731$3497
assign { } { }
assign $1\builder_bankmachine3_next_state[2:0] 3'000
sync always
sync init
update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0]
end
- attribute \src "ls180.v:1716.11-1716.43"
- process $proc$ls180.v:1716$3486
+ attribute \src "ls180.v:1732.11-1732.43"
+ process $proc$ls180.v:1732$3498
assign { } { }
assign $1\builder_multiplexer_state[2:0] 3'000
sync always
sync init
update \builder_multiplexer_state $1\builder_multiplexer_state[2:0]
end
- attribute \src "ls180.v:1717.11-1717.48"
- process $proc$ls180.v:1717$3487
+ attribute \src "ls180.v:1733.11-1733.48"
+ process $proc$ls180.v:1733$3499
assign { } { }
assign $1\builder_multiplexer_next_state[2:0] 3'000
sync always
sync init
update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0]
end
- attribute \src "ls180.v:172.5-172.47"
- process $proc$ls180.v:172$2809
- assign { } { }
- assign $1\main_libresocsim_converter2_counter[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0]
- end
- attribute \src "ls180.v:1730.5-1730.27"
- process $proc$ls180.v:1730$3488
+ attribute \src "ls180.v:1746.5-1746.27"
+ process $proc$ls180.v:1746$3500
assign { } { }
assign $0\builder_locked0[0:0] 1'0
sync always
update \builder_locked0 $0\builder_locked0[0:0]
sync init
end
- attribute \src "ls180.v:1731.5-1731.27"
- process $proc$ls180.v:1731$3489
+ attribute \src "ls180.v:1747.5-1747.27"
+ process $proc$ls180.v:1747$3501
assign { } { }
assign $0\builder_locked1[0:0] 1'0
sync always
update \builder_locked1 $0\builder_locked1[0:0]
sync init
end
- attribute \src "ls180.v:1732.5-1732.27"
- process $proc$ls180.v:1732$3490
+ attribute \src "ls180.v:1748.5-1748.27"
+ process $proc$ls180.v:1748$3502
assign { } { }
assign $0\builder_locked2[0:0] 1'0
sync always
update \builder_locked2 $0\builder_locked2[0:0]
sync init
end
- attribute \src "ls180.v:1733.5-1733.27"
- process $proc$ls180.v:1733$3491
+ attribute \src "ls180.v:1749.5-1749.27"
+ process $proc$ls180.v:1749$3503
assign { } { }
assign $0\builder_locked3[0:0] 1'0
sync always
update \builder_locked3 $0\builder_locked3[0:0]
sync init
end
- attribute \src "ls180.v:1734.5-1734.42"
- process $proc$ls180.v:1734$3492
+ attribute \src "ls180.v:175.5-175.62"
+ process $proc$ls180.v:175$2815
+ assign { } { }
+ assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0]
+ end
+ attribute \src "ls180.v:1750.5-1750.42"
+ process $proc$ls180.v:1750$3504
assign { } { }
assign $1\builder_new_master_wdata_ready[0:0] 1'0
sync always
sync init
update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0]
end
- attribute \src "ls180.v:1735.5-1735.43"
- process $proc$ls180.v:1735$3493
+ attribute \src "ls180.v:1751.5-1751.43"
+ process $proc$ls180.v:1751$3505
assign { } { }
assign $1\builder_new_master_rdata_valid0[0:0] 1'0
sync always
sync init
update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0]
end
- attribute \src "ls180.v:1736.5-1736.43"
- process $proc$ls180.v:1736$3494
+ attribute \src "ls180.v:1752.5-1752.43"
+ process $proc$ls180.v:1752$3506
assign { } { }
assign $1\builder_new_master_rdata_valid1[0:0] 1'0
sync always
sync init
update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0]
end
- attribute \src "ls180.v:1737.5-1737.43"
- process $proc$ls180.v:1737$3495
+ attribute \src "ls180.v:1753.5-1753.43"
+ process $proc$ls180.v:1753$3507
assign { } { }
assign $1\builder_new_master_rdata_valid2[0:0] 1'0
sync always
sync init
update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0]
end
- attribute \src "ls180.v:1738.5-1738.43"
- process $proc$ls180.v:1738$3496
+ attribute \src "ls180.v:1754.5-1754.43"
+ process $proc$ls180.v:1754$3508
assign { } { }
assign $1\builder_new_master_rdata_valid3[0:0] 1'0
sync always
sync init
update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0]
end
- attribute \src "ls180.v:1739.5-1739.35"
- process $proc$ls180.v:1739$3497
+ attribute \src "ls180.v:1755.5-1755.35"
+ process $proc$ls180.v:1755$3509
assign { } { }
assign $1\builder_converter_state[0:0] 1'0
sync always
sync init
update \builder_converter_state $1\builder_converter_state[0:0]
end
- attribute \src "ls180.v:174.12-174.53"
- process $proc$ls180.v:174$2810
- assign { } { }
- assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- sync always
- sync init
- update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0]
- end
- attribute \src "ls180.v:1740.5-1740.40"
- process $proc$ls180.v:1740$3498
+ attribute \src "ls180.v:1756.5-1756.40"
+ process $proc$ls180.v:1756$3510
assign { } { }
assign $1\builder_converter_next_state[0:0] 1'0
sync always
sync init
update \builder_converter_next_state $1\builder_converter_next_state[0:0]
end
- attribute \src "ls180.v:1741.5-1741.55"
- process $proc$ls180.v:1741$3499
+ attribute \src "ls180.v:1757.5-1757.55"
+ process $proc$ls180.v:1757$3511
assign { } { }
assign $1\main_converter_counter_converter_next_value[0:0] 1'0
sync always
sync init
update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0]
end
- attribute \src "ls180.v:1742.5-1742.58"
- process $proc$ls180.v:1742$3500
+ attribute \src "ls180.v:1758.5-1758.58"
+ process $proc$ls180.v:1758$3512
assign { } { }
assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0
sync always
sync init
update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0]
end
- attribute \src "ls180.v:1743.11-1743.42"
- process $proc$ls180.v:1743$3501
+ attribute \src "ls180.v:1759.11-1759.42"
+ process $proc$ls180.v:1759$3513
assign { } { }
assign $1\builder_spimaster0_state[1:0] 2'00
sync always
sync init
update \builder_spimaster0_state $1\builder_spimaster0_state[1:0]
end
- attribute \src "ls180.v:1744.11-1744.47"
- process $proc$ls180.v:1744$3502
+ attribute \src "ls180.v:176.11-176.69"
+ process $proc$ls180.v:176$2816
+ assign { } { }
+ assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000
+ sync always
+ update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0]
+ sync init
+ end
+ attribute \src "ls180.v:1760.11-1760.47"
+ process $proc$ls180.v:1760$3514
assign { } { }
assign $1\builder_spimaster0_next_state[1:0] 2'00
sync always
sync init
update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0]
end
- attribute \src "ls180.v:1745.11-1745.61"
- process $proc$ls180.v:1745$3503
+ attribute \src "ls180.v:1761.11-1761.61"
+ process $proc$ls180.v:1761$3515
assign { } { }
assign $1\main_spi_master_count_spimaster0_next_value[2:0] 3'000
sync always
sync init
update \main_spi_master_count_spimaster0_next_value $1\main_spi_master_count_spimaster0_next_value[2:0]
end
- attribute \src "ls180.v:1746.5-1746.58"
- process $proc$ls180.v:1746$3504
+ attribute \src "ls180.v:1762.5-1762.58"
+ process $proc$ls180.v:1762$3516
assign { } { }
assign $1\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0
sync always
sync init
update \main_spi_master_count_spimaster0_next_value_ce $1\main_spi_master_count_spimaster0_next_value_ce[0:0]
end
- attribute \src "ls180.v:1747.5-1747.41"
- process $proc$ls180.v:1747$3505
+ attribute \src "ls180.v:1763.5-1763.41"
+ process $proc$ls180.v:1763$3517
assign { } { }
assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0
sync always
sync init
update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0]
end
- attribute \src "ls180.v:1748.5-1748.46"
- process $proc$ls180.v:1748$3506
+ attribute \src "ls180.v:1764.5-1764.46"
+ process $proc$ls180.v:1764$3518
assign { } { }
assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0
sync always
sync init
update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0]
end
- attribute \src "ls180.v:1749.11-1749.66"
- process $proc$ls180.v:1749$3507
+ attribute \src "ls180.v:1765.11-1765.66"
+ process $proc$ls180.v:1765$3519
assign { } { }
assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
sync always
sync init
update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
end
- attribute \src "ls180.v:1750.5-1750.63"
- process $proc$ls180.v:1750$3508
+ attribute \src "ls180.v:1766.5-1766.63"
+ process $proc$ls180.v:1766$3520
assign { } { }
assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
end
- attribute \src "ls180.v:1751.11-1751.47"
- process $proc$ls180.v:1751$3509
+ attribute \src "ls180.v:1767.11-1767.47"
+ process $proc$ls180.v:1767$3521
assign { } { }
assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00
sync always
sync init
update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0]
end
- attribute \src "ls180.v:1752.11-1752.52"
- process $proc$ls180.v:1752$3510
+ attribute \src "ls180.v:1768.11-1768.52"
+ process $proc$ls180.v:1768$3522
assign { } { }
assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
sync always
sync init
update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0]
end
- attribute \src "ls180.v:1753.11-1753.66"
- process $proc$ls180.v:1753$3511
+ attribute \src "ls180.v:1769.11-1769.66"
+ process $proc$ls180.v:1769$3523
assign { } { }
assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
end
- attribute \src "ls180.v:1754.5-1754.63"
- process $proc$ls180.v:1754$3512
+ attribute \src "ls180.v:177.11-177.69"
+ process $proc$ls180.v:177$2817
+ assign { } { }
+ assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00
+ sync always
+ update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0]
+ sync init
+ end
+ attribute \src "ls180.v:1770.5-1770.63"
+ process $proc$ls180.v:1770$3524
assign { } { }
assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
end
- attribute \src "ls180.v:1755.11-1755.47"
- process $proc$ls180.v:1755$3513
+ attribute \src "ls180.v:1771.11-1771.47"
+ process $proc$ls180.v:1771$3525
assign { } { }
assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000
sync always
sync init
update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0]
end
- attribute \src "ls180.v:1756.11-1756.52"
- process $proc$ls180.v:1756$3514
+ attribute \src "ls180.v:1772.11-1772.52"
+ process $proc$ls180.v:1772$3526
assign { } { }
assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
sync always
sync init
update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0]
end
- attribute \src "ls180.v:1757.11-1757.67"
- process $proc$ls180.v:1757$3515
+ attribute \src "ls180.v:1773.11-1773.67"
+ process $proc$ls180.v:1773$3527
assign { } { }
assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
sync always
sync init
update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
end
- attribute \src "ls180.v:1758.5-1758.64"
- process $proc$ls180.v:1758$3516
+ attribute \src "ls180.v:1774.5-1774.64"
+ process $proc$ls180.v:1774$3528
assign { } { }
assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
end
- attribute \src "ls180.v:1759.12-1759.71"
- process $proc$ls180.v:1759$3517
+ attribute \src "ls180.v:1775.12-1775.71"
+ process $proc$ls180.v:1775$3529
assign { } { }
assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0
sync always
sync init
update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
end
- attribute \src "ls180.v:1760.5-1760.66"
- process $proc$ls180.v:1760$3518
+ attribute \src "ls180.v:1776.5-1776.66"
+ process $proc$ls180.v:1776$3530
assign { } { }
assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
end
- attribute \src "ls180.v:1761.5-1761.66"
- process $proc$ls180.v:1761$3519
+ attribute \src "ls180.v:1777.5-1777.66"
+ process $proc$ls180.v:1777$3531
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
end
- attribute \src "ls180.v:1762.5-1762.69"
- process $proc$ls180.v:1762$3520
+ attribute \src "ls180.v:1778.5-1778.69"
+ process $proc$ls180.v:1778$3532
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0
sync always
sync init
update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
end
- attribute \src "ls180.v:1763.5-1763.41"
- process $proc$ls180.v:1763$3521
+ attribute \src "ls180.v:1779.5-1779.41"
+ process $proc$ls180.v:1779$3533
assign { } { }
assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0
sync always
sync init
update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0]
end
- attribute \src "ls180.v:1764.5-1764.46"
- process $proc$ls180.v:1764$3522
+ attribute \src "ls180.v:1780.5-1780.46"
+ process $proc$ls180.v:1780$3534
assign { } { }
assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0
sync always
sync init
update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0]
end
- attribute \src "ls180.v:1765.5-1765.66"
- process $proc$ls180.v:1765$3523
+ attribute \src "ls180.v:1781.5-1781.66"
+ process $proc$ls180.v:1781$3535
assign { } { }
assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
end
- attribute \src "ls180.v:1766.5-1766.69"
- process $proc$ls180.v:1766$3524
+ attribute \src "ls180.v:1782.5-1782.69"
+ process $proc$ls180.v:1782$3536
assign { } { }
assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
end
- attribute \src "ls180.v:1767.11-1767.41"
- process $proc$ls180.v:1767$3525
+ attribute \src "ls180.v:1783.11-1783.41"
+ process $proc$ls180.v:1783$3537
assign { } { }
assign $1\builder_sdphy_fsm_state[2:0] 3'000
sync always
sync init
update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0]
end
- attribute \src "ls180.v:1768.11-1768.46"
- process $proc$ls180.v:1768$3526
+ attribute \src "ls180.v:1784.11-1784.46"
+ process $proc$ls180.v:1784$3538
assign { } { }
assign $1\builder_sdphy_fsm_next_state[2:0] 3'000
sync always
sync init
update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0]
end
- attribute \src "ls180.v:1769.11-1769.61"
- process $proc$ls180.v:1769$3527
+ attribute \src "ls180.v:1785.11-1785.61"
+ process $proc$ls180.v:1785$3539
assign { } { }
assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
sync always
sync init
update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
end
- attribute \src "ls180.v:1770.5-1770.58"
- process $proc$ls180.v:1770$3528
+ attribute \src "ls180.v:1786.5-1786.58"
+ process $proc$ls180.v:1786$3540
assign { } { }
assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
end
- attribute \src "ls180.v:1771.11-1771.48"
- process $proc$ls180.v:1771$3529
+ attribute \src "ls180.v:1787.11-1787.48"
+ process $proc$ls180.v:1787$3541
assign { } { }
assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000
sync always
sync init
update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0]
end
- attribute \src "ls180.v:1772.11-1772.53"
- process $proc$ls180.v:1772$3530
+ attribute \src "ls180.v:1788.11-1788.53"
+ process $proc$ls180.v:1788$3542
assign { } { }
assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000
sync always
sync init
update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0]
end
- attribute \src "ls180.v:1773.11-1773.70"
- process $proc$ls180.v:1773$3531
+ attribute \src "ls180.v:1789.11-1789.70"
+ process $proc$ls180.v:1789$3543
assign { } { }
assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
sync always
sync init
update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
end
- attribute \src "ls180.v:1774.5-1774.66"
- process $proc$ls180.v:1774$3532
+ attribute \src "ls180.v:179.5-179.44"
+ process $proc$ls180.v:179$2818
+ assign { } { }
+ assign $1\main_libresocsim_converter2_skip[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0]
+ end
+ attribute \src "ls180.v:1790.5-1790.66"
+ process $proc$ls180.v:1790$3544
assign { } { }
assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
end
- attribute \src "ls180.v:1775.12-1775.73"
- process $proc$ls180.v:1775$3533
+ attribute \src "ls180.v:1791.12-1791.73"
+ process $proc$ls180.v:1791$3545
assign { } { }
assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0
sync always
sync init
update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
end
- attribute \src "ls180.v:1776.5-1776.68"
- process $proc$ls180.v:1776$3534
+ attribute \src "ls180.v:1792.5-1792.68"
+ process $proc$ls180.v:1792$3546
assign { } { }
assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
end
- attribute \src "ls180.v:1777.5-1777.69"
- process $proc$ls180.v:1777$3535
+ attribute \src "ls180.v:1793.5-1793.69"
+ process $proc$ls180.v:1793$3547
assign { } { }
assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
end
- attribute \src "ls180.v:1778.5-1778.72"
- process $proc$ls180.v:1778$3536
+ attribute \src "ls180.v:1794.5-1794.72"
+ process $proc$ls180.v:1794$3548
assign { } { }
assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
end
- attribute \src "ls180.v:1779.5-1779.52"
- process $proc$ls180.v:1779$3537
+ attribute \src "ls180.v:1795.5-1795.52"
+ process $proc$ls180.v:1795$3549
assign { } { }
assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0
sync always
sync init
update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0]
end
- attribute \src "ls180.v:1780.5-1780.57"
- process $proc$ls180.v:1780$3538
+ attribute \src "ls180.v:1796.5-1796.57"
+ process $proc$ls180.v:1796$3550
assign { } { }
assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0
sync always
sync init
update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0]
end
- attribute \src "ls180.v:1781.12-1781.93"
- process $proc$ls180.v:1781$3539
+ attribute \src "ls180.v:1797.12-1797.93"
+ process $proc$ls180.v:1797$3551
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
end
- attribute \src "ls180.v:1782.5-1782.88"
- process $proc$ls180.v:1782$3540
+ attribute \src "ls180.v:1798.5-1798.88"
+ process $proc$ls180.v:1798$3552
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
end
- attribute \src "ls180.v:1783.12-1783.93"
- process $proc$ls180.v:1783$3541
+ attribute \src "ls180.v:1799.12-1799.93"
+ process $proc$ls180.v:1799$3553
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
end
- attribute \src "ls180.v:1784.5-1784.88"
- process $proc$ls180.v:1784$3542
+ attribute \src "ls180.v:180.5-180.47"
+ process $proc$ls180.v:180$2819
+ assign { } { }
+ assign $1\main_libresocsim_converter2_counter[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0]
+ end
+ attribute \src "ls180.v:1800.5-1800.88"
+ process $proc$ls180.v:1800$3554
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
end
- attribute \src "ls180.v:1785.12-1785.93"
- process $proc$ls180.v:1785$3543
+ attribute \src "ls180.v:1801.12-1801.93"
+ process $proc$ls180.v:1801$3555
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
end
- attribute \src "ls180.v:1786.5-1786.88"
- process $proc$ls180.v:1786$3544
+ attribute \src "ls180.v:1802.5-1802.88"
+ process $proc$ls180.v:1802$3556
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
end
- attribute \src "ls180.v:1787.12-1787.93"
- process $proc$ls180.v:1787$3545
+ attribute \src "ls180.v:1803.12-1803.93"
+ process $proc$ls180.v:1803$3557
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
end
- attribute \src "ls180.v:1788.5-1788.88"
- process $proc$ls180.v:1788$3546
+ attribute \src "ls180.v:1804.5-1804.88"
+ process $proc$ls180.v:1804$3558
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
end
- attribute \src "ls180.v:1789.11-1789.87"
- process $proc$ls180.v:1789$3547
+ attribute \src "ls180.v:1805.11-1805.87"
+ process $proc$ls180.v:1805$3559
assign { } { }
assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
sync always
sync init
update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
end
- attribute \src "ls180.v:1790.5-1790.84"
- process $proc$ls180.v:1790$3548
+ attribute \src "ls180.v:1806.5-1806.84"
+ process $proc$ls180.v:1806$3560
assign { } { }
assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
sync always
sync init
update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
end
- attribute \src "ls180.v:1791.11-1791.42"
- process $proc$ls180.v:1791$3549
+ attribute \src "ls180.v:1807.11-1807.42"
+ process $proc$ls180.v:1807$3561
assign { } { }
assign $1\builder_sdcore_fsm_state[2:0] 3'000
sync always
sync init
update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0]
end
- attribute \src "ls180.v:1792.11-1792.47"
- process $proc$ls180.v:1792$3550
+ attribute \src "ls180.v:1808.11-1808.47"
+ process $proc$ls180.v:1808$3562
assign { } { }
assign $1\builder_sdcore_fsm_next_state[2:0] 3'000
sync always
sync init
update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0]
end
- attribute \src "ls180.v:1793.5-1793.55"
- process $proc$ls180.v:1793$3551
+ attribute \src "ls180.v:1809.5-1809.55"
+ process $proc$ls180.v:1809$3563
assign { } { }
assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
end
- attribute \src "ls180.v:1794.5-1794.58"
- process $proc$ls180.v:1794$3552
+ attribute \src "ls180.v:1810.5-1810.58"
+ process $proc$ls180.v:1810$3564
assign { } { }
assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
end
- attribute \src "ls180.v:1795.5-1795.56"
- process $proc$ls180.v:1795$3553
+ attribute \src "ls180.v:1811.5-1811.56"
+ process $proc$ls180.v:1811$3565
assign { } { }
assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
sync always
sync init
update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
end
- attribute \src "ls180.v:1796.5-1796.59"
- process $proc$ls180.v:1796$3554
+ attribute \src "ls180.v:1812.5-1812.59"
+ process $proc$ls180.v:1812$3566
assign { } { }
assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
sync always
sync init
update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
end
- attribute \src "ls180.v:1797.11-1797.62"
- process $proc$ls180.v:1797$3555
+ attribute \src "ls180.v:1813.11-1813.62"
+ process $proc$ls180.v:1813$3567
assign { } { }
assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
sync always
sync init
update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
end
- attribute \src "ls180.v:1798.5-1798.59"
- process $proc$ls180.v:1798$3556
+ attribute \src "ls180.v:1814.5-1814.59"
+ process $proc$ls180.v:1814$3568
assign { } { }
assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
end
- attribute \src "ls180.v:1799.12-1799.65"
- process $proc$ls180.v:1799$3557
+ attribute \src "ls180.v:1815.12-1815.65"
+ process $proc$ls180.v:1815$3569
assign { } { }
assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
sync always
sync init
update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
end
- attribute \src "ls180.v:1800.5-1800.60"
- process $proc$ls180.v:1800$3558
+ attribute \src "ls180.v:1816.5-1816.60"
+ process $proc$ls180.v:1816$3570
assign { } { }
assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0
sync always
sync init
update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
end
- attribute \src "ls180.v:1801.5-1801.56"
- process $proc$ls180.v:1801$3559
+ attribute \src "ls180.v:1817.5-1817.56"
+ process $proc$ls180.v:1817$3571
assign { } { }
assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
end
- attribute \src "ls180.v:1802.5-1802.59"
- process $proc$ls180.v:1802$3560
+ attribute \src "ls180.v:1818.5-1818.59"
+ process $proc$ls180.v:1818$3572
assign { } { }
assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
end
- attribute \src "ls180.v:1803.5-1803.58"
- process $proc$ls180.v:1803$3561
+ attribute \src "ls180.v:1819.5-1819.58"
+ process $proc$ls180.v:1819$3573
assign { } { }
assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
end
- attribute \src "ls180.v:1804.5-1804.61"
- process $proc$ls180.v:1804$3562
+ attribute \src "ls180.v:182.12-182.53"
+ process $proc$ls180.v:182$2820
+ assign { } { }
+ assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync always
+ sync init
+ update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0]
+ end
+ attribute \src "ls180.v:1820.5-1820.61"
+ process $proc$ls180.v:1820$3574
assign { } { }
assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
end
- attribute \src "ls180.v:1805.5-1805.57"
- process $proc$ls180.v:1805$3563
+ attribute \src "ls180.v:1821.5-1821.57"
+ process $proc$ls180.v:1821$3575
assign { } { }
assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0
sync always
sync init
update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
end
- attribute \src "ls180.v:1806.5-1806.60"
- process $proc$ls180.v:1806$3564
+ attribute \src "ls180.v:1822.5-1822.60"
+ process $proc$ls180.v:1822$3576
assign { } { }
assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0
sync always
sync init
update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
end
- attribute \src "ls180.v:1807.5-1807.59"
- process $proc$ls180.v:1807$3565
+ attribute \src "ls180.v:1823.5-1823.59"
+ process $proc$ls180.v:1823$3577
assign { } { }
assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0
sync always
sync init
update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
end
- attribute \src "ls180.v:1808.5-1808.62"
- process $proc$ls180.v:1808$3566
+ attribute \src "ls180.v:1824.5-1824.62"
+ process $proc$ls180.v:1824$3578
assign { } { }
assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0
sync always
sync init
update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
end
- attribute \src "ls180.v:1809.13-1809.76"
- process $proc$ls180.v:1809$3567
+ attribute \src "ls180.v:1825.13-1825.76"
+ process $proc$ls180.v:1825$3579
assign { } { }
assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
end
- attribute \src "ls180.v:181.5-181.40"
- process $proc$ls180.v:181$2811
- assign { } { }
- assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0]
- end
- attribute \src "ls180.v:1810.5-1810.69"
- process $proc$ls180.v:1810$3568
+ attribute \src "ls180.v:1826.5-1826.69"
+ process $proc$ls180.v:1826$3580
assign { } { }
assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0
sync always
sync init
update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
end
- attribute \src "ls180.v:1811.11-1811.46"
- process $proc$ls180.v:1811$3569
+ attribute \src "ls180.v:1827.11-1827.46"
+ process $proc$ls180.v:1827$3581
assign { } { }
assign $1\builder_sdblock2memdma_state[1:0] 2'00
sync always
sync init
update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0]
end
- attribute \src "ls180.v:1812.11-1812.51"
- process $proc$ls180.v:1812$3570
+ attribute \src "ls180.v:1828.11-1828.51"
+ process $proc$ls180.v:1828$3582
assign { } { }
assign $1\builder_sdblock2memdma_next_state[1:0] 2'00
sync always
sync init
update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0]
end
- attribute \src "ls180.v:1813.12-1813.87"
- process $proc$ls180.v:1813$3571
+ attribute \src "ls180.v:1829.12-1829.87"
+ process $proc$ls180.v:1829$3583
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
end
- attribute \src "ls180.v:1814.5-1814.82"
- process $proc$ls180.v:1814$3572
+ attribute \src "ls180.v:1830.5-1830.82"
+ process $proc$ls180.v:1830$3584
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
end
- attribute \src "ls180.v:1815.5-1815.44"
- process $proc$ls180.v:1815$3573
+ attribute \src "ls180.v:1831.5-1831.44"
+ process $proc$ls180.v:1831$3585
assign { } { }
assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0
sync always
sync init
update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0]
end
- attribute \src "ls180.v:1816.5-1816.49"
- process $proc$ls180.v:1816$3574
+ attribute \src "ls180.v:1832.5-1832.49"
+ process $proc$ls180.v:1832$3586
assign { } { }
assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0
sync always
sync init
update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0]
end
- attribute \src "ls180.v:1817.12-1817.75"
- process $proc$ls180.v:1817$3575
+ attribute \src "ls180.v:1833.12-1833.75"
+ process $proc$ls180.v:1833$3587
assign { } { }
assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
end
- attribute \src "ls180.v:1818.5-1818.70"
- process $proc$ls180.v:1818$3576
+ attribute \src "ls180.v:1834.5-1834.70"
+ process $proc$ls180.v:1834$3588
assign { } { }
assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
end
- attribute \src "ls180.v:1819.11-1819.60"
- process $proc$ls180.v:1819$3577
+ attribute \src "ls180.v:1835.11-1835.60"
+ process $proc$ls180.v:1835$3589
assign { } { }
assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
sync always
sync init
update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0]
end
- attribute \src "ls180.v:1820.11-1820.65"
- process $proc$ls180.v:1820$3578
+ attribute \src "ls180.v:1836.11-1836.65"
+ process $proc$ls180.v:1836$3590
assign { } { }
assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00
sync always
sync init
update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0]
end
- attribute \src "ls180.v:1821.12-1821.87"
- process $proc$ls180.v:1821$3579
+ attribute \src "ls180.v:1837.12-1837.87"
+ process $proc$ls180.v:1837$3591
assign { } { }
assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
sync always
sync init
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
end
- attribute \src "ls180.v:1822.5-1822.82"
- process $proc$ls180.v:1822$3580
+ attribute \src "ls180.v:1838.5-1838.82"
+ process $proc$ls180.v:1838$3592
assign { } { }
assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0
sync always
sync init
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
end
- attribute \src "ls180.v:1823.11-1823.42"
- process $proc$ls180.v:1823$3581
+ attribute \src "ls180.v:1839.11-1839.42"
+ process $proc$ls180.v:1839$3593
assign { } { }
assign $1\builder_spimaster1_state[1:0] 2'00
sync always
sync init
update \builder_spimaster1_state $1\builder_spimaster1_state[1:0]
end
- attribute \src "ls180.v:1824.11-1824.47"
- process $proc$ls180.v:1824$3582
+ attribute \src "ls180.v:1840.11-1840.47"
+ process $proc$ls180.v:1840$3594
assign { } { }
assign $1\builder_spimaster1_next_state[1:0] 2'00
sync always
sync init
update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0]
end
- attribute \src "ls180.v:1825.11-1825.57"
- process $proc$ls180.v:1825$3583
+ attribute \src "ls180.v:1841.11-1841.57"
+ process $proc$ls180.v:1841$3595
assign { } { }
assign $1\libresocsim_count_spimaster1_next_value[2:0] 3'000
sync always
sync init
update \libresocsim_count_spimaster1_next_value $1\libresocsim_count_spimaster1_next_value[2:0]
end
- attribute \src "ls180.v:1826.5-1826.54"
- process $proc$ls180.v:1826$3584
+ attribute \src "ls180.v:1842.5-1842.54"
+ process $proc$ls180.v:1842$3596
assign { } { }
assign $1\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0
sync always
sync init
update \libresocsim_count_spimaster1_next_value_ce $1\libresocsim_count_spimaster1_next_value_ce[0:0]
end
- attribute \src "ls180.v:1827.12-1827.43"
- process $proc$ls180.v:1827$3585
+ attribute \src "ls180.v:1843.12-1843.43"
+ process $proc$ls180.v:1843$3597
assign { } { }
assign $1\builder_libresocsim_adr[13:0] 14'00000000000000
sync always
sync init
update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0]
end
- attribute \src "ls180.v:1828.5-1828.34"
- process $proc$ls180.v:1828$3586
+ attribute \src "ls180.v:1844.5-1844.34"
+ process $proc$ls180.v:1844$3598
assign { } { }
assign $1\builder_libresocsim_we[0:0] 1'0
sync always
sync init
update \builder_libresocsim_we $1\builder_libresocsim_we[0:0]
end
- attribute \src "ls180.v:1829.11-1829.43"
- process $proc$ls180.v:1829$3587
+ attribute \src "ls180.v:1845.11-1845.43"
+ process $proc$ls180.v:1845$3599
assign { } { }
assign $1\builder_libresocsim_dat_w[7:0] 8'00000000
sync always
sync init
update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0]
end
- attribute \src "ls180.v:1833.12-1833.54"
- process $proc$ls180.v:1833$3588
+ attribute \src "ls180.v:1849.12-1849.54"
+ process $proc$ls180.v:1849$3600
assign { } { }
assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0
sync always
sync init
update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0]
end
- attribute \src "ls180.v:1837.5-1837.44"
- process $proc$ls180.v:1837$3589
+ attribute \src "ls180.v:1853.5-1853.44"
+ process $proc$ls180.v:1853$3601
assign { } { }
assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0
sync always
sync init
update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0]
end
- attribute \src "ls180.v:1841.5-1841.44"
- process $proc$ls180.v:1841$3590
+ attribute \src "ls180.v:1857.5-1857.44"
+ process $proc$ls180.v:1857$3602
assign { } { }
assign $0\builder_libresocsim_wishbone_err[0:0] 1'0
sync always
update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0]
sync init
end
- attribute \src "ls180.v:1844.12-1844.40"
- process $proc$ls180.v:1844$3591
+ attribute \src "ls180.v:1860.12-1860.40"
+ process $proc$ls180.v:1860$3603
assign { } { }
assign $1\builder_shared_dat_r[31:0] 0
sync always
sync init
update \builder_shared_dat_r $1\builder_shared_dat_r[31:0]
end
- attribute \src "ls180.v:1848.5-1848.30"
- process $proc$ls180.v:1848$3592
+ attribute \src "ls180.v:1864.5-1864.30"
+ process $proc$ls180.v:1864$3604
assign { } { }
assign $1\builder_shared_ack[0:0] 1'0
sync always
sync init
update \builder_shared_ack $1\builder_shared_ack[0:0]
end
- attribute \src "ls180.v:185.5-185.40"
- process $proc$ls180.v:185$2812
- assign { } { }
- assign $0\main_libresocsim_ram_bus_err[0:0] 1'0
- sync always
- update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0]
- sync init
- end
- attribute \src "ls180.v:1854.11-1854.31"
- process $proc$ls180.v:1854$3593
+ attribute \src "ls180.v:1870.11-1870.31"
+ process $proc$ls180.v:1870$3605
assign { } { }
assign $1\builder_grant[2:0] 3'000
sync always
sync init
update \builder_grant $1\builder_grant[2:0]
end
- attribute \src "ls180.v:1855.11-1855.35"
- process $proc$ls180.v:1855$3594
+ attribute \src "ls180.v:1871.11-1871.35"
+ process $proc$ls180.v:1871$3606
assign { } { }
assign $1\builder_slave_sel[4:0] 5'00000
sync always
sync init
update \builder_slave_sel $1\builder_slave_sel[4:0]
end
- attribute \src "ls180.v:1856.11-1856.37"
- process $proc$ls180.v:1856$3595
+ attribute \src "ls180.v:1872.11-1872.37"
+ process $proc$ls180.v:1872$3607
assign { } { }
assign $1\builder_slave_sel_r[4:0] 5'00000
sync always
sync init
update \builder_slave_sel_r $1\builder_slave_sel_r[4:0]
end
- attribute \src "ls180.v:1857.5-1857.25"
- process $proc$ls180.v:1857$3596
+ attribute \src "ls180.v:1873.5-1873.25"
+ process $proc$ls180.v:1873$3608
assign { } { }
assign $1\builder_error[0:0] 1'0
sync always
sync init
update \builder_error $1\builder_error[0:0]
end
- attribute \src "ls180.v:1860.12-1860.39"
- process $proc$ls180.v:1860$3597
+ attribute \src "ls180.v:1876.12-1876.39"
+ process $proc$ls180.v:1876$3609
assign { } { }
assign $1\builder_count[19:0] 20'11110100001001000000
sync always
sync init
update \builder_count $1\builder_count[19:0]
end
- attribute \src "ls180.v:1864.11-1864.51"
- process $proc$ls180.v:1864$3598
+ attribute \src "ls180.v:1880.11-1880.51"
+ process $proc$ls180.v:1880$3610
assign { } { }
assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:188.11-188.37"
- process $proc$ls180.v:188$2813
+ attribute \src "ls180.v:189.5-189.40"
+ process $proc$ls180.v:189$2821
+ assign { } { }
+ assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0]
+ end
+ attribute \src "ls180.v:1921.11-1921.51"
+ process $proc$ls180.v:1921$3611
+ assign { } { }
+ assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000
+ sync always
+ sync init
+ update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0]
+ end
+ attribute \src "ls180.v:193.5-193.40"
+ process $proc$ls180.v:193$2822
+ assign { } { }
+ assign $0\main_libresocsim_ram_bus_err[0:0] 1'0
+ sync always
+ update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:1950.11-1950.51"
+ process $proc$ls180.v:1950$3612
+ assign { } { }
+ assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000
+ sync always
+ sync init
+ update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0]
+ end
+ attribute \src "ls180.v:196.11-196.37"
+ process $proc$ls180.v:196$2823
assign { } { }
assign $1\main_libresocsim_we[3:0] 4'0000
sync always
sync init
update \main_libresocsim_we $1\main_libresocsim_we[3:0]
end
- attribute \src "ls180.v:190.12-190.49"
- process $proc$ls180.v:190$2814
+ attribute \src "ls180.v:1963.11-1963.51"
+ process $proc$ls180.v:1963$3613
assign { } { }
- assign $1\main_libresocsim_load_storage[31:0] 0
+ assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0]
+ update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:1905.11-1905.51"
- process $proc$ls180.v:1905$3599
+ attribute \src "ls180.v:198.12-198.49"
+ process $proc$ls180.v:198$2824
assign { } { }
- assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\main_libresocsim_load_storage[31:0] 0
sync always
sync init
- update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0]
+ update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0]
end
- attribute \src "ls180.v:191.5-191.36"
- process $proc$ls180.v:191$2815
+ attribute \src "ls180.v:199.5-199.36"
+ process $proc$ls180.v:199$2825
assign { } { }
assign $1\main_libresocsim_load_re[0:0] 1'0
sync always
sync init
update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0]
end
- attribute \src "ls180.v:192.12-192.51"
- process $proc$ls180.v:192$2816
+ attribute \src "ls180.v:200.12-200.51"
+ process $proc$ls180.v:200$2826
assign { } { }
assign $1\main_libresocsim_reload_storage[31:0] 0
sync always
sync init
update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0]
end
- attribute \src "ls180.v:193.5-193.38"
- process $proc$ls180.v:193$2817
+ attribute \src "ls180.v:2004.11-2004.51"
+ process $proc$ls180.v:2004$3614
assign { } { }
- assign $1\main_libresocsim_reload_re[0:0] 1'0
+ assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0]
+ update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:1934.11-1934.51"
- process $proc$ls180.v:1934$3600
+ attribute \src "ls180.v:201.5-201.38"
+ process $proc$ls180.v:201$2827
assign { } { }
- assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\main_libresocsim_reload_re[0:0] 1'0
sync always
sync init
- update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0]
+ update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0]
end
- attribute \src "ls180.v:194.5-194.39"
- process $proc$ls180.v:194$2818
+ attribute \src "ls180.v:202.5-202.39"
+ process $proc$ls180.v:202$2828
assign { } { }
assign $1\main_libresocsim_en_storage[0:0] 1'0
sync always
sync init
update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0]
end
- attribute \src "ls180.v:195.5-195.34"
- process $proc$ls180.v:195$2819
+ attribute \src "ls180.v:203.5-203.34"
+ process $proc$ls180.v:203$2829
assign { } { }
assign $1\main_libresocsim_en_re[0:0] 1'0
sync always
sync init
update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0]
end
- attribute \src "ls180.v:196.5-196.49"
- process $proc$ls180.v:196$2820
+ attribute \src "ls180.v:204.5-204.49"
+ process $proc$ls180.v:204$2830
assign { } { }
assign $1\main_libresocsim_update_value_storage[0:0] 1'0
sync always
sync init
update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0]
end
- attribute \src "ls180.v:197.5-197.44"
- process $proc$ls180.v:197$2821
+ attribute \src "ls180.v:2045.11-2045.51"
+ process $proc$ls180.v:2045$3615
assign { } { }
- assign $1\main_libresocsim_update_value_re[0:0] 1'0
+ assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0]
+ update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:1975.11-1975.51"
- process $proc$ls180.v:1975$3601
+ attribute \src "ls180.v:205.5-205.44"
+ process $proc$ls180.v:205$2831
assign { } { }
- assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\main_libresocsim_update_value_re[0:0] 1'0
sync always
sync init
- update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0]
+ update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0]
end
- attribute \src "ls180.v:198.12-198.49"
- process $proc$ls180.v:198$2822
+ attribute \src "ls180.v:206.12-206.49"
+ process $proc$ls180.v:206$2832
assign { } { }
assign $1\main_libresocsim_value_status[31:0] 0
sync always
sync init
update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0]
end
- attribute \src "ls180.v:2016.11-2016.51"
- process $proc$ls180.v:2016$3602
+ attribute \src "ls180.v:210.5-210.41"
+ process $proc$ls180.v:210$2833
assign { } { }
- assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\main_libresocsim_zero_pending[0:0] 1'0
sync always
sync init
- update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0]
+ update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0]
end
- attribute \src "ls180.v:202.5-202.41"
- process $proc$ls180.v:202$2823
+ attribute \src "ls180.v:2110.11-2110.51"
+ process $proc$ls180.v:2110$3616
assign { } { }
- assign $1\main_libresocsim_zero_pending[0:0] 1'0
+ assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0]
+ update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:204.5-204.39"
- process $proc$ls180.v:204$2824
+ attribute \src "ls180.v:212.5-212.39"
+ process $proc$ls180.v:212$2834
assign { } { }
assign $1\main_libresocsim_zero_clear[0:0] 1'0
sync always
sync init
update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0]
end
- attribute \src "ls180.v:205.5-205.45"
- process $proc$ls180.v:205$2825
+ attribute \src "ls180.v:213.5-213.45"
+ process $proc$ls180.v:213$2835
assign { } { }
assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0
sync always
sync init
update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0]
end
- attribute \src "ls180.v:2081.11-2081.51"
- process $proc$ls180.v:2081$3603
- assign { } { }
- assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000
- sync always
- sync init
- update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0]
- end
- attribute \src "ls180.v:214.5-214.49"
- process $proc$ls180.v:214$2826
+ attribute \src "ls180.v:222.5-222.49"
+ process $proc$ls180.v:222$2836
assign { } { }
assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0
sync always
sync init
update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0]
end
- attribute \src "ls180.v:215.5-215.44"
- process $proc$ls180.v:215$2827
+ attribute \src "ls180.v:223.5-223.44"
+ process $proc$ls180.v:223$2837
assign { } { }
assign $1\main_libresocsim_eventmanager_re[0:0] 1'0
sync always
sync init
update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0]
end
- attribute \src "ls180.v:216.12-216.42"
- process $proc$ls180.v:216$2828
+ attribute \src "ls180.v:224.12-224.42"
+ process $proc$ls180.v:224$2838
assign { } { }
assign $1\main_libresocsim_value[31:0] 0
sync always
sync init
update \main_libresocsim_value $1\main_libresocsim_value[31:0]
end
- attribute \src "ls180.v:220.5-220.24"
- process $proc$ls180.v:220$2829
+ attribute \src "ls180.v:2243.11-2243.51"
+ process $proc$ls180.v:2243$3617
+ assign { } { }
+ assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000
+ sync always
+ sync init
+ update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0]
+ end
+ attribute \src "ls180.v:228.5-228.24"
+ process $proc$ls180.v:228$2839
assign { } { }
assign $1\main_int_rst[0:0] 1'1
sync always
sync init
update \main_int_rst $1\main_int_rst[0:0]
end
- attribute \src "ls180.v:2214.11-2214.51"
- process $proc$ls180.v:2214$3604
+ attribute \src "ls180.v:2324.11-2324.51"
+ process $proc$ls180.v:2324$3618
assign { } { }
- assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0]
+ update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:2295.11-2295.51"
- process $proc$ls180.v:2295$3605
+ attribute \src "ls180.v:2341.11-2341.51"
+ process $proc$ls180.v:2341$3619
assign { } { }
- assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0]
+ update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:2312.11-2312.51"
- process $proc$ls180.v:2312$3606
+ attribute \src "ls180.v:2382.11-2382.52"
+ process $proc$ls180.v:2382$3620
assign { } { }
- assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0]
+ update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:235.12-235.38"
- process $proc$ls180.v:235$2830
+ attribute \src "ls180.v:2415.11-2415.52"
+ process $proc$ls180.v:2415$3621
assign { } { }
- assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000
+ assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0]
+ update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:2353.11-2353.51"
- process $proc$ls180.v:2353$3607
+ attribute \src "ls180.v:243.12-243.38"
+ process $proc$ls180.v:243$2840
assign { } { }
- assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000
sync always
sync init
- update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0]
+ update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0]
end
- attribute \src "ls180.v:236.5-236.36"
- process $proc$ls180.v:236$2831
+ attribute \src "ls180.v:244.5-244.36"
+ process $proc$ls180.v:244$2841
assign { } { }
assign $1\main_dfi_p0_rddata_valid[0:0] 1'0
sync always
sync init
update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0]
end
- attribute \src "ls180.v:237.11-237.32"
- process $proc$ls180.v:237$2832
+ attribute \src "ls180.v:245.11-245.32"
+ process $proc$ls180.v:245$2842
assign { } { }
assign $1\main_rddata_en[2:0] 3'000
sync always
sync init
update \main_rddata_en $1\main_rddata_en[2:0]
end
- attribute \src "ls180.v:2386.11-2386.52"
- process $proc$ls180.v:2386$3608
+ attribute \src "ls180.v:2456.11-2456.52"
+ process $proc$ls180.v:2456$3622
assign { } { }
- assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000
+ assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0]
+ update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:240.5-240.36"
- process $proc$ls180.v:240$2833
+ attribute \src "ls180.v:248.5-248.36"
+ process $proc$ls180.v:248$2843
assign { } { }
assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1
sync always
sync init
update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0]
end
- attribute \src "ls180.v:241.5-241.35"
- process $proc$ls180.v:241$2834
+ attribute \src "ls180.v:249.5-249.35"
+ process $proc$ls180.v:249$2844
assign { } { }
assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1
sync always
sync init
update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0]
end
- attribute \src "ls180.v:242.5-242.36"
- process $proc$ls180.v:242$2835
+ attribute \src "ls180.v:250.5-250.36"
+ process $proc$ls180.v:250$2845
assign { } { }
assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1
sync always
sync init
update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0]
end
- attribute \src "ls180.v:2427.11-2427.52"
- process $proc$ls180.v:2427$3609
- assign { } { }
- assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000
- sync always
- sync init
- update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0]
- end
- attribute \src "ls180.v:243.5-243.35"
- process $proc$ls180.v:243$2836
+ attribute \src "ls180.v:251.5-251.35"
+ process $proc$ls180.v:251$2846
assign { } { }
assign $1\main_sdram_inti_p0_we_n[0:0] 1'1
sync always
sync init
update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0]
end
- attribute \src "ls180.v:247.5-247.36"
- process $proc$ls180.v:247$2837
- assign { } { }
- assign $0\main_sdram_inti_p0_act_n[0:0] 1'1
- sync always
- update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0]
- sync init
- end
- attribute \src "ls180.v:2492.11-2492.52"
- process $proc$ls180.v:2492$3610
- assign { } { }
- assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000
- sync always
- sync init
- update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0]
- end
- attribute \src "ls180.v:2517.11-2517.52"
- process $proc$ls180.v:2517$3611
+ attribute \src "ls180.v:2521.11-2521.52"
+ process $proc$ls180.v:2521$3623
assign { } { }
assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:252.12-252.45"
- process $proc$ls180.v:252$2838
+ attribute \src "ls180.v:2546.11-2546.52"
+ process $proc$ls180.v:2546$3624
assign { } { }
- assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
+ assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
- update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0]
+ update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:253.5-253.43"
- process $proc$ls180.v:253$2839
+ attribute \src "ls180.v:255.5-255.36"
+ process $proc$ls180.v:255$2847
assign { } { }
- assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0
+ assign $0\main_sdram_inti_p0_act_n[0:0] 1'1
sync always
+ update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0]
sync init
- update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0]
end
- attribute \src "ls180.v:2539.11-2539.31"
- process $proc$ls180.v:2539$3612
+ attribute \src "ls180.v:2568.11-2568.31"
+ process $proc$ls180.v:2568$3625
assign { } { }
assign $1\builder_state[1:0] 2'00
sync always
sync init
update \builder_state $1\builder_state[1:0]
end
- attribute \src "ls180.v:2540.11-2540.36"
- process $proc$ls180.v:2540$3613
+ attribute \src "ls180.v:2569.11-2569.36"
+ process $proc$ls180.v:2569$3626
assign { } { }
assign $1\builder_next_state[1:0] 2'00
sync always
sync init
update \builder_next_state $1\builder_next_state[1:0]
end
- attribute \src "ls180.v:2541.11-2541.55"
- process $proc$ls180.v:2541$3614
+ attribute \src "ls180.v:2570.11-2570.55"
+ process $proc$ls180.v:2570$3627
assign { } { }
assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000
sync always
sync init
update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0]
end
- attribute \src "ls180.v:2542.5-2542.52"
- process $proc$ls180.v:2542$3615
+ attribute \src "ls180.v:2571.5-2571.52"
+ process $proc$ls180.v:2571$3628
assign { } { }
assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0
sync always
sync init
update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0]
end
- attribute \src "ls180.v:2543.12-2543.55"
- process $proc$ls180.v:2543$3616
+ attribute \src "ls180.v:2572.12-2572.55"
+ process $proc$ls180.v:2572$3629
assign { } { }
assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000
sync always
sync init
update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0]
end
- attribute \src "ls180.v:2544.5-2544.50"
- process $proc$ls180.v:2544$3617
+ attribute \src "ls180.v:2573.5-2573.50"
+ process $proc$ls180.v:2573$3630
assign { } { }
assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
sync always
sync init
update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0]
end
- attribute \src "ls180.v:2545.5-2545.46"
- process $proc$ls180.v:2545$3618
+ attribute \src "ls180.v:2574.5-2574.46"
+ process $proc$ls180.v:2574$3631
assign { } { }
assign $1\builder_libresocsim_we_next_value2[0:0] 1'0
sync always
sync init
update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0]
end
- attribute \src "ls180.v:2546.5-2546.49"
- process $proc$ls180.v:2546$3619
+ attribute \src "ls180.v:2575.5-2575.49"
+ process $proc$ls180.v:2575$3632
assign { } { }
assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0
sync always
sync init
update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0]
end
- attribute \src "ls180.v:2547.5-2547.41"
- process $proc$ls180.v:2547$3620
+ attribute \src "ls180.v:2576.5-2576.41"
+ process $proc$ls180.v:2576$3633
assign { } { }
assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0]
end
- attribute \src "ls180.v:2548.12-2548.49"
- process $proc$ls180.v:2548$3621
+ attribute \src "ls180.v:2577.12-2577.49"
+ process $proc$ls180.v:2577$3634
assign { } { }
assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000
sync always
sync init
update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0]
end
- attribute \src "ls180.v:2549.11-2549.47"
- process $proc$ls180.v:2549$3622
+ attribute \src "ls180.v:2578.11-2578.47"
+ process $proc$ls180.v:2578$3635
assign { } { }
assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00
sync always
sync init
update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0]
end
- attribute \src "ls180.v:2550.5-2550.41"
- process $proc$ls180.v:2550$3623
+ attribute \src "ls180.v:2579.5-2579.41"
+ process $proc$ls180.v:2579$3636
assign { } { }
assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0]
end
- attribute \src "ls180.v:2551.5-2551.41"
- process $proc$ls180.v:2551$3624
+ attribute \src "ls180.v:2580.5-2580.41"
+ process $proc$ls180.v:2580$3637
assign { } { }
assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0]
end
- attribute \src "ls180.v:2552.5-2552.41"
- process $proc$ls180.v:2552$3625
+ attribute \src "ls180.v:2581.5-2581.41"
+ process $proc$ls180.v:2581$3638
assign { } { }
assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0]
end
- attribute \src "ls180.v:2553.5-2553.39"
- process $proc$ls180.v:2553$3626
+ attribute \src "ls180.v:2582.5-2582.39"
+ process $proc$ls180.v:2582$3639
assign { } { }
assign $1\builder_comb_t_array_muxed0[0:0] 1'0
sync always
sync init
update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0]
end
- attribute \src "ls180.v:2554.5-2554.39"
- process $proc$ls180.v:2554$3627
+ attribute \src "ls180.v:2583.5-2583.39"
+ process $proc$ls180.v:2583$3640
assign { } { }
assign $1\builder_comb_t_array_muxed1[0:0] 1'0
sync always
sync init
update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0]
end
- attribute \src "ls180.v:2555.5-2555.39"
- process $proc$ls180.v:2555$3628
+ attribute \src "ls180.v:2584.5-2584.39"
+ process $proc$ls180.v:2584$3641
assign { } { }
assign $1\builder_comb_t_array_muxed2[0:0] 1'0
sync always
sync init
update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0]
end
- attribute \src "ls180.v:2556.5-2556.41"
- process $proc$ls180.v:2556$3629
+ attribute \src "ls180.v:2585.5-2585.41"
+ process $proc$ls180.v:2585$3642
assign { } { }
assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0]
end
- attribute \src "ls180.v:2557.12-2557.49"
- process $proc$ls180.v:2557$3630
+ attribute \src "ls180.v:2586.12-2586.49"
+ process $proc$ls180.v:2586$3643
assign { } { }
assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000
sync always
sync init
update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0]
end
- attribute \src "ls180.v:2558.11-2558.47"
- process $proc$ls180.v:2558$3631
+ attribute \src "ls180.v:2587.11-2587.47"
+ process $proc$ls180.v:2587$3644
assign { } { }
assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00
sync always
sync init
update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0]
end
- attribute \src "ls180.v:2559.5-2559.41"
- process $proc$ls180.v:2559$3632
+ attribute \src "ls180.v:2588.5-2588.41"
+ process $proc$ls180.v:2588$3645
assign { } { }
assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0]
end
- attribute \src "ls180.v:2560.5-2560.42"
- process $proc$ls180.v:2560$3633
+ attribute \src "ls180.v:2589.5-2589.42"
+ process $proc$ls180.v:2589$3646
assign { } { }
assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0]
end
- attribute \src "ls180.v:2561.5-2561.42"
- process $proc$ls180.v:2561$3634
+ attribute \src "ls180.v:2590.5-2590.42"
+ process $proc$ls180.v:2590$3647
assign { } { }
assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0]
end
- attribute \src "ls180.v:2562.5-2562.39"
- process $proc$ls180.v:2562$3635
+ attribute \src "ls180.v:2591.5-2591.39"
+ process $proc$ls180.v:2591$3648
assign { } { }
assign $1\builder_comb_t_array_muxed3[0:0] 1'0
sync always
sync init
update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0]
end
- attribute \src "ls180.v:2563.5-2563.39"
- process $proc$ls180.v:2563$3636
+ attribute \src "ls180.v:2592.5-2592.39"
+ process $proc$ls180.v:2592$3649
assign { } { }
assign $1\builder_comb_t_array_muxed4[0:0] 1'0
sync always
sync init
update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0]
end
- attribute \src "ls180.v:2564.5-2564.39"
- process $proc$ls180.v:2564$3637
+ attribute \src "ls180.v:2593.5-2593.39"
+ process $proc$ls180.v:2593$3650
assign { } { }
assign $1\builder_comb_t_array_muxed5[0:0] 1'0
sync always
sync init
update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0]
end
- attribute \src "ls180.v:2565.12-2565.50"
- process $proc$ls180.v:2565$3638
+ attribute \src "ls180.v:2594.12-2594.50"
+ process $proc$ls180.v:2594$3651
assign { } { }
assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000
sync always
sync init
update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0]
end
- attribute \src "ls180.v:2566.5-2566.42"
- process $proc$ls180.v:2566$3639
+ attribute \src "ls180.v:2595.5-2595.42"
+ process $proc$ls180.v:2595$3652
assign { } { }
assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0]
end
- attribute \src "ls180.v:2567.5-2567.42"
- process $proc$ls180.v:2567$3640
+ attribute \src "ls180.v:2596.5-2596.42"
+ process $proc$ls180.v:2596$3653
assign { } { }
assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0]
end
- attribute \src "ls180.v:2568.12-2568.50"
- process $proc$ls180.v:2568$3641
+ attribute \src "ls180.v:2597.12-2597.50"
+ process $proc$ls180.v:2597$3654
assign { } { }
assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000
sync always
sync init
update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0]
end
- attribute \src "ls180.v:2569.5-2569.42"
- process $proc$ls180.v:2569$3642
+ attribute \src "ls180.v:2598.5-2598.42"
+ process $proc$ls180.v:2598$3655
assign { } { }
assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0]
end
- attribute \src "ls180.v:2570.5-2570.42"
- process $proc$ls180.v:2570$3643
+ attribute \src "ls180.v:2599.5-2599.42"
+ process $proc$ls180.v:2599$3656
assign { } { }
assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0]
end
- attribute \src "ls180.v:2571.12-2571.50"
- process $proc$ls180.v:2571$3644
+ attribute \src "ls180.v:260.12-260.45"
+ process $proc$ls180.v:260$2848
+ assign { } { }
+ assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0]
+ end
+ attribute \src "ls180.v:2600.12-2600.50"
+ process $proc$ls180.v:2600$3657
assign { } { }
assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000
sync always
sync init
update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0]
end
- attribute \src "ls180.v:2572.5-2572.42"
- process $proc$ls180.v:2572$3645
+ attribute \src "ls180.v:2601.5-2601.42"
+ process $proc$ls180.v:2601$3658
assign { } { }
assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0]
end
- attribute \src "ls180.v:2573.5-2573.42"
- process $proc$ls180.v:2573$3646
+ attribute \src "ls180.v:2602.5-2602.42"
+ process $proc$ls180.v:2602$3659
assign { } { }
assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0]
end
- attribute \src "ls180.v:2574.12-2574.50"
- process $proc$ls180.v:2574$3647
+ attribute \src "ls180.v:2603.12-2603.50"
+ process $proc$ls180.v:2603$3660
assign { } { }
assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000
sync always
sync init
update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0]
end
- attribute \src "ls180.v:2575.5-2575.42"
- process $proc$ls180.v:2575$3648
+ attribute \src "ls180.v:2604.5-2604.42"
+ process $proc$ls180.v:2604$3661
assign { } { }
assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0]
end
- attribute \src "ls180.v:2576.5-2576.42"
- process $proc$ls180.v:2576$3649
+ attribute \src "ls180.v:2605.5-2605.42"
+ process $proc$ls180.v:2605$3662
assign { } { }
assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0]
end
- attribute \src "ls180.v:2577.12-2577.50"
- process $proc$ls180.v:2577$3650
+ attribute \src "ls180.v:2606.12-2606.50"
+ process $proc$ls180.v:2606$3663
assign { } { }
assign $1\builder_comb_rhs_array_muxed24[31:0] 0
sync always
sync init
update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0]
end
- attribute \src "ls180.v:2578.12-2578.50"
- process $proc$ls180.v:2578$3651
+ attribute \src "ls180.v:2607.12-2607.50"
+ process $proc$ls180.v:2607$3664
assign { } { }
assign $1\builder_comb_rhs_array_muxed25[31:0] 0
sync always
sync init
update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0]
end
- attribute \src "ls180.v:2579.11-2579.48"
- process $proc$ls180.v:2579$3652
+ attribute \src "ls180.v:2608.11-2608.48"
+ process $proc$ls180.v:2608$3665
assign { } { }
assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000
sync always
sync init
update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0]
end
- attribute \src "ls180.v:2580.5-2580.42"
- process $proc$ls180.v:2580$3653
+ attribute \src "ls180.v:2609.5-2609.42"
+ process $proc$ls180.v:2609$3666
assign { } { }
assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0]
end
- attribute \src "ls180.v:2581.5-2581.42"
- process $proc$ls180.v:2581$3654
+ attribute \src "ls180.v:261.5-261.43"
+ process $proc$ls180.v:261$2849
+ assign { } { }
+ assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0]
+ end
+ attribute \src "ls180.v:2610.5-2610.42"
+ process $proc$ls180.v:2610$3667
assign { } { }
assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0]
end
- attribute \src "ls180.v:2582.5-2582.42"
- process $proc$ls180.v:2582$3655
+ attribute \src "ls180.v:2611.5-2611.42"
+ process $proc$ls180.v:2611$3668
assign { } { }
assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0
sync always
sync init
update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0]
end
- attribute \src "ls180.v:2583.11-2583.48"
- process $proc$ls180.v:2583$3656
+ attribute \src "ls180.v:2612.11-2612.48"
+ process $proc$ls180.v:2612$3669
assign { } { }
assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000
sync always
sync init
update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0]
end
- attribute \src "ls180.v:2584.11-2584.48"
- process $proc$ls180.v:2584$3657
+ attribute \src "ls180.v:2613.11-2613.48"
+ process $proc$ls180.v:2613$3670
assign { } { }
assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00
sync always
sync init
update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0]
end
- attribute \src "ls180.v:2585.11-2585.47"
- process $proc$ls180.v:2585$3658
+ attribute \src "ls180.v:2614.11-2614.47"
+ process $proc$ls180.v:2614$3671
assign { } { }
assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00
sync always
sync init
update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0]
end
- attribute \src "ls180.v:2586.12-2586.49"
- process $proc$ls180.v:2586$3659
+ attribute \src "ls180.v:2615.12-2615.49"
+ process $proc$ls180.v:2615$3672
assign { } { }
assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000
sync always
sync init
update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0]
end
- attribute \src "ls180.v:2587.5-2587.41"
- process $proc$ls180.v:2587$3660
+ attribute \src "ls180.v:2616.5-2616.41"
+ process $proc$ls180.v:2616$3673
assign { } { }
assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0
sync always
sync init
update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0]
end
- attribute \src "ls180.v:2588.5-2588.41"
- process $proc$ls180.v:2588$3661
+ attribute \src "ls180.v:2617.5-2617.41"
+ process $proc$ls180.v:2617$3674
assign { } { }
assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0
sync always
sync init
update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0]
end
- attribute \src "ls180.v:2589.5-2589.41"
- process $proc$ls180.v:2589$3662
+ attribute \src "ls180.v:2618.5-2618.41"
+ process $proc$ls180.v:2618$3675
assign { } { }
assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0
sync always
sync init
update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0]
end
- attribute \src "ls180.v:2590.5-2590.41"
- process $proc$ls180.v:2590$3663
+ attribute \src "ls180.v:2619.5-2619.41"
+ process $proc$ls180.v:2619$3676
assign { } { }
assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0
sync always
sync init
update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0]
end
- attribute \src "ls180.v:2591.5-2591.41"
- process $proc$ls180.v:2591$3664
+ attribute \src "ls180.v:2620.5-2620.41"
+ process $proc$ls180.v:2620$3677
assign { } { }
assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0
sync always
sync init
update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0]
end
- attribute \src "ls180.v:2592.5-2592.39"
- process $proc$ls180.v:2592$3665
+ attribute \src "ls180.v:2621.5-2621.39"
+ process $proc$ls180.v:2621$3678
assign { } { }
assign $1\builder_sync_f_array_muxed0[0:0] 1'0
sync always
sync init
update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0]
end
- attribute \src "ls180.v:2593.5-2593.39"
- process $proc$ls180.v:2593$3666
+ attribute \src "ls180.v:2622.5-2622.39"
+ process $proc$ls180.v:2622$3679
assign { } { }
assign $1\builder_sync_f_array_muxed1[0:0] 1'0
sync always
sync init
update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0]
end
- attribute \src "ls180.v:2650.32-2650.66"
- process $proc$ls180.v:2650$3667
+ attribute \src "ls180.v:2679.32-2679.66"
+ process $proc$ls180.v:2679$3680
assign { } { }
assign $1\builder_multiregimpl0_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0]
end
- attribute \src "ls180.v:2651.32-2651.66"
- process $proc$ls180.v:2651$3668
+ attribute \src "ls180.v:2680.32-2680.66"
+ process $proc$ls180.v:2680$3681
assign { } { }
assign $1\builder_multiregimpl0_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0]
end
- attribute \src "ls180.v:2652.32-2652.66"
- process $proc$ls180.v:2652$3669
+ attribute \src "ls180.v:2681.32-2681.66"
+ process $proc$ls180.v:2681$3682
assign { } { }
assign $1\builder_multiregimpl1_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0]
end
- attribute \src "ls180.v:2653.32-2653.66"
- process $proc$ls180.v:2653$3670
+ attribute \src "ls180.v:2682.32-2682.66"
+ process $proc$ls180.v:2682$3683
assign { } { }
assign $1\builder_multiregimpl1_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0]
end
- attribute \src "ls180.v:2654.32-2654.66"
- process $proc$ls180.v:2654$3671
+ attribute \src "ls180.v:2683.32-2683.66"
+ process $proc$ls180.v:2683$3684
assign { } { }
assign $1\builder_multiregimpl2_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0]
end
- attribute \src "ls180.v:2655.32-2655.66"
- process $proc$ls180.v:2655$3672
+ attribute \src "ls180.v:2684.32-2684.66"
+ process $proc$ls180.v:2684$3685
assign { } { }
assign $1\builder_multiregimpl2_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0]
end
- attribute \src "ls180.v:2656.32-2656.66"
- process $proc$ls180.v:2656$3673
+ attribute \src "ls180.v:2685.32-2685.66"
+ process $proc$ls180.v:2685$3686
assign { } { }
assign $1\builder_multiregimpl3_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0]
end
- attribute \src "ls180.v:2657.32-2657.66"
- process $proc$ls180.v:2657$3674
+ attribute \src "ls180.v:2686.32-2686.66"
+ process $proc$ls180.v:2686$3687
assign { } { }
assign $1\builder_multiregimpl3_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0]
end
- attribute \src "ls180.v:2658.32-2658.66"
- process $proc$ls180.v:2658$3675
+ attribute \src "ls180.v:2687.32-2687.66"
+ process $proc$ls180.v:2687$3688
assign { } { }
assign $1\builder_multiregimpl4_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0]
end
- attribute \src "ls180.v:2659.32-2659.66"
- process $proc$ls180.v:2659$3676
+ attribute \src "ls180.v:2688.32-2688.66"
+ process $proc$ls180.v:2688$3689
assign { } { }
assign $1\builder_multiregimpl4_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0]
end
- attribute \src "ls180.v:2660.32-2660.66"
- process $proc$ls180.v:2660$3677
+ attribute \src "ls180.v:2689.32-2689.66"
+ process $proc$ls180.v:2689$3690
assign { } { }
assign $1\builder_multiregimpl5_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0]
end
- attribute \src "ls180.v:2661.32-2661.66"
- process $proc$ls180.v:2661$3678
+ attribute \src "ls180.v:2690.32-2690.66"
+ process $proc$ls180.v:2690$3691
assign { } { }
assign $1\builder_multiregimpl5_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0]
end
- attribute \src "ls180.v:2662.32-2662.66"
- process $proc$ls180.v:2662$3679
+ attribute \src "ls180.v:2691.32-2691.66"
+ process $proc$ls180.v:2691$3692
assign { } { }
assign $1\builder_multiregimpl6_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0]
end
- attribute \src "ls180.v:2663.32-2663.66"
- process $proc$ls180.v:2663$3680
+ attribute \src "ls180.v:2692.32-2692.66"
+ process $proc$ls180.v:2692$3693
assign { } { }
assign $1\builder_multiregimpl6_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0]
end
- attribute \src "ls180.v:2664.32-2664.66"
- process $proc$ls180.v:2664$3681
+ attribute \src "ls180.v:2693.32-2693.66"
+ process $proc$ls180.v:2693$3694
assign { } { }
assign $1\builder_multiregimpl7_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0]
end
- attribute \src "ls180.v:2665.32-2665.66"
- process $proc$ls180.v:2665$3682
+ attribute \src "ls180.v:2694.32-2694.66"
+ process $proc$ls180.v:2694$3695
assign { } { }
assign $1\builder_multiregimpl7_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0]
end
- attribute \src "ls180.v:2666.32-2666.66"
- process $proc$ls180.v:2666$3683
+ attribute \src "ls180.v:2695.32-2695.66"
+ process $proc$ls180.v:2695$3696
assign { } { }
assign $1\builder_multiregimpl8_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0]
end
- attribute \src "ls180.v:2667.32-2667.66"
- process $proc$ls180.v:2667$3684
+ attribute \src "ls180.v:2696.32-2696.66"
+ process $proc$ls180.v:2696$3697
assign { } { }
assign $1\builder_multiregimpl8_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0]
end
- attribute \src "ls180.v:2668.32-2668.66"
- process $proc$ls180.v:2668$3685
+ attribute \src "ls180.v:2697.32-2697.66"
+ process $proc$ls180.v:2697$3698
assign { } { }
assign $1\builder_multiregimpl9_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0]
end
- attribute \src "ls180.v:2669.32-2669.66"
- process $proc$ls180.v:2669$3686
+ attribute \src "ls180.v:2698.32-2698.66"
+ process $proc$ls180.v:2698$3699
assign { } { }
assign $1\builder_multiregimpl9_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0]
end
- attribute \src "ls180.v:2670.32-2670.67"
- process $proc$ls180.v:2670$3687
+ attribute \src "ls180.v:2699.32-2699.67"
+ process $proc$ls180.v:2699$3700
assign { } { }
assign $1\builder_multiregimpl10_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0]
end
- attribute \src "ls180.v:2671.32-2671.67"
- process $proc$ls180.v:2671$3688
+ attribute \src "ls180.v:2700.32-2700.67"
+ process $proc$ls180.v:2700$3701
assign { } { }
assign $1\builder_multiregimpl10_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0]
end
- attribute \src "ls180.v:2672.32-2672.67"
- process $proc$ls180.v:2672$3689
+ attribute \src "ls180.v:2701.32-2701.67"
+ process $proc$ls180.v:2701$3702
assign { } { }
assign $1\builder_multiregimpl11_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0]
end
- attribute \src "ls180.v:2673.32-2673.67"
- process $proc$ls180.v:2673$3690
+ attribute \src "ls180.v:2702.32-2702.67"
+ process $proc$ls180.v:2702$3703
assign { } { }
assign $1\builder_multiregimpl11_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0]
end
- attribute \src "ls180.v:2674.32-2674.67"
- process $proc$ls180.v:2674$3691
+ attribute \src "ls180.v:2703.32-2703.67"
+ process $proc$ls180.v:2703$3704
assign { } { }
assign $1\builder_multiregimpl12_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0]
end
- attribute \src "ls180.v:2675.32-2675.67"
- process $proc$ls180.v:2675$3692
+ attribute \src "ls180.v:2704.32-2704.67"
+ process $proc$ls180.v:2704$3705
assign { } { }
assign $1\builder_multiregimpl12_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0]
end
- attribute \src "ls180.v:2676.32-2676.67"
- process $proc$ls180.v:2676$3693
+ attribute \src "ls180.v:2705.32-2705.67"
+ process $proc$ls180.v:2705$3706
assign { } { }
assign $1\builder_multiregimpl13_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0]
end
- attribute \src "ls180.v:2677.32-2677.67"
- process $proc$ls180.v:2677$3694
+ attribute \src "ls180.v:2706.32-2706.67"
+ process $proc$ls180.v:2706$3707
assign { } { }
assign $1\builder_multiregimpl13_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0]
end
- attribute \src "ls180.v:2678.32-2678.67"
- process $proc$ls180.v:2678$3695
+ attribute \src "ls180.v:2707.32-2707.67"
+ process $proc$ls180.v:2707$3708
assign { } { }
assign $1\builder_multiregimpl14_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0]
end
- attribute \src "ls180.v:2679.32-2679.67"
- process $proc$ls180.v:2679$3696
+ attribute \src "ls180.v:2708.32-2708.67"
+ process $proc$ls180.v:2708$3709
assign { } { }
assign $1\builder_multiregimpl14_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0]
end
- attribute \src "ls180.v:268.12-268.46"
- process $proc$ls180.v:268$2840
- assign { } { }
- assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000
- sync always
- sync init
- update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0]
- end
- attribute \src "ls180.v:2680.32-2680.67"
- process $proc$ls180.v:2680$3697
+ attribute \src "ls180.v:2709.32-2709.67"
+ process $proc$ls180.v:2709$3710
assign { } { }
assign $1\builder_multiregimpl15_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0]
end
- attribute \src "ls180.v:2681.32-2681.67"
- process $proc$ls180.v:2681$3698
+ attribute \src "ls180.v:2710.32-2710.67"
+ process $proc$ls180.v:2710$3711
assign { } { }
assign $1\builder_multiregimpl15_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0]
end
- attribute \src "ls180.v:2682.32-2682.67"
- process $proc$ls180.v:2682$3699
+ attribute \src "ls180.v:2711.32-2711.67"
+ process $proc$ls180.v:2711$3712
assign { } { }
assign $1\builder_multiregimpl16_regs0[0:0] 1'0
sync always
sync init
update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0]
end
- attribute \src "ls180.v:2683.32-2683.67"
- process $proc$ls180.v:2683$3700
+ attribute \src "ls180.v:2712.32-2712.67"
+ process $proc$ls180.v:2712$3713
assign { } { }
assign $1\builder_multiregimpl16_regs1[0:0] 1'0
sync always
sync init
update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0]
end
- attribute \src "ls180.v:269.5-269.44"
- process $proc$ls180.v:269$2841
- assign { } { }
- assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0
- sync always
- sync init
- update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0]
- end
- attribute \src "ls180.v:270.12-270.48"
- process $proc$ls180.v:270$2842
- assign { } { }
- assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000
- sync always
- sync init
- update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0]
- end
- attribute \src "ls180.v:271.11-271.43"
- process $proc$ls180.v:271$2843
- assign { } { }
- assign $1\main_sdram_master_p0_bank[1:0] 2'00
- sync always
- sync init
- update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0]
- end
- attribute \src "ls180.v:272.5-272.38"
- process $proc$ls180.v:272$2844
- assign { } { }
- assign $1\main_sdram_master_p0_cas_n[0:0] 1'1
- sync always
- sync init
- update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0]
- end
- attribute \src "ls180.v:2720.1-2725.4"
- process $proc$ls180.v:2720$13
+ attribute \src "ls180.v:2751.1-2756.4"
+ process $proc$ls180.v:2751$13
assign { } { }
assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000
assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint }
sync always
update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0]
end
- attribute \src "ls180.v:2727.1-2737.4"
- process $proc$ls180.v:2727$15
+ attribute \src "ls180.v:2758.1-2768.4"
+ process $proc$ls180.v:2758$15
assign { } { }
assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0
- attribute \src "ls180.v:2729.2-2736.9"
+ attribute \src "ls180.v:2760.2-2767.9"
switch \main_libresocsim_converter0_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
sync always
update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0]
end
- attribute \src "ls180.v:273.5-273.37"
- process $proc$ls180.v:273$2845
+ attribute \src "ls180.v:276.12-276.46"
+ process $proc$ls180.v:276$2850
assign { } { }
- assign $1\main_sdram_master_p0_cs_n[0:0] 1'1
+ assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000
sync always
sync init
- update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0]
+ update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0]
end
- attribute \src "ls180.v:2739.1-2785.4"
- process $proc$ls180.v:2739$16
+ attribute \src "ls180.v:277.5-277.44"
+ process $proc$ls180.v:277$2851
assign { } { }
+ assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0]
+ end
+ attribute \src "ls180.v:2770.1-2816.4"
+ process $proc$ls180.v:2770$16
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0
- assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
+ assign { } { }
+ assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
+ assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0
+ assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
assign $0\main_libresocsim_converter0_skip[0:0] 1'0
- assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
- assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
assign { } { }
- assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
- assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
+ assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0
+ assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
+ assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
assign $0\builder_converter0_next_state[0:0] \builder_converter0_state
- attribute \src "ls180.v:2751.2-2784.9"
+ attribute \src "ls180.v:2782.2-2815.9"
switch \builder_converter0_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter }
- attribute \src "ls180.v:2754.4-2761.11"
+ attribute \src "ls180.v:2785.4-2792.11"
switch \main_libresocsim_converter0_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4]
case
end
- attribute \src "ls180.v:2762.4-2775.7"
- switch $and$ls180.v:2762$17_Y
- attribute \src "ls180.v:2762.8-2762.81"
+ attribute \src "ls180.v:2793.4-2806.7"
+ switch $and$ls180.v:2793$17_Y
+ attribute \src "ls180.v:2793.8-2793.81"
case 1'1
- assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2763$18_Y
+ assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2794$18_Y
assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we
- assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2765$19_Y
- assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2766$20_Y
- attribute \src "ls180.v:2767.5-2774.8"
- switch $or$ls180.v:2767$21_Y
- attribute \src "ls180.v:2767.9-2767.97"
+ assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2796$19_Y
+ assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2797$20_Y
+ attribute \src "ls180.v:2798.5-2805.8"
+ switch $or$ls180.v:2798$21_Y
+ attribute \src "ls180.v:2798.9-2798.97"
case 1'1
- assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2768$22_Y
+ assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2799$22_Y
assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2770.6-2773.9"
- switch $eq$ls180.v:2770$23_Y
- attribute \src "ls180.v:2770.10-2770.55"
+ attribute \src "ls180.v:2801.6-2804.9"
+ switch $eq$ls180.v:2801$23_Y
+ attribute \src "ls180.v:2801.10-2801.55"
case 1'1
assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1
assign $0\builder_converter0_next_state[0:0] 1'0
case
assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2780.4-2782.7"
- switch $and$ls180.v:2780$24_Y
- attribute \src "ls180.v:2780.8-2780.81"
+ attribute \src "ls180.v:2811.4-2813.7"
+ switch $and$ls180.v:2811$24_Y
+ attribute \src "ls180.v:2811.8-2811.81"
case 1'1
assign $0\builder_converter0_next_state[0:0] 1'1
case
update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0]
update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
end
- attribute \src "ls180.v:274.5-274.38"
- process $proc$ls180.v:274$2846
- assign { } { }
- assign $1\main_sdram_master_p0_ras_n[0:0] 1'1
- sync always
- sync init
- update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0]
- end
- attribute \src "ls180.v:275.5-275.37"
- process $proc$ls180.v:275$2847
+ attribute \src "ls180.v:278.12-278.48"
+ process $proc$ls180.v:278$2852
assign { } { }
- assign $1\main_sdram_master_p0_we_n[0:0] 1'1
+ assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000
sync always
sync init
- update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0]
+ update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0]
end
- attribute \src "ls180.v:276.5-276.36"
- process $proc$ls180.v:276$2848
+ attribute \src "ls180.v:279.11-279.43"
+ process $proc$ls180.v:279$2853
assign { } { }
- assign $1\main_sdram_master_p0_cke[0:0] 1'0
+ assign $1\main_sdram_master_p0_bank[1:0] 2'00
sync always
sync init
- update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0]
+ update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0]
end
- attribute \src "ls180.v:277.5-277.36"
- process $proc$ls180.v:277$2849
+ attribute \src "ls180.v:280.5-280.38"
+ process $proc$ls180.v:280$2854
assign { } { }
- assign $1\main_sdram_master_p0_odt[0:0] 1'0
+ assign $1\main_sdram_master_p0_cas_n[0:0] 1'1
sync always
sync init
- update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0]
+ update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0]
end
- attribute \src "ls180.v:278.5-278.40"
- process $proc$ls180.v:278$2850
+ attribute \src "ls180.v:281.5-281.37"
+ process $proc$ls180.v:281$2855
assign { } { }
- assign $1\main_sdram_master_p0_reset_n[0:0] 1'0
+ assign $1\main_sdram_master_p0_cs_n[0:0] 1'1
sync always
sync init
- update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0]
+ update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0]
end
- attribute \src "ls180.v:2787.1-2797.4"
- process $proc$ls180.v:2787$26
+ attribute \src "ls180.v:2818.1-2828.4"
+ process $proc$ls180.v:2818$26
assign { } { }
assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0
- attribute \src "ls180.v:2789.2-2796.9"
+ attribute \src "ls180.v:2820.2-2827.9"
switch \main_libresocsim_converter1_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
sync always
update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0]
end
- attribute \src "ls180.v:279.5-279.38"
- process $proc$ls180.v:279$2851
+ attribute \src "ls180.v:282.5-282.38"
+ process $proc$ls180.v:282$2856
assign { } { }
- assign $1\main_sdram_master_p0_act_n[0:0] 1'1
+ assign $1\main_sdram_master_p0_ras_n[0:0] 1'1
sync always
sync init
- update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0]
+ update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0]
end
- attribute \src "ls180.v:2799.1-2845.4"
- process $proc$ls180.v:2799$27
+ attribute \src "ls180.v:283.5-283.37"
+ process $proc$ls180.v:283$2857
+ assign { } { }
+ assign $1\main_sdram_master_p0_we_n[0:0] 1'1
+ sync always
+ sync init
+ update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0]
+ end
+ attribute \src "ls180.v:2830.1-2876.4"
+ process $proc$ls180.v:2830$27
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\main_libresocsim_converter1_skip[0:0] 1'0
- assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
- assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
+ assign { } { }
+ assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0
+ assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0
+ assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000
assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0
assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
- assign { } { }
- assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
- assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0
+ assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
assign $0\builder_converter1_next_state[0:0] \builder_converter1_state
- attribute \src "ls180.v:2811.2-2844.9"
+ attribute \src "ls180.v:2842.2-2875.9"
switch \builder_converter1_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter }
- attribute \src "ls180.v:2814.4-2821.11"
+ attribute \src "ls180.v:2845.4-2852.11"
switch \main_libresocsim_converter1_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4]
case
end
- attribute \src "ls180.v:2822.4-2835.7"
- switch $and$ls180.v:2822$28_Y
- attribute \src "ls180.v:2822.8-2822.81"
+ attribute \src "ls180.v:2853.4-2866.7"
+ switch $and$ls180.v:2853$28_Y
+ attribute \src "ls180.v:2853.8-2853.81"
case 1'1
- assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2823$29_Y
+ assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2854$29_Y
assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we
- assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2825$30_Y
- assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2826$31_Y
- attribute \src "ls180.v:2827.5-2834.8"
- switch $or$ls180.v:2827$32_Y
- attribute \src "ls180.v:2827.9-2827.97"
+ assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2856$30_Y
+ assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2857$31_Y
+ attribute \src "ls180.v:2858.5-2865.8"
+ switch $or$ls180.v:2858$32_Y
+ attribute \src "ls180.v:2858.9-2858.97"
case 1'1
- assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2828$33_Y
+ assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2859$33_Y
assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2830.6-2833.9"
- switch $eq$ls180.v:2830$34_Y
- attribute \src "ls180.v:2830.10-2830.55"
+ attribute \src "ls180.v:2861.6-2864.9"
+ switch $eq$ls180.v:2861$34_Y
+ attribute \src "ls180.v:2861.10-2861.55"
case 1'1
assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1
assign $0\builder_converter1_next_state[0:0] 1'0
case
assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2840.4-2842.7"
- switch $and$ls180.v:2840$35_Y
- attribute \src "ls180.v:2840.8-2840.81"
+ attribute \src "ls180.v:2871.4-2873.7"
+ switch $and$ls180.v:2871$35_Y
+ attribute \src "ls180.v:2871.8-2871.81"
case 1'1
assign $0\builder_converter1_next_state[0:0] 1'1
case
update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0]
update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
end
- attribute \src "ls180.v:280.12-280.47"
- process $proc$ls180.v:280$2852
+ attribute \src "ls180.v:284.5-284.36"
+ process $proc$ls180.v:284$2858
assign { } { }
- assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
+ assign $1\main_sdram_master_p0_cke[0:0] 1'0
sync always
sync init
- update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0]
+ update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0]
end
- attribute \src "ls180.v:281.5-281.42"
- process $proc$ls180.v:281$2853
+ attribute \src "ls180.v:285.5-285.36"
+ process $proc$ls180.v:285$2859
assign { } { }
- assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0
+ assign $1\main_sdram_master_p0_odt[0:0] 1'0
sync always
sync init
- update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0]
+ update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0]
end
- attribute \src "ls180.v:282.11-282.50"
- process $proc$ls180.v:282$2854
+ attribute \src "ls180.v:286.5-286.40"
+ process $proc$ls180.v:286$2860
assign { } { }
- assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00
+ assign $1\main_sdram_master_p0_reset_n[0:0] 1'0
sync always
sync init
- update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0]
+ update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0]
end
- attribute \src "ls180.v:283.5-283.42"
- process $proc$ls180.v:283$2855
+ attribute \src "ls180.v:287.5-287.38"
+ process $proc$ls180.v:287$2861
assign { } { }
- assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0
+ assign $1\main_sdram_master_p0_act_n[0:0] 1'1
sync always
sync init
- update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0]
+ update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0]
end
- attribute \src "ls180.v:2847.1-2857.4"
- process $proc$ls180.v:2847$37
+ attribute \src "ls180.v:2878.1-2888.4"
+ process $proc$ls180.v:2878$37
assign { } { }
assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0
- attribute \src "ls180.v:2849.2-2856.9"
+ attribute \src "ls180.v:2880.2-2887.9"
switch \main_libresocsim_converter2_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
sync always
update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0]
end
- attribute \src "ls180.v:2859.1-2905.4"
- process $proc$ls180.v:2859$38
+ attribute \src "ls180.v:288.12-288.47"
+ process $proc$ls180.v:288$2862
+ assign { } { }
+ assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0]
+ end
+ attribute \src "ls180.v:289.5-289.42"
+ process $proc$ls180.v:289$2863
+ assign { } { }
+ assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0]
+ end
+ attribute \src "ls180.v:2890.1-2936.4"
+ process $proc$ls180.v:2890$38
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
+ assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
+ assign { } { }
+ assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
+ assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0
assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000
assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0
assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0
assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0
- assign { } { }
- assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
- assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0
assign $0\main_libresocsim_converter2_skip[0:0] 1'0
assign $0\builder_converter2_next_state[0:0] \builder_converter2_state
- attribute \src "ls180.v:2871.2-2904.9"
+ attribute \src "ls180.v:2902.2-2935.9"
switch \builder_converter2_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter }
- attribute \src "ls180.v:2874.4-2881.11"
+ attribute \src "ls180.v:2905.4-2912.11"
switch \main_libresocsim_converter2_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4]
case
end
- attribute \src "ls180.v:2882.4-2895.7"
- switch $and$ls180.v:2882$39_Y
- attribute \src "ls180.v:2882.8-2882.87"
+ attribute \src "ls180.v:2913.4-2926.7"
+ switch $and$ls180.v:2913$39_Y
+ attribute \src "ls180.v:2913.8-2913.87"
case 1'1
- assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2883$40_Y
+ assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2914$40_Y
assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we
- assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2885$41_Y
- assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2886$42_Y
- attribute \src "ls180.v:2887.5-2894.8"
- switch $or$ls180.v:2887$43_Y
- attribute \src "ls180.v:2887.9-2887.97"
+ assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2916$41_Y
+ assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2917$42_Y
+ attribute \src "ls180.v:2918.5-2925.8"
+ switch $or$ls180.v:2918$43_Y
+ attribute \src "ls180.v:2918.9-2918.97"
case 1'1
- assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2888$44_Y
+ assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2919$44_Y
assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2890.6-2893.9"
- switch $eq$ls180.v:2890$45_Y
- attribute \src "ls180.v:2890.10-2890.55"
+ attribute \src "ls180.v:2921.6-2924.9"
+ switch $eq$ls180.v:2921$45_Y
+ attribute \src "ls180.v:2921.10-2921.55"
case 1'1
assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1
assign $0\builder_converter2_next_state[0:0] 1'0
case
assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2900.4-2902.7"
- switch $and$ls180.v:2900$46_Y
- attribute \src "ls180.v:2900.8-2900.87"
+ attribute \src "ls180.v:2931.4-2933.7"
+ switch $and$ls180.v:2931$46_Y
+ attribute \src "ls180.v:2931.8-2931.87"
case 1'1
assign $0\builder_converter2_next_state[0:0] 1'1
case
update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0]
update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
end
- attribute \src "ls180.v:290.11-290.36"
- process $proc$ls180.v:290$2856
+ attribute \src "ls180.v:290.11-290.50"
+ process $proc$ls180.v:290$2864
assign { } { }
- assign $1\main_sdram_storage[3:0] 4'0001
+ assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00
sync always
sync init
- update \main_sdram_storage $1\main_sdram_storage[3:0]
- end
- attribute \src "ls180.v:2908.1-2914.4"
- process $proc$ls180.v:2908$47
- assign { } { }
- assign { } { }
- assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2910$50_Y
- assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2911$53_Y
- assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2912$56_Y
- assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2913$59_Y
- sync always
- update \main_libresocsim_we $0\main_libresocsim_we[3:0]
+ update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0]
end
- attribute \src "ls180.v:291.5-291.25"
- process $proc$ls180.v:291$2857
+ attribute \src "ls180.v:291.5-291.42"
+ process $proc$ls180.v:291$2865
assign { } { }
- assign $1\main_sdram_re[0:0] 1'0
+ assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0
sync always
sync init
- update \main_sdram_re $1\main_sdram_re[0:0]
+ update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0]
end
- attribute \src "ls180.v:292.11-292.44"
- process $proc$ls180.v:292$2858
+ attribute \src "ls180.v:2939.1-2945.4"
+ process $proc$ls180.v:2939$47
assign { } { }
- assign $1\main_sdram_command_storage[5:0] 6'000000
+ assign { } { }
+ assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2941$50_Y
+ assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2942$53_Y
+ assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2943$56_Y
+ assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2944$59_Y
sync always
- sync init
- update \main_sdram_command_storage $1\main_sdram_command_storage[5:0]
+ update \main_libresocsim_we $0\main_libresocsim_we[3:0]
end
- attribute \src "ls180.v:2920.1-2925.4"
- process $proc$ls180.v:2920$61
+ attribute \src "ls180.v:2951.1-2956.4"
+ process $proc$ls180.v:2951$61
assign { } { }
assign $0\main_libresocsim_zero_clear[0:0] 1'0
- attribute \src "ls180.v:2922.2-2924.5"
- switch $and$ls180.v:2922$62_Y
- attribute \src "ls180.v:2922.6-2922.90"
+ attribute \src "ls180.v:2953.2-2955.5"
+ switch $and$ls180.v:2953$62_Y
+ attribute \src "ls180.v:2953.6-2953.90"
case 1'1
assign $0\main_libresocsim_zero_clear[0:0] 1'1
case
sync always
update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0]
end
- attribute \src "ls180.v:293.5-293.33"
- process $proc$ls180.v:293$2859
+ attribute \src "ls180.v:298.11-298.36"
+ process $proc$ls180.v:298$2866
assign { } { }
- assign $1\main_sdram_command_re[0:0] 1'0
+ assign $1\main_sdram_storage[3:0] 4'0001
sync always
sync init
- update \main_sdram_command_re $1\main_sdram_command_re[0:0]
+ update \main_sdram_storage $1\main_sdram_storage[3:0]
end
- attribute \src "ls180.v:2964.1-3018.4"
- process $proc$ls180.v:2964$64
+ attribute \src "ls180.v:299.5-299.25"
+ process $proc$ls180.v:299$2867
assign { } { }
+ assign $1\main_sdram_re[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_re $1\main_sdram_re[0:0]
+ end
+ attribute \src "ls180.v:2995.1-3049.4"
+ process $proc$ls180.v:2995$64
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign { } { }
+ assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0
+ assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000
assign $0\main_sdram_master_p0_bank[1:0] 2'00
assign $0\main_sdram_master_p0_cas_n[0:0] 1'1
assign $0\main_sdram_master_p0_cs_n[0:0] 1'1
assign $0\main_sdram_master_p0_cke[0:0] 1'0
assign $0\main_sdram_master_p0_odt[0:0] 1'0
assign $0\main_sdram_master_p0_reset_n[0:0] 1'0
- assign $0\main_sdram_master_p0_act_n[0:0] 1'1
assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
- assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
+ assign $0\main_sdram_master_p0_act_n[0:0] 1'1
assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0
+ assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0
assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00
assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0
assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000
- assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0
- assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000
- attribute \src "ls180.v:2983.2-3017.5"
+ attribute \src "ls180.v:3014.2-3048.5"
switch \main_sdram_sel
- attribute \src "ls180.v:2983.6-2983.20"
+ attribute \src "ls180.v:3014.6-3014.20"
case 1'1
assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address
assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank
assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en
assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata
assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid
- attribute \src "ls180.v:3000.6-3000.10"
+ attribute \src "ls180.v:3031.6-3031.10"
case
assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address
assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank
update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0]
update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0]
end
- attribute \src "ls180.v:297.5-297.38"
- process $proc$ls180.v:297$2860
- assign { } { }
- assign $0\main_sdram_command_issue_w[0:0] 1'0
- sync always
- update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0]
- sync init
- end
- attribute \src "ls180.v:298.12-298.46"
- process $proc$ls180.v:298$2861
+ attribute \src "ls180.v:300.11-300.44"
+ process $proc$ls180.v:300$2868
assign { } { }
- assign $1\main_sdram_address_storage[12:0] 13'0000000000000
- sync always
- sync init
- update \main_sdram_address_storage $1\main_sdram_address_storage[12:0]
- end
- attribute \src "ls180.v:299.5-299.33"
- process $proc$ls180.v:299$2862
- assign { } { }
- assign $1\main_sdram_address_re[0:0] 1'0
- sync always
- sync init
- update \main_sdram_address_re $1\main_sdram_address_re[0:0]
- end
- attribute \src "ls180.v:300.11-300.45"
- process $proc$ls180.v:300$2863
- assign { } { }
- assign $1\main_sdram_baddress_storage[1:0] 2'00
+ assign $1\main_sdram_command_storage[5:0] 6'000000
sync always
sync init
- update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0]
+ update \main_sdram_command_storage $1\main_sdram_command_storage[5:0]
end
- attribute \src "ls180.v:301.5-301.34"
- process $proc$ls180.v:301$2864
+ attribute \src "ls180.v:301.5-301.33"
+ process $proc$ls180.v:301$2869
assign { } { }
- assign $1\main_sdram_baddress_re[0:0] 1'0
+ assign $1\main_sdram_command_re[0:0] 1'0
sync always
sync init
- update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0]
+ update \main_sdram_command_re $1\main_sdram_command_re[0:0]
end
- attribute \src "ls180.v:302.12-302.45"
- process $proc$ls180.v:302$2865
+ attribute \src "ls180.v:305.5-305.38"
+ process $proc$ls180.v:305$2870
assign { } { }
- assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000
+ assign $0\main_sdram_command_issue_w[0:0] 1'0
sync always
+ update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0]
sync init
- update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0]
end
- attribute \src "ls180.v:3022.1-3038.4"
- process $proc$ls180.v:3022$65
+ attribute \src "ls180.v:3053.1-3069.4"
+ process $proc$ls180.v:3053$65
assign { } { }
assign { } { }
assign { } { }
assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1
assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1
assign $0\main_sdram_inti_p0_we_n[0:0] 1'1
- attribute \src "ls180.v:3027.2-3037.5"
+ attribute \src "ls180.v:3058.2-3068.5"
switch \main_sdram_command_issue_re
- attribute \src "ls180.v:3027.6-3027.33"
+ attribute \src "ls180.v:3058.6-3058.33"
case 1'1
- assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3028$66_Y
- assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3029$67_Y
- assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3030$68_Y
- assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3031$69_Y
- attribute \src "ls180.v:3032.6-3032.10"
+ assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3059$66_Y
+ assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3060$67_Y
+ assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3061$68_Y
+ assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3062$69_Y
+ attribute \src "ls180.v:3063.6-3063.10"
case
assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1
assign $0\main_sdram_inti_p0_we_n[0:0] 1'1
update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0]
update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0]
end
- attribute \src "ls180.v:303.5-303.32"
- process $proc$ls180.v:303$2866
+ attribute \src "ls180.v:306.12-306.46"
+ process $proc$ls180.v:306$2871
assign { } { }
- assign $1\main_sdram_wrdata_re[0:0] 1'0
+ assign $1\main_sdram_address_storage[12:0] 13'0000000000000
sync always
sync init
- update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0]
+ update \main_sdram_address_storage $1\main_sdram_address_storage[12:0]
end
- attribute \src "ls180.v:304.12-304.37"
- process $proc$ls180.v:304$2867
+ attribute \src "ls180.v:307.5-307.33"
+ process $proc$ls180.v:307$2872
assign { } { }
- assign $1\main_sdram_status[15:0] 16'0000000000000000
+ assign $1\main_sdram_address_re[0:0] 1'0
sync always
sync init
- update \main_sdram_status $1\main_sdram_status[15:0]
+ update \main_sdram_address_re $1\main_sdram_address_re[0:0]
+ end
+ attribute \src "ls180.v:308.11-308.45"
+ process $proc$ls180.v:308$2873
+ assign { } { }
+ assign $1\main_sdram_baddress_storage[1:0] 2'00
+ sync always
+ sync init
+ update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0]
+ end
+ attribute \src "ls180.v:309.5-309.34"
+ process $proc$ls180.v:309$2874
+ assign { } { }
+ assign $1\main_sdram_baddress_re[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0]
end
- attribute \src "ls180.v:3081.1-3111.4"
- process $proc$ls180.v:3081$78
+ attribute \src "ls180.v:310.12-310.45"
+ process $proc$ls180.v:310$2875
assign { } { }
+ assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0]
+ end
+ attribute \src "ls180.v:311.5-311.32"
+ process $proc$ls180.v:311$2876
+ assign { } { }
+ assign $1\main_sdram_wrdata_re[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0]
+ end
+ attribute \src "ls180.v:3112.1-3142.4"
+ process $proc$ls180.v:3112$78
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\main_sdram_cmd_last[0:0] 1'0
assign $0\main_sdram_sequencer_start0[0:0] 1'0
assign $0\main_sdram_cmd_valid[0:0] 1'0
+ assign { } { }
+ assign $0\main_sdram_cmd_last[0:0] 1'0
assign $0\builder_refresher_next_state[1:0] \builder_refresher_state
- attribute \src "ls180.v:3087.2-3110.9"
+ attribute \src "ls180.v:3118.2-3141.9"
switch \builder_refresher_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
assign $0\main_sdram_cmd_valid[0:0] 1'1
- attribute \src "ls180.v:3090.4-3093.7"
+ attribute \src "ls180.v:3121.4-3124.7"
switch \main_sdram_cmd_ready
- attribute \src "ls180.v:3090.8-3090.28"
+ attribute \src "ls180.v:3121.8-3121.28"
case 1'1
assign $0\main_sdram_sequencer_start0[0:0] 1'1
assign $0\builder_refresher_next_state[1:0] 2'10
attribute \src "ls180.v:0.0-0.0"
case 2'10
assign $0\main_sdram_cmd_valid[0:0] 1'1
- attribute \src "ls180.v:3097.4-3101.7"
+ attribute \src "ls180.v:3128.4-3132.7"
switch \main_sdram_sequencer_done0
- attribute \src "ls180.v:3097.8-3097.34"
+ attribute \src "ls180.v:3128.8-3128.34"
case 1'1
assign $0\main_sdram_cmd_valid[0:0] 1'0
assign $0\main_sdram_cmd_last[0:0] 1'1
end
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:3104.4-3108.7"
+ attribute \src "ls180.v:3135.4-3139.7"
switch 1'1
- attribute \src "ls180.v:3104.8-3104.12"
+ attribute \src "ls180.v:3135.8-3135.12"
case 1'1
- attribute \src "ls180.v:3105.5-3107.8"
+ attribute \src "ls180.v:3136.5-3138.8"
switch \main_sdram_wants_refresh
- attribute \src "ls180.v:3105.9-3105.33"
+ attribute \src "ls180.v:3136.9-3136.33"
case 1'1
assign $0\builder_refresher_next_state[1:0] 2'01
case
update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0]
update \builder_refresher_next_state $0\builder_refresher_next_state[1:0]
end
- attribute \src "ls180.v:3126.1-3133.4"
- process $proc$ls180.v:3126$82
+ attribute \src "ls180.v:312.12-312.37"
+ process $proc$ls180.v:312$2877
+ assign { } { }
+ assign $1\main_sdram_status[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \main_sdram_status $1\main_sdram_status[15:0]
+ end
+ attribute \src "ls180.v:3157.1-3164.4"
+ process $proc$ls180.v:3157$82
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
- attribute \src "ls180.v:3128.2-3132.5"
+ attribute \src "ls180.v:3159.2-3163.5"
switch \main_sdram_bankmachine0_row_col_n_addr_sel
- attribute \src "ls180.v:3128.6-3128.48"
+ attribute \src "ls180.v:3159.6-3159.48"
case 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
- attribute \src "ls180.v:3130.6-3130.10"
+ attribute \src "ls180.v:3161.6-3161.10"
case
- assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3131$84_Y
+ assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3162$84_Y
end
sync always
update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:3137.1-3144.4"
- process $proc$ls180.v:3137$91
+ attribute \src "ls180.v:3168.1-3175.4"
+ process $proc$ls180.v:3168$91
assign { } { }
assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0
- attribute \src "ls180.v:3139.2-3143.5"
- switch $and$ls180.v:3139$92_Y
- attribute \src "ls180.v:3139.6-3139.115"
+ attribute \src "ls180.v:3170.2-3174.5"
+ switch $and$ls180.v:3170$92_Y
+ attribute \src "ls180.v:3170.6-3170.115"
case 1'1
- attribute \src "ls180.v:3140.3-3142.6"
- switch $ne$ls180.v:3140$93_Y
- attribute \src "ls180.v:3140.7-3140.143"
+ attribute \src "ls180.v:3171.3-3173.6"
+ switch $ne$ls180.v:3171$93_Y
+ attribute \src "ls180.v:3171.7-3171.143"
case 1'1
- assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3141$94_Y
+ assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3172$94_Y
case
end
case
sync always
update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0]
end
- attribute \src "ls180.v:3159.1-3166.4"
- process $proc$ls180.v:3159$95
+ attribute \src "ls180.v:3190.1-3197.4"
+ process $proc$ls180.v:3190$95
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- attribute \src "ls180.v:3161.2-3165.5"
+ attribute \src "ls180.v:3192.2-3196.5"
switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:3161.6-3161.58"
+ attribute \src "ls180.v:3192.6-3192.58"
case 1'1
- assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3162$96_Y
- attribute \src "ls180.v:3163.6-3163.10"
+ assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3193$96_Y
+ attribute \src "ls180.v:3194.6-3194.10"
case
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
end
sync always
update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:3175.1-3268.4"
- process $proc$ls180.v:3175$104
- assign { } { }
+ attribute \src "ls180.v:3206.1-3299.4"
+ process $proc$ls180.v:3206$104
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
+ assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0
assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0
assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
+ assign { } { }
assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
- assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
- assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state
- attribute \src "ls180.v:3191.2-3267.9"
+ attribute \src "ls180.v:3222.2-3298.9"
switch \builder_bankmachine0_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1
- attribute \src "ls180.v:3193.4-3201.7"
- switch $and$ls180.v:3193$105_Y
- attribute \src "ls180.v:3193.8-3193.87"
+ attribute \src "ls180.v:3224.4-3232.7"
+ switch $and$ls180.v:3224$105_Y
+ attribute \src "ls180.v:3224.8-3224.87"
case 1'1
assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3195.5-3197.8"
+ attribute \src "ls180.v:3226.5-3228.8"
switch \main_sdram_bankmachine0_cmd_ready
- attribute \src "ls180.v:3195.9-3195.42"
+ attribute \src "ls180.v:3226.9-3226.42"
case 1'1
assign $0\builder_bankmachine0_next_state[2:0] 3'101
case
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1
- attribute \src "ls180.v:3205.4-3207.7"
- switch $and$ls180.v:3205$106_Y
- attribute \src "ls180.v:3205.8-3205.87"
+ attribute \src "ls180.v:3236.4-3238.7"
+ switch $and$ls180.v:3236$106_Y
+ attribute \src "ls180.v:3236.8-3236.87"
case 1'1
assign $0\builder_bankmachine0_next_state[2:0] 3'101
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:3211.4-3220.7"
+ attribute \src "ls180.v:3242.4-3251.7"
switch \main_sdram_bankmachine0_trccon_ready
- attribute \src "ls180.v:3211.8-3211.44"
+ attribute \src "ls180.v:3242.8-3242.44"
case 1'1
assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1
assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1
- attribute \src "ls180.v:3216.5-3218.8"
+ attribute \src "ls180.v:3247.5-3249.8"
switch \main_sdram_bankmachine0_cmd_ready
- attribute \src "ls180.v:3216.9-3216.42"
+ attribute \src "ls180.v:3247.9-3247.42"
case 1'1
assign $0\builder_bankmachine0_next_state[2:0] 3'110
case
case 3'100
assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3223.4-3225.7"
+ attribute \src "ls180.v:3254.4-3256.7"
switch \main_sdram_bankmachine0_twtpcon_ready
- attribute \src "ls180.v:3223.8-3223.45"
+ attribute \src "ls180.v:3254.8-3254.45"
case 1'1
assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1
case
end
- attribute \src "ls180.v:3228.4-3230.7"
- switch $not$ls180.v:3228$107_Y
- attribute \src "ls180.v:3228.8-3228.46"
+ attribute \src "ls180.v:3259.4-3261.7"
+ switch $not$ls180.v:3259$107_Y
+ attribute \src "ls180.v:3259.8-3259.46"
case 1'1
assign $0\builder_bankmachine0_next_state[2:0] 3'000
case
assign $0\builder_bankmachine0_next_state[2:0] 3'000
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:3239.4-3265.7"
+ attribute \src "ls180.v:3270.4-3296.7"
switch \main_sdram_bankmachine0_refresh_req
- attribute \src "ls180.v:3239.8-3239.43"
+ attribute \src "ls180.v:3270.8-3270.43"
case 1'1
assign $0\builder_bankmachine0_next_state[2:0] 3'100
- attribute \src "ls180.v:3241.8-3241.12"
+ attribute \src "ls180.v:3272.8-3272.12"
case
- attribute \src "ls180.v:3242.5-3264.8"
+ attribute \src "ls180.v:3273.5-3295.8"
switch \main_sdram_bankmachine0_cmd_buffer_source_valid
- attribute \src "ls180.v:3242.9-3242.56"
+ attribute \src "ls180.v:3273.9-3273.56"
case 1'1
- attribute \src "ls180.v:3243.6-3263.9"
+ attribute \src "ls180.v:3274.6-3294.9"
switch \main_sdram_bankmachine0_row_opened
- attribute \src "ls180.v:3243.10-3243.44"
+ attribute \src "ls180.v:3274.10-3274.44"
case 1'1
- attribute \src "ls180.v:3244.7-3260.10"
+ attribute \src "ls180.v:3275.7-3291.10"
switch \main_sdram_bankmachine0_row_hit
- attribute \src "ls180.v:3244.11-3244.42"
+ attribute \src "ls180.v:3275.11-3275.42"
case 1'1
assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1
- attribute \src "ls180.v:3246.8-3253.11"
+ attribute \src "ls180.v:3277.8-3284.11"
switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we
- attribute \src "ls180.v:3246.12-3246.64"
+ attribute \src "ls180.v:3277.12-3277.64"
case 1'1
assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready
assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1
assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1
- attribute \src "ls180.v:3250.12-3250.16"
+ attribute \src "ls180.v:3281.12-3281.16"
case
assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready
assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1
end
- attribute \src "ls180.v:3255.8-3257.11"
- switch $and$ls180.v:3255$108_Y
- attribute \src "ls180.v:3255.12-3255.88"
+ attribute \src "ls180.v:3286.8-3288.11"
+ switch $and$ls180.v:3286$108_Y
+ attribute \src "ls180.v:3286.12-3286.88"
case 1'1
assign $0\builder_bankmachine0_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:3258.11-3258.15"
+ attribute \src "ls180.v:3289.11-3289.15"
case
assign $0\builder_bankmachine0_next_state[2:0] 3'001
end
- attribute \src "ls180.v:3261.10-3261.14"
+ attribute \src "ls180.v:3292.10-3292.14"
case
assign $0\builder_bankmachine0_next_state[2:0] 3'011
end
update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0]
end
- attribute \src "ls180.v:3283.1-3290.4"
- process $proc$ls180.v:3283$112
+ attribute \src "ls180.v:3314.1-3321.4"
+ process $proc$ls180.v:3314$112
assign { } { }
assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
- attribute \src "ls180.v:3285.2-3289.5"
+ attribute \src "ls180.v:3316.2-3320.5"
switch \main_sdram_bankmachine1_row_col_n_addr_sel
- attribute \src "ls180.v:3285.6-3285.48"
+ attribute \src "ls180.v:3316.6-3316.48"
case 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
- attribute \src "ls180.v:3287.6-3287.10"
+ attribute \src "ls180.v:3318.6-3318.10"
case
- assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3288$114_Y
+ assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3319$114_Y
end
sync always
update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:3294.1-3301.4"
- process $proc$ls180.v:3294$121
+ attribute \src "ls180.v:3325.1-3332.4"
+ process $proc$ls180.v:3325$121
assign { } { }
assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0
- attribute \src "ls180.v:3296.2-3300.5"
- switch $and$ls180.v:3296$122_Y
- attribute \src "ls180.v:3296.6-3296.115"
+ attribute \src "ls180.v:3327.2-3331.5"
+ switch $and$ls180.v:3327$122_Y
+ attribute \src "ls180.v:3327.6-3327.115"
case 1'1
- attribute \src "ls180.v:3297.3-3299.6"
- switch $ne$ls180.v:3297$123_Y
- attribute \src "ls180.v:3297.7-3297.143"
+ attribute \src "ls180.v:3328.3-3330.6"
+ switch $ne$ls180.v:3328$123_Y
+ attribute \src "ls180.v:3328.7-3328.143"
case 1'1
- assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3298$124_Y
+ assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3329$124_Y
case
end
case
sync always
update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0]
end
- attribute \src "ls180.v:3316.1-3323.4"
- process $proc$ls180.v:3316$125
+ attribute \src "ls180.v:3347.1-3354.4"
+ process $proc$ls180.v:3347$125
assign { } { }
assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- attribute \src "ls180.v:3318.2-3322.5"
+ attribute \src "ls180.v:3349.2-3353.5"
switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:3318.6-3318.58"
+ attribute \src "ls180.v:3349.6-3349.58"
case 1'1
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3319$126_Y
- attribute \src "ls180.v:3320.6-3320.10"
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3350$126_Y
+ attribute \src "ls180.v:3351.6-3351.10"
case
assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
end
sync always
update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:3332.1-3425.4"
- process $proc$ls180.v:3332$134
+ attribute \src "ls180.v:3363.1-3456.4"
+ process $proc$ls180.v:3363$134
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
+ assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
+ assign { } { }
assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0
assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0
assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
- assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
- assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
- assign { } { }
assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state
- attribute \src "ls180.v:3348.2-3424.9"
+ attribute \src "ls180.v:3379.2-3455.9"
switch \builder_bankmachine1_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1
- attribute \src "ls180.v:3350.4-3358.7"
- switch $and$ls180.v:3350$135_Y
- attribute \src "ls180.v:3350.8-3350.87"
+ attribute \src "ls180.v:3381.4-3389.7"
+ switch $and$ls180.v:3381$135_Y
+ attribute \src "ls180.v:3381.8-3381.87"
case 1'1
assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3352.5-3354.8"
+ attribute \src "ls180.v:3383.5-3385.8"
switch \main_sdram_bankmachine1_cmd_ready
- attribute \src "ls180.v:3352.9-3352.42"
+ attribute \src "ls180.v:3383.9-3383.42"
case 1'1
assign $0\builder_bankmachine1_next_state[2:0] 3'101
case
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1
- attribute \src "ls180.v:3362.4-3364.7"
- switch $and$ls180.v:3362$136_Y
- attribute \src "ls180.v:3362.8-3362.87"
+ attribute \src "ls180.v:3393.4-3395.7"
+ switch $and$ls180.v:3393$136_Y
+ attribute \src "ls180.v:3393.8-3393.87"
case 1'1
assign $0\builder_bankmachine1_next_state[2:0] 3'101
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:3368.4-3377.7"
+ attribute \src "ls180.v:3399.4-3408.7"
switch \main_sdram_bankmachine1_trccon_ready
- attribute \src "ls180.v:3368.8-3368.44"
+ attribute \src "ls180.v:3399.8-3399.44"
case 1'1
assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1
assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1
- attribute \src "ls180.v:3373.5-3375.8"
+ attribute \src "ls180.v:3404.5-3406.8"
switch \main_sdram_bankmachine1_cmd_ready
- attribute \src "ls180.v:3373.9-3373.42"
+ attribute \src "ls180.v:3404.9-3404.42"
case 1'1
assign $0\builder_bankmachine1_next_state[2:0] 3'110
case
case 3'100
assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3380.4-3382.7"
+ attribute \src "ls180.v:3411.4-3413.7"
switch \main_sdram_bankmachine1_twtpcon_ready
- attribute \src "ls180.v:3380.8-3380.45"
+ attribute \src "ls180.v:3411.8-3411.45"
case 1'1
assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1
case
end
- attribute \src "ls180.v:3385.4-3387.7"
- switch $not$ls180.v:3385$137_Y
- attribute \src "ls180.v:3385.8-3385.46"
+ attribute \src "ls180.v:3416.4-3418.7"
+ switch $not$ls180.v:3416$137_Y
+ attribute \src "ls180.v:3416.8-3416.46"
case 1'1
assign $0\builder_bankmachine1_next_state[2:0] 3'000
case
assign $0\builder_bankmachine1_next_state[2:0] 3'000
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:3396.4-3422.7"
+ attribute \src "ls180.v:3427.4-3453.7"
switch \main_sdram_bankmachine1_refresh_req
- attribute \src "ls180.v:3396.8-3396.43"
+ attribute \src "ls180.v:3427.8-3427.43"
case 1'1
assign $0\builder_bankmachine1_next_state[2:0] 3'100
- attribute \src "ls180.v:3398.8-3398.12"
+ attribute \src "ls180.v:3429.8-3429.12"
case
- attribute \src "ls180.v:3399.5-3421.8"
+ attribute \src "ls180.v:3430.5-3452.8"
switch \main_sdram_bankmachine1_cmd_buffer_source_valid
- attribute \src "ls180.v:3399.9-3399.56"
+ attribute \src "ls180.v:3430.9-3430.56"
case 1'1
- attribute \src "ls180.v:3400.6-3420.9"
+ attribute \src "ls180.v:3431.6-3451.9"
switch \main_sdram_bankmachine1_row_opened
- attribute \src "ls180.v:3400.10-3400.44"
+ attribute \src "ls180.v:3431.10-3431.44"
case 1'1
- attribute \src "ls180.v:3401.7-3417.10"
+ attribute \src "ls180.v:3432.7-3448.10"
switch \main_sdram_bankmachine1_row_hit
- attribute \src "ls180.v:3401.11-3401.42"
+ attribute \src "ls180.v:3432.11-3432.42"
case 1'1
assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1
- attribute \src "ls180.v:3403.8-3410.11"
+ attribute \src "ls180.v:3434.8-3441.11"
switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we
- attribute \src "ls180.v:3403.12-3403.64"
+ attribute \src "ls180.v:3434.12-3434.64"
case 1'1
assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready
assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1
assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1
- attribute \src "ls180.v:3407.12-3407.16"
+ attribute \src "ls180.v:3438.12-3438.16"
case
assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready
assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1
end
- attribute \src "ls180.v:3412.8-3414.11"
- switch $and$ls180.v:3412$138_Y
- attribute \src "ls180.v:3412.12-3412.88"
+ attribute \src "ls180.v:3443.8-3445.11"
+ switch $and$ls180.v:3443$138_Y
+ attribute \src "ls180.v:3443.12-3443.88"
case 1'1
assign $0\builder_bankmachine1_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:3415.11-3415.15"
+ attribute \src "ls180.v:3446.11-3446.15"
case
assign $0\builder_bankmachine1_next_state[2:0] 3'001
end
- attribute \src "ls180.v:3418.10-3418.14"
+ attribute \src "ls180.v:3449.10-3449.14"
case
assign $0\builder_bankmachine1_next_state[2:0] 3'011
end
update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0]
end
- attribute \src "ls180.v:334.12-334.46"
- process $proc$ls180.v:334$2868
+ attribute \src "ls180.v:342.12-342.46"
+ process $proc$ls180.v:342$2878
assign { } { }
assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000
sync always
sync init
update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0]
end
- attribute \src "ls180.v:335.11-335.47"
- process $proc$ls180.v:335$2869
+ attribute \src "ls180.v:343.11-343.47"
+ process $proc$ls180.v:343$2879
assign { } { }
assign $1\main_sdram_interface_wdata_we[1:0] 2'00
sync always
sync init
update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0]
end
- attribute \src "ls180.v:337.12-337.45"
- process $proc$ls180.v:337$2870
+ attribute \src "ls180.v:345.12-345.45"
+ process $proc$ls180.v:345$2880
assign { } { }
assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000
sync always
sync init
update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0]
end
- attribute \src "ls180.v:338.11-338.40"
- process $proc$ls180.v:338$2871
+ attribute \src "ls180.v:346.11-346.40"
+ process $proc$ls180.v:346$2881
assign { } { }
assign $1\main_sdram_dfi_p0_bank[1:0] 2'00
sync always
sync init
update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0]
end
- attribute \src "ls180.v:339.5-339.35"
- process $proc$ls180.v:339$2872
+ attribute \src "ls180.v:347.5-347.35"
+ process $proc$ls180.v:347$2882
assign { } { }
assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1
sync always
sync init
update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0]
end
- attribute \src "ls180.v:340.5-340.34"
- process $proc$ls180.v:340$2873
- assign { } { }
- assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1
- sync always
- sync init
- update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0]
- end
- attribute \src "ls180.v:341.5-341.35"
- process $proc$ls180.v:341$2874
- assign { } { }
- assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1
- sync always
- sync init
- update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0]
- end
- attribute \src "ls180.v:342.5-342.34"
- process $proc$ls180.v:342$2875
- assign { } { }
- assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1
- sync always
- sync init
- update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0]
- end
- attribute \src "ls180.v:3440.1-3447.4"
- process $proc$ls180.v:3440$142
+ attribute \src "ls180.v:3471.1-3478.4"
+ process $proc$ls180.v:3471$142
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
- attribute \src "ls180.v:3442.2-3446.5"
+ attribute \src "ls180.v:3473.2-3477.5"
switch \main_sdram_bankmachine2_row_col_n_addr_sel
- attribute \src "ls180.v:3442.6-3442.48"
+ attribute \src "ls180.v:3473.6-3473.48"
case 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
- attribute \src "ls180.v:3444.6-3444.10"
+ attribute \src "ls180.v:3475.6-3475.10"
case
- assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3445$144_Y
+ assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3476$144_Y
end
sync always
update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:3451.1-3458.4"
- process $proc$ls180.v:3451$151
+ attribute \src "ls180.v:348.5-348.34"
+ process $proc$ls180.v:348$2883
+ assign { } { }
+ assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1
+ sync always
+ sync init
+ update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0]
+ end
+ attribute \src "ls180.v:3482.1-3489.4"
+ process $proc$ls180.v:3482$151
assign { } { }
assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0
- attribute \src "ls180.v:3453.2-3457.5"
- switch $and$ls180.v:3453$152_Y
- attribute \src "ls180.v:3453.6-3453.115"
+ attribute \src "ls180.v:3484.2-3488.5"
+ switch $and$ls180.v:3484$152_Y
+ attribute \src "ls180.v:3484.6-3484.115"
case 1'1
- attribute \src "ls180.v:3454.3-3456.6"
- switch $ne$ls180.v:3454$153_Y
- attribute \src "ls180.v:3454.7-3454.143"
+ attribute \src "ls180.v:3485.3-3487.6"
+ switch $ne$ls180.v:3485$153_Y
+ attribute \src "ls180.v:3485.7-3485.143"
case 1'1
- assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3455$154_Y
+ assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3486$154_Y
case
end
case
sync always
update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0]
end
- attribute \src "ls180.v:346.5-346.35"
- process $proc$ls180.v:346$2876
+ attribute \src "ls180.v:349.5-349.35"
+ process $proc$ls180.v:349$2884
assign { } { }
- assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1
+ assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1
sync always
- update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0]
sync init
+ update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0]
end
- attribute \src "ls180.v:3473.1-3480.4"
- process $proc$ls180.v:3473$155
+ attribute \src "ls180.v:350.5-350.34"
+ process $proc$ls180.v:350$2885
+ assign { } { }
+ assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1
+ sync always
+ sync init
+ update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0]
+ end
+ attribute \src "ls180.v:3504.1-3511.4"
+ process $proc$ls180.v:3504$155
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- attribute \src "ls180.v:3475.2-3479.5"
+ attribute \src "ls180.v:3506.2-3510.5"
switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:3475.6-3475.58"
+ attribute \src "ls180.v:3506.6-3506.58"
case 1'1
- assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3476$156_Y
- attribute \src "ls180.v:3477.6-3477.10"
+ assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3507$156_Y
+ attribute \src "ls180.v:3508.6-3508.10"
case
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
end
sync always
update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:348.5-348.39"
- process $proc$ls180.v:348$2877
- assign { } { }
- assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0
- sync always
- sync init
- update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0]
- end
- attribute \src "ls180.v:3489.1-3582.4"
- process $proc$ls180.v:3489$164
+ attribute \src "ls180.v:3520.1-3613.4"
+ process $proc$ls180.v:3520$164
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
+ assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
+ assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
+ assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
+ assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
- assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
+ assign { } { }
assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0
assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0
- assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
- assign { } { }
- assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
- assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
- assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state
- attribute \src "ls180.v:3505.2-3581.9"
+ attribute \src "ls180.v:3536.2-3612.9"
switch \builder_bankmachine2_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1
- attribute \src "ls180.v:3507.4-3515.7"
- switch $and$ls180.v:3507$165_Y
- attribute \src "ls180.v:3507.8-3507.87"
+ attribute \src "ls180.v:3538.4-3546.7"
+ switch $and$ls180.v:3538$165_Y
+ attribute \src "ls180.v:3538.8-3538.87"
case 1'1
assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3509.5-3511.8"
+ attribute \src "ls180.v:3540.5-3542.8"
switch \main_sdram_bankmachine2_cmd_ready
- attribute \src "ls180.v:3509.9-3509.42"
+ attribute \src "ls180.v:3540.9-3540.42"
case 1'1
assign $0\builder_bankmachine2_next_state[2:0] 3'101
case
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1
- attribute \src "ls180.v:3519.4-3521.7"
- switch $and$ls180.v:3519$166_Y
- attribute \src "ls180.v:3519.8-3519.87"
+ attribute \src "ls180.v:3550.4-3552.7"
+ switch $and$ls180.v:3550$166_Y
+ attribute \src "ls180.v:3550.8-3550.87"
case 1'1
assign $0\builder_bankmachine2_next_state[2:0] 3'101
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:3525.4-3534.7"
+ attribute \src "ls180.v:3556.4-3565.7"
switch \main_sdram_bankmachine2_trccon_ready
- attribute \src "ls180.v:3525.8-3525.44"
+ attribute \src "ls180.v:3556.8-3556.44"
case 1'1
assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1
assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1
- attribute \src "ls180.v:3530.5-3532.8"
+ attribute \src "ls180.v:3561.5-3563.8"
switch \main_sdram_bankmachine2_cmd_ready
- attribute \src "ls180.v:3530.9-3530.42"
+ attribute \src "ls180.v:3561.9-3561.42"
case 1'1
assign $0\builder_bankmachine2_next_state[2:0] 3'110
case
case 3'100
assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3537.4-3539.7"
+ attribute \src "ls180.v:3568.4-3570.7"
switch \main_sdram_bankmachine2_twtpcon_ready
- attribute \src "ls180.v:3537.8-3537.45"
+ attribute \src "ls180.v:3568.8-3568.45"
case 1'1
assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1
case
end
- attribute \src "ls180.v:3542.4-3544.7"
- switch $not$ls180.v:3542$167_Y
- attribute \src "ls180.v:3542.8-3542.46"
+ attribute \src "ls180.v:3573.4-3575.7"
+ switch $not$ls180.v:3573$167_Y
+ attribute \src "ls180.v:3573.8-3573.46"
case 1'1
assign $0\builder_bankmachine2_next_state[2:0] 3'000
case
assign $0\builder_bankmachine2_next_state[2:0] 3'000
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:3553.4-3579.7"
+ attribute \src "ls180.v:3584.4-3610.7"
switch \main_sdram_bankmachine2_refresh_req
- attribute \src "ls180.v:3553.8-3553.43"
+ attribute \src "ls180.v:3584.8-3584.43"
case 1'1
assign $0\builder_bankmachine2_next_state[2:0] 3'100
- attribute \src "ls180.v:3555.8-3555.12"
+ attribute \src "ls180.v:3586.8-3586.12"
case
- attribute \src "ls180.v:3556.5-3578.8"
+ attribute \src "ls180.v:3587.5-3609.8"
switch \main_sdram_bankmachine2_cmd_buffer_source_valid
- attribute \src "ls180.v:3556.9-3556.56"
+ attribute \src "ls180.v:3587.9-3587.56"
case 1'1
- attribute \src "ls180.v:3557.6-3577.9"
+ attribute \src "ls180.v:3588.6-3608.9"
switch \main_sdram_bankmachine2_row_opened
- attribute \src "ls180.v:3557.10-3557.44"
+ attribute \src "ls180.v:3588.10-3588.44"
case 1'1
- attribute \src "ls180.v:3558.7-3574.10"
+ attribute \src "ls180.v:3589.7-3605.10"
switch \main_sdram_bankmachine2_row_hit
- attribute \src "ls180.v:3558.11-3558.42"
+ attribute \src "ls180.v:3589.11-3589.42"
case 1'1
assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1
- attribute \src "ls180.v:3560.8-3567.11"
+ attribute \src "ls180.v:3591.8-3598.11"
switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we
- attribute \src "ls180.v:3560.12-3560.64"
+ attribute \src "ls180.v:3591.12-3591.64"
case 1'1
assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready
assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1
assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1
- attribute \src "ls180.v:3564.12-3564.16"
+ attribute \src "ls180.v:3595.12-3595.16"
case
assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready
assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1
end
- attribute \src "ls180.v:3569.8-3571.11"
- switch $and$ls180.v:3569$168_Y
- attribute \src "ls180.v:3569.12-3569.88"
+ attribute \src "ls180.v:3600.8-3602.11"
+ switch $and$ls180.v:3600$168_Y
+ attribute \src "ls180.v:3600.12-3600.88"
case 1'1
assign $0\builder_bankmachine2_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:3572.11-3572.15"
+ attribute \src "ls180.v:3603.11-3603.15"
case
assign $0\builder_bankmachine2_next_state[2:0] 3'001
end
- attribute \src "ls180.v:3575.10-3575.14"
+ attribute \src "ls180.v:3606.10-3606.14"
case
assign $0\builder_bankmachine2_next_state[2:0] 3'011
end
update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0]
end
- attribute \src "ls180.v:350.5-350.39"
- process $proc$ls180.v:350$2878
- assign { } { }
- assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0
- sync always
- sync init
- update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0]
- end
- attribute \src "ls180.v:353.5-353.32"
- process $proc$ls180.v:353$2879
- assign { } { }
- assign $1\main_sdram_cmd_valid[0:0] 1'0
- sync always
- sync init
- update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0]
- end
- attribute \src "ls180.v:354.5-354.32"
- process $proc$ls180.v:354$2880
+ attribute \src "ls180.v:354.5-354.35"
+ process $proc$ls180.v:354$2886
assign { } { }
- assign $1\main_sdram_cmd_ready[0:0] 1'0
- sync always
- sync init
- update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0]
- end
- attribute \src "ls180.v:355.5-355.31"
- process $proc$ls180.v:355$2881
- assign { } { }
- assign $1\main_sdram_cmd_last[0:0] 1'0
+ assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1
sync always
+ update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0]
sync init
- update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0]
end
- attribute \src "ls180.v:356.12-356.44"
- process $proc$ls180.v:356$2882
+ attribute \src "ls180.v:356.5-356.39"
+ process $proc$ls180.v:356$2887
assign { } { }
- assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000
+ assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0
sync always
sync init
- update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0]
+ update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0]
end
- attribute \src "ls180.v:357.11-357.43"
- process $proc$ls180.v:357$2883
+ attribute \src "ls180.v:358.5-358.39"
+ process $proc$ls180.v:358$2888
assign { } { }
- assign $1\main_sdram_cmd_payload_ba[1:0] 2'00
+ assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0
sync always
sync init
- update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0]
+ update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0]
end
- attribute \src "ls180.v:358.5-358.38"
- process $proc$ls180.v:358$2884
+ attribute \src "ls180.v:361.5-361.32"
+ process $proc$ls180.v:361$2889
assign { } { }
- assign $1\main_sdram_cmd_payload_cas[0:0] 1'0
+ assign $1\main_sdram_cmd_valid[0:0] 1'0
sync always
sync init
- update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0]
+ update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0]
end
- attribute \src "ls180.v:359.5-359.38"
- process $proc$ls180.v:359$2885
+ attribute \src "ls180.v:362.5-362.32"
+ process $proc$ls180.v:362$2890
assign { } { }
- assign $1\main_sdram_cmd_payload_ras[0:0] 1'0
+ assign $1\main_sdram_cmd_ready[0:0] 1'0
sync always
sync init
- update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0]
+ update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0]
end
- attribute \src "ls180.v:3597.1-3604.4"
- process $proc$ls180.v:3597$172
+ attribute \src "ls180.v:3628.1-3635.4"
+ process $proc$ls180.v:3628$172
assign { } { }
assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
- attribute \src "ls180.v:3599.2-3603.5"
+ attribute \src "ls180.v:3630.2-3634.5"
switch \main_sdram_bankmachine3_row_col_n_addr_sel
- attribute \src "ls180.v:3599.6-3599.48"
+ attribute \src "ls180.v:3630.6-3630.48"
case 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
- attribute \src "ls180.v:3601.6-3601.10"
+ attribute \src "ls180.v:3632.6-3632.10"
case
- assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3602$174_Y
+ assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3633$174_Y
end
sync always
update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:360.5-360.37"
- process $proc$ls180.v:360$2886
+ attribute \src "ls180.v:363.5-363.31"
+ process $proc$ls180.v:363$2891
assign { } { }
- assign $1\main_sdram_cmd_payload_we[0:0] 1'0
+ assign $1\main_sdram_cmd_last[0:0] 1'0
sync always
sync init
- update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0]
+ update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0]
end
- attribute \src "ls180.v:3608.1-3615.4"
- process $proc$ls180.v:3608$181
+ attribute \src "ls180.v:3639.1-3646.4"
+ process $proc$ls180.v:3639$181
assign { } { }
assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
- attribute \src "ls180.v:3610.2-3614.5"
- switch $and$ls180.v:3610$182_Y
- attribute \src "ls180.v:3610.6-3610.115"
+ attribute \src "ls180.v:3641.2-3645.5"
+ switch $and$ls180.v:3641$182_Y
+ attribute \src "ls180.v:3641.6-3641.115"
case 1'1
- attribute \src "ls180.v:3611.3-3613.6"
- switch $ne$ls180.v:3611$183_Y
- attribute \src "ls180.v:3611.7-3611.143"
+ attribute \src "ls180.v:3642.3-3644.6"
+ switch $ne$ls180.v:3642$183_Y
+ attribute \src "ls180.v:3642.7-3642.143"
case 1'1
- assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3612$184_Y
+ assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3643$184_Y
case
end
case
sync always
update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0]
end
- attribute \src "ls180.v:361.5-361.42"
- process $proc$ls180.v:361$2887
+ attribute \src "ls180.v:364.12-364.44"
+ process $proc$ls180.v:364$2892
assign { } { }
- assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0
+ assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000
sync always
- update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0]
sync init
+ update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:362.5-362.43"
- process $proc$ls180.v:362$2888
+ attribute \src "ls180.v:365.11-365.43"
+ process $proc$ls180.v:365$2893
assign { } { }
- assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0
+ assign $1\main_sdram_cmd_payload_ba[1:0] 2'00
+ sync always
+ sync init
+ update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0]
+ end
+ attribute \src "ls180.v:366.5-366.38"
+ process $proc$ls180.v:366$2894
+ assign { } { }
+ assign $1\main_sdram_cmd_payload_cas[0:0] 1'0
sync always
- update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0]
sync init
+ update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:3630.1-3637.4"
- process $proc$ls180.v:3630$185
+ attribute \src "ls180.v:3661.1-3668.4"
+ process $proc$ls180.v:3661$185
assign { } { }
assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- attribute \src "ls180.v:3632.2-3636.5"
+ attribute \src "ls180.v:3663.2-3667.5"
switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:3632.6-3632.58"
+ attribute \src "ls180.v:3663.6-3663.58"
case 1'1
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3633$186_Y
- attribute \src "ls180.v:3634.6-3634.10"
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3664$186_Y
+ attribute \src "ls180.v:3665.6-3665.10"
case
assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
end
sync always
update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:3646.1-3739.4"
- process $proc$ls180.v:3646$194
+ attribute \src "ls180.v:367.5-367.38"
+ process $proc$ls180.v:367$2895
+ assign { } { }
+ assign $1\main_sdram_cmd_payload_ras[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0]
+ end
+ attribute \src "ls180.v:3677.1-3770.4"
+ process $proc$ls180.v:3677$194
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0
+ assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0
+ assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
+ assign { } { }
assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0
assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
- assign { } { }
- assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0
- assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0
- assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state
- attribute \src "ls180.v:3662.2-3738.9"
+ attribute \src "ls180.v:3693.2-3769.9"
switch \builder_bankmachine3_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1
- attribute \src "ls180.v:3664.4-3672.7"
- switch $and$ls180.v:3664$195_Y
- attribute \src "ls180.v:3664.8-3664.87"
+ attribute \src "ls180.v:3695.4-3703.7"
+ switch $and$ls180.v:3695$195_Y
+ attribute \src "ls180.v:3695.8-3695.87"
case 1'1
assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3666.5-3668.8"
+ attribute \src "ls180.v:3697.5-3699.8"
switch \main_sdram_bankmachine3_cmd_ready
- attribute \src "ls180.v:3666.9-3666.42"
+ attribute \src "ls180.v:3697.9-3697.42"
case 1'1
assign $0\builder_bankmachine3_next_state[2:0] 3'101
case
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1
- attribute \src "ls180.v:3676.4-3678.7"
- switch $and$ls180.v:3676$196_Y
- attribute \src "ls180.v:3676.8-3676.87"
+ attribute \src "ls180.v:3707.4-3709.7"
+ switch $and$ls180.v:3707$196_Y
+ attribute \src "ls180.v:3707.8-3707.87"
case 1'1
assign $0\builder_bankmachine3_next_state[2:0] 3'101
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:3682.4-3691.7"
+ attribute \src "ls180.v:3713.4-3722.7"
switch \main_sdram_bankmachine3_trccon_ready
- attribute \src "ls180.v:3682.8-3682.44"
+ attribute \src "ls180.v:3713.8-3713.44"
case 1'1
assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1
assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1
- attribute \src "ls180.v:3687.5-3689.8"
+ attribute \src "ls180.v:3718.5-3720.8"
switch \main_sdram_bankmachine3_cmd_ready
- attribute \src "ls180.v:3687.9-3687.42"
+ attribute \src "ls180.v:3718.9-3718.42"
case 1'1
assign $0\builder_bankmachine3_next_state[2:0] 3'110
case
case 3'100
assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:3694.4-3696.7"
+ attribute \src "ls180.v:3725.4-3727.7"
switch \main_sdram_bankmachine3_twtpcon_ready
- attribute \src "ls180.v:3694.8-3694.45"
+ attribute \src "ls180.v:3725.8-3725.45"
case 1'1
assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1
case
end
- attribute \src "ls180.v:3699.4-3701.7"
- switch $not$ls180.v:3699$197_Y
- attribute \src "ls180.v:3699.8-3699.46"
+ attribute \src "ls180.v:3730.4-3732.7"
+ switch $not$ls180.v:3730$197_Y
+ attribute \src "ls180.v:3730.8-3730.46"
case 1'1
assign $0\builder_bankmachine3_next_state[2:0] 3'000
case
assign $0\builder_bankmachine3_next_state[2:0] 3'000
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:3710.4-3736.7"
+ attribute \src "ls180.v:3741.4-3767.7"
switch \main_sdram_bankmachine3_refresh_req
- attribute \src "ls180.v:3710.8-3710.43"
+ attribute \src "ls180.v:3741.8-3741.43"
case 1'1
assign $0\builder_bankmachine3_next_state[2:0] 3'100
- attribute \src "ls180.v:3712.8-3712.12"
+ attribute \src "ls180.v:3743.8-3743.12"
case
- attribute \src "ls180.v:3713.5-3735.8"
+ attribute \src "ls180.v:3744.5-3766.8"
switch \main_sdram_bankmachine3_cmd_buffer_source_valid
- attribute \src "ls180.v:3713.9-3713.56"
+ attribute \src "ls180.v:3744.9-3744.56"
case 1'1
- attribute \src "ls180.v:3714.6-3734.9"
+ attribute \src "ls180.v:3745.6-3765.9"
switch \main_sdram_bankmachine3_row_opened
- attribute \src "ls180.v:3714.10-3714.44"
+ attribute \src "ls180.v:3745.10-3745.44"
case 1'1
- attribute \src "ls180.v:3715.7-3731.10"
+ attribute \src "ls180.v:3746.7-3762.10"
switch \main_sdram_bankmachine3_row_hit
- attribute \src "ls180.v:3715.11-3715.42"
+ attribute \src "ls180.v:3746.11-3746.42"
case 1'1
assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1
- attribute \src "ls180.v:3717.8-3724.11"
+ attribute \src "ls180.v:3748.8-3755.11"
switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we
- attribute \src "ls180.v:3717.12-3717.64"
+ attribute \src "ls180.v:3748.12-3748.64"
case 1'1
assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready
assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1
assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1
- attribute \src "ls180.v:3721.12-3721.16"
+ attribute \src "ls180.v:3752.12-3752.16"
case
assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready
assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1
end
- attribute \src "ls180.v:3726.8-3728.11"
- switch $and$ls180.v:3726$198_Y
- attribute \src "ls180.v:3726.12-3726.88"
+ attribute \src "ls180.v:3757.8-3759.11"
+ switch $and$ls180.v:3757$198_Y
+ attribute \src "ls180.v:3757.12-3757.88"
case 1'1
assign $0\builder_bankmachine3_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:3729.11-3729.15"
+ attribute \src "ls180.v:3760.11-3760.15"
case
assign $0\builder_bankmachine3_next_state[2:0] 3'001
end
- attribute \src "ls180.v:3732.10-3732.14"
+ attribute \src "ls180.v:3763.10-3763.14"
case
assign $0\builder_bankmachine3_next_state[2:0] 3'011
end
update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0]
end
- attribute \src "ls180.v:368.11-368.44"
- process $proc$ls180.v:368$2889
+ attribute \src "ls180.v:368.5-368.37"
+ process $proc$ls180.v:368$2896
assign { } { }
- assign $1\main_sdram_timer_count1[9:0] 10'1100001101
+ assign $1\main_sdram_cmd_payload_we[0:0] 1'0
sync always
sync init
- update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0]
+ update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:370.5-370.38"
- process $proc$ls180.v:370$2890
+ attribute \src "ls180.v:369.5-369.42"
+ process $proc$ls180.v:369$2897
assign { } { }
- assign $1\main_sdram_postponer_req_o[0:0] 1'0
+ assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0
sync always
+ update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0]
sync init
- update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0]
end
- attribute \src "ls180.v:371.5-371.38"
- process $proc$ls180.v:371$2891
+ attribute \src "ls180.v:370.5-370.43"
+ process $proc$ls180.v:370$2898
assign { } { }
- assign $1\main_sdram_postponer_count[0:0] 1'0
+ assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0
sync always
+ update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0]
sync init
- update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0]
end
- attribute \src "ls180.v:372.5-372.39"
- process $proc$ls180.v:372$2892
+ attribute \src "ls180.v:376.11-376.44"
+ process $proc$ls180.v:376$2899
assign { } { }
- assign $1\main_sdram_sequencer_start0[0:0] 1'0
+ assign $1\main_sdram_timer_count1[9:0] 10'1100001101
sync always
sync init
- update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0]
+ update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0]
end
- attribute \src "ls180.v:375.5-375.38"
- process $proc$ls180.v:375$2893
+ attribute \src "ls180.v:378.5-378.38"
+ process $proc$ls180.v:378$2900
assign { } { }
- assign $1\main_sdram_sequencer_done1[0:0] 1'0
+ assign $1\main_sdram_postponer_req_o[0:0] 1'0
sync always
sync init
- update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0]
+ update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0]
end
- attribute \src "ls180.v:3759.1-3765.4"
- process $proc$ls180.v:3759$237
- assign { } { }
+ attribute \src "ls180.v:379.5-379.38"
+ process $proc$ls180.v:379$2901
assign { } { }
- assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3761$250_Y
- assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3762$263_Y
- assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3763$276_Y
- assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3764$289_Y
+ assign $1\main_sdram_postponer_count[0:0] 1'0
sync always
- update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0]
+ sync init
+ update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0]
end
- attribute \src "ls180.v:376.11-376.46"
- process $proc$ls180.v:376$2894
+ attribute \src "ls180.v:3790.1-3796.4"
+ process $proc$ls180.v:3790$237
assign { } { }
- assign $1\main_sdram_sequencer_counter[3:0] 4'0000
+ assign { } { }
+ assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3792$250_Y
+ assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3793$263_Y
+ assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3794$276_Y
+ assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3795$289_Y
sync always
- sync init
- update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0]
+ update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0]
end
- attribute \src "ls180.v:377.5-377.38"
- process $proc$ls180.v:377$2895
+ attribute \src "ls180.v:380.5-380.39"
+ process $proc$ls180.v:380$2902
assign { } { }
- assign $1\main_sdram_sequencer_count[0:0] 1'0
+ assign $1\main_sdram_sequencer_start0[0:0] 1'0
sync always
sync init
- update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0]
+ update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0]
end
- attribute \src "ls180.v:3773.1-3778.4"
- process $proc$ls180.v:3773$290
+ attribute \src "ls180.v:3804.1-3809.4"
+ process $proc$ls180.v:3804$290
assign { } { }
assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
- attribute \src "ls180.v:3775.2-3777.5"
+ attribute \src "ls180.v:3806.2-3808.5"
switch \main_sdram_choose_cmd_cmd_valid
- attribute \src "ls180.v:3775.6-3775.37"
+ attribute \src "ls180.v:3806.6-3806.37"
case 1'1
assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0
case
sync always
update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:3779.1-3784.4"
- process $proc$ls180.v:3779$291
+ attribute \src "ls180.v:3810.1-3815.4"
+ process $proc$ls180.v:3810$291
assign { } { }
assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
- attribute \src "ls180.v:3781.2-3783.5"
+ attribute \src "ls180.v:3812.2-3814.5"
switch \main_sdram_choose_cmd_cmd_valid
- attribute \src "ls180.v:3781.6-3781.37"
+ attribute \src "ls180.v:3812.6-3812.37"
case 1'1
assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1
case
sync always
update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:3785.1-3790.4"
- process $proc$ls180.v:3785$292
+ attribute \src "ls180.v:3816.1-3821.4"
+ process $proc$ls180.v:3816$292
assign { } { }
assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0
- attribute \src "ls180.v:3787.2-3789.5"
+ attribute \src "ls180.v:3818.2-3820.5"
switch \main_sdram_choose_cmd_cmd_valid
- attribute \src "ls180.v:3787.6-3787.37"
+ attribute \src "ls180.v:3818.6-3818.37"
case 1'1
assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2
case
sync always
update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:3792.1-3798.4"
- process $proc$ls180.v:3792$295
+ attribute \src "ls180.v:3823.1-3829.4"
+ process $proc$ls180.v:3823$295
assign { } { }
assign { } { }
- assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3794$308_Y
- assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3795$321_Y
- assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3796$334_Y
- assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3797$347_Y
+ assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3825$308_Y
+ assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3826$321_Y
+ assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3827$334_Y
+ assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3828$347_Y
sync always
update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0]
end
- attribute \src "ls180.v:3806.1-3811.4"
- process $proc$ls180.v:3806$348
+ attribute \src "ls180.v:383.5-383.38"
+ process $proc$ls180.v:383$2903
+ assign { } { }
+ assign $1\main_sdram_sequencer_done1[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0]
+ end
+ attribute \src "ls180.v:3837.1-3842.4"
+ process $proc$ls180.v:3837$348
assign { } { }
assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0
- attribute \src "ls180.v:3808.2-3810.5"
+ attribute \src "ls180.v:3839.2-3841.5"
switch \main_sdram_choose_req_cmd_valid
- attribute \src "ls180.v:3808.6-3808.37"
+ attribute \src "ls180.v:3839.6-3839.37"
case 1'1
assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3
case
sync always
update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:3812.1-3817.4"
- process $proc$ls180.v:3812$349
+ attribute \src "ls180.v:384.11-384.46"
+ process $proc$ls180.v:384$2904
+ assign { } { }
+ assign $1\main_sdram_sequencer_counter[3:0] 4'0000
+ sync always
+ sync init
+ update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0]
+ end
+ attribute \src "ls180.v:3843.1-3848.4"
+ process $proc$ls180.v:3843$349
assign { } { }
assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0
- attribute \src "ls180.v:3814.2-3816.5"
+ attribute \src "ls180.v:3845.2-3847.5"
switch \main_sdram_choose_req_cmd_valid
- attribute \src "ls180.v:3814.6-3814.37"
+ attribute \src "ls180.v:3845.6-3845.37"
case 1'1
assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4
case
sync always
update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:3818.1-3823.4"
- process $proc$ls180.v:3818$350
+ attribute \src "ls180.v:3849.1-3854.4"
+ process $proc$ls180.v:3849$350
assign { } { }
assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0
- attribute \src "ls180.v:3820.2-3822.5"
+ attribute \src "ls180.v:3851.2-3853.5"
switch \main_sdram_choose_req_cmd_valid
- attribute \src "ls180.v:3820.6-3820.37"
+ attribute \src "ls180.v:3851.6-3851.37"
case 1'1
assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5
case
sync always
update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:3824.1-3832.4"
- process $proc$ls180.v:3824$351
+ attribute \src "ls180.v:385.5-385.38"
+ process $proc$ls180.v:385$2905
+ assign { } { }
+ assign $1\main_sdram_sequencer_count[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0]
+ end
+ attribute \src "ls180.v:3855.1-3863.4"
+ process $proc$ls180.v:3855$351
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
- attribute \src "ls180.v:3826.2-3828.5"
- switch $and$ls180.v:3826$354_Y
- attribute \src "ls180.v:3826.6-3826.115"
+ attribute \src "ls180.v:3857.2-3859.5"
+ switch $and$ls180.v:3857$354_Y
+ attribute \src "ls180.v:3857.6-3857.115"
case 1'1
assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:3829.2-3831.5"
- switch $and$ls180.v:3829$357_Y
- attribute \src "ls180.v:3829.6-3829.115"
+ attribute \src "ls180.v:3860.2-3862.5"
+ switch $and$ls180.v:3860$357_Y
+ attribute \src "ls180.v:3860.6-3860.115"
case 1'1
assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1
case
sync always
update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0]
end
- attribute \src "ls180.v:383.5-383.51"
- process $proc$ls180.v:383$2896
- assign { } { }
- assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0]
- end
- attribute \src "ls180.v:3833.1-3841.4"
- process $proc$ls180.v:3833$358
+ attribute \src "ls180.v:3864.1-3872.4"
+ process $proc$ls180.v:3864$358
assign { } { }
assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0
- attribute \src "ls180.v:3835.2-3837.5"
- switch $and$ls180.v:3835$361_Y
- attribute \src "ls180.v:3835.6-3835.115"
+ attribute \src "ls180.v:3866.2-3868.5"
+ switch $and$ls180.v:3866$361_Y
+ attribute \src "ls180.v:3866.6-3866.115"
case 1'1
assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:3838.2-3840.5"
- switch $and$ls180.v:3838$364_Y
- attribute \src "ls180.v:3838.6-3838.115"
+ attribute \src "ls180.v:3869.2-3871.5"
+ switch $and$ls180.v:3869$364_Y
+ attribute \src "ls180.v:3869.6-3869.115"
case 1'1
assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1
case
sync always
update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0]
end
- attribute \src "ls180.v:384.5-384.51"
- process $proc$ls180.v:384$2897
- assign { } { }
- assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0]
- end
- attribute \src "ls180.v:3842.1-3850.4"
- process $proc$ls180.v:3842$365
+ attribute \src "ls180.v:3873.1-3881.4"
+ process $proc$ls180.v:3873$365
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0
- attribute \src "ls180.v:3844.2-3846.5"
- switch $and$ls180.v:3844$368_Y
- attribute \src "ls180.v:3844.6-3844.115"
+ attribute \src "ls180.v:3875.2-3877.5"
+ switch $and$ls180.v:3875$368_Y
+ attribute \src "ls180.v:3875.6-3875.115"
case 1'1
assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:3847.2-3849.5"
- switch $and$ls180.v:3847$371_Y
- attribute \src "ls180.v:3847.6-3847.115"
+ attribute \src "ls180.v:3878.2-3880.5"
+ switch $and$ls180.v:3878$371_Y
+ attribute \src "ls180.v:3878.6-3878.115"
case 1'1
assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1
case
sync always
update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0]
end
- attribute \src "ls180.v:3851.1-3859.4"
- process $proc$ls180.v:3851$372
+ attribute \src "ls180.v:3882.1-3890.4"
+ process $proc$ls180.v:3882$372
assign { } { }
assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0
- attribute \src "ls180.v:3853.2-3855.5"
- switch $and$ls180.v:3853$375_Y
- attribute \src "ls180.v:3853.6-3853.115"
+ attribute \src "ls180.v:3884.2-3886.5"
+ switch $and$ls180.v:3884$375_Y
+ attribute \src "ls180.v:3884.6-3884.115"
case 1'1
assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:3856.2-3858.5"
- switch $and$ls180.v:3856$378_Y
- attribute \src "ls180.v:3856.6-3856.115"
+ attribute \src "ls180.v:3887.2-3889.5"
+ switch $and$ls180.v:3887$378_Y
+ attribute \src "ls180.v:3887.6-3887.115"
case 1'1
assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1
case
sync always
update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0]
end
- attribute \src "ls180.v:386.5-386.47"
- process $proc$ls180.v:386$2898
+ attribute \src "ls180.v:3895.1-3967.4"
+ process $proc$ls180.v:3895$381
assign { } { }
- assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0]
- end
- attribute \src "ls180.v:3864.1-3936.4"
- process $proc$ls180.v:3864$381
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0
+ assign $0\main_sdram_en0[0:0] 1'0
assign { } { }
assign $0\main_sdram_en1[0:0] 1'0
assign $0\main_sdram_choose_req_want_reads[0:0] 1'0
assign $0\main_sdram_choose_req_want_writes[0:0] 1'0
- assign { } { }
- assign { } { }
assign $0\main_sdram_cmd_ready[0:0] 1'0
+ assign { } { }
assign $0\main_sdram_steerer_sel[1:0] 2'00
- assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0
- assign $0\main_sdram_en0[0:0] 1'0
assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed
assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state
- attribute \src "ls180.v:3876.2-3935.9"
+ attribute \src "ls180.v:3907.2-3966.9"
switch \builder_multiplexer_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdram_en1[0:0] 1'1
assign $0\main_sdram_choose_req_want_writes[0:0] 1'1
assign $0\main_sdram_steerer_sel[1:0] 2'10
- attribute \src "ls180.v:3880.4-3886.7"
+ attribute \src "ls180.v:3911.4-3917.7"
switch 1'1
- attribute \src "ls180.v:3880.8-3880.12"
+ attribute \src "ls180.v:3911.8-3911.12"
case 1'1
- assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3881$388_Y
+ assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3912$388_Y
case
end
- attribute \src "ls180.v:3888.4-3892.7"
+ attribute \src "ls180.v:3919.4-3923.7"
switch \main_sdram_read_available
- attribute \src "ls180.v:3888.8-3888.33"
+ attribute \src "ls180.v:3919.8-3919.33"
case 1'1
- attribute \src "ls180.v:3889.5-3891.8"
- switch $or$ls180.v:3889$390_Y
- attribute \src "ls180.v:3889.9-3889.63"
+ attribute \src "ls180.v:3920.5-3922.8"
+ switch $or$ls180.v:3920$390_Y
+ attribute \src "ls180.v:3920.9-3920.63"
case 1'1
assign $0\builder_multiplexer_next_state[2:0] 3'011
case
end
case
end
- attribute \src "ls180.v:3893.4-3895.7"
+ attribute \src "ls180.v:3924.4-3926.7"
switch \main_sdram_go_to_refresh
- attribute \src "ls180.v:3893.8-3893.32"
+ attribute \src "ls180.v:3924.8-3924.32"
case 1'1
assign $0\builder_multiplexer_next_state[2:0] 3'010
case
case 3'010
assign $0\main_sdram_steerer_sel[1:0] 2'11
assign $0\main_sdram_cmd_ready[0:0] 1'1
- attribute \src "ls180.v:3900.4-3902.7"
+ attribute \src "ls180.v:3931.4-3933.7"
switch \main_sdram_cmd_last
- attribute \src "ls180.v:3900.8-3900.27"
+ attribute \src "ls180.v:3931.8-3931.27"
case 1'1
assign $0\builder_multiplexer_next_state[2:0] 3'000
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:3905.4-3907.7"
+ attribute \src "ls180.v:3936.4-3938.7"
switch \main_sdram_twtrcon_ready
- attribute \src "ls180.v:3905.8-3905.32"
+ attribute \src "ls180.v:3936.8-3936.32"
case 1'1
assign $0\builder_multiplexer_next_state[2:0] 3'000
case
assign $0\main_sdram_en0[0:0] 1'1
assign $0\main_sdram_choose_req_want_reads[0:0] 1'1
assign $0\main_sdram_steerer_sel[1:0] 2'10
- attribute \src "ls180.v:3918.4-3924.7"
+ attribute \src "ls180.v:3949.4-3955.7"
switch 1'1
- attribute \src "ls180.v:3918.8-3918.12"
+ attribute \src "ls180.v:3949.8-3949.12"
case 1'1
- assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3919$397_Y
+ assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3950$397_Y
case
end
- attribute \src "ls180.v:3926.4-3930.7"
+ attribute \src "ls180.v:3957.4-3961.7"
switch \main_sdram_write_available
- attribute \src "ls180.v:3926.8-3926.34"
+ attribute \src "ls180.v:3957.8-3957.34"
case 1'1
- attribute \src "ls180.v:3927.5-3929.8"
- switch $or$ls180.v:3927$399_Y
- attribute \src "ls180.v:3927.9-3927.62"
+ attribute \src "ls180.v:3958.5-3960.8"
+ switch $or$ls180.v:3958$399_Y
+ attribute \src "ls180.v:3958.9-3958.62"
case 1'1
assign $0\builder_multiplexer_next_state[2:0] 3'100
case
end
case
end
- attribute \src "ls180.v:3931.4-3933.7"
+ attribute \src "ls180.v:3962.4-3964.7"
switch \main_sdram_go_to_refresh
- attribute \src "ls180.v:3931.8-3931.32"
+ attribute \src "ls180.v:3962.8-3962.32"
case 1'1
assign $0\builder_multiplexer_next_state[2:0] 3'010
case
update \main_sdram_en1 $0\main_sdram_en1[0:0]
update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0]
end
- attribute \src "ls180.v:387.5-387.45"
- process $proc$ls180.v:387$2899
- assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0]
- end
- attribute \src "ls180.v:388.5-388.45"
- process $proc$ls180.v:388$2900
- assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0]
- end
- attribute \src "ls180.v:389.12-389.57"
- process $proc$ls180.v:389$2901
+ attribute \src "ls180.v:391.5-391.51"
+ process $proc$ls180.v:391$2906
assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
+ assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
+ update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0]
end
- attribute \src "ls180.v:391.5-391.51"
- process $proc$ls180.v:391$2902
+ attribute \src "ls180.v:392.5-392.51"
+ process $proc$ls180.v:392$2907
assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0]
+ update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0]
end
- attribute \src "ls180.v:392.5-392.51"
- process $proc$ls180.v:392$2903
+ attribute \src "ls180.v:394.5-394.47"
+ process $proc$ls180.v:394$2908
assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
+ update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0]
end
- attribute \src "ls180.v:393.5-393.50"
- process $proc$ls180.v:393$2904
+ attribute \src "ls180.v:395.5-395.45"
+ process $proc$ls180.v:395$2909
assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
+ update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0]
end
- attribute \src "ls180.v:394.5-394.54"
- process $proc$ls180.v:394$2905
+ attribute \src "ls180.v:396.5-396.45"
+ process $proc$ls180.v:396$2910
assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
+ update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0]
end
- attribute \src "ls180.v:395.5-395.55"
- process $proc$ls180.v:395$2906
+ attribute \src "ls180.v:397.12-397.57"
+ process $proc$ls180.v:397$2911
assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
sync always
sync init
- update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
+ update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:396.5-396.56"
- process $proc$ls180.v:396$2907
+ attribute \src "ls180.v:399.5-399.51"
+ process $proc$ls180.v:399$2912
assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
+ update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:3960.1-3973.4"
- process $proc$ls180.v:3960$528
+ attribute \src "ls180.v:3991.1-4004.4"
+ process $proc$ls180.v:3991$528
assign { } { }
assign { } { }
assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000
assign $0\main_sdram_interface_wdata_we[1:0] 2'00
- attribute \src "ls180.v:3963.2-3972.9"
+ attribute \src "ls180.v:3994.2-4003.9"
switch \builder_new_master_wdata_ready
attribute \src "ls180.v:0.0-0.0"
case 1'1
update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0]
update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0]
end
- attribute \src "ls180.v:397.5-397.50"
- process $proc$ls180.v:397$2908
+ attribute \src "ls180.v:400.5-400.51"
+ process $proc$ls180.v:400$2913
assign { } { }
- assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0]
+ update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:3980.1-3990.4"
- process $proc$ls180.v:3980$530
+ attribute \src "ls180.v:401.5-401.50"
+ process $proc$ls180.v:401$2914
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
+ end
+ attribute \src "ls180.v:4011.1-4021.4"
+ process $proc$ls180.v:4011$530
assign { } { }
assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000
- attribute \src "ls180.v:3982.2-3989.9"
+ attribute \src "ls180.v:4013.2-4020.9"
switch \main_converter_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
sync always
update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0]
end
- attribute \src "ls180.v:3992.1-4038.4"
- process $proc$ls180.v:3992$531
+ attribute \src "ls180.v:402.5-402.54"
+ process $proc$ls180.v:402$2915
assign { } { }
+ assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
+ end
+ attribute \src "ls180.v:4023.1-4069.4"
+ process $proc$ls180.v:4023$531
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000
+ assign { } { }
+ assign $0\main_converter_skip[0:0] 1'0
assign $0\main_wb_sdram_ack[0:0] 1'0
+ assign { } { }
+ assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000
+ assign $0\main_converter_counter_converter_next_value[0:0] 1'0
+ assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0
assign $0\main_litedram_wb_sel[1:0] 2'00
assign $0\main_litedram_wb_cyc[0:0] 1'0
assign $0\main_litedram_wb_stb[0:0] 1'0
assign $0\main_litedram_wb_we[0:0] 1'0
- assign { } { }
- assign $0\main_converter_counter_converter_next_value[0:0] 1'0
- assign $0\main_converter_skip[0:0] 1'0
- assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0
assign $0\builder_converter_next_state[0:0] \builder_converter_state
- attribute \src "ls180.v:4004.2-4037.9"
+ attribute \src "ls180.v:4035.2-4068.9"
switch \builder_converter_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter }
- attribute \src "ls180.v:4007.4-4014.11"
+ attribute \src "ls180.v:4038.4-4045.11"
switch \main_converter_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2]
case
end
- attribute \src "ls180.v:4015.4-4028.7"
- switch $and$ls180.v:4015$532_Y
- attribute \src "ls180.v:4015.8-4015.47"
+ attribute \src "ls180.v:4046.4-4059.7"
+ switch $and$ls180.v:4046$532_Y
+ attribute \src "ls180.v:4046.8-4046.47"
case 1'1
- assign $0\main_converter_skip[0:0] $eq$ls180.v:4016$533_Y
+ assign $0\main_converter_skip[0:0] $eq$ls180.v:4047$533_Y
assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we
- assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4018$534_Y
- assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4019$535_Y
- attribute \src "ls180.v:4020.5-4027.8"
- switch $or$ls180.v:4020$536_Y
- attribute \src "ls180.v:4020.9-4020.53"
+ assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4049$534_Y
+ assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4050$535_Y
+ attribute \src "ls180.v:4051.5-4058.8"
+ switch $or$ls180.v:4051$536_Y
+ attribute \src "ls180.v:4051.9-4051.53"
case 1'1
- assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4021$537_Y
+ assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4052$537_Y
assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4023.6-4026.9"
- switch $eq$ls180.v:4023$538_Y
- attribute \src "ls180.v:4023.10-4023.42"
+ attribute \src "ls180.v:4054.6-4057.9"
+ switch $eq$ls180.v:4054$538_Y
+ attribute \src "ls180.v:4054.10-4054.42"
case 1'1
assign $0\main_wb_sdram_ack[0:0] 1'1
assign $0\builder_converter_next_state[0:0] 1'0
case
assign $0\main_converter_counter_converter_next_value[0:0] 1'0
assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4033.4-4035.7"
- switch $and$ls180.v:4033$539_Y
- attribute \src "ls180.v:4033.8-4033.47"
+ attribute \src "ls180.v:4064.4-4066.7"
+ switch $and$ls180.v:4064$539_Y
+ attribute \src "ls180.v:4064.8-4064.47"
case 1'1
assign $0\builder_converter_next_state[0:0] 1'1
case
update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0]
update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0]
end
- attribute \src "ls180.v:400.5-400.67"
- process $proc$ls180.v:400$2909
+ attribute \src "ls180.v:403.5-403.55"
+ process $proc$ls180.v:403$2916
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
+ end
+ attribute \src "ls180.v:404.5-404.56"
+ process $proc$ls180.v:404$2917
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
+ end
+ attribute \src "ls180.v:405.5-405.50"
+ process $proc$ls180.v:405$2918
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0]
+ end
+ attribute \src "ls180.v:408.5-408.67"
+ process $proc$ls180.v:408$2919
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:401.5-401.66"
- process $proc$ls180.v:401$2910
+ attribute \src "ls180.v:409.5-409.66"
+ process $proc$ls180.v:409$2920
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:4083.1-4088.4"
- process $proc$ls180.v:4083$571
+ attribute \src "ls180.v:4114.1-4119.4"
+ process $proc$ls180.v:4114$571
assign { } { }
assign $0\main_uart_tx_clear[0:0] 1'0
- attribute \src "ls180.v:4085.2-4087.5"
- switch $and$ls180.v:4085$572_Y
- attribute \src "ls180.v:4085.6-4085.79"
+ attribute \src "ls180.v:4116.2-4118.5"
+ switch $and$ls180.v:4116$572_Y
+ attribute \src "ls180.v:4116.6-4116.79"
case 1'1
assign $0\main_uart_tx_clear[0:0] 1'1
case
sync always
update \main_uart_tx_clear $0\main_uart_tx_clear[0:0]
end
- attribute \src "ls180.v:4089.1-4093.4"
- process $proc$ls180.v:4089$573
+ attribute \src "ls180.v:4120.1-4124.4"
+ process $proc$ls180.v:4120$573
assign { } { }
assign { } { }
assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status
sync always
update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0]
end
- attribute \src "ls180.v:4094.1-4099.4"
- process $proc$ls180.v:4094$574
+ attribute \src "ls180.v:4125.1-4130.4"
+ process $proc$ls180.v:4125$574
assign { } { }
assign $0\main_uart_rx_clear[0:0] 1'0
- attribute \src "ls180.v:4096.2-4098.5"
- switch $and$ls180.v:4096$575_Y
- attribute \src "ls180.v:4096.6-4096.79"
+ attribute \src "ls180.v:4127.2-4129.5"
+ switch $and$ls180.v:4127$575_Y
+ attribute \src "ls180.v:4127.6-4127.79"
case 1'1
assign $0\main_uart_rx_clear[0:0] 1'1
case
sync always
update \main_uart_rx_clear $0\main_uart_rx_clear[0:0]
end
- attribute \src "ls180.v:4100.1-4104.4"
- process $proc$ls180.v:4100$576
+ attribute \src "ls180.v:4131.1-4135.4"
+ process $proc$ls180.v:4131$576
assign { } { }
assign { } { }
assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending
sync always
update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0]
end
- attribute \src "ls180.v:4122.1-4129.4"
- process $proc$ls180.v:4122$584
+ attribute \src "ls180.v:4153.1-4160.4"
+ process $proc$ls180.v:4153$584
assign { } { }
assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000
- attribute \src "ls180.v:4124.2-4128.5"
+ attribute \src "ls180.v:4155.2-4159.5"
switch \main_uart_tx_fifo_replace
- attribute \src "ls180.v:4124.6-4124.31"
+ attribute \src "ls180.v:4155.6-4155.31"
case 1'1
- assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4125$585_Y
- attribute \src "ls180.v:4126.6-4126.10"
+ assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4156$585_Y
+ attribute \src "ls180.v:4157.6-4157.10"
case
assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce
end
sync always
update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0]
end
- attribute \src "ls180.v:4152.1-4159.4"
- process $proc$ls180.v:4152$595
+ attribute \src "ls180.v:4183.1-4190.4"
+ process $proc$ls180.v:4183$595
assign { } { }
assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000
- attribute \src "ls180.v:4154.2-4158.5"
+ attribute \src "ls180.v:4185.2-4189.5"
switch \main_uart_rx_fifo_replace
- attribute \src "ls180.v:4154.6-4154.31"
+ attribute \src "ls180.v:4185.6-4185.31"
case 1'1
- assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4155$596_Y
- attribute \src "ls180.v:4156.6-4156.10"
+ assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4186$596_Y
+ attribute \src "ls180.v:4187.6-4187.10"
case
assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce
end
sync always
update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0]
end
- attribute \src "ls180.v:416.11-416.68"
- process $proc$ls180.v:416$2911
- assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000
- sync always
- sync init
- update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
- end
- attribute \src "ls180.v:417.5-417.64"
- process $proc$ls180.v:417$2912
- assign { } { }
- assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0
- sync always
- update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
- sync init
- end
- attribute \src "ls180.v:418.11-418.70"
- process $proc$ls180.v:418$2913
+ attribute \src "ls180.v:4213.1-4261.4"
+ process $proc$ls180.v:4213$606
assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000
- sync always
- sync init
- update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
- end
- attribute \src "ls180.v:4182.1-4230.4"
- process $proc$ls180.v:4182$606
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\main_spi_master_done0[0:0] 1'0
+ assign $0\main_spi_master_miso_latch[0:0] 1'0
+ assign $0\main_spi_master_irq[0:0] 1'0
assign { } { }
assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000
- assign $0\main_spi_master_miso_latch[0:0] 1'0
+ assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0
assign $0\main_spi_master_clk_enable[0:0] 1'0
- assign $0\main_spi_master_irq[0:0] 1'0
assign $0\main_spi_master_cs_enable[0:0] 1'0
- assign { } { }
assign $0\main_spi_master_mosi_latch[0:0] 1'0
- assign $0\main_spi_master_done0[0:0] 1'0
- assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0
assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state
- attribute \src "ls180.v:4193.2-4229.9"
+ attribute \src "ls180.v:4224.2-4260.9"
switch \builder_spimaster0_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000
assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4197.4-4200.7"
+ attribute \src "ls180.v:4228.4-4231.7"
switch \main_spi_master_clk_fall
- attribute \src "ls180.v:4197.8-4197.32"
+ attribute \src "ls180.v:4228.8-4228.32"
case 1'1
assign $0\main_spi_master_cs_enable[0:0] 1'1
assign $0\builder_spimaster0_next_state[1:0] 2'10
case 2'10
assign $0\main_spi_master_clk_enable[0:0] 1'1
assign $0\main_spi_master_cs_enable[0:0] 1'1
- attribute \src "ls180.v:4205.4-4211.7"
+ attribute \src "ls180.v:4236.4-4242.7"
switch \main_spi_master_clk_fall
- attribute \src "ls180.v:4205.8-4205.32"
+ attribute \src "ls180.v:4236.8-4236.32"
case 1'1
- assign $0\main_spi_master_count_spimaster0_next_value[2:0] $add$ls180.v:4206$607_Y
+ assign $0\main_spi_master_count_spimaster0_next_value[2:0] $add$ls180.v:4237$607_Y
assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4208.5-4210.8"
- switch $eq$ls180.v:4208$609_Y
- attribute \src "ls180.v:4208.9-4208.68"
+ attribute \src "ls180.v:4239.5-4241.8"
+ switch $eq$ls180.v:4239$609_Y
+ attribute \src "ls180.v:4239.9-4239.68"
case 1'1
assign $0\builder_spimaster0_next_state[1:0] 2'11
case
attribute \src "ls180.v:0.0-0.0"
case 2'11
assign $0\main_spi_master_cs_enable[0:0] 1'1
- attribute \src "ls180.v:4215.4-4219.7"
+ attribute \src "ls180.v:4246.4-4250.7"
switch \main_spi_master_clk_rise
- attribute \src "ls180.v:4215.8-4215.32"
+ attribute \src "ls180.v:4246.8-4246.32"
case 1'1
assign $0\main_spi_master_miso_latch[0:0] 1'1
assign $0\main_spi_master_irq[0:0] 1'1
attribute \src "ls180.v:0.0-0.0"
case
assign $0\main_spi_master_done0[0:0] 1'1
- attribute \src "ls180.v:4223.4-4227.7"
+ attribute \src "ls180.v:4254.4-4258.7"
switch \main_spi_master_start0
- attribute \src "ls180.v:4223.8-4223.30"
+ attribute \src "ls180.v:4254.8-4254.30"
case 1'1
assign $0\main_spi_master_done0[0:0] 1'0
assign $0\main_spi_master_mosi_latch[0:0] 1'1
update \main_spi_master_count_spimaster0_next_value $0\main_spi_master_count_spimaster0_next_value[2:0]
update \main_spi_master_count_spimaster0_next_value_ce $0\main_spi_master_count_spimaster0_next_value_ce[0:0]
end
- attribute \src "ls180.v:419.11-419.70"
- process $proc$ls180.v:419$2914
+ attribute \src "ls180.v:424.11-424.68"
+ process $proc$ls180.v:424$2921
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
+ end
+ attribute \src "ls180.v:425.5-425.64"
+ process $proc$ls180.v:425$2922
+ assign { } { }
+ assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0
+ sync always
+ update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:426.11-426.70"
+ process $proc$ls180.v:426$2923
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
+ end
+ attribute \src "ls180.v:427.11-427.70"
+ process $proc$ls180.v:427$2924
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
end
- attribute \src "ls180.v:420.11-420.73"
- process $proc$ls180.v:420$2915
+ attribute \src "ls180.v:428.11-428.73"
+ process $proc$ls180.v:428$2925
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:4258.1-4286.4"
- process $proc$ls180.v:4258$631
+ attribute \src "ls180.v:4293.1-4321.4"
+ process $proc$ls180.v:4293$631
assign { } { }
assign $0\main_sdphy_clocker_clk1[0:0] 1'0
- attribute \src "ls180.v:4260.2-4285.9"
+ attribute \src "ls180.v:4295.2-4320.9"
switch \main_sdphy_clocker_storage
attribute \src "ls180.v:0.0-0.0"
case 9'000000100
sync always
update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0]
end
- attribute \src "ls180.v:4288.1-4321.4"
- process $proc$ls180.v:4288$634
+ attribute \src "ls180.v:4323.1-4356.4"
+ process $proc$ls180.v:4323$634
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
- assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
- assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
assign { } { }
assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0
assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0
assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
+ assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
+ assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
+ assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state
- attribute \src "ls180.v:4298.2-4320.9"
+ attribute \src "ls180.v:4333.2-4355.9"
switch \builder_sdphy_sdphyinit_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1
assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1
assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111
- attribute \src "ls180.v:4305.4-4311.7"
+ attribute \src "ls180.v:4340.4-4346.7"
switch \main_sdphy_init_pads_out_ready
- attribute \src "ls180.v:4305.8-4305.38"
+ attribute \src "ls180.v:4340.8-4340.38"
case 1'1
- assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4306$635_Y
+ assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4341$635_Y
assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4308.5-4310.8"
- switch $eq$ls180.v:4308$636_Y
- attribute \src "ls180.v:4308.9-4308.41"
+ attribute \src "ls180.v:4343.5-4345.8"
+ switch $eq$ls180.v:4343$636_Y
+ attribute \src "ls180.v:4343.9-4343.41"
case 1'1
assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0
case
case
assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4316.4-4318.7"
+ attribute \src "ls180.v:4351.4-4353.7"
switch \main_sdphy_init_initialize_re
- attribute \src "ls180.v:4316.8-4316.37"
+ attribute \src "ls180.v:4351.8-4351.37"
case 1'1
assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1
case
update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
end
- attribute \src "ls180.v:4322.1-4398.4"
- process $proc$ls180.v:4322$637
+ attribute \src "ls180.v:4357.1-4433.4"
+ process $proc$ls180.v:4357$637
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
+ assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
+ assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
assign { } { }
assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0
assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
assign $0\main_sdphy_cmdw_done[0:0] 1'0
- assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
- assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
- assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state
- attribute \src "ls180.v:4332.2-4397.9"
+ attribute \src "ls180.v:4367.2-4432.9"
switch \builder_sdphy_sdphycmdw_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1
- attribute \src "ls180.v:4336.4-4361.11"
+ attribute \src "ls180.v:4371.4-4396.11"
switch \main_sdphy_cmdw_count
attribute \src "ls180.v:0.0-0.0"
case 8'00000000
assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0]
case
end
- attribute \src "ls180.v:4362.4-4373.7"
+ attribute \src "ls180.v:4397.4-4408.7"
switch \main_sdphy_cmdw_pads_out_ready
- attribute \src "ls180.v:4362.8-4362.38"
+ attribute \src "ls180.v:4397.8-4397.38"
case 1'1
- assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4363$638_Y
+ assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4398$638_Y
assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4365.5-4372.8"
- switch $eq$ls180.v:4365$639_Y
- attribute \src "ls180.v:4365.9-4365.40"
+ attribute \src "ls180.v:4400.5-4407.8"
+ switch $eq$ls180.v:4400$639_Y
+ attribute \src "ls180.v:4400.9-4400.40"
case 1'1
- attribute \src "ls180.v:4366.6-4371.9"
+ attribute \src "ls180.v:4401.6-4406.9"
switch \main_sdphy_cmdw_sink_last
- attribute \src "ls180.v:4366.10-4366.35"
+ attribute \src "ls180.v:4401.10-4401.35"
case 1'1
assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10
- attribute \src "ls180.v:4368.10-4368.14"
+ attribute \src "ls180.v:4403.10-4403.14"
case
assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1
assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1
assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1
- attribute \src "ls180.v:4379.4-4386.7"
+ attribute \src "ls180.v:4414.4-4421.7"
switch \main_sdphy_cmdw_pads_out_ready
- attribute \src "ls180.v:4379.8-4379.38"
+ attribute \src "ls180.v:4414.8-4414.38"
case 1'1
- assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4380$640_Y
+ assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4415$640_Y
assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4382.5-4385.8"
- switch $eq$ls180.v:4382$641_Y
- attribute \src "ls180.v:4382.9-4382.40"
+ attribute \src "ls180.v:4417.5-4420.8"
+ switch $eq$ls180.v:4417$641_Y
+ attribute \src "ls180.v:4417.9-4417.40"
case 1'1
assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1
assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
case
assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4391.4-4395.7"
- switch $and$ls180.v:4391$642_Y
- attribute \src "ls180.v:4391.8-4391.69"
+ attribute \src "ls180.v:4426.4-4430.7"
+ switch $and$ls180.v:4426$642_Y
+ attribute \src "ls180.v:4426.8-4426.69"
case 1'1
assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01
- attribute \src "ls180.v:4393.8-4393.12"
+ attribute \src "ls180.v:4428.8-4428.12"
case
assign $0\main_sdphy_cmdw_done[0:0] 1'1
end
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
end
- attribute \src "ls180.v:441.5-441.59"
- process $proc$ls180.v:441$2916
- assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
- end
- attribute \src "ls180.v:443.5-443.59"
- process $proc$ls180.v:443$2917
- assign { } { }
- assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
- end
- attribute \src "ls180.v:4432.1-4525.4"
- process $proc$ls180.v:4432$651
+ attribute \src "ls180.v:4467.1-4560.4"
+ process $proc$ls180.v:4467$651
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
+ assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000
+ assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
+ assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0
+ assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0
assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0
assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0
assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0
assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0
+ assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0
assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0
assign { } { }
assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
- assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0
assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0
assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0
- assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0
assign $0\main_sdphy_cmdr_source_last[0:0] 1'0
- assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
- assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000
- assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
- assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state
- attribute \src "ls180.v:4450.2-4524.9"
+ attribute \src "ls180.v:4485.2-4559.9"
switch \builder_sdphy_sdphycmdr_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1
- assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4458$652_Y
+ assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4493$652_Y
assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1
- attribute \src "ls180.v:4455.4-4457.7"
+ attribute \src "ls180.v:4490.4-4492.7"
switch \main_sdphy_cmdr_cmdr_source_source_valid0
- attribute \src "ls180.v:4455.8-4455.49"
+ attribute \src "ls180.v:4490.8-4490.49"
case 1'1
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:4460.4-4463.7"
- switch $eq$ls180.v:4460$653_Y
- attribute \src "ls180.v:4460.8-4460.41"
+ attribute \src "ls180.v:4495.4-4498.7"
+ switch $eq$ls180.v:4495$653_Y
+ attribute \src "ls180.v:4495.8-4495.41"
case 1'1
assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100
assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0
assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000
- assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4469$655_Y
+ assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4504$655_Y
assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0
- assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4486$658_Y
+ assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4521$658_Y
assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1
- attribute \src "ls180.v:4471.4-4485.7"
- switch $and$ls180.v:4471$656_Y
- attribute \src "ls180.v:4471.8-4471.69"
+ attribute \src "ls180.v:4506.4-4520.7"
+ switch $and$ls180.v:4506$656_Y
+ attribute \src "ls180.v:4506.8-4506.69"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1
- assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4473$657_Y
+ assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4508$657_Y
assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
- attribute \src "ls180.v:4475.5-4484.8"
+ attribute \src "ls180.v:4510.5-4519.8"
switch \main_sdphy_cmdr_source_last
- attribute \src "ls180.v:4475.9-4475.36"
+ attribute \src "ls180.v:4510.9-4510.36"
case 1'1
assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1
- attribute \src "ls180.v:4477.6-4483.9"
+ attribute \src "ls180.v:4512.6-4518.9"
switch \main_sdphy_cmdr_sink_last
- attribute \src "ls180.v:4477.10-4477.35"
+ attribute \src "ls180.v:4512.10-4512.35"
case 1'1
assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011
- attribute \src "ls180.v:4481.10-4481.14"
+ attribute \src "ls180.v:4516.10-4516.14"
case
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
end
end
case
end
- attribute \src "ls180.v:4488.4-4491.7"
- switch $eq$ls180.v:4488$659_Y
- attribute \src "ls180.v:4488.8-4488.41"
+ attribute \src "ls180.v:4523.4-4526.7"
+ switch $eq$ls180.v:4523$659_Y
+ attribute \src "ls180.v:4523.8-4523.41"
case 1'1
assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100
assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1
assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1
- attribute \src "ls180.v:4497.4-4503.7"
+ attribute \src "ls180.v:4532.4-4538.7"
switch \main_sdphy_cmdr_pads_out_ready
- attribute \src "ls180.v:4497.8-4497.38"
+ attribute \src "ls180.v:4532.8-4532.38"
case 1'1
- assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4498$660_Y
+ assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4533$660_Y
assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
- attribute \src "ls180.v:4500.5-4502.8"
- switch $eq$ls180.v:4500$661_Y
- attribute \src "ls180.v:4500.9-4500.40"
+ attribute \src "ls180.v:4535.5-4537.8"
+ switch $eq$ls180.v:4535$661_Y
+ attribute \src "ls180.v:4535.9-4535.40"
case 1'1
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
case
assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1
assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001
assign $0\main_sdphy_cmdr_source_last[0:0] 1'1
- attribute \src "ls180.v:4509.4-4511.7"
- switch $and$ls180.v:4509$662_Y
- attribute \src "ls180.v:4509.8-4509.69"
+ attribute \src "ls180.v:4544.4-4546.7"
+ switch $and$ls180.v:4544$662_Y
+ attribute \src "ls180.v:4544.8-4544.69"
case 1'1
assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
case
assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000
assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1
- attribute \src "ls180.v:4518.4-4522.7"
- switch $and$ls180.v:4518$664_Y
- attribute \src "ls180.v:4518.8-4518.94"
+ attribute \src "ls180.v:4553.4-4557.7"
+ switch $and$ls180.v:4553$664_Y
+ attribute \src "ls180.v:4553.8-4553.94"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1
assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1
update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
end
- attribute \src "ls180.v:444.5-444.58"
- process $proc$ls180.v:444$2918
+ attribute \src "ls180.v:449.5-449.59"
+ process $proc$ls180.v:449$2926
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
+ end
+ attribute \src "ls180.v:451.5-451.59"
+ process $proc$ls180.v:451$2927
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
+ end
+ attribute \src "ls180.v:452.5-452.58"
+ process $proc$ls180.v:452$2928
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
end
- attribute \src "ls180.v:445.5-445.64"
- process $proc$ls180.v:445$2919
+ attribute \src "ls180.v:453.5-453.64"
+ process $proc$ls180.v:453$2929
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
end
- attribute \src "ls180.v:446.12-446.74"
- process $proc$ls180.v:446$2920
+ attribute \src "ls180.v:454.12-454.74"
+ process $proc$ls180.v:454$2930
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
sync init
update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
end
- attribute \src "ls180.v:447.12-447.47"
- process $proc$ls180.v:447$2921
+ attribute \src "ls180.v:455.12-455.47"
+ process $proc$ls180.v:455$2931
assign { } { }
assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000
sync always
sync init
update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0]
end
- attribute \src "ls180.v:448.5-448.46"
- process $proc$ls180.v:448$2922
+ attribute \src "ls180.v:456.5-456.46"
+ process $proc$ls180.v:456$2932
assign { } { }
assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0]
end
- attribute \src "ls180.v:450.5-450.44"
- process $proc$ls180.v:450$2923
+ attribute \src "ls180.v:458.5-458.44"
+ process $proc$ls180.v:458$2933
assign { } { }
assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0]
end
- attribute \src "ls180.v:451.5-451.45"
- process $proc$ls180.v:451$2924
+ attribute \src "ls180.v:459.5-459.45"
+ process $proc$ls180.v:459$2934
assign { } { }
assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0]
end
- attribute \src "ls180.v:452.5-452.54"
- process $proc$ls180.v:452$2925
- assign { } { }
- assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
- end
- attribute \src "ls180.v:454.32-454.76"
- process $proc$ls180.v:454$2926
- assign { } { }
- assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
- end
- attribute \src "ls180.v:455.11-455.55"
- process $proc$ls180.v:455$2927
- assign { } { }
- assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000
- sync always
- sync init
- update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0]
- end
- attribute \src "ls180.v:4559.1-4586.4"
- process $proc$ls180.v:4559$672
+ attribute \src "ls180.v:4594.1-4621.4"
+ process $proc$ls180.v:4594$672
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\main_sdphy_dataw_valid[0:0] 1'0
assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
assign { } { }
+ assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
assign $0\main_sdphy_dataw_error[0:0] 1'0
assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0
- assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
- assign $0\main_sdphy_dataw_valid[0:0] 1'0
assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state
- attribute \src "ls180.v:4567.2-4585.9"
+ attribute \src "ls180.v:4602.2-4620.9"
switch \builder_sdphy_sdphycrcr_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1
assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1
- attribute \src "ls180.v:4572.4-4576.7"
+ attribute \src "ls180.v:4607.4-4611.7"
switch \main_sdphy_dataw_crcr_source_source_valid0
- attribute \src "ls180.v:4572.8-4572.50"
+ attribute \src "ls180.v:4607.8-4607.50"
case 1'1
- assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4573$673_Y
- assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4574$674_Y
+ assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4608$673_Y
+ assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4609$674_Y
assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0
case
end
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:4579.4-4583.7"
+ attribute \src "ls180.v:4614.4-4618.7"
switch \main_sdphy_dataw_start
- attribute \src "ls180.v:4579.8-4579.30"
+ attribute \src "ls180.v:4614.8-4614.30"
case 1'1
assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1
assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1
update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
end
- attribute \src "ls180.v:457.32-457.75"
- process $proc$ls180.v:457$2928
+ attribute \src "ls180.v:460.5-460.54"
+ process $proc$ls180.v:460$2935
assign { } { }
- assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1
+ assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
sync always
- update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0]
sync init
+ update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:4587.1-4659.4"
- process $proc$ls180.v:4587$675
+ attribute \src "ls180.v:462.32-462.76"
+ process $proc$ls180.v:462$2936
+ assign { } { }
+ assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
+ end
+ attribute \src "ls180.v:4622.1-4694.4"
+ process $proc$ls180.v:4622$675
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
assign { } { }
assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0
assign $0\main_sdphy_dataw_start[0:0] 1'0
assign $0\main_sdphy_dataw_stop[0:0] 1'0
+ assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state
- attribute \src "ls180.v:4598.2-4658.9"
+ attribute \src "ls180.v:4633.2-4693.9"
switch \builder_sdphy_fsm_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1
assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
- attribute \src "ls180.v:4603.4-4605.7"
+ attribute \src "ls180.v:4638.4-4640.7"
switch \main_sdphy_dataw_pads_out_ready
- attribute \src "ls180.v:4603.8-4603.39"
+ attribute \src "ls180.v:4638.8-4638.39"
case 1'1
assign $0\builder_sdphy_fsm_next_state[2:0] 3'010
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'010
- assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4608$676_Y
+ assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4643$676_Y
assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1
- attribute \src "ls180.v:4611.4-4618.11"
+ attribute \src "ls180.v:4646.4-4653.11"
switch \main_sdphy_dataw_count
attribute \src "ls180.v:0.0-0.0"
case 8'00000000
assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0]
case
end
- attribute \src "ls180.v:4619.4-4631.7"
+ attribute \src "ls180.v:4654.4-4666.7"
switch \main_sdphy_dataw_pads_out_ready
- attribute \src "ls180.v:4619.8-4619.39"
+ attribute \src "ls180.v:4654.8-4654.39"
case 1'1
- assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4620$677_Y
+ assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4655$677_Y
assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4622.5-4630.8"
- switch $eq$ls180.v:4622$678_Y
- attribute \src "ls180.v:4622.9-4622.41"
+ attribute \src "ls180.v:4657.5-4665.8"
+ switch $eq$ls180.v:4657$678_Y
+ attribute \src "ls180.v:4657.9-4657.41"
case 1'1
assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4625.6-4629.9"
+ attribute \src "ls180.v:4660.6-4664.9"
switch \main_sdphy_dataw_sink_last
- attribute \src "ls180.v:4625.10-4625.36"
+ attribute \src "ls180.v:4660.10-4660.36"
case 1'1
assign $0\builder_sdphy_fsm_next_state[2:0] 3'011
- attribute \src "ls180.v:4627.10-4627.14"
+ attribute \src "ls180.v:4662.10-4662.14"
case
assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1
end
assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1
assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111
- attribute \src "ls180.v:4637.4-4640.7"
+ attribute \src "ls180.v:4672.4-4675.7"
switch \main_sdphy_dataw_pads_out_ready
- attribute \src "ls180.v:4637.8-4637.39"
+ attribute \src "ls180.v:4672.8-4672.39"
case 1'1
assign $0\main_sdphy_dataw_start[0:0] 1'1
assign $0\builder_sdphy_fsm_next_state[2:0] 3'100
attribute \src "ls180.v:0.0-0.0"
case 3'100
assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
- attribute \src "ls180.v:4644.4-4649.7"
+ attribute \src "ls180.v:4679.4-4684.7"
switch \main_sdphy_dataw_pads_out_ready
- attribute \src "ls180.v:4644.8-4644.39"
+ attribute \src "ls180.v:4679.8-4679.39"
case 1'1
- attribute \src "ls180.v:4645.5-4648.8"
+ attribute \src "ls180.v:4680.5-4683.8"
switch \main_sdphy_dataw_pads_in_payload_data_i [0]
- attribute \src "ls180.v:4645.9-4645.51"
+ attribute \src "ls180.v:4680.9-4680.51"
case 1'1
assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1
assign $0\builder_sdphy_fsm_next_state[2:0] 3'000
case
assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:4654.4-4656.7"
- switch $and$ls180.v:4654$679_Y
- attribute \src "ls180.v:4654.8-4654.71"
+ attribute \src "ls180.v:4689.4-4691.7"
+ switch $and$ls180.v:4689$679_Y
+ attribute \src "ls180.v:4689.8-4689.71"
case 1'1
assign $0\builder_sdphy_fsm_next_state[2:0] 3'001
case
update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
end
- attribute \src "ls180.v:459.32-459.76"
- process $proc$ls180.v:459$2929
- assign { } { }
- assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1
- sync always
- update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0]
- sync init
- end
- attribute \src "ls180.v:465.5-465.51"
- process $proc$ls180.v:465$2930
+ attribute \src "ls180.v:463.11-463.55"
+ process $proc$ls180.v:463$2937
assign { } { }
- assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
+ assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000
sync always
sync init
- update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0]
+ update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0]
end
- attribute \src "ls180.v:466.5-466.51"
- process $proc$ls180.v:466$2931
+ attribute \src "ls180.v:465.32-465.75"
+ process $proc$ls180.v:465$2938
assign { } { }
- assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
+ assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1
sync always
+ update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0]
sync init
- update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0]
end
- attribute \src "ls180.v:468.5-468.47"
- process $proc$ls180.v:468$2932
+ attribute \src "ls180.v:467.32-467.76"
+ process $proc$ls180.v:467$2939
assign { } { }
- assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0]
- end
- attribute \src "ls180.v:469.5-469.45"
- process $proc$ls180.v:469$2933
- assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
+ assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1
sync always
+ update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0]
sync init
- update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0]
end
- attribute \src "ls180.v:4693.1-4794.4"
- process $proc$ls180.v:4693$687
+ attribute \src "ls180.v:4728.1-4829.4"
+ process $proc$ls180.v:4728$687
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\main_sdphy_datar_source_last[0:0] 1'0
- assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
- assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000
- assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000
- assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0
- assign $0\main_sdphy_datar_stop[0:0] 1'0
assign { } { }
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
assign $0\main_sdphy_datar_sink_ready[0:0] 1'0
assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0
assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0
+ assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0
assign $0\main_sdphy_datar_source_valid[0:0] 1'0
assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0
+ assign $0\main_sdphy_datar_source_last[0:0] 1'0
+ assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
+ assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000
+ assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000
+ assign $0\main_sdphy_datar_stop[0:0] 1'0
assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state
- attribute \src "ls180.v:4710.2-4793.9"
+ attribute \src "ls180.v:4745.2-4828.9"
switch \builder_sdphy_sdphydatar_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1
assign { } { }
assign { } { }
- assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4720$689_Y
+ assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4755$689_Y
assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1
- attribute \src "ls180.v:4717.4-4719.7"
+ attribute \src "ls180.v:4752.4-4754.7"
switch \main_sdphy_datar_datar_source_source_valid0
- attribute \src "ls180.v:4717.8-4717.51"
+ attribute \src "ls180.v:4752.8-4752.51"
case 1'1
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:4722.4-4725.7"
- switch $eq$ls180.v:4722$690_Y
- attribute \src "ls180.v:4722.8-4722.42"
+ attribute \src "ls180.v:4757.4-4760.7"
+ switch $eq$ls180.v:4757$690_Y
+ attribute \src "ls180.v:4757.8-4757.42"
case 1'1
assign $0\main_sdphy_datar_sink_ready[0:0] 1'1
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100
assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1
assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0
assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000
- assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4731$693_Y
+ assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4766$693_Y
assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0
- assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4752$695_Y
+ assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4787$695_Y
assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1
- attribute \src "ls180.v:4733.4-4751.7"
+ attribute \src "ls180.v:4768.4-4786.7"
switch \main_sdphy_datar_source_valid
- attribute \src "ls180.v:4733.8-4733.37"
+ attribute \src "ls180.v:4768.8-4768.37"
case 1'1
- attribute \src "ls180.v:4734.5-4750.8"
+ attribute \src "ls180.v:4769.5-4785.8"
switch \main_sdphy_datar_source_ready
- attribute \src "ls180.v:4734.9-4734.38"
+ attribute \src "ls180.v:4769.9-4769.38"
case 1'1
assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1
- assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4736$694_Y
+ assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4771$694_Y
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
- attribute \src "ls180.v:4738.6-4747.9"
+ attribute \src "ls180.v:4773.6-4782.9"
switch \main_sdphy_datar_source_last
- attribute \src "ls180.v:4738.10-4738.38"
+ attribute \src "ls180.v:4773.10-4773.38"
case 1'1
assign $0\main_sdphy_datar_sink_ready[0:0] 1'1
- attribute \src "ls180.v:4740.7-4746.10"
+ attribute \src "ls180.v:4775.7-4781.10"
switch \main_sdphy_datar_sink_last
- attribute \src "ls180.v:4740.11-4740.37"
+ attribute \src "ls180.v:4775.11-4775.37"
case 1'1
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011
- attribute \src "ls180.v:4744.11-4744.15"
+ attribute \src "ls180.v:4779.11-4779.15"
case
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000
end
case
end
- attribute \src "ls180.v:4748.9-4748.13"
+ attribute \src "ls180.v:4783.9-4783.13"
case
assign $0\main_sdphy_datar_stop[0:0] 1'1
end
case
end
- attribute \src "ls180.v:4754.4-4757.7"
- switch $eq$ls180.v:4754$696_Y
- attribute \src "ls180.v:4754.8-4754.42"
+ attribute \src "ls180.v:4789.4-4792.7"
+ switch $eq$ls180.v:4789$696_Y
+ attribute \src "ls180.v:4789.8-4789.42"
case 1'1
assign $0\main_sdphy_datar_sink_ready[0:0] 1'1
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100
attribute \src "ls180.v:0.0-0.0"
case 3'011
assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1
- attribute \src "ls180.v:4761.4-4767.7"
+ attribute \src "ls180.v:4796.4-4802.7"
switch \main_sdphy_datar_pads_out_ready
- attribute \src "ls180.v:4761.8-4761.39"
+ attribute \src "ls180.v:4796.8-4796.39"
case 1'1
- assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4762$697_Y
+ assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4797$697_Y
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
- attribute \src "ls180.v:4764.5-4766.8"
- switch $eq$ls180.v:4764$698_Y
- attribute \src "ls180.v:4764.9-4764.42"
+ attribute \src "ls180.v:4799.5-4801.8"
+ switch $eq$ls180.v:4799$698_Y
+ attribute \src "ls180.v:4799.9-4799.42"
case 1'1
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000
case
assign $0\main_sdphy_datar_source_valid[0:0] 1'1
assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001
assign $0\main_sdphy_datar_source_last[0:0] 1'1
- attribute \src "ls180.v:4773.4-4775.7"
- switch $and$ls180.v:4773$699_Y
- attribute \src "ls180.v:4773.8-4773.71"
+ attribute \src "ls180.v:4808.4-4810.7"
+ switch $and$ls180.v:4808$699_Y
+ attribute \src "ls180.v:4808.8-4808.71"
case 1'1
assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000
case
case
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
- attribute \src "ls180.v:4780.4-4791.7"
- switch $and$ls180.v:4780$700_Y
- attribute \src "ls180.v:4780.8-4780.71"
+ attribute \src "ls180.v:4815.4-4826.7"
+ switch $and$ls180.v:4815$700_Y
+ attribute \src "ls180.v:4815.8-4815.71"
case 1'1
assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1
- attribute \src "ls180.v:4782.5-4790.8"
+ attribute \src "ls180.v:4817.5-4825.8"
switch \main_sdphy_datar_pads_out_ready
- attribute \src "ls180.v:4782.9-4782.40"
+ attribute \src "ls180.v:4817.9-4817.40"
case 1'1
assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000
assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
end
- attribute \src "ls180.v:470.5-470.45"
- process $proc$ls180.v:470$2934
+ attribute \src "ls180.v:473.5-473.51"
+ process $proc$ls180.v:473$2940
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0]
+ end
+ attribute \src "ls180.v:474.5-474.51"
+ process $proc$ls180.v:474$2941
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0]
+ end
+ attribute \src "ls180.v:476.5-476.47"
+ process $proc$ls180.v:476$2942
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0]
+ end
+ attribute \src "ls180.v:477.5-477.45"
+ process $proc$ls180.v:477$2943
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0]
+ end
+ attribute \src "ls180.v:478.5-478.45"
+ process $proc$ls180.v:478$2944
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0]
end
- attribute \src "ls180.v:471.12-471.57"
- process $proc$ls180.v:471$2935
+ attribute \src "ls180.v:479.12-479.57"
+ process $proc$ls180.v:479$2945
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
sync always
sync init
update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:473.5-473.51"
- process $proc$ls180.v:473$2936
+ attribute \src "ls180.v:481.5-481.51"
+ process $proc$ls180.v:481$2946
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:474.5-474.51"
- process $proc$ls180.v:474$2937
+ attribute \src "ls180.v:482.5-482.51"
+ process $proc$ls180.v:482$2947
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:475.5-475.50"
- process $proc$ls180.v:475$2938
+ attribute \src "ls180.v:483.5-483.50"
+ process $proc$ls180.v:483$2948
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:476.5-476.54"
- process $proc$ls180.v:476$2939
+ attribute \src "ls180.v:484.5-484.54"
+ process $proc$ls180.v:484$2949
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
end
- attribute \src "ls180.v:477.5-477.55"
- process $proc$ls180.v:477$2940
+ attribute \src "ls180.v:485.5-485.55"
+ process $proc$ls180.v:485$2950
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
end
- attribute \src "ls180.v:478.5-478.56"
- process $proc$ls180.v:478$2941
+ attribute \src "ls180.v:486.5-486.56"
+ process $proc$ls180.v:486$2951
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
end
- attribute \src "ls180.v:479.5-479.50"
- process $proc$ls180.v:479$2942
+ attribute \src "ls180.v:487.5-487.50"
+ process $proc$ls180.v:487$2952
assign { } { }
assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0]
end
- attribute \src "ls180.v:482.5-482.67"
- process $proc$ls180.v:482$2943
- assign { } { }
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0
- sync always
- update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
- sync init
- end
- attribute \src "ls180.v:483.5-483.66"
- process $proc$ls180.v:483$2944
- assign { } { }
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0
- sync always
- update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
- sync init
- end
- attribute \src "ls180.v:4852.1-4859.4"
- process $proc$ls180.v:4852$822
+ attribute \src "ls180.v:4887.1-4894.4"
+ process $proc$ls180.v:4887$822
assign { } { }
assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000
- attribute \src "ls180.v:4854.2-4858.5"
+ attribute \src "ls180.v:4889.2-4893.5"
switch \main_sdcore_crc7_inserter_enable
- attribute \src "ls180.v:4854.6-4854.38"
+ attribute \src "ls180.v:4889.6-4889.38"
case 1'1
assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40
- attribute \src "ls180.v:4856.6-4856.10"
+ attribute \src "ls180.v:4891.6-4891.10"
case
assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0
end
sync always
update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0]
end
- attribute \src "ls180.v:4874.1-4881.4"
- process $proc$ls180.v:4874$845
+ attribute \src "ls180.v:490.5-490.67"
+ process $proc$ls180.v:490$2953
+ assign { } { }
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0
+ sync always
+ update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:4909.1-4916.4"
+ process $proc$ls180.v:4909$845
assign { } { }
assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:4876.2-4880.5"
+ attribute \src "ls180.v:4911.2-4915.5"
switch \main_sdcore_crc16_inserter_crc0_enable
- attribute \src "ls180.v:4876.6-4876.44"
+ attribute \src "ls180.v:4911.6-4911.44"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2
- attribute \src "ls180.v:4878.6-4878.10"
+ attribute \src "ls180.v:4913.6-4913.10"
case
assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0
end
sync always
update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0]
end
- attribute \src "ls180.v:4884.1-4891.4"
- process $proc$ls180.v:4884$856
+ attribute \src "ls180.v:491.5-491.66"
+ process $proc$ls180.v:491$2954
+ assign { } { }
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0
+ sync always
+ update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:4919.1-4926.4"
+ process $proc$ls180.v:4919$856
assign { } { }
assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:4886.2-4890.5"
+ attribute \src "ls180.v:4921.2-4925.5"
switch \main_sdcore_crc16_inserter_crc1_enable
- attribute \src "ls180.v:4886.6-4886.44"
+ attribute \src "ls180.v:4921.6-4921.44"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2
- attribute \src "ls180.v:4888.6-4888.10"
+ attribute \src "ls180.v:4923.6-4923.10"
case
assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0
end
sync always
update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0]
end
- attribute \src "ls180.v:4894.1-4901.4"
- process $proc$ls180.v:4894$867
+ attribute \src "ls180.v:4929.1-4936.4"
+ process $proc$ls180.v:4929$867
assign { } { }
assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:4896.2-4900.5"
+ attribute \src "ls180.v:4931.2-4935.5"
switch \main_sdcore_crc16_inserter_crc2_enable
- attribute \src "ls180.v:4896.6-4896.44"
+ attribute \src "ls180.v:4931.6-4931.44"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2
- attribute \src "ls180.v:4898.6-4898.10"
+ attribute \src "ls180.v:4933.6-4933.10"
case
assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0
end
sync always
update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0]
end
- attribute \src "ls180.v:49.5-49.42"
- process $proc$ls180.v:49$2765
- assign { } { }
- assign $1\main_libresocsim_reset_storage[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0]
- end
- attribute \src "ls180.v:4904.1-4911.4"
- process $proc$ls180.v:4904$878
+ attribute \src "ls180.v:4939.1-4946.4"
+ process $proc$ls180.v:4939$878
assign { } { }
assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:4906.2-4910.5"
+ attribute \src "ls180.v:4941.2-4945.5"
switch \main_sdcore_crc16_inserter_crc3_enable
- attribute \src "ls180.v:4906.6-4906.44"
+ attribute \src "ls180.v:4941.6-4941.44"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2
- attribute \src "ls180.v:4908.6-4908.10"
+ attribute \src "ls180.v:4943.6-4943.10"
case
assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0
end
sync always
update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0]
end
- attribute \src "ls180.v:4912.1-4991.4"
- process $proc$ls180.v:4912$879
+ attribute \src "ls180.v:4947.1-5026.4"
+ process $proc$ls180.v:4947$879
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { } { }
- assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000
- assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
- assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
- assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
- assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
- assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0
+ assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0
+ assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000
+ assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
+ assign { } { }
+ assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000
+ assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
+ assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state
- attribute \src "ls180.v:4929.2-4990.9"
+ attribute \src "ls180.v:4964.2-5025.9"
switch \builder_sdcore_crcupstreaminserter_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1
- attribute \src "ls180.v:4933.4-4935.7"
- switch $eq$ls180.v:4933$880_Y
- attribute \src "ls180.v:4933.8-4933.48"
+ attribute \src "ls180.v:4968.4-4970.7"
+ switch $eq$ls180.v:4968$880_Y
+ attribute \src "ls180.v:4968.8-4968.48"
case 1'1
assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1
case
end
- attribute \src "ls180.v:4936.4-4961.11"
+ attribute \src "ls180.v:4971.4-4996.11"
switch \main_sdcore_crc16_inserter_cnt
attribute \src "ls180.v:0.0-0.0"
case 3'000
assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] }
case
end
- attribute \src "ls180.v:4962.4-4969.7"
+ attribute \src "ls180.v:4997.4-5004.7"
switch \main_sdcore_crc16_inserter_source_ready
- attribute \src "ls180.v:4962.8-4962.47"
+ attribute \src "ls180.v:4997.8-4997.47"
case 1'1
- attribute \src "ls180.v:4963.5-4968.8"
- switch $eq$ls180.v:4963$881_Y
- attribute \src "ls180.v:4963.9-4963.49"
+ attribute \src "ls180.v:4998.5-5003.8"
+ switch $eq$ls180.v:4998$881_Y
+ attribute \src "ls180.v:4998.9-4998.49"
case 1'1
assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0
- attribute \src "ls180.v:4965.9-4965.13"
+ attribute \src "ls180.v:5000.9-5000.13"
case
- assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:4966$882_Y
+ assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5001$882_Y
assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1
end
case
assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1
assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc
assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1
- attribute \src "ls180.v:4984.4-4988.7"
- switch $and$ls180.v:4984$884_Y
- attribute \src "ls180.v:4984.8-4984.128"
+ attribute \src "ls180.v:5019.4-5023.7"
+ switch $and$ls180.v:5019$884_Y
+ attribute \src "ls180.v:5019.8-5019.128"
case 1'1
assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1
assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
end
- attribute \src "ls180.v:498.11-498.68"
- process $proc$ls180.v:498$2945
- assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000
- sync always
- sync init
- update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
- end
- attribute \src "ls180.v:499.5-499.64"
- process $proc$ls180.v:499$2946
- assign { } { }
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0
- sync always
- update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
- sync init
- end
- attribute \src "ls180.v:4992.1-4997.4"
- process $proc$ls180.v:4992$885
+ attribute \src "ls180.v:5027.1-5032.4"
+ process $proc$ls180.v:5027$885
assign { } { }
assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0
- attribute \src "ls180.v:4994.2-4996.5"
- switch $and$ls180.v:4994$892_Y
- attribute \src "ls180.v:4994.6-4994.301"
+ attribute \src "ls180.v:5029.2-5031.5"
+ switch $and$ls180.v:5029$892_Y
+ attribute \src "ls180.v:5029.6-5029.301"
case 1'1
assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1
case
sync always
update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0]
end
- attribute \src "ls180.v:50.5-50.37"
- process $proc$ls180.v:50$2766
- assign { } { }
- assign $1\main_libresocsim_reset_re[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0]
- end
- attribute \src "ls180.v:500.11-500.70"
- process $proc$ls180.v:500$2947
- assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000
- sync always
- sync init
- update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
- end
- attribute \src "ls180.v:5000.1-5007.4"
- process $proc$ls180.v:5000$894
+ attribute \src "ls180.v:5035.1-5042.4"
+ process $proc$ls180.v:5035$894
assign { } { }
assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
- attribute \src "ls180.v:5002.2-5006.5"
- switch $eq$ls180.v:5002$895_Y
- attribute \src "ls180.v:5002.6-5002.45"
+ attribute \src "ls180.v:5037.2-5041.5"
+ switch $eq$ls180.v:5037$895_Y
+ attribute \src "ls180.v:5037.6-5037.45"
case 1'1
assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1
- attribute \src "ls180.v:5004.6-5004.10"
+ attribute \src "ls180.v:5039.6-5039.10"
case
assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
end
sync always
update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0]
end
- attribute \src "ls180.v:501.11-501.70"
- process $proc$ls180.v:501$2948
- assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000
- sync always
- sync init
- update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
- end
- attribute \src "ls180.v:5010.1-5017.4"
- process $proc$ls180.v:5010$897
+ attribute \src "ls180.v:5045.1-5052.4"
+ process $proc$ls180.v:5045$897
assign { } { }
assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
- attribute \src "ls180.v:5012.2-5016.5"
- switch $eq$ls180.v:5012$898_Y
- attribute \src "ls180.v:5012.6-5012.45"
+ attribute \src "ls180.v:5047.2-5051.5"
+ switch $eq$ls180.v:5047$898_Y
+ attribute \src "ls180.v:5047.6-5047.45"
case 1'1
assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1
- attribute \src "ls180.v:5014.6-5014.10"
+ attribute \src "ls180.v:5049.6-5049.10"
case
assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
end
sync always
update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0]
end
- attribute \src "ls180.v:502.11-502.73"
- process $proc$ls180.v:502$2949
- assign { } { }
- assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- sync always
- sync init
- update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
- end
- attribute \src "ls180.v:5020.1-5027.4"
- process $proc$ls180.v:5020$900
+ attribute \src "ls180.v:5055.1-5062.4"
+ process $proc$ls180.v:5055$900
assign { } { }
assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
- attribute \src "ls180.v:5022.2-5026.5"
- switch $eq$ls180.v:5022$901_Y
- attribute \src "ls180.v:5022.6-5022.45"
+ attribute \src "ls180.v:5057.2-5061.5"
+ switch $eq$ls180.v:5057$901_Y
+ attribute \src "ls180.v:5057.6-5057.45"
case 1'1
assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1
- attribute \src "ls180.v:5024.6-5024.10"
+ attribute \src "ls180.v:5059.6-5059.10"
case
assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
end
sync always
update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0]
end
- attribute \src "ls180.v:5030.1-5037.4"
- process $proc$ls180.v:5030$903
+ attribute \src "ls180.v:506.11-506.68"
+ process $proc$ls180.v:506$2955
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
+ end
+ attribute \src "ls180.v:5065.1-5072.4"
+ process $proc$ls180.v:5065$903
assign { } { }
assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
- attribute \src "ls180.v:5032.2-5036.5"
- switch $eq$ls180.v:5032$904_Y
- attribute \src "ls180.v:5032.6-5032.45"
+ attribute \src "ls180.v:5067.2-5071.5"
+ switch $eq$ls180.v:5067$904_Y
+ attribute \src "ls180.v:5067.6-5067.45"
case 1'1
assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1
- attribute \src "ls180.v:5034.6-5034.10"
+ attribute \src "ls180.v:5069.6-5069.10"
case
assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
end
sync always
update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0]
end
- attribute \src "ls180.v:5039.1-5044.4"
- process $proc$ls180.v:5039$905
+ attribute \src "ls180.v:507.5-507.64"
+ process $proc$ls180.v:507$2956
+ assign { } { }
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0
+ sync always
+ update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:5074.1-5079.4"
+ process $proc$ls180.v:5074$905
assign { } { }
assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0
- attribute \src "ls180.v:5041.2-5043.5"
- switch $and$ls180.v:5041$907_Y
- attribute \src "ls180.v:5041.6-5041.85"
+ attribute \src "ls180.v:5076.2-5078.5"
+ switch $and$ls180.v:5076$907_Y
+ attribute \src "ls180.v:5076.6-5076.85"
case 1'1
assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1
case
sync always
update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0]
end
- attribute \src "ls180.v:5045.1-5052.4"
- process $proc$ls180.v:5045$908
+ attribute \src "ls180.v:508.11-508.70"
+ process $proc$ls180.v:508$2957
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
+ end
+ attribute \src "ls180.v:5080.1-5087.4"
+ process $proc$ls180.v:5080$908
assign { } { }
assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0
- attribute \src "ls180.v:5047.2-5051.5"
- switch $lt$ls180.v:5047$909_Y
- attribute \src "ls180.v:5047.6-5047.44"
+ attribute \src "ls180.v:5082.2-5086.5"
+ switch $lt$ls180.v:5082$909_Y
+ attribute \src "ls180.v:5082.6-5082.44"
case 1'1
assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1
- attribute \src "ls180.v:5049.6-5049.10"
+ attribute \src "ls180.v:5084.6-5084.10"
case
assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready
end
sync always
update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0]
end
- attribute \src "ls180.v:5056.1-5063.4"
- process $proc$ls180.v:5056$920
+ attribute \src "ls180.v:509.11-509.70"
+ process $proc$ls180.v:509$2958
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
+ end
+ attribute \src "ls180.v:5091.1-5098.4"
+ process $proc$ls180.v:5091$920
assign { } { }
assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:5058.2-5062.5"
+ attribute \src "ls180.v:5093.2-5097.5"
switch \main_sdcore_crc16_checker_crc0_enable
- attribute \src "ls180.v:5058.6-5058.43"
+ attribute \src "ls180.v:5093.6-5093.43"
case 1'1
assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2
- attribute \src "ls180.v:5060.6-5060.10"
+ attribute \src "ls180.v:5095.6-5095.10"
case
assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0
end
sync always
update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0]
end
- attribute \src "ls180.v:5066.1-5073.4"
- process $proc$ls180.v:5066$931
+ attribute \src "ls180.v:510.11-510.73"
+ process $proc$ls180.v:510$2959
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
+ end
+ attribute \src "ls180.v:5101.1-5108.4"
+ process $proc$ls180.v:5101$931
assign { } { }
assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:5068.2-5072.5"
+ attribute \src "ls180.v:5103.2-5107.5"
switch \main_sdcore_crc16_checker_crc1_enable
- attribute \src "ls180.v:5068.6-5068.43"
+ attribute \src "ls180.v:5103.6-5103.43"
case 1'1
assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2
- attribute \src "ls180.v:5070.6-5070.10"
+ attribute \src "ls180.v:5105.6-5105.10"
case
assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0
end
sync always
update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0]
end
- attribute \src "ls180.v:5076.1-5083.4"
- process $proc$ls180.v:5076$942
+ attribute \src "ls180.v:5111.1-5118.4"
+ process $proc$ls180.v:5111$942
assign { } { }
assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:5078.2-5082.5"
+ attribute \src "ls180.v:5113.2-5117.5"
switch \main_sdcore_crc16_checker_crc2_enable
- attribute \src "ls180.v:5078.6-5078.43"
+ attribute \src "ls180.v:5113.6-5113.43"
case 1'1
assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2
- attribute \src "ls180.v:5080.6-5080.10"
+ attribute \src "ls180.v:5115.6-5115.10"
case
assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0
end
sync always
update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0]
end
- attribute \src "ls180.v:5086.1-5093.4"
- process $proc$ls180.v:5086$953
+ attribute \src "ls180.v:5121.1-5128.4"
+ process $proc$ls180.v:5121$953
assign { } { }
assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000
- attribute \src "ls180.v:5088.2-5092.5"
+ attribute \src "ls180.v:5123.2-5127.5"
switch \main_sdcore_crc16_checker_crc3_enable
- attribute \src "ls180.v:5088.6-5088.43"
+ attribute \src "ls180.v:5123.6-5123.43"
case 1'1
assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2
- attribute \src "ls180.v:5090.6-5090.10"
+ attribute \src "ls180.v:5125.6-5125.10"
case
assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0
end
sync always
update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0]
end
- attribute \src "ls180.v:5094.1-5284.4"
- process $proc$ls180.v:5094$954
+ attribute \src "ls180.v:5129.1-5319.4"
+ process $proc$ls180.v:5129$954
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign { } { }
+ assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
+ assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
+ assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0
assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0
assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000
assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0
- assign { } { }
- assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
- assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
- assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state
- attribute \src "ls180.v:5135.2-5283.9"
+ attribute \src "ls180.v:5170.2-5318.9"
switch \builder_sdcore_fsm_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1
- attribute \src "ls180.v:5138.4-5158.11"
+ attribute \src "ls180.v:5173.4-5193.11"
switch \main_sdcore_cmd_count
attribute \src "ls180.v:0.0-0.0"
case 3'000
attribute \src "ls180.v:0.0-0.0"
case 3'101
assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 }
- assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5156$955_Y
+ assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5191$955_Y
case
end
- attribute \src "ls180.v:5159.4-5171.7"
- switch $and$ls180.v:5159$956_Y
- attribute \src "ls180.v:5159.8-5159.65"
+ attribute \src "ls180.v:5194.4-5206.7"
+ switch $and$ls180.v:5194$956_Y
+ attribute \src "ls180.v:5194.8-5194.65"
case 1'1
- assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5160$957_Y
+ assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5195$957_Y
assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1
- attribute \src "ls180.v:5162.5-5170.8"
- switch $eq$ls180.v:5162$958_Y
- attribute \src "ls180.v:5162.9-5162.40"
+ attribute \src "ls180.v:5197.5-5205.8"
+ switch $eq$ls180.v:5197$958_Y
+ attribute \src "ls180.v:5197.9-5197.40"
case 1'1
- attribute \src "ls180.v:5163.6-5169.9"
- switch $eq$ls180.v:5163$959_Y
- attribute \src "ls180.v:5163.10-5163.40"
+ attribute \src "ls180.v:5198.6-5204.9"
+ switch $eq$ls180.v:5198$959_Y
+ attribute \src "ls180.v:5198.10-5198.40"
case 1'1
assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1
assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1
assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
- attribute \src "ls180.v:5167.10-5167.14"
+ attribute \src "ls180.v:5202.10-5202.14"
case
assign $0\builder_sdcore_fsm_next_state[2:0] 3'010
end
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1
- assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5175$960_Y
+ assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5210$960_Y
assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1
- attribute \src "ls180.v:5176.4-5180.7"
- switch $eq$ls180.v:5176$961_Y
- attribute \src "ls180.v:5176.8-5176.38"
+ attribute \src "ls180.v:5211.4-5215.7"
+ switch $eq$ls180.v:5211$961_Y
+ attribute \src "ls180.v:5211.8-5211.38"
case 1'1
assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001
- attribute \src "ls180.v:5178.8-5178.12"
+ attribute \src "ls180.v:5213.8-5213.12"
case
assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110
end
- attribute \src "ls180.v:5182.4-5203.7"
+ attribute \src "ls180.v:5217.4-5238.7"
switch \main_sdphy_cmdr_source_valid
- attribute \src "ls180.v:5182.8-5182.36"
+ attribute \src "ls180.v:5217.8-5217.36"
case 1'1
- attribute \src "ls180.v:5183.5-5202.8"
- switch $eq$ls180.v:5183$962_Y
- attribute \src "ls180.v:5183.9-5183.56"
+ attribute \src "ls180.v:5218.5-5237.8"
+ switch $eq$ls180.v:5218$962_Y
+ attribute \src "ls180.v:5218.9-5218.56"
case 1'1
assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1
assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1
assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
- attribute \src "ls180.v:5187.9-5187.13"
+ attribute \src "ls180.v:5222.9-5222.13"
case
- attribute \src "ls180.v:5188.6-5201.9"
+ attribute \src "ls180.v:5223.6-5236.9"
switch \main_sdphy_cmdr_source_last
- attribute \src "ls180.v:5188.10-5188.37"
+ attribute \src "ls180.v:5223.10-5223.37"
case 1'1
- attribute \src "ls180.v:5189.7-5197.10"
- switch $eq$ls180.v:5189$963_Y
- attribute \src "ls180.v:5189.11-5189.42"
+ attribute \src "ls180.v:5224.7-5232.10"
+ switch $eq$ls180.v:5224$963_Y
+ attribute \src "ls180.v:5224.11-5224.42"
case 1'1
assign $0\builder_sdcore_fsm_next_state[2:0] 3'011
- attribute \src "ls180.v:5191.11-5191.15"
+ attribute \src "ls180.v:5226.11-5226.15"
case
- attribute \src "ls180.v:5192.8-5196.11"
- switch $eq$ls180.v:5192$964_Y
- attribute \src "ls180.v:5192.12-5192.43"
+ attribute \src "ls180.v:5227.8-5231.11"
+ switch $eq$ls180.v:5227$964_Y
+ attribute \src "ls180.v:5227.12-5227.43"
case 1'1
assign $0\builder_sdcore_fsm_next_state[2:0] 3'100
- attribute \src "ls180.v:5194.12-5194.16"
+ attribute \src "ls180.v:5229.12-5229.16"
case
assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
end
end
- attribute \src "ls180.v:5198.10-5198.14"
+ attribute \src "ls180.v:5233.10-5233.14"
case
assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data }
assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1
assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last
assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data
assign $0\main_sdphy_datar_source_ready[0:0] 1'1
- attribute \src "ls180.v:5211.4-5217.7"
- switch $and$ls180.v:5211$966_Y
- attribute \src "ls180.v:5211.8-5211.98"
+ attribute \src "ls180.v:5246.4-5252.7"
+ switch $and$ls180.v:5246$966_Y
+ attribute \src "ls180.v:5246.8-5246.98"
case 1'1
- assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5212$967_Y
+ assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5247$967_Y
assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1
- attribute \src "ls180.v:5214.5-5216.8"
- switch $eq$ls180.v:5214$969_Y
- attribute \src "ls180.v:5214.9-5214.77"
+ attribute \src "ls180.v:5249.5-5251.8"
+ switch $eq$ls180.v:5249$969_Y
+ attribute \src "ls180.v:5249.9-5249.77"
case 1'1
assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
case
end
case
end
- attribute \src "ls180.v:5219.4-5224.7"
+ attribute \src "ls180.v:5254.4-5259.7"
switch \main_sdphy_datar_source_valid
- attribute \src "ls180.v:5219.8-5219.37"
+ attribute \src "ls180.v:5254.8-5254.37"
case 1'1
- attribute \src "ls180.v:5220.5-5223.8"
- switch $ne$ls180.v:5220$970_Y
- attribute \src "ls180.v:5220.9-5220.57"
+ attribute \src "ls180.v:5255.5-5258.8"
+ switch $ne$ls180.v:5255$970_Y
+ attribute \src "ls180.v:5255.9-5255.57"
case 1'1
assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1
assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1
case 3'100
assign $0\main_sdphy_datar_sink_valid[0:0] 1'1
assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage
- assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5229$972_Y
- attribute \src "ls180.v:5230.4-5256.7"
+ assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5264$972_Y
+ attribute \src "ls180.v:5265.4-5291.7"
switch \main_sdphy_datar_source_valid
- attribute \src "ls180.v:5230.8-5230.37"
+ attribute \src "ls180.v:5265.8-5265.37"
case 1'1
- attribute \src "ls180.v:5231.5-5255.8"
- switch $eq$ls180.v:5231$973_Y
- attribute \src "ls180.v:5231.9-5231.57"
+ attribute \src "ls180.v:5266.5-5290.8"
+ switch $eq$ls180.v:5266$973_Y
+ attribute \src "ls180.v:5266.9-5266.57"
case 1'1
assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid
assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready
assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first
assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last
assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data
- attribute \src "ls180.v:5237.6-5245.9"
- switch $and$ls180.v:5237$974_Y
- attribute \src "ls180.v:5237.10-5237.72"
+ attribute \src "ls180.v:5272.6-5280.9"
+ switch $and$ls180.v:5272$974_Y
+ attribute \src "ls180.v:5272.10-5272.72"
case 1'1
- assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5238$975_Y
+ assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5273$975_Y
assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1
- attribute \src "ls180.v:5240.7-5244.10"
- switch $eq$ls180.v:5240$977_Y
- attribute \src "ls180.v:5240.11-5240.79"
+ attribute \src "ls180.v:5275.7-5279.10"
+ switch $eq$ls180.v:5275$977_Y
+ attribute \src "ls180.v:5275.11-5275.79"
case 1'1
assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
- attribute \src "ls180.v:5242.11-5242.15"
+ attribute \src "ls180.v:5277.11-5277.15"
case
assign $0\builder_sdcore_fsm_next_state[2:0] 3'100
end
case
end
- attribute \src "ls180.v:5246.9-5246.13"
+ attribute \src "ls180.v:5281.9-5281.13"
case
- attribute \src "ls180.v:5247.6-5254.9"
- switch $eq$ls180.v:5247$978_Y
- attribute \src "ls180.v:5247.10-5247.58"
+ attribute \src "ls180.v:5282.6-5289.9"
+ switch $eq$ls180.v:5282$978_Y
+ attribute \src "ls180.v:5282.10-5282.58"
case 1'1
assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1
assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1
assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1
assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1
- attribute \src "ls180.v:5267.4-5281.7"
+ attribute \src "ls180.v:5302.4-5316.7"
switch \main_sdcore_cmd_send_re
- attribute \src "ls180.v:5267.8-5267.31"
+ attribute \src "ls180.v:5302.8-5302.31"
case 1'1
assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1
update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
end
- attribute \src "ls180.v:51.12-51.60"
- process $proc$ls180.v:51$2767
- assign { } { }
- assign $1\main_libresocsim_scratch_storage[31:0] 305419896
- sync always
- sync init
- update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0]
- end
- attribute \src "ls180.v:52.5-52.39"
- process $proc$ls180.v:52$2768
- assign { } { }
- assign $1\main_libresocsim_scratch_re[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0]
- end
- attribute \src "ls180.v:523.5-523.59"
- process $proc$ls180.v:523$2950
+ attribute \src "ls180.v:531.5-531.59"
+ process $proc$ls180.v:531$2960
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
end
- attribute \src "ls180.v:525.5-525.59"
- process $proc$ls180.v:525$2951
+ attribute \src "ls180.v:533.5-533.59"
+ process $proc$ls180.v:533$2961
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
end
- attribute \src "ls180.v:526.5-526.58"
- process $proc$ls180.v:526$2952
+ attribute \src "ls180.v:534.5-534.58"
+ process $proc$ls180.v:534$2962
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
end
- attribute \src "ls180.v:527.5-527.64"
- process $proc$ls180.v:527$2953
+ attribute \src "ls180.v:5347.1-5354.4"
+ process $proc$ls180.v:5347$979
+ assign { } { }
+ assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000
+ attribute \src "ls180.v:5349.2-5353.5"
+ switch \main_sdblock2mem_fifo_replace
+ attribute \src "ls180.v:5349.6-5349.35"
+ case 1'1
+ assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5350$980_Y
+ attribute \src "ls180.v:5351.6-5351.10"
+ case
+ assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce
+ end
+ sync always
+ update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0]
+ end
+ attribute \src "ls180.v:535.5-535.64"
+ process $proc$ls180.v:535$2963
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
end
- attribute \src "ls180.v:528.12-528.74"
- process $proc$ls180.v:528$2954
+ attribute \src "ls180.v:536.12-536.74"
+ process $proc$ls180.v:536$2964
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
sync init
update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
end
- attribute \src "ls180.v:529.12-529.47"
- process $proc$ls180.v:529$2955
+ attribute \src "ls180.v:537.12-537.47"
+ process $proc$ls180.v:537$2965
assign { } { }
assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000
sync always
sync init
update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0]
end
- attribute \src "ls180.v:530.5-530.46"
- process $proc$ls180.v:530$2956
+ attribute \src "ls180.v:538.5-538.46"
+ process $proc$ls180.v:538$2966
assign { } { }
assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0]
end
- attribute \src "ls180.v:5312.1-5319.4"
- process $proc$ls180.v:5312$979
- assign { } { }
- assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000
- attribute \src "ls180.v:5314.2-5318.5"
- switch \main_sdblock2mem_fifo_replace
- attribute \src "ls180.v:5314.6-5314.35"
- case 1'1
- assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5315$980_Y
- attribute \src "ls180.v:5316.6-5316.10"
- case
- assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce
- end
- sync always
- update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0]
- end
- attribute \src "ls180.v:532.5-532.44"
- process $proc$ls180.v:532$2957
- assign { } { }
- assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0]
- end
- attribute \src "ls180.v:533.5-533.45"
- process $proc$ls180.v:533$2958
- assign { } { }
- assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0]
- end
- attribute \src "ls180.v:534.5-534.54"
- process $proc$ls180.v:534$2959
- assign { } { }
- assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
- end
- attribute \src "ls180.v:5345.1-5384.4"
- process $proc$ls180.v:5345$990
+ attribute \src "ls180.v:5380.1-5419.4"
+ process $proc$ls180.v:5380$990
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0
- assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0
assign { } { }
assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0
assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0
+ assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0
+ assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state
- attribute \src "ls180.v:5355.2-5383.9"
+ attribute \src "ls180.v:5390.2-5418.9"
switch \builder_sdblock2memdma_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid
assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data
- assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5359$991_Y
+ assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5394$991_Y
assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1
- attribute \src "ls180.v:5361.4-5372.7"
- switch $and$ls180.v:5361$992_Y
- attribute \src "ls180.v:5361.8-5361.103"
+ attribute \src "ls180.v:5396.4-5407.7"
+ switch $and$ls180.v:5396$992_Y
+ attribute \src "ls180.v:5396.8-5396.103"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5362$993_Y
+ assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5397$993_Y
assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:5364.5-5371.8"
- switch $eq$ls180.v:5364$995_Y
- attribute \src "ls180.v:5364.9-5364.106"
+ attribute \src "ls180.v:5399.5-5406.8"
+ switch $eq$ls180.v:5399$995_Y
+ attribute \src "ls180.v:5399.9-5399.106"
case 1'1
- attribute \src "ls180.v:5365.6-5370.9"
+ attribute \src "ls180.v:5400.6-5405.9"
switch \main_sdblock2mem_wishbonedmawriter_loop_storage
- attribute \src "ls180.v:5365.10-5365.57"
+ attribute \src "ls180.v:5400.10-5400.57"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:5368.10-5368.14"
+ attribute \src "ls180.v:5403.10-5403.14"
case
assign $0\builder_sdblock2memdma_next_state[1:0] 2'10
end
update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
end
- attribute \src "ls180.v:536.32-536.76"
- process $proc$ls180.v:536$2960
+ attribute \src "ls180.v:540.5-540.44"
+ process $proc$ls180.v:540$2967
assign { } { }
- assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
+ assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0]
+ update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0]
end
- attribute \src "ls180.v:537.11-537.55"
- process $proc$ls180.v:537$2961
+ attribute \src "ls180.v:541.5-541.45"
+ process $proc$ls180.v:541$2968
assign { } { }
- assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000
+ assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0]
+ update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0]
end
- attribute \src "ls180.v:539.32-539.75"
- process $proc$ls180.v:539$2962
+ attribute \src "ls180.v:542.5-542.54"
+ process $proc$ls180.v:542$2969
assign { } { }
- assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1
+ assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
sync always
- update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0]
sync init
+ update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:5404.1-5441.4"
- process $proc$ls180.v:5404$997
+ attribute \src "ls180.v:5439.1-5476.4"
+ process $proc$ls180.v:5439$997
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\main_interface1_bus_adr[31:0] 0
- assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0
- assign { } { }
- assign $0\main_interface1_bus_sel[3:0] 4'0000
- assign $0\main_interface1_bus_cyc[0:0] 1'0
- assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0
assign $0\main_interface1_bus_stb[0:0] 1'0
assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0
assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0
assign $0\main_interface1_bus_we[0:0] 1'0
assign $0\main_sdmem2block_dma_source_last[0:0] 1'0
assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0
+ assign $0\main_interface1_bus_adr[31:0] 0
+ assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0
+ assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0
+ assign { } { }
+ assign $0\main_interface1_bus_sel[3:0] 4'0000
+ assign $0\main_interface1_bus_cyc[0:0] 1'0
assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state
- attribute \src "ls180.v:5418.2-5440.9"
+ attribute \src "ls180.v:5453.2-5475.9"
switch \builder_sdmem2blockdma_fsm_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1
assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last
assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data
- attribute \src "ls180.v:5423.4-5426.7"
+ attribute \src "ls180.v:5458.4-5461.7"
switch \main_sdmem2block_dma_source_ready
- attribute \src "ls180.v:5423.8-5423.41"
+ attribute \src "ls180.v:5458.8-5458.41"
case 1'1
assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1
assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0
assign $0\main_interface1_bus_we[0:0] 1'0
assign $0\main_interface1_bus_sel[3:0] 4'1111
assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address
- attribute \src "ls180.v:5434.4-5438.7"
- switch $and$ls180.v:5434$998_Y
- attribute \src "ls180.v:5434.8-5434.59"
+ attribute \src "ls180.v:5469.4-5473.7"
+ switch $and$ls180.v:5469$998_Y
+ attribute \src "ls180.v:5469.8-5469.59"
case 1'1
assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] }
assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
end
- attribute \src "ls180.v:541.32-541.76"
- process $proc$ls180.v:541$2963
+ attribute \src "ls180.v:544.32-544.76"
+ process $proc$ls180.v:544$2970
assign { } { }
- assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1
+ assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
sync always
- update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0]
+ sync init
+ update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0]
+ end
+ attribute \src "ls180.v:545.11-545.55"
+ process $proc$ls180.v:545$2971
+ assign { } { }
+ assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000
+ sync always
+ sync init
+ update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0]
+ end
+ attribute \src "ls180.v:547.32-547.75"
+ process $proc$ls180.v:547$2972
+ assign { } { }
+ assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1
+ sync always
+ update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0]
sync init
end
- attribute \src "ls180.v:5442.1-5478.4"
- process $proc$ls180.v:5442$999
+ attribute \src "ls180.v:5477.1-5513.4"
+ process $proc$ls180.v:5477$999
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0
+ assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0
assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0
assign $0\main_sdmem2block_dma_done_status[0:0] 1'0
- assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
- assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0
- assign { } { }
assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0
- assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0
+ assign { } { }
+ assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state
- attribute \src "ls180.v:5451.2-5477.9"
+ attribute \src "ls180.v:5486.2-5512.9"
switch \builder_sdmem2blockdma_resetinserter_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1
- assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5454$1001_Y
- assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5455$1002_Y
- attribute \src "ls180.v:5456.4-5467.7"
+ assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5489$1001_Y
+ assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5490$1002_Y
+ attribute \src "ls180.v:5491.4-5502.7"
switch \main_sdmem2block_dma_sink_ready
- attribute \src "ls180.v:5456.8-5456.39"
+ attribute \src "ls180.v:5491.8-5491.39"
case 1'1
- assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5457$1003_Y
+ assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5492$1003_Y
assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:5459.5-5466.8"
+ attribute \src "ls180.v:5494.5-5501.8"
switch \main_sdmem2block_dma_sink_last
- attribute \src "ls180.v:5459.9-5459.39"
+ attribute \src "ls180.v:5494.9-5494.39"
case 1'1
- attribute \src "ls180.v:5460.6-5465.9"
+ attribute \src "ls180.v:5495.6-5500.9"
switch \main_sdmem2block_dma_loop_storage
- attribute \src "ls180.v:5460.10-5460.43"
+ attribute \src "ls180.v:5495.10-5495.43"
case 1'1
assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:5463.10-5463.14"
+ attribute \src "ls180.v:5498.10-5498.14"
case
assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10
end
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
end
- attribute \src "ls180.v:547.5-547.51"
- process $proc$ls180.v:547$2964
+ attribute \src "ls180.v:549.32-549.76"
+ process $proc$ls180.v:549$2973
assign { } { }
- assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
+ assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1
sync always
+ update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0]
sync init
- update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0]
end
- attribute \src "ls180.v:548.5-548.51"
- process $proc$ls180.v:548$2965
+ attribute \src "ls180.v:55.5-55.42"
+ process $proc$ls180.v:55$2775
assign { } { }
- assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
+ assign $1\main_libresocsim_reset_storage[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0]
+ update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0]
end
- attribute \src "ls180.v:5490.1-5506.4"
- process $proc$ls180.v:5490$1009
+ attribute \src "ls180.v:5525.1-5541.4"
+ process $proc$ls180.v:5525$1009
assign { } { }
assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000
- attribute \src "ls180.v:5492.2-5505.9"
+ attribute \src "ls180.v:5527.2-5540.9"
switch \main_sdmem2block_converter_mux
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0]
end
- attribute \src "ls180.v:550.5-550.47"
- process $proc$ls180.v:550$2966
- assign { } { }
- assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0]
- end
- attribute \src "ls180.v:551.5-551.45"
- process $proc$ls180.v:551$2967
- assign { } { }
- assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0]
- end
- attribute \src "ls180.v:552.5-552.45"
- process $proc$ls180.v:552$2968
+ attribute \src "ls180.v:555.5-555.51"
+ process $proc$ls180.v:555$2974
assign { } { }
- assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0
+ assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0]
+ update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0]
end
- attribute \src "ls180.v:5520.1-5527.4"
- process $proc$ls180.v:5520$1010
+ attribute \src "ls180.v:5555.1-5562.4"
+ process $proc$ls180.v:5555$1010
assign { } { }
assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000
- attribute \src "ls180.v:5522.2-5526.5"
+ attribute \src "ls180.v:5557.2-5561.5"
switch \main_sdmem2block_fifo_replace
- attribute \src "ls180.v:5522.6-5522.35"
+ attribute \src "ls180.v:5557.6-5557.35"
case 1'1
- assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5523$1011_Y
- attribute \src "ls180.v:5524.6-5524.10"
+ assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5558$1011_Y
+ attribute \src "ls180.v:5559.6-5559.10"
case
assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce
end
sync always
update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0]
end
- attribute \src "ls180.v:553.12-553.57"
- process $proc$ls180.v:553$2969
+ attribute \src "ls180.v:556.5-556.51"
+ process $proc$ls180.v:556$2975
assign { } { }
- assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
+ assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0]
+ update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0]
+ end
+ attribute \src "ls180.v:558.5-558.47"
+ process $proc$ls180.v:558$2976
+ assign { } { }
+ assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0]
end
- attribute \src "ls180.v:5545.1-5593.4"
- process $proc$ls180.v:5545$1021
+ attribute \src "ls180.v:5580.1-5628.4"
+ process $proc$ls180.v:5580$1021
assign { } { }
assign { } { }
assign { } { }
assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0
assign $0\libresocsim_mosi_latch[0:0] 1'0
assign $0\libresocsim_done0[0:0] 1'0
- assign $0\libresocsim_irq[0:0] 1'0
assign $0\libresocsim_miso_latch[0:0] 1'0
+ assign $0\libresocsim_irq[0:0] 1'0
assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state
- attribute \src "ls180.v:5556.2-5592.9"
+ attribute \src "ls180.v:5591.2-5627.9"
switch \builder_spimaster1_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000
assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:5560.4-5563.7"
+ attribute \src "ls180.v:5595.4-5598.7"
switch \libresocsim_clk_fall
- attribute \src "ls180.v:5560.8-5560.28"
+ attribute \src "ls180.v:5595.8-5595.28"
case 1'1
assign $0\libresocsim_cs_enable[0:0] 1'1
assign $0\builder_spimaster1_next_state[1:0] 2'10
case 2'10
assign $0\libresocsim_clk_enable[0:0] 1'1
assign $0\libresocsim_cs_enable[0:0] 1'1
- attribute \src "ls180.v:5568.4-5574.7"
+ attribute \src "ls180.v:5603.4-5609.7"
switch \libresocsim_clk_fall
- attribute \src "ls180.v:5568.8-5568.28"
+ attribute \src "ls180.v:5603.8-5603.28"
case 1'1
- assign $0\libresocsim_count_spimaster1_next_value[2:0] $add$ls180.v:5569$1022_Y
+ assign $0\libresocsim_count_spimaster1_next_value[2:0] $add$ls180.v:5604$1022_Y
assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:5571.5-5573.8"
- switch $eq$ls180.v:5571$1024_Y
- attribute \src "ls180.v:5571.9-5571.60"
+ attribute \src "ls180.v:5606.5-5608.8"
+ switch $eq$ls180.v:5606$1024_Y
+ attribute \src "ls180.v:5606.9-5606.60"
case 1'1
assign $0\builder_spimaster1_next_state[1:0] 2'11
case
attribute \src "ls180.v:0.0-0.0"
case 2'11
assign $0\libresocsim_cs_enable[0:0] 1'1
- attribute \src "ls180.v:5578.4-5582.7"
+ attribute \src "ls180.v:5613.4-5617.7"
switch \libresocsim_clk_rise
- attribute \src "ls180.v:5578.8-5578.28"
+ attribute \src "ls180.v:5613.8-5613.28"
case 1'1
assign $0\libresocsim_miso_latch[0:0] 1'1
assign $0\libresocsim_irq[0:0] 1'1
attribute \src "ls180.v:0.0-0.0"
case
assign $0\libresocsim_done0[0:0] 1'1
- attribute \src "ls180.v:5586.4-5590.7"
+ attribute \src "ls180.v:5621.4-5625.7"
switch \libresocsim_start0
- attribute \src "ls180.v:5586.8-5586.26"
+ attribute \src "ls180.v:5621.8-5621.26"
case 1'1
assign $0\libresocsim_done0[0:0] 1'0
assign $0\libresocsim_mosi_latch[0:0] 1'1
update \libresocsim_count_spimaster1_next_value $0\libresocsim_count_spimaster1_next_value[2:0]
update \libresocsim_count_spimaster1_next_value_ce $0\libresocsim_count_spimaster1_next_value_ce[0:0]
end
- attribute \src "ls180.v:555.5-555.51"
- process $proc$ls180.v:555$2970
- assign { } { }
- assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0]
- end
- attribute \src "ls180.v:556.5-556.51"
- process $proc$ls180.v:556$2971
+ attribute \src "ls180.v:559.5-559.45"
+ process $proc$ls180.v:559$2977
assign { } { }
- assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
+ assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0]
+ update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0]
end
- attribute \src "ls180.v:557.5-557.50"
- process $proc$ls180.v:557$2972
+ attribute \src "ls180.v:56.5-56.37"
+ process $proc$ls180.v:56$2776
assign { } { }
- assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
+ assign $1\main_libresocsim_reset_re[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0]
+ update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0]
end
- attribute \src "ls180.v:558.5-558.54"
- process $proc$ls180.v:558$2973
+ attribute \src "ls180.v:560.5-560.45"
+ process $proc$ls180.v:560$2978
assign { } { }
- assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
+ assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
+ update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0]
end
- attribute \src "ls180.v:559.5-559.55"
- process $proc$ls180.v:559$2974
+ attribute \src "ls180.v:561.12-561.57"
+ process $proc$ls180.v:561$2979
assign { } { }
- assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
+ assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
sync always
sync init
- update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
+ update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:5594.1-5630.4"
- process $proc$ls180.v:5594$1025
+ attribute \src "ls180.v:5629.1-5665.4"
+ process $proc$ls180.v:5629$1025
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\builder_libresocsim_we_next_value2[0:0] 1'0
+ assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0
+ assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0
+ assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0
assign { } { }
assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000
assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0
assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000
assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
- assign $0\builder_libresocsim_we_next_value2[0:0] 1'0
- assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0
- assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0
- assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0
assign $0\builder_next_state[1:0] \builder_state
- attribute \src "ls180.v:5605.2-5629.9"
+ attribute \src "ls180.v:5640.2-5664.9"
switch \builder_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
case
assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0]
assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1
- attribute \src "ls180.v:5621.4-5627.7"
- switch $and$ls180.v:5621$1026_Y
- attribute \src "ls180.v:5621.8-5621.77"
+ attribute \src "ls180.v:5656.4-5662.7"
+ switch $and$ls180.v:5656$1026_Y
+ attribute \src "ls180.v:5656.8-5656.77"
case 1'1
assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0]
assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1
- assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5624$1028_Y
+ assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5659$1028_Y
assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1
assign $0\builder_next_state[1:0] 2'01
case
update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0]
update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0]
end
- attribute \src "ls180.v:560.5-560.56"
- process $proc$ls180.v:560$2975
+ attribute \src "ls180.v:563.5-563.51"
+ process $proc$ls180.v:563$2980
+ assign { } { }
+ assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0]
+ end
+ attribute \src "ls180.v:564.5-564.51"
+ process $proc$ls180.v:564$2981
+ assign { } { }
+ assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0]
+ end
+ attribute \src "ls180.v:565.5-565.50"
+ process $proc$ls180.v:565$2982
+ assign { } { }
+ assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0]
+ end
+ attribute \src "ls180.v:566.5-566.54"
+ process $proc$ls180.v:566$2983
+ assign { } { }
+ assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
+ end
+ attribute \src "ls180.v:567.5-567.55"
+ process $proc$ls180.v:567$2984
+ assign { } { }
+ assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
+ end
+ attribute \src "ls180.v:568.5-568.56"
+ process $proc$ls180.v:568$2985
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
end
- attribute \src "ls180.v:561.5-561.50"
- process $proc$ls180.v:561$2976
+ attribute \src "ls180.v:569.5-569.50"
+ process $proc$ls180.v:569$2986
assign { } { }
assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0]
end
- attribute \src "ls180.v:564.5-564.67"
- process $proc$ls180.v:564$2977
+ attribute \src "ls180.v:5690.1-5697.4"
+ process $proc$ls180.v:5690$1049
assign { } { }
- assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0
+ assign { } { }
+ assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5692$1050_Y
+ assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5693$1051_Y
+ assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5694$1052_Y
+ assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5695$1053_Y
+ assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5696$1054_Y
sync always
- update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0]
- sync init
+ update \builder_slave_sel $0\builder_slave_sel[4:0]
end
- attribute \src "ls180.v:565.5-565.66"
- process $proc$ls180.v:565$2978
+ attribute \src "ls180.v:57.12-57.60"
+ process $proc$ls180.v:57$2777
assign { } { }
- assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0
+ assign $1\main_libresocsim_scratch_storage[31:0] 305419896
sync always
- update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
sync init
+ update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0]
end
- attribute \src "ls180.v:5655.1-5662.4"
- process $proc$ls180.v:5655$1049
- assign { } { }
+ attribute \src "ls180.v:572.5-572.67"
+ process $proc$ls180.v:572$2987
assign { } { }
- assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5657$1050_Y
- assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5658$1051_Y
- assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5659$1052_Y
- assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5660$1053_Y
- assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5661$1054_Y
+ assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
- update \builder_slave_sel $0\builder_slave_sel[4:0]
+ update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0]
+ sync init
end
- attribute \src "ls180.v:57.12-57.47"
- process $proc$ls180.v:57$2769
+ attribute \src "ls180.v:573.5-573.66"
+ process $proc$ls180.v:573$2988
assign { } { }
- assign $1\main_libresocsim_bus_errors[31:0] 0
+ assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
+ update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
sync init
- update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0]
end
- attribute \src "ls180.v:5705.1-5716.4"
- process $proc$ls180.v:5705$1067
+ attribute \src "ls180.v:5740.1-5751.4"
+ process $proc$ls180.v:5740$1067
assign { } { }
assign { } { }
assign { } { }
- assign $0\builder_error[0:0] 1'0
assign { } { }
assign { } { }
- assign $0\builder_shared_ack[0:0] $or$ls180.v:5709$1071_Y
- assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5710$1080_Y
- attribute \src "ls180.v:5711.2-5715.5"
+ assign $0\builder_error[0:0] 1'0
+ assign $0\builder_shared_ack[0:0] $or$ls180.v:5744$1071_Y
+ assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5745$1080_Y
+ attribute \src "ls180.v:5746.2-5750.5"
switch \builder_done
- attribute \src "ls180.v:5711.6-5711.18"
+ attribute \src "ls180.v:5746.6-5746.18"
case 1'1
assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111
assign $0\builder_shared_ack[0:0] 1'1
update \builder_shared_ack $0\builder_shared_ack[0:0]
update \builder_error $0\builder_error[0:0]
end
- attribute \src "ls180.v:580.11-580.68"
- process $proc$ls180.v:580$2979
+ attribute \src "ls180.v:58.5-58.39"
+ process $proc$ls180.v:58$2778
+ assign { } { }
+ assign $1\main_libresocsim_scratch_re[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0]
+ end
+ attribute \src "ls180.v:588.11-588.68"
+ process $proc$ls180.v:588$2989
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
end
- attribute \src "ls180.v:581.5-581.64"
- process $proc$ls180.v:581$2980
+ attribute \src "ls180.v:589.5-589.64"
+ process $proc$ls180.v:589$2990
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
sync init
end
- attribute \src "ls180.v:582.11-582.70"
- process $proc$ls180.v:582$2981
+ attribute \src "ls180.v:590.11-590.70"
+ process $proc$ls180.v:590$2991
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
end
- attribute \src "ls180.v:583.11-583.70"
- process $proc$ls180.v:583$2982
+ attribute \src "ls180.v:591.11-591.70"
+ process $proc$ls180.v:591$2992
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
end
- attribute \src "ls180.v:584.11-584.73"
- process $proc$ls180.v:584$2983
+ attribute \src "ls180.v:592.11-592.73"
+ process $proc$ls180.v:592$2993
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:59.12-59.55"
- process $proc$ls180.v:59$2770
- assign { } { }
- assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000
- sync always
- sync init
- update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0]
- end
- attribute \src "ls180.v:605.5-605.59"
- process $proc$ls180.v:605$2984
+ attribute \src "ls180.v:613.5-613.59"
+ process $proc$ls180.v:613$2994
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
end
- attribute \src "ls180.v:607.5-607.59"
- process $proc$ls180.v:607$2985
+ attribute \src "ls180.v:615.5-615.59"
+ process $proc$ls180.v:615$2995
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
end
- attribute \src "ls180.v:608.5-608.58"
- process $proc$ls180.v:608$2986
+ attribute \src "ls180.v:616.5-616.58"
+ process $proc$ls180.v:616$2996
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
end
- attribute \src "ls180.v:609.5-609.64"
- process $proc$ls180.v:609$2987
+ attribute \src "ls180.v:617.5-617.64"
+ process $proc$ls180.v:617$2997
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
end
- attribute \src "ls180.v:610.12-610.74"
- process $proc$ls180.v:610$2988
+ attribute \src "ls180.v:618.12-618.74"
+ process $proc$ls180.v:618$2998
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
sync init
update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
end
- attribute \src "ls180.v:611.12-611.47"
- process $proc$ls180.v:611$2989
+ attribute \src "ls180.v:619.12-619.47"
+ process $proc$ls180.v:619$2999
assign { } { }
assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000
sync always
sync init
update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0]
end
- attribute \src "ls180.v:612.5-612.46"
- process $proc$ls180.v:612$2990
+ attribute \src "ls180.v:620.5-620.46"
+ process $proc$ls180.v:620$3000
assign { } { }
assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0]
end
- attribute \src "ls180.v:614.5-614.44"
- process $proc$ls180.v:614$2991
+ attribute \src "ls180.v:622.5-622.44"
+ process $proc$ls180.v:622$3001
assign { } { }
assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0]
end
- attribute \src "ls180.v:615.5-615.45"
- process $proc$ls180.v:615$2992
+ attribute \src "ls180.v:623.5-623.45"
+ process $proc$ls180.v:623$3002
assign { } { }
assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0]
end
- attribute \src "ls180.v:616.5-616.54"
- process $proc$ls180.v:616$2993
+ attribute \src "ls180.v:624.5-624.54"
+ process $proc$ls180.v:624$3003
assign { } { }
assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:618.32-618.76"
- process $proc$ls180.v:618$2994
+ attribute \src "ls180.v:626.32-626.76"
+ process $proc$ls180.v:626$3004
assign { } { }
assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0]
end
- attribute \src "ls180.v:619.11-619.55"
- process $proc$ls180.v:619$2995
+ attribute \src "ls180.v:6265.1-6270.4"
+ process $proc$ls180.v:6265$1954
+ assign { } { }
+ assign $0\main_spi_master_start1[0:0] 1'0
+ attribute \src "ls180.v:6267.2-6269.5"
+ switch \main_spi_master_control_re
+ attribute \src "ls180.v:6267.6-6267.32"
+ case 1'1
+ assign $0\main_spi_master_start1[0:0] \main_spi_master_control_storage [0]
+ case
+ end
+ sync always
+ update \main_spi_master_start1 $0\main_spi_master_start1[0:0]
+ end
+ attribute \src "ls180.v:627.11-627.55"
+ process $proc$ls180.v:627$3005
assign { } { }
assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000
sync always
sync init
update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0]
end
- attribute \src "ls180.v:621.32-621.75"
- process $proc$ls180.v:621$2996
+ attribute \src "ls180.v:629.32-629.75"
+ process $proc$ls180.v:629$3006
assign { } { }
assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1
sync always
update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0]
sync init
end
- attribute \src "ls180.v:6216.1-6221.4"
- process $proc$ls180.v:6216$1939
+ attribute \src "ls180.v:63.12-63.47"
+ process $proc$ls180.v:63$2779
assign { } { }
- assign $0\main_spi_master_start1[0:0] 1'0
- attribute \src "ls180.v:6218.2-6220.5"
- switch \main_spi_master_control_re
- attribute \src "ls180.v:6218.6-6218.32"
- case 1'1
- assign $0\main_spi_master_start1[0:0] \main_spi_master_control_storage [0]
- case
- end
+ assign $1\main_libresocsim_bus_errors[31:0] 0
sync always
- update \main_spi_master_start1 $0\main_spi_master_start1[0:0]
+ sync init
+ update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0]
end
- attribute \src "ls180.v:623.32-623.76"
- process $proc$ls180.v:623$2997
+ attribute \src "ls180.v:631.32-631.76"
+ process $proc$ls180.v:631$3007
assign { } { }
assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1
sync always
update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0]
sync init
end
- attribute \src "ls180.v:6262.1-6267.4"
- process $proc$ls180.v:6262$2004
+ attribute \src "ls180.v:6311.1-6316.4"
+ process $proc$ls180.v:6311$2019
assign { } { }
assign $0\libresocsim_start1[0:0] 1'0
- attribute \src "ls180.v:6264.2-6266.5"
+ attribute \src "ls180.v:6313.2-6315.5"
switch \libresocsim_control_re
- attribute \src "ls180.v:6264.6-6264.28"
+ attribute \src "ls180.v:6313.6-6313.28"
case 1'1
assign $0\libresocsim_start1[0:0] \libresocsim_control_storage [0]
case
sync always
update \libresocsim_start1 $0\libresocsim_start1[0:0]
end
- attribute \src "ls180.v:629.5-629.51"
- process $proc$ls180.v:629$2998
+ attribute \src "ls180.v:637.5-637.51"
+ process $proc$ls180.v:637$3008
assign { } { }
assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0]
end
- attribute \src "ls180.v:630.5-630.51"
- process $proc$ls180.v:630$2999
+ attribute \src "ls180.v:638.5-638.51"
+ process $proc$ls180.v:638$3009
assign { } { }
assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0]
end
- attribute \src "ls180.v:632.5-632.47"
- process $proc$ls180.v:632$3000
+ attribute \src "ls180.v:640.5-640.47"
+ process $proc$ls180.v:640$3010
assign { } { }
assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0]
end
- attribute \src "ls180.v:633.5-633.45"
- process $proc$ls180.v:633$3001
+ attribute \src "ls180.v:641.5-641.45"
+ process $proc$ls180.v:641$3011
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0]
end
- attribute \src "ls180.v:634.5-634.45"
- process $proc$ls180.v:634$3002
+ attribute \src "ls180.v:642.5-642.45"
+ process $proc$ls180.v:642$3012
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0]
end
- attribute \src "ls180.v:635.12-635.57"
- process $proc$ls180.v:635$3003
+ attribute \src "ls180.v:643.12-643.57"
+ process $proc$ls180.v:643$3013
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
sync always
sync init
update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:637.5-637.51"
- process $proc$ls180.v:637$3004
+ attribute \src "ls180.v:645.5-645.51"
+ process $proc$ls180.v:645$3014
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:638.5-638.51"
- process $proc$ls180.v:638$3005
+ attribute \src "ls180.v:646.5-646.51"
+ process $proc$ls180.v:646$3015
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:639.5-639.50"
- process $proc$ls180.v:639$3006
+ attribute \src "ls180.v:647.5-647.50"
+ process $proc$ls180.v:647$3016
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:640.5-640.54"
- process $proc$ls180.v:640$3007
+ attribute \src "ls180.v:648.5-648.54"
+ process $proc$ls180.v:648$3017
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
end
- attribute \src "ls180.v:641.5-641.55"
- process $proc$ls180.v:641$3008
+ attribute \src "ls180.v:649.5-649.55"
+ process $proc$ls180.v:649$3018
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
sync always
sync init
update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
end
- attribute \src "ls180.v:642.5-642.56"
- process $proc$ls180.v:642$3009
+ attribute \src "ls180.v:65.12-65.55"
+ process $proc$ls180.v:65$2780
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
+ assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000
sync always
sync init
- update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
+ update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0]
end
- attribute \src "ls180.v:643.5-643.50"
- process $proc$ls180.v:643$3010
+ attribute \src "ls180.v:650.5-650.56"
+ process $proc$ls180.v:650$3019
assign { } { }
- assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0]
+ update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
end
- attribute \src "ls180.v:6448.1-6464.4"
- process $proc$ls180.v:6448$2224
+ attribute \src "ls180.v:6500.1-6516.4"
+ process $proc$ls180.v:6500$2240
assign { } { }
assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0
- attribute \src "ls180.v:6450.2-6463.9"
+ attribute \src "ls180.v:6502.2-6515.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0]
end
- attribute \src "ls180.v:646.5-646.67"
- process $proc$ls180.v:646$3011
+ attribute \src "ls180.v:651.5-651.50"
+ process $proc$ls180.v:651$3020
assign { } { }
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
sync always
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
sync init
+ update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0]
end
- attribute \src "ls180.v:6465.1-6481.4"
- process $proc$ls180.v:6465$2225
+ attribute \src "ls180.v:6517.1-6533.4"
+ process $proc$ls180.v:6517$2241
assign { } { }
assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000
- attribute \src "ls180.v:6467.2-6480.9"
+ attribute \src "ls180.v:6519.2-6532.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0]
end
- attribute \src "ls180.v:647.5-647.66"
- process $proc$ls180.v:647$3012
- assign { } { }
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0
- sync always
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
- sync init
- end
- attribute \src "ls180.v:6482.1-6498.4"
- process $proc$ls180.v:6482$2226
+ attribute \src "ls180.v:6534.1-6550.4"
+ process $proc$ls180.v:6534$2242
assign { } { }
assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00
- attribute \src "ls180.v:6484.2-6497.9"
+ attribute \src "ls180.v:6536.2-6549.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0]
end
- attribute \src "ls180.v:6499.1-6515.4"
- process $proc$ls180.v:6499$2227
+ attribute \src "ls180.v:654.5-654.67"
+ process $proc$ls180.v:654$3021
+ assign { } { }
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0
+ sync always
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:655.5-655.66"
+ process $proc$ls180.v:655$3022
+ assign { } { }
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0
+ sync always
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:6551.1-6567.4"
+ process $proc$ls180.v:6551$2243
assign { } { }
assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0
- attribute \src "ls180.v:6501.2-6514.9"
+ attribute \src "ls180.v:6553.2-6566.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0]
end
- attribute \src "ls180.v:6516.1-6532.4"
- process $proc$ls180.v:6516$2228
+ attribute \src "ls180.v:6568.1-6584.4"
+ process $proc$ls180.v:6568$2244
assign { } { }
assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0
- attribute \src "ls180.v:6518.2-6531.9"
+ attribute \src "ls180.v:6570.2-6583.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0]
end
- attribute \src "ls180.v:6533.1-6549.4"
- process $proc$ls180.v:6533$2229
+ attribute \src "ls180.v:6585.1-6601.4"
+ process $proc$ls180.v:6585$2245
assign { } { }
assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0
- attribute \src "ls180.v:6535.2-6548.9"
+ attribute \src "ls180.v:6587.2-6600.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0]
end
- attribute \src "ls180.v:6550.1-6566.4"
- process $proc$ls180.v:6550$2230
+ attribute \src "ls180.v:6602.1-6618.4"
+ process $proc$ls180.v:6602$2246
assign { } { }
assign $0\builder_comb_t_array_muxed0[0:0] 1'0
- attribute \src "ls180.v:6552.2-6565.9"
+ attribute \src "ls180.v:6604.2-6617.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0]
end
- attribute \src "ls180.v:6567.1-6583.4"
- process $proc$ls180.v:6567$2231
+ attribute \src "ls180.v:6619.1-6635.4"
+ process $proc$ls180.v:6619$2247
assign { } { }
assign $0\builder_comb_t_array_muxed1[0:0] 1'0
- attribute \src "ls180.v:6569.2-6582.9"
+ attribute \src "ls180.v:6621.2-6634.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0]
end
- attribute \src "ls180.v:6584.1-6600.4"
- process $proc$ls180.v:6584$2232
+ attribute \src "ls180.v:6636.1-6652.4"
+ process $proc$ls180.v:6636$2248
assign { } { }
assign $0\builder_comb_t_array_muxed2[0:0] 1'0
- attribute \src "ls180.v:6586.2-6599.9"
+ attribute \src "ls180.v:6638.2-6651.9"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0]
end
- attribute \src "ls180.v:66.5-66.46"
- process $proc$ls180.v:66$2771
- assign { } { }
- assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0]
- end
- attribute \src "ls180.v:6601.1-6617.4"
- process $proc$ls180.v:6601$2233
+ attribute \src "ls180.v:6653.1-6669.4"
+ process $proc$ls180.v:6653$2249
assign { } { }
assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0
- attribute \src "ls180.v:6603.2-6616.9"
+ attribute \src "ls180.v:6655.2-6668.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0]
end
- attribute \src "ls180.v:6618.1-6634.4"
- process $proc$ls180.v:6618$2234
+ attribute \src "ls180.v:6670.1-6686.4"
+ process $proc$ls180.v:6670$2250
assign { } { }
assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000
- attribute \src "ls180.v:6620.2-6633.9"
+ attribute \src "ls180.v:6672.2-6685.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0]
end
- attribute \src "ls180.v:662.11-662.68"
- process $proc$ls180.v:662$3013
- assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000
- sync always
- sync init
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
- end
- attribute \src "ls180.v:663.5-663.64"
- process $proc$ls180.v:663$3014
- assign { } { }
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0
- sync always
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
- sync init
- end
- attribute \src "ls180.v:6635.1-6651.4"
- process $proc$ls180.v:6635$2235
+ attribute \src "ls180.v:6687.1-6703.4"
+ process $proc$ls180.v:6687$2251
assign { } { }
assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00
- attribute \src "ls180.v:6637.2-6650.9"
+ attribute \src "ls180.v:6689.2-6702.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0]
end
- attribute \src "ls180.v:664.11-664.70"
- process $proc$ls180.v:664$3015
- assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000
- sync always
- sync init
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
- end
- attribute \src "ls180.v:665.11-665.70"
- process $proc$ls180.v:665$3016
+ attribute \src "ls180.v:670.11-670.68"
+ process $proc$ls180.v:670$3023
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000
+ assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
sync init
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
end
- attribute \src "ls180.v:6652.1-6668.4"
- process $proc$ls180.v:6652$2236
+ attribute \src "ls180.v:6704.1-6720.4"
+ process $proc$ls180.v:6704$2252
assign { } { }
assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0
- attribute \src "ls180.v:6654.2-6667.9"
+ attribute \src "ls180.v:6706.2-6719.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0]
end
- attribute \src "ls180.v:666.11-666.73"
- process $proc$ls180.v:666$3017
+ attribute \src "ls180.v:671.5-671.64"
+ process $proc$ls180.v:671$3024
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
sync init
- update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:6669.1-6685.4"
- process $proc$ls180.v:6669$2237
+ attribute \src "ls180.v:672.11-672.70"
+ process $proc$ls180.v:672$3025
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
+ end
+ attribute \src "ls180.v:6721.1-6737.4"
+ process $proc$ls180.v:6721$2253
assign { } { }
assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0
- attribute \src "ls180.v:6671.2-6684.9"
+ attribute \src "ls180.v:6723.2-6736.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0]
end
- attribute \src "ls180.v:6686.1-6702.4"
- process $proc$ls180.v:6686$2238
+ attribute \src "ls180.v:673.11-673.70"
+ process $proc$ls180.v:673$3026
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
+ end
+ attribute \src "ls180.v:6738.1-6754.4"
+ process $proc$ls180.v:6738$2254
assign { } { }
assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0
- attribute \src "ls180.v:6688.2-6701.9"
+ attribute \src "ls180.v:6740.2-6753.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0]
end
- attribute \src "ls180.v:6703.1-6719.4"
- process $proc$ls180.v:6703$2239
+ attribute \src "ls180.v:674.11-674.73"
+ process $proc$ls180.v:674$3027
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
+ end
+ attribute \src "ls180.v:6755.1-6771.4"
+ process $proc$ls180.v:6755$2255
assign { } { }
assign $0\builder_comb_t_array_muxed3[0:0] 1'0
- attribute \src "ls180.v:6705.2-6718.9"
+ attribute \src "ls180.v:6757.2-6770.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0]
end
- attribute \src "ls180.v:6720.1-6736.4"
- process $proc$ls180.v:6720$2240
+ attribute \src "ls180.v:6772.1-6788.4"
+ process $proc$ls180.v:6772$2256
assign { } { }
assign $0\builder_comb_t_array_muxed4[0:0] 1'0
- attribute \src "ls180.v:6722.2-6735.9"
+ attribute \src "ls180.v:6774.2-6787.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0]
end
- attribute \src "ls180.v:6737.1-6753.4"
- process $proc$ls180.v:6737$2241
+ attribute \src "ls180.v:6789.1-6805.4"
+ process $proc$ls180.v:6789$2257
assign { } { }
assign $0\builder_comb_t_array_muxed5[0:0] 1'0
- attribute \src "ls180.v:6739.2-6752.9"
+ attribute \src "ls180.v:6791.2-6804.9"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0]
end
- attribute \src "ls180.v:6754.1-6761.4"
- process $proc$ls180.v:6754$2242
+ attribute \src "ls180.v:6806.1-6813.4"
+ process $proc$ls180.v:6806$2258
assign { } { }
assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000
- attribute \src "ls180.v:6756.2-6760.9"
+ attribute \src "ls180.v:6808.2-6812.9"
switch \builder_roundrobin0_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0]
end
- attribute \src "ls180.v:6762.1-6769.4"
- process $proc$ls180.v:6762$2243
+ attribute \src "ls180.v:6814.1-6821.4"
+ process $proc$ls180.v:6814$2259
assign { } { }
assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0
- attribute \src "ls180.v:6764.2-6768.9"
+ attribute \src "ls180.v:6816.2-6820.9"
switch \builder_roundrobin0_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0]
end
- attribute \src "ls180.v:6770.1-6777.4"
- process $proc$ls180.v:6770$2244
+ attribute \src "ls180.v:6822.1-6829.4"
+ process $proc$ls180.v:6822$2260
assign { } { }
assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0
- attribute \src "ls180.v:6772.2-6776.9"
+ attribute \src "ls180.v:6824.2-6828.9"
switch \builder_roundrobin0_grant
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6774$2257_Y
+ assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6826$2273_Y
end
sync always
update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0]
end
- attribute \src "ls180.v:6778.1-6785.4"
- process $proc$ls180.v:6778$2258
+ attribute \src "ls180.v:6830.1-6837.4"
+ process $proc$ls180.v:6830$2274
assign { } { }
assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000
- attribute \src "ls180.v:6780.2-6784.9"
+ attribute \src "ls180.v:6832.2-6836.9"
switch \builder_roundrobin1_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0]
end
- attribute \src "ls180.v:6786.1-6793.4"
- process $proc$ls180.v:6786$2259
+ attribute \src "ls180.v:6838.1-6845.4"
+ process $proc$ls180.v:6838$2275
assign { } { }
assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0
- attribute \src "ls180.v:6788.2-6792.9"
+ attribute \src "ls180.v:6840.2-6844.9"
switch \builder_roundrobin1_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0]
end
- attribute \src "ls180.v:6794.1-6801.4"
- process $proc$ls180.v:6794$2260
+ attribute \src "ls180.v:6846.1-6853.4"
+ process $proc$ls180.v:6846$2276
assign { } { }
assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0
- attribute \src "ls180.v:6796.2-6800.9"
+ attribute \src "ls180.v:6848.2-6852.9"
switch \builder_roundrobin1_grant
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6798$2273_Y
+ assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6850$2289_Y
end
sync always
update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0]
end
- attribute \src "ls180.v:6802.1-6809.4"
- process $proc$ls180.v:6802$2274
+ attribute \src "ls180.v:6854.1-6861.4"
+ process $proc$ls180.v:6854$2290
assign { } { }
assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000
- attribute \src "ls180.v:6804.2-6808.9"
+ attribute \src "ls180.v:6856.2-6860.9"
switch \builder_roundrobin2_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0]
end
- attribute \src "ls180.v:6810.1-6817.4"
- process $proc$ls180.v:6810$2275
+ attribute \src "ls180.v:6862.1-6869.4"
+ process $proc$ls180.v:6862$2291
assign { } { }
assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0
- attribute \src "ls180.v:6812.2-6816.9"
+ attribute \src "ls180.v:6864.2-6868.9"
switch \builder_roundrobin2_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0]
end
- attribute \src "ls180.v:6818.1-6825.4"
- process $proc$ls180.v:6818$2276
+ attribute \src "ls180.v:6870.1-6877.4"
+ process $proc$ls180.v:6870$2292
assign { } { }
assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0
- attribute \src "ls180.v:6820.2-6824.9"
+ attribute \src "ls180.v:6872.2-6876.9"
switch \builder_roundrobin2_grant
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6822$2289_Y
+ assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6874$2305_Y
end
sync always
update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0]
end
- attribute \src "ls180.v:6826.1-6833.4"
- process $proc$ls180.v:6826$2290
+ attribute \src "ls180.v:6878.1-6885.4"
+ process $proc$ls180.v:6878$2306
assign { } { }
assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000
- attribute \src "ls180.v:6828.2-6832.9"
+ attribute \src "ls180.v:6880.2-6884.9"
switch \builder_roundrobin3_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0]
end
- attribute \src "ls180.v:6834.1-6841.4"
- process $proc$ls180.v:6834$2291
+ attribute \src "ls180.v:6886.1-6893.4"
+ process $proc$ls180.v:6886$2307
assign { } { }
assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0
- attribute \src "ls180.v:6836.2-6840.9"
+ attribute \src "ls180.v:6888.2-6892.9"
switch \builder_roundrobin3_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0]
end
- attribute \src "ls180.v:6842.1-6849.4"
- process $proc$ls180.v:6842$2292
+ attribute \src "ls180.v:6894.1-6901.4"
+ process $proc$ls180.v:6894$2308
assign { } { }
assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0
- attribute \src "ls180.v:6844.2-6848.9"
+ attribute \src "ls180.v:6896.2-6900.9"
switch \builder_roundrobin3_grant
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6846$2305_Y
+ assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6898$2321_Y
end
sync always
update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0]
end
- attribute \src "ls180.v:6850.1-6869.4"
- process $proc$ls180.v:6850$2306
+ attribute \src "ls180.v:6902.1-6921.4"
+ process $proc$ls180.v:6902$2322
assign { } { }
assign $0\builder_comb_rhs_array_muxed24[31:0] 0
- attribute \src "ls180.v:6852.2-6868.9"
+ attribute \src "ls180.v:6904.2-6920.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0]
end
- attribute \src "ls180.v:687.5-687.59"
- process $proc$ls180.v:687$3018
- assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
- end
- attribute \src "ls180.v:6870.1-6889.4"
- process $proc$ls180.v:6870$2307
+ attribute \src "ls180.v:6922.1-6941.4"
+ process $proc$ls180.v:6922$2323
assign { } { }
assign $0\builder_comb_rhs_array_muxed25[31:0] 0
- attribute \src "ls180.v:6872.2-6888.9"
+ attribute \src "ls180.v:6924.2-6940.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0]
end
- attribute \src "ls180.v:689.5-689.59"
- process $proc$ls180.v:689$3019
- assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
- end
- attribute \src "ls180.v:6890.1-6909.4"
- process $proc$ls180.v:6890$2308
+ attribute \src "ls180.v:6942.1-6961.4"
+ process $proc$ls180.v:6942$2324
assign { } { }
assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000
- attribute \src "ls180.v:6892.2-6908.9"
+ attribute \src "ls180.v:6944.2-6960.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0]
end
- attribute \src "ls180.v:690.5-690.58"
- process $proc$ls180.v:690$3020
- assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0
- sync always
- sync init
- update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
- end
- attribute \src "ls180.v:691.5-691.64"
- process $proc$ls180.v:691$3021
+ attribute \src "ls180.v:695.5-695.59"
+ process $proc$ls180.v:695$3028
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
+ update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
end
- attribute \src "ls180.v:6910.1-6929.4"
- process $proc$ls180.v:6910$2309
+ attribute \src "ls180.v:6962.1-6981.4"
+ process $proc$ls180.v:6962$2325
assign { } { }
assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0
- attribute \src "ls180.v:6912.2-6928.9"
+ attribute \src "ls180.v:6964.2-6980.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0]
end
- attribute \src "ls180.v:692.12-692.74"
- process $proc$ls180.v:692$3022
+ attribute \src "ls180.v:697.5-697.59"
+ process $proc$ls180.v:697$3029
assign { } { }
- assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
+ assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
+ update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
end
- attribute \src "ls180.v:693.12-693.47"
- process $proc$ls180.v:693$3023
+ attribute \src "ls180.v:698.5-698.58"
+ process $proc$ls180.v:698$3030
assign { } { }
- assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000
+ assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0]
+ update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
end
- attribute \src "ls180.v:6930.1-6949.4"
- process $proc$ls180.v:6930$2310
+ attribute \src "ls180.v:6982.1-7001.4"
+ process $proc$ls180.v:6982$2326
assign { } { }
assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0
- attribute \src "ls180.v:6932.2-6948.9"
+ attribute \src "ls180.v:6984.2-7000.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0]
end
- attribute \src "ls180.v:694.5-694.46"
- process $proc$ls180.v:694$3024
+ attribute \src "ls180.v:699.5-699.64"
+ process $proc$ls180.v:699$3031
assign { } { }
- assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0]
+ update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
+ end
+ attribute \src "ls180.v:700.12-700.74"
+ process $proc$ls180.v:700$3032
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
end
- attribute \src "ls180.v:6950.1-6969.4"
- process $proc$ls180.v:6950$2311
+ attribute \src "ls180.v:7002.1-7021.4"
+ process $proc$ls180.v:7002$2327
assign { } { }
assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0
- attribute \src "ls180.v:6952.2-6968.9"
+ attribute \src "ls180.v:7004.2-7020.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0]
end
- attribute \src "ls180.v:696.5-696.44"
- process $proc$ls180.v:696$3025
+ attribute \src "ls180.v:701.12-701.47"
+ process $proc$ls180.v:701$3033
assign { } { }
- assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000
sync always
sync init
- update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0]
+ update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0]
end
- attribute \src "ls180.v:697.5-697.45"
- process $proc$ls180.v:697$3026
+ attribute \src "ls180.v:702.5-702.46"
+ process $proc$ls180.v:702$3034
assign { } { }
- assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0]
+ update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0]
end
- attribute \src "ls180.v:6970.1-6989.4"
- process $proc$ls180.v:6970$2312
+ attribute \src "ls180.v:7022.1-7041.4"
+ process $proc$ls180.v:7022$2328
assign { } { }
assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000
- attribute \src "ls180.v:6972.2-6988.9"
+ attribute \src "ls180.v:7024.2-7040.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0]
end
- attribute \src "ls180.v:698.5-698.54"
- process $proc$ls180.v:698$3027
+ attribute \src "ls180.v:704.5-704.44"
+ process $proc$ls180.v:704$3035
assign { } { }
- assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
+ update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0]
end
- attribute \src "ls180.v:6990.1-7009.4"
- process $proc$ls180.v:6990$2313
+ attribute \src "ls180.v:7042.1-7061.4"
+ process $proc$ls180.v:7042$2329
assign { } { }
assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00
- attribute \src "ls180.v:6992.2-7008.9"
+ attribute \src "ls180.v:7044.2-7060.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0]
end
- attribute \src "ls180.v:70.5-70.46"
- process $proc$ls180.v:70$2772
+ attribute \src "ls180.v:705.5-705.45"
+ process $proc$ls180.v:705$3036
assign { } { }
- assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0
- sync always
- update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0]
- sync init
- end
- attribute \src "ls180.v:700.32-700.76"
- process $proc$ls180.v:700$3028
- assign { } { }
- assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
+ assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
+ update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0]
end
- attribute \src "ls180.v:701.11-701.55"
- process $proc$ls180.v:701$3029
+ attribute \src "ls180.v:706.5-706.54"
+ process $proc$ls180.v:706$3037
assign { } { }
- assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000
+ assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
sync always
sync init
- update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0]
+ update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:7010.1-7026.4"
- process $proc$ls180.v:7010$2314
+ attribute \src "ls180.v:7062.1-7078.4"
+ process $proc$ls180.v:7062$2330
assign { } { }
assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00
- attribute \src "ls180.v:7012.2-7025.9"
+ attribute \src "ls180.v:7064.2-7077.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0]
end
- attribute \src "ls180.v:7027.1-7043.4"
- process $proc$ls180.v:7027$2315
+ attribute \src "ls180.v:7079.1-7095.4"
+ process $proc$ls180.v:7079$2331
assign { } { }
assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000
- attribute \src "ls180.v:7029.2-7042.9"
+ attribute \src "ls180.v:7081.2-7094.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0]
end
- attribute \src "ls180.v:703.32-703.75"
- process $proc$ls180.v:703$3030
+ attribute \src "ls180.v:708.32-708.76"
+ process $proc$ls180.v:708$3038
assign { } { }
- assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1
+ assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
sync always
- update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0]
sync init
+ update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
end
- attribute \src "ls180.v:7044.1-7060.4"
- process $proc$ls180.v:7044$2316
+ attribute \src "ls180.v:709.11-709.55"
+ process $proc$ls180.v:709$3039
+ assign { } { }
+ assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000
+ sync always
+ sync init
+ update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0]
+ end
+ attribute \src "ls180.v:7096.1-7112.4"
+ process $proc$ls180.v:7096$2332
assign { } { }
assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0
- attribute \src "ls180.v:7046.2-7059.9"
+ attribute \src "ls180.v:7098.2-7111.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7051$2318_Y
+ assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7103$2334_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7054$2320_Y
+ assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7106$2336_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7057$2322_Y
+ assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7109$2338_Y
end
sync always
update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0]
end
- attribute \src "ls180.v:705.32-705.76"
- process $proc$ls180.v:705$3031
+ attribute \src "ls180.v:711.32-711.75"
+ process $proc$ls180.v:711$3040
assign { } { }
- assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1
+ assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1
sync always
- update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0]
+ update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0]
sync init
end
- attribute \src "ls180.v:7061.1-7077.4"
- process $proc$ls180.v:7061$2323
+ attribute \src "ls180.v:7113.1-7129.4"
+ process $proc$ls180.v:7113$2339
assign { } { }
assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0
- attribute \src "ls180.v:7063.2-7076.9"
+ attribute \src "ls180.v:7115.2-7128.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7068$2325_Y
+ assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7120$2341_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7071$2327_Y
+ assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7123$2343_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7074$2329_Y
+ assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7126$2345_Y
end
sync always
update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0]
end
- attribute \src "ls180.v:7078.1-7094.4"
- process $proc$ls180.v:7078$2330
+ attribute \src "ls180.v:713.32-713.76"
+ process $proc$ls180.v:713$3041
+ assign { } { }
+ assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1
+ sync always
+ update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:7130.1-7146.4"
+ process $proc$ls180.v:7130$2346
assign { } { }
assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0
- attribute \src "ls180.v:7080.2-7093.9"
+ attribute \src "ls180.v:7132.2-7145.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7085$2332_Y
+ assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7137$2348_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7088$2334_Y
+ assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7140$2350_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7091$2336_Y
+ assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7143$2352_Y
end
sync always
update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0]
end
- attribute \src "ls180.v:708.5-708.44"
- process $proc$ls180.v:708$3032
- assign { } { }
- assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0
- sync always
- update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0]
- sync init
- end
- attribute \src "ls180.v:709.5-709.45"
- process $proc$ls180.v:709$3033
- assign { } { }
- assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0
- sync always
- update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0]
- sync init
- end
- attribute \src "ls180.v:7095.1-7111.4"
- process $proc$ls180.v:7095$2337
+ attribute \src "ls180.v:7147.1-7163.4"
+ process $proc$ls180.v:7147$2353
assign { } { }
assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0
- attribute \src "ls180.v:7097.2-7110.9"
+ attribute \src "ls180.v:7149.2-7162.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7102$2339_Y
+ assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7154$2355_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7105$2341_Y
+ assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7157$2357_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7108$2343_Y
+ assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7160$2359_Y
end
sync always
update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0]
end
- attribute \src "ls180.v:710.5-710.43"
- process $proc$ls180.v:710$3034
- assign { } { }
- assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0
- sync always
- update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0]
- sync init
- end
- attribute \src "ls180.v:711.5-711.48"
- process $proc$ls180.v:711$3035
+ attribute \src "ls180.v:716.5-716.44"
+ process $proc$ls180.v:716$3042
assign { } { }
- assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0
+ assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0
sync always
- update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0]
+ update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0]
sync init
end
- attribute \src "ls180.v:7112.1-7128.4"
- process $proc$ls180.v:7112$2344
+ attribute \src "ls180.v:7164.1-7180.4"
+ process $proc$ls180.v:7164$2360
assign { } { }
assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0
- attribute \src "ls180.v:7114.2-7127.9"
+ attribute \src "ls180.v:7166.2-7179.9"
switch \main_sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7119$2346_Y
+ assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7171$2362_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7122$2348_Y
+ assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7174$2364_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7125$2350_Y
+ assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7177$2366_Y
end
sync always
update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0]
end
- attribute \src "ls180.v:7129.1-7157.4"
- process $proc$ls180.v:7129$2351
+ attribute \src "ls180.v:717.5-717.45"
+ process $proc$ls180.v:717$3043
+ assign { } { }
+ assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0
+ sync always
+ update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:718.5-718.43"
+ process $proc$ls180.v:718$3044
+ assign { } { }
+ assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0
+ sync always
+ update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:7181.1-7209.4"
+ process $proc$ls180.v:7181$2367
assign { } { }
assign $0\builder_sync_f_array_muxed0[0:0] 1'0
- attribute \src "ls180.v:7131.2-7156.9"
+ attribute \src "ls180.v:7183.2-7208.9"
switch \main_spi_master_mosi_sel
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0]
end
- attribute \src "ls180.v:713.5-713.43"
- process $proc$ls180.v:713$3036
+ attribute \src "ls180.v:719.5-719.48"
+ process $proc$ls180.v:719$3045
+ assign { } { }
+ assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0
+ sync always
+ update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:72.5-72.46"
+ process $proc$ls180.v:72$2781
+ assign { } { }
+ assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0
+ sync always
+ sync init
+ update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0]
+ end
+ attribute \src "ls180.v:721.5-721.43"
+ process $proc$ls180.v:721$3046
assign { } { }
assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0
sync always
update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0]
sync init
end
- attribute \src "ls180.v:7158.1-7186.4"
- process $proc$ls180.v:7158$2352
+ attribute \src "ls180.v:7210.1-7238.4"
+ process $proc$ls180.v:7210$2368
assign { } { }
assign $0\builder_sync_f_array_muxed1[0:0] 1'0
- attribute \src "ls180.v:7160.2-7185.9"
+ attribute \src "ls180.v:7212.2-7237.9"
switch \libresocsim_mosi_sel
attribute \src "ls180.v:0.0-0.0"
case 3'000
sync always
update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0]
end
- attribute \src "ls180.v:716.5-716.49"
- process $proc$ls180.v:716$3037
+ attribute \src "ls180.v:724.5-724.49"
+ process $proc$ls180.v:724$3047
assign { } { }
assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
sync always
sync init
update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:717.5-717.49"
- process $proc$ls180.v:717$3038
+ attribute \src "ls180.v:725.5-725.49"
+ process $proc$ls180.v:725$3048
assign { } { }
assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
sync always
sync init
update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:718.5-718.48"
- process $proc$ls180.v:718$3039
+ attribute \src "ls180.v:726.5-726.48"
+ process $proc$ls180.v:726$3049
assign { } { }
assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0
sync always
sync init
update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:722.11-722.46"
- process $proc$ls180.v:722$3040
- assign { } { }
- assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000
- sync always
- sync init
- update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0]
- end
- attribute \src "ls180.v:724.11-724.45"
- process $proc$ls180.v:724$3041
- assign { } { }
- assign $1\main_sdram_choose_cmd_grant[1:0] 2'00
- sync always
- sync init
- update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0]
- end
- attribute \src "ls180.v:7244.1-7262.4"
- process $proc$ls180.v:7244$2353
+ attribute \src "ls180.v:7296.1-7314.4"
+ process $proc$ls180.v:7296$2369
assign { } { }
assign { } { }
assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1
sync always
update \main_gpio_status $0\main_gpio_status[15:0]
end
- attribute \src "ls180.v:726.5-726.44"
- process $proc$ls180.v:726$3042
+ attribute \src "ls180.v:730.11-730.46"
+ process $proc$ls180.v:730$3050
assign { } { }
- assign $1\main_sdram_choose_req_want_reads[0:0] 1'0
+ assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000
sync always
sync init
- update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0]
+ update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0]
end
- attribute \src "ls180.v:727.5-727.45"
- process $proc$ls180.v:727$3043
+ attribute \src "ls180.v:732.11-732.45"
+ process $proc$ls180.v:732$3051
assign { } { }
- assign $1\main_sdram_choose_req_want_writes[0:0] 1'0
+ assign $1\main_sdram_choose_cmd_grant[1:0] 2'00
sync always
sync init
- update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0]
+ update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0]
end
- attribute \src "ls180.v:7283.1-7285.4"
- process $proc$ls180.v:7283$2354
+ attribute \src "ls180.v:7335.1-7337.4"
+ process $proc$ls180.v:7335$2370
assign { } { }
assign $0\main_int_rst[0:0] \sys_rst
sync posedge \por_clk
update \main_int_rst $0\main_int_rst[0:0]
end
- attribute \src "ls180.v:7287.1-7357.4"
- process $proc$ls180.v:7287$2355
+ attribute \src "ls180.v:7339.1-7409.4"
+ process $proc$ls180.v:7339$2371
assign { } { }
assign { } { }
assign { } { }
assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0]
assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1]
assign $0\sdram_clock[0:0] \sys_clk_1
- assign $0\sdcard_clk[0:0] $and$ls180.v:7344$2357_Y
+ assign $0\sdcard_clk[0:0] $and$ls180.v:7396$2373_Y
assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe
assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o
assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i
update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0]
update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0]
end
- attribute \src "ls180.v:729.5-729.48"
- process $proc$ls180.v:729$3044
+ attribute \src "ls180.v:734.5-734.44"
+ process $proc$ls180.v:734$3052
assign { } { }
- assign $1\main_sdram_choose_req_want_activates[0:0] 1'0
+ assign $1\main_sdram_choose_req_want_reads[0:0] 1'0
sync always
sync init
- update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0]
+ update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0]
end
- attribute \src "ls180.v:731.5-731.43"
- process $proc$ls180.v:731$3045
+ attribute \src "ls180.v:735.5-735.45"
+ process $proc$ls180.v:735$3053
assign { } { }
- assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0
+ assign $1\main_sdram_choose_req_want_writes[0:0] 1'0
sync always
sync init
- update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0]
+ update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0]
end
- attribute \src "ls180.v:734.5-734.49"
- process $proc$ls180.v:734$3046
+ attribute \src "ls180.v:737.5-737.48"
+ process $proc$ls180.v:737$3054
assign { } { }
- assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0
+ assign $1\main_sdram_choose_req_want_activates[0:0] 1'0
sync always
sync init
- update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0]
+ update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0]
end
- attribute \src "ls180.v:735.5-735.49"
- process $proc$ls180.v:735$3047
+ attribute \src "ls180.v:739.5-739.43"
+ process $proc$ls180.v:739$3055
assign { } { }
- assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0
+ assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0
sync always
sync init
- update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0]
+ update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0]
end
- attribute \src "ls180.v:7359.1-9973.4"
- process $proc$ls180.v:7359$2358
+ attribute \src "ls180.v:7411.1-10036.4"
+ process $proc$ls180.v:7411$2374
assign $0\spi_master_clk[0:0] \spi_master_clk
assign $0\spi_master_mosi[0:0] \spi_master_mosi
assign { } { }
assign $0\main_converter_dat_r[31:0] \main_converter_dat_r
assign $0\main_cmd_consumed[0:0] \main_cmd_consumed
assign $0\main_wdata_consumed[0:0] \main_wdata_consumed
- assign $0\main_storage[31:0] \main_storage
+ assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage
assign { } { }
assign { } { }
- assign $0\main_uart_clk_txen[0:0] \main_uart_clk_txen
- assign $0\main_phase_accumulator_tx[31:0] \main_phase_accumulator_tx
- assign $0\main_tx_reg[7:0] \main_tx_reg
- assign $0\main_tx_bitcount[3:0] \main_tx_bitcount
- assign $0\main_tx_busy[0:0] \main_tx_busy
+ assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen
+ assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx
+ assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg
+ assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount
+ assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy
assign { } { }
- assign $0\main_source_payload_data[7:0] \main_source_payload_data
- assign $0\main_uart_clk_rxen[0:0] \main_uart_clk_rxen
- assign $0\main_phase_accumulator_rx[31:0] \main_phase_accumulator_rx
+ assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data
+ assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen
+ assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx
assign { } { }
- assign $0\main_rx_reg[7:0] \main_rx_reg
- assign $0\main_rx_bitcount[3:0] \main_rx_bitcount
- assign $0\main_rx_busy[0:0] \main_rx_busy
+ assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg
+ assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount
+ assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy
assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending
assign { } { }
assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending
assign { } { }
assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage
assign { } { }
+ assign $0\main_i2c_storage[2:0] \main_i2c_storage
+ assign { } { }
assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\main_dummy[41:0] [0] $or$ls180.v:7360$2359_Y
- assign $0\main_dummy[41:0] [1] $or$ls180.v:7361$2360_Y
- assign $0\main_dummy[41:0] [2] $or$ls180.v:7362$2361_Y
- assign $0\main_dummy[41:0] [3] $or$ls180.v:7363$2362_Y
- assign $0\main_dummy[41:0] [4] $or$ls180.v:7364$2363_Y
- assign $0\main_dummy[41:0] [5] $or$ls180.v:7365$2364_Y
- assign $0\main_dummy[41:0] [6] $or$ls180.v:7366$2365_Y
- assign $0\main_dummy[41:0] [7] $or$ls180.v:7367$2366_Y
- assign $0\main_dummy[41:0] [8] $or$ls180.v:7368$2367_Y
- assign $0\main_dummy[41:0] [9] $or$ls180.v:7369$2368_Y
- assign $0\main_dummy[41:0] [10] $or$ls180.v:7370$2369_Y
- assign $0\main_dummy[41:0] [11] $or$ls180.v:7371$2370_Y
- assign $0\main_dummy[41:0] [12] $or$ls180.v:7372$2371_Y
- assign $0\main_dummy[41:0] [13] $or$ls180.v:7373$2372_Y
- assign $0\main_dummy[41:0] [14] $or$ls180.v:7374$2373_Y
- assign $0\main_dummy[41:0] [15] $or$ls180.v:7375$2374_Y
- assign $0\main_dummy[41:0] [16] $or$ls180.v:7376$2375_Y
- assign $0\main_dummy[41:0] [17] $or$ls180.v:7377$2376_Y
- assign $0\main_dummy[41:0] [18] $or$ls180.v:7378$2377_Y
- assign $0\main_dummy[41:0] [19] $or$ls180.v:7379$2378_Y
- assign $0\main_dummy[41:0] [20] $or$ls180.v:7380$2379_Y
- assign $0\main_dummy[41:0] [21] $or$ls180.v:7381$2380_Y
- assign $0\main_dummy[41:0] [22] $or$ls180.v:7382$2381_Y
- assign $0\main_dummy[41:0] [23] $or$ls180.v:7383$2382_Y
- assign $0\main_dummy[41:0] [24] $or$ls180.v:7384$2383_Y
- assign $0\main_dummy[41:0] [25] $or$ls180.v:7385$2384_Y
- assign $0\main_dummy[41:0] [26] $or$ls180.v:7386$2385_Y
- assign $0\main_dummy[41:0] [27] $or$ls180.v:7387$2386_Y
- assign $0\main_dummy[41:0] [28] $or$ls180.v:7388$2387_Y
- assign $0\main_dummy[41:0] [29] $or$ls180.v:7389$2388_Y
- assign $0\main_dummy[41:0] [30] $or$ls180.v:7390$2389_Y
- assign $0\main_dummy[41:0] [31] $or$ls180.v:7391$2390_Y
- assign $0\main_dummy[41:0] [32] $or$ls180.v:7392$2391_Y
- assign $0\main_dummy[41:0] [33] $or$ls180.v:7393$2392_Y
- assign $0\main_dummy[41:0] [34] $or$ls180.v:7394$2393_Y
- assign $0\main_dummy[41:0] [35] $or$ls180.v:7395$2394_Y
- assign $0\main_dummy[41:0] [36] $or$ls180.v:7396$2395_Y
- assign $0\main_dummy[41:0] [37] $or$ls180.v:7397$2396_Y
- assign $0\main_dummy[41:0] [38] $or$ls180.v:7398$2397_Y
- assign $0\main_dummy[41:0] [39] $or$ls180.v:7399$2398_Y
- assign $0\main_dummy[41:0] [40] $or$ls180.v:7400$2399_Y
- assign $0\main_dummy[41:0] [41] $or$ls180.v:7401$2400_Y
+ assign { } { }
+ assign $0\main_dummy[35:0] [0] $or$ls180.v:7412$2375_Y
+ assign $0\main_dummy[35:0] [1] $or$ls180.v:7413$2376_Y
+ assign $0\main_dummy[35:0] [2] $or$ls180.v:7414$2377_Y
+ assign $0\main_dummy[35:0] [3] $or$ls180.v:7415$2378_Y
+ assign $0\main_dummy[35:0] [4] $or$ls180.v:7416$2379_Y
+ assign $0\main_dummy[35:0] [5] $or$ls180.v:7417$2380_Y
+ assign $0\main_dummy[35:0] [6] $or$ls180.v:7418$2381_Y
+ assign $0\main_dummy[35:0] [7] $or$ls180.v:7419$2382_Y
+ assign $0\main_dummy[35:0] [8] $or$ls180.v:7420$2383_Y
+ assign $0\main_dummy[35:0] [9] $or$ls180.v:7421$2384_Y
+ assign $0\main_dummy[35:0] [10] $or$ls180.v:7422$2385_Y
+ assign $0\main_dummy[35:0] [11] $or$ls180.v:7423$2386_Y
+ assign $0\main_dummy[35:0] [12] $or$ls180.v:7424$2387_Y
+ assign $0\main_dummy[35:0] [13] $or$ls180.v:7425$2388_Y
+ assign $0\main_dummy[35:0] [14] $or$ls180.v:7426$2389_Y
+ assign $0\main_dummy[35:0] [15] $or$ls180.v:7427$2390_Y
+ assign $0\main_dummy[35:0] [16] $or$ls180.v:7428$2391_Y
+ assign $0\main_dummy[35:0] [17] $or$ls180.v:7429$2392_Y
+ assign $0\main_dummy[35:0] [18] $or$ls180.v:7430$2393_Y
+ assign $0\main_dummy[35:0] [19] $or$ls180.v:7431$2394_Y
+ assign $0\main_dummy[35:0] [20] $or$ls180.v:7432$2395_Y
+ assign $0\main_dummy[35:0] [21] $or$ls180.v:7433$2396_Y
+ assign $0\main_dummy[35:0] [22] $or$ls180.v:7434$2397_Y
+ assign $0\main_dummy[35:0] [23] $or$ls180.v:7435$2398_Y
+ assign $0\main_dummy[35:0] [24] $or$ls180.v:7436$2399_Y
+ assign $0\main_dummy[35:0] [25] $or$ls180.v:7437$2400_Y
+ assign $0\main_dummy[35:0] [26] $or$ls180.v:7438$2401_Y
+ assign $0\main_dummy[35:0] [27] $or$ls180.v:7439$2402_Y
+ assign $0\main_dummy[35:0] [28] $or$ls180.v:7440$2403_Y
+ assign $0\main_dummy[35:0] [29] $or$ls180.v:7441$2404_Y
+ assign $0\main_dummy[35:0] [30] $or$ls180.v:7442$2405_Y
+ assign $0\main_dummy[35:0] [31] $or$ls180.v:7443$2406_Y
+ assign $0\main_dummy[35:0] [32] $or$ls180.v:7444$2407_Y
+ assign $0\main_dummy[35:0] [33] $or$ls180.v:7445$2408_Y
+ assign $0\main_dummy[35:0] [34] $or$ls180.v:7446$2409_Y
+ assign $0\main_dummy[35:0] [35] $or$ls180.v:7447$2410_Y
assign $0\builder_converter0_state[0:0] \builder_converter0_next_state
assign $0\builder_converter1_state[0:0] \builder_converter1_next_state
assign $0\builder_converter2_state[0:0] \builder_converter2_next_state
assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0
assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0
assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1
- assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7843$2497_Y
- assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7844$2498_Y
- assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7845$2499_Y
+ assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7889$2507_Y
+ assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7890$2508_Y
+ assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7891$2509_Y
assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5
assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6
assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state
- assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7879$2517_Y
- assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7880$2529_Y
+ assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7925$2527_Y
+ assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7926$2539_Y
assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0
assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1
assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2
assign $0\builder_converter_state[0:0] \builder_converter_next_state
- assign $0\main_sink_ready[0:0] 1'0
- assign $0\main_source_valid[0:0] 1'0
- assign $0\main_rx_r[0:0] \main_rx
+ assign $0\main_uart_phy_sink_ready[0:0] 1'0
+ assign $0\main_uart_phy_source_valid[0:0] 1'0
+ assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx
assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger
assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger
- assign $0\main_spi_master_clk_divider1[15:0] $add$ls180.v:8038$2575_Y
- assign $0\spi_master_cs_n[0:0] $or$ls180.v:8047$2578_Y
+ assign $0\main_spi_master_clk_divider1[15:0] $add$ls180.v:8084$2585_Y
+ assign $0\spi_master_cs_n[0:0] $or$ls180.v:8093$2588_Y
assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state
assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1
assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1
assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state
assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state
assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state
- assign $0\libresocsim_clk_divider1[15:0] $add$ls180.v:8586$2670_Y
- assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8595$2673_Y
+ assign $0\libresocsim_clk_divider1[15:0] $add$ls180.v:8632$2680_Y
+ assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8641$2683_Y
assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state
assign $0\builder_state[1:0] \builder_next_state
assign $0\builder_slave_sel_r[4:0] \builder_slave_sel
assign $0\main_gpio_oe_re[0:0] \builder_csrbank1_oe0_re
assign $0\main_gpio_out_re[0:0] \builder_csrbank1_out0_re
assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000
- assign $0\main_pwm0_enable_re[0:0] \builder_csrbank2_enable0_re
- assign $0\main_pwm0_width_re[0:0] \builder_csrbank2_width0_re
- assign $0\main_pwm0_period_re[0:0] \builder_csrbank2_period0_re
+ assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re
assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000
- assign $0\main_pwm1_enable_re[0:0] \builder_csrbank3_enable0_re
- assign $0\main_pwm1_width_re[0:0] \builder_csrbank3_width0_re
- assign $0\main_pwm1_period_re[0:0] \builder_csrbank3_period0_re
+ assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re
+ assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re
+ assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re
assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000
- assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank4_dma_base0_re
- assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank4_dma_length0_re
- assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank4_dma_enable0_re
- assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank4_dma_loop0_re
+ assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re
+ assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re
+ assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re
assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000
- assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank5_cmd_argument0_re
- assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank5_cmd_command0_re
- assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank5_block_length0_re
- assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank5_block_count0_re
+ assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re
+ assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re
+ assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re
+ assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re
assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000
- assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank6_dma_base0_re
- assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank6_dma_length0_re
- assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank6_dma_enable0_re
- assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank6_dma_loop0_re
+ assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re
+ assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re
+ assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re
+ assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re
assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000
- assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank7_clocker_divider0_re
+ assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re
+ assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re
+ assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re
+ assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re
assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000
- assign $0\main_sdram_re[0:0] \builder_csrbank8_dfii_control0_re
- assign $0\main_sdram_command_re[0:0] \builder_csrbank8_dfii_pi0_command0_re
- assign $0\main_sdram_address_re[0:0] \builder_csrbank8_dfii_pi0_address0_re
- assign $0\main_sdram_baddress_re[0:0] \builder_csrbank8_dfii_pi0_baddress0_re
- assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank8_dfii_pi0_wrdata0_re
+ assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re
assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000
- assign $0\main_spi_master_control_re[0:0] \builder_csrbank9_control0_re
- assign $0\main_spi_master_mosi_re[0:0] \builder_csrbank9_mosi0_re
- assign $0\main_spi_master_cs_re[0:0] \builder_csrbank9_cs0_re
- assign $0\main_spi_master_loopback_re[0:0] \builder_csrbank9_loopback0_re
+ assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re
+ assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re
+ assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re
+ assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re
+ assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re
assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000
- assign $0\libresocsim_control_re[0:0] \builder_csrbank10_control0_re
- assign $0\libresocsim_mosi_re[0:0] \builder_csrbank10_mosi0_re
- assign $0\libresocsim_cs_re[0:0] \builder_csrbank10_cs0_re
- assign $0\libresocsim_loopback_re[0:0] \builder_csrbank10_loopback0_re
- assign $0\libresocsim_re[0:0] \builder_csrbank10_clk_divider0_re
+ assign $0\main_spi_master_control_re[0:0] \builder_csrbank10_control0_re
+ assign $0\main_spi_master_mosi_re[0:0] \builder_csrbank10_mosi0_re
+ assign $0\main_spi_master_cs_re[0:0] \builder_csrbank10_cs0_re
+ assign $0\main_spi_master_loopback_re[0:0] \builder_csrbank10_loopback0_re
assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000
- assign $0\main_libresocsim_load_re[0:0] \builder_csrbank11_load0_re
- assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank11_reload0_re
- assign $0\main_libresocsim_en_re[0:0] \builder_csrbank11_en0_re
- assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank11_update_value0_re
- assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank11_ev_enable0_re
+ assign $0\libresocsim_control_re[0:0] \builder_csrbank11_control0_re
+ assign $0\libresocsim_mosi_re[0:0] \builder_csrbank11_mosi0_re
+ assign $0\libresocsim_cs_re[0:0] \builder_csrbank11_cs0_re
+ assign $0\libresocsim_loopback_re[0:0] \builder_csrbank11_loopback0_re
+ assign $0\libresocsim_re[0:0] \builder_csrbank11_clk_divider0_re
assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000
- assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re
+ assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re
+ assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re
+ assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re
+ assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re
+ assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re
assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000
- assign $0\main_re[0:0] \builder_csrbank13_tuning_word0_re
+ assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re
+ assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000
+ assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re
assign $0\builder_multiregimpl0_regs0[0:0] \main_libresocsim_libresoc_constraintmanager0_uart0_rx
assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0
assign $0\builder_multiregimpl1_regs0[0:0] \main_gpio_pads_i [0]
assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0
assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15]
assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0
- attribute \src "ls180.v:7402.2-7404.5"
- switch $or$ls180.v:7402$2401_Y
- attribute \src "ls180.v:7402.6-7402.94"
+ attribute \src "ls180.v:7448.2-7450.5"
+ switch $or$ls180.v:7448$2411_Y
+ attribute \src "ls180.v:7448.6-7448.94"
case 1'1
assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r
case
end
- attribute \src "ls180.v:7406.2-7408.5"
+ attribute \src "ls180.v:7452.2-7454.5"
switch \main_libresocsim_converter0_counter_converter0_next_value_ce
- attribute \src "ls180.v:7406.6-7406.66"
+ attribute \src "ls180.v:7452.6-7452.66"
case 1'1
assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value
case
end
- attribute \src "ls180.v:7409.2-7412.5"
+ attribute \src "ls180.v:7455.2-7458.5"
switch \main_libresocsim_converter0_reset
- attribute \src "ls180.v:7409.6-7409.39"
+ attribute \src "ls180.v:7455.6-7455.39"
case 1'1
assign $0\main_libresocsim_converter0_counter[0:0] 1'0
assign $0\builder_converter0_state[0:0] 1'0
case
end
- attribute \src "ls180.v:7413.2-7415.5"
- switch $or$ls180.v:7413$2402_Y
- attribute \src "ls180.v:7413.6-7413.94"
+ attribute \src "ls180.v:7459.2-7461.5"
+ switch $or$ls180.v:7459$2412_Y
+ attribute \src "ls180.v:7459.6-7459.94"
case 1'1
assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r
case
end
- attribute \src "ls180.v:7417.2-7419.5"
+ attribute \src "ls180.v:7463.2-7465.5"
switch \main_libresocsim_converter1_counter_converter1_next_value_ce
- attribute \src "ls180.v:7417.6-7417.66"
+ attribute \src "ls180.v:7463.6-7463.66"
case 1'1
assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value
case
end
- attribute \src "ls180.v:7420.2-7423.5"
+ attribute \src "ls180.v:7466.2-7469.5"
switch \main_libresocsim_converter1_reset
- attribute \src "ls180.v:7420.6-7420.39"
+ attribute \src "ls180.v:7466.6-7466.39"
case 1'1
assign $0\main_libresocsim_converter1_counter[0:0] 1'0
assign $0\builder_converter1_state[0:0] 1'0
case
end
- attribute \src "ls180.v:7424.2-7426.5"
- switch $or$ls180.v:7424$2403_Y
- attribute \src "ls180.v:7424.6-7424.94"
+ attribute \src "ls180.v:7470.2-7472.5"
+ switch $or$ls180.v:7470$2413_Y
+ attribute \src "ls180.v:7470.6-7470.94"
case 1'1
assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r
case
end
- attribute \src "ls180.v:7428.2-7430.5"
+ attribute \src "ls180.v:7474.2-7476.5"
switch \main_libresocsim_converter2_counter_converter2_next_value_ce
- attribute \src "ls180.v:7428.6-7428.66"
+ attribute \src "ls180.v:7474.6-7474.66"
case 1'1
assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value
case
end
- attribute \src "ls180.v:7431.2-7434.5"
+ attribute \src "ls180.v:7477.2-7480.5"
switch \main_libresocsim_converter2_reset
- attribute \src "ls180.v:7431.6-7431.39"
+ attribute \src "ls180.v:7477.6-7477.39"
case 1'1
assign $0\main_libresocsim_converter2_counter[0:0] 1'0
assign $0\builder_converter2_state[0:0] 1'0
case
end
- attribute \src "ls180.v:7435.2-7439.5"
- switch $ne$ls180.v:7435$2404_Y
- attribute \src "ls180.v:7435.6-7435.53"
+ attribute \src "ls180.v:7481.2-7485.5"
+ switch $ne$ls180.v:7481$2414_Y
+ attribute \src "ls180.v:7481.6-7481.53"
case 1'1
- attribute \src "ls180.v:7436.3-7438.6"
+ attribute \src "ls180.v:7482.3-7484.6"
switch \main_libresocsim_bus_error
- attribute \src "ls180.v:7436.7-7436.33"
+ attribute \src "ls180.v:7482.7-7482.33"
case 1'1
- assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7437$2405_Y
+ assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7483$2415_Y
case
end
case
end
- attribute \src "ls180.v:7441.2-7443.5"
- switch $and$ls180.v:7441$2408_Y
- attribute \src "ls180.v:7441.6-7441.103"
+ attribute \src "ls180.v:7487.2-7489.5"
+ switch $and$ls180.v:7487$2418_Y
+ attribute \src "ls180.v:7487.6-7487.103"
case 1'1
assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1
case
end
- attribute \src "ls180.v:7444.2-7452.5"
+ attribute \src "ls180.v:7490.2-7498.5"
switch \main_libresocsim_en_storage
- attribute \src "ls180.v:7444.6-7444.33"
+ attribute \src "ls180.v:7490.6-7490.33"
case 1'1
- attribute \src "ls180.v:7445.3-7449.6"
- switch $eq$ls180.v:7445$2409_Y
- attribute \src "ls180.v:7445.7-7445.39"
+ attribute \src "ls180.v:7491.3-7495.6"
+ switch $eq$ls180.v:7491$2419_Y
+ attribute \src "ls180.v:7491.7-7491.39"
case 1'1
assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage
- attribute \src "ls180.v:7447.7-7447.11"
+ attribute \src "ls180.v:7493.7-7493.11"
case
- assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7448$2410_Y
+ assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7494$2420_Y
end
- attribute \src "ls180.v:7450.6-7450.10"
+ attribute \src "ls180.v:7496.6-7496.10"
case
assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage
end
- attribute \src "ls180.v:7453.2-7455.5"
+ attribute \src "ls180.v:7499.2-7501.5"
switch \main_libresocsim_update_value_re
- attribute \src "ls180.v:7453.6-7453.38"
+ attribute \src "ls180.v:7499.6-7499.38"
case 1'1
assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value
case
end
- attribute \src "ls180.v:7456.2-7458.5"
+ attribute \src "ls180.v:7502.2-7504.5"
switch \main_libresocsim_zero_clear
- attribute \src "ls180.v:7456.6-7456.33"
+ attribute \src "ls180.v:7502.6-7502.33"
case 1'1
assign $0\main_libresocsim_zero_pending[0:0] 1'0
case
end
- attribute \src "ls180.v:7460.2-7462.5"
- switch $and$ls180.v:7460$2412_Y
- attribute \src "ls180.v:7460.6-7460.76"
+ attribute \src "ls180.v:7506.2-7508.5"
+ switch $and$ls180.v:7506$2422_Y
+ attribute \src "ls180.v:7506.6-7506.76"
case 1'1
assign $0\main_libresocsim_zero_pending[0:0] 1'1
case
end
- attribute \src "ls180.v:7465.2-7467.5"
+ attribute \src "ls180.v:7511.2-7513.5"
switch \main_sdram_inti_p0_rddata_valid
- attribute \src "ls180.v:7465.6-7465.37"
+ attribute \src "ls180.v:7511.6-7511.37"
case 1'1
assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata
case
end
- attribute \src "ls180.v:7468.2-7472.5"
- switch $and$ls180.v:7468$2414_Y
- attribute \src "ls180.v:7468.6-7468.57"
+ attribute \src "ls180.v:7514.2-7518.5"
+ switch $and$ls180.v:7514$2424_Y
+ attribute \src "ls180.v:7514.6-7514.57"
case 1'1
- assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7469$2415_Y
- attribute \src "ls180.v:7470.6-7470.10"
+ assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7515$2425_Y
+ attribute \src "ls180.v:7516.6-7516.10"
case
assign $0\main_sdram_timer_count1[9:0] 10'1100001101
end
- attribute \src "ls180.v:7474.2-7480.5"
+ attribute \src "ls180.v:7520.2-7526.5"
switch \main_sdram_postponer_req_i
- attribute \src "ls180.v:7474.6-7474.32"
+ attribute \src "ls180.v:7520.6-7520.32"
case 1'1
- assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7475$2416_Y
- attribute \src "ls180.v:7476.3-7479.6"
- switch $eq$ls180.v:7476$2417_Y
- attribute \src "ls180.v:7476.7-7476.43"
+ assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7521$2426_Y
+ attribute \src "ls180.v:7522.3-7525.6"
+ switch $eq$ls180.v:7522$2427_Y
+ attribute \src "ls180.v:7522.7-7522.43"
case 1'1
assign $0\main_sdram_postponer_count[0:0] 1'0
assign $0\main_sdram_postponer_req_o[0:0] 1'1
end
case
end
- attribute \src "ls180.v:7481.2-7489.5"
+ attribute \src "ls180.v:7527.2-7535.5"
switch \main_sdram_sequencer_start0
- attribute \src "ls180.v:7481.6-7481.33"
+ attribute \src "ls180.v:7527.6-7527.33"
case 1'1
assign $0\main_sdram_sequencer_count[0:0] 1'0
- attribute \src "ls180.v:7483.6-7483.10"
+ attribute \src "ls180.v:7529.6-7529.10"
case
- attribute \src "ls180.v:7484.3-7488.6"
+ attribute \src "ls180.v:7530.3-7534.6"
switch \main_sdram_sequencer_done1
- attribute \src "ls180.v:7484.7-7484.33"
+ attribute \src "ls180.v:7530.7-7530.33"
case 1'1
- attribute \src "ls180.v:7485.4-7487.7"
- switch $ne$ls180.v:7485$2418_Y
- attribute \src "ls180.v:7485.8-7485.44"
+ attribute \src "ls180.v:7531.4-7533.7"
+ switch $ne$ls180.v:7531$2428_Y
+ attribute \src "ls180.v:7531.8-7531.44"
case 1'1
- assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7486$2419_Y
+ assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7532$2429_Y
case
end
case
end
end
- attribute \src "ls180.v:7496.2-7502.5"
- switch $and$ls180.v:7496$2421_Y
- attribute \src "ls180.v:7496.6-7496.76"
+ attribute \src "ls180.v:7542.2-7548.5"
+ switch $and$ls180.v:7542$2431_Y
+ attribute \src "ls180.v:7542.6-7542.76"
case 1'1
assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000
assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
assign $0\main_sdram_cmd_payload_we[0:0] 1'1
case
end
- attribute \src "ls180.v:7503.2-7509.5"
- switch $eq$ls180.v:7503$2422_Y
- attribute \src "ls180.v:7503.6-7503.44"
+ attribute \src "ls180.v:7549.2-7555.5"
+ switch $eq$ls180.v:7549$2432_Y
+ attribute \src "ls180.v:7549.6-7549.44"
case 1'1
assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000
assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
assign $0\main_sdram_cmd_payload_we[0:0] 1'0
case
end
- attribute \src "ls180.v:7510.2-7517.5"
- switch $eq$ls180.v:7510$2423_Y
- attribute \src "ls180.v:7510.6-7510.44"
+ attribute \src "ls180.v:7556.2-7563.5"
+ switch $eq$ls180.v:7556$2433_Y
+ attribute \src "ls180.v:7556.6-7556.44"
case 1'1
assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000
assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
assign $0\main_sdram_sequencer_done1[0:0] 1'1
case
end
- attribute \src "ls180.v:7518.2-7528.5"
- switch $eq$ls180.v:7518$2424_Y
- attribute \src "ls180.v:7518.6-7518.44"
+ attribute \src "ls180.v:7564.2-7574.5"
+ switch $eq$ls180.v:7564$2434_Y
+ attribute \src "ls180.v:7564.6-7564.44"
case 1'1
assign $0\main_sdram_sequencer_counter[3:0] 4'0000
- attribute \src "ls180.v:7520.6-7520.10"
+ attribute \src "ls180.v:7566.6-7566.10"
case
- attribute \src "ls180.v:7521.3-7527.6"
- switch $ne$ls180.v:7521$2425_Y
- attribute \src "ls180.v:7521.7-7521.45"
+ attribute \src "ls180.v:7567.3-7573.6"
+ switch $ne$ls180.v:7567$2435_Y
+ attribute \src "ls180.v:7567.7-7567.45"
case 1'1
- assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7522$2426_Y
- attribute \src "ls180.v:7523.7-7523.11"
+ assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7568$2436_Y
+ attribute \src "ls180.v:7569.7-7569.11"
case
- attribute \src "ls180.v:7524.4-7526.7"
+ attribute \src "ls180.v:7570.4-7572.7"
switch \main_sdram_sequencer_start1
- attribute \src "ls180.v:7524.8-7524.35"
+ attribute \src "ls180.v:7570.8-7570.35"
case 1'1
assign $0\main_sdram_sequencer_counter[3:0] 4'0001
case
end
end
end
- attribute \src "ls180.v:7530.2-7537.5"
+ attribute \src "ls180.v:7576.2-7583.5"
switch \main_sdram_bankmachine0_row_close
- attribute \src "ls180.v:7530.6-7530.39"
+ attribute \src "ls180.v:7576.6-7576.39"
case 1'1
assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0
- attribute \src "ls180.v:7532.6-7532.10"
+ attribute \src "ls180.v:7578.6-7578.10"
case
- attribute \src "ls180.v:7533.3-7536.6"
+ attribute \src "ls180.v:7579.3-7582.6"
switch \main_sdram_bankmachine0_row_open
- attribute \src "ls180.v:7533.7-7533.39"
+ attribute \src "ls180.v:7579.7-7579.39"
case 1'1
assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1
assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
case
end
end
- attribute \src "ls180.v:7538.2-7540.5"
- switch $and$ls180.v:7538$2429_Y
- attribute \src "ls180.v:7538.6-7538.191"
+ attribute \src "ls180.v:7584.2-7586.5"
+ switch $and$ls180.v:7584$2439_Y
+ attribute \src "ls180.v:7584.6-7584.191"
case 1'1
- assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7539$2430_Y
+ assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7585$2440_Y
case
end
- attribute \src "ls180.v:7541.2-7543.5"
+ attribute \src "ls180.v:7587.2-7589.5"
switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7541.6-7541.58"
+ attribute \src "ls180.v:7587.6-7587.58"
case 1'1
- assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7542$2431_Y
+ assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7588$2441_Y
case
end
- attribute \src "ls180.v:7544.2-7552.5"
- switch $and$ls180.v:7544$2434_Y
- attribute \src "ls180.v:7544.6-7544.191"
+ attribute \src "ls180.v:7590.2-7598.5"
+ switch $and$ls180.v:7590$2444_Y
+ attribute \src "ls180.v:7590.6-7590.191"
case 1'1
- attribute \src "ls180.v:7545.3-7547.6"
- switch $not$ls180.v:7545$2435_Y
- attribute \src "ls180.v:7545.7-7545.62"
+ attribute \src "ls180.v:7591.3-7593.6"
+ switch $not$ls180.v:7591$2445_Y
+ attribute \src "ls180.v:7591.7-7591.62"
case 1'1
- assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7546$2436_Y
+ assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7592$2446_Y
case
end
- attribute \src "ls180.v:7548.6-7548.10"
+ attribute \src "ls180.v:7594.6-7594.10"
case
- attribute \src "ls180.v:7549.3-7551.6"
+ attribute \src "ls180.v:7595.3-7597.6"
switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7549.7-7549.59"
+ attribute \src "ls180.v:7595.7-7595.59"
case 1'1
- assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7550$2437_Y
+ assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7596$2447_Y
case
end
end
- attribute \src "ls180.v:7553.2-7559.5"
- switch $or$ls180.v:7553$2439_Y
- attribute \src "ls180.v:7553.6-7553.108"
+ attribute \src "ls180.v:7599.2-7605.5"
+ switch $or$ls180.v:7599$2449_Y
+ attribute \src "ls180.v:7599.6-7599.108"
case 1'1
assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid
assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first
assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr
case
end
- attribute \src "ls180.v:7560.2-7574.5"
+ attribute \src "ls180.v:7606.2-7620.5"
switch \main_sdram_bankmachine0_twtpcon_valid
- attribute \src "ls180.v:7560.6-7560.43"
+ attribute \src "ls180.v:7606.6-7606.43"
case 1'1
assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100
- attribute \src "ls180.v:7562.3-7566.6"
+ attribute \src "ls180.v:7608.3-7612.6"
switch 1'0
- attribute \src "ls180.v:7564.7-7564.11"
+ attribute \src "ls180.v:7610.7-7610.11"
case
assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:7567.6-7567.10"
+ attribute \src "ls180.v:7613.6-7613.10"
case
- attribute \src "ls180.v:7568.3-7573.6"
- switch $not$ls180.v:7568$2440_Y
- attribute \src "ls180.v:7568.7-7568.47"
+ attribute \src "ls180.v:7614.3-7619.6"
+ switch $not$ls180.v:7614$2450_Y
+ attribute \src "ls180.v:7614.7-7614.47"
case 1'1
- assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7569$2441_Y
- attribute \src "ls180.v:7570.4-7572.7"
- switch $eq$ls180.v:7570$2442_Y
- attribute \src "ls180.v:7570.8-7570.55"
+ assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7615$2451_Y
+ attribute \src "ls180.v:7616.4-7618.7"
+ switch $eq$ls180.v:7616$2452_Y
+ attribute \src "ls180.v:7616.8-7616.55"
case 1'1
assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:7576.2-7583.5"
+ attribute \src "ls180.v:7622.2-7629.5"
switch \main_sdram_bankmachine1_row_close
- attribute \src "ls180.v:7576.6-7576.39"
+ attribute \src "ls180.v:7622.6-7622.39"
case 1'1
assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0
- attribute \src "ls180.v:7578.6-7578.10"
+ attribute \src "ls180.v:7624.6-7624.10"
case
- attribute \src "ls180.v:7579.3-7582.6"
+ attribute \src "ls180.v:7625.3-7628.6"
switch \main_sdram_bankmachine1_row_open
- attribute \src "ls180.v:7579.7-7579.39"
+ attribute \src "ls180.v:7625.7-7625.39"
case 1'1
assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1
assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
case
end
end
- attribute \src "ls180.v:7584.2-7586.5"
- switch $and$ls180.v:7584$2445_Y
- attribute \src "ls180.v:7584.6-7584.191"
+ attribute \src "ls180.v:7630.2-7632.5"
+ switch $and$ls180.v:7630$2455_Y
+ attribute \src "ls180.v:7630.6-7630.191"
case 1'1
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7585$2446_Y
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7631$2456_Y
case
end
- attribute \src "ls180.v:7587.2-7589.5"
+ attribute \src "ls180.v:7633.2-7635.5"
switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7587.6-7587.58"
+ attribute \src "ls180.v:7633.6-7633.58"
case 1'1
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7588$2447_Y
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7634$2457_Y
case
end
- attribute \src "ls180.v:7590.2-7598.5"
- switch $and$ls180.v:7590$2450_Y
- attribute \src "ls180.v:7590.6-7590.191"
+ attribute \src "ls180.v:7636.2-7644.5"
+ switch $and$ls180.v:7636$2460_Y
+ attribute \src "ls180.v:7636.6-7636.191"
case 1'1
- attribute \src "ls180.v:7591.3-7593.6"
- switch $not$ls180.v:7591$2451_Y
- attribute \src "ls180.v:7591.7-7591.62"
+ attribute \src "ls180.v:7637.3-7639.6"
+ switch $not$ls180.v:7637$2461_Y
+ attribute \src "ls180.v:7637.7-7637.62"
case 1'1
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7592$2452_Y
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7638$2462_Y
case
end
- attribute \src "ls180.v:7594.6-7594.10"
+ attribute \src "ls180.v:7640.6-7640.10"
case
- attribute \src "ls180.v:7595.3-7597.6"
+ attribute \src "ls180.v:7641.3-7643.6"
switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7595.7-7595.59"
+ attribute \src "ls180.v:7641.7-7641.59"
case 1'1
- assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7596$2453_Y
+ assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7642$2463_Y
case
end
end
- attribute \src "ls180.v:7599.2-7605.5"
- switch $or$ls180.v:7599$2455_Y
- attribute \src "ls180.v:7599.6-7599.108"
+ attribute \src "ls180.v:7645.2-7651.5"
+ switch $or$ls180.v:7645$2465_Y
+ attribute \src "ls180.v:7645.6-7645.108"
case 1'1
assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid
assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first
assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr
case
end
- attribute \src "ls180.v:7606.2-7620.5"
+ attribute \src "ls180.v:7652.2-7666.5"
switch \main_sdram_bankmachine1_twtpcon_valid
- attribute \src "ls180.v:7606.6-7606.43"
+ attribute \src "ls180.v:7652.6-7652.43"
case 1'1
assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100
- attribute \src "ls180.v:7608.3-7612.6"
+ attribute \src "ls180.v:7654.3-7658.6"
switch 1'0
- attribute \src "ls180.v:7610.7-7610.11"
+ attribute \src "ls180.v:7656.7-7656.11"
case
assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:7613.6-7613.10"
+ attribute \src "ls180.v:7659.6-7659.10"
case
- attribute \src "ls180.v:7614.3-7619.6"
- switch $not$ls180.v:7614$2456_Y
- attribute \src "ls180.v:7614.7-7614.47"
+ attribute \src "ls180.v:7660.3-7665.6"
+ switch $not$ls180.v:7660$2466_Y
+ attribute \src "ls180.v:7660.7-7660.47"
case 1'1
- assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7615$2457_Y
- attribute \src "ls180.v:7616.4-7618.7"
- switch $eq$ls180.v:7616$2458_Y
- attribute \src "ls180.v:7616.8-7616.55"
+ assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7661$2467_Y
+ attribute \src "ls180.v:7662.4-7664.7"
+ switch $eq$ls180.v:7662$2468_Y
+ attribute \src "ls180.v:7662.8-7662.55"
case 1'1
assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:7622.2-7629.5"
+ attribute \src "ls180.v:7668.2-7675.5"
switch \main_sdram_bankmachine2_row_close
- attribute \src "ls180.v:7622.6-7622.39"
+ attribute \src "ls180.v:7668.6-7668.39"
case 1'1
assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0
- attribute \src "ls180.v:7624.6-7624.10"
+ attribute \src "ls180.v:7670.6-7670.10"
case
- attribute \src "ls180.v:7625.3-7628.6"
+ attribute \src "ls180.v:7671.3-7674.6"
switch \main_sdram_bankmachine2_row_open
- attribute \src "ls180.v:7625.7-7625.39"
+ attribute \src "ls180.v:7671.7-7671.39"
case 1'1
assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1
assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
case
end
end
- attribute \src "ls180.v:7630.2-7632.5"
- switch $and$ls180.v:7630$2461_Y
- attribute \src "ls180.v:7630.6-7630.191"
+ attribute \src "ls180.v:7676.2-7678.5"
+ switch $and$ls180.v:7676$2471_Y
+ attribute \src "ls180.v:7676.6-7676.191"
case 1'1
- assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7631$2462_Y
+ assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7677$2472_Y
case
end
- attribute \src "ls180.v:7633.2-7635.5"
+ attribute \src "ls180.v:7679.2-7681.5"
switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7633.6-7633.58"
+ attribute \src "ls180.v:7679.6-7679.58"
case 1'1
- assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7634$2463_Y
+ assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7680$2473_Y
case
end
- attribute \src "ls180.v:7636.2-7644.5"
- switch $and$ls180.v:7636$2466_Y
- attribute \src "ls180.v:7636.6-7636.191"
+ attribute \src "ls180.v:7682.2-7690.5"
+ switch $and$ls180.v:7682$2476_Y
+ attribute \src "ls180.v:7682.6-7682.191"
case 1'1
- attribute \src "ls180.v:7637.3-7639.6"
- switch $not$ls180.v:7637$2467_Y
- attribute \src "ls180.v:7637.7-7637.62"
+ attribute \src "ls180.v:7683.3-7685.6"
+ switch $not$ls180.v:7683$2477_Y
+ attribute \src "ls180.v:7683.7-7683.62"
case 1'1
- assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7638$2468_Y
+ assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7684$2478_Y
case
end
- attribute \src "ls180.v:7640.6-7640.10"
+ attribute \src "ls180.v:7686.6-7686.10"
case
- attribute \src "ls180.v:7641.3-7643.6"
+ attribute \src "ls180.v:7687.3-7689.6"
switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7641.7-7641.59"
+ attribute \src "ls180.v:7687.7-7687.59"
case 1'1
- assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7642$2469_Y
+ assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7688$2479_Y
case
end
end
- attribute \src "ls180.v:7645.2-7651.5"
- switch $or$ls180.v:7645$2471_Y
- attribute \src "ls180.v:7645.6-7645.108"
+ attribute \src "ls180.v:7691.2-7697.5"
+ switch $or$ls180.v:7691$2481_Y
+ attribute \src "ls180.v:7691.6-7691.108"
case 1'1
assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid
assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first
assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr
case
end
- attribute \src "ls180.v:7652.2-7666.5"
+ attribute \src "ls180.v:7698.2-7712.5"
switch \main_sdram_bankmachine2_twtpcon_valid
- attribute \src "ls180.v:7652.6-7652.43"
+ attribute \src "ls180.v:7698.6-7698.43"
case 1'1
assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100
- attribute \src "ls180.v:7654.3-7658.6"
+ attribute \src "ls180.v:7700.3-7704.6"
switch 1'0
- attribute \src "ls180.v:7656.7-7656.11"
+ attribute \src "ls180.v:7702.7-7702.11"
case
assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:7659.6-7659.10"
+ attribute \src "ls180.v:7705.6-7705.10"
case
- attribute \src "ls180.v:7660.3-7665.6"
- switch $not$ls180.v:7660$2472_Y
- attribute \src "ls180.v:7660.7-7660.47"
+ attribute \src "ls180.v:7706.3-7711.6"
+ switch $not$ls180.v:7706$2482_Y
+ attribute \src "ls180.v:7706.7-7706.47"
case 1'1
- assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7661$2473_Y
- attribute \src "ls180.v:7662.4-7664.7"
- switch $eq$ls180.v:7662$2474_Y
- attribute \src "ls180.v:7662.8-7662.55"
+ assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7707$2483_Y
+ attribute \src "ls180.v:7708.4-7710.7"
+ switch $eq$ls180.v:7708$2484_Y
+ attribute \src "ls180.v:7708.8-7708.55"
case 1'1
assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:7668.2-7675.5"
+ attribute \src "ls180.v:7714.2-7721.5"
switch \main_sdram_bankmachine3_row_close
- attribute \src "ls180.v:7668.6-7668.39"
+ attribute \src "ls180.v:7714.6-7714.39"
case 1'1
assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0
- attribute \src "ls180.v:7670.6-7670.10"
+ attribute \src "ls180.v:7716.6-7716.10"
case
- attribute \src "ls180.v:7671.3-7674.6"
+ attribute \src "ls180.v:7717.3-7720.6"
switch \main_sdram_bankmachine3_row_open
- attribute \src "ls180.v:7671.7-7671.39"
+ attribute \src "ls180.v:7717.7-7717.39"
case 1'1
assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1
assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
case
end
end
- attribute \src "ls180.v:7676.2-7678.5"
- switch $and$ls180.v:7676$2477_Y
- attribute \src "ls180.v:7676.6-7676.191"
+ attribute \src "ls180.v:7722.2-7724.5"
+ switch $and$ls180.v:7722$2487_Y
+ attribute \src "ls180.v:7722.6-7722.191"
case 1'1
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7677$2478_Y
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7723$2488_Y
case
end
- attribute \src "ls180.v:7679.2-7681.5"
+ attribute \src "ls180.v:7725.2-7727.5"
switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7679.6-7679.58"
+ attribute \src "ls180.v:7725.6-7725.58"
case 1'1
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7680$2479_Y
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7726$2489_Y
case
end
- attribute \src "ls180.v:7682.2-7690.5"
- switch $and$ls180.v:7682$2482_Y
- attribute \src "ls180.v:7682.6-7682.191"
+ attribute \src "ls180.v:7728.2-7736.5"
+ switch $and$ls180.v:7728$2492_Y
+ attribute \src "ls180.v:7728.6-7728.191"
case 1'1
- attribute \src "ls180.v:7683.3-7685.6"
- switch $not$ls180.v:7683$2483_Y
- attribute \src "ls180.v:7683.7-7683.62"
+ attribute \src "ls180.v:7729.3-7731.6"
+ switch $not$ls180.v:7729$2493_Y
+ attribute \src "ls180.v:7729.7-7729.62"
case 1'1
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7684$2484_Y
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7730$2494_Y
case
end
- attribute \src "ls180.v:7686.6-7686.10"
+ attribute \src "ls180.v:7732.6-7732.10"
case
- attribute \src "ls180.v:7687.3-7689.6"
+ attribute \src "ls180.v:7733.3-7735.6"
switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:7687.7-7687.59"
+ attribute \src "ls180.v:7733.7-7733.59"
case 1'1
- assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7688$2485_Y
+ assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7734$2495_Y
case
end
end
- attribute \src "ls180.v:7691.2-7697.5"
- switch $or$ls180.v:7691$2487_Y
- attribute \src "ls180.v:7691.6-7691.108"
+ attribute \src "ls180.v:7737.2-7743.5"
+ switch $or$ls180.v:7737$2497_Y
+ attribute \src "ls180.v:7737.6-7737.108"
case 1'1
assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid
assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first
assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr
case
end
- attribute \src "ls180.v:7698.2-7712.5"
+ attribute \src "ls180.v:7744.2-7758.5"
switch \main_sdram_bankmachine3_twtpcon_valid
- attribute \src "ls180.v:7698.6-7698.43"
+ attribute \src "ls180.v:7744.6-7744.43"
case 1'1
assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100
- attribute \src "ls180.v:7700.3-7704.6"
+ attribute \src "ls180.v:7746.3-7750.6"
switch 1'0
- attribute \src "ls180.v:7702.7-7702.11"
+ attribute \src "ls180.v:7748.7-7748.11"
case
assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:7705.6-7705.10"
+ attribute \src "ls180.v:7751.6-7751.10"
case
- attribute \src "ls180.v:7706.3-7711.6"
- switch $not$ls180.v:7706$2488_Y
- attribute \src "ls180.v:7706.7-7706.47"
+ attribute \src "ls180.v:7752.3-7757.6"
+ switch $not$ls180.v:7752$2498_Y
+ attribute \src "ls180.v:7752.7-7752.47"
case 1'1
- assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7707$2489_Y
- attribute \src "ls180.v:7708.4-7710.7"
- switch $eq$ls180.v:7708$2490_Y
- attribute \src "ls180.v:7708.8-7708.55"
+ assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7753$2499_Y
+ attribute \src "ls180.v:7754.4-7756.7"
+ switch $eq$ls180.v:7754$2500_Y
+ attribute \src "ls180.v:7754.8-7754.55"
case 1'1
assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:7714.2-7720.5"
- switch $not$ls180.v:7714$2491_Y
- attribute \src "ls180.v:7714.6-7714.23"
+ attribute \src "ls180.v:7760.2-7766.5"
+ switch $not$ls180.v:7760$2501_Y
+ attribute \src "ls180.v:7760.6-7760.23"
case 1'1
assign $0\main_sdram_time0[4:0] 5'11111
- attribute \src "ls180.v:7716.6-7716.10"
+ attribute \src "ls180.v:7762.6-7762.10"
case
- attribute \src "ls180.v:7717.3-7719.6"
- switch $not$ls180.v:7717$2492_Y
- attribute \src "ls180.v:7717.7-7717.30"
+ attribute \src "ls180.v:7763.3-7765.6"
+ switch $not$ls180.v:7763$2502_Y
+ attribute \src "ls180.v:7763.7-7763.30"
case 1'1
- assign $0\main_sdram_time0[4:0] $sub$ls180.v:7718$2493_Y
+ assign $0\main_sdram_time0[4:0] $sub$ls180.v:7764$2503_Y
case
end
end
- attribute \src "ls180.v:7721.2-7727.5"
- switch $not$ls180.v:7721$2494_Y
- attribute \src "ls180.v:7721.6-7721.23"
+ attribute \src "ls180.v:7767.2-7773.5"
+ switch $not$ls180.v:7767$2504_Y
+ attribute \src "ls180.v:7767.6-7767.23"
case 1'1
assign $0\main_sdram_time1[3:0] 4'1111
- attribute \src "ls180.v:7723.6-7723.10"
+ attribute \src "ls180.v:7769.6-7769.10"
case
- attribute \src "ls180.v:7724.3-7726.6"
- switch $not$ls180.v:7724$2495_Y
- attribute \src "ls180.v:7724.7-7724.30"
+ attribute \src "ls180.v:7770.3-7772.6"
+ switch $not$ls180.v:7770$2505_Y
+ attribute \src "ls180.v:7770.7-7770.30"
case 1'1
- assign $0\main_sdram_time1[3:0] $sub$ls180.v:7725$2496_Y
+ assign $0\main_sdram_time1[3:0] $sub$ls180.v:7771$2506_Y
case
end
end
- attribute \src "ls180.v:7728.2-7783.5"
+ attribute \src "ls180.v:7774.2-7829.5"
switch \main_sdram_choose_cmd_ce
- attribute \src "ls180.v:7728.6-7728.30"
+ attribute \src "ls180.v:7774.6-7774.30"
case 1'1
- attribute \src "ls180.v:7729.3-7782.10"
+ attribute \src "ls180.v:7775.3-7828.10"
switch \main_sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
- attribute \src "ls180.v:7731.5-7741.8"
+ attribute \src "ls180.v:7777.5-7787.8"
switch \main_sdram_choose_cmd_request [1]
- attribute \src "ls180.v:7731.9-7731.41"
+ attribute \src "ls180.v:7777.9-7777.41"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
- attribute \src "ls180.v:7733.9-7733.13"
+ attribute \src "ls180.v:7779.9-7779.13"
case
- attribute \src "ls180.v:7734.6-7740.9"
+ attribute \src "ls180.v:7780.6-7786.9"
switch \main_sdram_choose_cmd_request [2]
- attribute \src "ls180.v:7734.10-7734.42"
+ attribute \src "ls180.v:7780.10-7780.42"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
- attribute \src "ls180.v:7736.10-7736.14"
+ attribute \src "ls180.v:7782.10-7782.14"
case
- attribute \src "ls180.v:7737.7-7739.10"
+ attribute \src "ls180.v:7783.7-7785.10"
switch \main_sdram_choose_cmd_request [3]
- attribute \src "ls180.v:7737.11-7737.43"
+ attribute \src "ls180.v:7783.11-7783.43"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'01
- attribute \src "ls180.v:7744.5-7754.8"
+ attribute \src "ls180.v:7790.5-7800.8"
switch \main_sdram_choose_cmd_request [2]
- attribute \src "ls180.v:7744.9-7744.41"
+ attribute \src "ls180.v:7790.9-7790.41"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
- attribute \src "ls180.v:7746.9-7746.13"
+ attribute \src "ls180.v:7792.9-7792.13"
case
- attribute \src "ls180.v:7747.6-7753.9"
+ attribute \src "ls180.v:7793.6-7799.9"
switch \main_sdram_choose_cmd_request [3]
- attribute \src "ls180.v:7747.10-7747.42"
+ attribute \src "ls180.v:7793.10-7793.42"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
- attribute \src "ls180.v:7749.10-7749.14"
+ attribute \src "ls180.v:7795.10-7795.14"
case
- attribute \src "ls180.v:7750.7-7752.10"
+ attribute \src "ls180.v:7796.7-7798.10"
switch \main_sdram_choose_cmd_request [0]
- attribute \src "ls180.v:7750.11-7750.43"
+ attribute \src "ls180.v:7796.11-7796.43"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'10
- attribute \src "ls180.v:7757.5-7767.8"
+ attribute \src "ls180.v:7803.5-7813.8"
switch \main_sdram_choose_cmd_request [3]
- attribute \src "ls180.v:7757.9-7757.41"
+ attribute \src "ls180.v:7803.9-7803.41"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
- attribute \src "ls180.v:7759.9-7759.13"
+ attribute \src "ls180.v:7805.9-7805.13"
case
- attribute \src "ls180.v:7760.6-7766.9"
+ attribute \src "ls180.v:7806.6-7812.9"
switch \main_sdram_choose_cmd_request [0]
- attribute \src "ls180.v:7760.10-7760.42"
+ attribute \src "ls180.v:7806.10-7806.42"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
- attribute \src "ls180.v:7762.10-7762.14"
+ attribute \src "ls180.v:7808.10-7808.14"
case
- attribute \src "ls180.v:7763.7-7765.10"
+ attribute \src "ls180.v:7809.7-7811.10"
switch \main_sdram_choose_cmd_request [1]
- attribute \src "ls180.v:7763.11-7763.43"
+ attribute \src "ls180.v:7809.11-7809.43"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'11
- attribute \src "ls180.v:7770.5-7780.8"
+ attribute \src "ls180.v:7816.5-7826.8"
switch \main_sdram_choose_cmd_request [0]
- attribute \src "ls180.v:7770.9-7770.41"
+ attribute \src "ls180.v:7816.9-7816.41"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
- attribute \src "ls180.v:7772.9-7772.13"
+ attribute \src "ls180.v:7818.9-7818.13"
case
- attribute \src "ls180.v:7773.6-7779.9"
+ attribute \src "ls180.v:7819.6-7825.9"
switch \main_sdram_choose_cmd_request [1]
- attribute \src "ls180.v:7773.10-7773.42"
+ attribute \src "ls180.v:7819.10-7819.42"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
- attribute \src "ls180.v:7775.10-7775.14"
+ attribute \src "ls180.v:7821.10-7821.14"
case
- attribute \src "ls180.v:7776.7-7778.10"
+ attribute \src "ls180.v:7822.7-7824.10"
switch \main_sdram_choose_cmd_request [2]
- attribute \src "ls180.v:7776.11-7776.43"
+ attribute \src "ls180.v:7822.11-7822.43"
case 1'1
assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
case
end
case
end
- attribute \src "ls180.v:7784.2-7839.5"
+ attribute \src "ls180.v:7830.2-7885.5"
switch \main_sdram_choose_req_ce
- attribute \src "ls180.v:7784.6-7784.30"
+ attribute \src "ls180.v:7830.6-7830.30"
case 1'1
- attribute \src "ls180.v:7785.3-7838.10"
+ attribute \src "ls180.v:7831.3-7884.10"
switch \main_sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
- attribute \src "ls180.v:7787.5-7797.8"
+ attribute \src "ls180.v:7833.5-7843.8"
switch \main_sdram_choose_req_request [1]
- attribute \src "ls180.v:7787.9-7787.41"
+ attribute \src "ls180.v:7833.9-7833.41"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'01
- attribute \src "ls180.v:7789.9-7789.13"
+ attribute \src "ls180.v:7835.9-7835.13"
case
- attribute \src "ls180.v:7790.6-7796.9"
+ attribute \src "ls180.v:7836.6-7842.9"
switch \main_sdram_choose_req_request [2]
- attribute \src "ls180.v:7790.10-7790.42"
+ attribute \src "ls180.v:7836.10-7836.42"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'10
- attribute \src "ls180.v:7792.10-7792.14"
+ attribute \src "ls180.v:7838.10-7838.14"
case
- attribute \src "ls180.v:7793.7-7795.10"
+ attribute \src "ls180.v:7839.7-7841.10"
switch \main_sdram_choose_req_request [3]
- attribute \src "ls180.v:7793.11-7793.43"
+ attribute \src "ls180.v:7839.11-7839.43"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'11
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'01
- attribute \src "ls180.v:7800.5-7810.8"
+ attribute \src "ls180.v:7846.5-7856.8"
switch \main_sdram_choose_req_request [2]
- attribute \src "ls180.v:7800.9-7800.41"
+ attribute \src "ls180.v:7846.9-7846.41"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'10
- attribute \src "ls180.v:7802.9-7802.13"
+ attribute \src "ls180.v:7848.9-7848.13"
case
- attribute \src "ls180.v:7803.6-7809.9"
+ attribute \src "ls180.v:7849.6-7855.9"
switch \main_sdram_choose_req_request [3]
- attribute \src "ls180.v:7803.10-7803.42"
+ attribute \src "ls180.v:7849.10-7849.42"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'11
- attribute \src "ls180.v:7805.10-7805.14"
+ attribute \src "ls180.v:7851.10-7851.14"
case
- attribute \src "ls180.v:7806.7-7808.10"
+ attribute \src "ls180.v:7852.7-7854.10"
switch \main_sdram_choose_req_request [0]
- attribute \src "ls180.v:7806.11-7806.43"
+ attribute \src "ls180.v:7852.11-7852.43"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'00
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'10
- attribute \src "ls180.v:7813.5-7823.8"
+ attribute \src "ls180.v:7859.5-7869.8"
switch \main_sdram_choose_req_request [3]
- attribute \src "ls180.v:7813.9-7813.41"
+ attribute \src "ls180.v:7859.9-7859.41"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'11
- attribute \src "ls180.v:7815.9-7815.13"
+ attribute \src "ls180.v:7861.9-7861.13"
case
- attribute \src "ls180.v:7816.6-7822.9"
+ attribute \src "ls180.v:7862.6-7868.9"
switch \main_sdram_choose_req_request [0]
- attribute \src "ls180.v:7816.10-7816.42"
+ attribute \src "ls180.v:7862.10-7862.42"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'00
- attribute \src "ls180.v:7818.10-7818.14"
+ attribute \src "ls180.v:7864.10-7864.14"
case
- attribute \src "ls180.v:7819.7-7821.10"
+ attribute \src "ls180.v:7865.7-7867.10"
switch \main_sdram_choose_req_request [1]
- attribute \src "ls180.v:7819.11-7819.43"
+ attribute \src "ls180.v:7865.11-7865.43"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'01
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'11
- attribute \src "ls180.v:7826.5-7836.8"
+ attribute \src "ls180.v:7872.5-7882.8"
switch \main_sdram_choose_req_request [0]
- attribute \src "ls180.v:7826.9-7826.41"
+ attribute \src "ls180.v:7872.9-7872.41"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'00
- attribute \src "ls180.v:7828.9-7828.13"
+ attribute \src "ls180.v:7874.9-7874.13"
case
- attribute \src "ls180.v:7829.6-7835.9"
+ attribute \src "ls180.v:7875.6-7881.9"
switch \main_sdram_choose_req_request [1]
- attribute \src "ls180.v:7829.10-7829.42"
+ attribute \src "ls180.v:7875.10-7875.42"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'01
- attribute \src "ls180.v:7831.10-7831.14"
+ attribute \src "ls180.v:7877.10-7877.14"
case
- attribute \src "ls180.v:7832.7-7834.10"
+ attribute \src "ls180.v:7878.7-7880.10"
switch \main_sdram_choose_req_request [2]
- attribute \src "ls180.v:7832.11-7832.43"
+ attribute \src "ls180.v:7878.11-7878.43"
case 1'1
assign $0\main_sdram_choose_req_grant[1:0] 2'10
case
end
case
end
- attribute \src "ls180.v:7848.2-7862.5"
+ attribute \src "ls180.v:7894.2-7908.5"
switch \main_sdram_tccdcon_valid
- attribute \src "ls180.v:7848.6-7848.30"
+ attribute \src "ls180.v:7894.6-7894.30"
case 1'1
assign $0\main_sdram_tccdcon_count[0:0] 1'0
- attribute \src "ls180.v:7850.3-7854.6"
+ attribute \src "ls180.v:7896.3-7900.6"
switch 1'1
- attribute \src "ls180.v:7850.7-7850.11"
+ attribute \src "ls180.v:7896.7-7896.11"
case 1'1
assign $0\main_sdram_tccdcon_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:7855.6-7855.10"
+ attribute \src "ls180.v:7901.6-7901.10"
case
- attribute \src "ls180.v:7856.3-7861.6"
- switch $not$ls180.v:7856$2500_Y
- attribute \src "ls180.v:7856.7-7856.34"
+ attribute \src "ls180.v:7902.3-7907.6"
+ switch $not$ls180.v:7902$2510_Y
+ attribute \src "ls180.v:7902.7-7902.34"
case 1'1
- assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7857$2501_Y
- attribute \src "ls180.v:7858.4-7860.7"
- switch $eq$ls180.v:7858$2502_Y
- attribute \src "ls180.v:7858.8-7858.42"
+ assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7903$2511_Y
+ attribute \src "ls180.v:7904.4-7906.7"
+ switch $eq$ls180.v:7904$2512_Y
+ attribute \src "ls180.v:7904.8-7904.42"
case 1'1
assign $0\main_sdram_tccdcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:7863.2-7877.5"
+ attribute \src "ls180.v:7909.2-7923.5"
switch \main_sdram_twtrcon_valid
- attribute \src "ls180.v:7863.6-7863.30"
+ attribute \src "ls180.v:7909.6-7909.30"
case 1'1
assign $0\main_sdram_twtrcon_count[2:0] 3'100
- attribute \src "ls180.v:7865.3-7869.6"
+ attribute \src "ls180.v:7911.3-7915.6"
switch 1'0
- attribute \src "ls180.v:7867.7-7867.11"
+ attribute \src "ls180.v:7913.7-7913.11"
case
assign $0\main_sdram_twtrcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:7870.6-7870.10"
+ attribute \src "ls180.v:7916.6-7916.10"
case
- attribute \src "ls180.v:7871.3-7876.6"
- switch $not$ls180.v:7871$2503_Y
- attribute \src "ls180.v:7871.7-7871.34"
+ attribute \src "ls180.v:7917.3-7922.6"
+ switch $not$ls180.v:7917$2513_Y
+ attribute \src "ls180.v:7917.7-7917.34"
case 1'1
- assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7872$2504_Y
- attribute \src "ls180.v:7873.4-7875.7"
- switch $eq$ls180.v:7873$2505_Y
- attribute \src "ls180.v:7873.8-7873.42"
+ assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7918$2514_Y
+ attribute \src "ls180.v:7919.4-7921.7"
+ switch $eq$ls180.v:7919$2515_Y
+ attribute \src "ls180.v:7919.8-7919.42"
case 1'1
assign $0\main_sdram_twtrcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:7884.2-7886.5"
- switch $or$ls180.v:7884$2530_Y
- attribute \src "ls180.v:7884.6-7884.50"
+ attribute \src "ls180.v:7930.2-7932.5"
+ switch $or$ls180.v:7930$2540_Y
+ attribute \src "ls180.v:7930.6-7930.50"
case 1'1
assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r
case
end
- attribute \src "ls180.v:7888.2-7890.5"
+ attribute \src "ls180.v:7934.2-7936.5"
switch \main_converter_counter_converter_next_value_ce
- attribute \src "ls180.v:7888.6-7888.52"
+ attribute \src "ls180.v:7934.6-7934.52"
case 1'1
assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value
case
end
- attribute \src "ls180.v:7891.2-7894.5"
+ attribute \src "ls180.v:7937.2-7940.5"
switch \main_converter_reset
- attribute \src "ls180.v:7891.6-7891.26"
+ attribute \src "ls180.v:7937.6-7937.26"
case 1'1
assign $0\main_converter_counter[0:0] 1'0
assign $0\builder_converter_state[0:0] 1'0
case
end
- attribute \src "ls180.v:7895.2-7905.5"
+ attribute \src "ls180.v:7941.2-7951.5"
switch \main_litedram_wb_ack
- attribute \src "ls180.v:7895.6-7895.26"
+ attribute \src "ls180.v:7941.6-7941.26"
case 1'1
assign $0\main_cmd_consumed[0:0] 1'0
assign $0\main_wdata_consumed[0:0] 1'0
- attribute \src "ls180.v:7898.6-7898.10"
+ attribute \src "ls180.v:7944.6-7944.10"
case
- attribute \src "ls180.v:7899.3-7901.6"
- switch $and$ls180.v:7899$2531_Y
- attribute \src "ls180.v:7899.7-7899.50"
+ attribute \src "ls180.v:7945.3-7947.6"
+ switch $and$ls180.v:7945$2541_Y
+ attribute \src "ls180.v:7945.7-7945.50"
case 1'1
assign $0\main_cmd_consumed[0:0] 1'1
case
end
- attribute \src "ls180.v:7902.3-7904.6"
- switch $and$ls180.v:7902$2532_Y
- attribute \src "ls180.v:7902.7-7902.54"
+ attribute \src "ls180.v:7948.3-7950.6"
+ switch $and$ls180.v:7948$2542_Y
+ attribute \src "ls180.v:7948.7-7948.54"
case 1'1
assign $0\main_wdata_consumed[0:0] 1'1
case
end
end
- attribute \src "ls180.v:7907.2-7928.5"
- switch $and$ls180.v:7907$2536_Y
- attribute \src "ls180.v:7907.6-7907.64"
+ attribute \src "ls180.v:7953.2-7974.5"
+ switch $and$ls180.v:7953$2546_Y
+ attribute \src "ls180.v:7953.6-7953.91"
case 1'1
- assign $0\main_tx_reg[7:0] \main_sink_payload_data
- assign $0\main_tx_bitcount[3:0] 4'0000
- assign $0\main_tx_busy[0:0] 1'1
+ assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data
+ assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000
+ assign $0\main_uart_phy_tx_busy[0:0] 1'1
assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'0
- attribute \src "ls180.v:7912.6-7912.10"
+ attribute \src "ls180.v:7958.6-7958.10"
case
- attribute \src "ls180.v:7913.3-7927.6"
- switch $and$ls180.v:7913$2537_Y
- attribute \src "ls180.v:7913.7-7913.42"
+ attribute \src "ls180.v:7959.3-7973.6"
+ switch $and$ls180.v:7959$2547_Y
+ attribute \src "ls180.v:7959.7-7959.60"
case 1'1
- assign $0\main_tx_bitcount[3:0] $add$ls180.v:7914$2538_Y
- attribute \src "ls180.v:7915.4-7926.7"
- switch $eq$ls180.v:7915$2539_Y
- attribute \src "ls180.v:7915.8-7915.34"
+ assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7960$2548_Y
+ attribute \src "ls180.v:7961.4-7972.7"
+ switch $eq$ls180.v:7961$2549_Y
+ attribute \src "ls180.v:7961.8-7961.43"
case 1'1
assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1
- attribute \src "ls180.v:7917.8-7917.12"
+ attribute \src "ls180.v:7963.8-7963.12"
case
- attribute \src "ls180.v:7918.5-7925.8"
- switch $eq$ls180.v:7918$2540_Y
- attribute \src "ls180.v:7918.9-7918.35"
+ attribute \src "ls180.v:7964.5-7971.8"
+ switch $eq$ls180.v:7964$2550_Y
+ attribute \src "ls180.v:7964.9-7964.44"
case 1'1
assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1
- assign $0\main_tx_busy[0:0] 1'0
- assign $0\main_sink_ready[0:0] 1'1
- attribute \src "ls180.v:7922.9-7922.13"
+ assign $0\main_uart_phy_tx_busy[0:0] 1'0
+ assign $0\main_uart_phy_sink_ready[0:0] 1'1
+ attribute \src "ls180.v:7968.9-7968.13"
case
- assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] \main_tx_reg [0]
- assign $0\main_tx_reg[7:0] { 1'0 \main_tx_reg [7:1] }
+ assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] \main_uart_phy_tx_reg [0]
+ assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] }
end
end
case
end
end
- attribute \src "ls180.v:7929.2-7933.5"
- switch \main_tx_busy
- attribute \src "ls180.v:7929.6-7929.18"
+ attribute \src "ls180.v:7975.2-7979.5"
+ switch \main_uart_phy_tx_busy
+ attribute \src "ls180.v:7975.6-7975.27"
case 1'1
- assign { $0\main_uart_clk_txen[0:0] $0\main_phase_accumulator_tx[31:0] } $add$ls180.v:7930$2541_Y
- attribute \src "ls180.v:7931.6-7931.10"
+ assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7976$2551_Y
+ attribute \src "ls180.v:7977.6-7977.10"
case
- assign { $0\main_uart_clk_txen[0:0] $0\main_phase_accumulator_tx[31:0] } { 1'0 \main_storage }
+ assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage }
end
- attribute \src "ls180.v:7936.2-7960.5"
- switch $not$ls180.v:7936$2542_Y
- attribute \src "ls180.v:7936.6-7936.21"
+ attribute \src "ls180.v:7982.2-8006.5"
+ switch $not$ls180.v:7982$2552_Y
+ attribute \src "ls180.v:7982.6-7982.30"
case 1'1
- attribute \src "ls180.v:7937.3-7940.6"
- switch $and$ls180.v:7937$2544_Y
- attribute \src "ls180.v:7937.7-7937.31"
+ attribute \src "ls180.v:7983.3-7986.6"
+ switch $and$ls180.v:7983$2554_Y
+ attribute \src "ls180.v:7983.7-7983.49"
case 1'1
- assign $0\main_rx_busy[0:0] 1'1
- assign $0\main_rx_bitcount[3:0] 4'0000
+ assign $0\main_uart_phy_rx_busy[0:0] 1'1
+ assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000
case
end
- attribute \src "ls180.v:7941.6-7941.10"
+ attribute \src "ls180.v:7987.6-7987.10"
case
- attribute \src "ls180.v:7942.3-7959.6"
- switch \main_uart_clk_rxen
- attribute \src "ls180.v:7942.7-7942.25"
+ attribute \src "ls180.v:7988.3-8005.6"
+ switch \main_uart_phy_uart_clk_rxen
+ attribute \src "ls180.v:7988.7-7988.34"
case 1'1
- assign $0\main_rx_bitcount[3:0] $add$ls180.v:7943$2545_Y
- attribute \src "ls180.v:7944.4-7958.7"
- switch $eq$ls180.v:7944$2546_Y
- attribute \src "ls180.v:7944.8-7944.34"
+ assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:7989$2555_Y
+ attribute \src "ls180.v:7990.4-8004.7"
+ switch $eq$ls180.v:7990$2556_Y
+ attribute \src "ls180.v:7990.8-7990.43"
case 1'1
- attribute \src "ls180.v:7945.5-7947.8"
- switch \main_rx
- attribute \src "ls180.v:7945.9-7945.16"
+ attribute \src "ls180.v:7991.5-7993.8"
+ switch \main_uart_phy_rx
+ attribute \src "ls180.v:7991.9-7991.25"
case 1'1
- assign $0\main_rx_busy[0:0] 1'0
+ assign $0\main_uart_phy_rx_busy[0:0] 1'0
case
end
- attribute \src "ls180.v:7948.8-7948.12"
+ attribute \src "ls180.v:7994.8-7994.12"
case
- attribute \src "ls180.v:7949.5-7957.8"
- switch $eq$ls180.v:7949$2547_Y
- attribute \src "ls180.v:7949.9-7949.35"
+ attribute \src "ls180.v:7995.5-8003.8"
+ switch $eq$ls180.v:7995$2557_Y
+ attribute \src "ls180.v:7995.9-7995.44"
case 1'1
- assign $0\main_rx_busy[0:0] 1'0
- attribute \src "ls180.v:7951.6-7954.9"
- switch \main_rx
- attribute \src "ls180.v:7951.10-7951.17"
+ assign $0\main_uart_phy_rx_busy[0:0] 1'0
+ attribute \src "ls180.v:7997.6-8000.9"
+ switch \main_uart_phy_rx
+ attribute \src "ls180.v:7997.10-7997.26"
case 1'1
- assign $0\main_source_payload_data[7:0] \main_rx_reg
- assign $0\main_source_valid[0:0] 1'1
+ assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg
+ assign $0\main_uart_phy_source_valid[0:0] 1'1
case
end
- attribute \src "ls180.v:7955.9-7955.13"
+ attribute \src "ls180.v:8001.9-8001.13"
case
- assign $0\main_rx_reg[7:0] { \main_rx \main_rx_reg [7:1] }
+ assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] }
end
end
case
end
end
- attribute \src "ls180.v:7961.2-7965.5"
- switch \main_rx_busy
- attribute \src "ls180.v:7961.6-7961.18"
+ attribute \src "ls180.v:8007.2-8011.5"
+ switch \main_uart_phy_rx_busy
+ attribute \src "ls180.v:8007.6-8007.27"
case 1'1
- assign { $0\main_uart_clk_rxen[0:0] $0\main_phase_accumulator_rx[31:0] } $add$ls180.v:7962$2548_Y
- attribute \src "ls180.v:7963.6-7963.10"
+ assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8008$2558_Y
+ attribute \src "ls180.v:8009.6-8009.10"
case
- assign { $0\main_uart_clk_rxen[0:0] $0\main_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000
+ assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000
end
- attribute \src "ls180.v:7966.2-7968.5"
+ attribute \src "ls180.v:8012.2-8014.5"
switch \main_uart_tx_clear
- attribute \src "ls180.v:7966.6-7966.24"
+ attribute \src "ls180.v:8012.6-8012.24"
case 1'1
assign $0\main_uart_tx_pending[0:0] 1'0
case
end
- attribute \src "ls180.v:7970.2-7972.5"
- switch $and$ls180.v:7970$2550_Y
- attribute \src "ls180.v:7970.6-7970.58"
+ attribute \src "ls180.v:8016.2-8018.5"
+ switch $and$ls180.v:8016$2560_Y
+ attribute \src "ls180.v:8016.6-8016.58"
case 1'1
assign $0\main_uart_tx_pending[0:0] 1'1
case
end
- attribute \src "ls180.v:7973.2-7975.5"
+ attribute \src "ls180.v:8019.2-8021.5"
switch \main_uart_rx_clear
- attribute \src "ls180.v:7973.6-7973.24"
+ attribute \src "ls180.v:8019.6-8019.24"
case 1'1
assign $0\main_uart_rx_pending[0:0] 1'0
case
end
- attribute \src "ls180.v:7977.2-7979.5"
- switch $and$ls180.v:7977$2552_Y
- attribute \src "ls180.v:7977.6-7977.58"
+ attribute \src "ls180.v:8023.2-8025.5"
+ switch $and$ls180.v:8023$2562_Y
+ attribute \src "ls180.v:8023.6-8023.58"
case 1'1
assign $0\main_uart_rx_pending[0:0] 1'1
case
end
- attribute \src "ls180.v:7980.2-7986.5"
+ attribute \src "ls180.v:8026.2-8032.5"
switch \main_uart_tx_fifo_syncfifo_re
- attribute \src "ls180.v:7980.6-7980.35"
+ attribute \src "ls180.v:8026.6-8026.35"
case 1'1
assign $0\main_uart_tx_fifo_readable[0:0] 1'1
- attribute \src "ls180.v:7982.6-7982.10"
+ attribute \src "ls180.v:8028.6-8028.10"
case
- attribute \src "ls180.v:7983.3-7985.6"
+ attribute \src "ls180.v:8029.3-8031.6"
switch \main_uart_tx_fifo_re
- attribute \src "ls180.v:7983.7-7983.27"
+ attribute \src "ls180.v:8029.7-8029.27"
case 1'1
assign $0\main_uart_tx_fifo_readable[0:0] 1'0
case
end
end
- attribute \src "ls180.v:7987.2-7989.5"
- switch $and$ls180.v:7987$2555_Y
- attribute \src "ls180.v:7987.6-7987.108"
+ attribute \src "ls180.v:8033.2-8035.5"
+ switch $and$ls180.v:8033$2565_Y
+ attribute \src "ls180.v:8033.6-8033.108"
case 1'1
- assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:7988$2556_Y
+ assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8034$2566_Y
case
end
- attribute \src "ls180.v:7990.2-7992.5"
+ attribute \src "ls180.v:8036.2-8038.5"
switch \main_uart_tx_fifo_do_read
- attribute \src "ls180.v:7990.6-7990.31"
+ attribute \src "ls180.v:8036.6-8036.31"
case 1'1
- assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:7991$2557_Y
+ assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8037$2567_Y
case
end
- attribute \src "ls180.v:7993.2-8001.5"
- switch $and$ls180.v:7993$2560_Y
- attribute \src "ls180.v:7993.6-7993.108"
+ attribute \src "ls180.v:8039.2-8047.5"
+ switch $and$ls180.v:8039$2570_Y
+ attribute \src "ls180.v:8039.6-8039.108"
case 1'1
- attribute \src "ls180.v:7994.3-7996.6"
- switch $not$ls180.v:7994$2561_Y
- attribute \src "ls180.v:7994.7-7994.35"
+ attribute \src "ls180.v:8040.3-8042.6"
+ switch $not$ls180.v:8040$2571_Y
+ attribute \src "ls180.v:8040.7-8040.35"
case 1'1
- assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:7995$2562_Y
+ assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8041$2572_Y
case
end
- attribute \src "ls180.v:7997.6-7997.10"
+ attribute \src "ls180.v:8043.6-8043.10"
case
- attribute \src "ls180.v:7998.3-8000.6"
+ attribute \src "ls180.v:8044.3-8046.6"
switch \main_uart_tx_fifo_do_read
- attribute \src "ls180.v:7998.7-7998.32"
+ attribute \src "ls180.v:8044.7-8044.32"
case 1'1
- assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:7999$2563_Y
+ assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8045$2573_Y
case
end
end
- attribute \src "ls180.v:8002.2-8008.5"
+ attribute \src "ls180.v:8048.2-8054.5"
switch \main_uart_rx_fifo_syncfifo_re
- attribute \src "ls180.v:8002.6-8002.35"
+ attribute \src "ls180.v:8048.6-8048.35"
case 1'1
assign $0\main_uart_rx_fifo_readable[0:0] 1'1
- attribute \src "ls180.v:8004.6-8004.10"
+ attribute \src "ls180.v:8050.6-8050.10"
case
- attribute \src "ls180.v:8005.3-8007.6"
+ attribute \src "ls180.v:8051.3-8053.6"
switch \main_uart_rx_fifo_re
- attribute \src "ls180.v:8005.7-8005.27"
+ attribute \src "ls180.v:8051.7-8051.27"
case 1'1
assign $0\main_uart_rx_fifo_readable[0:0] 1'0
case
end
end
- attribute \src "ls180.v:8009.2-8011.5"
- switch $and$ls180.v:8009$2566_Y
- attribute \src "ls180.v:8009.6-8009.108"
+ attribute \src "ls180.v:8055.2-8057.5"
+ switch $and$ls180.v:8055$2576_Y
+ attribute \src "ls180.v:8055.6-8055.108"
case 1'1
- assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8010$2567_Y
+ assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8056$2577_Y
case
end
- attribute \src "ls180.v:8012.2-8014.5"
+ attribute \src "ls180.v:8058.2-8060.5"
switch \main_uart_rx_fifo_do_read
- attribute \src "ls180.v:8012.6-8012.31"
+ attribute \src "ls180.v:8058.6-8058.31"
case 1'1
- assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8013$2568_Y
+ assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8059$2578_Y
case
end
- attribute \src "ls180.v:8015.2-8023.5"
- switch $and$ls180.v:8015$2571_Y
- attribute \src "ls180.v:8015.6-8015.108"
+ attribute \src "ls180.v:8061.2-8069.5"
+ switch $and$ls180.v:8061$2581_Y
+ attribute \src "ls180.v:8061.6-8061.108"
case 1'1
- attribute \src "ls180.v:8016.3-8018.6"
- switch $not$ls180.v:8016$2572_Y
- attribute \src "ls180.v:8016.7-8016.35"
+ attribute \src "ls180.v:8062.3-8064.6"
+ switch $not$ls180.v:8062$2582_Y
+ attribute \src "ls180.v:8062.7-8062.35"
case 1'1
- assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8017$2573_Y
+ assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8063$2583_Y
case
end
- attribute \src "ls180.v:8019.6-8019.10"
+ attribute \src "ls180.v:8065.6-8065.10"
case
- attribute \src "ls180.v:8020.3-8022.6"
+ attribute \src "ls180.v:8066.3-8068.6"
switch \main_uart_rx_fifo_do_read
- attribute \src "ls180.v:8020.7-8020.32"
+ attribute \src "ls180.v:8066.7-8066.32"
case 1'1
- assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8021$2574_Y
+ assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8067$2584_Y
case
end
end
- attribute \src "ls180.v:8024.2-8037.5"
+ attribute \src "ls180.v:8070.2-8083.5"
switch \main_uart_reset
- attribute \src "ls180.v:8024.6-8024.21"
+ attribute \src "ls180.v:8070.6-8070.21"
case 1'1
assign $0\main_uart_tx_pending[0:0] 1'0
assign $0\main_uart_tx_old_trigger[0:0] 1'0
assign $0\main_uart_rx_fifo_consume[3:0] 4'0000
case
end
- attribute \src "ls180.v:8039.2-8046.5"
+ attribute \src "ls180.v:8085.2-8092.5"
switch \main_spi_master_clk_rise
- attribute \src "ls180.v:8039.6-8039.30"
+ attribute \src "ls180.v:8085.6-8085.30"
case 1'1
assign $0\spi_master_clk[0:0] \main_spi_master_clk_enable
- attribute \src "ls180.v:8041.6-8041.10"
+ attribute \src "ls180.v:8087.6-8087.10"
case
- attribute \src "ls180.v:8042.3-8045.6"
+ attribute \src "ls180.v:8088.3-8091.6"
switch \main_spi_master_clk_fall
- attribute \src "ls180.v:8042.7-8042.31"
+ attribute \src "ls180.v:8088.7-8088.31"
case 1'1
assign $0\main_spi_master_clk_divider1[15:0] 16'0000000000000000
assign $0\spi_master_clk[0:0] 1'0
case
end
end
- attribute \src "ls180.v:8048.2-8058.5"
+ attribute \src "ls180.v:8094.2-8104.5"
switch \main_spi_master_mosi_latch
- attribute \src "ls180.v:8048.6-8048.32"
+ attribute \src "ls180.v:8094.6-8094.32"
case 1'1
assign $0\main_spi_master_mosi_data[7:0] \main_spi_master_mosi
assign $0\main_spi_master_mosi_sel[2:0] 3'111
- attribute \src "ls180.v:8051.6-8051.10"
+ attribute \src "ls180.v:8097.6-8097.10"
case
- attribute \src "ls180.v:8052.3-8057.6"
+ attribute \src "ls180.v:8098.3-8103.6"
switch \main_spi_master_clk_fall
- attribute \src "ls180.v:8052.7-8052.31"
+ attribute \src "ls180.v:8098.7-8098.31"
case 1'1
- assign $0\main_spi_master_mosi_sel[2:0] $sub$ls180.v:8056$2579_Y
- attribute \src "ls180.v:8053.4-8055.7"
+ assign $0\main_spi_master_mosi_sel[2:0] $sub$ls180.v:8102$2589_Y
+ attribute \src "ls180.v:8099.4-8101.7"
switch \main_spi_master_cs_enable
- attribute \src "ls180.v:8053.8-8053.33"
+ attribute \src "ls180.v:8099.8-8099.33"
case 1'1
assign $0\spi_master_mosi[0:0] \builder_sync_f_array_muxed0
case
case
end
end
- attribute \src "ls180.v:8059.2-8065.5"
+ attribute \src "ls180.v:8105.2-8111.5"
switch \main_spi_master_clk_rise
- attribute \src "ls180.v:8059.6-8059.30"
+ attribute \src "ls180.v:8105.6-8105.30"
case 1'1
- attribute \src "ls180.v:8060.3-8064.6"
+ attribute \src "ls180.v:8106.3-8110.6"
switch \main_spi_master_loopback
- attribute \src "ls180.v:8060.7-8060.31"
+ attribute \src "ls180.v:8106.7-8106.31"
case 1'1
assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_mosi }
- attribute \src "ls180.v:8062.7-8062.11"
+ attribute \src "ls180.v:8108.7-8108.11"
case
assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_miso }
end
case
end
- attribute \src "ls180.v:8066.2-8068.5"
+ attribute \src "ls180.v:8112.2-8114.5"
switch \main_spi_master_miso_latch
- attribute \src "ls180.v:8066.6-8066.32"
+ attribute \src "ls180.v:8112.6-8112.32"
case 1'1
assign $0\main_spi_master_miso[7:0] \main_spi_master_miso_data
case
end
- attribute \src "ls180.v:8070.2-8072.5"
+ attribute \src "ls180.v:8116.2-8118.5"
switch \main_spi_master_count_spimaster0_next_value_ce
- attribute \src "ls180.v:8070.6-8070.52"
+ attribute \src "ls180.v:8116.6-8116.52"
case 1'1
assign $0\main_spi_master_count[2:0] \main_spi_master_count_spimaster0_next_value
case
end
- attribute \src "ls180.v:8073.2-8086.5"
+ attribute \src "ls180.v:8119.2-8132.5"
switch \main_pwm0_enable
- attribute \src "ls180.v:8073.6-8073.22"
+ attribute \src "ls180.v:8119.6-8119.22"
case 1'1
- assign $0\main_pwm0_counter[31:0] $add$ls180.v:8074$2580_Y
- attribute \src "ls180.v:8075.3-8079.6"
- switch $lt$ls180.v:8075$2581_Y
- attribute \src "ls180.v:8075.7-8075.44"
+ assign $0\main_pwm0_counter[31:0] $add$ls180.v:8120$2590_Y
+ attribute \src "ls180.v:8121.3-8125.6"
+ switch $lt$ls180.v:8121$2591_Y
+ attribute \src "ls180.v:8121.7-8121.44"
case 1'1
assign $0\pwm0[0:0] 1'1
- attribute \src "ls180.v:8077.7-8077.11"
+ attribute \src "ls180.v:8123.7-8123.11"
case
assign $0\pwm0[0:0] 1'0
end
- attribute \src "ls180.v:8080.3-8082.6"
- switch $ge$ls180.v:8080$2583_Y
- attribute \src "ls180.v:8080.7-8080.55"
+ attribute \src "ls180.v:8126.3-8128.6"
+ switch $ge$ls180.v:8126$2593_Y
+ attribute \src "ls180.v:8126.7-8126.55"
case 1'1
assign $0\main_pwm0_counter[31:0] 0
case
end
- attribute \src "ls180.v:8083.6-8083.10"
+ attribute \src "ls180.v:8129.6-8129.10"
case
assign $0\main_pwm0_counter[31:0] 0
assign $0\pwm0[0:0] 1'0
end
- attribute \src "ls180.v:8087.2-8100.5"
+ attribute \src "ls180.v:8133.2-8146.5"
switch \main_pwm1_enable
- attribute \src "ls180.v:8087.6-8087.22"
+ attribute \src "ls180.v:8133.6-8133.22"
case 1'1
- assign $0\main_pwm1_counter[31:0] $add$ls180.v:8088$2584_Y
- attribute \src "ls180.v:8089.3-8093.6"
- switch $lt$ls180.v:8089$2585_Y
- attribute \src "ls180.v:8089.7-8089.44"
+ assign $0\main_pwm1_counter[31:0] $add$ls180.v:8134$2594_Y
+ attribute \src "ls180.v:8135.3-8139.6"
+ switch $lt$ls180.v:8135$2595_Y
+ attribute \src "ls180.v:8135.7-8135.44"
case 1'1
assign $0\pwm1[0:0] 1'1
- attribute \src "ls180.v:8091.7-8091.11"
+ attribute \src "ls180.v:8137.7-8137.11"
case
assign $0\pwm1[0:0] 1'0
end
- attribute \src "ls180.v:8094.3-8096.6"
- switch $ge$ls180.v:8094$2587_Y
- attribute \src "ls180.v:8094.7-8094.55"
+ attribute \src "ls180.v:8140.3-8142.6"
+ switch $ge$ls180.v:8140$2597_Y
+ attribute \src "ls180.v:8140.7-8140.55"
case 1'1
assign $0\main_pwm1_counter[31:0] 0
case
end
- attribute \src "ls180.v:8097.6-8097.10"
+ attribute \src "ls180.v:8143.6-8143.10"
case
assign $0\main_pwm1_counter[31:0] 0
assign $0\pwm1[0:0] 1'0
end
- attribute \src "ls180.v:8101.2-8103.5"
- switch $not$ls180.v:8101$2588_Y
- attribute \src "ls180.v:8101.6-8101.32"
+ attribute \src "ls180.v:8147.2-8149.5"
+ switch $not$ls180.v:8147$2598_Y
+ attribute \src "ls180.v:8147.6-8147.32"
case 1'1
- assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8102$2589_Y
+ assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8148$2599_Y
case
end
- attribute \src "ls180.v:8107.2-8109.5"
+ attribute \src "ls180.v:8153.2-8155.5"
switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce
- attribute \src "ls180.v:8107.6-8107.57"
+ attribute \src "ls180.v:8153.6-8153.57"
case 1'1
assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value
case
end
- attribute \src "ls180.v:8111.2-8113.5"
+ attribute \src "ls180.v:8157.2-8159.5"
switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce
- attribute \src "ls180.v:8111.6-8111.57"
+ attribute \src "ls180.v:8157.6-8157.57"
case 1'1
assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value
case
end
- attribute \src "ls180.v:8114.2-8116.5"
+ attribute \src "ls180.v:8160.2-8162.5"
switch \main_sdphy_cmdr_cmdr_pads_in_valid
- attribute \src "ls180.v:8114.6-8114.40"
+ attribute \src "ls180.v:8160.6-8160.40"
case 1'1
- assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8115$2590_Y
+ assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8161$2600_Y
case
end
- attribute \src "ls180.v:8117.2-8119.5"
+ attribute \src "ls180.v:8163.2-8165.5"
switch \main_sdphy_cmdr_cmdr_converter_source_ready
- attribute \src "ls180.v:8117.6-8117.49"
+ attribute \src "ls180.v:8163.6-8163.49"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
case
end
- attribute \src "ls180.v:8120.2-8127.5"
+ attribute \src "ls180.v:8166.2-8173.5"
switch \main_sdphy_cmdr_cmdr_converter_load_part
- attribute \src "ls180.v:8120.6-8120.46"
+ attribute \src "ls180.v:8166.6-8166.46"
case 1'1
- attribute \src "ls180.v:8121.3-8126.6"
- switch $or$ls180.v:8121$2592_Y
- attribute \src "ls180.v:8121.7-8121.98"
+ attribute \src "ls180.v:8167.3-8172.6"
+ switch $or$ls180.v:8167$2602_Y
+ attribute \src "ls180.v:8167.7-8167.98"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1
- attribute \src "ls180.v:8124.7-8124.11"
+ attribute \src "ls180.v:8170.7-8170.11"
case
- assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8125$2593_Y
+ assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8171$2603_Y
end
case
end
- attribute \src "ls180.v:8128.2-8141.5"
- switch $and$ls180.v:8128$2594_Y
- attribute \src "ls180.v:8128.6-8128.97"
+ attribute \src "ls180.v:8174.2-8187.5"
+ switch $and$ls180.v:8174$2604_Y
+ attribute \src "ls180.v:8174.6-8174.97"
case 1'1
- attribute \src "ls180.v:8129.3-8135.6"
- switch $and$ls180.v:8129$2595_Y
- attribute \src "ls180.v:8129.7-8129.94"
+ attribute \src "ls180.v:8175.3-8181.6"
+ switch $and$ls180.v:8175$2605_Y
+ attribute \src "ls180.v:8175.7-8175.94"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first
assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last
- attribute \src "ls180.v:8132.7-8132.11"
+ attribute \src "ls180.v:8178.7-8178.11"
case
assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0
assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0
end
- attribute \src "ls180.v:8136.6-8136.10"
+ attribute \src "ls180.v:8182.6-8182.10"
case
- attribute \src "ls180.v:8137.3-8140.6"
- switch $and$ls180.v:8137$2596_Y
- attribute \src "ls180.v:8137.7-8137.94"
+ attribute \src "ls180.v:8183.3-8186.6"
+ switch $and$ls180.v:8183$2606_Y
+ attribute \src "ls180.v:8183.7-8183.94"
case 1'1
- assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8138$2597_Y
- assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8139$2598_Y
+ assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8184$2607_Y
+ assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8185$2608_Y
case
end
end
- attribute \src "ls180.v:8142.2-8169.5"
+ attribute \src "ls180.v:8188.2-8215.5"
switch \main_sdphy_cmdr_cmdr_converter_load_part
- attribute \src "ls180.v:8142.6-8142.46"
+ attribute \src "ls180.v:8188.6-8188.46"
case 1'1
- attribute \src "ls180.v:8143.3-8168.10"
+ attribute \src "ls180.v:8189.3-8214.10"
switch \main_sdphy_cmdr_cmdr_converter_demux
attribute \src "ls180.v:0.0-0.0"
case 3'000
end
case
end
- attribute \src "ls180.v:8170.2-8172.5"
+ attribute \src "ls180.v:8216.2-8218.5"
switch \main_sdphy_cmdr_cmdr_converter_load_part
- attribute \src "ls180.v:8170.6-8170.46"
+ attribute \src "ls180.v:8216.6-8216.46"
case 1'1
- assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8171$2599_Y
+ assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8217$2609_Y
case
end
- attribute \src "ls180.v:8173.2-8178.5"
- switch $or$ls180.v:8173$2601_Y
- attribute \src "ls180.v:8173.6-8173.88"
+ attribute \src "ls180.v:8219.2-8224.5"
+ switch $or$ls180.v:8219$2611_Y
+ attribute \src "ls180.v:8219.6-8219.88"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid
assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first
assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data
case
end
- attribute \src "ls180.v:8179.2-8184.5"
+ attribute \src "ls180.v:8225.2-8230.5"
switch \main_sdphy_cmdr_cmdr_reset
- attribute \src "ls180.v:8179.6-8179.32"
+ attribute \src "ls180.v:8225.6-8225.32"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0
assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0
case
end
- attribute \src "ls180.v:8186.2-8188.5"
+ attribute \src "ls180.v:8232.2-8234.5"
switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0
- attribute \src "ls180.v:8186.6-8186.58"
+ attribute \src "ls180.v:8232.6-8232.58"
case 1'1
assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0
case
end
- attribute \src "ls180.v:8189.2-8191.5"
+ attribute \src "ls180.v:8235.2-8237.5"
switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1
- attribute \src "ls180.v:8189.6-8189.60"
+ attribute \src "ls180.v:8235.6-8235.60"
case 1'1
assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1
case
end
- attribute \src "ls180.v:8192.2-8194.5"
+ attribute \src "ls180.v:8238.2-8240.5"
switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2
- attribute \src "ls180.v:8192.6-8192.63"
+ attribute \src "ls180.v:8238.6-8238.63"
case 1'1
assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2
case
end
- attribute \src "ls180.v:8195.2-8197.5"
+ attribute \src "ls180.v:8241.2-8243.5"
switch \main_sdphy_dataw_crcr_pads_in_valid
- attribute \src "ls180.v:8195.6-8195.41"
+ attribute \src "ls180.v:8241.6-8241.41"
case 1'1
- assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8196$2602_Y
+ assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8242$2612_Y
case
end
- attribute \src "ls180.v:8198.2-8200.5"
+ attribute \src "ls180.v:8244.2-8246.5"
switch \main_sdphy_dataw_crcr_converter_source_ready
- attribute \src "ls180.v:8198.6-8198.50"
+ attribute \src "ls180.v:8244.6-8244.50"
case 1'1
assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
case
end
- attribute \src "ls180.v:8201.2-8208.5"
+ attribute \src "ls180.v:8247.2-8254.5"
switch \main_sdphy_dataw_crcr_converter_load_part
- attribute \src "ls180.v:8201.6-8201.47"
+ attribute \src "ls180.v:8247.6-8247.47"
case 1'1
- attribute \src "ls180.v:8202.3-8207.6"
- switch $or$ls180.v:8202$2604_Y
- attribute \src "ls180.v:8202.7-8202.100"
+ attribute \src "ls180.v:8248.3-8253.6"
+ switch $or$ls180.v:8248$2614_Y
+ attribute \src "ls180.v:8248.7-8248.100"
case 1'1
assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1
- attribute \src "ls180.v:8205.7-8205.11"
+ attribute \src "ls180.v:8251.7-8251.11"
case
- assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8206$2605_Y
+ assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8252$2615_Y
end
case
end
- attribute \src "ls180.v:8209.2-8222.5"
- switch $and$ls180.v:8209$2606_Y
- attribute \src "ls180.v:8209.6-8209.99"
+ attribute \src "ls180.v:8255.2-8268.5"
+ switch $and$ls180.v:8255$2616_Y
+ attribute \src "ls180.v:8255.6-8255.99"
case 1'1
- attribute \src "ls180.v:8210.3-8216.6"
- switch $and$ls180.v:8210$2607_Y
- attribute \src "ls180.v:8210.7-8210.96"
+ attribute \src "ls180.v:8256.3-8262.6"
+ switch $and$ls180.v:8256$2617_Y
+ attribute \src "ls180.v:8256.7-8256.96"
case 1'1
assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first
assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last
- attribute \src "ls180.v:8213.7-8213.11"
+ attribute \src "ls180.v:8259.7-8259.11"
case
assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0
assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0
end
- attribute \src "ls180.v:8217.6-8217.10"
+ attribute \src "ls180.v:8263.6-8263.10"
case
- attribute \src "ls180.v:8218.3-8221.6"
- switch $and$ls180.v:8218$2608_Y
- attribute \src "ls180.v:8218.7-8218.96"
+ attribute \src "ls180.v:8264.3-8267.6"
+ switch $and$ls180.v:8264$2618_Y
+ attribute \src "ls180.v:8264.7-8264.96"
case 1'1
- assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8219$2609_Y
- assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8220$2610_Y
+ assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8265$2619_Y
+ assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8266$2620_Y
case
end
end
- attribute \src "ls180.v:8223.2-8250.5"
+ attribute \src "ls180.v:8269.2-8296.5"
switch \main_sdphy_dataw_crcr_converter_load_part
- attribute \src "ls180.v:8223.6-8223.47"
+ attribute \src "ls180.v:8269.6-8269.47"
case 1'1
- attribute \src "ls180.v:8224.3-8249.10"
+ attribute \src "ls180.v:8270.3-8295.10"
switch \main_sdphy_dataw_crcr_converter_demux
attribute \src "ls180.v:0.0-0.0"
case 3'000
end
case
end
- attribute \src "ls180.v:8251.2-8253.5"
+ attribute \src "ls180.v:8297.2-8299.5"
switch \main_sdphy_dataw_crcr_converter_load_part
- attribute \src "ls180.v:8251.6-8251.47"
+ attribute \src "ls180.v:8297.6-8297.47"
case 1'1
- assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8252$2611_Y
+ assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8298$2621_Y
case
end
- attribute \src "ls180.v:8254.2-8259.5"
- switch $or$ls180.v:8254$2613_Y
- attribute \src "ls180.v:8254.6-8254.90"
+ attribute \src "ls180.v:8300.2-8305.5"
+ switch $or$ls180.v:8300$2623_Y
+ attribute \src "ls180.v:8300.6-8300.90"
case 1'1
assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid
assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first
assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data
case
end
- attribute \src "ls180.v:8260.2-8265.5"
+ attribute \src "ls180.v:8306.2-8311.5"
switch \main_sdphy_dataw_crcr_reset
- attribute \src "ls180.v:8260.6-8260.33"
+ attribute \src "ls180.v:8306.6-8306.33"
case 1'1
assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0
assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0
case
end
- attribute \src "ls180.v:8267.2-8269.5"
+ attribute \src "ls180.v:8313.2-8315.5"
switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce
- attribute \src "ls180.v:8267.6-8267.63"
+ attribute \src "ls180.v:8313.6-8313.63"
case 1'1
assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value
case
end
- attribute \src "ls180.v:8271.2-8273.5"
+ attribute \src "ls180.v:8317.2-8319.5"
switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce
- attribute \src "ls180.v:8271.6-8271.52"
+ attribute \src "ls180.v:8317.6-8317.52"
case 1'1
assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value
case
end
- attribute \src "ls180.v:8274.2-8276.5"
+ attribute \src "ls180.v:8320.2-8322.5"
switch \main_sdphy_datar_datar_pads_in_valid
- attribute \src "ls180.v:8274.6-8274.42"
+ attribute \src "ls180.v:8320.6-8320.42"
case 1'1
- assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8275$2614_Y
+ assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8321$2624_Y
case
end
- attribute \src "ls180.v:8277.2-8279.5"
+ attribute \src "ls180.v:8323.2-8325.5"
switch \main_sdphy_datar_datar_converter_source_ready
- attribute \src "ls180.v:8277.6-8277.51"
+ attribute \src "ls180.v:8323.6-8323.51"
case 1'1
assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
case
end
- attribute \src "ls180.v:8280.2-8287.5"
+ attribute \src "ls180.v:8326.2-8333.5"
switch \main_sdphy_datar_datar_converter_load_part
- attribute \src "ls180.v:8280.6-8280.48"
+ attribute \src "ls180.v:8326.6-8326.48"
case 1'1
- attribute \src "ls180.v:8281.3-8286.6"
- switch $or$ls180.v:8281$2616_Y
- attribute \src "ls180.v:8281.7-8281.102"
+ attribute \src "ls180.v:8327.3-8332.6"
+ switch $or$ls180.v:8327$2626_Y
+ attribute \src "ls180.v:8327.7-8327.102"
case 1'1
assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0
assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1
- attribute \src "ls180.v:8284.7-8284.11"
+ attribute \src "ls180.v:8330.7-8330.11"
case
- assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8285$2617_Y
+ assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8331$2627_Y
end
case
end
- attribute \src "ls180.v:8288.2-8301.5"
- switch $and$ls180.v:8288$2618_Y
- attribute \src "ls180.v:8288.6-8288.101"
+ attribute \src "ls180.v:8334.2-8347.5"
+ switch $and$ls180.v:8334$2628_Y
+ attribute \src "ls180.v:8334.6-8334.101"
case 1'1
- attribute \src "ls180.v:8289.3-8295.6"
- switch $and$ls180.v:8289$2619_Y
- attribute \src "ls180.v:8289.7-8289.98"
+ attribute \src "ls180.v:8335.3-8341.6"
+ switch $and$ls180.v:8335$2629_Y
+ attribute \src "ls180.v:8335.7-8335.98"
case 1'1
assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first
assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last
- attribute \src "ls180.v:8292.7-8292.11"
+ attribute \src "ls180.v:8338.7-8338.11"
case
assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0
assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0
end
- attribute \src "ls180.v:8296.6-8296.10"
+ attribute \src "ls180.v:8342.6-8342.10"
case
- attribute \src "ls180.v:8297.3-8300.6"
- switch $and$ls180.v:8297$2620_Y
- attribute \src "ls180.v:8297.7-8297.98"
+ attribute \src "ls180.v:8343.3-8346.6"
+ switch $and$ls180.v:8343$2630_Y
+ attribute \src "ls180.v:8343.7-8343.98"
case 1'1
- assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8298$2621_Y
- assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8299$2622_Y
+ assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8344$2631_Y
+ assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8345$2632_Y
case
end
end
- attribute \src "ls180.v:8302.2-8311.5"
+ attribute \src "ls180.v:8348.2-8357.5"
switch \main_sdphy_datar_datar_converter_load_part
- attribute \src "ls180.v:8302.6-8302.48"
+ attribute \src "ls180.v:8348.6-8348.48"
case 1'1
- attribute \src "ls180.v:8303.3-8310.10"
+ attribute \src "ls180.v:8349.3-8356.10"
switch \main_sdphy_datar_datar_converter_demux
attribute \src "ls180.v:0.0-0.0"
case 1'0
end
case
end
- attribute \src "ls180.v:8312.2-8314.5"
+ attribute \src "ls180.v:8358.2-8360.5"
switch \main_sdphy_datar_datar_converter_load_part
- attribute \src "ls180.v:8312.6-8312.48"
+ attribute \src "ls180.v:8358.6-8358.48"
case 1'1
- assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8313$2623_Y
+ assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8359$2633_Y
case
end
- attribute \src "ls180.v:8315.2-8320.5"
- switch $or$ls180.v:8315$2625_Y
- attribute \src "ls180.v:8315.6-8315.92"
+ attribute \src "ls180.v:8361.2-8366.5"
+ switch $or$ls180.v:8361$2635_Y
+ attribute \src "ls180.v:8361.6-8361.92"
case 1'1
assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid
assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first
assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data
case
end
- attribute \src "ls180.v:8321.2-8326.5"
+ attribute \src "ls180.v:8367.2-8372.5"
switch \main_sdphy_datar_datar_reset
- attribute \src "ls180.v:8321.6-8321.34"
+ attribute \src "ls180.v:8367.6-8367.34"
case 1'1
assign $0\main_sdphy_datar_datar_run[0:0] 1'0
assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0
assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0
case
end
- attribute \src "ls180.v:8328.2-8330.5"
+ attribute \src "ls180.v:8374.2-8376.5"
switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0
- attribute \src "ls180.v:8328.6-8328.60"
+ attribute \src "ls180.v:8374.6-8374.60"
case 1'1
assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0
case
end
- attribute \src "ls180.v:8331.2-8333.5"
+ attribute \src "ls180.v:8377.2-8379.5"
switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1
- attribute \src "ls180.v:8331.6-8331.62"
+ attribute \src "ls180.v:8377.6-8377.62"
case 1'1
assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1
case
end
- attribute \src "ls180.v:8334.2-8336.5"
+ attribute \src "ls180.v:8380.2-8382.5"
switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2
- attribute \src "ls180.v:8334.6-8334.66"
+ attribute \src "ls180.v:8380.6-8380.66"
case 1'1
assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2
case
end
- attribute \src "ls180.v:8337.2-8343.5"
+ attribute \src "ls180.v:8383.2-8389.5"
switch \main_sdcore_crc7_inserter_clr
- attribute \src "ls180.v:8337.6-8337.35"
+ attribute \src "ls180.v:8383.6-8383.35"
case 1'1
assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000
- attribute \src "ls180.v:8339.6-8339.10"
+ attribute \src "ls180.v:8385.6-8385.10"
case
- attribute \src "ls180.v:8340.3-8342.6"
+ attribute \src "ls180.v:8386.3-8388.6"
switch \main_sdcore_crc7_inserter_enable
- attribute \src "ls180.v:8340.7-8340.39"
+ attribute \src "ls180.v:8386.7-8386.39"
case 1'1
assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40
case
end
end
- attribute \src "ls180.v:8344.2-8350.5"
+ attribute \src "ls180.v:8390.2-8396.5"
switch \main_sdcore_crc16_inserter_crc0_clr
- attribute \src "ls180.v:8344.6-8344.41"
+ attribute \src "ls180.v:8390.6-8390.41"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8346.6-8346.10"
+ attribute \src "ls180.v:8392.6-8392.10"
case
- attribute \src "ls180.v:8347.3-8349.6"
+ attribute \src "ls180.v:8393.3-8395.6"
switch \main_sdcore_crc16_inserter_crc0_enable
- attribute \src "ls180.v:8347.7-8347.45"
+ attribute \src "ls180.v:8393.7-8393.45"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2
case
end
end
- attribute \src "ls180.v:8351.2-8357.5"
+ attribute \src "ls180.v:8397.2-8403.5"
switch \main_sdcore_crc16_inserter_crc1_clr
- attribute \src "ls180.v:8351.6-8351.41"
+ attribute \src "ls180.v:8397.6-8397.41"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8353.6-8353.10"
+ attribute \src "ls180.v:8399.6-8399.10"
case
- attribute \src "ls180.v:8354.3-8356.6"
+ attribute \src "ls180.v:8400.3-8402.6"
switch \main_sdcore_crc16_inserter_crc1_enable
- attribute \src "ls180.v:8354.7-8354.45"
+ attribute \src "ls180.v:8400.7-8400.45"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2
case
end
end
- attribute \src "ls180.v:8358.2-8364.5"
+ attribute \src "ls180.v:8404.2-8410.5"
switch \main_sdcore_crc16_inserter_crc2_clr
- attribute \src "ls180.v:8358.6-8358.41"
+ attribute \src "ls180.v:8404.6-8404.41"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8360.6-8360.10"
+ attribute \src "ls180.v:8406.6-8406.10"
case
- attribute \src "ls180.v:8361.3-8363.6"
+ attribute \src "ls180.v:8407.3-8409.6"
switch \main_sdcore_crc16_inserter_crc2_enable
- attribute \src "ls180.v:8361.7-8361.45"
+ attribute \src "ls180.v:8407.7-8407.45"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2
case
end
end
- attribute \src "ls180.v:8365.2-8371.5"
+ attribute \src "ls180.v:8411.2-8417.5"
switch \main_sdcore_crc16_inserter_crc3_clr
- attribute \src "ls180.v:8365.6-8365.41"
+ attribute \src "ls180.v:8411.6-8411.41"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8367.6-8367.10"
+ attribute \src "ls180.v:8413.6-8413.10"
case
- attribute \src "ls180.v:8368.3-8370.6"
+ attribute \src "ls180.v:8414.3-8416.6"
switch \main_sdcore_crc16_inserter_crc3_enable
- attribute \src "ls180.v:8368.7-8368.45"
+ attribute \src "ls180.v:8414.7-8414.45"
case 1'1
assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2
case
end
end
- attribute \src "ls180.v:8373.2-8375.5"
+ attribute \src "ls180.v:8419.2-8421.5"
switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0
- attribute \src "ls180.v:8373.6-8373.82"
+ attribute \src "ls180.v:8419.6-8419.82"
case 1'1
assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0
case
end
- attribute \src "ls180.v:8376.2-8378.5"
+ attribute \src "ls180.v:8422.2-8424.5"
switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1
- attribute \src "ls180.v:8376.6-8376.82"
+ attribute \src "ls180.v:8422.6-8422.82"
case 1'1
assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1
case
end
- attribute \src "ls180.v:8379.2-8381.5"
+ attribute \src "ls180.v:8425.2-8427.5"
switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2
- attribute \src "ls180.v:8379.6-8379.82"
+ attribute \src "ls180.v:8425.6-8425.82"
case 1'1
assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2
case
end
- attribute \src "ls180.v:8382.2-8384.5"
+ attribute \src "ls180.v:8428.2-8430.5"
switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3
- attribute \src "ls180.v:8382.6-8382.82"
+ attribute \src "ls180.v:8428.6-8428.82"
case 1'1
assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3
case
end
- attribute \src "ls180.v:8385.2-8387.5"
+ attribute \src "ls180.v:8431.2-8433.5"
switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4
- attribute \src "ls180.v:8385.6-8385.78"
+ attribute \src "ls180.v:8431.6-8431.78"
case 1'1
assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4
case
end
- attribute \src "ls180.v:8388.2-8390.5"
- switch $and$ls180.v:8388$2626_Y
- attribute \src "ls180.v:8388.6-8388.83"
+ attribute \src "ls180.v:8434.2-8436.5"
+ switch $and$ls180.v:8434$2636_Y
+ attribute \src "ls180.v:8434.6-8434.83"
case 1'1
assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc
case
end
- attribute \src "ls180.v:8391.2-8393.5"
- switch $and$ls180.v:8391$2627_Y
- attribute \src "ls180.v:8391.6-8391.83"
+ attribute \src "ls180.v:8437.2-8439.5"
+ switch $and$ls180.v:8437$2637_Y
+ attribute \src "ls180.v:8437.6-8437.83"
case 1'1
assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc
case
end
- attribute \src "ls180.v:8394.2-8396.5"
- switch $and$ls180.v:8394$2628_Y
- attribute \src "ls180.v:8394.6-8394.83"
+ attribute \src "ls180.v:8440.2-8442.5"
+ switch $and$ls180.v:8440$2638_Y
+ attribute \src "ls180.v:8440.6-8440.83"
case 1'1
assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc
case
end
- attribute \src "ls180.v:8397.2-8399.5"
- switch $and$ls180.v:8397$2629_Y
- attribute \src "ls180.v:8397.6-8397.83"
+ attribute \src "ls180.v:8443.2-8445.5"
+ switch $and$ls180.v:8443$2639_Y
+ attribute \src "ls180.v:8443.6-8443.83"
case 1'1
assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc
case
end
- attribute \src "ls180.v:8400.2-8404.5"
- switch $and$ls180.v:8400$2630_Y
- attribute \src "ls180.v:8400.6-8400.83"
+ attribute \src "ls180.v:8446.2-8450.5"
+ switch $and$ls180.v:8446$2640_Y
+ attribute \src "ls180.v:8446.6-8446.83"
case 1'1
assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] }
assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13]
assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12]
case
end
- attribute \src "ls180.v:8405.2-8409.5"
- switch $and$ls180.v:8405$2631_Y
- attribute \src "ls180.v:8405.6-8405.83"
+ attribute \src "ls180.v:8451.2-8455.5"
+ switch $and$ls180.v:8451$2641_Y
+ attribute \src "ls180.v:8451.6-8451.83"
case 1'1
assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] }
assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13]
assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12]
case
end
- attribute \src "ls180.v:8410.2-8414.5"
- switch $and$ls180.v:8410$2632_Y
- attribute \src "ls180.v:8410.6-8410.83"
+ attribute \src "ls180.v:8456.2-8460.5"
+ switch $and$ls180.v:8456$2642_Y
+ attribute \src "ls180.v:8456.6-8456.83"
case 1'1
assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] }
assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13]
assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12]
case
end
- attribute \src "ls180.v:8415.2-8419.5"
- switch $and$ls180.v:8415$2633_Y
- attribute \src "ls180.v:8415.6-8415.83"
+ attribute \src "ls180.v:8461.2-8465.5"
+ switch $and$ls180.v:8461$2643_Y
+ attribute \src "ls180.v:8461.6-8461.83"
case 1'1
assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] }
assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13]
assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12]
case
end
- attribute \src "ls180.v:8420.2-8428.5"
- switch $and$ls180.v:8420$2634_Y
- attribute \src "ls180.v:8420.6-8420.83"
+ attribute \src "ls180.v:8466.2-8474.5"
+ switch $and$ls180.v:8466$2644_Y
+ attribute \src "ls180.v:8466.6-8466.83"
case 1'1
- attribute \src "ls180.v:8421.3-8427.6"
+ attribute \src "ls180.v:8467.3-8473.6"
switch \main_sdcore_crc16_checker_sink_last
- attribute \src "ls180.v:8421.7-8421.42"
+ attribute \src "ls180.v:8467.7-8467.42"
case 1'1
assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000
- attribute \src "ls180.v:8423.7-8423.11"
+ attribute \src "ls180.v:8469.7-8469.11"
case
- attribute \src "ls180.v:8424.4-8426.7"
- switch $ne$ls180.v:8424$2635_Y
- attribute \src "ls180.v:8424.8-8424.48"
+ attribute \src "ls180.v:8470.4-8472.7"
+ switch $ne$ls180.v:8470$2645_Y
+ attribute \src "ls180.v:8470.8-8470.48"
case 1'1
- assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8425$2636_Y
+ assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8471$2646_Y
case
end
end
case
end
- attribute \src "ls180.v:8429.2-8435.5"
+ attribute \src "ls180.v:8475.2-8481.5"
switch \main_sdcore_crc16_checker_crc0_clr
- attribute \src "ls180.v:8429.6-8429.40"
+ attribute \src "ls180.v:8475.6-8475.40"
case 1'1
assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8431.6-8431.10"
+ attribute \src "ls180.v:8477.6-8477.10"
case
- attribute \src "ls180.v:8432.3-8434.6"
+ attribute \src "ls180.v:8478.3-8480.6"
switch \main_sdcore_crc16_checker_crc0_enable
- attribute \src "ls180.v:8432.7-8432.44"
+ attribute \src "ls180.v:8478.7-8478.44"
case 1'1
assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2
case
end
end
- attribute \src "ls180.v:8436.2-8442.5"
+ attribute \src "ls180.v:8482.2-8488.5"
switch \main_sdcore_crc16_checker_crc1_clr
- attribute \src "ls180.v:8436.6-8436.40"
+ attribute \src "ls180.v:8482.6-8482.40"
case 1'1
assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8438.6-8438.10"
+ attribute \src "ls180.v:8484.6-8484.10"
case
- attribute \src "ls180.v:8439.3-8441.6"
+ attribute \src "ls180.v:8485.3-8487.6"
switch \main_sdcore_crc16_checker_crc1_enable
- attribute \src "ls180.v:8439.7-8439.44"
+ attribute \src "ls180.v:8485.7-8485.44"
case 1'1
assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2
case
end
end
- attribute \src "ls180.v:8443.2-8449.5"
+ attribute \src "ls180.v:8489.2-8495.5"
switch \main_sdcore_crc16_checker_crc2_clr
- attribute \src "ls180.v:8443.6-8443.40"
+ attribute \src "ls180.v:8489.6-8489.40"
case 1'1
assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8445.6-8445.10"
+ attribute \src "ls180.v:8491.6-8491.10"
case
- attribute \src "ls180.v:8446.3-8448.6"
+ attribute \src "ls180.v:8492.3-8494.6"
switch \main_sdcore_crc16_checker_crc2_enable
- attribute \src "ls180.v:8446.7-8446.44"
+ attribute \src "ls180.v:8492.7-8492.44"
case 1'1
assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2
case
end
end
- attribute \src "ls180.v:8450.2-8456.5"
+ attribute \src "ls180.v:8496.2-8502.5"
switch \main_sdcore_crc16_checker_crc3_clr
- attribute \src "ls180.v:8450.6-8450.40"
+ attribute \src "ls180.v:8496.6-8496.40"
case 1'1
assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
- attribute \src "ls180.v:8452.6-8452.10"
+ attribute \src "ls180.v:8498.6-8498.10"
case
- attribute \src "ls180.v:8453.3-8455.6"
+ attribute \src "ls180.v:8499.3-8501.6"
switch \main_sdcore_crc16_checker_crc3_enable
- attribute \src "ls180.v:8453.7-8453.44"
+ attribute \src "ls180.v:8499.7-8499.44"
case 1'1
assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2
case
end
end
- attribute \src "ls180.v:8458.2-8460.5"
+ attribute \src "ls180.v:8504.2-8506.5"
switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0
- attribute \src "ls180.v:8458.6-8458.52"
+ attribute \src "ls180.v:8504.6-8504.52"
case 1'1
assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0
case
end
- attribute \src "ls180.v:8461.2-8463.5"
+ attribute \src "ls180.v:8507.2-8509.5"
switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1
- attribute \src "ls180.v:8461.6-8461.53"
+ attribute \src "ls180.v:8507.6-8507.53"
case 1'1
assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1
case
end
- attribute \src "ls180.v:8464.2-8466.5"
+ attribute \src "ls180.v:8510.2-8512.5"
switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2
- attribute \src "ls180.v:8464.6-8464.53"
+ attribute \src "ls180.v:8510.6-8510.53"
case 1'1
assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2
case
end
- attribute \src "ls180.v:8467.2-8469.5"
+ attribute \src "ls180.v:8513.2-8515.5"
switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3
- attribute \src "ls180.v:8467.6-8467.54"
+ attribute \src "ls180.v:8513.6-8513.54"
case 1'1
assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3
case
end
- attribute \src "ls180.v:8470.2-8472.5"
+ attribute \src "ls180.v:8516.2-8518.5"
switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4
- attribute \src "ls180.v:8470.6-8470.53"
+ attribute \src "ls180.v:8516.6-8516.53"
case 1'1
assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4
case
end
- attribute \src "ls180.v:8473.2-8475.5"
+ attribute \src "ls180.v:8519.2-8521.5"
switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5
- attribute \src "ls180.v:8473.6-8473.55"
+ attribute \src "ls180.v:8519.6-8519.55"
case 1'1
assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5
case
end
- attribute \src "ls180.v:8476.2-8478.5"
+ attribute \src "ls180.v:8522.2-8524.5"
switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6
- attribute \src "ls180.v:8476.6-8476.54"
+ attribute \src "ls180.v:8522.6-8522.54"
case 1'1
assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6
case
end
- attribute \src "ls180.v:8479.2-8481.5"
+ attribute \src "ls180.v:8525.2-8527.5"
switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7
- attribute \src "ls180.v:8479.6-8479.56"
+ attribute \src "ls180.v:8525.6-8525.56"
case 1'1
assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7
case
end
- attribute \src "ls180.v:8482.2-8484.5"
+ attribute \src "ls180.v:8528.2-8530.5"
switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8
- attribute \src "ls180.v:8482.6-8482.63"
+ attribute \src "ls180.v:8528.6-8528.63"
case 1'1
assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8
case
end
- attribute \src "ls180.v:8485.2-8487.5"
- switch $and$ls180.v:8485$2639_Y
- attribute \src "ls180.v:8485.6-8485.120"
+ attribute \src "ls180.v:8531.2-8533.5"
+ switch $and$ls180.v:8531$2649_Y
+ attribute \src "ls180.v:8531.6-8531.120"
case 1'1
- assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8486$2640_Y
+ assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8532$2650_Y
case
end
- attribute \src "ls180.v:8488.2-8490.5"
+ attribute \src "ls180.v:8534.2-8536.5"
switch \main_sdblock2mem_fifo_do_read
- attribute \src "ls180.v:8488.6-8488.35"
+ attribute \src "ls180.v:8534.6-8534.35"
case 1'1
- assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8489$2641_Y
+ assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8535$2651_Y
case
end
- attribute \src "ls180.v:8491.2-8499.5"
- switch $and$ls180.v:8491$2644_Y
- attribute \src "ls180.v:8491.6-8491.120"
+ attribute \src "ls180.v:8537.2-8545.5"
+ switch $and$ls180.v:8537$2654_Y
+ attribute \src "ls180.v:8537.6-8537.120"
case 1'1
- attribute \src "ls180.v:8492.3-8494.6"
- switch $not$ls180.v:8492$2645_Y
- attribute \src "ls180.v:8492.7-8492.39"
+ attribute \src "ls180.v:8538.3-8540.6"
+ switch $not$ls180.v:8538$2655_Y
+ attribute \src "ls180.v:8538.7-8538.39"
case 1'1
- assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8493$2646_Y
+ assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8539$2656_Y
case
end
- attribute \src "ls180.v:8495.6-8495.10"
+ attribute \src "ls180.v:8541.6-8541.10"
case
- attribute \src "ls180.v:8496.3-8498.6"
+ attribute \src "ls180.v:8542.3-8544.6"
switch \main_sdblock2mem_fifo_do_read
- attribute \src "ls180.v:8496.7-8496.36"
+ attribute \src "ls180.v:8542.7-8542.36"
case 1'1
- assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8497$2647_Y
+ assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8543$2657_Y
case
end
end
- attribute \src "ls180.v:8500.2-8502.5"
+ attribute \src "ls180.v:8546.2-8548.5"
switch \main_sdblock2mem_converter_source_ready
- attribute \src "ls180.v:8500.6-8500.45"
+ attribute \src "ls180.v:8546.6-8546.45"
case 1'1
assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0
case
end
- attribute \src "ls180.v:8503.2-8510.5"
+ attribute \src "ls180.v:8549.2-8556.5"
switch \main_sdblock2mem_converter_load_part
- attribute \src "ls180.v:8503.6-8503.42"
+ attribute \src "ls180.v:8549.6-8549.42"
case 1'1
- attribute \src "ls180.v:8504.3-8509.6"
- switch $or$ls180.v:8504$2649_Y
- attribute \src "ls180.v:8504.7-8504.90"
+ attribute \src "ls180.v:8550.3-8555.6"
+ switch $or$ls180.v:8550$2659_Y
+ attribute \src "ls180.v:8550.7-8550.90"
case 1'1
assign $0\main_sdblock2mem_converter_demux[1:0] 2'00
assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1
- attribute \src "ls180.v:8507.7-8507.11"
+ attribute \src "ls180.v:8553.7-8553.11"
case
- assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8508$2650_Y
+ assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8554$2660_Y
end
case
end
- attribute \src "ls180.v:8511.2-8524.5"
- switch $and$ls180.v:8511$2651_Y
- attribute \src "ls180.v:8511.6-8511.89"
+ attribute \src "ls180.v:8557.2-8570.5"
+ switch $and$ls180.v:8557$2661_Y
+ attribute \src "ls180.v:8557.6-8557.89"
case 1'1
- attribute \src "ls180.v:8512.3-8518.6"
- switch $and$ls180.v:8512$2652_Y
- attribute \src "ls180.v:8512.7-8512.86"
+ attribute \src "ls180.v:8558.3-8564.6"
+ switch $and$ls180.v:8558$2662_Y
+ attribute \src "ls180.v:8558.7-8558.86"
case 1'1
assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first
assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last
- attribute \src "ls180.v:8515.7-8515.11"
+ attribute \src "ls180.v:8561.7-8561.11"
case
assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0
assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0
end
- attribute \src "ls180.v:8519.6-8519.10"
+ attribute \src "ls180.v:8565.6-8565.10"
case
- attribute \src "ls180.v:8520.3-8523.6"
- switch $and$ls180.v:8520$2653_Y
- attribute \src "ls180.v:8520.7-8520.86"
+ attribute \src "ls180.v:8566.3-8569.6"
+ switch $and$ls180.v:8566$2663_Y
+ attribute \src "ls180.v:8566.7-8566.86"
case 1'1
- assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8521$2654_Y
- assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8522$2655_Y
+ assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8567$2664_Y
+ assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8568$2665_Y
case
end
end
- attribute \src "ls180.v:8525.2-8540.5"
+ attribute \src "ls180.v:8571.2-8586.5"
switch \main_sdblock2mem_converter_load_part
- attribute \src "ls180.v:8525.6-8525.42"
+ attribute \src "ls180.v:8571.6-8571.42"
case 1'1
- attribute \src "ls180.v:8526.3-8539.10"
+ attribute \src "ls180.v:8572.3-8585.10"
switch \main_sdblock2mem_converter_demux
attribute \src "ls180.v:0.0-0.0"
case 2'00
end
case
end
- attribute \src "ls180.v:8541.2-8543.5"
+ attribute \src "ls180.v:8587.2-8589.5"
switch \main_sdblock2mem_converter_load_part
- attribute \src "ls180.v:8541.6-8541.42"
+ attribute \src "ls180.v:8587.6-8587.42"
case 1'1
- assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8542$2656_Y
+ assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8588$2666_Y
case
end
- attribute \src "ls180.v:8545.2-8547.5"
+ attribute \src "ls180.v:8591.2-8593.5"
switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce
- attribute \src "ls180.v:8545.6-8545.76"
+ attribute \src "ls180.v:8591.6-8591.76"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value
case
end
- attribute \src "ls180.v:8548.2-8551.5"
+ attribute \src "ls180.v:8594.2-8597.5"
switch \main_sdblock2mem_wishbonedmawriter_reset
- attribute \src "ls180.v:8548.6-8548.46"
+ attribute \src "ls180.v:8594.6-8594.46"
case 1'1
assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0
assign $0\builder_sdblock2memdma_state[1:0] 2'00
case
end
- attribute \src "ls180.v:8553.2-8555.5"
+ attribute \src "ls180.v:8599.2-8601.5"
switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce
- attribute \src "ls180.v:8553.6-8553.64"
+ attribute \src "ls180.v:8599.6-8599.64"
case 1'1
assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value
case
end
- attribute \src "ls180.v:8557.2-8559.5"
+ attribute \src "ls180.v:8603.2-8605.5"
switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce
- attribute \src "ls180.v:8557.6-8557.76"
+ attribute \src "ls180.v:8603.6-8603.76"
case 1'1
assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value
case
end
- attribute \src "ls180.v:8560.2-8563.5"
+ attribute \src "ls180.v:8606.2-8609.5"
switch \main_sdmem2block_dma_reset
- attribute \src "ls180.v:8560.6-8560.32"
+ attribute \src "ls180.v:8606.6-8606.32"
case 1'1
assign $0\main_sdmem2block_dma_offset[31:0] 0
assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
case
end
- attribute \src "ls180.v:8564.2-8570.5"
- switch $and$ls180.v:8564$2657_Y
- attribute \src "ls180.v:8564.6-8564.89"
+ attribute \src "ls180.v:8610.2-8616.5"
+ switch $and$ls180.v:8610$2667_Y
+ attribute \src "ls180.v:8610.6-8610.89"
case 1'1
- attribute \src "ls180.v:8565.3-8569.6"
+ attribute \src "ls180.v:8611.3-8615.6"
switch \main_sdmem2block_converter_last
- attribute \src "ls180.v:8565.7-8565.38"
+ attribute \src "ls180.v:8611.7-8611.38"
case 1'1
assign $0\main_sdmem2block_converter_mux[1:0] 2'00
- attribute \src "ls180.v:8567.7-8567.11"
+ attribute \src "ls180.v:8613.7-8613.11"
case
- assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8568$2658_Y
+ assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8614$2668_Y
end
case
end
- attribute \src "ls180.v:8571.2-8573.5"
- switch $and$ls180.v:8571$2661_Y
- attribute \src "ls180.v:8571.6-8571.120"
+ attribute \src "ls180.v:8617.2-8619.5"
+ switch $and$ls180.v:8617$2671_Y
+ attribute \src "ls180.v:8617.6-8617.120"
case 1'1
- assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8572$2662_Y
+ assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8618$2672_Y
case
end
- attribute \src "ls180.v:8574.2-8576.5"
+ attribute \src "ls180.v:8620.2-8622.5"
switch \main_sdmem2block_fifo_do_read
- attribute \src "ls180.v:8574.6-8574.35"
+ attribute \src "ls180.v:8620.6-8620.35"
case 1'1
- assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8575$2663_Y
+ assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8621$2673_Y
case
end
- attribute \src "ls180.v:8577.2-8585.5"
- switch $and$ls180.v:8577$2666_Y
- attribute \src "ls180.v:8577.6-8577.120"
+ attribute \src "ls180.v:8623.2-8631.5"
+ switch $and$ls180.v:8623$2676_Y
+ attribute \src "ls180.v:8623.6-8623.120"
case 1'1
- attribute \src "ls180.v:8578.3-8580.6"
- switch $not$ls180.v:8578$2667_Y
- attribute \src "ls180.v:8578.7-8578.39"
+ attribute \src "ls180.v:8624.3-8626.6"
+ switch $not$ls180.v:8624$2677_Y
+ attribute \src "ls180.v:8624.7-8624.39"
case 1'1
- assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8579$2668_Y
+ assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8625$2678_Y
case
end
- attribute \src "ls180.v:8581.6-8581.10"
+ attribute \src "ls180.v:8627.6-8627.10"
case
- attribute \src "ls180.v:8582.3-8584.6"
+ attribute \src "ls180.v:8628.3-8630.6"
switch \main_sdmem2block_fifo_do_read
- attribute \src "ls180.v:8582.7-8582.36"
+ attribute \src "ls180.v:8628.7-8628.36"
case 1'1
- assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8583$2669_Y
+ assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8629$2679_Y
case
end
end
- attribute \src "ls180.v:8587.2-8594.5"
+ attribute \src "ls180.v:8633.2-8640.5"
switch \libresocsim_clk_rise
- attribute \src "ls180.v:8587.6-8587.26"
+ attribute \src "ls180.v:8633.6-8633.26"
case 1'1
assign $0\spisdcard_clk[0:0] \libresocsim_clk_enable
- attribute \src "ls180.v:8589.6-8589.10"
+ attribute \src "ls180.v:8635.6-8635.10"
case
- attribute \src "ls180.v:8590.3-8593.6"
+ attribute \src "ls180.v:8636.3-8639.6"
switch \libresocsim_clk_fall
- attribute \src "ls180.v:8590.7-8590.27"
+ attribute \src "ls180.v:8636.7-8636.27"
case 1'1
assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000
assign $0\spisdcard_clk[0:0] 1'0
case
end
end
- attribute \src "ls180.v:8596.2-8606.5"
+ attribute \src "ls180.v:8642.2-8652.5"
switch \libresocsim_mosi_latch
- attribute \src "ls180.v:8596.6-8596.28"
+ attribute \src "ls180.v:8642.6-8642.28"
case 1'1
assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi
assign $0\libresocsim_mosi_sel[2:0] 3'111
- attribute \src "ls180.v:8599.6-8599.10"
+ attribute \src "ls180.v:8645.6-8645.10"
case
- attribute \src "ls180.v:8600.3-8605.6"
+ attribute \src "ls180.v:8646.3-8651.6"
switch \libresocsim_clk_fall
- attribute \src "ls180.v:8600.7-8600.27"
+ attribute \src "ls180.v:8646.7-8646.27"
case 1'1
- assign $0\libresocsim_mosi_sel[2:0] $sub$ls180.v:8604$2674_Y
- attribute \src "ls180.v:8601.4-8603.7"
+ assign $0\libresocsim_mosi_sel[2:0] $sub$ls180.v:8650$2684_Y
+ attribute \src "ls180.v:8647.4-8649.7"
switch \libresocsim_cs_enable
- attribute \src "ls180.v:8601.8-8601.29"
+ attribute \src "ls180.v:8647.8-8647.29"
case 1'1
assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed1
case
case
end
end
- attribute \src "ls180.v:8607.2-8613.5"
+ attribute \src "ls180.v:8653.2-8659.5"
switch \libresocsim_clk_rise
- attribute \src "ls180.v:8607.6-8607.26"
+ attribute \src "ls180.v:8653.6-8653.26"
case 1'1
- attribute \src "ls180.v:8608.3-8612.6"
+ attribute \src "ls180.v:8654.3-8658.6"
switch \libresocsim_loopback
- attribute \src "ls180.v:8608.7-8608.27"
+ attribute \src "ls180.v:8654.7-8654.27"
case 1'1
assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_mosi }
- attribute \src "ls180.v:8610.7-8610.11"
+ attribute \src "ls180.v:8656.7-8656.11"
case
assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_miso }
end
case
end
- attribute \src "ls180.v:8614.2-8616.5"
+ attribute \src "ls180.v:8660.2-8662.5"
switch \libresocsim_miso_latch
- attribute \src "ls180.v:8614.6-8614.28"
+ attribute \src "ls180.v:8660.6-8660.28"
case 1'1
assign $0\libresocsim_miso[7:0] \libresocsim_miso_data
case
end
- attribute \src "ls180.v:8618.2-8620.5"
+ attribute \src "ls180.v:8664.2-8666.5"
switch \libresocsim_count_spimaster1_next_value_ce
- attribute \src "ls180.v:8618.6-8618.48"
+ attribute \src "ls180.v:8664.6-8664.48"
case 1'1
assign $0\libresocsim_count[2:0] \libresocsim_count_spimaster1_next_value
case
end
- attribute \src "ls180.v:8622.2-8624.5"
+ attribute \src "ls180.v:8668.2-8670.5"
switch \builder_libresocsim_dat_w_next_value_ce0
- attribute \src "ls180.v:8622.6-8622.46"
+ attribute \src "ls180.v:8668.6-8668.46"
case 1'1
assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0
case
end
- attribute \src "ls180.v:8625.2-8627.5"
+ attribute \src "ls180.v:8671.2-8673.5"
switch \builder_libresocsim_adr_next_value_ce1
- attribute \src "ls180.v:8625.6-8625.44"
+ attribute \src "ls180.v:8671.6-8671.44"
case 1'1
assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1
case
end
- attribute \src "ls180.v:8628.2-8630.5"
+ attribute \src "ls180.v:8674.2-8676.5"
switch \builder_libresocsim_we_next_value_ce2
- attribute \src "ls180.v:8628.6-8628.43"
+ attribute \src "ls180.v:8674.6-8674.43"
case 1'1
assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2
case
end
- attribute \src "ls180.v:8631.2-8727.9"
+ attribute \src "ls180.v:8677.2-8773.9"
switch \builder_grant
attribute \src "ls180.v:0.0-0.0"
case 3'000
- attribute \src "ls180.v:8633.4-8649.7"
- switch $not$ls180.v:8633$2675_Y
- attribute \src "ls180.v:8633.8-8633.29"
+ attribute \src "ls180.v:8679.4-8695.7"
+ switch $not$ls180.v:8679$2685_Y
+ attribute \src "ls180.v:8679.8-8679.29"
case 1'1
- attribute \src "ls180.v:8634.5-8648.8"
+ attribute \src "ls180.v:8680.5-8694.8"
switch \builder_request [1]
- attribute \src "ls180.v:8634.9-8634.27"
+ attribute \src "ls180.v:8680.9-8680.27"
case 1'1
assign $0\builder_grant[2:0] 3'001
- attribute \src "ls180.v:8636.9-8636.13"
+ attribute \src "ls180.v:8682.9-8682.13"
case
- attribute \src "ls180.v:8637.6-8647.9"
+ attribute \src "ls180.v:8683.6-8693.9"
switch \builder_request [2]
- attribute \src "ls180.v:8637.10-8637.28"
+ attribute \src "ls180.v:8683.10-8683.28"
case 1'1
assign $0\builder_grant[2:0] 3'010
- attribute \src "ls180.v:8639.10-8639.14"
+ attribute \src "ls180.v:8685.10-8685.14"
case
- attribute \src "ls180.v:8640.7-8646.10"
+ attribute \src "ls180.v:8686.7-8692.10"
switch \builder_request [3]
- attribute \src "ls180.v:8640.11-8640.29"
+ attribute \src "ls180.v:8686.11-8686.29"
case 1'1
assign $0\builder_grant[2:0] 3'011
- attribute \src "ls180.v:8642.11-8642.15"
+ attribute \src "ls180.v:8688.11-8688.15"
case
- attribute \src "ls180.v:8643.8-8645.11"
+ attribute \src "ls180.v:8689.8-8691.11"
switch \builder_request [4]
- attribute \src "ls180.v:8643.12-8643.30"
+ attribute \src "ls180.v:8689.12-8689.30"
case 1'1
assign $0\builder_grant[2:0] 3'100
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'001
- attribute \src "ls180.v:8652.4-8668.7"
- switch $not$ls180.v:8652$2676_Y
- attribute \src "ls180.v:8652.8-8652.29"
+ attribute \src "ls180.v:8698.4-8714.7"
+ switch $not$ls180.v:8698$2686_Y
+ attribute \src "ls180.v:8698.8-8698.29"
case 1'1
- attribute \src "ls180.v:8653.5-8667.8"
+ attribute \src "ls180.v:8699.5-8713.8"
switch \builder_request [2]
- attribute \src "ls180.v:8653.9-8653.27"
+ attribute \src "ls180.v:8699.9-8699.27"
case 1'1
assign $0\builder_grant[2:0] 3'010
- attribute \src "ls180.v:8655.9-8655.13"
+ attribute \src "ls180.v:8701.9-8701.13"
case
- attribute \src "ls180.v:8656.6-8666.9"
+ attribute \src "ls180.v:8702.6-8712.9"
switch \builder_request [3]
- attribute \src "ls180.v:8656.10-8656.28"
+ attribute \src "ls180.v:8702.10-8702.28"
case 1'1
assign $0\builder_grant[2:0] 3'011
- attribute \src "ls180.v:8658.10-8658.14"
+ attribute \src "ls180.v:8704.10-8704.14"
case
- attribute \src "ls180.v:8659.7-8665.10"
+ attribute \src "ls180.v:8705.7-8711.10"
switch \builder_request [4]
- attribute \src "ls180.v:8659.11-8659.29"
+ attribute \src "ls180.v:8705.11-8705.29"
case 1'1
assign $0\builder_grant[2:0] 3'100
- attribute \src "ls180.v:8661.11-8661.15"
+ attribute \src "ls180.v:8707.11-8707.15"
case
- attribute \src "ls180.v:8662.8-8664.11"
+ attribute \src "ls180.v:8708.8-8710.11"
switch \builder_request [0]
- attribute \src "ls180.v:8662.12-8662.30"
+ attribute \src "ls180.v:8708.12-8708.30"
case 1'1
assign $0\builder_grant[2:0] 3'000
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'010
- attribute \src "ls180.v:8671.4-8687.7"
- switch $not$ls180.v:8671$2677_Y
- attribute \src "ls180.v:8671.8-8671.29"
+ attribute \src "ls180.v:8717.4-8733.7"
+ switch $not$ls180.v:8717$2687_Y
+ attribute \src "ls180.v:8717.8-8717.29"
case 1'1
- attribute \src "ls180.v:8672.5-8686.8"
+ attribute \src "ls180.v:8718.5-8732.8"
switch \builder_request [3]
- attribute \src "ls180.v:8672.9-8672.27"
+ attribute \src "ls180.v:8718.9-8718.27"
case 1'1
assign $0\builder_grant[2:0] 3'011
- attribute \src "ls180.v:8674.9-8674.13"
+ attribute \src "ls180.v:8720.9-8720.13"
case
- attribute \src "ls180.v:8675.6-8685.9"
+ attribute \src "ls180.v:8721.6-8731.9"
switch \builder_request [4]
- attribute \src "ls180.v:8675.10-8675.28"
+ attribute \src "ls180.v:8721.10-8721.28"
case 1'1
assign $0\builder_grant[2:0] 3'100
- attribute \src "ls180.v:8677.10-8677.14"
+ attribute \src "ls180.v:8723.10-8723.14"
case
- attribute \src "ls180.v:8678.7-8684.10"
+ attribute \src "ls180.v:8724.7-8730.10"
switch \builder_request [0]
- attribute \src "ls180.v:8678.11-8678.29"
+ attribute \src "ls180.v:8724.11-8724.29"
case 1'1
assign $0\builder_grant[2:0] 3'000
- attribute \src "ls180.v:8680.11-8680.15"
+ attribute \src "ls180.v:8726.11-8726.15"
case
- attribute \src "ls180.v:8681.8-8683.11"
+ attribute \src "ls180.v:8727.8-8729.11"
switch \builder_request [1]
- attribute \src "ls180.v:8681.12-8681.30"
+ attribute \src "ls180.v:8727.12-8727.30"
case 1'1
assign $0\builder_grant[2:0] 3'001
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:8690.4-8706.7"
- switch $not$ls180.v:8690$2678_Y
- attribute \src "ls180.v:8690.8-8690.29"
+ attribute \src "ls180.v:8736.4-8752.7"
+ switch $not$ls180.v:8736$2688_Y
+ attribute \src "ls180.v:8736.8-8736.29"
case 1'1
- attribute \src "ls180.v:8691.5-8705.8"
+ attribute \src "ls180.v:8737.5-8751.8"
switch \builder_request [4]
- attribute \src "ls180.v:8691.9-8691.27"
+ attribute \src "ls180.v:8737.9-8737.27"
case 1'1
assign $0\builder_grant[2:0] 3'100
- attribute \src "ls180.v:8693.9-8693.13"
+ attribute \src "ls180.v:8739.9-8739.13"
case
- attribute \src "ls180.v:8694.6-8704.9"
+ attribute \src "ls180.v:8740.6-8750.9"
switch \builder_request [0]
- attribute \src "ls180.v:8694.10-8694.28"
+ attribute \src "ls180.v:8740.10-8740.28"
case 1'1
assign $0\builder_grant[2:0] 3'000
- attribute \src "ls180.v:8696.10-8696.14"
+ attribute \src "ls180.v:8742.10-8742.14"
case
- attribute \src "ls180.v:8697.7-8703.10"
+ attribute \src "ls180.v:8743.7-8749.10"
switch \builder_request [1]
- attribute \src "ls180.v:8697.11-8697.29"
+ attribute \src "ls180.v:8743.11-8743.29"
case 1'1
assign $0\builder_grant[2:0] 3'001
- attribute \src "ls180.v:8699.11-8699.15"
+ attribute \src "ls180.v:8745.11-8745.15"
case
- attribute \src "ls180.v:8700.8-8702.11"
+ attribute \src "ls180.v:8746.8-8748.11"
switch \builder_request [2]
- attribute \src "ls180.v:8700.12-8700.30"
+ attribute \src "ls180.v:8746.12-8746.30"
case 1'1
assign $0\builder_grant[2:0] 3'010
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'100
- attribute \src "ls180.v:8709.4-8725.7"
- switch $not$ls180.v:8709$2679_Y
- attribute \src "ls180.v:8709.8-8709.29"
+ attribute \src "ls180.v:8755.4-8771.7"
+ switch $not$ls180.v:8755$2689_Y
+ attribute \src "ls180.v:8755.8-8755.29"
case 1'1
- attribute \src "ls180.v:8710.5-8724.8"
+ attribute \src "ls180.v:8756.5-8770.8"
switch \builder_request [0]
- attribute \src "ls180.v:8710.9-8710.27"
+ attribute \src "ls180.v:8756.9-8756.27"
case 1'1
assign $0\builder_grant[2:0] 3'000
- attribute \src "ls180.v:8712.9-8712.13"
+ attribute \src "ls180.v:8758.9-8758.13"
case
- attribute \src "ls180.v:8713.6-8723.9"
+ attribute \src "ls180.v:8759.6-8769.9"
switch \builder_request [1]
- attribute \src "ls180.v:8713.10-8713.28"
+ attribute \src "ls180.v:8759.10-8759.28"
case 1'1
assign $0\builder_grant[2:0] 3'001
- attribute \src "ls180.v:8715.10-8715.14"
+ attribute \src "ls180.v:8761.10-8761.14"
case
- attribute \src "ls180.v:8716.7-8722.10"
+ attribute \src "ls180.v:8762.7-8768.10"
switch \builder_request [2]
- attribute \src "ls180.v:8716.11-8716.29"
+ attribute \src "ls180.v:8762.11-8762.29"
case 1'1
assign $0\builder_grant[2:0] 3'010
- attribute \src "ls180.v:8718.11-8718.15"
+ attribute \src "ls180.v:8764.11-8764.15"
case
- attribute \src "ls180.v:8719.8-8721.11"
+ attribute \src "ls180.v:8765.8-8767.11"
switch \builder_request [3]
- attribute \src "ls180.v:8719.12-8719.30"
+ attribute \src "ls180.v:8765.12-8765.30"
case 1'1
assign $0\builder_grant[2:0] 3'011
case
end
case
end
- attribute \src "ls180.v:8729.2-8735.5"
+ attribute \src "ls180.v:8775.2-8781.5"
switch \builder_wait
- attribute \src "ls180.v:8729.6-8729.18"
+ attribute \src "ls180.v:8775.6-8775.18"
case 1'1
- attribute \src "ls180.v:8730.3-8732.6"
- switch $not$ls180.v:8730$2680_Y
- attribute \src "ls180.v:8730.7-8730.22"
+ attribute \src "ls180.v:8776.3-8778.6"
+ switch $not$ls180.v:8776$2690_Y
+ attribute \src "ls180.v:8776.7-8776.22"
case 1'1
- assign $0\builder_count[19:0] $sub$ls180.v:8731$2681_Y
+ assign $0\builder_count[19:0] $sub$ls180.v:8777$2691_Y
case
end
- attribute \src "ls180.v:8733.6-8733.10"
+ attribute \src "ls180.v:8779.6-8779.10"
case
assign $0\builder_count[19:0] 20'11110100001001000000
end
- attribute \src "ls180.v:8737.2-8767.5"
+ attribute \src "ls180.v:8783.2-8813.5"
switch \builder_csrbank0_sel
- attribute \src "ls180.v:8737.6-8737.26"
+ attribute \src "ls180.v:8783.6-8783.26"
case 1'1
- attribute \src "ls180.v:8738.3-8766.10"
+ attribute \src "ls180.v:8784.3-8812.10"
switch \builder_interface0_bank_bus_adr [3:0]
attribute \src "ls180.v:0.0-0.0"
case 4'0000
end
case
end
- attribute \src "ls180.v:8768.2-8770.5"
+ attribute \src "ls180.v:8814.2-8816.5"
switch \builder_csrbank0_reset0_re
- attribute \src "ls180.v:8768.6-8768.32"
+ attribute \src "ls180.v:8814.6-8814.32"
case 1'1
assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r
case
end
- attribute \src "ls180.v:8772.2-8774.5"
+ attribute \src "ls180.v:8818.2-8820.5"
switch \builder_csrbank0_scratch3_re
- attribute \src "ls180.v:8772.6-8772.34"
+ attribute \src "ls180.v:8818.6-8818.34"
case 1'1
assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r
case
end
- attribute \src "ls180.v:8775.2-8777.5"
+ attribute \src "ls180.v:8821.2-8823.5"
switch \builder_csrbank0_scratch2_re
- attribute \src "ls180.v:8775.6-8775.34"
+ attribute \src "ls180.v:8821.6-8821.34"
case 1'1
assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r
case
end
- attribute \src "ls180.v:8778.2-8780.5"
+ attribute \src "ls180.v:8824.2-8826.5"
switch \builder_csrbank0_scratch1_re
- attribute \src "ls180.v:8778.6-8778.34"
+ attribute \src "ls180.v:8824.6-8824.34"
case 1'1
assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r
case
end
- attribute \src "ls180.v:8781.2-8783.5"
+ attribute \src "ls180.v:8827.2-8829.5"
switch \builder_csrbank0_scratch0_re
- attribute \src "ls180.v:8781.6-8781.34"
+ attribute \src "ls180.v:8827.6-8827.34"
case 1'1
assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r
case
end
- attribute \src "ls180.v:8786.2-8807.5"
+ attribute \src "ls180.v:8832.2-8853.5"
switch \builder_csrbank1_sel
- attribute \src "ls180.v:8786.6-8786.26"
+ attribute \src "ls180.v:8832.6-8832.26"
case 1'1
- attribute \src "ls180.v:8787.3-8806.10"
+ attribute \src "ls180.v:8833.3-8852.10"
switch \builder_interface1_bank_bus_adr [2:0]
attribute \src "ls180.v:0.0-0.0"
case 3'000
end
case
end
- attribute \src "ls180.v:8808.2-8810.5"
+ attribute \src "ls180.v:8854.2-8856.5"
switch \builder_csrbank1_oe1_re
- attribute \src "ls180.v:8808.6-8808.29"
+ attribute \src "ls180.v:8854.6-8854.29"
case 1'1
assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r
case
end
- attribute \src "ls180.v:8811.2-8813.5"
+ attribute \src "ls180.v:8857.2-8859.5"
switch \builder_csrbank1_oe0_re
- attribute \src "ls180.v:8811.6-8811.29"
+ attribute \src "ls180.v:8857.6-8857.29"
case 1'1
assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r
case
end
- attribute \src "ls180.v:8815.2-8817.5"
+ attribute \src "ls180.v:8861.2-8863.5"
switch \builder_csrbank1_out1_re
- attribute \src "ls180.v:8815.6-8815.30"
+ attribute \src "ls180.v:8861.6-8861.30"
case 1'1
assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r
case
end
- attribute \src "ls180.v:8818.2-8820.5"
+ attribute \src "ls180.v:8864.2-8866.5"
switch \builder_csrbank1_out0_re
- attribute \src "ls180.v:8818.6-8818.30"
+ attribute \src "ls180.v:8864.6-8864.30"
case 1'1
assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r
case
end
- attribute \src "ls180.v:8823.2-8853.5"
+ attribute \src "ls180.v:8869.2-8878.5"
switch \builder_csrbank2_sel
- attribute \src "ls180.v:8823.6-8823.26"
+ attribute \src "ls180.v:8869.6-8869.26"
case 1'1
- attribute \src "ls180.v:8824.3-8852.10"
- switch \builder_interface2_bank_bus_adr [3:0]
+ attribute \src "ls180.v:8870.3-8877.10"
+ switch \builder_interface2_bank_bus_adr [0]
+ attribute \src "ls180.v:0.0-0.0"
+ case 1'0
+ assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 1'1
+ assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w }
+ case
+ end
+ case
+ end
+ attribute \src "ls180.v:8879.2-8881.5"
+ switch \builder_csrbank2_w0_re
+ attribute \src "ls180.v:8879.6-8879.28"
+ case 1'1
+ assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r
+ case
+ end
+ attribute \src "ls180.v:8884.2-8914.5"
+ switch \builder_csrbank3_sel
+ attribute \src "ls180.v:8884.6-8884.26"
+ case 1'1
+ attribute \src "ls180.v:8885.3-8913.10"
+ switch \builder_interface3_bank_bus_adr [3:0]
attribute \src "ls180.v:0.0-0.0"
case 4'0000
- assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_enable0_w }
+ assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w }
attribute \src "ls180.v:0.0-0.0"
case 4'0001
- assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width3_w
+ assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w
attribute \src "ls180.v:0.0-0.0"
case 4'0010
- assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width2_w
+ assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w
attribute \src "ls180.v:0.0-0.0"
case 4'0011
- assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width1_w
+ assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w
attribute \src "ls180.v:0.0-0.0"
case 4'0100
- assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width0_w
+ assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w
attribute \src "ls180.v:0.0-0.0"
case 4'0101
- assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period3_w
+ assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w
attribute \src "ls180.v:0.0-0.0"
case 4'0110
- assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period2_w
+ assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w
attribute \src "ls180.v:0.0-0.0"
case 4'0111
- assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period1_w
+ assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w
attribute \src "ls180.v:0.0-0.0"
case 4'1000
- assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period0_w
+ assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w
case
end
case
end
- attribute \src "ls180.v:8854.2-8856.5"
- switch \builder_csrbank2_enable0_re
- attribute \src "ls180.v:8854.6-8854.33"
+ attribute \src "ls180.v:8915.2-8917.5"
+ switch \builder_csrbank3_enable0_re
+ attribute \src "ls180.v:8915.6-8915.33"
case 1'1
- assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank2_enable0_r
+ assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r
case
end
- attribute \src "ls180.v:8858.2-8860.5"
- switch \builder_csrbank2_width3_re
- attribute \src "ls180.v:8858.6-8858.32"
+ attribute \src "ls180.v:8919.2-8921.5"
+ switch \builder_csrbank3_width3_re
+ attribute \src "ls180.v:8919.6-8919.32"
case 1'1
- assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank2_width3_r
+ assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r
case
end
- attribute \src "ls180.v:8861.2-8863.5"
- switch \builder_csrbank2_width2_re
- attribute \src "ls180.v:8861.6-8861.32"
+ attribute \src "ls180.v:8922.2-8924.5"
+ switch \builder_csrbank3_width2_re
+ attribute \src "ls180.v:8922.6-8922.32"
case 1'1
- assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank2_width2_r
+ assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r
case
end
- attribute \src "ls180.v:8864.2-8866.5"
- switch \builder_csrbank2_width1_re
- attribute \src "ls180.v:8864.6-8864.32"
+ attribute \src "ls180.v:8925.2-8927.5"
+ switch \builder_csrbank3_width1_re
+ attribute \src "ls180.v:8925.6-8925.32"
case 1'1
- assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank2_width1_r
+ assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r
case
end
- attribute \src "ls180.v:8867.2-8869.5"
- switch \builder_csrbank2_width0_re
- attribute \src "ls180.v:8867.6-8867.32"
+ attribute \src "ls180.v:8928.2-8930.5"
+ switch \builder_csrbank3_width0_re
+ attribute \src "ls180.v:8928.6-8928.32"
case 1'1
- assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank2_width0_r
+ assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r
case
end
- attribute \src "ls180.v:8871.2-8873.5"
- switch \builder_csrbank2_period3_re
- attribute \src "ls180.v:8871.6-8871.33"
+ attribute \src "ls180.v:8932.2-8934.5"
+ switch \builder_csrbank3_period3_re
+ attribute \src "ls180.v:8932.6-8932.33"
case 1'1
- assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank2_period3_r
+ assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r
case
end
- attribute \src "ls180.v:8874.2-8876.5"
- switch \builder_csrbank2_period2_re
- attribute \src "ls180.v:8874.6-8874.33"
+ attribute \src "ls180.v:8935.2-8937.5"
+ switch \builder_csrbank3_period2_re
+ attribute \src "ls180.v:8935.6-8935.33"
case 1'1
- assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank2_period2_r
+ assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r
case
end
- attribute \src "ls180.v:8877.2-8879.5"
- switch \builder_csrbank2_period1_re
- attribute \src "ls180.v:8877.6-8877.33"
+ attribute \src "ls180.v:8938.2-8940.5"
+ switch \builder_csrbank3_period1_re
+ attribute \src "ls180.v:8938.6-8938.33"
case 1'1
- assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank2_period1_r
+ assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r
case
end
- attribute \src "ls180.v:8880.2-8882.5"
- switch \builder_csrbank2_period0_re
- attribute \src "ls180.v:8880.6-8880.33"
+ attribute \src "ls180.v:8941.2-8943.5"
+ switch \builder_csrbank3_period0_re
+ attribute \src "ls180.v:8941.6-8941.33"
case 1'1
- assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank2_period0_r
+ assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r
case
end
- attribute \src "ls180.v:8885.2-8915.5"
- switch \builder_csrbank3_sel
- attribute \src "ls180.v:8885.6-8885.26"
+ attribute \src "ls180.v:8946.2-8976.5"
+ switch \builder_csrbank4_sel
+ attribute \src "ls180.v:8946.6-8946.26"
case 1'1
- attribute \src "ls180.v:8886.3-8914.10"
- switch \builder_interface3_bank_bus_adr [3:0]
+ attribute \src "ls180.v:8947.3-8975.10"
+ switch \builder_interface4_bank_bus_adr [3:0]
attribute \src "ls180.v:0.0-0.0"
case 4'0000
- assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w }
+ assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w }
attribute \src "ls180.v:0.0-0.0"
case 4'0001
- assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w
+ assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w
attribute \src "ls180.v:0.0-0.0"
case 4'0010
- assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w
+ assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w
attribute \src "ls180.v:0.0-0.0"
case 4'0011
- assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w
+ assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w
attribute \src "ls180.v:0.0-0.0"
case 4'0100
- assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w
+ assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w
attribute \src "ls180.v:0.0-0.0"
case 4'0101
- assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w
+ assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w
attribute \src "ls180.v:0.0-0.0"
case 4'0110
- assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w
+ assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w
attribute \src "ls180.v:0.0-0.0"
case 4'0111
- assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w
+ assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w
attribute \src "ls180.v:0.0-0.0"
case 4'1000
- assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w
+ assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w
case
end
case
end
- attribute \src "ls180.v:8916.2-8918.5"
- switch \builder_csrbank3_enable0_re
- attribute \src "ls180.v:8916.6-8916.33"
+ attribute \src "ls180.v:8977.2-8979.5"
+ switch \builder_csrbank4_enable0_re
+ attribute \src "ls180.v:8977.6-8977.33"
case 1'1
- assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank3_enable0_r
+ assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r
case
end
- attribute \src "ls180.v:8920.2-8922.5"
- switch \builder_csrbank3_width3_re
- attribute \src "ls180.v:8920.6-8920.32"
+ attribute \src "ls180.v:8981.2-8983.5"
+ switch \builder_csrbank4_width3_re
+ attribute \src "ls180.v:8981.6-8981.32"
case 1'1
- assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank3_width3_r
+ assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r
case
end
- attribute \src "ls180.v:8923.2-8925.5"
- switch \builder_csrbank3_width2_re
- attribute \src "ls180.v:8923.6-8923.32"
+ attribute \src "ls180.v:8984.2-8986.5"
+ switch \builder_csrbank4_width2_re
+ attribute \src "ls180.v:8984.6-8984.32"
case 1'1
- assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank3_width2_r
+ assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r
case
end
- attribute \src "ls180.v:8926.2-8928.5"
- switch \builder_csrbank3_width1_re
- attribute \src "ls180.v:8926.6-8926.32"
+ attribute \src "ls180.v:8987.2-8989.5"
+ switch \builder_csrbank4_width1_re
+ attribute \src "ls180.v:8987.6-8987.32"
case 1'1
- assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank3_width1_r
+ assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r
case
end
- attribute \src "ls180.v:8929.2-8931.5"
- switch \builder_csrbank3_width0_re
- attribute \src "ls180.v:8929.6-8929.32"
+ attribute \src "ls180.v:8990.2-8992.5"
+ switch \builder_csrbank4_width0_re
+ attribute \src "ls180.v:8990.6-8990.32"
case 1'1
- assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank3_width0_r
+ assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r
case
end
- attribute \src "ls180.v:8933.2-8935.5"
- switch \builder_csrbank3_period3_re
- attribute \src "ls180.v:8933.6-8933.33"
+ attribute \src "ls180.v:8994.2-8996.5"
+ switch \builder_csrbank4_period3_re
+ attribute \src "ls180.v:8994.6-8994.33"
case 1'1
- assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank3_period3_r
+ assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r
case
end
- attribute \src "ls180.v:8936.2-8938.5"
- switch \builder_csrbank3_period2_re
- attribute \src "ls180.v:8936.6-8936.33"
+ attribute \src "ls180.v:8997.2-8999.5"
+ switch \builder_csrbank4_period2_re
+ attribute \src "ls180.v:8997.6-8997.33"
case 1'1
- assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank3_period2_r
+ assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r
case
end
- attribute \src "ls180.v:8939.2-8941.5"
- switch \builder_csrbank3_period1_re
- attribute \src "ls180.v:8939.6-8939.33"
+ attribute \src "ls180.v:9000.2-9002.5"
+ switch \builder_csrbank4_period1_re
+ attribute \src "ls180.v:9000.6-9000.33"
case 1'1
- assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank3_period1_r
+ assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r
case
end
- attribute \src "ls180.v:8942.2-8944.5"
- switch \builder_csrbank3_period0_re
- attribute \src "ls180.v:8942.6-8942.33"
+ attribute \src "ls180.v:9003.2-9005.5"
+ switch \builder_csrbank4_period0_re
+ attribute \src "ls180.v:9003.6-9003.33"
case 1'1
- assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank3_period0_r
+ assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r
case
end
- attribute \src "ls180.v:8947.2-8995.5"
- switch \builder_csrbank4_sel
- attribute \src "ls180.v:8947.6-8947.26"
+ attribute \src "ls180.v:9008.2-9056.5"
+ switch \builder_csrbank5_sel
+ attribute \src "ls180.v:9008.6-9008.26"
case 1'1
- attribute \src "ls180.v:8948.3-8994.10"
- switch \builder_interface4_bank_bus_adr [3:0]
+ attribute \src "ls180.v:9009.3-9055.10"
+ switch \builder_interface5_bank_bus_adr [3:0]
attribute \src "ls180.v:0.0-0.0"
case 4'0000
- assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base7_w
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w
attribute \src "ls180.v:0.0-0.0"
case 4'0001
- assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base6_w
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w
attribute \src "ls180.v:0.0-0.0"
case 4'0010
- assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base5_w
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w
attribute \src "ls180.v:0.0-0.0"
case 4'0011
- assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base4_w
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w
attribute \src "ls180.v:0.0-0.0"
case 4'0100
- assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base3_w
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w
attribute \src "ls180.v:0.0-0.0"
case 4'0101
- assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base2_w
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w
attribute \src "ls180.v:0.0-0.0"
case 4'0110
- assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base1_w
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w
attribute \src "ls180.v:0.0-0.0"
case 4'0111
- assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base0_w
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w
attribute \src "ls180.v:0.0-0.0"
case 4'1000
- assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length3_w
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w
attribute \src "ls180.v:0.0-0.0"
case 4'1001
- assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length2_w
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w
attribute \src "ls180.v:0.0-0.0"
case 4'1010
- assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length1_w
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w
attribute \src "ls180.v:0.0-0.0"
case 4'1011
- assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length0_w
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w
attribute \src "ls180.v:0.0-0.0"
case 4'1100
- assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_dma_enable0_w }
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w }
attribute \src "ls180.v:0.0-0.0"
case 4'1101
- assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_dma_done_w }
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w }
attribute \src "ls180.v:0.0-0.0"
case 4'1110
- assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_dma_loop0_w }
+ assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w }
case
end
case
end
- attribute \src "ls180.v:8996.2-8998.5"
- switch \builder_csrbank4_dma_base7_re
- attribute \src "ls180.v:8996.6-8996.35"
+ attribute \src "ls180.v:9057.2-9059.5"
+ switch \builder_csrbank5_dma_base7_re
+ attribute \src "ls180.v:9057.6-9057.35"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank4_dma_base7_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r
case
end
- attribute \src "ls180.v:8999.2-9001.5"
- switch \builder_csrbank4_dma_base6_re
- attribute \src "ls180.v:8999.6-8999.35"
+ attribute \src "ls180.v:9060.2-9062.5"
+ switch \builder_csrbank5_dma_base6_re
+ attribute \src "ls180.v:9060.6-9060.35"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank4_dma_base6_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r
case
end
- attribute \src "ls180.v:9002.2-9004.5"
- switch \builder_csrbank4_dma_base5_re
- attribute \src "ls180.v:9002.6-9002.35"
+ attribute \src "ls180.v:9063.2-9065.5"
+ switch \builder_csrbank5_dma_base5_re
+ attribute \src "ls180.v:9063.6-9063.35"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank4_dma_base5_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r
case
end
- attribute \src "ls180.v:9005.2-9007.5"
- switch \builder_csrbank4_dma_base4_re
- attribute \src "ls180.v:9005.6-9005.35"
+ attribute \src "ls180.v:9066.2-9068.5"
+ switch \builder_csrbank5_dma_base4_re
+ attribute \src "ls180.v:9066.6-9066.35"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank4_dma_base4_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r
case
end
- attribute \src "ls180.v:9008.2-9010.5"
- switch \builder_csrbank4_dma_base3_re
- attribute \src "ls180.v:9008.6-9008.35"
+ attribute \src "ls180.v:9069.2-9071.5"
+ switch \builder_csrbank5_dma_base3_re
+ attribute \src "ls180.v:9069.6-9069.35"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank4_dma_base3_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r
case
end
- attribute \src "ls180.v:9011.2-9013.5"
- switch \builder_csrbank4_dma_base2_re
- attribute \src "ls180.v:9011.6-9011.35"
+ attribute \src "ls180.v:9072.2-9074.5"
+ switch \builder_csrbank5_dma_base2_re
+ attribute \src "ls180.v:9072.6-9072.35"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank4_dma_base2_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r
case
end
- attribute \src "ls180.v:9014.2-9016.5"
- switch \builder_csrbank4_dma_base1_re
- attribute \src "ls180.v:9014.6-9014.35"
+ attribute \src "ls180.v:9075.2-9077.5"
+ switch \builder_csrbank5_dma_base1_re
+ attribute \src "ls180.v:9075.6-9075.35"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank4_dma_base1_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r
case
end
- attribute \src "ls180.v:9017.2-9019.5"
- switch \builder_csrbank4_dma_base0_re
- attribute \src "ls180.v:9017.6-9017.35"
+ attribute \src "ls180.v:9078.2-9080.5"
+ switch \builder_csrbank5_dma_base0_re
+ attribute \src "ls180.v:9078.6-9078.35"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank4_dma_base0_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r
case
end
- attribute \src "ls180.v:9021.2-9023.5"
- switch \builder_csrbank4_dma_length3_re
- attribute \src "ls180.v:9021.6-9021.37"
+ attribute \src "ls180.v:9082.2-9084.5"
+ switch \builder_csrbank5_dma_length3_re
+ attribute \src "ls180.v:9082.6-9082.37"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank4_dma_length3_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r
case
end
- attribute \src "ls180.v:9024.2-9026.5"
- switch \builder_csrbank4_dma_length2_re
- attribute \src "ls180.v:9024.6-9024.37"
+ attribute \src "ls180.v:9085.2-9087.5"
+ switch \builder_csrbank5_dma_length2_re
+ attribute \src "ls180.v:9085.6-9085.37"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank4_dma_length2_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r
case
end
- attribute \src "ls180.v:9027.2-9029.5"
- switch \builder_csrbank4_dma_length1_re
- attribute \src "ls180.v:9027.6-9027.37"
+ attribute \src "ls180.v:9088.2-9090.5"
+ switch \builder_csrbank5_dma_length1_re
+ attribute \src "ls180.v:9088.6-9088.37"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank4_dma_length1_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r
case
end
- attribute \src "ls180.v:9030.2-9032.5"
- switch \builder_csrbank4_dma_length0_re
- attribute \src "ls180.v:9030.6-9030.37"
+ attribute \src "ls180.v:9091.2-9093.5"
+ switch \builder_csrbank5_dma_length0_re
+ attribute \src "ls180.v:9091.6-9091.37"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank4_dma_length0_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r
case
end
- attribute \src "ls180.v:9034.2-9036.5"
- switch \builder_csrbank4_dma_enable0_re
- attribute \src "ls180.v:9034.6-9034.37"
+ attribute \src "ls180.v:9095.2-9097.5"
+ switch \builder_csrbank5_dma_enable0_re
+ attribute \src "ls180.v:9095.6-9095.37"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank4_dma_enable0_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r
case
end
- attribute \src "ls180.v:9038.2-9040.5"
- switch \builder_csrbank4_dma_loop0_re
- attribute \src "ls180.v:9038.6-9038.35"
+ attribute \src "ls180.v:9099.2-9101.5"
+ switch \builder_csrbank5_dma_loop0_re
+ attribute \src "ls180.v:9099.6-9099.35"
case 1'1
- assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank4_dma_loop0_r
+ assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r
case
end
- attribute \src "ls180.v:9043.2-9145.5"
- switch \builder_csrbank5_sel
- attribute \src "ls180.v:9043.6-9043.26"
+ attribute \src "ls180.v:9104.2-9206.5"
+ switch \builder_csrbank6_sel
+ attribute \src "ls180.v:9104.6-9104.26"
case 1'1
- attribute \src "ls180.v:9044.3-9144.10"
- switch \builder_interface5_bank_bus_adr [5:0]
+ attribute \src "ls180.v:9105.3-9205.10"
+ switch \builder_interface6_bank_bus_adr [5:0]
attribute \src "ls180.v:0.0-0.0"
case 6'000000
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument3_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w
attribute \src "ls180.v:0.0-0.0"
case 6'000001
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument2_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w
attribute \src "ls180.v:0.0-0.0"
case 6'000010
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument1_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w
attribute \src "ls180.v:0.0-0.0"
case 6'000011
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument0_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w
attribute \src "ls180.v:0.0-0.0"
case 6'000100
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command3_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w
attribute \src "ls180.v:0.0-0.0"
case 6'000101
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command2_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w
attribute \src "ls180.v:0.0-0.0"
case 6'000110
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command1_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w
attribute \src "ls180.v:0.0-0.0"
case 6'000111
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command0_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w
attribute \src "ls180.v:0.0-0.0"
case 6'001000
- assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w }
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w }
attribute \src "ls180.v:0.0-0.0"
case 6'001001
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response15_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w
attribute \src "ls180.v:0.0-0.0"
case 6'001010
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response14_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w
attribute \src "ls180.v:0.0-0.0"
case 6'001011
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response13_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w
attribute \src "ls180.v:0.0-0.0"
case 6'001100
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response12_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w
attribute \src "ls180.v:0.0-0.0"
case 6'001101
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response11_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w
attribute \src "ls180.v:0.0-0.0"
case 6'001110
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response10_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w
attribute \src "ls180.v:0.0-0.0"
case 6'001111
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response9_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w
attribute \src "ls180.v:0.0-0.0"
case 6'010000
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response8_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w
attribute \src "ls180.v:0.0-0.0"
case 6'010001
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response7_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w
attribute \src "ls180.v:0.0-0.0"
case 6'010010
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response6_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w
attribute \src "ls180.v:0.0-0.0"
case 6'010011
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response5_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w
attribute \src "ls180.v:0.0-0.0"
case 6'010100
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response4_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w
attribute \src "ls180.v:0.0-0.0"
case 6'010101
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response3_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w
attribute \src "ls180.v:0.0-0.0"
case 6'010110
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response2_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w
attribute \src "ls180.v:0.0-0.0"
case 6'010111
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response1_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w
attribute \src "ls180.v:0.0-0.0"
case 6'011000
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response0_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w
attribute \src "ls180.v:0.0-0.0"
case 6'011001
- assign $0\builder_interface5_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank5_cmd_event_w }
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w }
attribute \src "ls180.v:0.0-0.0"
case 6'011010
- assign $0\builder_interface5_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank5_data_event_w }
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w }
attribute \src "ls180.v:0.0-0.0"
case 6'011011
- assign $0\builder_interface5_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank5_block_length1_w }
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w }
attribute \src "ls180.v:0.0-0.0"
case 6'011100
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_length0_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w
attribute \src "ls180.v:0.0-0.0"
case 6'011101
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count3_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w
attribute \src "ls180.v:0.0-0.0"
case 6'011110
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count2_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w
attribute \src "ls180.v:0.0-0.0"
case 6'011111
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count1_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w
attribute \src "ls180.v:0.0-0.0"
case 6'100000
- assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count0_w
- case
- end
- case
- end
- attribute \src "ls180.v:9146.2-9148.5"
- switch \builder_csrbank5_cmd_argument3_re
- attribute \src "ls180.v:9146.6-9146.39"
- case 1'1
- assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank5_cmd_argument3_r
- case
- end
- attribute \src "ls180.v:9149.2-9151.5"
- switch \builder_csrbank5_cmd_argument2_re
- attribute \src "ls180.v:9149.6-9149.39"
- case 1'1
- assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank5_cmd_argument2_r
- case
- end
- attribute \src "ls180.v:9152.2-9154.5"
- switch \builder_csrbank5_cmd_argument1_re
- attribute \src "ls180.v:9152.6-9152.39"
- case 1'1
- assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank5_cmd_argument1_r
- case
- end
- attribute \src "ls180.v:9155.2-9157.5"
- switch \builder_csrbank5_cmd_argument0_re
- attribute \src "ls180.v:9155.6-9155.39"
- case 1'1
- assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank5_cmd_argument0_r
- case
- end
- attribute \src "ls180.v:9159.2-9161.5"
- switch \builder_csrbank5_cmd_command3_re
- attribute \src "ls180.v:9159.6-9159.38"
- case 1'1
- assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank5_cmd_command3_r
- case
- end
- attribute \src "ls180.v:9162.2-9164.5"
- switch \builder_csrbank5_cmd_command2_re
- attribute \src "ls180.v:9162.6-9162.38"
- case 1'1
- assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank5_cmd_command2_r
- case
- end
- attribute \src "ls180.v:9165.2-9167.5"
- switch \builder_csrbank5_cmd_command1_re
- attribute \src "ls180.v:9165.6-9165.38"
- case 1'1
- assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank5_cmd_command1_r
- case
- end
- attribute \src "ls180.v:9168.2-9170.5"
- switch \builder_csrbank5_cmd_command0_re
- attribute \src "ls180.v:9168.6-9168.38"
- case 1'1
- assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank5_cmd_command0_r
- case
- end
- attribute \src "ls180.v:9172.2-9174.5"
- switch \builder_csrbank5_block_length1_re
- attribute \src "ls180.v:9172.6-9172.39"
- case 1'1
- assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank5_block_length1_r
- case
- end
- attribute \src "ls180.v:9175.2-9177.5"
- switch \builder_csrbank5_block_length0_re
- attribute \src "ls180.v:9175.6-9175.39"
- case 1'1
- assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank5_block_length0_r
- case
- end
- attribute \src "ls180.v:9179.2-9181.5"
- switch \builder_csrbank5_block_count3_re
- attribute \src "ls180.v:9179.6-9179.38"
- case 1'1
- assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank5_block_count3_r
- case
- end
- attribute \src "ls180.v:9182.2-9184.5"
- switch \builder_csrbank5_block_count2_re
- attribute \src "ls180.v:9182.6-9182.38"
- case 1'1
- assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank5_block_count2_r
- case
- end
- attribute \src "ls180.v:9185.2-9187.5"
- switch \builder_csrbank5_block_count1_re
- attribute \src "ls180.v:9185.6-9185.38"
- case 1'1
- assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank5_block_count1_r
- case
- end
- attribute \src "ls180.v:9188.2-9190.5"
- switch \builder_csrbank5_block_count0_re
- attribute \src "ls180.v:9188.6-9188.38"
- case 1'1
- assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank5_block_count0_r
- case
- end
- attribute \src "ls180.v:9193.2-9253.5"
- switch \builder_csrbank6_sel
- attribute \src "ls180.v:9193.6-9193.26"
- case 1'1
- attribute \src "ls180.v:9194.3-9252.10"
- switch \builder_interface6_bank_bus_adr [4:0]
- attribute \src "ls180.v:0.0-0.0"
- case 5'00000
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base7_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'00001
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base6_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'00010
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base5_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'00011
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base4_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'00100
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base3_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'00101
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base2_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'00110
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base1_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'00111
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base0_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'01000
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length3_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'01001
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length2_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'01010
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length1_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'01011
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length0_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'01100
- assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_dma_enable0_w }
- attribute \src "ls180.v:0.0-0.0"
- case 5'01101
- assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_dma_done_w }
- attribute \src "ls180.v:0.0-0.0"
- case 5'01110
- assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_dma_loop0_w }
- attribute \src "ls180.v:0.0-0.0"
- case 5'01111
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset3_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'10000
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset2_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'10001
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset1_w
- attribute \src "ls180.v:0.0-0.0"
- case 5'10010
- assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset0_w
+ assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w
case
end
case
end
- attribute \src "ls180.v:9254.2-9256.5"
- switch \builder_csrbank6_dma_base7_re
- attribute \src "ls180.v:9254.6-9254.35"
+ attribute \src "ls180.v:9207.2-9209.5"
+ switch \builder_csrbank6_cmd_argument3_re
+ attribute \src "ls180.v:9207.6-9207.39"
case 1'1
- assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank6_dma_base7_r
+ assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r
case
end
- attribute \src "ls180.v:9257.2-9259.5"
- switch \builder_csrbank6_dma_base6_re
- attribute \src "ls180.v:9257.6-9257.35"
+ attribute \src "ls180.v:9210.2-9212.5"
+ switch \builder_csrbank6_cmd_argument2_re
+ attribute \src "ls180.v:9210.6-9210.39"
case 1'1
- assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank6_dma_base6_r
+ assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r
case
end
- attribute \src "ls180.v:9260.2-9262.5"
- switch \builder_csrbank6_dma_base5_re
- attribute \src "ls180.v:9260.6-9260.35"
+ attribute \src "ls180.v:9213.2-9215.5"
+ switch \builder_csrbank6_cmd_argument1_re
+ attribute \src "ls180.v:9213.6-9213.39"
case 1'1
- assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank6_dma_base5_r
+ assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r
case
end
- attribute \src "ls180.v:9263.2-9265.5"
- switch \builder_csrbank6_dma_base4_re
- attribute \src "ls180.v:9263.6-9263.35"
+ attribute \src "ls180.v:9216.2-9218.5"
+ switch \builder_csrbank6_cmd_argument0_re
+ attribute \src "ls180.v:9216.6-9216.39"
case 1'1
- assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank6_dma_base4_r
+ assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r
case
end
- attribute \src "ls180.v:9266.2-9268.5"
- switch \builder_csrbank6_dma_base3_re
- attribute \src "ls180.v:9266.6-9266.35"
+ attribute \src "ls180.v:9220.2-9222.5"
+ switch \builder_csrbank6_cmd_command3_re
+ attribute \src "ls180.v:9220.6-9220.38"
case 1'1
- assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank6_dma_base3_r
+ assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r
case
end
- attribute \src "ls180.v:9269.2-9271.5"
- switch \builder_csrbank6_dma_base2_re
- attribute \src "ls180.v:9269.6-9269.35"
+ attribute \src "ls180.v:9223.2-9225.5"
+ switch \builder_csrbank6_cmd_command2_re
+ attribute \src "ls180.v:9223.6-9223.38"
case 1'1
- assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank6_dma_base2_r
+ assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r
case
end
- attribute \src "ls180.v:9272.2-9274.5"
- switch \builder_csrbank6_dma_base1_re
- attribute \src "ls180.v:9272.6-9272.35"
+ attribute \src "ls180.v:9226.2-9228.5"
+ switch \builder_csrbank6_cmd_command1_re
+ attribute \src "ls180.v:9226.6-9226.38"
case 1'1
- assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank6_dma_base1_r
+ assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r
case
end
- attribute \src "ls180.v:9275.2-9277.5"
- switch \builder_csrbank6_dma_base0_re
- attribute \src "ls180.v:9275.6-9275.35"
+ attribute \src "ls180.v:9229.2-9231.5"
+ switch \builder_csrbank6_cmd_command0_re
+ attribute \src "ls180.v:9229.6-9229.38"
case 1'1
- assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank6_dma_base0_r
+ assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r
case
end
- attribute \src "ls180.v:9279.2-9281.5"
- switch \builder_csrbank6_dma_length3_re
- attribute \src "ls180.v:9279.6-9279.37"
+ attribute \src "ls180.v:9233.2-9235.5"
+ switch \builder_csrbank6_block_length1_re
+ attribute \src "ls180.v:9233.6-9233.39"
case 1'1
- assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank6_dma_length3_r
+ assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r
case
end
- attribute \src "ls180.v:9282.2-9284.5"
- switch \builder_csrbank6_dma_length2_re
- attribute \src "ls180.v:9282.6-9282.37"
+ attribute \src "ls180.v:9236.2-9238.5"
+ switch \builder_csrbank6_block_length0_re
+ attribute \src "ls180.v:9236.6-9236.39"
case 1'1
- assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank6_dma_length2_r
+ assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r
case
end
- attribute \src "ls180.v:9285.2-9287.5"
- switch \builder_csrbank6_dma_length1_re
- attribute \src "ls180.v:9285.6-9285.37"
+ attribute \src "ls180.v:9240.2-9242.5"
+ switch \builder_csrbank6_block_count3_re
+ attribute \src "ls180.v:9240.6-9240.38"
case 1'1
- assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank6_dma_length1_r
+ assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r
case
end
- attribute \src "ls180.v:9288.2-9290.5"
- switch \builder_csrbank6_dma_length0_re
- attribute \src "ls180.v:9288.6-9288.37"
+ attribute \src "ls180.v:9243.2-9245.5"
+ switch \builder_csrbank6_block_count2_re
+ attribute \src "ls180.v:9243.6-9243.38"
case 1'1
- assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank6_dma_length0_r
+ assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r
case
end
- attribute \src "ls180.v:9292.2-9294.5"
- switch \builder_csrbank6_dma_enable0_re
- attribute \src "ls180.v:9292.6-9292.37"
+ attribute \src "ls180.v:9246.2-9248.5"
+ switch \builder_csrbank6_block_count1_re
+ attribute \src "ls180.v:9246.6-9246.38"
case 1'1
- assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank6_dma_enable0_r
+ assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r
case
end
- attribute \src "ls180.v:9296.2-9298.5"
- switch \builder_csrbank6_dma_loop0_re
- attribute \src "ls180.v:9296.6-9296.35"
+ attribute \src "ls180.v:9249.2-9251.5"
+ switch \builder_csrbank6_block_count0_re
+ attribute \src "ls180.v:9249.6-9249.38"
case 1'1
- assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank6_dma_loop0_r
+ assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r
case
end
- attribute \src "ls180.v:9301.2-9316.5"
+ attribute \src "ls180.v:9254.2-9314.5"
switch \builder_csrbank7_sel
- attribute \src "ls180.v:9301.6-9301.26"
- case 1'1
- attribute \src "ls180.v:9302.3-9315.10"
- switch \builder_interface7_bank_bus_adr [1:0]
- attribute \src "ls180.v:0.0-0.0"
- case 2'00
- assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_card_detect_w }
- attribute \src "ls180.v:0.0-0.0"
- case 2'01
- assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_clocker_divider1_w }
- attribute \src "ls180.v:0.0-0.0"
- case 2'10
- assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_clocker_divider0_w
- attribute \src "ls180.v:0.0-0.0"
- case 2'11
- assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w }
- case
- end
- case
- end
- attribute \src "ls180.v:9317.2-9319.5"
- switch \builder_csrbank7_clocker_divider1_re
- attribute \src "ls180.v:9317.6-9317.42"
- case 1'1
- assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank7_clocker_divider1_r
- case
- end
- attribute \src "ls180.v:9320.2-9322.5"
- switch \builder_csrbank7_clocker_divider0_re
- attribute \src "ls180.v:9320.6-9320.42"
- case 1'1
- assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank7_clocker_divider0_r
- case
- end
- attribute \src "ls180.v:9325.2-9358.5"
- switch \builder_csrbank8_sel
- attribute \src "ls180.v:9325.6-9325.26"
- case 1'1
- attribute \src "ls180.v:9326.3-9357.10"
- switch \builder_interface8_bank_bus_adr [3:0]
- attribute \src "ls180.v:0.0-0.0"
- case 4'0000
- assign $0\builder_interface8_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank8_dfii_control0_w }
- attribute \src "ls180.v:0.0-0.0"
- case 4'0001
- assign $0\builder_interface8_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank8_dfii_pi0_command0_w }
- attribute \src "ls180.v:0.0-0.0"
- case 4'0010
- assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w }
- attribute \src "ls180.v:0.0-0.0"
- case 4'0011
- assign $0\builder_interface8_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank8_dfii_pi0_address1_w }
- attribute \src "ls180.v:0.0-0.0"
- case 4'0100
- assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_address0_w
- attribute \src "ls180.v:0.0-0.0"
- case 4'0101
- assign $0\builder_interface8_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank8_dfii_pi0_baddress0_w }
- attribute \src "ls180.v:0.0-0.0"
- case 4'0110
- assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_wrdata1_w
- attribute \src "ls180.v:0.0-0.0"
- case 4'0111
- assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_wrdata0_w
- attribute \src "ls180.v:0.0-0.0"
- case 4'1000
- assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_rddata1_w
- attribute \src "ls180.v:0.0-0.0"
- case 4'1001
- assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_rddata0_w
- case
- end
- case
- end
- attribute \src "ls180.v:9359.2-9361.5"
- switch \builder_csrbank8_dfii_control0_re
- attribute \src "ls180.v:9359.6-9359.39"
- case 1'1
- assign $0\main_sdram_storage[3:0] \builder_csrbank8_dfii_control0_r
- case
- end
- attribute \src "ls180.v:9363.2-9365.5"
- switch \builder_csrbank8_dfii_pi0_command0_re
- attribute \src "ls180.v:9363.6-9363.43"
- case 1'1
- assign $0\main_sdram_command_storage[5:0] \builder_csrbank8_dfii_pi0_command0_r
- case
- end
- attribute \src "ls180.v:9367.2-9369.5"
- switch \builder_csrbank8_dfii_pi0_address1_re
- attribute \src "ls180.v:9367.6-9367.43"
- case 1'1
- assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank8_dfii_pi0_address1_r
- case
- end
- attribute \src "ls180.v:9370.2-9372.5"
- switch \builder_csrbank8_dfii_pi0_address0_re
- attribute \src "ls180.v:9370.6-9370.43"
- case 1'1
- assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank8_dfii_pi0_address0_r
- case
- end
- attribute \src "ls180.v:9374.2-9376.5"
- switch \builder_csrbank8_dfii_pi0_baddress0_re
- attribute \src "ls180.v:9374.6-9374.44"
- case 1'1
- assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank8_dfii_pi0_baddress0_r
- case
- end
- attribute \src "ls180.v:9378.2-9380.5"
- switch \builder_csrbank8_dfii_pi0_wrdata1_re
- attribute \src "ls180.v:9378.6-9378.42"
- case 1'1
- assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank8_dfii_pi0_wrdata1_r
- case
- end
- attribute \src "ls180.v:9381.2-9383.5"
- switch \builder_csrbank8_dfii_pi0_wrdata0_re
- attribute \src "ls180.v:9381.6-9381.42"
- case 1'1
- assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank8_dfii_pi0_wrdata0_r
- case
- end
- attribute \src "ls180.v:9386.2-9410.5"
- switch \builder_csrbank9_sel
- attribute \src "ls180.v:9386.6-9386.26"
- case 1'1
- attribute \src "ls180.v:9387.3-9409.10"
- switch \builder_interface9_bank_bus_adr [2:0]
- attribute \src "ls180.v:0.0-0.0"
- case 3'000
- assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_control1_w
- attribute \src "ls180.v:0.0-0.0"
- case 3'001
- assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_control0_w
- attribute \src "ls180.v:0.0-0.0"
- case 3'010
- assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_status_w }
- attribute \src "ls180.v:0.0-0.0"
- case 3'011
- assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_mosi0_w
- attribute \src "ls180.v:0.0-0.0"
- case 3'100
- assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_miso_w
- attribute \src "ls180.v:0.0-0.0"
- case 3'101
- assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_cs0_w }
- attribute \src "ls180.v:0.0-0.0"
- case 3'110
- assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_loopback0_w }
- case
- end
- case
- end
- attribute \src "ls180.v:9411.2-9413.5"
- switch \builder_csrbank9_control1_re
- attribute \src "ls180.v:9411.6-9411.34"
- case 1'1
- assign $0\main_spi_master_control_storage[15:0] [15:8] \builder_csrbank9_control1_r
- case
- end
- attribute \src "ls180.v:9414.2-9416.5"
- switch \builder_csrbank9_control0_re
- attribute \src "ls180.v:9414.6-9414.34"
- case 1'1
- assign $0\main_spi_master_control_storage[15:0] [7:0] \builder_csrbank9_control0_r
- case
- end
- attribute \src "ls180.v:9418.2-9420.5"
- switch \builder_csrbank9_mosi0_re
- attribute \src "ls180.v:9418.6-9418.31"
- case 1'1
- assign $0\main_spi_master_mosi_storage[7:0] \builder_csrbank9_mosi0_r
- case
- end
- attribute \src "ls180.v:9422.2-9424.5"
- switch \builder_csrbank9_cs0_re
- attribute \src "ls180.v:9422.6-9422.29"
- case 1'1
- assign $0\main_spi_master_cs_storage[0:0] \builder_csrbank9_cs0_r
- case
- end
- attribute \src "ls180.v:9426.2-9428.5"
- switch \builder_csrbank9_loopback0_re
- attribute \src "ls180.v:9426.6-9426.35"
- case 1'1
- assign $0\main_spi_master_loopback_storage[0:0] \builder_csrbank9_loopback0_r
- case
- end
- attribute \src "ls180.v:9431.2-9461.5"
- switch \builder_csrbank10_sel
- attribute \src "ls180.v:9431.6-9431.27"
- case 1'1
- attribute \src "ls180.v:9432.3-9460.10"
- switch \builder_interface10_bank_bus_adr [3:0]
- attribute \src "ls180.v:0.0-0.0"
- case 4'0000
- assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w
- attribute \src "ls180.v:0.0-0.0"
- case 4'0001
- assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w
- attribute \src "ls180.v:0.0-0.0"
- case 4'0010
- assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w }
- attribute \src "ls180.v:0.0-0.0"
- case 4'0011
- assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w
- attribute \src "ls180.v:0.0-0.0"
- case 4'0100
- assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w
- attribute \src "ls180.v:0.0-0.0"
- case 4'0101
- assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w }
- attribute \src "ls180.v:0.0-0.0"
- case 4'0110
- assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w }
- attribute \src "ls180.v:0.0-0.0"
- case 4'0111
- assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_clk_divider1_w
- attribute \src "ls180.v:0.0-0.0"
- case 4'1000
- assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_clk_divider0_w
- case
- end
- case
- end
- attribute \src "ls180.v:9462.2-9464.5"
- switch \builder_csrbank10_control1_re
- attribute \src "ls180.v:9462.6-9462.35"
- case 1'1
- assign $0\libresocsim_control_storage[15:0] [15:8] \builder_csrbank10_control1_r
- case
- end
- attribute \src "ls180.v:9465.2-9467.5"
- switch \builder_csrbank10_control0_re
- attribute \src "ls180.v:9465.6-9465.35"
- case 1'1
- assign $0\libresocsim_control_storage[15:0] [7:0] \builder_csrbank10_control0_r
- case
- end
- attribute \src "ls180.v:9469.2-9471.5"
- switch \builder_csrbank10_mosi0_re
- attribute \src "ls180.v:9469.6-9469.32"
- case 1'1
- assign $0\libresocsim_mosi_storage[7:0] \builder_csrbank10_mosi0_r
- case
- end
- attribute \src "ls180.v:9473.2-9475.5"
- switch \builder_csrbank10_cs0_re
- attribute \src "ls180.v:9473.6-9473.30"
- case 1'1
- assign $0\libresocsim_cs_storage[0:0] \builder_csrbank10_cs0_r
- case
- end
- attribute \src "ls180.v:9477.2-9479.5"
- switch \builder_csrbank10_loopback0_re
- attribute \src "ls180.v:9477.6-9477.36"
- case 1'1
- assign $0\libresocsim_loopback_storage[0:0] \builder_csrbank10_loopback0_r
- case
- end
- attribute \src "ls180.v:9481.2-9483.5"
- switch \builder_csrbank10_clk_divider1_re
- attribute \src "ls180.v:9481.6-9481.39"
- case 1'1
- assign $0\libresocsim_storage[15:0] [15:8] \builder_csrbank10_clk_divider1_r
- case
- end
- attribute \src "ls180.v:9484.2-9486.5"
- switch \builder_csrbank10_clk_divider0_re
- attribute \src "ls180.v:9484.6-9484.39"
- case 1'1
- assign $0\libresocsim_storage[15:0] [7:0] \builder_csrbank10_clk_divider0_r
- case
- end
- attribute \src "ls180.v:9489.2-9543.5"
- switch \builder_csrbank11_sel
- attribute \src "ls180.v:9489.6-9489.27"
+ attribute \src "ls180.v:9254.6-9254.26"
case 1'1
- attribute \src "ls180.v:9490.3-9542.10"
- switch \builder_interface11_bank_bus_adr [4:0]
+ attribute \src "ls180.v:9255.3-9313.10"
+ switch \builder_interface7_bank_bus_adr [4:0]
attribute \src "ls180.v:0.0-0.0"
case 5'00000
- assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load3_w
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w
attribute \src "ls180.v:0.0-0.0"
case 5'00001
- assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load2_w
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w
attribute \src "ls180.v:0.0-0.0"
case 5'00010
- assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load1_w
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w
attribute \src "ls180.v:0.0-0.0"
case 5'00011
- assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load0_w
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w
attribute \src "ls180.v:0.0-0.0"
case 5'00100
- assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload3_w
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w
attribute \src "ls180.v:0.0-0.0"
case 5'00101
- assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload2_w
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w
attribute \src "ls180.v:0.0-0.0"
case 5'00110
- assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload1_w
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w
attribute \src "ls180.v:0.0-0.0"
case 5'00111
- assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload0_w
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w
attribute \src "ls180.v:0.0-0.0"
case 5'01000
- assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_en0_w }
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w
attribute \src "ls180.v:0.0-0.0"
case 5'01001
- assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_update_value0_w }
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w
attribute \src "ls180.v:0.0-0.0"
case 5'01010
- assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value3_w
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w
attribute \src "ls180.v:0.0-0.0"
case 5'01011
- assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value2_w
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w
attribute \src "ls180.v:0.0-0.0"
case 5'01100
- assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value1_w
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w }
attribute \src "ls180.v:0.0-0.0"
case 5'01101
- assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value0_w
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w }
attribute \src "ls180.v:0.0-0.0"
case 5'01110
- assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w }
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w }
attribute \src "ls180.v:0.0-0.0"
case 5'01111
- assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w }
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w
attribute \src "ls180.v:0.0-0.0"
case 5'10000
- assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_ev_enable0_w }
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'10001
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'10010
+ assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w
case
end
case
end
- attribute \src "ls180.v:9544.2-9546.5"
- switch \builder_csrbank11_load3_re
- attribute \src "ls180.v:9544.6-9544.32"
+ attribute \src "ls180.v:9315.2-9317.5"
+ switch \builder_csrbank7_dma_base7_re
+ attribute \src "ls180.v:9315.6-9315.35"
case 1'1
- assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank11_load3_r
+ assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r
case
end
- attribute \src "ls180.v:9547.2-9549.5"
- switch \builder_csrbank11_load2_re
- attribute \src "ls180.v:9547.6-9547.32"
+ attribute \src "ls180.v:9318.2-9320.5"
+ switch \builder_csrbank7_dma_base6_re
+ attribute \src "ls180.v:9318.6-9318.35"
case 1'1
- assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank11_load2_r
+ assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r
case
end
- attribute \src "ls180.v:9550.2-9552.5"
- switch \builder_csrbank11_load1_re
- attribute \src "ls180.v:9550.6-9550.32"
+ attribute \src "ls180.v:9321.2-9323.5"
+ switch \builder_csrbank7_dma_base5_re
+ attribute \src "ls180.v:9321.6-9321.35"
case 1'1
- assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank11_load1_r
+ assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r
case
end
- attribute \src "ls180.v:9553.2-9555.5"
- switch \builder_csrbank11_load0_re
- attribute \src "ls180.v:9553.6-9553.32"
+ attribute \src "ls180.v:9324.2-9326.5"
+ switch \builder_csrbank7_dma_base4_re
+ attribute \src "ls180.v:9324.6-9324.35"
case 1'1
- assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank11_load0_r
+ assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r
case
end
- attribute \src "ls180.v:9557.2-9559.5"
- switch \builder_csrbank11_reload3_re
- attribute \src "ls180.v:9557.6-9557.34"
+ attribute \src "ls180.v:9327.2-9329.5"
+ switch \builder_csrbank7_dma_base3_re
+ attribute \src "ls180.v:9327.6-9327.35"
case 1'1
- assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank11_reload3_r
+ assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r
case
end
- attribute \src "ls180.v:9560.2-9562.5"
- switch \builder_csrbank11_reload2_re
- attribute \src "ls180.v:9560.6-9560.34"
+ attribute \src "ls180.v:9330.2-9332.5"
+ switch \builder_csrbank7_dma_base2_re
+ attribute \src "ls180.v:9330.6-9330.35"
case 1'1
- assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank11_reload2_r
+ assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r
case
end
- attribute \src "ls180.v:9563.2-9565.5"
- switch \builder_csrbank11_reload1_re
- attribute \src "ls180.v:9563.6-9563.34"
+ attribute \src "ls180.v:9333.2-9335.5"
+ switch \builder_csrbank7_dma_base1_re
+ attribute \src "ls180.v:9333.6-9333.35"
case 1'1
- assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank11_reload1_r
+ assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r
case
end
- attribute \src "ls180.v:9566.2-9568.5"
- switch \builder_csrbank11_reload0_re
- attribute \src "ls180.v:9566.6-9566.34"
+ attribute \src "ls180.v:9336.2-9338.5"
+ switch \builder_csrbank7_dma_base0_re
+ attribute \src "ls180.v:9336.6-9336.35"
case 1'1
- assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank11_reload0_r
+ assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r
case
end
- attribute \src "ls180.v:9570.2-9572.5"
- switch \builder_csrbank11_en0_re
- attribute \src "ls180.v:9570.6-9570.30"
+ attribute \src "ls180.v:9340.2-9342.5"
+ switch \builder_csrbank7_dma_length3_re
+ attribute \src "ls180.v:9340.6-9340.37"
case 1'1
- assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank11_en0_r
+ assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r
case
end
- attribute \src "ls180.v:9574.2-9576.5"
- switch \builder_csrbank11_update_value0_re
- attribute \src "ls180.v:9574.6-9574.40"
+ attribute \src "ls180.v:9343.2-9345.5"
+ switch \builder_csrbank7_dma_length2_re
+ attribute \src "ls180.v:9343.6-9343.37"
case 1'1
- assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank11_update_value0_r
+ assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r
case
end
- attribute \src "ls180.v:9578.2-9580.5"
- switch \builder_csrbank11_ev_enable0_re
- attribute \src "ls180.v:9578.6-9578.37"
+ attribute \src "ls180.v:9346.2-9348.5"
+ switch \builder_csrbank7_dma_length1_re
+ attribute \src "ls180.v:9346.6-9346.37"
case 1'1
- assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank11_ev_enable0_r
+ assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r
case
end
- attribute \src "ls180.v:9583.2-9610.5"
- switch \builder_csrbank12_sel
- attribute \src "ls180.v:9583.6-9583.27"
+ attribute \src "ls180.v:9349.2-9351.5"
+ switch \builder_csrbank7_dma_length0_re
+ attribute \src "ls180.v:9349.6-9349.37"
+ case 1'1
+ assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r
+ case
+ end
+ attribute \src "ls180.v:9353.2-9355.5"
+ switch \builder_csrbank7_dma_enable0_re
+ attribute \src "ls180.v:9353.6-9353.37"
+ case 1'1
+ assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r
+ case
+ end
+ attribute \src "ls180.v:9357.2-9359.5"
+ switch \builder_csrbank7_dma_loop0_re
+ attribute \src "ls180.v:9357.6-9357.35"
+ case 1'1
+ assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r
+ case
+ end
+ attribute \src "ls180.v:9362.2-9377.5"
+ switch \builder_csrbank8_sel
+ attribute \src "ls180.v:9362.6-9362.26"
+ case 1'1
+ attribute \src "ls180.v:9363.3-9376.10"
+ switch \builder_interface8_bank_bus_adr [1:0]
+ attribute \src "ls180.v:0.0-0.0"
+ case 2'00
+ assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 2'01
+ assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 2'10
+ assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 2'11
+ assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w }
+ case
+ end
+ case
+ end
+ attribute \src "ls180.v:9378.2-9380.5"
+ switch \builder_csrbank8_clocker_divider1_re
+ attribute \src "ls180.v:9378.6-9378.42"
+ case 1'1
+ assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r
+ case
+ end
+ attribute \src "ls180.v:9381.2-9383.5"
+ switch \builder_csrbank8_clocker_divider0_re
+ attribute \src "ls180.v:9381.6-9381.42"
+ case 1'1
+ assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r
+ case
+ end
+ attribute \src "ls180.v:9386.2-9419.5"
+ switch \builder_csrbank9_sel
+ attribute \src "ls180.v:9386.6-9386.26"
+ case 1'1
+ attribute \src "ls180.v:9387.3-9418.10"
+ switch \builder_interface9_bank_bus_adr [3:0]
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0000
+ assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0001
+ assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0010
+ assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0011
+ assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0100
+ assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0101
+ assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0110
+ assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0111
+ assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'1000
+ assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'1001
+ assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w
+ case
+ end
+ case
+ end
+ attribute \src "ls180.v:9420.2-9422.5"
+ switch \builder_csrbank9_dfii_control0_re
+ attribute \src "ls180.v:9420.6-9420.39"
+ case 1'1
+ assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r
+ case
+ end
+ attribute \src "ls180.v:9424.2-9426.5"
+ switch \builder_csrbank9_dfii_pi0_command0_re
+ attribute \src "ls180.v:9424.6-9424.43"
+ case 1'1
+ assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r
+ case
+ end
+ attribute \src "ls180.v:9428.2-9430.5"
+ switch \builder_csrbank9_dfii_pi0_address1_re
+ attribute \src "ls180.v:9428.6-9428.43"
+ case 1'1
+ assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r
+ case
+ end
+ attribute \src "ls180.v:9431.2-9433.5"
+ switch \builder_csrbank9_dfii_pi0_address0_re
+ attribute \src "ls180.v:9431.6-9431.43"
+ case 1'1
+ assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r
+ case
+ end
+ attribute \src "ls180.v:9435.2-9437.5"
+ switch \builder_csrbank9_dfii_pi0_baddress0_re
+ attribute \src "ls180.v:9435.6-9435.44"
+ case 1'1
+ assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r
+ case
+ end
+ attribute \src "ls180.v:9439.2-9441.5"
+ switch \builder_csrbank9_dfii_pi0_wrdata1_re
+ attribute \src "ls180.v:9439.6-9439.42"
+ case 1'1
+ assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r
+ case
+ end
+ attribute \src "ls180.v:9442.2-9444.5"
+ switch \builder_csrbank9_dfii_pi0_wrdata0_re
+ attribute \src "ls180.v:9442.6-9442.42"
+ case 1'1
+ assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r
+ case
+ end
+ attribute \src "ls180.v:9447.2-9471.5"
+ switch \builder_csrbank10_sel
+ attribute \src "ls180.v:9447.6-9447.27"
case 1'1
- attribute \src "ls180.v:9584.3-9609.10"
- switch \builder_interface12_bank_bus_adr [2:0]
+ attribute \src "ls180.v:9448.3-9470.10"
+ switch \builder_interface10_bank_bus_adr [2:0]
attribute \src "ls180.v:0.0-0.0"
case 3'000
- assign $0\builder_interface12_bank_bus_dat_r[7:0] \main_uart_rxtx_w
+ assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w
attribute \src "ls180.v:0.0-0.0"
case 3'001
- assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_txfull_w }
+ assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w
attribute \src "ls180.v:0.0-0.0"
case 3'010
- assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_rxempty_w }
+ assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w }
attribute \src "ls180.v:0.0-0.0"
case 3'011
- assign $0\builder_interface12_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w }
+ assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w
attribute \src "ls180.v:0.0-0.0"
case 3'100
- assign $0\builder_interface12_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w }
+ assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w
attribute \src "ls180.v:0.0-0.0"
case 3'101
- assign $0\builder_interface12_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank12_ev_enable0_w }
+ assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w }
attribute \src "ls180.v:0.0-0.0"
case 3'110
- assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_txempty_w }
+ assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w }
+ case
+ end
+ case
+ end
+ attribute \src "ls180.v:9472.2-9474.5"
+ switch \builder_csrbank10_control1_re
+ attribute \src "ls180.v:9472.6-9472.35"
+ case 1'1
+ assign $0\main_spi_master_control_storage[15:0] [15:8] \builder_csrbank10_control1_r
+ case
+ end
+ attribute \src "ls180.v:9475.2-9477.5"
+ switch \builder_csrbank10_control0_re
+ attribute \src "ls180.v:9475.6-9475.35"
+ case 1'1
+ assign $0\main_spi_master_control_storage[15:0] [7:0] \builder_csrbank10_control0_r
+ case
+ end
+ attribute \src "ls180.v:9479.2-9481.5"
+ switch \builder_csrbank10_mosi0_re
+ attribute \src "ls180.v:9479.6-9479.32"
+ case 1'1
+ assign $0\main_spi_master_mosi_storage[7:0] \builder_csrbank10_mosi0_r
+ case
+ end
+ attribute \src "ls180.v:9483.2-9485.5"
+ switch \builder_csrbank10_cs0_re
+ attribute \src "ls180.v:9483.6-9483.30"
+ case 1'1
+ assign $0\main_spi_master_cs_storage[0:0] \builder_csrbank10_cs0_r
+ case
+ end
+ attribute \src "ls180.v:9487.2-9489.5"
+ switch \builder_csrbank10_loopback0_re
+ attribute \src "ls180.v:9487.6-9487.36"
+ case 1'1
+ assign $0\main_spi_master_loopback_storage[0:0] \builder_csrbank10_loopback0_r
+ case
+ end
+ attribute \src "ls180.v:9492.2-9522.5"
+ switch \builder_csrbank11_sel
+ attribute \src "ls180.v:9492.6-9492.27"
+ case 1'1
+ attribute \src "ls180.v:9493.3-9521.10"
+ switch \builder_interface11_bank_bus_adr [3:0]
attribute \src "ls180.v:0.0-0.0"
- case 3'111
- assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_rxfull_w }
+ case 4'0000
+ assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0001
+ assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0010
+ assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0011
+ assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0100
+ assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0101
+ assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0110
+ assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'0111
+ assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 4'1000
+ assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w
case
end
case
end
+ attribute \src "ls180.v:9523.2-9525.5"
+ switch \builder_csrbank11_control1_re
+ attribute \src "ls180.v:9523.6-9523.35"
+ case 1'1
+ assign $0\libresocsim_control_storage[15:0] [15:8] \builder_csrbank11_control1_r
+ case
+ end
+ attribute \src "ls180.v:9526.2-9528.5"
+ switch \builder_csrbank11_control0_re
+ attribute \src "ls180.v:9526.6-9526.35"
+ case 1'1
+ assign $0\libresocsim_control_storage[15:0] [7:0] \builder_csrbank11_control0_r
+ case
+ end
+ attribute \src "ls180.v:9530.2-9532.5"
+ switch \builder_csrbank11_mosi0_re
+ attribute \src "ls180.v:9530.6-9530.32"
+ case 1'1
+ assign $0\libresocsim_mosi_storage[7:0] \builder_csrbank11_mosi0_r
+ case
+ end
+ attribute \src "ls180.v:9534.2-9536.5"
+ switch \builder_csrbank11_cs0_re
+ attribute \src "ls180.v:9534.6-9534.30"
+ case 1'1
+ assign $0\libresocsim_cs_storage[0:0] \builder_csrbank11_cs0_r
+ case
+ end
+ attribute \src "ls180.v:9538.2-9540.5"
+ switch \builder_csrbank11_loopback0_re
+ attribute \src "ls180.v:9538.6-9538.36"
+ case 1'1
+ assign $0\libresocsim_loopback_storage[0:0] \builder_csrbank11_loopback0_r
+ case
+ end
+ attribute \src "ls180.v:9542.2-9544.5"
+ switch \builder_csrbank11_clk_divider1_re
+ attribute \src "ls180.v:9542.6-9542.39"
+ case 1'1
+ assign $0\libresocsim_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r
+ case
+ end
+ attribute \src "ls180.v:9545.2-9547.5"
+ switch \builder_csrbank11_clk_divider0_re
+ attribute \src "ls180.v:9545.6-9545.39"
+ case 1'1
+ assign $0\libresocsim_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r
+ case
+ end
+ attribute \src "ls180.v:9550.2-9604.5"
+ switch \builder_csrbank12_sel
+ attribute \src "ls180.v:9550.6-9550.27"
+ case 1'1
+ attribute \src "ls180.v:9551.3-9603.10"
+ switch \builder_interface12_bank_bus_adr [4:0]
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'00000
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'00001
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'00010
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'00011
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'00100
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'00101
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'00110
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'00111
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'01000
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'01001
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'01010
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'01011
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'01100
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'01101
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'01110
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'01111
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 5'10000
+ assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w }
+ case
+ end
+ case
+ end
+ attribute \src "ls180.v:9605.2-9607.5"
+ switch \builder_csrbank12_load3_re
+ attribute \src "ls180.v:9605.6-9605.32"
+ case 1'1
+ assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r
+ case
+ end
+ attribute \src "ls180.v:9608.2-9610.5"
+ switch \builder_csrbank12_load2_re
+ attribute \src "ls180.v:9608.6-9608.32"
+ case 1'1
+ assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r
+ case
+ end
attribute \src "ls180.v:9611.2-9613.5"
+ switch \builder_csrbank12_load1_re
+ attribute \src "ls180.v:9611.6-9611.32"
+ case 1'1
+ assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r
+ case
+ end
+ attribute \src "ls180.v:9614.2-9616.5"
+ switch \builder_csrbank12_load0_re
+ attribute \src "ls180.v:9614.6-9614.32"
+ case 1'1
+ assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r
+ case
+ end
+ attribute \src "ls180.v:9618.2-9620.5"
+ switch \builder_csrbank12_reload3_re
+ attribute \src "ls180.v:9618.6-9618.34"
+ case 1'1
+ assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r
+ case
+ end
+ attribute \src "ls180.v:9621.2-9623.5"
+ switch \builder_csrbank12_reload2_re
+ attribute \src "ls180.v:9621.6-9621.34"
+ case 1'1
+ assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r
+ case
+ end
+ attribute \src "ls180.v:9624.2-9626.5"
+ switch \builder_csrbank12_reload1_re
+ attribute \src "ls180.v:9624.6-9624.34"
+ case 1'1
+ assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r
+ case
+ end
+ attribute \src "ls180.v:9627.2-9629.5"
+ switch \builder_csrbank12_reload0_re
+ attribute \src "ls180.v:9627.6-9627.34"
+ case 1'1
+ assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r
+ case
+ end
+ attribute \src "ls180.v:9631.2-9633.5"
+ switch \builder_csrbank12_en0_re
+ attribute \src "ls180.v:9631.6-9631.30"
+ case 1'1
+ assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r
+ case
+ end
+ attribute \src "ls180.v:9635.2-9637.5"
+ switch \builder_csrbank12_update_value0_re
+ attribute \src "ls180.v:9635.6-9635.40"
+ case 1'1
+ assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r
+ case
+ end
+ attribute \src "ls180.v:9639.2-9641.5"
switch \builder_csrbank12_ev_enable0_re
- attribute \src "ls180.v:9611.6-9611.37"
+ attribute \src "ls180.v:9639.6-9639.37"
case 1'1
- assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank12_ev_enable0_r
+ assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r
case
end
- attribute \src "ls180.v:9616.2-9631.5"
+ attribute \src "ls180.v:9644.2-9671.5"
switch \builder_csrbank13_sel
- attribute \src "ls180.v:9616.6-9616.27"
+ attribute \src "ls180.v:9644.6-9644.27"
+ case 1'1
+ attribute \src "ls180.v:9645.3-9670.10"
+ switch \builder_interface13_bank_bus_adr [2:0]
+ attribute \src "ls180.v:0.0-0.0"
+ case 3'000
+ assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w
+ attribute \src "ls180.v:0.0-0.0"
+ case 3'001
+ assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 3'010
+ assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 3'011
+ assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 3'100
+ assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 3'101
+ assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 3'110
+ assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w }
+ attribute \src "ls180.v:0.0-0.0"
+ case 3'111
+ assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w }
+ case
+ end
+ case
+ end
+ attribute \src "ls180.v:9672.2-9674.5"
+ switch \builder_csrbank13_ev_enable0_re
+ attribute \src "ls180.v:9672.6-9672.37"
case 1'1
- attribute \src "ls180.v:9617.3-9630.10"
- switch \builder_interface13_bank_bus_adr [1:0]
+ assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r
+ case
+ end
+ attribute \src "ls180.v:9677.2-9692.5"
+ switch \builder_csrbank14_sel
+ attribute \src "ls180.v:9677.6-9677.27"
+ case 1'1
+ attribute \src "ls180.v:9678.3-9691.10"
+ switch \builder_interface14_bank_bus_adr [1:0]
attribute \src "ls180.v:0.0-0.0"
case 2'00
- assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word3_w
+ assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word2_w
+ assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word1_w
+ assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w
attribute \src "ls180.v:0.0-0.0"
case 2'11
- assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word0_w
+ assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w
case
end
case
end
- attribute \src "ls180.v:9632.2-9634.5"
- switch \builder_csrbank13_tuning_word3_re
- attribute \src "ls180.v:9632.6-9632.39"
+ attribute \src "ls180.v:9693.2-9695.5"
+ switch \builder_csrbank14_tuning_word3_re
+ attribute \src "ls180.v:9693.6-9693.39"
case 1'1
- assign $0\main_storage[31:0] [31:24] \builder_csrbank13_tuning_word3_r
+ assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r
case
end
- attribute \src "ls180.v:9635.2-9637.5"
- switch \builder_csrbank13_tuning_word2_re
- attribute \src "ls180.v:9635.6-9635.39"
+ attribute \src "ls180.v:9696.2-9698.5"
+ switch \builder_csrbank14_tuning_word2_re
+ attribute \src "ls180.v:9696.6-9696.39"
case 1'1
- assign $0\main_storage[31:0] [23:16] \builder_csrbank13_tuning_word2_r
+ assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r
case
end
- attribute \src "ls180.v:9638.2-9640.5"
- switch \builder_csrbank13_tuning_word1_re
- attribute \src "ls180.v:9638.6-9638.39"
+ attribute \src "ls180.v:9699.2-9701.5"
+ switch \builder_csrbank14_tuning_word1_re
+ attribute \src "ls180.v:9699.6-9699.39"
case 1'1
- assign $0\main_storage[31:0] [15:8] \builder_csrbank13_tuning_word1_r
+ assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r
case
end
- attribute \src "ls180.v:9641.2-9643.5"
- switch \builder_csrbank13_tuning_word0_re
- attribute \src "ls180.v:9641.6-9641.39"
+ attribute \src "ls180.v:9702.2-9704.5"
+ switch \builder_csrbank14_tuning_word0_re
+ attribute \src "ls180.v:9702.6-9702.39"
case 1'1
- assign $0\main_storage[31:0] [7:0] \builder_csrbank13_tuning_word0_r
+ assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r
case
end
- attribute \src "ls180.v:9645.2-9938.5"
+ attribute \src "ls180.v:9706.2-10001.5"
switch \sys_rst_1
- attribute \src "ls180.v:9645.6-9645.15"
+ attribute \src "ls180.v:9706.6-9706.15"
case 1'1
assign $0\main_libresocsim_reset_storage[0:0] 1'0
assign $0\main_libresocsim_reset_re[0:0] 1'0
assign $0\main_converter_counter[0:0] 1'0
assign $0\main_cmd_consumed[0:0] 1'0
assign $0\main_wdata_consumed[0:0] 1'0
- assign $0\main_storage[31:0] 9895604
- assign $0\main_re[0:0] 1'0
- assign $0\main_sink_ready[0:0] 1'0
- assign $0\main_uart_clk_txen[0:0] 1'0
- assign $0\main_tx_busy[0:0] 1'0
- assign $0\main_source_valid[0:0] 1'0
- assign $0\main_uart_clk_rxen[0:0] 1'0
- assign $0\main_rx_r[0:0] 1'0
- assign $0\main_rx_busy[0:0] 1'0
+ assign $0\main_uart_phy_storage[31:0] 9895604
+ assign $0\main_uart_phy_re[0:0] 1'0
+ assign $0\main_uart_phy_sink_ready[0:0] 1'0
+ assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0
+ assign $0\main_uart_phy_tx_busy[0:0] 1'0
+ assign $0\main_uart_phy_source_valid[0:0] 1'0
+ assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0
+ assign $0\main_uart_phy_rx_r[0:0] 1'0
+ assign $0\main_uart_phy_rx_busy[0:0] 1'0
assign $0\main_uart_tx_pending[0:0] 1'0
assign $0\main_uart_tx_old_trigger[0:0] 1'0
assign $0\main_uart_rx_pending[0:0] 1'0
assign $0\main_spi_master_mosi_data[7:0] 8'00000000
assign $0\main_spi_master_mosi_sel[2:0] 3'000
assign $0\main_spi_master_miso_data[7:0] 8'00000000
- assign $0\main_dummy[41:0] 42'000000000000000000000000000000000000000000
+ assign $0\main_dummy[35:0] 36'000000000000000000000000000000000000
assign $0\pwm0[0:0] 1'0
assign $0\main_pwm0_enable_storage[0:0] 1'0
assign $0\main_pwm0_enable_re[0:0] 1'0
assign $0\main_pwm1_enable_re[0:0] 1'0
assign $0\main_pwm1_width_re[0:0] 1'0
assign $0\main_pwm1_period_re[0:0] 1'0
+ assign $0\main_i2c_storage[2:0] 3'000
+ assign $0\main_i2c_re[0:0] 1'0
assign $0\main_sdphy_clocker_storage[8:0] 9'100000000
assign $0\main_sdphy_clocker_re[0:0] 1'0
assign $0\main_sdphy_clocker_clk0[0:0] 1'0
update \main_converter_dat_r $0\main_converter_dat_r[31:0]
update \main_cmd_consumed $0\main_cmd_consumed[0:0]
update \main_wdata_consumed $0\main_wdata_consumed[0:0]
- update \main_storage $0\main_storage[31:0]
- update \main_re $0\main_re[0:0]
- update \main_sink_ready $0\main_sink_ready[0:0]
- update \main_uart_clk_txen $0\main_uart_clk_txen[0:0]
- update \main_phase_accumulator_tx $0\main_phase_accumulator_tx[31:0]
- update \main_tx_reg $0\main_tx_reg[7:0]
- update \main_tx_bitcount $0\main_tx_bitcount[3:0]
- update \main_tx_busy $0\main_tx_busy[0:0]
- update \main_source_valid $0\main_source_valid[0:0]
- update \main_source_payload_data $0\main_source_payload_data[7:0]
- update \main_uart_clk_rxen $0\main_uart_clk_rxen[0:0]
- update \main_phase_accumulator_rx $0\main_phase_accumulator_rx[31:0]
- update \main_rx_r $0\main_rx_r[0:0]
- update \main_rx_reg $0\main_rx_reg[7:0]
- update \main_rx_bitcount $0\main_rx_bitcount[3:0]
- update \main_rx_busy $0\main_rx_busy[0:0]
+ update \main_uart_phy_storage $0\main_uart_phy_storage[31:0]
+ update \main_uart_phy_re $0\main_uart_phy_re[0:0]
+ update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0]
+ update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0]
+ update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0]
+ update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0]
+ update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0]
+ update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0]
+ update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0]
+ update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0]
+ update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0]
+ update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0]
+ update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0]
+ update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0]
+ update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0]
+ update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0]
update \main_uart_tx_pending $0\main_uart_tx_pending[0:0]
update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0]
update \main_uart_rx_pending $0\main_uart_rx_pending[0:0]
update \main_spi_master_mosi_data $0\main_spi_master_mosi_data[7:0]
update \main_spi_master_mosi_sel $0\main_spi_master_mosi_sel[2:0]
update \main_spi_master_miso_data $0\main_spi_master_miso_data[7:0]
- update \main_dummy $0\main_dummy[41:0]
+ update \main_dummy $0\main_dummy[35:0]
update \main_pwm0_counter $0\main_pwm0_counter[31:0]
update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0]
update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0]
update \main_pwm1_width_re $0\main_pwm1_width_re[0:0]
update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0]
update \main_pwm1_period_re $0\main_pwm1_period_re[0:0]
+ update \main_i2c_storage $0\main_i2c_storage[2:0]
+ update \main_i2c_re $0\main_i2c_re[0:0]
update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0]
update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0]
update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0]
update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0]
update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0]
update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0]
+ update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0]
update \builder_state $0\builder_state[1:0]
update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0]
update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0]
update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0]
update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0]
end
- attribute \src "ls180.v:736.5-736.48"
- process $proc$ls180.v:736$3048
+ attribute \src "ls180.v:742.5-742.49"
+ process $proc$ls180.v:742$3056
+ assign { } { }
+ assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0]
+ end
+ attribute \src "ls180.v:743.5-743.49"
+ process $proc$ls180.v:743$3057
+ assign { } { }
+ assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0
+ sync always
+ sync init
+ update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0]
+ end
+ attribute \src "ls180.v:744.5-744.48"
+ process $proc$ls180.v:744$3058
assign { } { }
assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0
sync always
sync init
update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:740.11-740.46"
- process $proc$ls180.v:740$3049
+ attribute \src "ls180.v:748.11-748.46"
+ process $proc$ls180.v:748$3059
assign { } { }
assign $1\main_sdram_choose_req_valids[3:0] 4'0000
sync always
sync init
update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0]
end
- attribute \src "ls180.v:742.11-742.45"
- process $proc$ls180.v:742$3050
+ attribute \src "ls180.v:750.11-750.45"
+ process $proc$ls180.v:750$3060
assign { } { }
assign $1\main_sdram_choose_req_grant[1:0] 2'00
sync always
sync init
update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0]
end
- attribute \src "ls180.v:744.12-744.36"
- process $proc$ls180.v:744$3051
+ attribute \src "ls180.v:752.12-752.36"
+ process $proc$ls180.v:752$3061
assign { } { }
assign $0\main_sdram_nop_a[12:0] 13'0000000000000
sync always
update \main_sdram_nop_a $0\main_sdram_nop_a[12:0]
sync init
end
- attribute \src "ls180.v:745.11-745.35"
- process $proc$ls180.v:745$3052
+ attribute \src "ls180.v:753.11-753.35"
+ process $proc$ls180.v:753$3062
assign { } { }
assign $0\main_sdram_nop_ba[1:0] 2'00
sync always
update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0]
sync init
end
- attribute \src "ls180.v:746.11-746.40"
- process $proc$ls180.v:746$3053
+ attribute \src "ls180.v:754.11-754.40"
+ process $proc$ls180.v:754$3063
assign { } { }
assign $1\main_sdram_steerer_sel[1:0] 2'00
sync always
sync init
update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0]
end
- attribute \src "ls180.v:747.5-747.31"
- process $proc$ls180.v:747$3054
+ attribute \src "ls180.v:755.5-755.31"
+ process $proc$ls180.v:755$3064
assign { } { }
assign $0\main_sdram_steerer0[0:0] 1'1
sync always
update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0]
sync init
end
- attribute \src "ls180.v:748.5-748.31"
- process $proc$ls180.v:748$3055
+ attribute \src "ls180.v:756.5-756.31"
+ process $proc$ls180.v:756$3065
assign { } { }
assign $0\main_sdram_steerer1[0:0] 1'1
sync always
update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0]
sync init
end
- attribute \src "ls180.v:750.32-750.63"
- process $proc$ls180.v:750$3056
+ attribute \src "ls180.v:758.32-758.63"
+ process $proc$ls180.v:758$3066
assign { } { }
assign $0\main_sdram_trrdcon_ready[0:0] 1'1
sync always
update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0]
sync init
end
- attribute \src "ls180.v:752.32-752.63"
- process $proc$ls180.v:752$3057
+ attribute \src "ls180.v:76.5-76.46"
+ process $proc$ls180.v:76$2782
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0
+ sync always
+ update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:760.32-760.63"
+ process $proc$ls180.v:760$3067
assign { } { }
assign $0\main_sdram_tfawcon_ready[0:0] 1'1
sync always
update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0]
sync init
end
- attribute \src "ls180.v:754.32-754.63"
- process $proc$ls180.v:754$3058
+ attribute \src "ls180.v:762.32-762.63"
+ process $proc$ls180.v:762$3068
assign { } { }
assign $1\main_sdram_tccdcon_ready[0:0] 1'0
sync always
sync init
update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0]
end
- attribute \src "ls180.v:755.5-755.36"
- process $proc$ls180.v:755$3059
+ attribute \src "ls180.v:763.5-763.36"
+ process $proc$ls180.v:763$3069
assign { } { }
assign $1\main_sdram_tccdcon_count[0:0] 1'0
sync always
sync init
update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0]
end
- attribute \src "ls180.v:757.32-757.63"
- process $proc$ls180.v:757$3060
+ attribute \src "ls180.v:765.32-765.63"
+ process $proc$ls180.v:765$3070
assign { } { }
assign $1\main_sdram_twtrcon_ready[0:0] 1'0
sync always
sync init
update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0]
end
- attribute \src "ls180.v:758.11-758.42"
- process $proc$ls180.v:758$3061
+ attribute \src "ls180.v:766.11-766.42"
+ process $proc$ls180.v:766$3071
assign { } { }
assign $1\main_sdram_twtrcon_count[2:0] 3'000
sync always
sync init
update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0]
end
- attribute \src "ls180.v:761.5-761.26"
- process $proc$ls180.v:761$3062
+ attribute \src "ls180.v:769.5-769.26"
+ process $proc$ls180.v:769$3072
assign { } { }
assign $1\main_sdram_en0[0:0] 1'0
sync always
sync init
update \main_sdram_en0 $1\main_sdram_en0[0:0]
end
- attribute \src "ls180.v:763.11-763.34"
- process $proc$ls180.v:763$3063
+ attribute \src "ls180.v:771.11-771.34"
+ process $proc$ls180.v:771$3073
assign { } { }
assign $1\main_sdram_time0[4:0] 5'00000
sync always
sync init
update \main_sdram_time0 $1\main_sdram_time0[4:0]
end
- attribute \src "ls180.v:764.5-764.26"
- process $proc$ls180.v:764$3064
+ attribute \src "ls180.v:772.5-772.26"
+ process $proc$ls180.v:772$3074
assign { } { }
assign $1\main_sdram_en1[0:0] 1'0
sync always
sync init
update \main_sdram_en1 $1\main_sdram_en1[0:0]
end
- attribute \src "ls180.v:766.11-766.34"
- process $proc$ls180.v:766$3065
+ attribute \src "ls180.v:774.11-774.34"
+ process $proc$ls180.v:774$3075
assign { } { }
assign $1\main_sdram_time1[3:0] 4'0000
sync always
sync init
update \main_sdram_time1 $1\main_sdram_time1[3:0]
end
- attribute \src "ls180.v:77.5-77.46"
- process $proc$ls180.v:77$2773
- assign { } { }
- assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0
- sync always
- sync init
- update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0]
- end
- attribute \src "ls180.v:787.5-787.29"
- process $proc$ls180.v:787$3066
+ attribute \src "ls180.v:795.5-795.29"
+ process $proc$ls180.v:795$3076
assign { } { }
assign $1\main_wb_sdram_ack[0:0] 1'0
sync always
sync init
update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0]
end
- attribute \src "ls180.v:791.5-791.29"
- process $proc$ls180.v:791$3067
+ attribute \src "ls180.v:799.5-799.29"
+ process $proc$ls180.v:799$3077
assign { } { }
assign $0\main_wb_sdram_err[0:0] 1'0
sync always
update \main_wb_sdram_err $0\main_wb_sdram_err[0:0]
sync init
end
- attribute \src "ls180.v:792.12-792.40"
- process $proc$ls180.v:792$3068
+ attribute \src "ls180.v:800.12-800.40"
+ process $proc$ls180.v:800$3078
assign { } { }
assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000
sync always
sync init
update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0]
end
- attribute \src "ls180.v:793.12-793.42"
- process $proc$ls180.v:793$3069
+ attribute \src "ls180.v:801.12-801.42"
+ process $proc$ls180.v:801$3079
assign { } { }
assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000
sync always
sync init
update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0]
end
- attribute \src "ls180.v:795.11-795.38"
- process $proc$ls180.v:795$3070
+ attribute \src "ls180.v:803.11-803.38"
+ process $proc$ls180.v:803$3080
assign { } { }
assign $1\main_litedram_wb_sel[1:0] 2'00
sync always
sync init
update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0]
end
- attribute \src "ls180.v:796.5-796.32"
- process $proc$ls180.v:796$3071
+ attribute \src "ls180.v:804.5-804.32"
+ process $proc$ls180.v:804$3081
assign { } { }
assign $1\main_litedram_wb_cyc[0:0] 1'0
sync always
sync init
update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0]
end
- attribute \src "ls180.v:797.5-797.32"
- process $proc$ls180.v:797$3072
+ attribute \src "ls180.v:805.5-805.32"
+ process $proc$ls180.v:805$3082
assign { } { }
assign $1\main_litedram_wb_stb[0:0] 1'0
sync always
sync init
update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0]
end
- attribute \src "ls180.v:799.5-799.31"
- process $proc$ls180.v:799$3073
+ attribute \src "ls180.v:807.5-807.31"
+ process $proc$ls180.v:807$3083
assign { } { }
assign $1\main_litedram_wb_we[0:0] 1'0
sync always
sync init
update \main_litedram_wb_we $1\main_litedram_wb_we[0:0]
end
- attribute \src "ls180.v:800.5-800.31"
- process $proc$ls180.v:800$3074
+ attribute \src "ls180.v:808.5-808.31"
+ process $proc$ls180.v:808$3084
assign { } { }
assign $1\main_converter_skip[0:0] 1'0
sync always
sync init
update \main_converter_skip $1\main_converter_skip[0:0]
end
- attribute \src "ls180.v:801.5-801.34"
- process $proc$ls180.v:801$3075
+ attribute \src "ls180.v:809.5-809.34"
+ process $proc$ls180.v:809$3085
assign { } { }
assign $1\main_converter_counter[0:0] 1'0
sync always
sync init
update \main_converter_counter $1\main_converter_counter[0:0]
end
- attribute \src "ls180.v:803.12-803.40"
- process $proc$ls180.v:803$3076
+ attribute \src "ls180.v:811.12-811.40"
+ process $proc$ls180.v:811$3086
assign { } { }
assign $1\main_converter_dat_r[31:0] 0
sync always
sync init
update \main_converter_dat_r $1\main_converter_dat_r[31:0]
end
- attribute \src "ls180.v:804.5-804.29"
- process $proc$ls180.v:804$3077
+ attribute \src "ls180.v:812.5-812.29"
+ process $proc$ls180.v:812$3087
assign { } { }
assign $1\main_cmd_consumed[0:0] 1'0
sync always
sync init
update \main_cmd_consumed $1\main_cmd_consumed[0:0]
end
- attribute \src "ls180.v:805.5-805.31"
- process $proc$ls180.v:805$3078
+ attribute \src "ls180.v:813.5-813.31"
+ process $proc$ls180.v:813$3088
assign { } { }
assign $1\main_wdata_consumed[0:0] 1'0
sync always
sync init
update \main_wdata_consumed $1\main_wdata_consumed[0:0]
end
- attribute \src "ls180.v:809.12-809.38"
- process $proc$ls180.v:809$3079
+ attribute \src "ls180.v:817.12-817.47"
+ process $proc$ls180.v:817$3089
assign { } { }
- assign $1\main_storage[31:0] 9895604
+ assign $1\main_uart_phy_storage[31:0] 9895604
sync always
sync init
- update \main_storage $1\main_storage[31:0]
+ update \main_uart_phy_storage $1\main_uart_phy_storage[31:0]
end
- attribute \src "ls180.v:81.5-81.46"
- process $proc$ls180.v:81$2774
+ attribute \src "ls180.v:818.5-818.28"
+ process $proc$ls180.v:818$3090
assign { } { }
- assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0
+ assign $1\main_uart_phy_re[0:0] 1'0
sync always
- update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0]
sync init
+ update \main_uart_phy_re $1\main_uart_phy_re[0:0]
end
- attribute \src "ls180.v:810.5-810.19"
- process $proc$ls180.v:810$3080
+ attribute \src "ls180.v:820.5-820.36"
+ process $proc$ls180.v:820$3091
assign { } { }
- assign $1\main_re[0:0] 1'0
+ assign $1\main_uart_phy_sink_ready[0:0] 1'0
sync always
sync init
- update \main_re $1\main_re[0:0]
+ update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0]
end
- attribute \src "ls180.v:812.5-812.27"
- process $proc$ls180.v:812$3081
+ attribute \src "ls180.v:824.5-824.39"
+ process $proc$ls180.v:824$3092
assign { } { }
- assign $1\main_sink_ready[0:0] 1'0
+ assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0
sync always
sync init
- update \main_sink_ready $1\main_sink_ready[0:0]
+ update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0]
end
- attribute \src "ls180.v:816.5-816.30"
- process $proc$ls180.v:816$3082
+ attribute \src "ls180.v:825.12-825.54"
+ process $proc$ls180.v:825$3093
assign { } { }
- assign $1\main_uart_clk_txen[0:0] 1'0
+ assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0
sync always
sync init
- update \main_uart_clk_txen $1\main_uart_clk_txen[0:0]
+ update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0]
end
- attribute \src "ls180.v:817.12-817.45"
- process $proc$ls180.v:817$3083
+ attribute \src "ls180.v:826.11-826.38"
+ process $proc$ls180.v:826$3094
assign { } { }
- assign $1\main_phase_accumulator_tx[31:0] 0
+ assign $1\main_uart_phy_tx_reg[7:0] 8'00000000
sync always
sync init
- update \main_phase_accumulator_tx $1\main_phase_accumulator_tx[31:0]
+ update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0]
end
- attribute \src "ls180.v:818.11-818.29"
- process $proc$ls180.v:818$3084
+ attribute \src "ls180.v:827.11-827.43"
+ process $proc$ls180.v:827$3095
assign { } { }
- assign $1\main_tx_reg[7:0] 8'00000000
+ assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000
sync always
sync init
- update \main_tx_reg $1\main_tx_reg[7:0]
+ update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0]
end
- attribute \src "ls180.v:819.11-819.34"
- process $proc$ls180.v:819$3085
+ attribute \src "ls180.v:828.5-828.33"
+ process $proc$ls180.v:828$3096
assign { } { }
- assign $1\main_tx_bitcount[3:0] 4'0000
+ assign $1\main_uart_phy_tx_busy[0:0] 1'0
sync always
sync init
- update \main_tx_bitcount $1\main_tx_bitcount[3:0]
+ update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0]
end
- attribute \src "ls180.v:820.5-820.24"
- process $proc$ls180.v:820$3086
+ attribute \src "ls180.v:829.5-829.38"
+ process $proc$ls180.v:829$3097
assign { } { }
- assign $1\main_tx_busy[0:0] 1'0
+ assign $1\main_uart_phy_source_valid[0:0] 1'0
sync always
sync init
- update \main_tx_busy $1\main_tx_busy[0:0]
+ update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0]
end
- attribute \src "ls180.v:821.5-821.29"
- process $proc$ls180.v:821$3087
+ attribute \src "ls180.v:83.5-83.46"
+ process $proc$ls180.v:83$2783
assign { } { }
- assign $1\main_source_valid[0:0] 1'0
+ assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0
sync always
sync init
- update \main_source_valid $1\main_source_valid[0:0]
+ update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0]
end
- attribute \src "ls180.v:823.5-823.29"
- process $proc$ls180.v:823$3088
+ attribute \src "ls180.v:831.5-831.38"
+ process $proc$ls180.v:831$3098
assign { } { }
- assign $0\main_source_first[0:0] 1'0
+ assign $0\main_uart_phy_source_first[0:0] 1'0
sync always
- update \main_source_first $0\main_source_first[0:0]
+ update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0]
sync init
end
- attribute \src "ls180.v:824.5-824.28"
- process $proc$ls180.v:824$3089
+ attribute \src "ls180.v:832.5-832.37"
+ process $proc$ls180.v:832$3099
assign { } { }
- assign $0\main_source_last[0:0] 1'0
+ assign $0\main_uart_phy_source_last[0:0] 1'0
sync always
- update \main_source_last $0\main_source_last[0:0]
+ update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0]
sync init
end
- attribute \src "ls180.v:825.11-825.42"
- process $proc$ls180.v:825$3090
+ attribute \src "ls180.v:833.11-833.51"
+ process $proc$ls180.v:833$3100
assign { } { }
- assign $1\main_source_payload_data[7:0] 8'00000000
+ assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000
sync always
sync init
- update \main_source_payload_data $1\main_source_payload_data[7:0]
+ update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0]
end
- attribute \src "ls180.v:826.5-826.30"
- process $proc$ls180.v:826$3091
+ attribute \src "ls180.v:834.5-834.39"
+ process $proc$ls180.v:834$3101
assign { } { }
- assign $1\main_uart_clk_rxen[0:0] 1'0
+ assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0
sync always
sync init
- update \main_uart_clk_rxen $1\main_uart_clk_rxen[0:0]
+ update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0]
end
- attribute \src "ls180.v:827.12-827.45"
- process $proc$ls180.v:827$3092
+ attribute \src "ls180.v:835.12-835.54"
+ process $proc$ls180.v:835$3102
assign { } { }
- assign $1\main_phase_accumulator_rx[31:0] 0
+ assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0
sync always
sync init
- update \main_phase_accumulator_rx $1\main_phase_accumulator_rx[31:0]
+ update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0]
end
- attribute \src "ls180.v:829.5-829.21"
- process $proc$ls180.v:829$3093
+ attribute \src "ls180.v:837.5-837.30"
+ process $proc$ls180.v:837$3103
assign { } { }
- assign $1\main_rx_r[0:0] 1'0
+ assign $1\main_uart_phy_rx_r[0:0] 1'0
sync always
sync init
- update \main_rx_r $1\main_rx_r[0:0]
+ update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0]
end
- attribute \src "ls180.v:830.11-830.29"
- process $proc$ls180.v:830$3094
+ attribute \src "ls180.v:838.11-838.38"
+ process $proc$ls180.v:838$3104
assign { } { }
- assign $1\main_rx_reg[7:0] 8'00000000
+ assign $1\main_uart_phy_rx_reg[7:0] 8'00000000
sync always
sync init
- update \main_rx_reg $1\main_rx_reg[7:0]
+ update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0]
end
- attribute \src "ls180.v:831.11-831.34"
- process $proc$ls180.v:831$3095
+ attribute \src "ls180.v:839.11-839.43"
+ process $proc$ls180.v:839$3105
assign { } { }
- assign $1\main_rx_bitcount[3:0] 4'0000
+ assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000
sync always
sync init
- update \main_rx_bitcount $1\main_rx_bitcount[3:0]
+ update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0]
end
- attribute \src "ls180.v:832.5-832.24"
- process $proc$ls180.v:832$3096
+ attribute \src "ls180.v:840.5-840.33"
+ process $proc$ls180.v:840$3106
assign { } { }
- assign $1\main_rx_busy[0:0] 1'0
+ assign $1\main_uart_phy_rx_busy[0:0] 1'0
sync always
sync init
- update \main_rx_busy $1\main_rx_busy[0:0]
+ update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0]
end
- attribute \src "ls180.v:843.5-843.32"
- process $proc$ls180.v:843$3097
+ attribute \src "ls180.v:851.5-851.32"
+ process $proc$ls180.v:851$3107
assign { } { }
assign $1\main_uart_tx_pending[0:0] 1'0
sync always
sync init
update \main_uart_tx_pending $1\main_uart_tx_pending[0:0]
end
- attribute \src "ls180.v:845.5-845.30"
- process $proc$ls180.v:845$3098
+ attribute \src "ls180.v:853.5-853.30"
+ process $proc$ls180.v:853$3108
assign { } { }
assign $1\main_uart_tx_clear[0:0] 1'0
sync always
sync init
update \main_uart_tx_clear $1\main_uart_tx_clear[0:0]
end
- attribute \src "ls180.v:846.5-846.36"
- process $proc$ls180.v:846$3099
+ attribute \src "ls180.v:854.5-854.36"
+ process $proc$ls180.v:854$3109
assign { } { }
assign $1\main_uart_tx_old_trigger[0:0] 1'0
sync always
sync init
update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0]
end
- attribute \src "ls180.v:848.5-848.32"
- process $proc$ls180.v:848$3100
+ attribute \src "ls180.v:856.5-856.32"
+ process $proc$ls180.v:856$3110
assign { } { }
assign $1\main_uart_rx_pending[0:0] 1'0
sync always
sync init
update \main_uart_rx_pending $1\main_uart_rx_pending[0:0]
end
- attribute \src "ls180.v:850.5-850.30"
- process $proc$ls180.v:850$3101
+ attribute \src "ls180.v:858.5-858.30"
+ process $proc$ls180.v:858$3111
assign { } { }
assign $1\main_uart_rx_clear[0:0] 1'0
sync always
sync init
update \main_uart_rx_clear $1\main_uart_rx_clear[0:0]
end
- attribute \src "ls180.v:851.5-851.36"
- process $proc$ls180.v:851$3102
+ attribute \src "ls180.v:859.5-859.36"
+ process $proc$ls180.v:859$3112
assign { } { }
assign $1\main_uart_rx_old_trigger[0:0] 1'0
sync always
sync init
update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0]
end
- attribute \src "ls180.v:855.11-855.49"
- process $proc$ls180.v:855$3103
+ attribute \src "ls180.v:863.11-863.49"
+ process $proc$ls180.v:863$3113
assign { } { }
assign $1\main_uart_eventmanager_status_w[1:0] 2'00
sync always
sync init
update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0]
end
- attribute \src "ls180.v:859.11-859.50"
- process $proc$ls180.v:859$3104
+ attribute \src "ls180.v:867.11-867.50"
+ process $proc$ls180.v:867$3114
assign { } { }
assign $1\main_uart_eventmanager_pending_w[1:0] 2'00
sync always
sync init
update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0]
end
- attribute \src "ls180.v:860.11-860.48"
- process $proc$ls180.v:860$3105
+ attribute \src "ls180.v:868.11-868.48"
+ process $proc$ls180.v:868$3115
assign { } { }
assign $1\main_uart_eventmanager_storage[1:0] 2'00
sync always
sync init
update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0]
end
- attribute \src "ls180.v:861.5-861.37"
- process $proc$ls180.v:861$3106
+ attribute \src "ls180.v:869.5-869.37"
+ process $proc$ls180.v:869$3116
assign { } { }
assign $1\main_uart_eventmanager_re[0:0] 1'0
sync always
sync init
update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0]
end
- attribute \src "ls180.v:878.5-878.40"
- process $proc$ls180.v:878$3107
+ attribute \src "ls180.v:87.5-87.46"
+ process $proc$ls180.v:87$2784
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0
+ sync always
+ update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:886.5-886.40"
+ process $proc$ls180.v:886$3117
assign { } { }
assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0
sync always
update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:879.5-879.39"
- process $proc$ls180.v:879$3108
+ attribute \src "ls180.v:887.5-887.39"
+ process $proc$ls180.v:887$3118
assign { } { }
assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0
sync always
update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:887.5-887.38"
- process $proc$ls180.v:887$3109
+ attribute \src "ls180.v:895.5-895.38"
+ process $proc$ls180.v:895$3119
assign { } { }
assign $1\main_uart_tx_fifo_readable[0:0] 1'0
sync always
sync init
update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0]
end
- attribute \src "ls180.v:894.11-894.42"
- process $proc$ls180.v:894$3110
+ attribute \src "ls180.v:902.11-902.42"
+ process $proc$ls180.v:902$3120
assign { } { }
assign $1\main_uart_tx_fifo_level0[4:0] 5'00000
sync always
sync init
update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0]
end
- attribute \src "ls180.v:895.5-895.37"
- process $proc$ls180.v:895$3111
+ attribute \src "ls180.v:903.5-903.37"
+ process $proc$ls180.v:903$3121
assign { } { }
assign $0\main_uart_tx_fifo_replace[0:0] 1'0
sync always
update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0]
sync init
end
- attribute \src "ls180.v:896.11-896.43"
- process $proc$ls180.v:896$3112
+ attribute \src "ls180.v:904.11-904.43"
+ process $proc$ls180.v:904$3122
assign { } { }
assign $1\main_uart_tx_fifo_produce[3:0] 4'0000
sync always
sync init
update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0]
end
- attribute \src "ls180.v:897.11-897.43"
- process $proc$ls180.v:897$3113
+ attribute \src "ls180.v:905.11-905.43"
+ process $proc$ls180.v:905$3123
assign { } { }
assign $1\main_uart_tx_fifo_consume[3:0] 4'0000
sync always
sync init
update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0]
end
- attribute \src "ls180.v:898.11-898.46"
- process $proc$ls180.v:898$3114
+ attribute \src "ls180.v:906.11-906.46"
+ process $proc$ls180.v:906$3124
assign { } { }
assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000
sync always
sync init
update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0]
end
- attribute \src "ls180.v:924.5-924.38"
- process $proc$ls180.v:924$3115
+ attribute \src "ls180.v:932.5-932.38"
+ process $proc$ls180.v:932$3125
assign { } { }
assign $1\main_uart_rx_fifo_readable[0:0] 1'0
sync always
sync init
update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0]
end
- attribute \src "ls180.v:931.11-931.42"
- process $proc$ls180.v:931$3116
+ attribute \src "ls180.v:939.11-939.42"
+ process $proc$ls180.v:939$3126
assign { } { }
assign $1\main_uart_rx_fifo_level0[4:0] 5'00000
sync always
sync init
update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0]
end
- attribute \src "ls180.v:932.5-932.37"
- process $proc$ls180.v:932$3117
+ attribute \src "ls180.v:940.5-940.37"
+ process $proc$ls180.v:940$3127
assign { } { }
assign $0\main_uart_rx_fifo_replace[0:0] 1'0
sync always
update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0]
sync init
end
- attribute \src "ls180.v:933.11-933.43"
- process $proc$ls180.v:933$3118
+ attribute \src "ls180.v:941.11-941.43"
+ process $proc$ls180.v:941$3128
assign { } { }
assign $1\main_uart_rx_fifo_produce[3:0] 4'0000
sync always
sync init
update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0]
end
- attribute \src "ls180.v:934.11-934.43"
- process $proc$ls180.v:934$3119
+ attribute \src "ls180.v:942.11-942.43"
+ process $proc$ls180.v:942$3129
assign { } { }
assign $1\main_uart_rx_fifo_consume[3:0] 4'0000
sync always
sync init
update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0]
end
- attribute \src "ls180.v:935.11-935.46"
- process $proc$ls180.v:935$3120
+ attribute \src "ls180.v:943.11-943.46"
+ process $proc$ls180.v:943$3130
assign { } { }
assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000
sync always
sync init
update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0]
end
- attribute \src "ls180.v:950.5-950.27"
- process $proc$ls180.v:950$3121
+ attribute \src "ls180.v:958.5-958.27"
+ process $proc$ls180.v:958$3131
assign { } { }
assign $0\main_uart_reset[0:0] 1'0
sync always
update \main_uart_reset $0\main_uart_reset[0:0]
sync init
end
- attribute \src "ls180.v:951.12-951.40"
- process $proc$ls180.v:951$3122
+ attribute \src "ls180.v:959.12-959.40"
+ process $proc$ls180.v:959$3132
assign { } { }
assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000
sync always
sync init
update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0]
end
- attribute \src "ls180.v:952.5-952.27"
- process $proc$ls180.v:952$3123
+ attribute \src "ls180.v:960.5-960.27"
+ process $proc$ls180.v:960$3133
assign { } { }
assign $1\main_gpio_oe_re[0:0] 1'0
sync always
sync init
update \main_gpio_oe_re $1\main_gpio_oe_re[0:0]
end
- attribute \src "ls180.v:953.12-953.36"
- process $proc$ls180.v:953$3124
+ attribute \src "ls180.v:961.12-961.36"
+ process $proc$ls180.v:961$3134
assign { } { }
assign $1\main_gpio_status[15:0] 16'0000000000000000
sync always
sync init
update \main_gpio_status $1\main_gpio_status[15:0]
end
- attribute \src "ls180.v:955.12-955.41"
- process $proc$ls180.v:955$3125
+ attribute \src "ls180.v:963.12-963.41"
+ process $proc$ls180.v:963$3135
assign { } { }
assign $1\main_gpio_out_storage[15:0] 16'0000000000000000
sync always
sync init
update \main_gpio_out_storage $1\main_gpio_out_storage[15:0]
end
- attribute \src "ls180.v:956.5-956.28"
- process $proc$ls180.v:956$3126
+ attribute \src "ls180.v:964.5-964.28"
+ process $proc$ls180.v:964$3136
assign { } { }
assign $1\main_gpio_out_re[0:0] 1'0
sync always
sync init
update \main_gpio_out_re $1\main_gpio_out_re[0:0]
end
- attribute \src "ls180.v:962.5-962.33"
- process $proc$ls180.v:962$3127
+ attribute \src "ls180.v:970.5-970.33"
+ process $proc$ls180.v:970$3137
assign { } { }
assign $1\main_spi_master_done0[0:0] 1'0
sync always
sync init
update \main_spi_master_done0 $1\main_spi_master_done0[0:0]
end
- attribute \src "ls180.v:963.5-963.31"
- process $proc$ls180.v:963$3128
+ attribute \src "ls180.v:971.5-971.31"
+ process $proc$ls180.v:971$3138
assign { } { }
assign $1\main_spi_master_irq[0:0] 1'0
sync always
sync init
update \main_spi_master_irq $1\main_spi_master_irq[0:0]
end
- attribute \src "ls180.v:965.11-965.38"
- process $proc$ls180.v:965$3129
+ attribute \src "ls180.v:973.11-973.38"
+ process $proc$ls180.v:973$3139
assign { } { }
assign $1\main_spi_master_miso[7:0] 8'00000000
sync always
sync init
update \main_spi_master_miso $1\main_spi_master_miso[7:0]
end
- attribute \src "ls180.v:968.12-968.48"
- process $proc$ls180.v:968$3130
+ attribute \src "ls180.v:976.12-976.48"
+ process $proc$ls180.v:976$3140
assign { } { }
assign $0\main_spi_master_clk_divider0[15:0] 16'0000000000000111
sync always
update \main_spi_master_clk_divider0 $0\main_spi_master_clk_divider0[15:0]
sync init
end
- attribute \src "ls180.v:969.5-969.34"
- process $proc$ls180.v:969$3131
+ attribute \src "ls180.v:977.5-977.34"
+ process $proc$ls180.v:977$3141
assign { } { }
assign $1\main_spi_master_start1[0:0] 1'0
sync always
sync init
update \main_spi_master_start1 $1\main_spi_master_start1[0:0]
end
- attribute \src "ls180.v:971.12-971.51"
- process $proc$ls180.v:971$3132
+ attribute \src "ls180.v:979.12-979.51"
+ process $proc$ls180.v:979$3142
assign { } { }
assign $1\main_spi_master_control_storage[15:0] 16'0000000000000000
sync always
sync init
update \main_spi_master_control_storage $1\main_spi_master_control_storage[15:0]
end
- attribute \src "ls180.v:972.5-972.38"
- process $proc$ls180.v:972$3133
+ attribute \src "ls180.v:980.5-980.38"
+ process $proc$ls180.v:980$3143
assign { } { }
assign $1\main_spi_master_control_re[0:0] 1'0
sync always
sync init
update \main_spi_master_control_re $1\main_spi_master_control_re[0:0]
end
- attribute \src "ls180.v:976.11-976.46"
- process $proc$ls180.v:976$3134
+ attribute \src "ls180.v:984.11-984.46"
+ process $proc$ls180.v:984$3144
assign { } { }
assign $1\main_spi_master_mosi_storage[7:0] 8'00000000
sync always
sync init
update \main_spi_master_mosi_storage $1\main_spi_master_mosi_storage[7:0]
end
- attribute \src "ls180.v:977.5-977.35"
- process $proc$ls180.v:977$3135
+ attribute \src "ls180.v:985.5-985.35"
+ process $proc$ls180.v:985$3145
assign { } { }
assign $1\main_spi_master_mosi_re[0:0] 1'0
sync always
sync init
update \main_spi_master_mosi_re $1\main_spi_master_mosi_re[0:0]
end
- attribute \src "ls180.v:981.5-981.38"
- process $proc$ls180.v:981$3136
+ attribute \src "ls180.v:989.5-989.38"
+ process $proc$ls180.v:989$3146
assign { } { }
assign $1\main_spi_master_cs_storage[0:0] 1'1
sync always
sync init
update \main_spi_master_cs_storage $1\main_spi_master_cs_storage[0:0]
end
- attribute \src "ls180.v:982.5-982.33"
- process $proc$ls180.v:982$3137
+ attribute \src "ls180.v:990.5-990.33"
+ process $proc$ls180.v:990$3147
assign { } { }
assign $1\main_spi_master_cs_re[0:0] 1'0
sync always
sync init
update \main_spi_master_cs_re $1\main_spi_master_cs_re[0:0]
end
- attribute \src "ls180.v:983.5-983.44"
- process $proc$ls180.v:983$3138
+ attribute \src "ls180.v:991.5-991.44"
+ process $proc$ls180.v:991$3148
assign { } { }
assign $1\main_spi_master_loopback_storage[0:0] 1'0
sync always
sync init
update \main_spi_master_loopback_storage $1\main_spi_master_loopback_storage[0:0]
end
- attribute \src "ls180.v:984.5-984.39"
- process $proc$ls180.v:984$3139
+ attribute \src "ls180.v:992.5-992.39"
+ process $proc$ls180.v:992$3149
assign { } { }
assign $1\main_spi_master_loopback_re[0:0] 1'0
sync always
sync init
update \main_spi_master_loopback_re $1\main_spi_master_loopback_re[0:0]
end
- attribute \src "ls180.v:985.5-985.38"
- process $proc$ls180.v:985$3140
+ attribute \src "ls180.v:993.5-993.38"
+ process $proc$ls180.v:993$3150
assign { } { }
assign $1\main_spi_master_clk_enable[0:0] 1'0
sync always
sync init
update \main_spi_master_clk_enable $1\main_spi_master_clk_enable[0:0]
end
- attribute \src "ls180.v:986.5-986.37"
- process $proc$ls180.v:986$3141
+ attribute \src "ls180.v:994.5-994.37"
+ process $proc$ls180.v:994$3151
assign { } { }
assign $1\main_spi_master_cs_enable[0:0] 1'0
sync always
sync init
update \main_spi_master_cs_enable $1\main_spi_master_cs_enable[0:0]
end
- attribute \src "ls180.v:987.11-987.39"
- process $proc$ls180.v:987$3142
+ attribute \src "ls180.v:995.11-995.39"
+ process $proc$ls180.v:995$3152
assign { } { }
assign $1\main_spi_master_count[2:0] 3'000
sync always
sync init
update \main_spi_master_count $1\main_spi_master_count[2:0]
end
- attribute \src "ls180.v:988.5-988.38"
- process $proc$ls180.v:988$3143
+ attribute \src "ls180.v:996.5-996.38"
+ process $proc$ls180.v:996$3153
assign { } { }
assign $1\main_spi_master_mosi_latch[0:0] 1'0
sync always
sync init
update \main_spi_master_mosi_latch $1\main_spi_master_mosi_latch[0:0]
end
- attribute \src "ls180.v:989.5-989.38"
- process $proc$ls180.v:989$3144
+ attribute \src "ls180.v:997.5-997.38"
+ process $proc$ls180.v:997$3154
assign { } { }
assign $1\main_spi_master_miso_latch[0:0] 1'0
sync always
sync init
update \main_spi_master_miso_latch $1\main_spi_master_miso_latch[0:0]
end
- attribute \src "ls180.v:990.12-990.48"
- process $proc$ls180.v:990$3145
+ attribute \src "ls180.v:998.12-998.48"
+ process $proc$ls180.v:998$3155
assign { } { }
assign $1\main_spi_master_clk_divider1[15:0] 16'0000000000000000
sync always
sync init
update \main_spi_master_clk_divider1 $1\main_spi_master_clk_divider1[15:0]
end
- attribute \src "ls180.v:993.11-993.43"
- process $proc$ls180.v:993$3146
- assign { } { }
- assign $1\main_spi_master_mosi_data[7:0] 8'00000000
- sync always
- sync init
- update \main_spi_master_mosi_data $1\main_spi_master_mosi_data[7:0]
- end
- attribute \src "ls180.v:994.11-994.42"
- process $proc$ls180.v:994$3147
- assign { } { }
- assign $1\main_spi_master_mosi_sel[2:0] 3'000
- sync always
- sync init
- update \main_spi_master_mosi_sel $1\main_spi_master_mosi_sel[2:0]
- end
- attribute \src "ls180.v:995.11-995.43"
- process $proc$ls180.v:995$3148
- assign { } { }
- assign $1\main_spi_master_miso_data[7:0] 8'00000000
- sync always
- sync init
- update \main_spi_master_miso_data $1\main_spi_master_miso_data[7:0]
- end
- attribute \src "ls180.v:997.12-997.30"
- process $proc$ls180.v:997$3149
- assign { } { }
- assign $1\main_dummy[41:0] 42'000000000000000000000000000000000000000000
- sync always
- sync init
- update \main_dummy $1\main_dummy[41:0]
- end
- attribute \src "ls180.v:9977.1-9987.4"
- process $proc$ls180.v:9977$2682
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 7'xxxxxxx
- assign $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 0
- assign $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 7'xxxxxxx
- assign $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 0
- assign $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 7'xxxxxxx
- assign $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 0
- assign $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 7'xxxxxxx
- assign $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 0
- assign $0\memadr[6:0] \main_libresocsim_adr
- attribute \src "ls180.v:9978.2-9979.65"
- switch \main_libresocsim_we [0]
- attribute \src "ls180.v:9978.6-9978.28"
- case 1'1
- assign $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 \main_libresocsim_adr
- assign $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] }
- assign $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 255
- case
- end
- attribute \src "ls180.v:9980.2-9981.67"
- switch \main_libresocsim_we [1]
- attribute \src "ls180.v:9980.6-9980.28"
- case 1'1
- assign $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 \main_libresocsim_adr
- assign $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx }
- assign $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 65280
- case
- end
- attribute \src "ls180.v:9982.2-9983.69"
- switch \main_libresocsim_we [2]
- attribute \src "ls180.v:9982.6-9982.28"
- case 1'1
- assign $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 \main_libresocsim_adr
- assign $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
- assign $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 16711680
- case
- end
- attribute \src "ls180.v:9984.2-9985.69"
- switch \main_libresocsim_we [3]
- attribute \src "ls180.v:9984.6-9984.28"
- case 1'1
- assign $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 \main_libresocsim_adr
- assign $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
- assign $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 32'11111111000000000000000000000000
- case
- end
- sync posedge \sys_clk_1
- update \memadr $0\memadr[6:0]
- update $memwr$\mem$ls180.v:9979$1_ADDR $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683
- update $memwr$\mem$ls180.v:9979$1_DATA $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684
- update $memwr$\mem$ls180.v:9979$1_EN $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685
- update $memwr$\mem$ls180.v:9981$2_ADDR $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686
- update $memwr$\mem$ls180.v:9981$2_DATA $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687
- update $memwr$\mem$ls180.v:9981$2_EN $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688
- update $memwr$\mem$ls180.v:9983$3_ADDR $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689
- update $memwr$\mem$ls180.v:9983$3_DATA $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690
- update $memwr$\mem$ls180.v:9983$3_EN $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691
- update $memwr$\mem$ls180.v:9985$4_ADDR $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692
- update $memwr$\mem$ls180.v:9985$4_DATA $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693
- update $memwr$\mem$ls180.v:9985$4_EN $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694
- end
- attribute \src "ls180.v:9997.1-10001.4"
- process $proc$ls180.v:9997$2696
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 3'xxx
- assign $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 25'xxxxxxxxxxxxxxxxxxxxxxxxx
- assign $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 25'0000000000000000000000000
- assign $0\memdat[24:0] $memrd$\storage$ls180.v:10000$2700_DATA
- attribute \src "ls180.v:9998.2-9999.129"
- switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:9998.6-9998.60"
- case 1'1
- assign $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
- assign $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
- assign $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 25'1111111111111111111111111
- case
- end
- sync posedge \sys_clk_1
- update \memdat $0\memdat[24:0]
- update $memwr$\storage$ls180.v:9999$5_ADDR $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697
- update $memwr$\storage$ls180.v:9999$5_DATA $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698
- update $memwr$\storage$ls180.v:9999$5_EN $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699
- end
connect \main_libresocsim_libresoc_reset \main_libresocsim_reset
+ connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i
+ connect \sys_pll_48_o \main_libresocsim_libresoc_pll_48_o
connect \uart_tx \main_libresocsim_libresoc_constraintmanager1_uart0_tx
connect \main_libresocsim_libresoc_constraintmanager1_uart0_rx \uart_rx
connect \main_libresocsim_libresoc_constraintmanager1_gpio0_i \gpio_i
connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0
connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0
connect \main_libresocsim_bus_error \builder_error
- connect \main_libresocsim_converter0_reset $not$ls180.v:2726$14_Y
+ connect \main_libresocsim_converter0_reset $not$ls180.v:2757$14_Y
connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] }
- connect \main_libresocsim_converter1_reset $not$ls180.v:2786$25_Y
+ connect \main_libresocsim_converter1_reset $not$ls180.v:2817$25_Y
connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] }
- connect \main_libresocsim_converter2_reset $not$ls180.v:2846$36_Y
+ connect \main_libresocsim_converter2_reset $not$ls180.v:2877$36_Y
connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] }
connect \main_libresocsim_reset \main_libresocsim_reset_re
connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors
connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0]
connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r
connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w
- connect \main_libresocsim_zero_trigger $ne$ls180.v:2918$60_Y
+ connect \main_libresocsim_zero_trigger $ne$ls180.v:2949$60_Y
connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status
connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending
- connect \main_libresocsim_irq $and$ls180.v:2927$63_Y
+ connect \main_libresocsim_irq $and$ls180.v:2958$63_Y
connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger
connect \sys_clk_1 \sys_clk
connect \por_clk \sys_clk
connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n
connect \main_sdram_inti_p0_address \main_sdram_address_storage
connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage
- connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3041$70_Y
- connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3042$71_Y
+ connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3072$70_Y
+ connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3073$71_Y
connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage
connect \main_sdram_inti_p0_wrdata_mask 2'00
connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid
connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock
connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready
connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid
- connect \main_sdram_timer_wait $not$ls180.v:3073$72_Y
+ connect \main_sdram_timer_wait $not$ls180.v:3104$72_Y
connect \main_sdram_postponer_req_i \main_sdram_timer_done0
connect \main_sdram_wants_refresh \main_sdram_postponer_req_o
- connect \main_sdram_timer_done1 $eq$ls180.v:3076$73_Y
+ connect \main_sdram_timer_done1 $eq$ls180.v:3107$73_Y
connect \main_sdram_timer_done0 \main_sdram_timer_done1
connect \main_sdram_timer_count0 \main_sdram_timer_count1
- connect \main_sdram_sequencer_start1 $or$ls180.v:3079$75_Y
- connect \main_sdram_sequencer_done0 $and$ls180.v:3080$77_Y
+ connect \main_sdram_sequencer_start1 $or$ls180.v:3110$75_Y
+ connect \main_sdram_sequencer_done0 $and$ls180.v:3111$77_Y
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid
connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we
connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last
connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we
connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr
- connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3122$79_Y
- connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3123$80_Y
- connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3124$81_Y
+ connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3153$79_Y
+ connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3154$80_Y
+ connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3155$81_Y
connect \main_sdram_bankmachine0_cmd_payload_ba 2'00
- connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3134$86_Y
- connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3135$88_Y
- connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3136$90_Y
+ connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3165$86_Y
+ connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3166$88_Y
+ connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3167$90_Y
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we }
connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din
- connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3168$98_Y
- connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3169$99_Y
+ connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3199$98_Y
+ connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3200$99_Y
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r
- connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3172$100_Y
- connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3173$101_Y
- connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3174$103_Y
+ connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3203$100_Y
+ connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3204$101_Y
+ connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3205$103_Y
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid
connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we
connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last
connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we
connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr
- connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3279$109_Y
- connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3280$110_Y
- connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3281$111_Y
+ connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3310$109_Y
+ connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3311$110_Y
+ connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3312$111_Y
connect \main_sdram_bankmachine1_cmd_payload_ba 2'01
- connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3291$116_Y
- connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3292$118_Y
- connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3293$120_Y
+ connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3322$116_Y
+ connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3323$118_Y
+ connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3324$120_Y
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we }
connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din
- connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3325$128_Y
- connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3326$129_Y
+ connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3356$128_Y
+ connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3357$129_Y
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r
- connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3329$130_Y
- connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3330$131_Y
- connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3331$133_Y
+ connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3360$130_Y
+ connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3361$131_Y
+ connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3362$133_Y
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid
connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we
connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last
connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we
connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr
- connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3436$139_Y
- connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3437$140_Y
- connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3438$141_Y
+ connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3467$139_Y
+ connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3468$140_Y
+ connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3469$141_Y
connect \main_sdram_bankmachine2_cmd_payload_ba 2'10
- connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3448$146_Y
- connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3449$148_Y
- connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3450$150_Y
+ connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3479$146_Y
+ connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3480$148_Y
+ connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3481$150_Y
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we }
connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din
- connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3482$158_Y
- connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3483$159_Y
+ connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3513$158_Y
+ connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3514$159_Y
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r
- connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3486$160_Y
- connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3487$161_Y
- connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3488$163_Y
+ connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3517$160_Y
+ connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3518$161_Y
+ connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3519$163_Y
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid
connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we
connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last
connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we
connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr
- connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3593$169_Y
- connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3594$170_Y
- connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3595$171_Y
+ connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3624$169_Y
+ connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3625$170_Y
+ connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3626$171_Y
connect \main_sdram_bankmachine3_cmd_payload_ba 2'11
- connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3605$176_Y
- connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3606$178_Y
- connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3607$180_Y
+ connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3636$176_Y
+ connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3637$178_Y
+ connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3638$180_Y
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we }
connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din
- connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3639$188_Y
- connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3640$189_Y
+ connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3670$188_Y
+ connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3671$189_Y
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r
- connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3643$190_Y
- connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3644$191_Y
- connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3645$193_Y
+ connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3674$190_Y
+ connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3675$191_Y
+ connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3676$193_Y
connect \main_sdram_choose_req_want_cmds 1'1
- connect \main_sdram_trrdcon_valid $and$ls180.v:3741$204_Y
- connect \main_sdram_tfawcon_valid $and$ls180.v:3742$210_Y
- connect \main_sdram_ras_allowed $and$ls180.v:3743$211_Y
- connect \main_sdram_tccdcon_valid $and$ls180.v:3744$214_Y
+ connect \main_sdram_trrdcon_valid $and$ls180.v:3772$204_Y
+ connect \main_sdram_tfawcon_valid $and$ls180.v:3773$210_Y
+ connect \main_sdram_ras_allowed $and$ls180.v:3774$211_Y
+ connect \main_sdram_tccdcon_valid $and$ls180.v:3775$214_Y
connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready
- connect \main_sdram_twtrcon_valid $and$ls180.v:3746$216_Y
- connect \main_sdram_read_available $or$ls180.v:3747$223_Y
- connect \main_sdram_write_available $or$ls180.v:3748$230_Y
- connect \main_sdram_max_time0 $eq$ls180.v:3749$231_Y
- connect \main_sdram_max_time1 $eq$ls180.v:3750$232_Y
+ connect \main_sdram_twtrcon_valid $and$ls180.v:3777$216_Y
+ connect \main_sdram_read_available $or$ls180.v:3778$223_Y
+ connect \main_sdram_write_available $or$ls180.v:3779$230_Y
+ connect \main_sdram_max_time0 $eq$ls180.v:3780$231_Y
+ connect \main_sdram_max_time1 $eq$ls180.v:3781$232_Y
connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid
connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid
connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid
connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid
- connect \main_sdram_go_to_refresh $and$ls180.v:3755$235_Y
+ connect \main_sdram_go_to_refresh $and$ls180.v:3786$235_Y
connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata
connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata
- connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3758$236_Y
+ connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3789$236_Y
connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids
connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0
connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1
connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3
connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4
connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5
- connect \main_sdram_choose_cmd_ce $or$ls180.v:3791$294_Y
+ connect \main_sdram_choose_cmd_ce $or$ls180.v:3822$294_Y
connect \main_sdram_choose_req_request \main_sdram_choose_req_valids
connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6
connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7
connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9
connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10
connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11
- connect \main_sdram_choose_req_ce $or$ls180.v:3860$380_Y
+ connect \main_sdram_choose_req_ce $or$ls180.v:3891$380_Y
connect \main_sdram_dfi_p0_reset_n 1'1
connect \main_sdram_dfi_p0_cke \main_sdram_steerer0
connect \main_sdram_dfi_p0_odt \main_sdram_steerer1
- connect \builder_roundrobin0_request $and$ls180.v:3937$412_Y
- connect \builder_roundrobin0_ce $and$ls180.v:3938$415_Y
+ connect \builder_roundrobin0_request $and$ls180.v:3968$412_Y
+ connect \builder_roundrobin0_ce $and$ls180.v:3969$415_Y
connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12
connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13
connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14
- connect \builder_roundrobin1_request $and$ls180.v:3942$428_Y
- connect \builder_roundrobin1_ce $and$ls180.v:3943$431_Y
+ connect \builder_roundrobin1_request $and$ls180.v:3973$428_Y
+ connect \builder_roundrobin1_ce $and$ls180.v:3974$431_Y
connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15
connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16
connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17
- connect \builder_roundrobin2_request $and$ls180.v:3947$444_Y
- connect \builder_roundrobin2_ce $and$ls180.v:3948$447_Y
+ connect \builder_roundrobin2_request $and$ls180.v:3978$444_Y
+ connect \builder_roundrobin2_ce $and$ls180.v:3979$447_Y
connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18
connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19
connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20
- connect \builder_roundrobin3_request $and$ls180.v:3952$460_Y
- connect \builder_roundrobin3_ce $and$ls180.v:3953$463_Y
+ connect \builder_roundrobin3_request $and$ls180.v:3983$460_Y
+ connect \builder_roundrobin3_ce $and$ls180.v:3984$463_Y
connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21
connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22
connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23
- connect \main_port_cmd_ready $or$ls180.v:3957$527_Y
+ connect \main_port_cmd_ready $or$ls180.v:3988$527_Y
connect \main_port_wdata_ready \builder_new_master_wdata_ready
connect \main_port_rdata_valid \builder_new_master_rdata_valid3
connect \main_port_rdata_payload_data \main_sdram_interface_rdata
connect \builder_roundrobin1_grant 1'0
connect \builder_roundrobin2_grant 1'0
connect \builder_roundrobin3_grant 1'0
- connect \main_converter_reset $not$ls180.v:3979$529_Y
+ connect \main_converter_reset $not$ls180.v:4010$529_Y
connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] }
- connect \main_port_cmd_payload_addr $sub$ls180.v:4039$540_Y [23:0]
+ connect \main_port_cmd_payload_addr $sub$ls180.v:4070$540_Y [23:0]
connect \main_port_cmd_payload_we \main_litedram_wb_we
connect \main_port_wdata_payload_data \main_litedram_wb_dat_w
connect \main_port_wdata_payload_we \main_litedram_wb_sel
connect \main_litedram_wb_dat_r \main_port_rdata_payload_data
- connect \main_port_flush $not$ls180.v:4044$541_Y
- connect \main_port_cmd_last $not$ls180.v:4045$542_Y
- connect \main_port_cmd_valid $and$ls180.v:4046$545_Y
- connect \main_port_wdata_valid $and$ls180.v:4047$549_Y
- connect \main_port_rdata_ready $and$ls180.v:4048$552_Y
- connect \main_litedram_wb_ack $and$ls180.v:4049$557_Y
- connect \main_ack_cmd $or$ls180.v:4050$559_Y
- connect \main_ack_wdata $or$ls180.v:4051$561_Y
- connect \main_ack_rdata $and$ls180.v:4052$562_Y
- connect \main_uart_uart_sink_valid \main_source_valid
- connect \main_source_ready \main_uart_uart_sink_ready
- connect \main_uart_uart_sink_first \main_source_first
- connect \main_uart_uart_sink_last \main_source_last
- connect \main_uart_uart_sink_payload_data \main_source_payload_data
- connect \main_sink_valid \main_uart_uart_source_valid
- connect \main_uart_uart_source_ready \main_sink_ready
- connect \main_sink_first \main_uart_uart_source_first
- connect \main_sink_last \main_uart_uart_source_last
- connect \main_sink_payload_data \main_uart_uart_source_payload_data
+ connect \main_port_flush $not$ls180.v:4075$541_Y
+ connect \main_port_cmd_last $not$ls180.v:4076$542_Y
+ connect \main_port_cmd_valid $and$ls180.v:4077$545_Y
+ connect \main_port_wdata_valid $and$ls180.v:4078$549_Y
+ connect \main_port_rdata_ready $and$ls180.v:4079$552_Y
+ connect \main_litedram_wb_ack $and$ls180.v:4080$557_Y
+ connect \main_ack_cmd $or$ls180.v:4081$559_Y
+ connect \main_ack_wdata $or$ls180.v:4082$561_Y
+ connect \main_ack_rdata $and$ls180.v:4083$562_Y
+ connect \main_uart_uart_sink_valid \main_uart_phy_source_valid
+ connect \main_uart_phy_source_ready \main_uart_uart_sink_ready
+ connect \main_uart_uart_sink_first \main_uart_phy_source_first
+ connect \main_uart_uart_sink_last \main_uart_phy_source_last
+ connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data
+ connect \main_uart_phy_sink_valid \main_uart_uart_source_valid
+ connect \main_uart_uart_source_ready \main_uart_phy_sink_ready
+ connect \main_uart_phy_sink_first \main_uart_uart_source_first
+ connect \main_uart_phy_sink_last \main_uart_uart_source_last
+ connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data
connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re
connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r
- connect \main_uart_txfull_status $not$ls180.v:4065$563_Y
- connect \main_uart_txempty_status $not$ls180.v:4066$564_Y
+ connect \main_uart_txfull_status $not$ls180.v:4096$563_Y
+ connect \main_uart_txempty_status $not$ls180.v:4097$564_Y
connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid
connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready
connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first
connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last
connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data
- connect \main_uart_tx_trigger $not$ls180.v:4072$565_Y
+ connect \main_uart_tx_trigger $not$ls180.v:4103$565_Y
connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid
connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready
connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first
connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last
connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data
- connect \main_uart_rxempty_status $not$ls180.v:4078$566_Y
- connect \main_uart_rxfull_status $not$ls180.v:4079$567_Y
+ connect \main_uart_rxempty_status $not$ls180.v:4109$566_Y
+ connect \main_uart_rxfull_status $not$ls180.v:4110$567_Y
connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data
- connect \main_uart_rx_fifo_source_ready $or$ls180.v:4081$569_Y
- connect \main_uart_rx_trigger $not$ls180.v:4082$570_Y
- connect \main_uart_irq $or$ls180.v:4105$579_Y
+ connect \main_uart_rx_fifo_source_ready $or$ls180.v:4112$569_Y
+ connect \main_uart_rx_trigger $not$ls180.v:4113$570_Y
+ connect \main_uart_irq $or$ls180.v:4136$579_Y
connect \main_uart_tx_status \main_uart_tx_trigger
connect \main_uart_rx_status \main_uart_rx_trigger
connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data }
connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last
connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data
connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready
- connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4120$582_Y
- connect \main_uart_tx_fifo_level1 $add$ls180.v:4121$583_Y
+ connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4151$582_Y
+ connect \main_uart_tx_fifo_level1 $add$ls180.v:4152$583_Y
connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din
- connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4131$587_Y
- connect \main_uart_tx_fifo_do_read $and$ls180.v:4132$588_Y
+ connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4162$587_Y
+ connect \main_uart_tx_fifo_do_read $and$ls180.v:4163$588_Y
connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume
connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r
connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read
- connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4136$589_Y
- connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4137$590_Y
+ connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4167$589_Y
+ connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4168$590_Y
connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data }
connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout
connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable
connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last
connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data
connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready
- connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4150$593_Y
- connect \main_uart_rx_fifo_level1 $add$ls180.v:4151$594_Y
+ connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4181$593_Y
+ connect \main_uart_rx_fifo_level1 $add$ls180.v:4182$594_Y
connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din
- connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4161$598_Y
- connect \main_uart_rx_fifo_do_read $and$ls180.v:4162$599_Y
+ connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4192$598_Y
+ connect \main_uart_rx_fifo_do_read $and$ls180.v:4193$599_Y
connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume
connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r
connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read
- connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4166$600_Y
- connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4167$601_Y
+ connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4197$600_Y
+ connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4198$601_Y
connect \main_gpio_pads_i \main_libresocsim_libresoc_constraintmanager0_gpio0_i
connect \main_libresocsim_libresoc_constraintmanager0_gpio0_o \main_gpio_pads_o
connect \main_libresocsim_libresoc_constraintmanager0_gpio0_oe \main_gpio_pads_oe
connect \main_spi_master_miso_status \main_spi_master_miso
connect \main_spi_master_cs \main_spi_master_cs_storage
connect \main_spi_master_loopback \main_spi_master_loopback_storage
- connect \main_spi_master_clk_rise $eq$ls180.v:4180$603_Y
- connect \main_spi_master_clk_fall $eq$ls180.v:4181$605_Y
+ connect \main_spi_master_clk_rise $eq$ls180.v:4211$603_Y
+ connect \main_spi_master_clk_fall $eq$ls180.v:4212$605_Y
+ connect \i2c_scl \main_i2c_scl
+ connect \i2c_sda_oe \main_i2c_oe
+ connect \i2c_sda_o \main_i2c_sda0
+ connect \main_i2c_sda1 \i2c_sda_i
connect \main_sdphy_status 1'0
- connect \main_sdphy_sdpads_clk $or$ls180.v:4232$613_Y
- connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4233$617_Y
- connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4234$621_Y
- connect \main_sdphy_sdpads_data_oe $or$ls180.v:4235$625_Y
- connect \main_sdphy_sdpads_data_o $or$ls180.v:4236$629_Y
+ connect \main_sdphy_sdpads_clk $or$ls180.v:4267$613_Y
+ connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4268$617_Y
+ connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4269$621_Y
+ connect \main_sdphy_sdpads_data_oe $or$ls180.v:4270$625_Y
+ connect \main_sdphy_sdpads_data_o $or$ls180.v:4271$629_Y
connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce
connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce
connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce
connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce
connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i
connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i
- connect \main_sdphy_clocker_stop $or$ls180.v:4257$630_Y
- connect \main_sdphy_clocker_ce $and$ls180.v:4287$633_Y
+ connect \main_sdphy_clocker_stop $or$ls180.v:4292$630_Y
+ connect \main_sdphy_clocker_ce $and$ls180.v:4322$633_Y
connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid
connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready
connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first
connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i
connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o
connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe
- connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4410$643_Y
- connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4411$645_Y
+ connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4445$643_Y
+ connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4446$645_Y
connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i
connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1
connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready
connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first
connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last
connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data
- connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4428$647_Y
+ connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4463$647_Y
connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all
- connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4430$648_Y
- connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4431$650_Y
+ connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4465$648_Y
+ connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4466$650_Y
connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid
connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready
connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first
connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i
connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o
connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe
- connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4537$665_Y
- connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4538$666_Y
+ connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4572$665_Y
+ connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4573$666_Y
connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0]
connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1
connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready
connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first
connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last
connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data
- connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4555$668_Y
+ connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4590$668_Y
connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all
- connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4557$669_Y
- connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4558$671_Y
+ connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4592$669_Y
+ connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4593$671_Y
connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid
connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready
connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first
connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i
connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o
connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe
- connect \main_sdphy_datar_datar_start $eq$ls180.v:4671$680_Y
- connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4672$681_Y
+ connect \main_sdphy_datar_datar_start $eq$ls180.v:4706$680_Y
+ connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4707$681_Y
connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i
connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1
connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready
connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first
connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last
connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data
- connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4689$683_Y
+ connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4724$683_Y
connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all
- connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4691$684_Y
- connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4692$686_Y
+ connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4726$684_Y
+ connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4727$686_Y
connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid
connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready
connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first
connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0]
connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5]
connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done }
- connect \main_sdcore_data_event_status { $not$ls180.v:4808$701_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done }
+ connect \main_sdcore_data_event_status { $not$ls180.v:4843$701_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done }
connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage }
connect \main_sdcore_crc7_inserter_clr 1'1
connect \main_sdcore_crc7_inserter_enable 1'1
- connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4812$704_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4812$702_Y }
- connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4813$707_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4813$705_Y }
- connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4814$710_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4814$708_Y }
- connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4815$713_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4815$711_Y }
- connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4816$716_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4816$714_Y }
- connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4817$719_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4817$717_Y }
- connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4818$722_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4818$720_Y }
- connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4819$725_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4819$723_Y }
- connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4820$728_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4820$726_Y }
- connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4821$731_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4821$729_Y }
- connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4822$734_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4822$732_Y }
- connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4823$737_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4823$735_Y }
- connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4824$740_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4824$738_Y }
- connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4825$743_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4825$741_Y }
- connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4826$746_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4826$744_Y }
- connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4827$749_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4827$747_Y }
- connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4828$752_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4828$750_Y }
- connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4829$755_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4829$753_Y }
- connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4830$758_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4830$756_Y }
- connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4831$761_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4831$759_Y }
- connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4832$764_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4832$762_Y }
- connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4833$767_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4833$765_Y }
- connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4834$770_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4834$768_Y }
- connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4835$773_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4835$771_Y }
- connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4836$776_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4836$774_Y }
- connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4837$779_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4837$777_Y }
- connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4838$782_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4838$780_Y }
- connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4839$785_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4839$783_Y }
- connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4840$788_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4840$786_Y }
- connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4841$791_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4841$789_Y }
- connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4842$794_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4842$792_Y }
- connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4843$797_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4843$795_Y }
- connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4844$800_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4844$798_Y }
- connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4845$803_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4845$801_Y }
- connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4846$806_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4846$804_Y }
- connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4847$809_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4847$807_Y }
- connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4848$812_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4848$810_Y }
- connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4849$815_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4849$813_Y }
- connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4850$818_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4850$816_Y }
- connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4851$821_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4851$819_Y }
+ connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4847$704_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4847$702_Y }
+ connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4848$707_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4848$705_Y }
+ connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4849$710_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4849$708_Y }
+ connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4850$713_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4850$711_Y }
+ connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4851$716_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4851$714_Y }
+ connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4852$719_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4852$717_Y }
+ connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4853$722_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4853$720_Y }
+ connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4854$725_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4854$723_Y }
+ connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4855$728_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4855$726_Y }
+ connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4856$731_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4856$729_Y }
+ connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4857$734_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4857$732_Y }
+ connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4858$737_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4858$735_Y }
+ connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4859$740_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4859$738_Y }
+ connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4860$743_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4860$741_Y }
+ connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4861$746_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4861$744_Y }
+ connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4862$749_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4862$747_Y }
+ connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4863$752_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4863$750_Y }
+ connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4864$755_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4864$753_Y }
+ connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4865$758_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4865$756_Y }
+ connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4866$761_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4866$759_Y }
+ connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4867$764_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4867$762_Y }
+ connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4868$767_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4868$765_Y }
+ connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4869$770_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4869$768_Y }
+ connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4870$773_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4870$771_Y }
+ connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4871$776_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4871$774_Y }
+ connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4872$779_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4872$777_Y }
+ connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4873$782_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4873$780_Y }
+ connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4874$785_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4874$783_Y }
+ connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4875$788_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4875$786_Y }
+ connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4876$791_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4876$789_Y }
+ connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4877$794_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4877$792_Y }
+ connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4878$797_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4878$795_Y }
+ connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4879$800_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4879$798_Y }
+ connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4880$803_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4880$801_Y }
+ connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4881$806_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4881$804_Y }
+ connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4882$809_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4882$807_Y }
+ connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4883$812_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4883$810_Y }
+ connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4884$815_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4884$813_Y }
+ connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4885$818_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4885$816_Y }
+ connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4886$821_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4886$819_Y }
connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] }
- connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4861$824_Y
- connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4862$825_Y
+ connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4896$824_Y
+ connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4897$825_Y
connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] }
- connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4864$827_Y
- connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4865$828_Y
+ connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4899$827_Y
+ connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4900$828_Y
connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] }
- connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4867$830_Y
- connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4868$831_Y
+ connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4902$830_Y
+ connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4903$831_Y
connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] }
- connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4870$833_Y
- connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4871$834_Y
- connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4872$839_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4872$837_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4872$835_Y }
- connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4873$844_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4873$842_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4873$840_Y }
- connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4882$850_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4882$848_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4882$846_Y }
- connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4883$855_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4883$853_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4883$851_Y }
- connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:4892$861_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:4892$859_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:4892$857_Y }
- connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:4893$866_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:4893$864_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:4893$862_Y }
- connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:4902$872_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:4902$870_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:4902$868_Y }
- connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:4903$877_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:4903$875_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:4903$873_Y }
+ connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4905$833_Y
+ connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4906$834_Y
+ connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4907$839_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4907$837_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4907$835_Y }
+ connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4908$844_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4908$842_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4908$840_Y }
+ connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4917$850_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4917$848_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4917$846_Y }
+ connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4918$855_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4918$853_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4918$851_Y }
+ connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:4927$861_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:4927$859_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:4927$857_Y }
+ connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:4928$866_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:4928$864_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:4928$862_Y }
+ connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:4937$872_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:4937$870_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:4937$868_Y }
+ connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:4938$877_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:4938$875_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:4938$873_Y }
connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] }
- connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:4999$893_Y
+ connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5034$893_Y
connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] }
- connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5009$896_Y
+ connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5044$896_Y
connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] }
- connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5019$899_Y
+ connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5054$899_Y
connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] }
- connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5029$902_Y
+ connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5064$902_Y
connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val
connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last
- connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5054$914_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5054$912_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5054$910_Y }
- connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5055$919_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5055$917_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5055$915_Y }
- connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5064$925_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5064$923_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5064$921_Y }
- connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5065$930_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5065$928_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5065$926_Y }
- connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5074$936_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5074$934_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5074$932_Y }
- connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5075$941_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5075$939_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5075$937_Y }
- connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5084$947_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5084$945_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5084$943_Y }
- connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5085$952_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5085$950_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5085$948_Y }
+ connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5089$914_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5089$912_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5089$910_Y }
+ connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5090$919_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5090$917_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5090$915_Y }
+ connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5099$925_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5099$923_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5099$921_Y }
+ connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5100$930_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5100$928_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5100$926_Y }
+ connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5109$936_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5109$934_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5109$932_Y }
+ connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5110$941_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5110$939_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5110$937_Y }
+ connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5119$947_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5119$945_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5119$943_Y }
+ connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5120$952_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5120$950_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5120$948_Y }
connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0
connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready
connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first
connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data
connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready
connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din
- connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5321$982_Y
- connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5322$983_Y
+ connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5356$982_Y
+ connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5357$983_Y
connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume
connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r
- connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5325$984_Y
- connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5326$985_Y
+ connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5360$984_Y
+ connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5361$985_Y
connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid
connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready
connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first
connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last
connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data
- connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5332$987_Y
+ connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5367$987_Y
connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all
- connect \main_sdblock2mem_converter_load_part $and$ls180.v:5334$988_Y
+ connect \main_sdblock2mem_converter_load_part $and$ls180.v:5369$988_Y
connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1
connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1
connect \main_interface0_bus_we 1'1
connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack
connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2]
connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] }
- connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5344$989_Y
+ connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5379$989_Y
connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid
connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready
connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first
connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2]
connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] }
connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset
- connect \main_sdmem2block_dma_reset $not$ls180.v:5403$996_Y
+ connect \main_sdmem2block_dma_reset $not$ls180.v:5438$996_Y
connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid
connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1
connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first
connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last
connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data
- connect \main_sdmem2block_converter_first $eq$ls180.v:5484$1004_Y
- connect \main_sdmem2block_converter_last $eq$ls180.v:5485$1005_Y
+ connect \main_sdmem2block_converter_first $eq$ls180.v:5519$1004_Y
+ connect \main_sdmem2block_converter_last $eq$ls180.v:5520$1005_Y
connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid
- connect \main_sdmem2block_converter_source_first $and$ls180.v:5487$1006_Y
- connect \main_sdmem2block_converter_source_last $and$ls180.v:5488$1007_Y
- connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5489$1008_Y
+ connect \main_sdmem2block_converter_source_first $and$ls180.v:5522$1006_Y
+ connect \main_sdmem2block_converter_source_last $and$ls180.v:5523$1007_Y
+ connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5524$1008_Y
connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last
connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data }
connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout
connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data
connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready
connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din
- connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5529$1013_Y
- connect \main_sdmem2block_fifo_do_read $and$ls180.v:5530$1014_Y
+ connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5564$1013_Y
+ connect \main_sdmem2block_fifo_do_read $and$ls180.v:5565$1014_Y
connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume
connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r
- connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5533$1015_Y
- connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5534$1016_Y
+ connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5568$1015_Y
+ connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5569$1016_Y
connect \libresocsim_start0 \libresocsim_start1
connect \libresocsim_length0 \libresocsim_length1
connect \libresocsim_mosi \libresocsim_mosi_storage
connect \libresocsim_miso_status \libresocsim_miso
connect \libresocsim_cs \libresocsim_cs_storage
connect \libresocsim_loopback \libresocsim_loopback_storage
- connect \libresocsim_clk_rise $eq$ls180.v:5542$1018_Y
- connect \libresocsim_clk_fall $eq$ls180.v:5543$1020_Y
+ connect \libresocsim_clk_rise $eq$ls180.v:5577$1018_Y
+ connect \libresocsim_clk_fall $eq$ls180.v:5578$1020_Y
connect \libresocsim_clk_divider0 \libresocsim_storage
connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0]
connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25
connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r
connect \main_interface0_bus_dat_r \builder_shared_dat_r
connect \main_interface1_bus_dat_r \builder_shared_dat_r
- connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5644$1030_Y
- connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5645$1032_Y
- connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5646$1034_Y
- connect \main_interface0_bus_ack $and$ls180.v:5647$1036_Y
- connect \main_interface1_bus_ack $and$ls180.v:5648$1038_Y
- connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5649$1040_Y
- connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5650$1042_Y
- connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5651$1044_Y
- connect \main_interface0_bus_err $and$ls180.v:5652$1046_Y
- connect \main_interface1_bus_err $and$ls180.v:5653$1048_Y
+ connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5679$1030_Y
+ connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5680$1032_Y
+ connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5681$1034_Y
+ connect \main_interface0_bus_ack $and$ls180.v:5682$1036_Y
+ connect \main_interface1_bus_ack $and$ls180.v:5683$1038_Y
+ connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5684$1040_Y
+ connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5685$1042_Y
+ connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5686$1044_Y
+ connect \main_interface0_bus_err $and$ls180.v:5687$1046_Y
+ connect \main_interface1_bus_err $and$ls180.v:5688$1048_Y
connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc }
connect \main_libresocsim_ram_bus_adr \builder_shared_adr
connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w
connect \builder_libresocsim_wishbone_we \builder_shared_we
connect \builder_libresocsim_wishbone_cti \builder_shared_cti
connect \builder_libresocsim_wishbone_bte \builder_shared_bte
- connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5698$1055_Y
- connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5699$1056_Y
- connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5700$1057_Y
- connect \main_wb_sdram_cyc $and$ls180.v:5701$1058_Y
- connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5702$1059_Y
- connect \builder_shared_err $or$ls180.v:5703$1063_Y
- connect \builder_wait $and$ls180.v:5704$1066_Y
- connect \builder_done $eq$ls180.v:5717$1081_Y
- connect \builder_csrbank0_sel $eq$ls180.v:5718$1082_Y
+ connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5733$1055_Y
+ connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5734$1056_Y
+ connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5735$1057_Y
+ connect \main_wb_sdram_cyc $and$ls180.v:5736$1058_Y
+ connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5737$1059_Y
+ connect \builder_shared_err $or$ls180.v:5738$1063_Y
+ connect \builder_wait $and$ls180.v:5739$1066_Y
+ connect \builder_done $eq$ls180.v:5752$1081_Y
+ connect \builder_csrbank0_sel $eq$ls180.v:5753$1082_Y
connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0]
- connect \builder_csrbank0_reset0_re $and$ls180.v:5720$1085_Y
- connect \builder_csrbank0_reset0_we $and$ls180.v:5721$1089_Y
+ connect \builder_csrbank0_reset0_re $and$ls180.v:5755$1085_Y
+ connect \builder_csrbank0_reset0_we $and$ls180.v:5756$1089_Y
connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_scratch3_re $and$ls180.v:5723$1092_Y
- connect \builder_csrbank0_scratch3_we $and$ls180.v:5724$1096_Y
+ connect \builder_csrbank0_scratch3_re $and$ls180.v:5758$1092_Y
+ connect \builder_csrbank0_scratch3_we $and$ls180.v:5759$1096_Y
connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_scratch2_re $and$ls180.v:5726$1099_Y
- connect \builder_csrbank0_scratch2_we $and$ls180.v:5727$1103_Y
+ connect \builder_csrbank0_scratch2_re $and$ls180.v:5761$1099_Y
+ connect \builder_csrbank0_scratch2_we $and$ls180.v:5762$1103_Y
connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_scratch1_re $and$ls180.v:5729$1106_Y
- connect \builder_csrbank0_scratch1_we $and$ls180.v:5730$1110_Y
+ connect \builder_csrbank0_scratch1_re $and$ls180.v:5764$1106_Y
+ connect \builder_csrbank0_scratch1_we $and$ls180.v:5765$1110_Y
connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_scratch0_re $and$ls180.v:5732$1113_Y
- connect \builder_csrbank0_scratch0_we $and$ls180.v:5733$1117_Y
+ connect \builder_csrbank0_scratch0_re $and$ls180.v:5767$1113_Y
+ connect \builder_csrbank0_scratch0_we $and$ls180.v:5768$1117_Y
connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5735$1120_Y
- connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5736$1124_Y
+ connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5770$1120_Y
+ connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5771$1124_Y
connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5738$1127_Y
- connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5739$1131_Y
+ connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5773$1127_Y
+ connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5774$1131_Y
connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5741$1134_Y
- connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5742$1138_Y
+ connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5776$1134_Y
+ connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5777$1138_Y
connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w
- connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5744$1141_Y
- connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5745$1145_Y
+ connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5779$1141_Y
+ connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5780$1145_Y
connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage
connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24]
connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16]
connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8]
connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0]
connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we
- connect \builder_csrbank1_sel $eq$ls180.v:5756$1146_Y
+ connect \builder_csrbank1_sel $eq$ls180.v:5791$1146_Y
connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w
- connect \builder_csrbank1_oe1_re $and$ls180.v:5758$1149_Y
- connect \builder_csrbank1_oe1_we $and$ls180.v:5759$1153_Y
+ connect \builder_csrbank1_oe1_re $and$ls180.v:5793$1149_Y
+ connect \builder_csrbank1_oe1_we $and$ls180.v:5794$1153_Y
connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w
- connect \builder_csrbank1_oe0_re $and$ls180.v:5761$1156_Y
- connect \builder_csrbank1_oe0_we $and$ls180.v:5762$1160_Y
+ connect \builder_csrbank1_oe0_re $and$ls180.v:5796$1156_Y
+ connect \builder_csrbank1_oe0_we $and$ls180.v:5797$1160_Y
connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w
- connect \builder_csrbank1_in1_re $and$ls180.v:5764$1163_Y
- connect \builder_csrbank1_in1_we $and$ls180.v:5765$1167_Y
+ connect \builder_csrbank1_in1_re $and$ls180.v:5799$1163_Y
+ connect \builder_csrbank1_in1_we $and$ls180.v:5800$1167_Y
connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w
- connect \builder_csrbank1_in0_re $and$ls180.v:5767$1170_Y
- connect \builder_csrbank1_in0_we $and$ls180.v:5768$1174_Y
+ connect \builder_csrbank1_in0_re $and$ls180.v:5802$1170_Y
+ connect \builder_csrbank1_in0_we $and$ls180.v:5803$1174_Y
connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w
- connect \builder_csrbank1_out1_re $and$ls180.v:5770$1177_Y
- connect \builder_csrbank1_out1_we $and$ls180.v:5771$1181_Y
+ connect \builder_csrbank1_out1_re $and$ls180.v:5805$1177_Y
+ connect \builder_csrbank1_out1_we $and$ls180.v:5806$1181_Y
connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w
- connect \builder_csrbank1_out0_re $and$ls180.v:5773$1184_Y
- connect \builder_csrbank1_out0_we $and$ls180.v:5774$1188_Y
+ connect \builder_csrbank1_out0_re $and$ls180.v:5808$1184_Y
+ connect \builder_csrbank1_out0_we $and$ls180.v:5809$1188_Y
connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8]
connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0]
connect \builder_csrbank1_in1_w \main_gpio_status [15:8]
connect \main_gpio_we \builder_csrbank1_in0_we
connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8]
connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0]
- connect \builder_csrbank2_sel $eq$ls180.v:5782$1189_Y
- connect \builder_csrbank2_enable0_r \builder_interface2_bank_bus_dat_w [0]
- connect \builder_csrbank2_enable0_re $and$ls180.v:5784$1192_Y
- connect \builder_csrbank2_enable0_we $and$ls180.v:5785$1196_Y
- connect \builder_csrbank2_width3_r \builder_interface2_bank_bus_dat_w
- connect \builder_csrbank2_width3_re $and$ls180.v:5787$1199_Y
- connect \builder_csrbank2_width3_we $and$ls180.v:5788$1203_Y
- connect \builder_csrbank2_width2_r \builder_interface2_bank_bus_dat_w
- connect \builder_csrbank2_width2_re $and$ls180.v:5790$1206_Y
- connect \builder_csrbank2_width2_we $and$ls180.v:5791$1210_Y
- connect \builder_csrbank2_width1_r \builder_interface2_bank_bus_dat_w
- connect \builder_csrbank2_width1_re $and$ls180.v:5793$1213_Y
- connect \builder_csrbank2_width1_we $and$ls180.v:5794$1217_Y
- connect \builder_csrbank2_width0_r \builder_interface2_bank_bus_dat_w
- connect \builder_csrbank2_width0_re $and$ls180.v:5796$1220_Y
- connect \builder_csrbank2_width0_we $and$ls180.v:5797$1224_Y
- connect \builder_csrbank2_period3_r \builder_interface2_bank_bus_dat_w
- connect \builder_csrbank2_period3_re $and$ls180.v:5799$1227_Y
- connect \builder_csrbank2_period3_we $and$ls180.v:5800$1231_Y
- connect \builder_csrbank2_period2_r \builder_interface2_bank_bus_dat_w
- connect \builder_csrbank2_period2_re $and$ls180.v:5802$1234_Y
- connect \builder_csrbank2_period2_we $and$ls180.v:5803$1238_Y
- connect \builder_csrbank2_period1_r \builder_interface2_bank_bus_dat_w
- connect \builder_csrbank2_period1_re $and$ls180.v:5805$1241_Y
- connect \builder_csrbank2_period1_we $and$ls180.v:5806$1245_Y
- connect \builder_csrbank2_period0_r \builder_interface2_bank_bus_dat_w
- connect \builder_csrbank2_period0_re $and$ls180.v:5808$1248_Y
- connect \builder_csrbank2_period0_we $and$ls180.v:5809$1252_Y
- connect \builder_csrbank2_enable0_w \main_pwm0_enable_storage
- connect \builder_csrbank2_width3_w \main_pwm0_width_storage [31:24]
- connect \builder_csrbank2_width2_w \main_pwm0_width_storage [23:16]
- connect \builder_csrbank2_width1_w \main_pwm0_width_storage [15:8]
- connect \builder_csrbank2_width0_w \main_pwm0_width_storage [7:0]
- connect \builder_csrbank2_period3_w \main_pwm0_period_storage [31:24]
- connect \builder_csrbank2_period2_w \main_pwm0_period_storage [23:16]
- connect \builder_csrbank2_period1_w \main_pwm0_period_storage [15:8]
- connect \builder_csrbank2_period0_w \main_pwm0_period_storage [7:0]
- connect \builder_csrbank3_sel $eq$ls180.v:5819$1253_Y
+ connect \builder_csrbank2_sel $eq$ls180.v:5817$1189_Y
+ connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0]
+ connect \builder_csrbank2_w0_re $and$ls180.v:5819$1192_Y
+ connect \builder_csrbank2_w0_we $and$ls180.v:5820$1196_Y
+ connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0]
+ connect \builder_csrbank2_r_re $and$ls180.v:5822$1199_Y
+ connect \builder_csrbank2_r_we $and$ls180.v:5823$1203_Y
+ connect \main_i2c_scl \main_i2c_storage [0]
+ connect \main_i2c_oe \main_i2c_storage [1]
+ connect \main_i2c_sda0 \main_i2c_storage [2]
+ connect \builder_csrbank2_w0_w \main_i2c_storage
+ connect \main_i2c_status \main_i2c_sda1
+ connect \builder_csrbank2_r_w \main_i2c_status
+ connect \main_i2c_we \builder_csrbank2_r_we
+ connect \builder_csrbank3_sel $eq$ls180.v:5831$1204_Y
connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0]
- connect \builder_csrbank3_enable0_re $and$ls180.v:5821$1256_Y
- connect \builder_csrbank3_enable0_we $and$ls180.v:5822$1260_Y
+ connect \builder_csrbank3_enable0_re $and$ls180.v:5833$1207_Y
+ connect \builder_csrbank3_enable0_we $and$ls180.v:5834$1211_Y
connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_width3_re $and$ls180.v:5824$1263_Y
- connect \builder_csrbank3_width3_we $and$ls180.v:5825$1267_Y
+ connect \builder_csrbank3_width3_re $and$ls180.v:5836$1214_Y
+ connect \builder_csrbank3_width3_we $and$ls180.v:5837$1218_Y
connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_width2_re $and$ls180.v:5827$1270_Y
- connect \builder_csrbank3_width2_we $and$ls180.v:5828$1274_Y
+ connect \builder_csrbank3_width2_re $and$ls180.v:5839$1221_Y
+ connect \builder_csrbank3_width2_we $and$ls180.v:5840$1225_Y
connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_width1_re $and$ls180.v:5830$1277_Y
- connect \builder_csrbank3_width1_we $and$ls180.v:5831$1281_Y
+ connect \builder_csrbank3_width1_re $and$ls180.v:5842$1228_Y
+ connect \builder_csrbank3_width1_we $and$ls180.v:5843$1232_Y
connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_width0_re $and$ls180.v:5833$1284_Y
- connect \builder_csrbank3_width0_we $and$ls180.v:5834$1288_Y
+ connect \builder_csrbank3_width0_re $and$ls180.v:5845$1235_Y
+ connect \builder_csrbank3_width0_we $and$ls180.v:5846$1239_Y
connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_period3_re $and$ls180.v:5836$1291_Y
- connect \builder_csrbank3_period3_we $and$ls180.v:5837$1295_Y
+ connect \builder_csrbank3_period3_re $and$ls180.v:5848$1242_Y
+ connect \builder_csrbank3_period3_we $and$ls180.v:5849$1246_Y
connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_period2_re $and$ls180.v:5839$1298_Y
- connect \builder_csrbank3_period2_we $and$ls180.v:5840$1302_Y
+ connect \builder_csrbank3_period2_re $and$ls180.v:5851$1249_Y
+ connect \builder_csrbank3_period2_we $and$ls180.v:5852$1253_Y
connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_period1_re $and$ls180.v:5842$1305_Y
- connect \builder_csrbank3_period1_we $and$ls180.v:5843$1309_Y
+ connect \builder_csrbank3_period1_re $and$ls180.v:5854$1256_Y
+ connect \builder_csrbank3_period1_we $and$ls180.v:5855$1260_Y
connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w
- connect \builder_csrbank3_period0_re $and$ls180.v:5845$1312_Y
- connect \builder_csrbank3_period0_we $and$ls180.v:5846$1316_Y
- connect \builder_csrbank3_enable0_w \main_pwm1_enable_storage
- connect \builder_csrbank3_width3_w \main_pwm1_width_storage [31:24]
- connect \builder_csrbank3_width2_w \main_pwm1_width_storage [23:16]
- connect \builder_csrbank3_width1_w \main_pwm1_width_storage [15:8]
- connect \builder_csrbank3_width0_w \main_pwm1_width_storage [7:0]
- connect \builder_csrbank3_period3_w \main_pwm1_period_storage [31:24]
- connect \builder_csrbank3_period2_w \main_pwm1_period_storage [23:16]
- connect \builder_csrbank3_period1_w \main_pwm1_period_storage [15:8]
- connect \builder_csrbank3_period0_w \main_pwm1_period_storage [7:0]
- connect \builder_csrbank4_sel $eq$ls180.v:5856$1317_Y
- connect \builder_csrbank4_dma_base7_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_dma_base7_re $and$ls180.v:5858$1320_Y
- connect \builder_csrbank4_dma_base7_we $and$ls180.v:5859$1324_Y
- connect \builder_csrbank4_dma_base6_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_dma_base6_re $and$ls180.v:5861$1327_Y
- connect \builder_csrbank4_dma_base6_we $and$ls180.v:5862$1331_Y
- connect \builder_csrbank4_dma_base5_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_dma_base5_re $and$ls180.v:5864$1334_Y
- connect \builder_csrbank4_dma_base5_we $and$ls180.v:5865$1338_Y
- connect \builder_csrbank4_dma_base4_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_dma_base4_re $and$ls180.v:5867$1341_Y
- connect \builder_csrbank4_dma_base4_we $and$ls180.v:5868$1345_Y
- connect \builder_csrbank4_dma_base3_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_dma_base3_re $and$ls180.v:5870$1348_Y
- connect \builder_csrbank4_dma_base3_we $and$ls180.v:5871$1352_Y
- connect \builder_csrbank4_dma_base2_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_dma_base2_re $and$ls180.v:5873$1355_Y
- connect \builder_csrbank4_dma_base2_we $and$ls180.v:5874$1359_Y
- connect \builder_csrbank4_dma_base1_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_dma_base1_re $and$ls180.v:5876$1362_Y
- connect \builder_csrbank4_dma_base1_we $and$ls180.v:5877$1366_Y
- connect \builder_csrbank4_dma_base0_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_dma_base0_re $and$ls180.v:5879$1369_Y
- connect \builder_csrbank4_dma_base0_we $and$ls180.v:5880$1373_Y
- connect \builder_csrbank4_dma_length3_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_dma_length3_re $and$ls180.v:5882$1376_Y
- connect \builder_csrbank4_dma_length3_we $and$ls180.v:5883$1380_Y
- connect \builder_csrbank4_dma_length2_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_dma_length2_re $and$ls180.v:5885$1383_Y
- connect \builder_csrbank4_dma_length2_we $and$ls180.v:5886$1387_Y
- connect \builder_csrbank4_dma_length1_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_dma_length1_re $and$ls180.v:5888$1390_Y
- connect \builder_csrbank4_dma_length1_we $and$ls180.v:5889$1394_Y
- connect \builder_csrbank4_dma_length0_r \builder_interface4_bank_bus_dat_w
- connect \builder_csrbank4_dma_length0_re $and$ls180.v:5891$1397_Y
- connect \builder_csrbank4_dma_length0_we $and$ls180.v:5892$1401_Y
- connect \builder_csrbank4_dma_enable0_r \builder_interface4_bank_bus_dat_w [0]
- connect \builder_csrbank4_dma_enable0_re $and$ls180.v:5894$1404_Y
- connect \builder_csrbank4_dma_enable0_we $and$ls180.v:5895$1408_Y
- connect \builder_csrbank4_dma_done_r \builder_interface4_bank_bus_dat_w [0]
- connect \builder_csrbank4_dma_done_re $and$ls180.v:5897$1411_Y
- connect \builder_csrbank4_dma_done_we $and$ls180.v:5898$1415_Y
- connect \builder_csrbank4_dma_loop0_r \builder_interface4_bank_bus_dat_w [0]
- connect \builder_csrbank4_dma_loop0_re $and$ls180.v:5900$1418_Y
- connect \builder_csrbank4_dma_loop0_we $and$ls180.v:5901$1422_Y
- connect \builder_csrbank4_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56]
- connect \builder_csrbank4_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48]
- connect \builder_csrbank4_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40]
- connect \builder_csrbank4_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32]
- connect \builder_csrbank4_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24]
- connect \builder_csrbank4_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16]
- connect \builder_csrbank4_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8]
- connect \builder_csrbank4_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0]
- connect \builder_csrbank4_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24]
- connect \builder_csrbank4_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16]
- connect \builder_csrbank4_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8]
- connect \builder_csrbank4_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0]
- connect \builder_csrbank4_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage
- connect \builder_csrbank4_dma_done_w \main_sdblock2mem_wishbonedmawriter_status
- connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank4_dma_done_we
- connect \builder_csrbank4_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage
- connect \builder_csrbank5_sel $eq$ls180.v:5918$1423_Y
- connect \builder_csrbank5_cmd_argument3_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_argument3_re $and$ls180.v:5920$1426_Y
- connect \builder_csrbank5_cmd_argument3_we $and$ls180.v:5921$1430_Y
- connect \builder_csrbank5_cmd_argument2_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_argument2_re $and$ls180.v:5923$1433_Y
- connect \builder_csrbank5_cmd_argument2_we $and$ls180.v:5924$1437_Y
- connect \builder_csrbank5_cmd_argument1_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_argument1_re $and$ls180.v:5926$1440_Y
- connect \builder_csrbank5_cmd_argument1_we $and$ls180.v:5927$1444_Y
- connect \builder_csrbank5_cmd_argument0_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_argument0_re $and$ls180.v:5929$1447_Y
- connect \builder_csrbank5_cmd_argument0_we $and$ls180.v:5930$1451_Y
- connect \builder_csrbank5_cmd_command3_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_command3_re $and$ls180.v:5932$1454_Y
- connect \builder_csrbank5_cmd_command3_we $and$ls180.v:5933$1458_Y
- connect \builder_csrbank5_cmd_command2_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_command2_re $and$ls180.v:5935$1461_Y
- connect \builder_csrbank5_cmd_command2_we $and$ls180.v:5936$1465_Y
- connect \builder_csrbank5_cmd_command1_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_command1_re $and$ls180.v:5938$1468_Y
- connect \builder_csrbank5_cmd_command1_we $and$ls180.v:5939$1472_Y
- connect \builder_csrbank5_cmd_command0_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_command0_re $and$ls180.v:5941$1475_Y
- connect \builder_csrbank5_cmd_command0_we $and$ls180.v:5942$1479_Y
- connect \main_sdcore_cmd_send_r \builder_interface5_bank_bus_dat_w [0]
- connect \main_sdcore_cmd_send_re $and$ls180.v:5944$1482_Y
- connect \main_sdcore_cmd_send_we $and$ls180.v:5945$1486_Y
- connect \builder_csrbank5_cmd_response15_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response15_re $and$ls180.v:5947$1489_Y
- connect \builder_csrbank5_cmd_response15_we $and$ls180.v:5948$1493_Y
- connect \builder_csrbank5_cmd_response14_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response14_re $and$ls180.v:5950$1496_Y
- connect \builder_csrbank5_cmd_response14_we $and$ls180.v:5951$1500_Y
- connect \builder_csrbank5_cmd_response13_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response13_re $and$ls180.v:5953$1503_Y
- connect \builder_csrbank5_cmd_response13_we $and$ls180.v:5954$1507_Y
- connect \builder_csrbank5_cmd_response12_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response12_re $and$ls180.v:5956$1510_Y
- connect \builder_csrbank5_cmd_response12_we $and$ls180.v:5957$1514_Y
- connect \builder_csrbank5_cmd_response11_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response11_re $and$ls180.v:5959$1517_Y
- connect \builder_csrbank5_cmd_response11_we $and$ls180.v:5960$1521_Y
- connect \builder_csrbank5_cmd_response10_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response10_re $and$ls180.v:5962$1524_Y
- connect \builder_csrbank5_cmd_response10_we $and$ls180.v:5963$1528_Y
- connect \builder_csrbank5_cmd_response9_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response9_re $and$ls180.v:5965$1531_Y
- connect \builder_csrbank5_cmd_response9_we $and$ls180.v:5966$1535_Y
- connect \builder_csrbank5_cmd_response8_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response8_re $and$ls180.v:5968$1538_Y
- connect \builder_csrbank5_cmd_response8_we $and$ls180.v:5969$1542_Y
- connect \builder_csrbank5_cmd_response7_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response7_re $and$ls180.v:5971$1545_Y
- connect \builder_csrbank5_cmd_response7_we $and$ls180.v:5972$1549_Y
- connect \builder_csrbank5_cmd_response6_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response6_re $and$ls180.v:5974$1552_Y
- connect \builder_csrbank5_cmd_response6_we $and$ls180.v:5975$1556_Y
- connect \builder_csrbank5_cmd_response5_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response5_re $and$ls180.v:5977$1559_Y
- connect \builder_csrbank5_cmd_response5_we $and$ls180.v:5978$1563_Y
- connect \builder_csrbank5_cmd_response4_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response4_re $and$ls180.v:5980$1566_Y
- connect \builder_csrbank5_cmd_response4_we $and$ls180.v:5981$1570_Y
- connect \builder_csrbank5_cmd_response3_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response3_re $and$ls180.v:5983$1573_Y
- connect \builder_csrbank5_cmd_response3_we $and$ls180.v:5984$1577_Y
- connect \builder_csrbank5_cmd_response2_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response2_re $and$ls180.v:5986$1580_Y
- connect \builder_csrbank5_cmd_response2_we $and$ls180.v:5987$1584_Y
- connect \builder_csrbank5_cmd_response1_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response1_re $and$ls180.v:5989$1587_Y
- connect \builder_csrbank5_cmd_response1_we $and$ls180.v:5990$1591_Y
- connect \builder_csrbank5_cmd_response0_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_cmd_response0_re $and$ls180.v:5992$1594_Y
- connect \builder_csrbank5_cmd_response0_we $and$ls180.v:5993$1598_Y
- connect \builder_csrbank5_cmd_event_r \builder_interface5_bank_bus_dat_w [3:0]
- connect \builder_csrbank5_cmd_event_re $and$ls180.v:5995$1601_Y
- connect \builder_csrbank5_cmd_event_we $and$ls180.v:5996$1605_Y
- connect \builder_csrbank5_data_event_r \builder_interface5_bank_bus_dat_w [3:0]
- connect \builder_csrbank5_data_event_re $and$ls180.v:5998$1608_Y
- connect \builder_csrbank5_data_event_we $and$ls180.v:5999$1612_Y
- connect \builder_csrbank5_block_length1_r \builder_interface5_bank_bus_dat_w [1:0]
- connect \builder_csrbank5_block_length1_re $and$ls180.v:6001$1615_Y
- connect \builder_csrbank5_block_length1_we $and$ls180.v:6002$1619_Y
- connect \builder_csrbank5_block_length0_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_block_length0_re $and$ls180.v:6004$1622_Y
- connect \builder_csrbank5_block_length0_we $and$ls180.v:6005$1626_Y
- connect \builder_csrbank5_block_count3_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_block_count3_re $and$ls180.v:6007$1629_Y
- connect \builder_csrbank5_block_count3_we $and$ls180.v:6008$1633_Y
- connect \builder_csrbank5_block_count2_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_block_count2_re $and$ls180.v:6010$1636_Y
- connect \builder_csrbank5_block_count2_we $and$ls180.v:6011$1640_Y
- connect \builder_csrbank5_block_count1_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_block_count1_re $and$ls180.v:6013$1643_Y
- connect \builder_csrbank5_block_count1_we $and$ls180.v:6014$1647_Y
- connect \builder_csrbank5_block_count0_r \builder_interface5_bank_bus_dat_w
- connect \builder_csrbank5_block_count0_re $and$ls180.v:6016$1650_Y
- connect \builder_csrbank5_block_count0_we $and$ls180.v:6017$1654_Y
- connect \builder_csrbank5_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24]
- connect \builder_csrbank5_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16]
- connect \builder_csrbank5_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8]
- connect \builder_csrbank5_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0]
- connect \builder_csrbank5_cmd_command3_w \main_sdcore_cmd_command_storage [31:24]
- connect \builder_csrbank5_cmd_command2_w \main_sdcore_cmd_command_storage [23:16]
- connect \builder_csrbank5_cmd_command1_w \main_sdcore_cmd_command_storage [15:8]
- connect \builder_csrbank5_cmd_command0_w \main_sdcore_cmd_command_storage [7:0]
- connect \builder_csrbank5_cmd_response15_w \main_sdcore_cmd_response_status [127:120]
- connect \builder_csrbank5_cmd_response14_w \main_sdcore_cmd_response_status [119:112]
- connect \builder_csrbank5_cmd_response13_w \main_sdcore_cmd_response_status [111:104]
- connect \builder_csrbank5_cmd_response12_w \main_sdcore_cmd_response_status [103:96]
- connect \builder_csrbank5_cmd_response11_w \main_sdcore_cmd_response_status [95:88]
- connect \builder_csrbank5_cmd_response10_w \main_sdcore_cmd_response_status [87:80]
- connect \builder_csrbank5_cmd_response9_w \main_sdcore_cmd_response_status [79:72]
- connect \builder_csrbank5_cmd_response8_w \main_sdcore_cmd_response_status [71:64]
- connect \builder_csrbank5_cmd_response7_w \main_sdcore_cmd_response_status [63:56]
- connect \builder_csrbank5_cmd_response6_w \main_sdcore_cmd_response_status [55:48]
- connect \builder_csrbank5_cmd_response5_w \main_sdcore_cmd_response_status [47:40]
- connect \builder_csrbank5_cmd_response4_w \main_sdcore_cmd_response_status [39:32]
- connect \builder_csrbank5_cmd_response3_w \main_sdcore_cmd_response_status [31:24]
- connect \builder_csrbank5_cmd_response2_w \main_sdcore_cmd_response_status [23:16]
- connect \builder_csrbank5_cmd_response1_w \main_sdcore_cmd_response_status [15:8]
- connect \builder_csrbank5_cmd_response0_w \main_sdcore_cmd_response_status [7:0]
- connect \main_sdcore_cmd_response_we \builder_csrbank5_cmd_response0_we
- connect \builder_csrbank5_cmd_event_w \main_sdcore_cmd_event_status
- connect \main_sdcore_cmd_event_we \builder_csrbank5_cmd_event_we
- connect \builder_csrbank5_data_event_w \main_sdcore_data_event_status
- connect \main_sdcore_data_event_we \builder_csrbank5_data_event_we
- connect \builder_csrbank5_block_length1_w \main_sdcore_block_length_storage [9:8]
- connect \builder_csrbank5_block_length0_w \main_sdcore_block_length_storage [7:0]
- connect \builder_csrbank5_block_count3_w \main_sdcore_block_count_storage [31:24]
- connect \builder_csrbank5_block_count2_w \main_sdcore_block_count_storage [23:16]
- connect \builder_csrbank5_block_count1_w \main_sdcore_block_count_storage [15:8]
- connect \builder_csrbank5_block_count0_w \main_sdcore_block_count_storage [7:0]
- connect \builder_csrbank6_sel $eq$ls180.v:6053$1655_Y
- connect \builder_csrbank6_dma_base7_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_base7_re $and$ls180.v:6055$1658_Y
- connect \builder_csrbank6_dma_base7_we $and$ls180.v:6056$1662_Y
- connect \builder_csrbank6_dma_base6_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_base6_re $and$ls180.v:6058$1665_Y
- connect \builder_csrbank6_dma_base6_we $and$ls180.v:6059$1669_Y
- connect \builder_csrbank6_dma_base5_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_base5_re $and$ls180.v:6061$1672_Y
- connect \builder_csrbank6_dma_base5_we $and$ls180.v:6062$1676_Y
- connect \builder_csrbank6_dma_base4_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_base4_re $and$ls180.v:6064$1679_Y
- connect \builder_csrbank6_dma_base4_we $and$ls180.v:6065$1683_Y
- connect \builder_csrbank6_dma_base3_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_base3_re $and$ls180.v:6067$1686_Y
- connect \builder_csrbank6_dma_base3_we $and$ls180.v:6068$1690_Y
- connect \builder_csrbank6_dma_base2_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_base2_re $and$ls180.v:6070$1693_Y
- connect \builder_csrbank6_dma_base2_we $and$ls180.v:6071$1697_Y
- connect \builder_csrbank6_dma_base1_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_base1_re $and$ls180.v:6073$1700_Y
- connect \builder_csrbank6_dma_base1_we $and$ls180.v:6074$1704_Y
- connect \builder_csrbank6_dma_base0_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_base0_re $and$ls180.v:6076$1707_Y
- connect \builder_csrbank6_dma_base0_we $and$ls180.v:6077$1711_Y
- connect \builder_csrbank6_dma_length3_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_length3_re $and$ls180.v:6079$1714_Y
- connect \builder_csrbank6_dma_length3_we $and$ls180.v:6080$1718_Y
- connect \builder_csrbank6_dma_length2_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_length2_re $and$ls180.v:6082$1721_Y
- connect \builder_csrbank6_dma_length2_we $and$ls180.v:6083$1725_Y
- connect \builder_csrbank6_dma_length1_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_length1_re $and$ls180.v:6085$1728_Y
- connect \builder_csrbank6_dma_length1_we $and$ls180.v:6086$1732_Y
- connect \builder_csrbank6_dma_length0_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_length0_re $and$ls180.v:6088$1735_Y
- connect \builder_csrbank6_dma_length0_we $and$ls180.v:6089$1739_Y
- connect \builder_csrbank6_dma_enable0_r \builder_interface6_bank_bus_dat_w [0]
- connect \builder_csrbank6_dma_enable0_re $and$ls180.v:6091$1742_Y
- connect \builder_csrbank6_dma_enable0_we $and$ls180.v:6092$1746_Y
- connect \builder_csrbank6_dma_done_r \builder_interface6_bank_bus_dat_w [0]
- connect \builder_csrbank6_dma_done_re $and$ls180.v:6094$1749_Y
- connect \builder_csrbank6_dma_done_we $and$ls180.v:6095$1753_Y
- connect \builder_csrbank6_dma_loop0_r \builder_interface6_bank_bus_dat_w [0]
- connect \builder_csrbank6_dma_loop0_re $and$ls180.v:6097$1756_Y
- connect \builder_csrbank6_dma_loop0_we $and$ls180.v:6098$1760_Y
- connect \builder_csrbank6_dma_offset3_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_offset3_re $and$ls180.v:6100$1763_Y
- connect \builder_csrbank6_dma_offset3_we $and$ls180.v:6101$1767_Y
- connect \builder_csrbank6_dma_offset2_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_offset2_re $and$ls180.v:6103$1770_Y
- connect \builder_csrbank6_dma_offset2_we $and$ls180.v:6104$1774_Y
- connect \builder_csrbank6_dma_offset1_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_offset1_re $and$ls180.v:6106$1777_Y
- connect \builder_csrbank6_dma_offset1_we $and$ls180.v:6107$1781_Y
- connect \builder_csrbank6_dma_offset0_r \builder_interface6_bank_bus_dat_w
- connect \builder_csrbank6_dma_offset0_re $and$ls180.v:6109$1784_Y
- connect \builder_csrbank6_dma_offset0_we $and$ls180.v:6110$1788_Y
- connect \builder_csrbank6_dma_base7_w \main_sdmem2block_dma_base_storage [63:56]
- connect \builder_csrbank6_dma_base6_w \main_sdmem2block_dma_base_storage [55:48]
- connect \builder_csrbank6_dma_base5_w \main_sdmem2block_dma_base_storage [47:40]
- connect \builder_csrbank6_dma_base4_w \main_sdmem2block_dma_base_storage [39:32]
- connect \builder_csrbank6_dma_base3_w \main_sdmem2block_dma_base_storage [31:24]
- connect \builder_csrbank6_dma_base2_w \main_sdmem2block_dma_base_storage [23:16]
- connect \builder_csrbank6_dma_base1_w \main_sdmem2block_dma_base_storage [15:8]
- connect \builder_csrbank6_dma_base0_w \main_sdmem2block_dma_base_storage [7:0]
- connect \builder_csrbank6_dma_length3_w \main_sdmem2block_dma_length_storage [31:24]
- connect \builder_csrbank6_dma_length2_w \main_sdmem2block_dma_length_storage [23:16]
- connect \builder_csrbank6_dma_length1_w \main_sdmem2block_dma_length_storage [15:8]
- connect \builder_csrbank6_dma_length0_w \main_sdmem2block_dma_length_storage [7:0]
- connect \builder_csrbank6_dma_enable0_w \main_sdmem2block_dma_enable_storage
- connect \builder_csrbank6_dma_done_w \main_sdmem2block_dma_done_status
- connect \main_sdmem2block_dma_done_we \builder_csrbank6_dma_done_we
- connect \builder_csrbank6_dma_loop0_w \main_sdmem2block_dma_loop_storage
- connect \builder_csrbank6_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24]
- connect \builder_csrbank6_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16]
- connect \builder_csrbank6_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8]
- connect \builder_csrbank6_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0]
- connect \main_sdmem2block_dma_offset_we \builder_csrbank6_dma_offset0_we
- connect \builder_csrbank7_sel $eq$ls180.v:6132$1789_Y
- connect \builder_csrbank7_card_detect_r \builder_interface7_bank_bus_dat_w [0]
- connect \builder_csrbank7_card_detect_re $and$ls180.v:6134$1792_Y
- connect \builder_csrbank7_card_detect_we $and$ls180.v:6135$1796_Y
- connect \builder_csrbank7_clocker_divider1_r \builder_interface7_bank_bus_dat_w [0]
- connect \builder_csrbank7_clocker_divider1_re $and$ls180.v:6137$1799_Y
- connect \builder_csrbank7_clocker_divider1_we $and$ls180.v:6138$1803_Y
- connect \builder_csrbank7_clocker_divider0_r \builder_interface7_bank_bus_dat_w
- connect \builder_csrbank7_clocker_divider0_re $and$ls180.v:6140$1806_Y
- connect \builder_csrbank7_clocker_divider0_we $and$ls180.v:6141$1810_Y
- connect \main_sdphy_init_initialize_r \builder_interface7_bank_bus_dat_w [0]
- connect \main_sdphy_init_initialize_re $and$ls180.v:6143$1813_Y
- connect \main_sdphy_init_initialize_we $and$ls180.v:6144$1817_Y
- connect \builder_csrbank7_card_detect_w \main_sdphy_status
- connect \main_sdphy_we \builder_csrbank7_card_detect_we
- connect \builder_csrbank7_clocker_divider1_w \main_sdphy_clocker_storage [8]
- connect \builder_csrbank7_clocker_divider0_w \main_sdphy_clocker_storage [7:0]
- connect \builder_csrbank8_sel $eq$ls180.v:6149$1818_Y
- connect \builder_csrbank8_dfii_control0_r \builder_interface8_bank_bus_dat_w [3:0]
- connect \builder_csrbank8_dfii_control0_re $and$ls180.v:6151$1821_Y
- connect \builder_csrbank8_dfii_control0_we $and$ls180.v:6152$1825_Y
- connect \builder_csrbank8_dfii_pi0_command0_r \builder_interface8_bank_bus_dat_w [5:0]
- connect \builder_csrbank8_dfii_pi0_command0_re $and$ls180.v:6154$1828_Y
- connect \builder_csrbank8_dfii_pi0_command0_we $and$ls180.v:6155$1832_Y
- connect \main_sdram_command_issue_r \builder_interface8_bank_bus_dat_w [0]
- connect \main_sdram_command_issue_re $and$ls180.v:6157$1835_Y
- connect \main_sdram_command_issue_we $and$ls180.v:6158$1839_Y
- connect \builder_csrbank8_dfii_pi0_address1_r \builder_interface8_bank_bus_dat_w [4:0]
- connect \builder_csrbank8_dfii_pi0_address1_re $and$ls180.v:6160$1842_Y
- connect \builder_csrbank8_dfii_pi0_address1_we $and$ls180.v:6161$1846_Y
- connect \builder_csrbank8_dfii_pi0_address0_r \builder_interface8_bank_bus_dat_w
- connect \builder_csrbank8_dfii_pi0_address0_re $and$ls180.v:6163$1849_Y
- connect \builder_csrbank8_dfii_pi0_address0_we $and$ls180.v:6164$1853_Y
- connect \builder_csrbank8_dfii_pi0_baddress0_r \builder_interface8_bank_bus_dat_w [1:0]
- connect \builder_csrbank8_dfii_pi0_baddress0_re $and$ls180.v:6166$1856_Y
- connect \builder_csrbank8_dfii_pi0_baddress0_we $and$ls180.v:6167$1860_Y
- connect \builder_csrbank8_dfii_pi0_wrdata1_r \builder_interface8_bank_bus_dat_w
- connect \builder_csrbank8_dfii_pi0_wrdata1_re $and$ls180.v:6169$1863_Y
- connect \builder_csrbank8_dfii_pi0_wrdata1_we $and$ls180.v:6170$1867_Y
- connect \builder_csrbank8_dfii_pi0_wrdata0_r \builder_interface8_bank_bus_dat_w
- connect \builder_csrbank8_dfii_pi0_wrdata0_re $and$ls180.v:6172$1870_Y
- connect \builder_csrbank8_dfii_pi0_wrdata0_we $and$ls180.v:6173$1874_Y
- connect \builder_csrbank8_dfii_pi0_rddata1_r \builder_interface8_bank_bus_dat_w
- connect \builder_csrbank8_dfii_pi0_rddata1_re $and$ls180.v:6175$1877_Y
- connect \builder_csrbank8_dfii_pi0_rddata1_we $and$ls180.v:6176$1881_Y
- connect \builder_csrbank8_dfii_pi0_rddata0_r \builder_interface8_bank_bus_dat_w
- connect \builder_csrbank8_dfii_pi0_rddata0_re $and$ls180.v:6178$1884_Y
- connect \builder_csrbank8_dfii_pi0_rddata0_we $and$ls180.v:6179$1888_Y
+ connect \builder_csrbank3_period0_re $and$ls180.v:5857$1263_Y
+ connect \builder_csrbank3_period0_we $and$ls180.v:5858$1267_Y
+ connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage
+ connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24]
+ connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16]
+ connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8]
+ connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0]
+ connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24]
+ connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16]
+ connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8]
+ connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0]
+ connect \builder_csrbank4_sel $eq$ls180.v:5868$1268_Y
+ connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0]
+ connect \builder_csrbank4_enable0_re $and$ls180.v:5870$1271_Y
+ connect \builder_csrbank4_enable0_we $and$ls180.v:5871$1275_Y
+ connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w
+ connect \builder_csrbank4_width3_re $and$ls180.v:5873$1278_Y
+ connect \builder_csrbank4_width3_we $and$ls180.v:5874$1282_Y
+ connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w
+ connect \builder_csrbank4_width2_re $and$ls180.v:5876$1285_Y
+ connect \builder_csrbank4_width2_we $and$ls180.v:5877$1289_Y
+ connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w
+ connect \builder_csrbank4_width1_re $and$ls180.v:5879$1292_Y
+ connect \builder_csrbank4_width1_we $and$ls180.v:5880$1296_Y
+ connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w
+ connect \builder_csrbank4_width0_re $and$ls180.v:5882$1299_Y
+ connect \builder_csrbank4_width0_we $and$ls180.v:5883$1303_Y
+ connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w
+ connect \builder_csrbank4_period3_re $and$ls180.v:5885$1306_Y
+ connect \builder_csrbank4_period3_we $and$ls180.v:5886$1310_Y
+ connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w
+ connect \builder_csrbank4_period2_re $and$ls180.v:5888$1313_Y
+ connect \builder_csrbank4_period2_we $and$ls180.v:5889$1317_Y
+ connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w
+ connect \builder_csrbank4_period1_re $and$ls180.v:5891$1320_Y
+ connect \builder_csrbank4_period1_we $and$ls180.v:5892$1324_Y
+ connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w
+ connect \builder_csrbank4_period0_re $and$ls180.v:5894$1327_Y
+ connect \builder_csrbank4_period0_we $and$ls180.v:5895$1331_Y
+ connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage
+ connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24]
+ connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16]
+ connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8]
+ connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0]
+ connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24]
+ connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16]
+ connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8]
+ connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0]
+ connect \builder_csrbank5_sel $eq$ls180.v:5905$1332_Y
+ connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w
+ connect \builder_csrbank5_dma_base7_re $and$ls180.v:5907$1335_Y
+ connect \builder_csrbank5_dma_base7_we $and$ls180.v:5908$1339_Y
+ connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w
+ connect \builder_csrbank5_dma_base6_re $and$ls180.v:5910$1342_Y
+ connect \builder_csrbank5_dma_base6_we $and$ls180.v:5911$1346_Y
+ connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w
+ connect \builder_csrbank5_dma_base5_re $and$ls180.v:5913$1349_Y
+ connect \builder_csrbank5_dma_base5_we $and$ls180.v:5914$1353_Y
+ connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w
+ connect \builder_csrbank5_dma_base4_re $and$ls180.v:5916$1356_Y
+ connect \builder_csrbank5_dma_base4_we $and$ls180.v:5917$1360_Y
+ connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w
+ connect \builder_csrbank5_dma_base3_re $and$ls180.v:5919$1363_Y
+ connect \builder_csrbank5_dma_base3_we $and$ls180.v:5920$1367_Y
+ connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w
+ connect \builder_csrbank5_dma_base2_re $and$ls180.v:5922$1370_Y
+ connect \builder_csrbank5_dma_base2_we $and$ls180.v:5923$1374_Y
+ connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w
+ connect \builder_csrbank5_dma_base1_re $and$ls180.v:5925$1377_Y
+ connect \builder_csrbank5_dma_base1_we $and$ls180.v:5926$1381_Y
+ connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w
+ connect \builder_csrbank5_dma_base0_re $and$ls180.v:5928$1384_Y
+ connect \builder_csrbank5_dma_base0_we $and$ls180.v:5929$1388_Y
+ connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w
+ connect \builder_csrbank5_dma_length3_re $and$ls180.v:5931$1391_Y
+ connect \builder_csrbank5_dma_length3_we $and$ls180.v:5932$1395_Y
+ connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w
+ connect \builder_csrbank5_dma_length2_re $and$ls180.v:5934$1398_Y
+ connect \builder_csrbank5_dma_length2_we $and$ls180.v:5935$1402_Y
+ connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w
+ connect \builder_csrbank5_dma_length1_re $and$ls180.v:5937$1405_Y
+ connect \builder_csrbank5_dma_length1_we $and$ls180.v:5938$1409_Y
+ connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w
+ connect \builder_csrbank5_dma_length0_re $and$ls180.v:5940$1412_Y
+ connect \builder_csrbank5_dma_length0_we $and$ls180.v:5941$1416_Y
+ connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0]
+ connect \builder_csrbank5_dma_enable0_re $and$ls180.v:5943$1419_Y
+ connect \builder_csrbank5_dma_enable0_we $and$ls180.v:5944$1423_Y
+ connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0]
+ connect \builder_csrbank5_dma_done_re $and$ls180.v:5946$1426_Y
+ connect \builder_csrbank5_dma_done_we $and$ls180.v:5947$1430_Y
+ connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0]
+ connect \builder_csrbank5_dma_loop0_re $and$ls180.v:5949$1433_Y
+ connect \builder_csrbank5_dma_loop0_we $and$ls180.v:5950$1437_Y
+ connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56]
+ connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48]
+ connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40]
+ connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32]
+ connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24]
+ connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16]
+ connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8]
+ connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0]
+ connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24]
+ connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16]
+ connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8]
+ connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0]
+ connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage
+ connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status
+ connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we
+ connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage
+ connect \builder_csrbank6_sel $eq$ls180.v:5967$1438_Y
+ connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:5969$1441_Y
+ connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:5970$1445_Y
+ connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:5972$1448_Y
+ connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:5973$1452_Y
+ connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:5975$1455_Y
+ connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:5976$1459_Y
+ connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:5978$1462_Y
+ connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:5979$1466_Y
+ connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_command3_re $and$ls180.v:5981$1469_Y
+ connect \builder_csrbank6_cmd_command3_we $and$ls180.v:5982$1473_Y
+ connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_command2_re $and$ls180.v:5984$1476_Y
+ connect \builder_csrbank6_cmd_command2_we $and$ls180.v:5985$1480_Y
+ connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_command1_re $and$ls180.v:5987$1483_Y
+ connect \builder_csrbank6_cmd_command1_we $and$ls180.v:5988$1487_Y
+ connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_command0_re $and$ls180.v:5990$1490_Y
+ connect \builder_csrbank6_cmd_command0_we $and$ls180.v:5991$1494_Y
+ connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0]
+ connect \main_sdcore_cmd_send_re $and$ls180.v:5993$1497_Y
+ connect \main_sdcore_cmd_send_we $and$ls180.v:5994$1501_Y
+ connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response15_re $and$ls180.v:5996$1504_Y
+ connect \builder_csrbank6_cmd_response15_we $and$ls180.v:5997$1508_Y
+ connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response14_re $and$ls180.v:5999$1511_Y
+ connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6000$1515_Y
+ connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6002$1518_Y
+ connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6003$1522_Y
+ connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6005$1525_Y
+ connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6006$1529_Y
+ connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6008$1532_Y
+ connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6009$1536_Y
+ connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6011$1539_Y
+ connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6012$1543_Y
+ connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6014$1546_Y
+ connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6015$1550_Y
+ connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6017$1553_Y
+ connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6018$1557_Y
+ connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6020$1560_Y
+ connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6021$1564_Y
+ connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6023$1567_Y
+ connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6024$1571_Y
+ connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6026$1574_Y
+ connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6027$1578_Y
+ connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6029$1581_Y
+ connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6030$1585_Y
+ connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6032$1588_Y
+ connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6033$1592_Y
+ connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6035$1595_Y
+ connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6036$1599_Y
+ connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6038$1602_Y
+ connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6039$1606_Y
+ connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6041$1609_Y
+ connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6042$1613_Y
+ connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0]
+ connect \builder_csrbank6_cmd_event_re $and$ls180.v:6044$1616_Y
+ connect \builder_csrbank6_cmd_event_we $and$ls180.v:6045$1620_Y
+ connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0]
+ connect \builder_csrbank6_data_event_re $and$ls180.v:6047$1623_Y
+ connect \builder_csrbank6_data_event_we $and$ls180.v:6048$1627_Y
+ connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0]
+ connect \builder_csrbank6_block_length1_re $and$ls180.v:6050$1630_Y
+ connect \builder_csrbank6_block_length1_we $and$ls180.v:6051$1634_Y
+ connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_block_length0_re $and$ls180.v:6053$1637_Y
+ connect \builder_csrbank6_block_length0_we $and$ls180.v:6054$1641_Y
+ connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_block_count3_re $and$ls180.v:6056$1644_Y
+ connect \builder_csrbank6_block_count3_we $and$ls180.v:6057$1648_Y
+ connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_block_count2_re $and$ls180.v:6059$1651_Y
+ connect \builder_csrbank6_block_count2_we $and$ls180.v:6060$1655_Y
+ connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_block_count1_re $and$ls180.v:6062$1658_Y
+ connect \builder_csrbank6_block_count1_we $and$ls180.v:6063$1662_Y
+ connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w
+ connect \builder_csrbank6_block_count0_re $and$ls180.v:6065$1665_Y
+ connect \builder_csrbank6_block_count0_we $and$ls180.v:6066$1669_Y
+ connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24]
+ connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16]
+ connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8]
+ connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0]
+ connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24]
+ connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16]
+ connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8]
+ connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0]
+ connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120]
+ connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112]
+ connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104]
+ connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96]
+ connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88]
+ connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80]
+ connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72]
+ connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64]
+ connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56]
+ connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48]
+ connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40]
+ connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32]
+ connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24]
+ connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16]
+ connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8]
+ connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0]
+ connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we
+ connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status
+ connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we
+ connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status
+ connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we
+ connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8]
+ connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0]
+ connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24]
+ connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16]
+ connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8]
+ connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0]
+ connect \builder_csrbank7_sel $eq$ls180.v:6102$1670_Y
+ connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_base7_re $and$ls180.v:6104$1673_Y
+ connect \builder_csrbank7_dma_base7_we $and$ls180.v:6105$1677_Y
+ connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_base6_re $and$ls180.v:6107$1680_Y
+ connect \builder_csrbank7_dma_base6_we $and$ls180.v:6108$1684_Y
+ connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_base5_re $and$ls180.v:6110$1687_Y
+ connect \builder_csrbank7_dma_base5_we $and$ls180.v:6111$1691_Y
+ connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_base4_re $and$ls180.v:6113$1694_Y
+ connect \builder_csrbank7_dma_base4_we $and$ls180.v:6114$1698_Y
+ connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_base3_re $and$ls180.v:6116$1701_Y
+ connect \builder_csrbank7_dma_base3_we $and$ls180.v:6117$1705_Y
+ connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_base2_re $and$ls180.v:6119$1708_Y
+ connect \builder_csrbank7_dma_base2_we $and$ls180.v:6120$1712_Y
+ connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_base1_re $and$ls180.v:6122$1715_Y
+ connect \builder_csrbank7_dma_base1_we $and$ls180.v:6123$1719_Y
+ connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_base0_re $and$ls180.v:6125$1722_Y
+ connect \builder_csrbank7_dma_base0_we $and$ls180.v:6126$1726_Y
+ connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_length3_re $and$ls180.v:6128$1729_Y
+ connect \builder_csrbank7_dma_length3_we $and$ls180.v:6129$1733_Y
+ connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_length2_re $and$ls180.v:6131$1736_Y
+ connect \builder_csrbank7_dma_length2_we $and$ls180.v:6132$1740_Y
+ connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_length1_re $and$ls180.v:6134$1743_Y
+ connect \builder_csrbank7_dma_length1_we $and$ls180.v:6135$1747_Y
+ connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_length0_re $and$ls180.v:6137$1750_Y
+ connect \builder_csrbank7_dma_length0_we $and$ls180.v:6138$1754_Y
+ connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0]
+ connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6140$1757_Y
+ connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6141$1761_Y
+ connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0]
+ connect \builder_csrbank7_dma_done_re $and$ls180.v:6143$1764_Y
+ connect \builder_csrbank7_dma_done_we $and$ls180.v:6144$1768_Y
+ connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0]
+ connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6146$1771_Y
+ connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6147$1775_Y
+ connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6149$1778_Y
+ connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6150$1782_Y
+ connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6152$1785_Y
+ connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6153$1789_Y
+ connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6155$1792_Y
+ connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6156$1796_Y
+ connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w
+ connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6158$1799_Y
+ connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6159$1803_Y
+ connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56]
+ connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48]
+ connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40]
+ connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32]
+ connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24]
+ connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16]
+ connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8]
+ connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0]
+ connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24]
+ connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16]
+ connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8]
+ connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0]
+ connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage
+ connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status
+ connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we
+ connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage
+ connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24]
+ connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16]
+ connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8]
+ connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0]
+ connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we
+ connect \builder_csrbank8_sel $eq$ls180.v:6181$1804_Y
+ connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0]
+ connect \builder_csrbank8_card_detect_re $and$ls180.v:6183$1807_Y
+ connect \builder_csrbank8_card_detect_we $and$ls180.v:6184$1811_Y
+ connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0]
+ connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6186$1814_Y
+ connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6187$1818_Y
+ connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w
+ connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6189$1821_Y
+ connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6190$1825_Y
+ connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0]
+ connect \main_sdphy_init_initialize_re $and$ls180.v:6192$1828_Y
+ connect \main_sdphy_init_initialize_we $and$ls180.v:6193$1832_Y
+ connect \builder_csrbank8_card_detect_w \main_sdphy_status
+ connect \main_sdphy_we \builder_csrbank8_card_detect_we
+ connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8]
+ connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0]
+ connect \builder_csrbank9_sel $eq$ls180.v:6198$1833_Y
+ connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0]
+ connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6200$1836_Y
+ connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6201$1840_Y
+ connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0]
+ connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6203$1843_Y
+ connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6204$1847_Y
+ connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0]
+ connect \main_sdram_command_issue_re $and$ls180.v:6206$1850_Y
+ connect \main_sdram_command_issue_we $and$ls180.v:6207$1854_Y
+ connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0]
+ connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6209$1857_Y
+ connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6210$1861_Y
+ connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w
+ connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6212$1864_Y
+ connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6213$1868_Y
+ connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0]
+ connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6215$1871_Y
+ connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6216$1875_Y
+ connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w
+ connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6218$1878_Y
+ connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6219$1882_Y
+ connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w
+ connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6221$1885_Y
+ connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6222$1889_Y
+ connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w
+ connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6224$1892_Y
+ connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6225$1896_Y
+ connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w
+ connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6227$1899_Y
+ connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6228$1903_Y
connect \main_sdram_sel \main_sdram_storage [0]
connect \main_sdram_cke \main_sdram_storage [1]
connect \main_sdram_odt \main_sdram_storage [2]
connect \main_sdram_reset_n \main_sdram_storage [3]
- connect \builder_csrbank8_dfii_control0_w \main_sdram_storage
- connect \builder_csrbank8_dfii_pi0_command0_w \main_sdram_command_storage
- connect \builder_csrbank8_dfii_pi0_address1_w \main_sdram_address_storage [12:8]
- connect \builder_csrbank8_dfii_pi0_address0_w \main_sdram_address_storage [7:0]
- connect \builder_csrbank8_dfii_pi0_baddress0_w \main_sdram_baddress_storage
- connect \builder_csrbank8_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8]
- connect \builder_csrbank8_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0]
- connect \builder_csrbank8_dfii_pi0_rddata1_w \main_sdram_status [15:8]
- connect \builder_csrbank8_dfii_pi0_rddata0_w \main_sdram_status [7:0]
- connect \main_sdram_we \builder_csrbank8_dfii_pi0_rddata0_we
- connect \builder_csrbank9_sel $eq$ls180.v:6194$1889_Y
- connect \builder_csrbank9_control1_r \builder_interface9_bank_bus_dat_w
- connect \builder_csrbank9_control1_re $and$ls180.v:6196$1892_Y
- connect \builder_csrbank9_control1_we $and$ls180.v:6197$1896_Y
- connect \builder_csrbank9_control0_r \builder_interface9_bank_bus_dat_w
- connect \builder_csrbank9_control0_re $and$ls180.v:6199$1899_Y
- connect \builder_csrbank9_control0_we $and$ls180.v:6200$1903_Y
- connect \builder_csrbank9_status_r \builder_interface9_bank_bus_dat_w [0]
- connect \builder_csrbank9_status_re $and$ls180.v:6202$1906_Y
- connect \builder_csrbank9_status_we $and$ls180.v:6203$1910_Y
- connect \builder_csrbank9_mosi0_r \builder_interface9_bank_bus_dat_w
- connect \builder_csrbank9_mosi0_re $and$ls180.v:6205$1913_Y
- connect \builder_csrbank9_mosi0_we $and$ls180.v:6206$1917_Y
- connect \builder_csrbank9_miso_r \builder_interface9_bank_bus_dat_w
- connect \builder_csrbank9_miso_re $and$ls180.v:6208$1920_Y
- connect \builder_csrbank9_miso_we $and$ls180.v:6209$1924_Y
- connect \builder_csrbank9_cs0_r \builder_interface9_bank_bus_dat_w [0]
- connect \builder_csrbank9_cs0_re $and$ls180.v:6211$1927_Y
- connect \builder_csrbank9_cs0_we $and$ls180.v:6212$1931_Y
- connect \builder_csrbank9_loopback0_r \builder_interface9_bank_bus_dat_w [0]
- connect \builder_csrbank9_loopback0_re $and$ls180.v:6214$1934_Y
- connect \builder_csrbank9_loopback0_we $and$ls180.v:6215$1938_Y
- connect \main_spi_master_length1 \main_spi_master_control_storage [15:8]
- connect \builder_csrbank9_control1_w \main_spi_master_control_storage [15:8]
- connect \builder_csrbank9_control0_w \main_spi_master_control_storage [7:0]
- connect \main_spi_master_status_status \main_spi_master_done1
- connect \builder_csrbank9_status_w \main_spi_master_status_status
- connect \main_spi_master_status_we \builder_csrbank9_status_we
- connect \builder_csrbank9_mosi0_w \main_spi_master_mosi_storage
- connect \builder_csrbank9_miso_w \main_spi_master_miso_status
- connect \main_spi_master_miso_we \builder_csrbank9_miso_we
- connect \main_spi_master_sel \main_spi_master_cs_storage
- connect \builder_csrbank9_cs0_w \main_spi_master_cs_storage
- connect \builder_csrbank9_loopback0_w \main_spi_master_loopback_storage
- connect \builder_csrbank10_sel $eq$ls180.v:6234$1940_Y
+ connect \builder_csrbank9_dfii_control0_w \main_sdram_storage
+ connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage
+ connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8]
+ connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0]
+ connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage
+ connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8]
+ connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0]
+ connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8]
+ connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0]
+ connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we
+ connect \builder_csrbank10_sel $eq$ls180.v:6243$1904_Y
connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w
- connect \builder_csrbank10_control1_re $and$ls180.v:6236$1943_Y
- connect \builder_csrbank10_control1_we $and$ls180.v:6237$1947_Y
+ connect \builder_csrbank10_control1_re $and$ls180.v:6245$1907_Y
+ connect \builder_csrbank10_control1_we $and$ls180.v:6246$1911_Y
connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w
- connect \builder_csrbank10_control0_re $and$ls180.v:6239$1950_Y
- connect \builder_csrbank10_control0_we $and$ls180.v:6240$1954_Y
+ connect \builder_csrbank10_control0_re $and$ls180.v:6248$1914_Y
+ connect \builder_csrbank10_control0_we $and$ls180.v:6249$1918_Y
connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0]
- connect \builder_csrbank10_status_re $and$ls180.v:6242$1957_Y
- connect \builder_csrbank10_status_we $and$ls180.v:6243$1961_Y
+ connect \builder_csrbank10_status_re $and$ls180.v:6251$1921_Y
+ connect \builder_csrbank10_status_we $and$ls180.v:6252$1925_Y
connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w
- connect \builder_csrbank10_mosi0_re $and$ls180.v:6245$1964_Y
- connect \builder_csrbank10_mosi0_we $and$ls180.v:6246$1968_Y
+ connect \builder_csrbank10_mosi0_re $and$ls180.v:6254$1928_Y
+ connect \builder_csrbank10_mosi0_we $and$ls180.v:6255$1932_Y
connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w
- connect \builder_csrbank10_miso_re $and$ls180.v:6248$1971_Y
- connect \builder_csrbank10_miso_we $and$ls180.v:6249$1975_Y
+ connect \builder_csrbank10_miso_re $and$ls180.v:6257$1935_Y
+ connect \builder_csrbank10_miso_we $and$ls180.v:6258$1939_Y
connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0]
- connect \builder_csrbank10_cs0_re $and$ls180.v:6251$1978_Y
- connect \builder_csrbank10_cs0_we $and$ls180.v:6252$1982_Y
+ connect \builder_csrbank10_cs0_re $and$ls180.v:6260$1942_Y
+ connect \builder_csrbank10_cs0_we $and$ls180.v:6261$1946_Y
connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0]
- connect \builder_csrbank10_loopback0_re $and$ls180.v:6254$1985_Y
- connect \builder_csrbank10_loopback0_we $and$ls180.v:6255$1989_Y
- connect \builder_csrbank10_clk_divider1_r \builder_interface10_bank_bus_dat_w
- connect \builder_csrbank10_clk_divider1_re $and$ls180.v:6257$1992_Y
- connect \builder_csrbank10_clk_divider1_we $and$ls180.v:6258$1996_Y
- connect \builder_csrbank10_clk_divider0_r \builder_interface10_bank_bus_dat_w
- connect \builder_csrbank10_clk_divider0_re $and$ls180.v:6260$1999_Y
- connect \builder_csrbank10_clk_divider0_we $and$ls180.v:6261$2003_Y
+ connect \builder_csrbank10_loopback0_re $and$ls180.v:6263$1949_Y
+ connect \builder_csrbank10_loopback0_we $and$ls180.v:6264$1953_Y
+ connect \main_spi_master_length1 \main_spi_master_control_storage [15:8]
+ connect \builder_csrbank10_control1_w \main_spi_master_control_storage [15:8]
+ connect \builder_csrbank10_control0_w \main_spi_master_control_storage [7:0]
+ connect \main_spi_master_status_status \main_spi_master_done1
+ connect \builder_csrbank10_status_w \main_spi_master_status_status
+ connect \main_spi_master_status_we \builder_csrbank10_status_we
+ connect \builder_csrbank10_mosi0_w \main_spi_master_mosi_storage
+ connect \builder_csrbank10_miso_w \main_spi_master_miso_status
+ connect \main_spi_master_miso_we \builder_csrbank10_miso_we
+ connect \main_spi_master_sel \main_spi_master_cs_storage
+ connect \builder_csrbank10_cs0_w \main_spi_master_cs_storage
+ connect \builder_csrbank10_loopback0_w \main_spi_master_loopback_storage
+ connect \builder_csrbank11_sel $eq$ls180.v:6283$1955_Y
+ connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w
+ connect \builder_csrbank11_control1_re $and$ls180.v:6285$1958_Y
+ connect \builder_csrbank11_control1_we $and$ls180.v:6286$1962_Y
+ connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w
+ connect \builder_csrbank11_control0_re $and$ls180.v:6288$1965_Y
+ connect \builder_csrbank11_control0_we $and$ls180.v:6289$1969_Y
+ connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0]
+ connect \builder_csrbank11_status_re $and$ls180.v:6291$1972_Y
+ connect \builder_csrbank11_status_we $and$ls180.v:6292$1976_Y
+ connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w
+ connect \builder_csrbank11_mosi0_re $and$ls180.v:6294$1979_Y
+ connect \builder_csrbank11_mosi0_we $and$ls180.v:6295$1983_Y
+ connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w
+ connect \builder_csrbank11_miso_re $and$ls180.v:6297$1986_Y
+ connect \builder_csrbank11_miso_we $and$ls180.v:6298$1990_Y
+ connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0]
+ connect \builder_csrbank11_cs0_re $and$ls180.v:6300$1993_Y
+ connect \builder_csrbank11_cs0_we $and$ls180.v:6301$1997_Y
+ connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0]
+ connect \builder_csrbank11_loopback0_re $and$ls180.v:6303$2000_Y
+ connect \builder_csrbank11_loopback0_we $and$ls180.v:6304$2004_Y
+ connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w
+ connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6306$2007_Y
+ connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6307$2011_Y
+ connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w
+ connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6309$2014_Y
+ connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6310$2018_Y
connect \libresocsim_length1 \libresocsim_control_storage [15:8]
- connect \builder_csrbank10_control1_w \libresocsim_control_storage [15:8]
- connect \builder_csrbank10_control0_w \libresocsim_control_storage [7:0]
+ connect \builder_csrbank11_control1_w \libresocsim_control_storage [15:8]
+ connect \builder_csrbank11_control0_w \libresocsim_control_storage [7:0]
connect \libresocsim_status_status \libresocsim_done1
- connect \builder_csrbank10_status_w \libresocsim_status_status
- connect \libresocsim_status_we \builder_csrbank10_status_we
- connect \builder_csrbank10_mosi0_w \libresocsim_mosi_storage
- connect \builder_csrbank10_miso_w \libresocsim_miso_status
- connect \libresocsim_miso_we \builder_csrbank10_miso_we
+ connect \builder_csrbank11_status_w \libresocsim_status_status
+ connect \libresocsim_status_we \builder_csrbank11_status_we
+ connect \builder_csrbank11_mosi0_w \libresocsim_mosi_storage
+ connect \builder_csrbank11_miso_w \libresocsim_miso_status
+ connect \libresocsim_miso_we \builder_csrbank11_miso_we
connect \libresocsim_sel \libresocsim_cs_storage
- connect \builder_csrbank10_cs0_w \libresocsim_cs_storage
- connect \builder_csrbank10_loopback0_w \libresocsim_loopback_storage
- connect \builder_csrbank10_clk_divider1_w \libresocsim_storage [15:8]
- connect \builder_csrbank10_clk_divider0_w \libresocsim_storage [7:0]
- connect \builder_csrbank11_sel $eq$ls180.v:6282$2005_Y
- connect \builder_csrbank11_load3_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_load3_re $and$ls180.v:6284$2008_Y
- connect \builder_csrbank11_load3_we $and$ls180.v:6285$2012_Y
- connect \builder_csrbank11_load2_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_load2_re $and$ls180.v:6287$2015_Y
- connect \builder_csrbank11_load2_we $and$ls180.v:6288$2019_Y
- connect \builder_csrbank11_load1_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_load1_re $and$ls180.v:6290$2022_Y
- connect \builder_csrbank11_load1_we $and$ls180.v:6291$2026_Y
- connect \builder_csrbank11_load0_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_load0_re $and$ls180.v:6293$2029_Y
- connect \builder_csrbank11_load0_we $and$ls180.v:6294$2033_Y
- connect \builder_csrbank11_reload3_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_reload3_re $and$ls180.v:6296$2036_Y
- connect \builder_csrbank11_reload3_we $and$ls180.v:6297$2040_Y
- connect \builder_csrbank11_reload2_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_reload2_re $and$ls180.v:6299$2043_Y
- connect \builder_csrbank11_reload2_we $and$ls180.v:6300$2047_Y
- connect \builder_csrbank11_reload1_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_reload1_re $and$ls180.v:6302$2050_Y
- connect \builder_csrbank11_reload1_we $and$ls180.v:6303$2054_Y
- connect \builder_csrbank11_reload0_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_reload0_re $and$ls180.v:6305$2057_Y
- connect \builder_csrbank11_reload0_we $and$ls180.v:6306$2061_Y
- connect \builder_csrbank11_en0_r \builder_interface11_bank_bus_dat_w [0]
- connect \builder_csrbank11_en0_re $and$ls180.v:6308$2064_Y
- connect \builder_csrbank11_en0_we $and$ls180.v:6309$2068_Y
- connect \builder_csrbank11_update_value0_r \builder_interface11_bank_bus_dat_w [0]
- connect \builder_csrbank11_update_value0_re $and$ls180.v:6311$2071_Y
- connect \builder_csrbank11_update_value0_we $and$ls180.v:6312$2075_Y
- connect \builder_csrbank11_value3_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_value3_re $and$ls180.v:6314$2078_Y
- connect \builder_csrbank11_value3_we $and$ls180.v:6315$2082_Y
- connect \builder_csrbank11_value2_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_value2_re $and$ls180.v:6317$2085_Y
- connect \builder_csrbank11_value2_we $and$ls180.v:6318$2089_Y
- connect \builder_csrbank11_value1_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_value1_re $and$ls180.v:6320$2092_Y
- connect \builder_csrbank11_value1_we $and$ls180.v:6321$2096_Y
- connect \builder_csrbank11_value0_r \builder_interface11_bank_bus_dat_w
- connect \builder_csrbank11_value0_re $and$ls180.v:6323$2099_Y
- connect \builder_csrbank11_value0_we $and$ls180.v:6324$2103_Y
- connect \main_libresocsim_eventmanager_status_r \builder_interface11_bank_bus_dat_w [0]
- connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6326$2106_Y
- connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6327$2110_Y
- connect \main_libresocsim_eventmanager_pending_r \builder_interface11_bank_bus_dat_w [0]
- connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6329$2113_Y
- connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6330$2117_Y
- connect \builder_csrbank11_ev_enable0_r \builder_interface11_bank_bus_dat_w [0]
- connect \builder_csrbank11_ev_enable0_re $and$ls180.v:6332$2120_Y
- connect \builder_csrbank11_ev_enable0_we $and$ls180.v:6333$2124_Y
- connect \builder_csrbank11_load3_w \main_libresocsim_load_storage [31:24]
- connect \builder_csrbank11_load2_w \main_libresocsim_load_storage [23:16]
- connect \builder_csrbank11_load1_w \main_libresocsim_load_storage [15:8]
- connect \builder_csrbank11_load0_w \main_libresocsim_load_storage [7:0]
- connect \builder_csrbank11_reload3_w \main_libresocsim_reload_storage [31:24]
- connect \builder_csrbank11_reload2_w \main_libresocsim_reload_storage [23:16]
- connect \builder_csrbank11_reload1_w \main_libresocsim_reload_storage [15:8]
- connect \builder_csrbank11_reload0_w \main_libresocsim_reload_storage [7:0]
- connect \builder_csrbank11_en0_w \main_libresocsim_en_storage
- connect \builder_csrbank11_update_value0_w \main_libresocsim_update_value_storage
- connect \builder_csrbank11_value3_w \main_libresocsim_value_status [31:24]
- connect \builder_csrbank11_value2_w \main_libresocsim_value_status [23:16]
- connect \builder_csrbank11_value1_w \main_libresocsim_value_status [15:8]
- connect \builder_csrbank11_value0_w \main_libresocsim_value_status [7:0]
- connect \main_libresocsim_value_we \builder_csrbank11_value0_we
- connect \builder_csrbank11_ev_enable0_w \main_libresocsim_eventmanager_storage
- connect \builder_csrbank12_sel $eq$ls180.v:6350$2125_Y
- connect \main_uart_rxtx_r \builder_interface12_bank_bus_dat_w
- connect \main_uart_rxtx_re $and$ls180.v:6352$2128_Y
- connect \main_uart_rxtx_we $and$ls180.v:6353$2132_Y
- connect \builder_csrbank12_txfull_r \builder_interface12_bank_bus_dat_w [0]
- connect \builder_csrbank12_txfull_re $and$ls180.v:6355$2135_Y
- connect \builder_csrbank12_txfull_we $and$ls180.v:6356$2139_Y
- connect \builder_csrbank12_rxempty_r \builder_interface12_bank_bus_dat_w [0]
- connect \builder_csrbank12_rxempty_re $and$ls180.v:6358$2142_Y
- connect \builder_csrbank12_rxempty_we $and$ls180.v:6359$2146_Y
- connect \main_uart_eventmanager_status_r \builder_interface12_bank_bus_dat_w [1:0]
- connect \main_uart_eventmanager_status_re $and$ls180.v:6361$2149_Y
- connect \main_uart_eventmanager_status_we $and$ls180.v:6362$2153_Y
- connect \main_uart_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [1:0]
- connect \main_uart_eventmanager_pending_re $and$ls180.v:6364$2156_Y
- connect \main_uart_eventmanager_pending_we $and$ls180.v:6365$2160_Y
- connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [1:0]
- connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6367$2163_Y
- connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6368$2167_Y
- connect \builder_csrbank12_txempty_r \builder_interface12_bank_bus_dat_w [0]
- connect \builder_csrbank12_txempty_re $and$ls180.v:6370$2170_Y
- connect \builder_csrbank12_txempty_we $and$ls180.v:6371$2174_Y
- connect \builder_csrbank12_rxfull_r \builder_interface12_bank_bus_dat_w [0]
- connect \builder_csrbank12_rxfull_re $and$ls180.v:6373$2177_Y
- connect \builder_csrbank12_rxfull_we $and$ls180.v:6374$2181_Y
- connect \builder_csrbank12_txfull_w \main_uart_txfull_status
- connect \main_uart_txfull_we \builder_csrbank12_txfull_we
- connect \builder_csrbank12_rxempty_w \main_uart_rxempty_status
- connect \main_uart_rxempty_we \builder_csrbank12_rxempty_we
- connect \builder_csrbank12_ev_enable0_w \main_uart_eventmanager_storage
- connect \builder_csrbank12_txempty_w \main_uart_txempty_status
- connect \main_uart_txempty_we \builder_csrbank12_txempty_we
- connect \builder_csrbank12_rxfull_w \main_uart_rxfull_status
- connect \main_uart_rxfull_we \builder_csrbank12_rxfull_we
- connect \builder_csrbank13_sel $eq$ls180.v:6384$2182_Y
- connect \builder_csrbank13_tuning_word3_r \builder_interface13_bank_bus_dat_w
- connect \builder_csrbank13_tuning_word3_re $and$ls180.v:6386$2185_Y
- connect \builder_csrbank13_tuning_word3_we $and$ls180.v:6387$2189_Y
- connect \builder_csrbank13_tuning_word2_r \builder_interface13_bank_bus_dat_w
- connect \builder_csrbank13_tuning_word2_re $and$ls180.v:6389$2192_Y
- connect \builder_csrbank13_tuning_word2_we $and$ls180.v:6390$2196_Y
- connect \builder_csrbank13_tuning_word1_r \builder_interface13_bank_bus_dat_w
- connect \builder_csrbank13_tuning_word1_re $and$ls180.v:6392$2199_Y
- connect \builder_csrbank13_tuning_word1_we $and$ls180.v:6393$2203_Y
- connect \builder_csrbank13_tuning_word0_r \builder_interface13_bank_bus_dat_w
- connect \builder_csrbank13_tuning_word0_re $and$ls180.v:6395$2206_Y
- connect \builder_csrbank13_tuning_word0_we $and$ls180.v:6396$2210_Y
- connect \builder_csrbank13_tuning_word3_w \main_storage [31:24]
- connect \builder_csrbank13_tuning_word2_w \main_storage [23:16]
- connect \builder_csrbank13_tuning_word1_w \main_storage [15:8]
- connect \builder_csrbank13_tuning_word0_w \main_storage [7:0]
+ connect \builder_csrbank11_cs0_w \libresocsim_cs_storage
+ connect \builder_csrbank11_loopback0_w \libresocsim_loopback_storage
+ connect \builder_csrbank11_clk_divider1_w \libresocsim_storage [15:8]
+ connect \builder_csrbank11_clk_divider0_w \libresocsim_storage [7:0]
+ connect \builder_csrbank12_sel $eq$ls180.v:6331$2020_Y
+ connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w
+ connect \builder_csrbank12_load3_re $and$ls180.v:6333$2023_Y
+ connect \builder_csrbank12_load3_we $and$ls180.v:6334$2027_Y
+ connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w
+ connect \builder_csrbank12_load2_re $and$ls180.v:6336$2030_Y
+ connect \builder_csrbank12_load2_we $and$ls180.v:6337$2034_Y
+ connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w
+ connect \builder_csrbank12_load1_re $and$ls180.v:6339$2037_Y
+ connect \builder_csrbank12_load1_we $and$ls180.v:6340$2041_Y
+ connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w
+ connect \builder_csrbank12_load0_re $and$ls180.v:6342$2044_Y
+ connect \builder_csrbank12_load0_we $and$ls180.v:6343$2048_Y
+ connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w
+ connect \builder_csrbank12_reload3_re $and$ls180.v:6345$2051_Y
+ connect \builder_csrbank12_reload3_we $and$ls180.v:6346$2055_Y
+ connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w
+ connect \builder_csrbank12_reload2_re $and$ls180.v:6348$2058_Y
+ connect \builder_csrbank12_reload2_we $and$ls180.v:6349$2062_Y
+ connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w
+ connect \builder_csrbank12_reload1_re $and$ls180.v:6351$2065_Y
+ connect \builder_csrbank12_reload1_we $and$ls180.v:6352$2069_Y
+ connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w
+ connect \builder_csrbank12_reload0_re $and$ls180.v:6354$2072_Y
+ connect \builder_csrbank12_reload0_we $and$ls180.v:6355$2076_Y
+ connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0]
+ connect \builder_csrbank12_en0_re $and$ls180.v:6357$2079_Y
+ connect \builder_csrbank12_en0_we $and$ls180.v:6358$2083_Y
+ connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0]
+ connect \builder_csrbank12_update_value0_re $and$ls180.v:6360$2086_Y
+ connect \builder_csrbank12_update_value0_we $and$ls180.v:6361$2090_Y
+ connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w
+ connect \builder_csrbank12_value3_re $and$ls180.v:6363$2093_Y
+ connect \builder_csrbank12_value3_we $and$ls180.v:6364$2097_Y
+ connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w
+ connect \builder_csrbank12_value2_re $and$ls180.v:6366$2100_Y
+ connect \builder_csrbank12_value2_we $and$ls180.v:6367$2104_Y
+ connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w
+ connect \builder_csrbank12_value1_re $and$ls180.v:6369$2107_Y
+ connect \builder_csrbank12_value1_we $and$ls180.v:6370$2111_Y
+ connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w
+ connect \builder_csrbank12_value0_re $and$ls180.v:6372$2114_Y
+ connect \builder_csrbank12_value0_we $and$ls180.v:6373$2118_Y
+ connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0]
+ connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6375$2121_Y
+ connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6376$2125_Y
+ connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0]
+ connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6378$2128_Y
+ connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6379$2132_Y
+ connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0]
+ connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6381$2135_Y
+ connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6382$2139_Y
+ connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24]
+ connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16]
+ connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8]
+ connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0]
+ connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24]
+ connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16]
+ connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8]
+ connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0]
+ connect \builder_csrbank12_en0_w \main_libresocsim_en_storage
+ connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage
+ connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24]
+ connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16]
+ connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8]
+ connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0]
+ connect \main_libresocsim_value_we \builder_csrbank12_value0_we
+ connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage
+ connect \builder_csrbank13_sel $eq$ls180.v:6399$2140_Y
+ connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w
+ connect \main_uart_rxtx_re $and$ls180.v:6401$2143_Y
+ connect \main_uart_rxtx_we $and$ls180.v:6402$2147_Y
+ connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0]
+ connect \builder_csrbank13_txfull_re $and$ls180.v:6404$2150_Y
+ connect \builder_csrbank13_txfull_we $and$ls180.v:6405$2154_Y
+ connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0]
+ connect \builder_csrbank13_rxempty_re $and$ls180.v:6407$2157_Y
+ connect \builder_csrbank13_rxempty_we $and$ls180.v:6408$2161_Y
+ connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0]
+ connect \main_uart_eventmanager_status_re $and$ls180.v:6410$2164_Y
+ connect \main_uart_eventmanager_status_we $and$ls180.v:6411$2168_Y
+ connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0]
+ connect \main_uart_eventmanager_pending_re $and$ls180.v:6413$2171_Y
+ connect \main_uart_eventmanager_pending_we $and$ls180.v:6414$2175_Y
+ connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0]
+ connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6416$2178_Y
+ connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6417$2182_Y
+ connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0]
+ connect \builder_csrbank13_txempty_re $and$ls180.v:6419$2185_Y
+ connect \builder_csrbank13_txempty_we $and$ls180.v:6420$2189_Y
+ connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0]
+ connect \builder_csrbank13_rxfull_re $and$ls180.v:6422$2192_Y
+ connect \builder_csrbank13_rxfull_we $and$ls180.v:6423$2196_Y
+ connect \builder_csrbank13_txfull_w \main_uart_txfull_status
+ connect \main_uart_txfull_we \builder_csrbank13_txfull_we
+ connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status
+ connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we
+ connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage
+ connect \builder_csrbank13_txempty_w \main_uart_txempty_status
+ connect \main_uart_txempty_we \builder_csrbank13_txempty_we
+ connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status
+ connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we
+ connect \builder_csrbank14_sel $eq$ls180.v:6433$2197_Y
+ connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w
+ connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6435$2200_Y
+ connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6436$2204_Y
+ connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w
+ connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6438$2207_Y
+ connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6439$2211_Y
+ connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w
+ connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6441$2214_Y
+ connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6442$2218_Y
+ connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w
+ connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6444$2221_Y
+ connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6445$2225_Y
+ connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24]
+ connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16]
+ connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8]
+ connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0]
connect \builder_csr_interconnect_adr \builder_libresocsim_adr
connect \builder_csr_interconnect_we \builder_libresocsim_we
connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w
connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr
connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr
connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr
+ connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr
connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we
connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we
connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we
connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we
connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we
connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we
+ connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we
connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w
connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w
connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w
connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w
connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w
connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w
- connect \builder_csr_interconnect_dat_r $or$ls180.v:6447$2223_Y
+ connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w
+ connect \builder_csr_interconnect_dat_r $or$ls180.v:6499$2239_Y
connect \sdrio_clk \sys_clk_1
connect \sdrio_clk_1 \sys_clk_1
connect \sdrio_clk_2 \sys_clk_1
connect \sdrio_clk_53 \sys_clk_1
connect \sdrio_clk_54 \sys_clk_1
connect \sdrio_clk_55 \sys_clk_1
- connect \main_rx \builder_multiregimpl0_regs1
+ connect \main_uart_phy_rx \builder_multiregimpl0_regs1
connect \main_pwm0_enable \main_pwm0_enable_storage
connect \main_pwm0_width \main_pwm0_width_storage
connect \main_pwm0_period \main_pwm0_period_storage
connect \sdrio_clk_66 \sys_clk_1
connect \sdrio_clk_67 \sys_clk_1
connect \sdrio_clk_68 \sys_clk_1
- connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:9989$2695_DATA
+ connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10052$2705_DATA
connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat
- connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10007$2702_DATA
+ connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10070$2712_DATA
connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1
- connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10021$2709_DATA
+ connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10084$2719_DATA
connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2
- connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10035$2716_DATA
+ connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10098$2726_DATA
connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3
- connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10049$2723_DATA
+ connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10112$2733_DATA
connect \main_uart_tx_fifo_wrport_dat_r \memdat_4
connect \main_uart_tx_fifo_rdport_dat_r \memdat_5
connect \main_uart_rx_fifo_wrport_dat_r \memdat_6
connect \main_uart_rx_fifo_rdport_dat_r \memdat_7
connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8
- connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10097$2744_DATA
+ connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10160$2754_DATA
connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9
- connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10111$2751_DATA
+ connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10174$2761_DATA
end
-attribute \src "libresoc.v:44585.1-44669.10"
+attribute \src "libresoc.v:44776.1-44787.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in.ppick"
+attribute \nmigen.hierarchy "test_issuer.pll"
+attribute \generator "nMigen"
+module \pll
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:80"
+ wire input 1 \clk_24_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:81"
+ wire output 4 \clk_pll_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:82"
+ wire input 2 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:527"
+ wire output 3 \rst$1
+ connect \rst$1 \rst
+ connect \clk_pll_o \clk_24_i
+end
+attribute \src "libresoc.v:44791.1-44875.10"
+attribute \cells_not_processed 1
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick"
attribute \generator "nMigen"
module \ppick
- attribute \src "libresoc.v:44642.17-44642.91"
- wire $not$libresoc.v:44642$1361_Y
- attribute \src "libresoc.v:44644.18-44644.93"
- wire $not$libresoc.v:44644$1363_Y
- attribute \src "libresoc.v:44646.18-44646.93"
- wire $not$libresoc.v:44646$1365_Y
- attribute \src "libresoc.v:44647.17-44647.138"
- wire width 8 $not$libresoc.v:44647$1366_Y
- attribute \src "libresoc.v:44649.18-44649.93"
- wire $not$libresoc.v:44649$1368_Y
- attribute \src "libresoc.v:44651.18-44651.93"
- wire $not$libresoc.v:44651$1370_Y
- attribute \src "libresoc.v:44653.18-44653.93"
- wire $not$libresoc.v:44653$1372_Y
- attribute \src "libresoc.v:44656.17-44656.91"
- wire $not$libresoc.v:44656$1375_Y
- attribute \src "libresoc.v:44643.18-44643.116"
- wire $reduce_or$libresoc.v:44643$1362_Y
- attribute \src "libresoc.v:44645.18-44645.122"
- wire $reduce_or$libresoc.v:44645$1364_Y
- attribute \src "libresoc.v:44648.18-44648.128"
- wire $reduce_or$libresoc.v:44648$1367_Y
- attribute \src "libresoc.v:44650.18-44650.134"
- wire $reduce_or$libresoc.v:44650$1369_Y
- attribute \src "libresoc.v:44652.18-44652.140"
- wire $reduce_or$libresoc.v:44652$1371_Y
- attribute \src "libresoc.v:44654.18-44654.90"
- wire $reduce_or$libresoc.v:44654$1373_Y
- attribute \src "libresoc.v:44655.17-44655.103"
- wire $reduce_or$libresoc.v:44655$1374_Y
- attribute \src "libresoc.v:44657.17-44657.109"
- wire $reduce_or$libresoc.v:44657$1376_Y
+ attribute \src "libresoc.v:44848.17-44848.91"
+ wire $not$libresoc.v:44848$1401_Y
+ attribute \src "libresoc.v:44850.18-44850.93"
+ wire $not$libresoc.v:44850$1403_Y
+ attribute \src "libresoc.v:44852.18-44852.93"
+ wire $not$libresoc.v:44852$1405_Y
+ attribute \src "libresoc.v:44853.17-44853.138"
+ wire width 8 $not$libresoc.v:44853$1406_Y
+ attribute \src "libresoc.v:44855.18-44855.93"
+ wire $not$libresoc.v:44855$1408_Y
+ attribute \src "libresoc.v:44857.18-44857.93"
+ wire $not$libresoc.v:44857$1410_Y
+ attribute \src "libresoc.v:44859.18-44859.93"
+ wire $not$libresoc.v:44859$1412_Y
+ attribute \src "libresoc.v:44862.17-44862.91"
+ wire $not$libresoc.v:44862$1415_Y
+ attribute \src "libresoc.v:44849.18-44849.116"
+ wire $reduce_or$libresoc.v:44849$1402_Y
+ attribute \src "libresoc.v:44851.18-44851.122"
+ wire $reduce_or$libresoc.v:44851$1404_Y
+ attribute \src "libresoc.v:44854.18-44854.128"
+ wire $reduce_or$libresoc.v:44854$1407_Y
+ attribute \src "libresoc.v:44856.18-44856.134"
+ wire $reduce_or$libresoc.v:44856$1409_Y
+ attribute \src "libresoc.v:44858.18-44858.140"
+ wire $reduce_or$libresoc.v:44858$1411_Y
+ attribute \src "libresoc.v:44860.18-44860.90"
+ wire $reduce_or$libresoc.v:44860$1413_Y
+ attribute \src "libresoc.v:44861.17-44861.103"
+ wire $reduce_or$libresoc.v:44861$1414_Y
+ attribute \src "libresoc.v:44863.17-44863.109"
+ wire $reduce_or$libresoc.v:44863$1416_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53"
wire width 8 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \t7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44642$1361
+ cell $not $not$libresoc.v:44848$1401
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:44642$1361_Y
+ connect \Y $not$libresoc.v:44848$1401_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44644$1363
+ cell $not $not$libresoc.v:44850$1403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:44644$1363_Y
+ connect \Y $not$libresoc.v:44850$1403_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44646$1365
+ cell $not $not$libresoc.v:44852$1405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:44646$1365_Y
+ connect \Y $not$libresoc.v:44852$1405_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53"
- cell $not $not$libresoc.v:44647$1366
+ cell $not $not$libresoc.v:44853$1406
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] }
- connect \Y $not$libresoc.v:44647$1366_Y
+ connect \Y $not$libresoc.v:44853$1406_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44649$1368
+ cell $not $not$libresoc.v:44855$1408
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:44649$1368_Y
+ connect \Y $not$libresoc.v:44855$1408_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44651$1370
+ cell $not $not$libresoc.v:44857$1410
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:44651$1370_Y
+ connect \Y $not$libresoc.v:44857$1410_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44653$1372
+ cell $not $not$libresoc.v:44859$1412
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:44653$1372_Y
+ connect \Y $not$libresoc.v:44859$1412_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44656$1375
+ cell $not $not$libresoc.v:44862$1415
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:44656$1375_Y
+ connect \Y $not$libresoc.v:44862$1415_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44643$1362
+ cell $reduce_or $reduce_or$libresoc.v:44849$1402
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [5] \i [6] \i [7] \ni [3] }
- connect \Y $reduce_or$libresoc.v:44643$1362_Y
+ connect \Y $reduce_or$libresoc.v:44849$1402_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44645$1364
+ cell $reduce_or $reduce_or$libresoc.v:44851$1404
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] }
- connect \Y $reduce_or$libresoc.v:44645$1364_Y
+ connect \Y $reduce_or$libresoc.v:44851$1404_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44648$1367
+ cell $reduce_or $reduce_or$libresoc.v:44854$1407
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] }
- connect \Y $reduce_or$libresoc.v:44648$1367_Y
+ connect \Y $reduce_or$libresoc.v:44854$1407_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44650$1369
+ cell $reduce_or $reduce_or$libresoc.v:44856$1409
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] }
- connect \Y $reduce_or$libresoc.v:44650$1369_Y
+ connect \Y $reduce_or$libresoc.v:44856$1409_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44652$1371
+ cell $reduce_or $reduce_or$libresoc.v:44858$1411
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] }
- connect \Y $reduce_or$libresoc.v:44652$1371_Y
+ connect \Y $reduce_or$libresoc.v:44858$1411_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69"
- cell $reduce_or $reduce_or$libresoc.v:44654$1373
+ cell $reduce_or $reduce_or$libresoc.v:44860$1413
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:44654$1373_Y
+ connect \Y $reduce_or$libresoc.v:44860$1413_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44655$1374
+ cell $reduce_or $reduce_or$libresoc.v:44861$1414
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [7] \ni [1] }
- connect \Y $reduce_or$libresoc.v:44655$1374_Y
+ connect \Y $reduce_or$libresoc.v:44861$1414_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44657$1376
+ cell $reduce_or $reduce_or$libresoc.v:44863$1416
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [6] \i [7] \ni [2] }
- connect \Y $reduce_or$libresoc.v:44657$1376_Y
- end
- connect \$7 $not$libresoc.v:44642$1361_Y
- connect \$12 $reduce_or$libresoc.v:44643$1362_Y
- connect \$11 $not$libresoc.v:44644$1363_Y
- connect \$16 $reduce_or$libresoc.v:44645$1364_Y
- connect \$15 $not$libresoc.v:44646$1365_Y
- connect \$1 $not$libresoc.v:44647$1366_Y
- connect \$20 $reduce_or$libresoc.v:44648$1367_Y
- connect \$19 $not$libresoc.v:44649$1368_Y
- connect \$24 $reduce_or$libresoc.v:44650$1369_Y
- connect \$23 $not$libresoc.v:44651$1370_Y
- connect \$28 $reduce_or$libresoc.v:44652$1371_Y
- connect \$27 $not$libresoc.v:44653$1372_Y
- connect \$31 $reduce_or$libresoc.v:44654$1373_Y
- connect \$4 $reduce_or$libresoc.v:44655$1374_Y
- connect \$3 $not$libresoc.v:44656$1375_Y
- connect \$8 $reduce_or$libresoc.v:44657$1376_Y
+ connect \Y $reduce_or$libresoc.v:44863$1416_Y
+ end
+ connect \$7 $not$libresoc.v:44848$1401_Y
+ connect \$12 $reduce_or$libresoc.v:44849$1402_Y
+ connect \$11 $not$libresoc.v:44850$1403_Y
+ connect \$16 $reduce_or$libresoc.v:44851$1404_Y
+ connect \$15 $not$libresoc.v:44852$1405_Y
+ connect \$1 $not$libresoc.v:44853$1406_Y
+ connect \$20 $reduce_or$libresoc.v:44854$1407_Y
+ connect \$19 $not$libresoc.v:44855$1408_Y
+ connect \$24 $reduce_or$libresoc.v:44856$1409_Y
+ connect \$23 $not$libresoc.v:44857$1410_Y
+ connect \$28 $reduce_or$libresoc.v:44858$1411_Y
+ connect \$27 $not$libresoc.v:44859$1412_Y
+ connect \$31 $reduce_or$libresoc.v:44860$1413_Y
+ connect \$4 $reduce_or$libresoc.v:44861$1414_Y
+ connect \$3 $not$libresoc.v:44862$1415_Y
+ connect \$8 $reduce_or$libresoc.v:44863$1416_Y
connect \en_o \$31
connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 }
connect \t7 \$27
connect \t0 \i [7]
connect \ni \$1
end
-attribute \src "libresoc.v:44673.1-44757.10"
+attribute \src "libresoc.v:44879.1-44963.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out.ppick"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick"
attribute \generator "nMigen"
module \ppick$1
- attribute \src "libresoc.v:44730.17-44730.91"
- wire $not$libresoc.v:44730$1377_Y
- attribute \src "libresoc.v:44732.18-44732.93"
- wire $not$libresoc.v:44732$1379_Y
- attribute \src "libresoc.v:44734.18-44734.93"
- wire $not$libresoc.v:44734$1381_Y
- attribute \src "libresoc.v:44735.17-44735.138"
- wire width 8 $not$libresoc.v:44735$1382_Y
- attribute \src "libresoc.v:44737.18-44737.93"
- wire $not$libresoc.v:44737$1384_Y
- attribute \src "libresoc.v:44739.18-44739.93"
- wire $not$libresoc.v:44739$1386_Y
- attribute \src "libresoc.v:44741.18-44741.93"
- wire $not$libresoc.v:44741$1388_Y
- attribute \src "libresoc.v:44744.17-44744.91"
- wire $not$libresoc.v:44744$1391_Y
- attribute \src "libresoc.v:44731.18-44731.116"
- wire $reduce_or$libresoc.v:44731$1378_Y
- attribute \src "libresoc.v:44733.18-44733.122"
- wire $reduce_or$libresoc.v:44733$1380_Y
- attribute \src "libresoc.v:44736.18-44736.128"
- wire $reduce_or$libresoc.v:44736$1383_Y
- attribute \src "libresoc.v:44738.18-44738.134"
- wire $reduce_or$libresoc.v:44738$1385_Y
- attribute \src "libresoc.v:44740.18-44740.140"
- wire $reduce_or$libresoc.v:44740$1387_Y
- attribute \src "libresoc.v:44742.18-44742.90"
- wire $reduce_or$libresoc.v:44742$1389_Y
- attribute \src "libresoc.v:44743.17-44743.103"
- wire $reduce_or$libresoc.v:44743$1390_Y
- attribute \src "libresoc.v:44745.17-44745.109"
- wire $reduce_or$libresoc.v:44745$1392_Y
+ attribute \src "libresoc.v:44936.17-44936.91"
+ wire $not$libresoc.v:44936$1417_Y
+ attribute \src "libresoc.v:44938.18-44938.93"
+ wire $not$libresoc.v:44938$1419_Y
+ attribute \src "libresoc.v:44940.18-44940.93"
+ wire $not$libresoc.v:44940$1421_Y
+ attribute \src "libresoc.v:44941.17-44941.138"
+ wire width 8 $not$libresoc.v:44941$1422_Y
+ attribute \src "libresoc.v:44943.18-44943.93"
+ wire $not$libresoc.v:44943$1424_Y
+ attribute \src "libresoc.v:44945.18-44945.93"
+ wire $not$libresoc.v:44945$1426_Y
+ attribute \src "libresoc.v:44947.18-44947.93"
+ wire $not$libresoc.v:44947$1428_Y
+ attribute \src "libresoc.v:44950.17-44950.91"
+ wire $not$libresoc.v:44950$1431_Y
+ attribute \src "libresoc.v:44937.18-44937.116"
+ wire $reduce_or$libresoc.v:44937$1418_Y
+ attribute \src "libresoc.v:44939.18-44939.122"
+ wire $reduce_or$libresoc.v:44939$1420_Y
+ attribute \src "libresoc.v:44942.18-44942.128"
+ wire $reduce_or$libresoc.v:44942$1423_Y
+ attribute \src "libresoc.v:44944.18-44944.134"
+ wire $reduce_or$libresoc.v:44944$1425_Y
+ attribute \src "libresoc.v:44946.18-44946.140"
+ wire $reduce_or$libresoc.v:44946$1427_Y
+ attribute \src "libresoc.v:44948.18-44948.90"
+ wire $reduce_or$libresoc.v:44948$1429_Y
+ attribute \src "libresoc.v:44949.17-44949.103"
+ wire $reduce_or$libresoc.v:44949$1430_Y
+ attribute \src "libresoc.v:44951.17-44951.109"
+ wire $reduce_or$libresoc.v:44951$1432_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53"
wire width 8 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \t7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44730$1377
+ cell $not $not$libresoc.v:44936$1417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:44730$1377_Y
+ connect \Y $not$libresoc.v:44936$1417_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44732$1379
+ cell $not $not$libresoc.v:44938$1419
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:44732$1379_Y
+ connect \Y $not$libresoc.v:44938$1419_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44734$1381
+ cell $not $not$libresoc.v:44940$1421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:44734$1381_Y
+ connect \Y $not$libresoc.v:44940$1421_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53"
- cell $not $not$libresoc.v:44735$1382
+ cell $not $not$libresoc.v:44941$1422
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] }
- connect \Y $not$libresoc.v:44735$1382_Y
+ connect \Y $not$libresoc.v:44941$1422_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44737$1384
+ cell $not $not$libresoc.v:44943$1424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:44737$1384_Y
+ connect \Y $not$libresoc.v:44943$1424_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44739$1386
+ cell $not $not$libresoc.v:44945$1426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:44739$1386_Y
+ connect \Y $not$libresoc.v:44945$1426_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44741$1388
+ cell $not $not$libresoc.v:44947$1428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:44741$1388_Y
+ connect \Y $not$libresoc.v:44947$1428_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:44744$1391
+ cell $not $not$libresoc.v:44950$1431
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:44744$1391_Y
+ connect \Y $not$libresoc.v:44950$1431_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44731$1378
+ cell $reduce_or $reduce_or$libresoc.v:44937$1418
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [5] \i [6] \i [7] \ni [3] }
- connect \Y $reduce_or$libresoc.v:44731$1378_Y
+ connect \Y $reduce_or$libresoc.v:44937$1418_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44733$1380
+ cell $reduce_or $reduce_or$libresoc.v:44939$1420
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] }
- connect \Y $reduce_or$libresoc.v:44733$1380_Y
+ connect \Y $reduce_or$libresoc.v:44939$1420_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44736$1383
+ cell $reduce_or $reduce_or$libresoc.v:44942$1423
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] }
- connect \Y $reduce_or$libresoc.v:44736$1383_Y
+ connect \Y $reduce_or$libresoc.v:44942$1423_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44738$1385
+ cell $reduce_or $reduce_or$libresoc.v:44944$1425
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] }
- connect \Y $reduce_or$libresoc.v:44738$1385_Y
+ connect \Y $reduce_or$libresoc.v:44944$1425_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44740$1387
+ cell $reduce_or $reduce_or$libresoc.v:44946$1427
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] }
- connect \Y $reduce_or$libresoc.v:44740$1387_Y
+ connect \Y $reduce_or$libresoc.v:44946$1427_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69"
- cell $reduce_or $reduce_or$libresoc.v:44742$1389
+ cell $reduce_or $reduce_or$libresoc.v:44948$1429
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:44742$1389_Y
+ connect \Y $reduce_or$libresoc.v:44948$1429_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44743$1390
+ cell $reduce_or $reduce_or$libresoc.v:44949$1430
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [7] \ni [1] }
- connect \Y $reduce_or$libresoc.v:44743$1390_Y
+ connect \Y $reduce_or$libresoc.v:44949$1430_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:44745$1392
+ cell $reduce_or $reduce_or$libresoc.v:44951$1432
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [6] \i [7] \ni [2] }
- connect \Y $reduce_or$libresoc.v:44745$1392_Y
- end
- connect \$7 $not$libresoc.v:44730$1377_Y
- connect \$12 $reduce_or$libresoc.v:44731$1378_Y
- connect \$11 $not$libresoc.v:44732$1379_Y
- connect \$16 $reduce_or$libresoc.v:44733$1380_Y
- connect \$15 $not$libresoc.v:44734$1381_Y
- connect \$1 $not$libresoc.v:44735$1382_Y
- connect \$20 $reduce_or$libresoc.v:44736$1383_Y
- connect \$19 $not$libresoc.v:44737$1384_Y
- connect \$24 $reduce_or$libresoc.v:44738$1385_Y
- connect \$23 $not$libresoc.v:44739$1386_Y
- connect \$28 $reduce_or$libresoc.v:44740$1387_Y
- connect \$27 $not$libresoc.v:44741$1388_Y
- connect \$31 $reduce_or$libresoc.v:44742$1389_Y
- connect \$4 $reduce_or$libresoc.v:44743$1390_Y
- connect \$3 $not$libresoc.v:44744$1391_Y
- connect \$8 $reduce_or$libresoc.v:44745$1392_Y
+ connect \Y $reduce_or$libresoc.v:44951$1432_Y
+ end
+ connect \$7 $not$libresoc.v:44936$1417_Y
+ connect \$12 $reduce_or$libresoc.v:44937$1418_Y
+ connect \$11 $not$libresoc.v:44938$1419_Y
+ connect \$16 $reduce_or$libresoc.v:44939$1420_Y
+ connect \$15 $not$libresoc.v:44940$1421_Y
+ connect \$1 $not$libresoc.v:44941$1422_Y
+ connect \$20 $reduce_or$libresoc.v:44942$1423_Y
+ connect \$19 $not$libresoc.v:44943$1424_Y
+ connect \$24 $reduce_or$libresoc.v:44944$1425_Y
+ connect \$23 $not$libresoc.v:44945$1426_Y
+ connect \$28 $reduce_or$libresoc.v:44946$1427_Y
+ connect \$27 $not$libresoc.v:44947$1428_Y
+ connect \$31 $reduce_or$libresoc.v:44948$1429_Y
+ connect \$4 $reduce_or$libresoc.v:44949$1430_Y
+ connect \$3 $not$libresoc.v:44950$1431_Y
+ connect \$8 $reduce_or$libresoc.v:44951$1432_Y
connect \en_o \$31
connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 }
connect \t7 \$27
connect \t0 \i [7]
connect \ni \$1
end
-attribute \src "libresoc.v:44761.1-45576.10"
+attribute \src "libresoc.v:44967.1-45782.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec_a.sprmap"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap"
attribute \generator "nMigen"
module \sprmap
- attribute \src "libresoc.v:44888.3-44918.6"
+ attribute \src "libresoc.v:45094.3-45124.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:44919.3-44949.6"
+ attribute \src "libresoc.v:45125.3-45155.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:44762.7-44762.20"
+ attribute \src "libresoc.v:44968.7-44968.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:44950.3-45262.6"
+ attribute \src "libresoc.v:45156.3-45468.6"
wire width 10 $0\spr_o[9:0]
- attribute \src "libresoc.v:45263.3-45575.6"
+ attribute \src "libresoc.v:45469.3-45781.6"
wire $0\spr_o_ok[0:0]
- attribute \src "libresoc.v:44888.3-44918.6"
+ attribute \src "libresoc.v:45094.3-45124.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:44919.3-44949.6"
+ attribute \src "libresoc.v:45125.3-45155.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:44950.3-45262.6"
+ attribute \src "libresoc.v:45156.3-45468.6"
wire width 10 $1\spr_o[9:0]
- attribute \src "libresoc.v:45263.3-45575.6"
+ attribute \src "libresoc.v:45469.3-45781.6"
wire $1\spr_o_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire width 3 output 3 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire output 4 \fast_o_ok
- attribute \src "libresoc.v:44762.7-44762.15"
+ attribute \src "libresoc.v:44968.7-44968.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59"
wire width 10 input 5 \spr_i
wire width 10 output 1 \spr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire output 2 \spr_o_ok
- attribute \src "libresoc.v:44762.7-44762.20"
- process $proc$libresoc.v:44762$1397
+ attribute \src "libresoc.v:44968.7-44968.20"
+ process $proc$libresoc.v:44968$1437
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:44888.3-44918.6"
- process $proc$libresoc.v:44888$1393
+ attribute \src "libresoc.v:45094.3-45124.6"
+ process $proc$libresoc.v:45094$1433
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $1\fast_o[2:0]
- attribute \src "libresoc.v:44889.5-44889.29"
+ attribute \src "libresoc.v:45095.5-45095.29"
switch \initial
- attribute \src "libresoc.v:44889.9-44889.17"
+ attribute \src "libresoc.v:45095.9-45095.17"
case 1'1
case
end
sync always
update \fast_o $0\fast_o[2:0]
end
- attribute \src "libresoc.v:44919.3-44949.6"
- process $proc$libresoc.v:44919$1394
+ attribute \src "libresoc.v:45125.3-45155.6"
+ process $proc$libresoc.v:45125$1434
assign { } { }
assign { } { }
assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:44920.5-44920.29"
+ attribute \src "libresoc.v:45126.5-45126.29"
switch \initial
- attribute \src "libresoc.v:44920.9-44920.17"
+ attribute \src "libresoc.v:45126.9-45126.17"
case 1'1
case
end
sync always
update \fast_o_ok $0\fast_o_ok[0:0]
end
- attribute \src "libresoc.v:44950.3-45262.6"
- process $proc$libresoc.v:44950$1395
+ attribute \src "libresoc.v:45156.3-45468.6"
+ process $proc$libresoc.v:45156$1435
assign { } { }
assign { } { }
assign $0\spr_o[9:0] $1\spr_o[9:0]
- attribute \src "libresoc.v:44951.5-44951.29"
+ attribute \src "libresoc.v:45157.5-45157.29"
switch \initial
- attribute \src "libresoc.v:44951.9-44951.17"
+ attribute \src "libresoc.v:45157.9-45157.17"
case 1'1
case
end
sync always
update \spr_o $0\spr_o[9:0]
end
- attribute \src "libresoc.v:45263.3-45575.6"
- process $proc$libresoc.v:45263$1396
+ attribute \src "libresoc.v:45469.3-45781.6"
+ process $proc$libresoc.v:45469$1436
assign { } { }
assign { } { }
assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:45264.5-45264.29"
+ attribute \src "libresoc.v:45470.5-45470.29"
switch \initial
- attribute \src "libresoc.v:45264.9-45264.17"
+ attribute \src "libresoc.v:45470.9-45470.17"
case 1'1
case
end
update \spr_o_ok $0\spr_o_ok[0:0]
end
end
-attribute \src "libresoc.v:45580.1-46395.10"
+attribute \src "libresoc.v:45786.1-46601.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.dec2.dec_o.sprmap"
+attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap"
attribute \generator "nMigen"
module \sprmap$2
- attribute \src "libresoc.v:45707.3-45737.6"
+ attribute \src "libresoc.v:45913.3-45943.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:45738.3-45768.6"
+ attribute \src "libresoc.v:45944.3-45974.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:45581.7-45581.20"
+ attribute \src "libresoc.v:45787.7-45787.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:45769.3-46081.6"
+ attribute \src "libresoc.v:45975.3-46287.6"
wire width 10 $0\spr_o[9:0]
- attribute \src "libresoc.v:46082.3-46394.6"
+ attribute \src "libresoc.v:46288.3-46600.6"
wire $0\spr_o_ok[0:0]
- attribute \src "libresoc.v:45707.3-45737.6"
+ attribute \src "libresoc.v:45913.3-45943.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:45738.3-45768.6"
+ attribute \src "libresoc.v:45944.3-45974.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:45769.3-46081.6"
+ attribute \src "libresoc.v:45975.3-46287.6"
wire width 10 $1\spr_o[9:0]
- attribute \src "libresoc.v:46082.3-46394.6"
+ attribute \src "libresoc.v:46288.3-46600.6"
wire $1\spr_o_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire width 3 output 3 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire output 4 \fast_o_ok
- attribute \src "libresoc.v:45581.7-45581.15"
+ attribute \src "libresoc.v:45787.7-45787.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59"
wire width 10 input 5 \spr_i
wire width 10 output 1 \spr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
wire output 2 \spr_o_ok
- attribute \src "libresoc.v:45581.7-45581.20"
- process $proc$libresoc.v:45581$1402
+ attribute \src "libresoc.v:45787.7-45787.20"
+ process $proc$libresoc.v:45787$1442
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:45707.3-45737.6"
- process $proc$libresoc.v:45707$1398
+ attribute \src "libresoc.v:45913.3-45943.6"
+ process $proc$libresoc.v:45913$1438
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $1\fast_o[2:0]
- attribute \src "libresoc.v:45708.5-45708.29"
+ attribute \src "libresoc.v:45914.5-45914.29"
switch \initial
- attribute \src "libresoc.v:45708.9-45708.17"
+ attribute \src "libresoc.v:45914.9-45914.17"
case 1'1
case
end
sync always
update \fast_o $0\fast_o[2:0]
end
- attribute \src "libresoc.v:45738.3-45768.6"
- process $proc$libresoc.v:45738$1399
+ attribute \src "libresoc.v:45944.3-45974.6"
+ process $proc$libresoc.v:45944$1439
assign { } { }
assign { } { }
assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:45739.5-45739.29"
+ attribute \src "libresoc.v:45945.5-45945.29"
switch \initial
- attribute \src "libresoc.v:45739.9-45739.17"
+ attribute \src "libresoc.v:45945.9-45945.17"
case 1'1
case
end
sync always
update \fast_o_ok $0\fast_o_ok[0:0]
end
- attribute \src "libresoc.v:45769.3-46081.6"
- process $proc$libresoc.v:45769$1400
+ attribute \src "libresoc.v:45975.3-46287.6"
+ process $proc$libresoc.v:45975$1440
assign { } { }
assign { } { }
assign $0\spr_o[9:0] $1\spr_o[9:0]
- attribute \src "libresoc.v:45770.5-45770.29"
+ attribute \src "libresoc.v:45976.5-45976.29"
switch \initial
- attribute \src "libresoc.v:45770.9-45770.17"
+ attribute \src "libresoc.v:45976.9-45976.17"
case 1'1
case
end
sync always
update \spr_o $0\spr_o[9:0]
end
- attribute \src "libresoc.v:46082.3-46394.6"
- process $proc$libresoc.v:46082$1401
+ attribute \src "libresoc.v:46288.3-46600.6"
+ process $proc$libresoc.v:46288$1441
assign { } { }
assign { } { }
assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:46083.5-46083.29"
+ attribute \src "libresoc.v:46289.5-46289.29"
switch \initial
- attribute \src "libresoc.v:46083.9-46083.17"
+ attribute \src "libresoc.v:46289.9-46289.17"
case 1'1
case
end
update \spr_o_ok $0\spr_o_ok[0:0]
end
end
-attribute \src "libresoc.v:46400.1-49501.10"
+attribute \src "libresoc.v:46606.1-47121.10"
attribute \cells_not_processed 1
attribute \top 1
attribute \nmigen.hierarchy "test_issuer"
attribute \generator "nMigen"
module \test_issuer
- attribute \src "libresoc.v:49107.3-49143.6"
- wire $0\bigendian_i$next[0:0]$1844
- attribute \src "libresoc.v:48104.3-48105.39"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39"
+ wire input 9 \TAP_bus__tck
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39"
+ wire input 7 \TAP_bus__tdi
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39"
+ wire output 6 \TAP_bus__tdo
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39"
+ wire input 8 \TAP_bus__tms
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:92"
+ wire output 5 \busy_o
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:527"
+ wire input 166 \clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:36"
+ wire width 3 input 164 \clk_sel_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:34"
+ wire \clksel_clk_24_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:37"
+ wire \clksel_core_clk_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458"
+ wire \clksel_pllclk_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:38"
+ wire \clksel_rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:91"
+ wire input 4 \core_bigendian_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire input 136 \dbus__ack
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire width 45 input 130 \dbus__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire width 2 input 139 \dbus__bte
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire width 3 input 138 \dbus__cti
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire input 134 \dbus__cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire width 64 input 132 \dbus__dat_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire width 64 input 131 \dbus__dat_w
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire input 140 \dbus__err
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire width 8 input 133 \dbus__sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire input 135 \dbus__stb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire input 137 \dbus__we
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 23 \gpio_gpio0__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 24 \gpio_gpio0__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 25 \gpio_gpio0__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 26 \gpio_gpio0__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 27 \gpio_gpio0__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 28 \gpio_gpio0__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 83 \gpio_gpio10__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 84 \gpio_gpio10__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 85 \gpio_gpio10__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 86 \gpio_gpio10__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 87 \gpio_gpio10__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 88 \gpio_gpio10__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 89 \gpio_gpio11__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 90 \gpio_gpio11__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 91 \gpio_gpio11__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 92 \gpio_gpio11__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 93 \gpio_gpio11__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 94 \gpio_gpio11__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 95 \gpio_gpio12__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 96 \gpio_gpio12__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 97 \gpio_gpio12__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 98 \gpio_gpio12__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 99 \gpio_gpio12__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 100 \gpio_gpio12__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 101 \gpio_gpio13__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 102 \gpio_gpio13__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 103 \gpio_gpio13__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 104 \gpio_gpio13__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 105 \gpio_gpio13__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 106 \gpio_gpio13__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 107 \gpio_gpio14__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 108 \gpio_gpio14__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 109 \gpio_gpio14__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 110 \gpio_gpio14__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 111 \gpio_gpio14__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 112 \gpio_gpio14__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 113 \gpio_gpio15__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 114 \gpio_gpio15__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 115 \gpio_gpio15__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 116 \gpio_gpio15__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 117 \gpio_gpio15__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 118 \gpio_gpio15__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 29 \gpio_gpio1__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 30 \gpio_gpio1__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 31 \gpio_gpio1__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 32 \gpio_gpio1__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 33 \gpio_gpio1__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 34 \gpio_gpio1__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 35 \gpio_gpio2__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 36 \gpio_gpio2__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 37 \gpio_gpio2__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 38 \gpio_gpio2__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 39 \gpio_gpio2__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 40 \gpio_gpio2__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 41 \gpio_gpio3__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 42 \gpio_gpio3__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 43 \gpio_gpio3__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 44 \gpio_gpio3__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 45 \gpio_gpio3__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 46 \gpio_gpio3__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 47 \gpio_gpio4__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 48 \gpio_gpio4__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 49 \gpio_gpio4__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 50 \gpio_gpio4__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 51 \gpio_gpio4__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 52 \gpio_gpio4__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 53 \gpio_gpio5__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 54 \gpio_gpio5__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 55 \gpio_gpio5__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 56 \gpio_gpio5__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 57 \gpio_gpio5__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 58 \gpio_gpio5__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 59 \gpio_gpio6__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 60 \gpio_gpio6__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 61 \gpio_gpio6__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 62 \gpio_gpio6__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 63 \gpio_gpio6__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 64 \gpio_gpio6__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 65 \gpio_gpio7__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 66 \gpio_gpio7__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 67 \gpio_gpio7__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 68 \gpio_gpio7__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 69 \gpio_gpio7__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 70 \gpio_gpio7__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 71 \gpio_gpio8__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 72 \gpio_gpio8__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 73 \gpio_gpio8__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 74 \gpio_gpio8__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 75 \gpio_gpio8__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 76 \gpio_gpio8__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 77 \gpio_gpio9__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 78 \gpio_gpio9__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 79 \gpio_gpio9__core__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 80 \gpio_gpio9__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 81 \gpio_gpio9__pad__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 82 \gpio_gpio9__pad__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+ wire input 125 \ibus__ack
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+ wire width 45 output 119 \ibus__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+ wire width 2 input 128 \ibus__bte
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+ wire width 3 input 127 \ibus__cti
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+ wire output 123 \ibus__cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+ wire width 64 input 121 \ibus__dat_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+ wire width 64 input 120 \ibus__dat_w
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+ wire input 129 \ibus__err
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+ wire width 8 output 122 \ibus__sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+ wire output 124 \ibus__stb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+ wire input 126 \ibus__we
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
+ wire output 147 \icp_wb__ack
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
+ wire width 28 input 141 \icp_wb__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
+ wire width 2 input 150 \icp_wb__bte
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
+ wire width 3 input 149 \icp_wb__cti
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
+ wire input 145 \icp_wb__cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
+ wire width 32 output 143 \icp_wb__dat_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
+ wire width 32 input 142 \icp_wb__dat_w
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
+ wire input 151 \icp_wb__err
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
+ wire width 4 input 144 \icp_wb__sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
+ wire input 146 \icp_wb__stb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
+ wire input 148 \icp_wb__we
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
+ wire output 158 \ics_wb__ack
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
+ wire width 28 input 152 \ics_wb__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
+ wire width 2 input 161 \ics_wb__bte
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
+ wire width 3 input 160 \ics_wb__cti
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
+ wire input 156 \ics_wb__cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
+ wire width 32 output 154 \ics_wb__dat_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
+ wire width 32 input 153 \ics_wb__dat_w
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
+ wire input 162 \ics_wb__err
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
+ wire width 4 input 155 \ics_wb__sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
+ wire input 157 \ics_wb__stb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
+ wire input 159 \ics_wb__we
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
+ wire width 16 input 163 \int_level_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:457"
+ wire \intclk_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
+ wire input 17 \jtag_wb__ack
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
+ wire width 29 output 10 \jtag_wb__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
+ wire output 14 \jtag_wb__cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
+ wire width 64 input 12 \jtag_wb__dat_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
+ wire width 64 output 11 \jtag_wb__dat_w
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
+ wire input 18 \jtag_wb__err
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
+ wire output 13 \jtag_wb__sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
+ wire output 15 \jtag_wb__stb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
+ wire output 16 \jtag_wb__we
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:93"
+ wire input 3 \memerr_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+ wire width 64 input 168 \pc_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+ wire input 1 \pc_i_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:89"
+ wire width 64 output 2 \pc_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:35"
+ wire output 165 \pll_48_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:80"
+ wire \pll_clk_24_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:81"
+ wire \pll_clk_pll_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:82"
+ wire \pll_rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:527"
+ wire output 167 \rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 21 \uart_rx__core__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 22 \uart_rx__pad__i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire input 19 \uart_tx__core__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
+ wire output 20 \uart_tx__pad__o
+ attribute \module_not_derived 1
+ attribute \src "libresoc.v:46959.10-46966.4"
+ cell \clksel \clksel
+ connect \clk_24_i \clksel_clk_24_i
+ connect \clk_sel_i \clk_sel_i
+ connect \core_clk_o \clksel_core_clk_o
+ connect \pll_48_o \pll_48_o
+ connect \pllclk_clk \clksel_pllclk_clk
+ connect \rst \clksel_rst
+ end
+ attribute \module_not_derived 1
+ attribute \src "libresoc.v:46967.7-46972.4"
+ cell \pll \pll
+ connect \clk_24_i \pll_clk_24_i
+ connect \clk_pll_o \pll_clk_pll_o
+ connect \rst \pll_rst
+ connect \rst$1 \rst
+ end
+ attribute \module_not_derived 1
+ attribute \src "libresoc.v:46973.6-47114.4"
+ cell \ti \ti
+ connect \TAP_bus__tck \TAP_bus__tck
+ connect \TAP_bus__tdi \TAP_bus__tdi
+ connect \TAP_bus__tdo \TAP_bus__tdo
+ connect \TAP_bus__tms \TAP_bus__tms
+ connect \busy_o \busy_o
+ connect \core_bigendian_i \core_bigendian_i
+ connect \gpio_gpio0__core__i \gpio_gpio0__core__i
+ connect \gpio_gpio0__core__o \gpio_gpio0__core__o
+ connect \gpio_gpio0__core__oe \gpio_gpio0__core__oe
+ connect \gpio_gpio0__pad__i \gpio_gpio0__pad__i
+ connect \gpio_gpio0__pad__o \gpio_gpio0__pad__o
+ connect \gpio_gpio0__pad__oe \gpio_gpio0__pad__oe
+ connect \gpio_gpio10__core__i \gpio_gpio10__core__i
+ connect \gpio_gpio10__core__o \gpio_gpio10__core__o
+ connect \gpio_gpio10__core__oe \gpio_gpio10__core__oe
+ connect \gpio_gpio10__pad__i \gpio_gpio10__pad__i
+ connect \gpio_gpio10__pad__o \gpio_gpio10__pad__o
+ connect \gpio_gpio10__pad__oe \gpio_gpio10__pad__oe
+ connect \gpio_gpio11__core__i \gpio_gpio11__core__i
+ connect \gpio_gpio11__core__o \gpio_gpio11__core__o
+ connect \gpio_gpio11__core__oe \gpio_gpio11__core__oe
+ connect \gpio_gpio11__pad__i \gpio_gpio11__pad__i
+ connect \gpio_gpio11__pad__o \gpio_gpio11__pad__o
+ connect \gpio_gpio11__pad__oe \gpio_gpio11__pad__oe
+ connect \gpio_gpio12__core__i \gpio_gpio12__core__i
+ connect \gpio_gpio12__core__o \gpio_gpio12__core__o
+ connect \gpio_gpio12__core__oe \gpio_gpio12__core__oe
+ connect \gpio_gpio12__pad__i \gpio_gpio12__pad__i
+ connect \gpio_gpio12__pad__o \gpio_gpio12__pad__o
+ connect \gpio_gpio12__pad__oe \gpio_gpio12__pad__oe
+ connect \gpio_gpio13__core__i \gpio_gpio13__core__i
+ connect \gpio_gpio13__core__o \gpio_gpio13__core__o
+ connect \gpio_gpio13__core__oe \gpio_gpio13__core__oe
+ connect \gpio_gpio13__pad__i \gpio_gpio13__pad__i
+ connect \gpio_gpio13__pad__o \gpio_gpio13__pad__o
+ connect \gpio_gpio13__pad__oe \gpio_gpio13__pad__oe
+ connect \gpio_gpio14__core__i \gpio_gpio14__core__i
+ connect \gpio_gpio14__core__o \gpio_gpio14__core__o
+ connect \gpio_gpio14__core__oe \gpio_gpio14__core__oe
+ connect \gpio_gpio14__pad__i \gpio_gpio14__pad__i
+ connect \gpio_gpio14__pad__o \gpio_gpio14__pad__o
+ connect \gpio_gpio14__pad__oe \gpio_gpio14__pad__oe
+ connect \gpio_gpio15__core__i \gpio_gpio15__core__i
+ connect \gpio_gpio15__core__o \gpio_gpio15__core__o
+ connect \gpio_gpio15__core__oe \gpio_gpio15__core__oe
+ connect \gpio_gpio15__pad__i \gpio_gpio15__pad__i
+ connect \gpio_gpio15__pad__o \gpio_gpio15__pad__o
+ connect \gpio_gpio15__pad__oe \gpio_gpio15__pad__oe
+ connect \gpio_gpio1__core__i \gpio_gpio1__core__i
+ connect \gpio_gpio1__core__o \gpio_gpio1__core__o
+ connect \gpio_gpio1__core__oe \gpio_gpio1__core__oe
+ connect \gpio_gpio1__pad__i \gpio_gpio1__pad__i
+ connect \gpio_gpio1__pad__o \gpio_gpio1__pad__o
+ connect \gpio_gpio1__pad__oe \gpio_gpio1__pad__oe
+ connect \gpio_gpio2__core__i \gpio_gpio2__core__i
+ connect \gpio_gpio2__core__o \gpio_gpio2__core__o
+ connect \gpio_gpio2__core__oe \gpio_gpio2__core__oe
+ connect \gpio_gpio2__pad__i \gpio_gpio2__pad__i
+ connect \gpio_gpio2__pad__o \gpio_gpio2__pad__o
+ connect \gpio_gpio2__pad__oe \gpio_gpio2__pad__oe
+ connect \gpio_gpio3__core__i \gpio_gpio3__core__i
+ connect \gpio_gpio3__core__o \gpio_gpio3__core__o
+ connect \gpio_gpio3__core__oe \gpio_gpio3__core__oe
+ connect \gpio_gpio3__pad__i \gpio_gpio3__pad__i
+ connect \gpio_gpio3__pad__o \gpio_gpio3__pad__o
+ connect \gpio_gpio3__pad__oe \gpio_gpio3__pad__oe
+ connect \gpio_gpio4__core__i \gpio_gpio4__core__i
+ connect \gpio_gpio4__core__o \gpio_gpio4__core__o
+ connect \gpio_gpio4__core__oe \gpio_gpio4__core__oe
+ connect \gpio_gpio4__pad__i \gpio_gpio4__pad__i
+ connect \gpio_gpio4__pad__o \gpio_gpio4__pad__o
+ connect \gpio_gpio4__pad__oe \gpio_gpio4__pad__oe
+ connect \gpio_gpio5__core__i \gpio_gpio5__core__i
+ connect \gpio_gpio5__core__o \gpio_gpio5__core__o
+ connect \gpio_gpio5__core__oe \gpio_gpio5__core__oe
+ connect \gpio_gpio5__pad__i \gpio_gpio5__pad__i
+ connect \gpio_gpio5__pad__o \gpio_gpio5__pad__o
+ connect \gpio_gpio5__pad__oe \gpio_gpio5__pad__oe
+ connect \gpio_gpio6__core__i \gpio_gpio6__core__i
+ connect \gpio_gpio6__core__o \gpio_gpio6__core__o
+ connect \gpio_gpio6__core__oe \gpio_gpio6__core__oe
+ connect \gpio_gpio6__pad__i \gpio_gpio6__pad__i
+ connect \gpio_gpio6__pad__o \gpio_gpio6__pad__o
+ connect \gpio_gpio6__pad__oe \gpio_gpio6__pad__oe
+ connect \gpio_gpio7__core__i \gpio_gpio7__core__i
+ connect \gpio_gpio7__core__o \gpio_gpio7__core__o
+ connect \gpio_gpio7__core__oe \gpio_gpio7__core__oe
+ connect \gpio_gpio7__pad__i \gpio_gpio7__pad__i
+ connect \gpio_gpio7__pad__o \gpio_gpio7__pad__o
+ connect \gpio_gpio7__pad__oe \gpio_gpio7__pad__oe
+ connect \gpio_gpio8__core__i \gpio_gpio8__core__i
+ connect \gpio_gpio8__core__o \gpio_gpio8__core__o
+ connect \gpio_gpio8__core__oe \gpio_gpio8__core__oe
+ connect \gpio_gpio8__pad__i \gpio_gpio8__pad__i
+ connect \gpio_gpio8__pad__o \gpio_gpio8__pad__o
+ connect \gpio_gpio8__pad__oe \gpio_gpio8__pad__oe
+ connect \gpio_gpio9__core__i \gpio_gpio9__core__i
+ connect \gpio_gpio9__core__o \gpio_gpio9__core__o
+ connect \gpio_gpio9__core__oe \gpio_gpio9__core__oe
+ connect \gpio_gpio9__pad__i \gpio_gpio9__pad__i
+ connect \gpio_gpio9__pad__o \gpio_gpio9__pad__o
+ connect \gpio_gpio9__pad__oe \gpio_gpio9__pad__oe
+ connect \ibus__ack \ibus__ack
+ connect \ibus__adr \ibus__adr
+ connect \ibus__cyc \ibus__cyc
+ connect \ibus__dat_r \ibus__dat_r
+ connect \ibus__err \ibus__err
+ connect \ibus__sel \ibus__sel
+ connect \ibus__stb \ibus__stb
+ connect \icp_wb__ack \icp_wb__ack
+ connect \icp_wb__adr \icp_wb__adr
+ connect \icp_wb__cyc \icp_wb__cyc
+ connect \icp_wb__dat_r \icp_wb__dat_r
+ connect \icp_wb__dat_w \icp_wb__dat_w
+ connect \icp_wb__sel \icp_wb__sel
+ connect \icp_wb__stb \icp_wb__stb
+ connect \icp_wb__we \icp_wb__we
+ connect \ics_wb__ack \ics_wb__ack
+ connect \ics_wb__adr \ics_wb__adr
+ connect \ics_wb__cyc \ics_wb__cyc
+ connect \ics_wb__dat_r \ics_wb__dat_r
+ connect \ics_wb__dat_w \ics_wb__dat_w
+ connect \ics_wb__stb \ics_wb__stb
+ connect \ics_wb__we \ics_wb__we
+ connect \int_level_i \int_level_i
+ connect \jtag_wb__ack \jtag_wb__ack
+ connect \jtag_wb__adr \jtag_wb__adr
+ connect \jtag_wb__cyc \jtag_wb__cyc
+ connect \jtag_wb__dat_r \jtag_wb__dat_r
+ connect \jtag_wb__dat_w \jtag_wb__dat_w
+ connect \jtag_wb__sel \jtag_wb__sel
+ connect \jtag_wb__stb \jtag_wb__stb
+ connect \jtag_wb__we \jtag_wb__we
+ connect \pc_i \pc_i
+ connect \pc_i_ok \pc_i_ok
+ connect \pc_o \pc_o
+ connect \uart_rx__core__i \uart_rx__core__i
+ connect \uart_rx__pad__i \uart_rx__pad__i
+ connect \uart_tx__core__o \uart_tx__core__o
+ connect \uart_tx__pad__o \uart_tx__pad__o
+ end
+ connect \clksel_rst \rst
+ connect \pll_rst \rst
+ connect \pll_clk_24_i \clksel_clk_24_i
+ connect \clksel_clk_24_i \clk
+ connect \clksel_pllclk_clk \pll_clk_pll_o
+ connect \intclk_clk \clksel_core_clk_o
+end
+attribute \src "libresoc.v:47125.1-50180.10"
+attribute \cells_not_processed 1
+attribute \nmigen.hierarchy "test_issuer.ti"
+attribute \generator "nMigen"
+module \ti
+ attribute \src "libresoc.v:49784.3-49820.6"
+ wire $0\bigendian_i$next[0:0]$1884
+ attribute \src "libresoc.v:48789.3-48790.39"
wire $0\bigendian_i[0:0]
- attribute \src "libresoc.v:48831.3-48843.6"
+ attribute \src "libresoc.v:49508.3-49520.6"
wire width 4 $0\cia__ren[3:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 8 $0\core_asmcode$next[7:0]$1605
- attribute \src "libresoc.v:48108.3-48109.41"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 8 $0\core_asmcode$next[7:0]$1645
+ attribute \src "libresoc.v:48793.3-48794.41"
wire width 8 $0\core_asmcode[7:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 64 $0\core_core_cia$next[63:0]$1606
- attribute \src "libresoc.v:48184.3-48185.43"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 64 $0\core_core_cia$next[63:0]$1646
+ attribute \src "libresoc.v:48861.3-48862.43"
wire width 64 $0\core_core_cia[63:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 8 $0\core_core_cr_rd$next[7:0]$1607
- attribute \src "libresoc.v:48210.3-48211.47"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 8 $0\core_core_cr_rd$next[7:0]$1647
+ attribute \src "libresoc.v:48887.3-48888.47"
wire width 8 $0\core_core_cr_rd[7:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_core_cr_rd_ok$next[0:0]$1608
- attribute \src "libresoc.v:48212.3-48213.53"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_core_cr_rd_ok$next[0:0]$1648
+ attribute \src "libresoc.v:48889.3-48890.53"
wire $0\core_core_cr_rd_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 8 $0\core_core_cr_wr$next[7:0]$1609
- attribute \src "libresoc.v:48214.3-48215.47"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 8 $0\core_core_cr_wr$next[7:0]$1649
+ attribute \src "libresoc.v:48893.3-48894.47"
wire width 8 $0\core_core_cr_wr[7:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_core_cr_wr_ok$next[0:0]$1610
- attribute \src "libresoc.v:48216.3-48217.53"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_core_cr_wr_ok$next[0:0]$1650
+ attribute \src "libresoc.v:48895.3-48896.53"
wire $0\core_core_cr_wr_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 12 $0\core_core_fn_unit$next[11:0]$1611
- attribute \src "libresoc.v:48190.3-48191.51"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 12 $0\core_core_fn_unit$next[11:0]$1651
+ attribute \src "libresoc.v:48867.3-48868.51"
wire width 12 $0\core_core_fn_unit[11:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 2 $0\core_core_input_carry$next[1:0]$1612
- attribute \src "libresoc.v:48204.3-48205.59"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 2 $0\core_core_input_carry$next[1:0]$1652
+ attribute \src "libresoc.v:48881.3-48882.59"
wire width 2 $0\core_core_input_carry[1:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 32 $0\core_core_insn$next[31:0]$1613
- attribute \src "libresoc.v:48186.3-48187.45"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 32 $0\core_core_insn$next[31:0]$1653
+ attribute \src "libresoc.v:48863.3-48864.45"
wire width 32 $0\core_core_insn[31:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 7 $0\core_core_insn_type$next[6:0]$1614
- attribute \src "libresoc.v:48188.3-48189.55"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 7 $0\core_core_insn_type$next[6:0]$1654
+ attribute \src "libresoc.v:48865.3-48866.55"
wire width 7 $0\core_core_insn_type[6:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_core_is_32bit$next[0:0]$1615
- attribute \src "libresoc.v:48218.3-48219.53"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_core_is_32bit$next[0:0]$1655
+ attribute \src "libresoc.v:48897.3-48898.53"
wire $0\core_core_is_32bit[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_core_lk$next[0:0]$1616
- attribute \src "libresoc.v:48192.3-48193.41"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_core_lk$next[0:0]$1656
+ attribute \src "libresoc.v:48871.3-48872.41"
wire $0\core_core_lk[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 64 $0\core_core_msr$next[63:0]$1617
- attribute \src "libresoc.v:48182.3-48183.43"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 64 $0\core_core_msr$next[63:0]$1657
+ attribute \src "libresoc.v:48859.3-48860.43"
wire width 64 $0\core_core_msr[63:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_core_oe$next[0:0]$1618
- attribute \src "libresoc.v:48198.3-48199.41"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_core_oe$next[0:0]$1658
+ attribute \src "libresoc.v:48877.3-48878.41"
wire $0\core_core_oe[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_core_oe_ok$next[0:0]$1619
- attribute \src "libresoc.v:48200.3-48201.47"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_core_oe_ok$next[0:0]$1659
+ attribute \src "libresoc.v:48879.3-48880.47"
wire $0\core_core_oe_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_core_rc$next[0:0]$1620
- attribute \src "libresoc.v:48194.3-48195.41"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_core_rc$next[0:0]$1660
+ attribute \src "libresoc.v:48873.3-48874.41"
wire $0\core_core_rc[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_core_rc_ok$next[0:0]$1621
- attribute \src "libresoc.v:48196.3-48197.47"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_core_rc_ok$next[0:0]$1661
+ attribute \src "libresoc.v:48875.3-48876.47"
wire $0\core_core_rc_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 13 $0\core_core_trapaddr$next[12:0]$1622
- attribute \src "libresoc.v:48208.3-48209.53"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 13 $0\core_core_trapaddr$next[12:0]$1662
+ attribute \src "libresoc.v:48885.3-48886.53"
wire width 13 $0\core_core_trapaddr[12:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 7 $0\core_core_traptype$next[6:0]$1623
- attribute \src "libresoc.v:48206.3-48207.53"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 7 $0\core_core_traptype$next[6:0]$1663
+ attribute \src "libresoc.v:48883.3-48884.53"
wire width 7 $0\core_core_traptype[6:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $0\core_cr_in1$next[2:0]$1624
- attribute \src "libresoc.v:48164.3-48165.39"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $0\core_cr_in1$next[2:0]$1664
+ attribute \src "libresoc.v:48843.3-48844.39"
wire width 3 $0\core_cr_in1[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_cr_in1_ok$next[0:0]$1625
- attribute \src "libresoc.v:48166.3-48167.45"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_cr_in1_ok$next[0:0]$1665
+ attribute \src "libresoc.v:48845.3-48846.45"
wire $0\core_cr_in1_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $0\core_cr_in2$39$next[2:0]$1626
- attribute \src "libresoc.v:48172.3-48173.47"
- wire width 3 $0\core_cr_in2$39[2:0]$1503
- attribute \src "libresoc.v:46722.13-46722.36"
- wire width 3 $0\core_cr_in2$39[2:0]$1929
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $0\core_cr_in2$next[2:0]$1627
- attribute \src "libresoc.v:48168.3-48169.39"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $0\core_cr_in2$39$next[2:0]$1666
+ attribute \src "libresoc.v:48851.3-48852.47"
+ wire width 3 $0\core_cr_in2$39[2:0]$1543
+ attribute \src "libresoc.v:47445.13-47445.36"
+ wire width 3 $0\core_cr_in2$39[2:0]$1969
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $0\core_cr_in2$next[2:0]$1667
+ attribute \src "libresoc.v:48847.3-48848.39"
wire width 3 $0\core_cr_in2[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_cr_in2_ok$40$next[0:0]$1628
- attribute \src "libresoc.v:48174.3-48175.53"
- wire $0\core_cr_in2_ok$40[0:0]$1505
- attribute \src "libresoc.v:46730.7-46730.33"
- wire $0\core_cr_in2_ok$40[0:0]$1932
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_cr_in2_ok$next[0:0]$1629
- attribute \src "libresoc.v:48170.3-48171.45"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_cr_in2_ok$40$next[0:0]$1668
+ attribute \src "libresoc.v:48853.3-48854.53"
+ wire $0\core_cr_in2_ok$40[0:0]$1545
+ attribute \src "libresoc.v:47453.7-47453.33"
+ wire $0\core_cr_in2_ok$40[0:0]$1972
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_cr_in2_ok$next[0:0]$1669
+ attribute \src "libresoc.v:48849.3-48850.45"
wire $0\core_cr_in2_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $0\core_cr_out$next[2:0]$1630
- attribute \src "libresoc.v:48176.3-48177.39"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $0\core_cr_out$next[2:0]$1670
+ attribute \src "libresoc.v:48855.3-48856.39"
wire width 3 $0\core_cr_out[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_cr_out_ok$next[0:0]$1631
- attribute \src "libresoc.v:48178.3-48179.45"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_cr_out_ok$next[0:0]$1671
+ attribute \src "libresoc.v:48857.3-48858.45"
wire $0\core_cr_out_ok[0:0]
- attribute \src "libresoc.v:49395.3-49426.6"
- wire width 64 $0\core_dec$next[63:0]$1882
- attribute \src "libresoc.v:48094.3-48095.33"
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire width 64 $0\core_dec$next[63:0]$1922
+ attribute \src "libresoc.v:48779.3-48780.33"
wire width 64 $0\core_dec[63:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $0\core_ea$next[4:0]$1632
- attribute \src "libresoc.v:48116.3-48117.31"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $0\core_ea$next[4:0]$1672
+ attribute \src "libresoc.v:48799.3-48800.31"
wire width 5 $0\core_ea[4:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_ea_ok$next[0:0]$1633
- attribute \src "libresoc.v:48118.3-48119.37"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_ea_ok$next[0:0]$1673
+ attribute \src "libresoc.v:48801.3-48802.37"
wire $0\core_ea_ok[0:0]
- attribute \src "libresoc.v:49395.3-49426.6"
- wire $0\core_eint$next[0:0]$1883
- attribute \src "libresoc.v:48246.3-48247.35"
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire $0\core_eint$next[0:0]$1923
+ attribute \src "libresoc.v:48777.3-48778.35"
wire $0\core_eint[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $0\core_fast1$next[2:0]$1634
- attribute \src "libresoc.v:48146.3-48147.37"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $0\core_fast1$next[2:0]$1674
+ attribute \src "libresoc.v:48827.3-48828.37"
wire width 3 $0\core_fast1[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_fast1_ok$next[0:0]$1635
- attribute \src "libresoc.v:48148.3-48149.43"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_fast1_ok$next[0:0]$1675
+ attribute \src "libresoc.v:48829.3-48830.43"
wire $0\core_fast1_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $0\core_fast2$next[2:0]$1636
- attribute \src "libresoc.v:48150.3-48151.37"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $0\core_fast2$next[2:0]$1676
+ attribute \src "libresoc.v:48831.3-48832.37"
wire width 3 $0\core_fast2[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_fast2_ok$next[0:0]$1637
- attribute \src "libresoc.v:48152.3-48153.43"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_fast2_ok$next[0:0]$1677
+ attribute \src "libresoc.v:48833.3-48834.43"
wire $0\core_fast2_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $0\core_fasto1$next[2:0]$1638
- attribute \src "libresoc.v:48154.3-48155.39"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $0\core_fasto1$next[2:0]$1678
+ attribute \src "libresoc.v:48835.3-48836.39"
wire width 3 $0\core_fasto1[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_fasto1_ok$next[0:0]$1639
- attribute \src "libresoc.v:48156.3-48157.45"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_fasto1_ok$next[0:0]$1679
+ attribute \src "libresoc.v:48837.3-48838.45"
wire $0\core_fasto1_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $0\core_fasto2$next[2:0]$1640
- attribute \src "libresoc.v:48160.3-48161.39"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $0\core_fasto2$next[2:0]$1680
+ attribute \src "libresoc.v:48839.3-48840.39"
wire width 3 $0\core_fasto2[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_fasto2_ok$next[0:0]$1641
- attribute \src "libresoc.v:48162.3-48163.45"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_fasto2_ok$next[0:0]$1681
+ attribute \src "libresoc.v:48841.3-48842.45"
wire $0\core_fasto2_ok[0:0]
- attribute \src "libresoc.v:49395.3-49426.6"
- wire width 64 $0\core_msr$next[63:0]$1884
- attribute \src "libresoc.v:48244.3-48245.33"
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire width 64 $0\core_msr$next[63:0]$1924
+ attribute \src "libresoc.v:48775.3-48776.33"
wire width 64 $0\core_msr[63:0]
- attribute \src "libresoc.v:49395.3-49426.6"
- wire width 64 $0\core_pc$next[63:0]$1885
- attribute \src "libresoc.v:48224.3-48225.31"
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire width 64 $0\core_pc$next[63:0]$1925
+ attribute \src "libresoc.v:48773.3-48774.31"
wire width 64 $0\core_pc[63:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $0\core_reg1$next[4:0]$1642
- attribute \src "libresoc.v:48120.3-48121.35"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $0\core_reg1$next[4:0]$1682
+ attribute \src "libresoc.v:48803.3-48804.35"
wire width 5 $0\core_reg1[4:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_reg1_ok$next[0:0]$1643
- attribute \src "libresoc.v:48122.3-48123.41"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_reg1_ok$next[0:0]$1683
+ attribute \src "libresoc.v:48805.3-48806.41"
wire $0\core_reg1_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $0\core_reg2$next[4:0]$1644
- attribute \src "libresoc.v:48124.3-48125.35"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $0\core_reg2$next[4:0]$1684
+ attribute \src "libresoc.v:48807.3-48808.35"
wire width 5 $0\core_reg2[4:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_reg2_ok$next[0:0]$1645
- attribute \src "libresoc.v:48126.3-48127.41"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_reg2_ok$next[0:0]$1685
+ attribute \src "libresoc.v:48809.3-48810.41"
wire $0\core_reg2_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $0\core_reg3$next[4:0]$1646
- attribute \src "libresoc.v:48128.3-48129.35"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $0\core_reg3$next[4:0]$1686
+ attribute \src "libresoc.v:48811.3-48812.35"
wire width 5 $0\core_reg3[4:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_reg3_ok$next[0:0]$1647
- attribute \src "libresoc.v:48130.3-48131.41"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_reg3_ok$next[0:0]$1687
+ attribute \src "libresoc.v:48813.3-48814.41"
wire $0\core_reg3_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $0\core_rego$next[4:0]$1648
- attribute \src "libresoc.v:48110.3-48111.35"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $0\core_rego$next[4:0]$1688
+ attribute \src "libresoc.v:48795.3-48796.35"
wire width 5 $0\core_rego[4:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_rego_ok$next[0:0]$1649
- attribute \src "libresoc.v:48112.3-48113.41"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_rego_ok$next[0:0]$1689
+ attribute \src "libresoc.v:48797.3-48798.41"
wire $0\core_rego_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 10 $0\core_spr1$next[9:0]$1650
- attribute \src "libresoc.v:48138.3-48139.35"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 10 $0\core_spr1$next[9:0]$1690
+ attribute \src "libresoc.v:48819.3-48820.35"
wire width 10 $0\core_spr1[9:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_spr1_ok$next[0:0]$1651
- attribute \src "libresoc.v:48140.3-48141.41"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_spr1_ok$next[0:0]$1691
+ attribute \src "libresoc.v:48821.3-48822.41"
wire $0\core_spr1_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 10 $0\core_spro$next[9:0]$1652
- attribute \src "libresoc.v:48132.3-48133.35"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 10 $0\core_spro$next[9:0]$1692
+ attribute \src "libresoc.v:48815.3-48816.35"
wire width 10 $0\core_spro[9:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_spro_ok$next[0:0]$1653
- attribute \src "libresoc.v:48134.3-48135.41"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_spro_ok$next[0:0]$1693
+ attribute \src "libresoc.v:48817.3-48818.41"
wire $0\core_spro_ok[0:0]
- attribute \src "libresoc.v:49317.3-49335.6"
+ attribute \src "libresoc.v:49994.3-50012.6"
wire $0\core_stopped_i[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $0\core_xer_in$next[2:0]$1654
- attribute \src "libresoc.v:48142.3-48143.39"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $0\core_xer_in$next[2:0]$1694
+ attribute \src "libresoc.v:48823.3-48824.39"
wire width 3 $0\core_xer_in[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $0\core_xer_out$next[0:0]$1655
- attribute \src "libresoc.v:48144.3-48145.41"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $0\core_xer_out$next[0:0]$1695
+ attribute \src "libresoc.v:48825.3-48826.41"
wire $0\core_xer_out[0:0]
- attribute \src "libresoc.v:48226.3-48227.30"
+ attribute \src "libresoc.v:48903.3-48904.30"
wire $0\cu_st__rel_o_dly[0:0]
- attribute \src "libresoc.v:48588.3-48596.6"
- wire $0\d_cr_delay$next[0:0]$1558
- attribute \src "libresoc.v:48158.3-48159.37"
+ attribute \src "libresoc.v:49265.3-49273.6"
+ wire $0\d_cr_delay$next[0:0]$1598
+ attribute \src "libresoc.v:48923.3-48924.37"
wire $0\d_cr_delay[0:0]
- attribute \src "libresoc.v:48549.3-48557.6"
- wire $0\d_reg_delay$next[0:0]$1552
- attribute \src "libresoc.v:48180.3-48181.39"
+ attribute \src "libresoc.v:49226.3-49234.6"
+ wire $0\d_reg_delay$next[0:0]$1592
+ attribute \src "libresoc.v:48769.3-48770.39"
wire $0\d_reg_delay[0:0]
- attribute \src "libresoc.v:48627.3-48635.6"
- wire $0\d_xer_delay$next[0:0]$1564
- attribute \src "libresoc.v:48136.3-48137.39"
+ attribute \src "libresoc.v:49304.3-49312.6"
+ wire $0\d_xer_delay$next[0:0]$1604
+ attribute \src "libresoc.v:48913.3-48914.39"
wire $0\d_xer_delay[0:0]
- attribute \src "libresoc.v:48865.3-48885.6"
+ attribute \src "libresoc.v:49542.3-49562.6"
wire width 64 $0\data_i[63:0]
- attribute \src "libresoc.v:49336.3-49354.6"
+ attribute \src "libresoc.v:50013.3-50031.6"
wire $0\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:48607.3-48616.6"
+ attribute \src "libresoc.v:49284.3-49293.6"
wire $0\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:48597.3-48606.6"
+ attribute \src "libresoc.v:49274.3-49283.6"
wire width 64 $0\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:48568.3-48577.6"
+ attribute \src "libresoc.v:49245.3-49254.6"
wire $0\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:48558.3-48567.6"
+ attribute \src "libresoc.v:49235.3-49244.6"
wire width 64 $0\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:48646.3-48655.6"
+ attribute \src "libresoc.v:49323.3-49332.6"
wire $0\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:48636.3-48645.6"
+ attribute \src "libresoc.v:49313.3-49322.6"
wire width 64 $0\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:48500.3-48508.6"
- wire width 4 $0\dbg_dmi_addr_i$next[3:0]$1543
- attribute \src "libresoc.v:48242.3-48243.45"
+ attribute \src "libresoc.v:49177.3-49185.6"
+ wire width 4 $0\dbg_dmi_addr_i$next[3:0]$1583
+ attribute \src "libresoc.v:48921.3-48922.45"
wire width 4 $0\dbg_dmi_addr_i[3:0]
- attribute \src "libresoc.v:48902.3-48910.6"
- wire width 64 $0\dbg_dmi_din$next[63:0]$1597
- attribute \src "libresoc.v:48236.3-48237.39"
+ attribute \src "libresoc.v:49579.3-49587.6"
+ wire width 64 $0\dbg_dmi_din$next[63:0]$1637
+ attribute \src "libresoc.v:48915.3-48916.39"
wire width 64 $0\dbg_dmi_din[63:0]
- attribute \src "libresoc.v:48509.3-48517.6"
- wire $0\dbg_dmi_req_i$next[0:0]$1546
- attribute \src "libresoc.v:48240.3-48241.43"
+ attribute \src "libresoc.v:49186.3-49194.6"
+ wire $0\dbg_dmi_req_i$next[0:0]$1586
+ attribute \src "libresoc.v:48919.3-48920.43"
wire $0\dbg_dmi_req_i[0:0]
- attribute \src "libresoc.v:48797.3-48805.6"
- wire $0\dbg_dmi_we_i$next[0:0]$1586
- attribute \src "libresoc.v:48238.3-48239.41"
+ attribute \src "libresoc.v:49474.3-49482.6"
+ wire $0\dbg_dmi_we_i$next[0:0]$1626
+ attribute \src "libresoc.v:48917.3-48918.41"
wire $0\dbg_dmi_we_i[0:0]
- attribute \src "libresoc.v:48770.3-48785.6"
- wire width 64 $0\dec2_cur_dec$next[63:0]$1581
- attribute \src "libresoc.v:48092.3-48093.41"
+ attribute \src "libresoc.v:49447.3-49462.6"
+ wire width 64 $0\dec2_cur_dec$next[63:0]$1621
+ attribute \src "libresoc.v:48869.3-48870.41"
wire width 64 $0\dec2_cur_dec[63:0]
- attribute \src "libresoc.v:49061.3-49069.6"
- wire $0\dec2_cur_eint$next[0:0]$1835
- attribute \src "libresoc.v:48230.3-48231.43"
+ attribute \src "libresoc.v:49738.3-49746.6"
+ wire $0\dec2_cur_eint$next[0:0]$1875
+ attribute \src "libresoc.v:48907.3-48908.43"
wire $0\dec2_cur_eint[0:0]
- attribute \src "libresoc.v:49355.3-49375.6"
- wire width 64 $0\dec2_cur_msr$next[63:0]$1876
- attribute \src "libresoc.v:48096.3-48097.41"
+ attribute \src "libresoc.v:50032.3-50052.6"
+ wire width 64 $0\dec2_cur_msr$next[63:0]$1916
+ attribute \src "libresoc.v:48781.3-48782.41"
wire width 64 $0\dec2_cur_msr[63:0]
- attribute \src "libresoc.v:49210.3-49230.6"
- wire width 64 $0\dec2_cur_pc$next[63:0]$1853
- attribute \src "libresoc.v:48102.3-48103.39"
+ attribute \src "libresoc.v:49887.3-49907.6"
+ wire width 64 $0\dec2_cur_pc$next[63:0]$1893
+ attribute \src "libresoc.v:48787.3-48788.39"
wire width 64 $0\dec2_cur_pc[63:0]
- attribute \src "libresoc.v:49376.3-49394.6"
+ attribute \src "libresoc.v:50053.3-50071.6"
wire width 32 $0\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:49307.3-49316.6"
- wire width 2 $0\delay$next[1:0]$1871
- attribute \src "libresoc.v:48228.3-48229.27"
+ attribute \src "libresoc.v:49984.3-49993.6"
+ wire width 2 $0\delay$next[1:0]$1911
+ attribute \src "libresoc.v:48905.3-48906.27"
wire width 2 $0\delay[1:0]
- attribute \src "libresoc.v:48529.3-48538.6"
+ attribute \src "libresoc.v:49206.3-49215.6"
wire width 5 $0\dmi__addr[4:0]
- attribute \src "libresoc.v:48539.3-48548.6"
+ attribute \src "libresoc.v:49216.3-49225.6"
wire $0\dmi__ren[0:0]
- attribute \src "libresoc.v:48686.3-48713.6"
- wire width 2 $0\fsm_state$115$next[1:0]$1571
- attribute \src "libresoc.v:48114.3-48115.45"
- wire width 2 $0\fsm_state$115[1:0]$1473
- attribute \src "libresoc.v:47637.13-47637.35"
- wire width 2 $0\fsm_state$115[1:0]$1978
- attribute \src "libresoc.v:49261.3-49306.6"
- wire width 2 $0\fsm_state$next[1:0]$1864
- attribute \src "libresoc.v:48098.3-48099.35"
+ attribute \src "libresoc.v:49363.3-49390.6"
+ wire width 2 $0\fsm_state$115$next[1:0]$1611
+ attribute \src "libresoc.v:48891.3-48892.45"
+ wire width 2 $0\fsm_state$115[1:0]$1565
+ attribute \src "libresoc.v:48338.13-48338.35"
+ wire width 2 $0\fsm_state$115[1:0]$2018
+ attribute \src "libresoc.v:49938.3-49983.6"
+ wire width 2 $0\fsm_state$next[1:0]$1904
+ attribute \src "libresoc.v:48783.3-48784.35"
wire width 2 $0\fsm_state[1:0]
- attribute \src "libresoc.v:48578.3-48587.6"
+ attribute \src "libresoc.v:49255.3-49264.6"
wire width 8 $0\full_rd2__ren[7:0]
- attribute \src "libresoc.v:48617.3-48626.6"
+ attribute \src "libresoc.v:49294.3-49303.6"
wire width 3 $0\full_rd__ren[2:0]
- attribute \src "libresoc.v:49427.3-49450.6"
- wire width 32 $0\ilatch$next[31:0]$1899
- attribute \src "libresoc.v:48202.3-48203.29"
+ attribute \src "libresoc.v:50104.3-50127.6"
+ wire width 32 $0\ilatch$next[31:0]$1939
+ attribute \src "libresoc.v:48771.3-48772.29"
wire width 32 $0\ilatch[31:0]
- attribute \src "libresoc.v:49144.3-49159.6"
+ attribute \src "libresoc.v:49821.3-49836.6"
wire width 48 $0\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:49160.3-49184.6"
+ attribute \src "libresoc.v:49837.3-49861.6"
wire $0\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:49185.3-49209.6"
+ attribute \src "libresoc.v:49862.3-49886.6"
wire $0\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:46401.7-46401.20"
+ attribute \src "libresoc.v:47126.7-47126.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:48725.3-48739.6"
- wire width 3 $0\issue__addr$119[2:0]$1576
- attribute \src "libresoc.v:48656.3-48670.6"
+ attribute \src "libresoc.v:49402.3-49416.6"
+ wire width 3 $0\issue__addr$119[2:0]$1616
+ attribute \src "libresoc.v:49333.3-49347.6"
wire width 3 $0\issue__addr[2:0]
- attribute \src "libresoc.v:48755.3-48769.6"
+ attribute \src "libresoc.v:49432.3-49446.6"
wire width 64 $0\issue__data_i[63:0]
- attribute \src "libresoc.v:48671.3-48685.6"
+ attribute \src "libresoc.v:49348.3-49362.6"
wire $0\issue__ren[0:0]
- attribute \src "libresoc.v:48740.3-48754.6"
+ attribute \src "libresoc.v:49417.3-49431.6"
wire $0\issue__wen[0:0]
- attribute \src "libresoc.v:48518.3-48528.6"
+ attribute \src "libresoc.v:49195.3-49205.6"
wire $0\issue_i[0:0]
- attribute \src "libresoc.v:49451.3-49470.6"
+ attribute \src "libresoc.v:50128.3-50147.6"
wire $0\ivalid_i[0:0]
- attribute \src "libresoc.v:49043.3-49051.6"
- wire $0\jtag_dmi0_ack_o$next[0:0]$1829
- attribute \src "libresoc.v:48234.3-48235.47"
+ attribute \src "libresoc.v:49720.3-49728.6"
+ wire $0\jtag_dmi0_ack_o$next[0:0]$1869
+ attribute \src "libresoc.v:48911.3-48912.47"
wire $0\jtag_dmi0_ack_o[0:0]
- attribute \src "libresoc.v:49052.3-49060.6"
- wire width 64 $0\jtag_dmi0_dout$next[63:0]$1832
- attribute \src "libresoc.v:48232.3-48233.45"
+ attribute \src "libresoc.v:49729.3-49737.6"
+ wire width 64 $0\jtag_dmi0_dout$next[63:0]$1872
+ attribute \src "libresoc.v:48909.3-48910.45"
wire width 64 $0\jtag_dmi0_dout[63:0]
- attribute \src "libresoc.v:48886.3-48901.6"
+ attribute \src "libresoc.v:49563.3-49578.6"
wire width 4 $0\msr__ren[3:0]
- attribute \src "libresoc.v:49231.3-49260.6"
- wire $0\msr_read$next[0:0]$1858
- attribute \src "libresoc.v:48100.3-48101.33"
+ attribute \src "libresoc.v:49908.3-49937.6"
+ wire $0\msr_read$next[0:0]$1898
+ attribute \src "libresoc.v:48785.3-48786.33"
wire $0\msr_read[0:0]
- attribute \src "libresoc.v:48714.3-48724.6"
+ attribute \src "libresoc.v:49391.3-49401.6"
wire width 64 $0\new_dec[63:0]
- attribute \src "libresoc.v:48786.3-48796.6"
+ attribute \src "libresoc.v:49463.3-49473.6"
wire width 64 $0\new_tb[63:0]
- attribute \src "libresoc.v:48815.3-48830.6"
+ attribute \src "libresoc.v:49492.3-49507.6"
wire width 64 $0\pc[63:0]
- attribute \src "libresoc.v:48911.3-48935.6"
- wire $0\pc_changed$next[0:0]$1600
- attribute \src "libresoc.v:48220.3-48221.37"
+ attribute \src "libresoc.v:49588.3-49612.6"
+ wire $0\pc_changed$next[0:0]$1640
+ attribute \src "libresoc.v:48899.3-48900.37"
wire $0\pc_changed[0:0]
- attribute \src "libresoc.v:48806.3-48814.6"
- wire $0\pc_ok_delay$next[0:0]$1589
- attribute \src "libresoc.v:48222.3-48223.39"
+ attribute \src "libresoc.v:49483.3-49491.6"
+ wire $0\pc_ok_delay$next[0:0]$1629
+ attribute \src "libresoc.v:48901.3-48902.39"
wire $0\pc_ok_delay[0:0]
- attribute \src "libresoc.v:49070.3-49106.6"
- wire width 32 $0\raw_insn_i$next[31:0]$1838
- attribute \src "libresoc.v:48106.3-48107.37"
+ attribute \src "libresoc.v:49747.3-49783.6"
+ wire width 32 $0\raw_insn_i$next[31:0]$1878
+ attribute \src "libresoc.v:48791.3-48792.37"
wire width 32 $0\raw_insn_i[31:0]
- attribute \src "libresoc.v:48844.3-48864.6"
+ attribute \src "libresoc.v:49521.3-49541.6"
wire width 4 $0\wen[3:0]
- attribute \src "libresoc.v:49107.3-49143.6"
- wire $1\bigendian_i$next[0:0]$1845
- attribute \src "libresoc.v:46531.7-46531.25"
+ attribute \src "libresoc.v:49784.3-49820.6"
+ wire $1\bigendian_i$next[0:0]$1885
+ attribute \src "libresoc.v:47256.7-47256.25"
wire $1\bigendian_i[0:0]
- attribute \src "libresoc.v:48831.3-48843.6"
+ attribute \src "libresoc.v:49508.3-49520.6"
wire width 4 $1\cia__ren[3:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 8 $1\core_asmcode$next[7:0]$1656
- attribute \src "libresoc.v:46543.13-46543.33"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 8 $1\core_asmcode$next[7:0]$1696
+ attribute \src "libresoc.v:47266.13-47266.33"
wire width 8 $1\core_asmcode[7:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 64 $1\core_core_cia$next[63:0]$1657
- attribute \src "libresoc.v:46549.14-46549.50"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 64 $1\core_core_cia$next[63:0]$1697
+ attribute \src "libresoc.v:47272.14-47272.50"
wire width 64 $1\core_core_cia[63:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 8 $1\core_core_cr_rd$next[7:0]$1658
- attribute \src "libresoc.v:46553.13-46553.36"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 8 $1\core_core_cr_rd$next[7:0]$1698
+ attribute \src "libresoc.v:47276.13-47276.36"
wire width 8 $1\core_core_cr_rd[7:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_core_cr_rd_ok$next[0:0]$1659
- attribute \src "libresoc.v:46557.7-46557.32"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_core_cr_rd_ok$next[0:0]$1699
+ attribute \src "libresoc.v:47280.7-47280.32"
wire $1\core_core_cr_rd_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 8 $1\core_core_cr_wr$next[7:0]$1660
- attribute \src "libresoc.v:46561.13-46561.36"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 8 $1\core_core_cr_wr$next[7:0]$1700
+ attribute \src "libresoc.v:47284.13-47284.36"
wire width 8 $1\core_core_cr_wr[7:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_core_cr_wr_ok$next[0:0]$1661
- attribute \src "libresoc.v:46565.7-46565.32"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_core_cr_wr_ok$next[0:0]$1701
+ attribute \src "libresoc.v:47288.7-47288.32"
wire $1\core_core_cr_wr_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 12 $1\core_core_fn_unit$next[11:0]$1662
- attribute \src "libresoc.v:46582.14-46582.41"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 12 $1\core_core_fn_unit$next[11:0]$1702
+ attribute \src "libresoc.v:47305.14-47305.41"
wire width 12 $1\core_core_fn_unit[11:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 2 $1\core_core_input_carry$next[1:0]$1663
- attribute \src "libresoc.v:46590.13-46590.41"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 2 $1\core_core_input_carry$next[1:0]$1703
+ attribute \src "libresoc.v:47313.13-47313.41"
wire width 2 $1\core_core_input_carry[1:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 32 $1\core_core_insn$next[31:0]$1664
- attribute \src "libresoc.v:46594.14-46594.36"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 32 $1\core_core_insn$next[31:0]$1704
+ attribute \src "libresoc.v:47317.14-47317.36"
wire width 32 $1\core_core_insn[31:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 7 $1\core_core_insn_type$next[6:0]$1665
- attribute \src "libresoc.v:46672.13-46672.40"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 7 $1\core_core_insn_type$next[6:0]$1705
+ attribute \src "libresoc.v:47395.13-47395.40"
wire width 7 $1\core_core_insn_type[6:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_core_is_32bit$next[0:0]$1666
- attribute \src "libresoc.v:46676.7-46676.32"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_core_is_32bit$next[0:0]$1706
+ attribute \src "libresoc.v:47399.7-47399.32"
wire $1\core_core_is_32bit[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_core_lk$next[0:0]$1667
- attribute \src "libresoc.v:46680.7-46680.26"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_core_lk$next[0:0]$1707
+ attribute \src "libresoc.v:47403.7-47403.26"
wire $1\core_core_lk[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 64 $1\core_core_msr$next[63:0]$1668
- attribute \src "libresoc.v:46684.14-46684.50"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 64 $1\core_core_msr$next[63:0]$1708
+ attribute \src "libresoc.v:47407.14-47407.50"
wire width 64 $1\core_core_msr[63:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_core_oe$next[0:0]$1669
- attribute \src "libresoc.v:46688.7-46688.26"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_core_oe$next[0:0]$1709
+ attribute \src "libresoc.v:47411.7-47411.26"
wire $1\core_core_oe[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_core_oe_ok$next[0:0]$1670
- attribute \src "libresoc.v:46692.7-46692.29"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_core_oe_ok$next[0:0]$1710
+ attribute \src "libresoc.v:47415.7-47415.29"
wire $1\core_core_oe_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_core_rc$next[0:0]$1671
- attribute \src "libresoc.v:46696.7-46696.26"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_core_rc$next[0:0]$1711
+ attribute \src "libresoc.v:47419.7-47419.26"
wire $1\core_core_rc[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_core_rc_ok$next[0:0]$1672
- attribute \src "libresoc.v:46700.7-46700.29"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_core_rc_ok$next[0:0]$1712
+ attribute \src "libresoc.v:47423.7-47423.29"
wire $1\core_core_rc_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 13 $1\core_core_trapaddr$next[12:0]$1673
- attribute \src "libresoc.v:46704.14-46704.43"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 13 $1\core_core_trapaddr$next[12:0]$1713
+ attribute \src "libresoc.v:47427.14-47427.43"
wire width 13 $1\core_core_trapaddr[12:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 7 $1\core_core_traptype$next[6:0]$1674
- attribute \src "libresoc.v:46708.13-46708.39"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 7 $1\core_core_traptype$next[6:0]$1714
+ attribute \src "libresoc.v:47431.13-47431.39"
wire width 7 $1\core_core_traptype[6:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $1\core_cr_in1$next[2:0]$1675
- attribute \src "libresoc.v:46712.13-46712.31"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $1\core_cr_in1$next[2:0]$1715
+ attribute \src "libresoc.v:47435.13-47435.31"
wire width 3 $1\core_cr_in1[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_cr_in1_ok$next[0:0]$1676
- attribute \src "libresoc.v:46716.7-46716.28"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_cr_in1_ok$next[0:0]$1716
+ attribute \src "libresoc.v:47439.7-47439.28"
wire $1\core_cr_in1_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $1\core_cr_in2$39$next[2:0]$1677
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $1\core_cr_in2$next[2:0]$1678
- attribute \src "libresoc.v:46720.13-46720.31"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $1\core_cr_in2$39$next[2:0]$1717
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $1\core_cr_in2$next[2:0]$1718
+ attribute \src "libresoc.v:47443.13-47443.31"
wire width 3 $1\core_cr_in2[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_cr_in2_ok$40$next[0:0]$1679
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_cr_in2_ok$next[0:0]$1680
- attribute \src "libresoc.v:46728.7-46728.28"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_cr_in2_ok$40$next[0:0]$1719
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_cr_in2_ok$next[0:0]$1720
+ attribute \src "libresoc.v:47451.7-47451.28"
wire $1\core_cr_in2_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $1\core_cr_out$next[2:0]$1681
- attribute \src "libresoc.v:46736.13-46736.31"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $1\core_cr_out$next[2:0]$1721
+ attribute \src "libresoc.v:47459.13-47459.31"
wire width 3 $1\core_cr_out[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_cr_out_ok$next[0:0]$1682
- attribute \src "libresoc.v:46740.7-46740.28"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_cr_out_ok$next[0:0]$1722
+ attribute \src "libresoc.v:47463.7-47463.28"
wire $1\core_cr_out_ok[0:0]
- attribute \src "libresoc.v:49395.3-49426.6"
- wire width 64 $1\core_dec$next[63:0]$1886
- attribute \src "libresoc.v:46744.14-46744.45"
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire width 64 $1\core_dec$next[63:0]$1926
+ attribute \src "libresoc.v:47467.14-47467.45"
wire width 64 $1\core_dec[63:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $1\core_ea$next[4:0]$1683
- attribute \src "libresoc.v:46748.13-46748.28"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $1\core_ea$next[4:0]$1723
+ attribute \src "libresoc.v:47471.13-47471.28"
wire width 5 $1\core_ea[4:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_ea_ok$next[0:0]$1684
- attribute \src "libresoc.v:46752.7-46752.24"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_ea_ok$next[0:0]$1724
+ attribute \src "libresoc.v:47475.7-47475.24"
wire $1\core_ea_ok[0:0]
- attribute \src "libresoc.v:49395.3-49426.6"
- wire $1\core_eint$next[0:0]$1887
- attribute \src "libresoc.v:46756.7-46756.23"
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire $1\core_eint$next[0:0]$1927
+ attribute \src "libresoc.v:47479.7-47479.23"
wire $1\core_eint[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $1\core_fast1$next[2:0]$1685
- attribute \src "libresoc.v:46760.13-46760.30"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $1\core_fast1$next[2:0]$1725
+ attribute \src "libresoc.v:47483.13-47483.30"
wire width 3 $1\core_fast1[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_fast1_ok$next[0:0]$1686
- attribute \src "libresoc.v:46764.7-46764.27"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_fast1_ok$next[0:0]$1726
+ attribute \src "libresoc.v:47487.7-47487.27"
wire $1\core_fast1_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $1\core_fast2$next[2:0]$1687
- attribute \src "libresoc.v:46768.13-46768.30"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $1\core_fast2$next[2:0]$1727
+ attribute \src "libresoc.v:47491.13-47491.30"
wire width 3 $1\core_fast2[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_fast2_ok$next[0:0]$1688
- attribute \src "libresoc.v:46772.7-46772.27"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_fast2_ok$next[0:0]$1728
+ attribute \src "libresoc.v:47495.7-47495.27"
wire $1\core_fast2_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $1\core_fasto1$next[2:0]$1689
- attribute \src "libresoc.v:46776.13-46776.31"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $1\core_fasto1$next[2:0]$1729
+ attribute \src "libresoc.v:47499.13-47499.31"
wire width 3 $1\core_fasto1[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_fasto1_ok$next[0:0]$1690
- attribute \src "libresoc.v:46780.7-46780.28"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_fasto1_ok$next[0:0]$1730
+ attribute \src "libresoc.v:47503.7-47503.28"
wire $1\core_fasto1_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $1\core_fasto2$next[2:0]$1691
- attribute \src "libresoc.v:46784.13-46784.31"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $1\core_fasto2$next[2:0]$1731
+ attribute \src "libresoc.v:47507.13-47507.31"
wire width 3 $1\core_fasto2[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_fasto2_ok$next[0:0]$1692
- attribute \src "libresoc.v:46788.7-46788.28"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_fasto2_ok$next[0:0]$1732
+ attribute \src "libresoc.v:47511.7-47511.28"
wire $1\core_fasto2_ok[0:0]
- attribute \src "libresoc.v:49395.3-49426.6"
- wire width 64 $1\core_msr$next[63:0]$1888
- attribute \src "libresoc.v:46792.14-46792.45"
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire width 64 $1\core_msr$next[63:0]$1928
+ attribute \src "libresoc.v:47515.14-47515.45"
wire width 64 $1\core_msr[63:0]
- attribute \src "libresoc.v:49395.3-49426.6"
- wire width 64 $1\core_pc$next[63:0]$1889
- attribute \src "libresoc.v:46796.14-46796.44"
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire width 64 $1\core_pc$next[63:0]$1929
+ attribute \src "libresoc.v:47519.14-47519.44"
wire width 64 $1\core_pc[63:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $1\core_reg1$next[4:0]$1693
- attribute \src "libresoc.v:46800.13-46800.30"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $1\core_reg1$next[4:0]$1733
+ attribute \src "libresoc.v:47523.13-47523.30"
wire width 5 $1\core_reg1[4:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_reg1_ok$next[0:0]$1694
- attribute \src "libresoc.v:46804.7-46804.26"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_reg1_ok$next[0:0]$1734
+ attribute \src "libresoc.v:47527.7-47527.26"
wire $1\core_reg1_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $1\core_reg2$next[4:0]$1695
- attribute \src "libresoc.v:46808.13-46808.30"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $1\core_reg2$next[4:0]$1735
+ attribute \src "libresoc.v:47531.13-47531.30"
wire width 5 $1\core_reg2[4:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_reg2_ok$next[0:0]$1696
- attribute \src "libresoc.v:46812.7-46812.26"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_reg2_ok$next[0:0]$1736
+ attribute \src "libresoc.v:47535.7-47535.26"
wire $1\core_reg2_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $1\core_reg3$next[4:0]$1697
- attribute \src "libresoc.v:46816.13-46816.30"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $1\core_reg3$next[4:0]$1737
+ attribute \src "libresoc.v:47539.13-47539.30"
wire width 5 $1\core_reg3[4:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_reg3_ok$next[0:0]$1698
- attribute \src "libresoc.v:46820.7-46820.26"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_reg3_ok$next[0:0]$1738
+ attribute \src "libresoc.v:47543.7-47543.26"
wire $1\core_reg3_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $1\core_rego$next[4:0]$1699
- attribute \src "libresoc.v:46824.13-46824.30"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $1\core_rego$next[4:0]$1739
+ attribute \src "libresoc.v:47547.13-47547.30"
wire width 5 $1\core_rego[4:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_rego_ok$next[0:0]$1700
- attribute \src "libresoc.v:46828.7-46828.26"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_rego_ok$next[0:0]$1740
+ attribute \src "libresoc.v:47551.7-47551.26"
wire $1\core_rego_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 10 $1\core_spr1$next[9:0]$1701
- attribute \src "libresoc.v:46945.13-46945.32"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 10 $1\core_spr1$next[9:0]$1741
+ attribute \src "libresoc.v:47668.13-47668.32"
wire width 10 $1\core_spr1[9:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_spr1_ok$next[0:0]$1702
- attribute \src "libresoc.v:46949.7-46949.26"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_spr1_ok$next[0:0]$1742
+ attribute \src "libresoc.v:47672.7-47672.26"
wire $1\core_spr1_ok[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 10 $1\core_spro$next[9:0]$1703
- attribute \src "libresoc.v:47064.13-47064.32"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 10 $1\core_spro$next[9:0]$1743
+ attribute \src "libresoc.v:47787.13-47787.32"
wire width 10 $1\core_spro[9:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_spro_ok$next[0:0]$1704
- attribute \src "libresoc.v:47068.7-47068.26"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_spro_ok$next[0:0]$1744
+ attribute \src "libresoc.v:47791.7-47791.26"
wire $1\core_spro_ok[0:0]
- attribute \src "libresoc.v:49317.3-49335.6"
+ attribute \src "libresoc.v:49994.3-50012.6"
wire $1\core_stopped_i[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $1\core_xer_in$next[2:0]$1705
- attribute \src "libresoc.v:47076.13-47076.31"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $1\core_xer_in$next[2:0]$1745
+ attribute \src "libresoc.v:47799.13-47799.31"
wire width 3 $1\core_xer_in[2:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $1\core_xer_out$next[0:0]$1706
- attribute \src "libresoc.v:47080.7-47080.26"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $1\core_xer_out$next[0:0]$1746
+ attribute \src "libresoc.v:47803.7-47803.26"
wire $1\core_xer_out[0:0]
- attribute \src "libresoc.v:47096.7-47096.30"
+ attribute \src "libresoc.v:47819.7-47819.30"
wire $1\cu_st__rel_o_dly[0:0]
- attribute \src "libresoc.v:48588.3-48596.6"
- wire $1\d_cr_delay$next[0:0]$1559
- attribute \src "libresoc.v:47102.7-47102.24"
+ attribute \src "libresoc.v:49265.3-49273.6"
+ wire $1\d_cr_delay$next[0:0]$1599
+ attribute \src "libresoc.v:47825.7-47825.24"
wire $1\d_cr_delay[0:0]
- attribute \src "libresoc.v:48549.3-48557.6"
- wire $1\d_reg_delay$next[0:0]$1553
- attribute \src "libresoc.v:47106.7-47106.25"
+ attribute \src "libresoc.v:49226.3-49234.6"
+ wire $1\d_reg_delay$next[0:0]$1593
+ attribute \src "libresoc.v:47829.7-47829.25"
wire $1\d_reg_delay[0:0]
- attribute \src "libresoc.v:48627.3-48635.6"
- wire $1\d_xer_delay$next[0:0]$1565
- attribute \src "libresoc.v:47110.7-47110.25"
+ attribute \src "libresoc.v:49304.3-49312.6"
+ wire $1\d_xer_delay$next[0:0]$1605
+ attribute \src "libresoc.v:47833.7-47833.25"
wire $1\d_xer_delay[0:0]
- attribute \src "libresoc.v:48865.3-48885.6"
+ attribute \src "libresoc.v:49542.3-49562.6"
wire width 64 $1\data_i[63:0]
- attribute \src "libresoc.v:49336.3-49354.6"
+ attribute \src "libresoc.v:50013.3-50031.6"
wire $1\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:48607.3-48616.6"
+ attribute \src "libresoc.v:49284.3-49293.6"
wire $1\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:48597.3-48606.6"
+ attribute \src "libresoc.v:49274.3-49283.6"
wire width 64 $1\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:48568.3-48577.6"
+ attribute \src "libresoc.v:49245.3-49254.6"
wire $1\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:48558.3-48567.6"
+ attribute \src "libresoc.v:49235.3-49244.6"
wire width 64 $1\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:48646.3-48655.6"
+ attribute \src "libresoc.v:49323.3-49332.6"
wire $1\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:48636.3-48645.6"
+ attribute \src "libresoc.v:49313.3-49322.6"
wire width 64 $1\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:48500.3-48508.6"
- wire width 4 $1\dbg_dmi_addr_i$next[3:0]$1544
- attribute \src "libresoc.v:47148.13-47148.34"
+ attribute \src "libresoc.v:49177.3-49185.6"
+ wire width 4 $1\dbg_dmi_addr_i$next[3:0]$1584
+ attribute \src "libresoc.v:47871.13-47871.34"
wire width 4 $1\dbg_dmi_addr_i[3:0]
- attribute \src "libresoc.v:48902.3-48910.6"
- wire width 64 $1\dbg_dmi_din$next[63:0]$1598
- attribute \src "libresoc.v:47152.14-47152.48"
+ attribute \src "libresoc.v:49579.3-49587.6"
+ wire width 64 $1\dbg_dmi_din$next[63:0]$1638
+ attribute \src "libresoc.v:47875.14-47875.48"
wire width 64 $1\dbg_dmi_din[63:0]
- attribute \src "libresoc.v:48509.3-48517.6"
- wire $1\dbg_dmi_req_i$next[0:0]$1547
- attribute \src "libresoc.v:47158.7-47158.27"
+ attribute \src "libresoc.v:49186.3-49194.6"
+ wire $1\dbg_dmi_req_i$next[0:0]$1587
+ attribute \src "libresoc.v:47881.7-47881.27"
wire $1\dbg_dmi_req_i[0:0]
- attribute \src "libresoc.v:48797.3-48805.6"
- wire $1\dbg_dmi_we_i$next[0:0]$1587
- attribute \src "libresoc.v:47162.7-47162.26"
+ attribute \src "libresoc.v:49474.3-49482.6"
+ wire $1\dbg_dmi_we_i$next[0:0]$1627
+ attribute \src "libresoc.v:47885.7-47885.26"
wire $1\dbg_dmi_we_i[0:0]
- attribute \src "libresoc.v:48770.3-48785.6"
- wire width 64 $1\dec2_cur_dec$next[63:0]$1582
- attribute \src "libresoc.v:47220.14-47220.49"
+ attribute \src "libresoc.v:49447.3-49462.6"
+ wire width 64 $1\dec2_cur_dec$next[63:0]$1622
+ attribute \src "libresoc.v:47921.14-47921.49"
wire width 64 $1\dec2_cur_dec[63:0]
- attribute \src "libresoc.v:49061.3-49069.6"
- wire $1\dec2_cur_eint$next[0:0]$1836
- attribute \src "libresoc.v:47224.7-47224.27"
+ attribute \src "libresoc.v:49738.3-49746.6"
+ wire $1\dec2_cur_eint$next[0:0]$1876
+ attribute \src "libresoc.v:47925.7-47925.27"
wire $1\dec2_cur_eint[0:0]
- attribute \src "libresoc.v:49355.3-49375.6"
- wire width 64 $1\dec2_cur_msr$next[63:0]$1877
- attribute \src "libresoc.v:47228.14-47228.49"
+ attribute \src "libresoc.v:50032.3-50052.6"
+ wire width 64 $1\dec2_cur_msr$next[63:0]$1917
+ attribute \src "libresoc.v:47929.14-47929.49"
wire width 64 $1\dec2_cur_msr[63:0]
- attribute \src "libresoc.v:49210.3-49230.6"
- wire width 64 $1\dec2_cur_pc$next[63:0]$1854
- attribute \src "libresoc.v:47232.14-47232.48"
+ attribute \src "libresoc.v:49887.3-49907.6"
+ wire width 64 $1\dec2_cur_pc$next[63:0]$1894
+ attribute \src "libresoc.v:47933.14-47933.48"
wire width 64 $1\dec2_cur_pc[63:0]
- attribute \src "libresoc.v:49376.3-49394.6"
+ attribute \src "libresoc.v:50053.3-50071.6"
wire width 32 $1\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:49307.3-49316.6"
- wire width 2 $1\delay$next[1:0]$1872
- attribute \src "libresoc.v:47625.13-47625.25"
+ attribute \src "libresoc.v:49984.3-49993.6"
+ wire width 2 $1\delay$next[1:0]$1912
+ attribute \src "libresoc.v:48326.13-48326.25"
wire width 2 $1\delay[1:0]
- attribute \src "libresoc.v:48529.3-48538.6"
+ attribute \src "libresoc.v:49206.3-49215.6"
wire width 5 $1\dmi__addr[4:0]
- attribute \src "libresoc.v:48539.3-48548.6"
+ attribute \src "libresoc.v:49216.3-49225.6"
wire $1\dmi__ren[0:0]
- attribute \src "libresoc.v:48686.3-48713.6"
- wire width 2 $1\fsm_state$115$next[1:0]$1572
- attribute \src "libresoc.v:49261.3-49306.6"
- wire width 2 $1\fsm_state$next[1:0]$1865
- attribute \src "libresoc.v:47635.13-47635.29"
+ attribute \src "libresoc.v:49363.3-49390.6"
+ wire width 2 $1\fsm_state$115$next[1:0]$1612
+ attribute \src "libresoc.v:49938.3-49983.6"
+ wire width 2 $1\fsm_state$next[1:0]$1905
+ attribute \src "libresoc.v:48336.13-48336.29"
wire width 2 $1\fsm_state[1:0]
- attribute \src "libresoc.v:48578.3-48587.6"
+ attribute \src "libresoc.v:49255.3-49264.6"
wire width 8 $1\full_rd2__ren[7:0]
- attribute \src "libresoc.v:48617.3-48626.6"
+ attribute \src "libresoc.v:49294.3-49303.6"
wire width 3 $1\full_rd__ren[2:0]
- attribute \src "libresoc.v:49427.3-49450.6"
- wire width 32 $1\ilatch$next[31:0]$1900
- attribute \src "libresoc.v:47909.14-47909.28"
+ attribute \src "libresoc.v:50104.3-50127.6"
+ wire width 32 $1\ilatch$next[31:0]$1940
+ attribute \src "libresoc.v:48588.14-48588.28"
wire width 32 $1\ilatch[31:0]
- attribute \src "libresoc.v:49144.3-49159.6"
+ attribute \src "libresoc.v:49821.3-49836.6"
wire width 48 $1\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:49160.3-49184.6"
+ attribute \src "libresoc.v:49837.3-49861.6"
wire $1\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:49185.3-49209.6"
+ attribute \src "libresoc.v:49862.3-49886.6"
wire $1\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:48725.3-48739.6"
- wire width 3 $1\issue__addr$119[2:0]$1577
- attribute \src "libresoc.v:48656.3-48670.6"
+ attribute \src "libresoc.v:49402.3-49416.6"
+ wire width 3 $1\issue__addr$119[2:0]$1617
+ attribute \src "libresoc.v:49333.3-49347.6"
wire width 3 $1\issue__addr[2:0]
- attribute \src "libresoc.v:48755.3-48769.6"
+ attribute \src "libresoc.v:49432.3-49446.6"
wire width 64 $1\issue__data_i[63:0]
- attribute \src "libresoc.v:48671.3-48685.6"
+ attribute \src "libresoc.v:49348.3-49362.6"
wire $1\issue__ren[0:0]
- attribute \src "libresoc.v:48740.3-48754.6"
+ attribute \src "libresoc.v:49417.3-49431.6"
wire $1\issue__wen[0:0]
- attribute \src "libresoc.v:48518.3-48528.6"
+ attribute \src "libresoc.v:49195.3-49205.6"
wire $1\issue_i[0:0]
- attribute \src "libresoc.v:49451.3-49470.6"
+ attribute \src "libresoc.v:50128.3-50147.6"
wire $1\ivalid_i[0:0]
- attribute \src "libresoc.v:49043.3-49051.6"
- wire $1\jtag_dmi0_ack_o$next[0:0]$1830
- attribute \src "libresoc.v:47941.7-47941.29"
+ attribute \src "libresoc.v:49720.3-49728.6"
+ wire $1\jtag_dmi0_ack_o$next[0:0]$1870
+ attribute \src "libresoc.v:48624.7-48624.29"
wire $1\jtag_dmi0_ack_o[0:0]
- attribute \src "libresoc.v:49052.3-49060.6"
- wire width 64 $1\jtag_dmi0_dout$next[63:0]$1833
- attribute \src "libresoc.v:47949.14-47949.51"
+ attribute \src "libresoc.v:49729.3-49737.6"
+ wire width 64 $1\jtag_dmi0_dout$next[63:0]$1873
+ attribute \src "libresoc.v:48632.14-48632.51"
wire width 64 $1\jtag_dmi0_dout[63:0]
- attribute \src "libresoc.v:48886.3-48901.6"
+ attribute \src "libresoc.v:49563.3-49578.6"
wire width 4 $1\msr__ren[3:0]
- attribute \src "libresoc.v:49231.3-49260.6"
- wire $1\msr_read$next[0:0]$1859
- attribute \src "libresoc.v:47981.7-47981.22"
+ attribute \src "libresoc.v:49908.3-49937.6"
+ wire $1\msr_read$next[0:0]$1899
+ attribute \src "libresoc.v:48660.7-48660.22"
wire $1\msr_read[0:0]
- attribute \src "libresoc.v:48714.3-48724.6"
+ attribute \src "libresoc.v:49391.3-49401.6"
wire width 64 $1\new_dec[63:0]
- attribute \src "libresoc.v:48786.3-48796.6"
+ attribute \src "libresoc.v:49463.3-49473.6"
wire width 64 $1\new_tb[63:0]
- attribute \src "libresoc.v:48815.3-48830.6"
+ attribute \src "libresoc.v:49492.3-49507.6"
wire width 64 $1\pc[63:0]
- attribute \src "libresoc.v:48911.3-48935.6"
- wire $1\pc_changed$next[0:0]$1601
- attribute \src "libresoc.v:47993.7-47993.24"
+ attribute \src "libresoc.v:49588.3-49612.6"
+ wire $1\pc_changed$next[0:0]$1641
+ attribute \src "libresoc.v:48672.7-48672.24"
wire $1\pc_changed[0:0]
- attribute \src "libresoc.v:48806.3-48814.6"
- wire $1\pc_ok_delay$next[0:0]$1590
- attribute \src "libresoc.v:48003.7-48003.25"
+ attribute \src "libresoc.v:49483.3-49491.6"
+ wire $1\pc_ok_delay$next[0:0]$1630
+ attribute \src "libresoc.v:48682.7-48682.25"
wire $1\pc_ok_delay[0:0]
- attribute \src "libresoc.v:49070.3-49106.6"
- wire width 32 $1\raw_insn_i$next[31:0]$1839
- attribute \src "libresoc.v:48009.14-48009.32"
+ attribute \src "libresoc.v:49747.3-49783.6"
+ wire width 32 $1\raw_insn_i$next[31:0]$1879
+ attribute \src "libresoc.v:48688.14-48688.32"
wire width 32 $1\raw_insn_i[31:0]
- attribute \src "libresoc.v:48844.3-48864.6"
+ attribute \src "libresoc.v:49521.3-49541.6"
wire width 4 $1\wen[3:0]
- attribute \src "libresoc.v:49107.3-49143.6"
- wire $2\bigendian_i$next[0:0]$1846
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 8 $2\core_asmcode$next[7:0]$1707
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 64 $2\core_core_cia$next[63:0]$1708
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 8 $2\core_core_cr_rd$next[7:0]$1709
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_core_cr_rd_ok$next[0:0]$1710
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 8 $2\core_core_cr_wr$next[7:0]$1711
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_core_cr_wr_ok$next[0:0]$1712
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 12 $2\core_core_fn_unit$next[11:0]$1713
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 2 $2\core_core_input_carry$next[1:0]$1714
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 32 $2\core_core_insn$next[31:0]$1715
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 7 $2\core_core_insn_type$next[6:0]$1716
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_core_is_32bit$next[0:0]$1717
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_core_lk$next[0:0]$1718
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 64 $2\core_core_msr$next[63:0]$1719
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_core_oe$next[0:0]$1720
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_core_oe_ok$next[0:0]$1721
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_core_rc$next[0:0]$1722
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_core_rc_ok$next[0:0]$1723
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 13 $2\core_core_trapaddr$next[12:0]$1724
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 7 $2\core_core_traptype$next[6:0]$1725
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $2\core_cr_in1$next[2:0]$1726
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_cr_in1_ok$next[0:0]$1727
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $2\core_cr_in2$39$next[2:0]$1728
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $2\core_cr_in2$next[2:0]$1729
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_cr_in2_ok$40$next[0:0]$1730
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_cr_in2_ok$next[0:0]$1731
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $2\core_cr_out$next[2:0]$1732
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_cr_out_ok$next[0:0]$1733
- attribute \src "libresoc.v:49395.3-49426.6"
- wire width 64 $2\core_dec$next[63:0]$1890
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $2\core_ea$next[4:0]$1734
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_ea_ok$next[0:0]$1735
- attribute \src "libresoc.v:49395.3-49426.6"
- wire $2\core_eint$next[0:0]$1891
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $2\core_fast1$next[2:0]$1736
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_fast1_ok$next[0:0]$1737
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $2\core_fast2$next[2:0]$1738
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_fast2_ok$next[0:0]$1739
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $2\core_fasto1$next[2:0]$1740
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_fasto1_ok$next[0:0]$1741
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $2\core_fasto2$next[2:0]$1742
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_fasto2_ok$next[0:0]$1743
- attribute \src "libresoc.v:49395.3-49426.6"
- wire width 64 $2\core_msr$next[63:0]$1892
- attribute \src "libresoc.v:49395.3-49426.6"
- wire width 64 $2\core_pc$next[63:0]$1893
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $2\core_reg1$next[4:0]$1744
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_reg1_ok$next[0:0]$1745
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $2\core_reg2$next[4:0]$1746
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_reg2_ok$next[0:0]$1747
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $2\core_reg3$next[4:0]$1748
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_reg3_ok$next[0:0]$1749
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $2\core_rego$next[4:0]$1750
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_rego_ok$next[0:0]$1751
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 10 $2\core_spr1$next[9:0]$1752
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_spr1_ok$next[0:0]$1753
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 10 $2\core_spro$next[9:0]$1754
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_spro_ok$next[0:0]$1755
- attribute \src "libresoc.v:49317.3-49335.6"
+ attribute \src "libresoc.v:49784.3-49820.6"
+ wire $2\bigendian_i$next[0:0]$1886
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 8 $2\core_asmcode$next[7:0]$1747
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 64 $2\core_core_cia$next[63:0]$1748
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 8 $2\core_core_cr_rd$next[7:0]$1749
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_core_cr_rd_ok$next[0:0]$1750
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 8 $2\core_core_cr_wr$next[7:0]$1751
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_core_cr_wr_ok$next[0:0]$1752
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 12 $2\core_core_fn_unit$next[11:0]$1753
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 2 $2\core_core_input_carry$next[1:0]$1754
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 32 $2\core_core_insn$next[31:0]$1755
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 7 $2\core_core_insn_type$next[6:0]$1756
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_core_is_32bit$next[0:0]$1757
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_core_lk$next[0:0]$1758
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 64 $2\core_core_msr$next[63:0]$1759
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_core_oe$next[0:0]$1760
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_core_oe_ok$next[0:0]$1761
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_core_rc$next[0:0]$1762
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_core_rc_ok$next[0:0]$1763
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 13 $2\core_core_trapaddr$next[12:0]$1764
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 7 $2\core_core_traptype$next[6:0]$1765
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $2\core_cr_in1$next[2:0]$1766
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_cr_in1_ok$next[0:0]$1767
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $2\core_cr_in2$39$next[2:0]$1768
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $2\core_cr_in2$next[2:0]$1769
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_cr_in2_ok$40$next[0:0]$1770
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_cr_in2_ok$next[0:0]$1771
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $2\core_cr_out$next[2:0]$1772
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_cr_out_ok$next[0:0]$1773
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire width 64 $2\core_dec$next[63:0]$1930
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $2\core_ea$next[4:0]$1774
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_ea_ok$next[0:0]$1775
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire $2\core_eint$next[0:0]$1931
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $2\core_fast1$next[2:0]$1776
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_fast1_ok$next[0:0]$1777
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $2\core_fast2$next[2:0]$1778
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_fast2_ok$next[0:0]$1779
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $2\core_fasto1$next[2:0]$1780
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_fasto1_ok$next[0:0]$1781
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $2\core_fasto2$next[2:0]$1782
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_fasto2_ok$next[0:0]$1783
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire width 64 $2\core_msr$next[63:0]$1932
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire width 64 $2\core_pc$next[63:0]$1933
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $2\core_reg1$next[4:0]$1784
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_reg1_ok$next[0:0]$1785
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $2\core_reg2$next[4:0]$1786
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_reg2_ok$next[0:0]$1787
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $2\core_reg3$next[4:0]$1788
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_reg3_ok$next[0:0]$1789
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $2\core_rego$next[4:0]$1790
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_rego_ok$next[0:0]$1791
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 10 $2\core_spr1$next[9:0]$1792
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_spr1_ok$next[0:0]$1793
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 10 $2\core_spro$next[9:0]$1794
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_spro_ok$next[0:0]$1795
+ attribute \src "libresoc.v:49994.3-50012.6"
wire $2\core_stopped_i[0:0]
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $2\core_xer_in$next[2:0]$1756
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $2\core_xer_out$next[0:0]$1757
- attribute \src "libresoc.v:48865.3-48885.6"
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $2\core_xer_in$next[2:0]$1796
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $2\core_xer_out$next[0:0]$1797
+ attribute \src "libresoc.v:49542.3-49562.6"
wire width 64 $2\data_i[63:0]
- attribute \src "libresoc.v:49336.3-49354.6"
+ attribute \src "libresoc.v:50013.3-50031.6"
wire $2\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:48770.3-48785.6"
- wire width 64 $2\dec2_cur_dec$next[63:0]$1583
- attribute \src "libresoc.v:49355.3-49375.6"
- wire width 64 $2\dec2_cur_msr$next[63:0]$1878
- attribute \src "libresoc.v:49210.3-49230.6"
- wire width 64 $2\dec2_cur_pc$next[63:0]$1855
- attribute \src "libresoc.v:49376.3-49394.6"
+ attribute \src "libresoc.v:49447.3-49462.6"
+ wire width 64 $2\dec2_cur_dec$next[63:0]$1623
+ attribute \src "libresoc.v:50032.3-50052.6"
+ wire width 64 $2\dec2_cur_msr$next[63:0]$1918
+ attribute \src "libresoc.v:49887.3-49907.6"
+ wire width 64 $2\dec2_cur_pc$next[63:0]$1895
+ attribute \src "libresoc.v:50053.3-50071.6"
wire width 32 $2\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:48686.3-48713.6"
- wire width 2 $2\fsm_state$115$next[1:0]$1573
- attribute \src "libresoc.v:49261.3-49306.6"
- wire width 2 $2\fsm_state$next[1:0]$1866
- attribute \src "libresoc.v:49427.3-49450.6"
- wire width 32 $2\ilatch$next[31:0]$1901
- attribute \src "libresoc.v:49144.3-49159.6"
+ attribute \src "libresoc.v:49363.3-49390.6"
+ wire width 2 $2\fsm_state$115$next[1:0]$1613
+ attribute \src "libresoc.v:49938.3-49983.6"
+ wire width 2 $2\fsm_state$next[1:0]$1906
+ attribute \src "libresoc.v:50104.3-50127.6"
+ wire width 32 $2\ilatch$next[31:0]$1941
+ attribute \src "libresoc.v:49821.3-49836.6"
wire width 48 $2\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:49160.3-49184.6"
+ attribute \src "libresoc.v:49837.3-49861.6"
wire $2\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:49185.3-49209.6"
+ attribute \src "libresoc.v:49862.3-49886.6"
wire $2\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:49451.3-49470.6"
+ attribute \src "libresoc.v:50128.3-50147.6"
wire $2\ivalid_i[0:0]
- attribute \src "libresoc.v:48886.3-48901.6"
+ attribute \src "libresoc.v:49563.3-49578.6"
wire width 4 $2\msr__ren[3:0]
- attribute \src "libresoc.v:49231.3-49260.6"
- wire $2\msr_read$next[0:0]$1860
- attribute \src "libresoc.v:48815.3-48830.6"
+ attribute \src "libresoc.v:49908.3-49937.6"
+ wire $2\msr_read$next[0:0]$1900
+ attribute \src "libresoc.v:49492.3-49507.6"
wire width 64 $2\pc[63:0]
- attribute \src "libresoc.v:48911.3-48935.6"
- wire $2\pc_changed$next[0:0]$1602
- attribute \src "libresoc.v:49070.3-49106.6"
- wire width 32 $2\raw_insn_i$next[31:0]$1840
- attribute \src "libresoc.v:48844.3-48864.6"
+ attribute \src "libresoc.v:49588.3-49612.6"
+ wire $2\pc_changed$next[0:0]$1642
+ attribute \src "libresoc.v:49747.3-49783.6"
+ wire width 32 $2\raw_insn_i$next[31:0]$1880
+ attribute \src "libresoc.v:49521.3-49541.6"
wire width 4 $2\wen[3:0]
- attribute \src "libresoc.v:49107.3-49143.6"
- wire $3\bigendian_i$next[0:0]$1847
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 8 $3\core_asmcode$next[7:0]$1758
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 64 $3\core_core_cia$next[63:0]$1759
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 8 $3\core_core_cr_rd$next[7:0]$1760
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_core_cr_rd_ok$next[0:0]$1761
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 8 $3\core_core_cr_wr$next[7:0]$1762
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_core_cr_wr_ok$next[0:0]$1763
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 12 $3\core_core_fn_unit$next[11:0]$1764
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 2 $3\core_core_input_carry$next[1:0]$1765
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 32 $3\core_core_insn$next[31:0]$1766
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 7 $3\core_core_insn_type$next[6:0]$1767
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_core_is_32bit$next[0:0]$1768
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_core_lk$next[0:0]$1769
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 64 $3\core_core_msr$next[63:0]$1770
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_core_oe$next[0:0]$1771
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_core_oe_ok$next[0:0]$1772
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_core_rc$next[0:0]$1773
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_core_rc_ok$next[0:0]$1774
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 13 $3\core_core_trapaddr$next[12:0]$1775
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 7 $3\core_core_traptype$next[6:0]$1776
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $3\core_cr_in1$next[2:0]$1777
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_cr_in1_ok$next[0:0]$1778
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $3\core_cr_in2$39$next[2:0]$1779
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $3\core_cr_in2$next[2:0]$1780
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_cr_in2_ok$40$next[0:0]$1781
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_cr_in2_ok$next[0:0]$1782
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $3\core_cr_out$next[2:0]$1783
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_cr_out_ok$next[0:0]$1784
- attribute \src "libresoc.v:49395.3-49426.6"
- wire width 64 $3\core_dec$next[63:0]$1894
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $3\core_ea$next[4:0]$1785
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_ea_ok$next[0:0]$1786
- attribute \src "libresoc.v:49395.3-49426.6"
- wire $3\core_eint$next[0:0]$1895
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $3\core_fast1$next[2:0]$1787
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_fast1_ok$next[0:0]$1788
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $3\core_fast2$next[2:0]$1789
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_fast2_ok$next[0:0]$1790
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $3\core_fasto1$next[2:0]$1791
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_fasto1_ok$next[0:0]$1792
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $3\core_fasto2$next[2:0]$1793
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_fasto2_ok$next[0:0]$1794
- attribute \src "libresoc.v:49395.3-49426.6"
- wire width 64 $3\core_msr$next[63:0]$1896
- attribute \src "libresoc.v:49395.3-49426.6"
- wire width 64 $3\core_pc$next[63:0]$1897
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $3\core_reg1$next[4:0]$1795
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_reg1_ok$next[0:0]$1796
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $3\core_reg2$next[4:0]$1797
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_reg2_ok$next[0:0]$1798
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $3\core_reg3$next[4:0]$1799
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_reg3_ok$next[0:0]$1800
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 5 $3\core_rego$next[4:0]$1801
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_rego_ok$next[0:0]$1802
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 10 $3\core_spr1$next[9:0]$1803
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_spr1_ok$next[0:0]$1804
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 10 $3\core_spro$next[9:0]$1805
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_spro_ok$next[0:0]$1806
- attribute \src "libresoc.v:48936.3-49042.6"
- wire width 3 $3\core_xer_in$next[2:0]$1807
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $3\core_xer_out$next[0:0]$1808
- attribute \src "libresoc.v:48865.3-48885.6"
+ attribute \src "libresoc.v:49784.3-49820.6"
+ wire $3\bigendian_i$next[0:0]$1887
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 8 $3\core_asmcode$next[7:0]$1798
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 64 $3\core_core_cia$next[63:0]$1799
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 8 $3\core_core_cr_rd$next[7:0]$1800
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_core_cr_rd_ok$next[0:0]$1801
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 8 $3\core_core_cr_wr$next[7:0]$1802
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_core_cr_wr_ok$next[0:0]$1803
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 12 $3\core_core_fn_unit$next[11:0]$1804
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 2 $3\core_core_input_carry$next[1:0]$1805
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 32 $3\core_core_insn$next[31:0]$1806
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 7 $3\core_core_insn_type$next[6:0]$1807
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_core_is_32bit$next[0:0]$1808
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_core_lk$next[0:0]$1809
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 64 $3\core_core_msr$next[63:0]$1810
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_core_oe$next[0:0]$1811
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_core_oe_ok$next[0:0]$1812
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_core_rc$next[0:0]$1813
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_core_rc_ok$next[0:0]$1814
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 13 $3\core_core_trapaddr$next[12:0]$1815
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 7 $3\core_core_traptype$next[6:0]$1816
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $3\core_cr_in1$next[2:0]$1817
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_cr_in1_ok$next[0:0]$1818
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $3\core_cr_in2$39$next[2:0]$1819
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $3\core_cr_in2$next[2:0]$1820
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_cr_in2_ok$40$next[0:0]$1821
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_cr_in2_ok$next[0:0]$1822
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $3\core_cr_out$next[2:0]$1823
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_cr_out_ok$next[0:0]$1824
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire width 64 $3\core_dec$next[63:0]$1934
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $3\core_ea$next[4:0]$1825
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_ea_ok$next[0:0]$1826
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire $3\core_eint$next[0:0]$1935
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $3\core_fast1$next[2:0]$1827
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_fast1_ok$next[0:0]$1828
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $3\core_fast2$next[2:0]$1829
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_fast2_ok$next[0:0]$1830
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $3\core_fasto1$next[2:0]$1831
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_fasto1_ok$next[0:0]$1832
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $3\core_fasto2$next[2:0]$1833
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_fasto2_ok$next[0:0]$1834
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire width 64 $3\core_msr$next[63:0]$1936
+ attribute \src "libresoc.v:50072.3-50103.6"
+ wire width 64 $3\core_pc$next[63:0]$1937
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $3\core_reg1$next[4:0]$1835
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_reg1_ok$next[0:0]$1836
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $3\core_reg2$next[4:0]$1837
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_reg2_ok$next[0:0]$1838
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $3\core_reg3$next[4:0]$1839
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_reg3_ok$next[0:0]$1840
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 5 $3\core_rego$next[4:0]$1841
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_rego_ok$next[0:0]$1842
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 10 $3\core_spr1$next[9:0]$1843
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_spr1_ok$next[0:0]$1844
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 10 $3\core_spro$next[9:0]$1845
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_spro_ok$next[0:0]$1846
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire width 3 $3\core_xer_in$next[2:0]$1847
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $3\core_xer_out$next[0:0]$1848
+ attribute \src "libresoc.v:49542.3-49562.6"
wire width 64 $3\data_i[63:0]
- attribute \src "libresoc.v:49355.3-49375.6"
- wire width 64 $3\dec2_cur_msr$next[63:0]$1879
- attribute \src "libresoc.v:49210.3-49230.6"
- wire width 64 $3\dec2_cur_pc$next[63:0]$1856
- attribute \src "libresoc.v:49261.3-49306.6"
- wire width 2 $3\fsm_state$next[1:0]$1867
- attribute \src "libresoc.v:49427.3-49450.6"
- wire width 32 $3\ilatch$next[31:0]$1902
- attribute \src "libresoc.v:49160.3-49184.6"
+ attribute \src "libresoc.v:50032.3-50052.6"
+ wire width 64 $3\dec2_cur_msr$next[63:0]$1919
+ attribute \src "libresoc.v:49887.3-49907.6"
+ wire width 64 $3\dec2_cur_pc$next[63:0]$1896
+ attribute \src "libresoc.v:49938.3-49983.6"
+ wire width 2 $3\fsm_state$next[1:0]$1907
+ attribute \src "libresoc.v:50104.3-50127.6"
+ wire width 32 $3\ilatch$next[31:0]$1942
+ attribute \src "libresoc.v:49837.3-49861.6"
wire $3\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:49185.3-49209.6"
+ attribute \src "libresoc.v:49862.3-49886.6"
wire $3\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:49231.3-49260.6"
- wire $3\msr_read$next[0:0]$1861
- attribute \src "libresoc.v:48911.3-48935.6"
- wire $3\pc_changed$next[0:0]$1603
- attribute \src "libresoc.v:49070.3-49106.6"
- wire width 32 $3\raw_insn_i$next[31:0]$1841
- attribute \src "libresoc.v:48844.3-48864.6"
+ attribute \src "libresoc.v:49908.3-49937.6"
+ wire $3\msr_read$next[0:0]$1901
+ attribute \src "libresoc.v:49588.3-49612.6"
+ wire $3\pc_changed$next[0:0]$1643
+ attribute \src "libresoc.v:49747.3-49783.6"
+ wire width 32 $3\raw_insn_i$next[31:0]$1881
+ attribute \src "libresoc.v:49521.3-49541.6"
wire width 4 $3\wen[3:0]
- attribute \src "libresoc.v:49107.3-49143.6"
- wire $4\bigendian_i$next[0:0]$1848
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_core_cr_rd_ok$next[0:0]$1809
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_core_cr_wr_ok$next[0:0]$1810
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_core_oe_ok$next[0:0]$1811
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_core_rc_ok$next[0:0]$1812
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_cr_in1_ok$next[0:0]$1813
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_cr_in2_ok$40$next[0:0]$1814
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_cr_in2_ok$next[0:0]$1815
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_cr_out_ok$next[0:0]$1816
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_ea_ok$next[0:0]$1817
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_fast1_ok$next[0:0]$1818
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_fast2_ok$next[0:0]$1819
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_fasto1_ok$next[0:0]$1820
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_fasto2_ok$next[0:0]$1821
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_reg1_ok$next[0:0]$1822
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_reg2_ok$next[0:0]$1823
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_reg3_ok$next[0:0]$1824
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_rego_ok$next[0:0]$1825
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_spr1_ok$next[0:0]$1826
- attribute \src "libresoc.v:48936.3-49042.6"
- wire $4\core_spro_ok$next[0:0]$1827
- attribute \src "libresoc.v:49261.3-49306.6"
- wire width 2 $4\fsm_state$next[1:0]$1868
- attribute \src "libresoc.v:49231.3-49260.6"
- wire $4\msr_read$next[0:0]$1862
- attribute \src "libresoc.v:49070.3-49106.6"
- wire width 32 $4\raw_insn_i$next[31:0]$1842
- attribute \src "libresoc.v:49261.3-49306.6"
- wire width 2 $5\fsm_state$next[1:0]$1869
- attribute \src "libresoc.v:48046.19-48046.110"
- wire width 65 $add$libresoc.v:48046$1415_Y
- attribute \src "libresoc.v:48049.18-48049.107"
- wire width 65 $add$libresoc.v:48049$1418_Y
- attribute \src "libresoc.v:48048.18-48048.104"
- wire $and$libresoc.v:48048$1417_Y
- attribute \src "libresoc.v:48057.18-48057.101"
- wire $and$libresoc.v:48057$1426_Y
- attribute \src "libresoc.v:48058.18-48058.109"
- wire width 4 $and$libresoc.v:48058$1427_Y
- attribute \src "libresoc.v:48066.18-48066.101"
- wire $and$libresoc.v:48066$1435_Y
- attribute \src "libresoc.v:48069.18-48069.101"
- wire $and$libresoc.v:48069$1438_Y
- attribute \src "libresoc.v:48072.18-48072.101"
- wire $and$libresoc.v:48072$1441_Y
- attribute \src "libresoc.v:48076.18-48076.101"
- wire $and$libresoc.v:48076$1445_Y
- attribute \src "libresoc.v:48079.18-48079.101"
- wire $and$libresoc.v:48079$1448_Y
- attribute \src "libresoc.v:48083.18-48083.101"
- wire $and$libresoc.v:48083$1452_Y
- attribute \src "libresoc.v:48088.18-48088.101"
- wire $and$libresoc.v:48088$1457_Y
- attribute \src "libresoc.v:48091.18-48091.101"
- wire $and$libresoc.v:48091$1460_Y
- attribute \src "libresoc.v:48043.19-48043.109"
- wire width 64 $extend$libresoc.v:48043$1410_Y
- attribute \src "libresoc.v:48044.19-48044.108"
- wire width 64 $extend$libresoc.v:48044$1412_Y
- attribute \src "libresoc.v:48037.19-48037.111"
- wire width 7 $mul$libresoc.v:48037$1404_Y
- attribute \src "libresoc.v:48039.19-48039.111"
- wire width 7 $mul$libresoc.v:48039$1406_Y
- attribute \src "libresoc.v:48041.18-48041.101"
- wire $ne$libresoc.v:48041$1408_Y
- attribute \src "libresoc.v:48042.19-48042.118"
- wire $ne$libresoc.v:48042$1409_Y
- attribute \src "libresoc.v:48060.17-48060.101"
- wire $ne$libresoc.v:48060$1429_Y
- attribute \src "libresoc.v:48036.18-48036.99"
- wire $not$libresoc.v:48036$1403_Y
- attribute \src "libresoc.v:48047.18-48047.103"
- wire $not$libresoc.v:48047$1416_Y
- attribute \src "libresoc.v:48050.18-48050.98"
- wire $not$libresoc.v:48050$1419_Y
- attribute \src "libresoc.v:48051.18-48051.101"
- wire $not$libresoc.v:48051$1420_Y
- attribute \src "libresoc.v:48052.18-48052.101"
- wire $not$libresoc.v:48052$1421_Y
- attribute \src "libresoc.v:48053.18-48053.101"
- wire $not$libresoc.v:48053$1422_Y
- attribute \src "libresoc.v:48054.18-48054.101"
- wire $not$libresoc.v:48054$1423_Y
- attribute \src "libresoc.v:48055.18-48055.106"
- wire $not$libresoc.v:48055$1424_Y
- attribute \src "libresoc.v:48056.18-48056.103"
- wire $not$libresoc.v:48056$1425_Y
- attribute \src "libresoc.v:48061.18-48061.101"
- wire $not$libresoc.v:48061$1430_Y
- attribute \src "libresoc.v:48062.18-48062.101"
- wire $not$libresoc.v:48062$1431_Y
- attribute \src "libresoc.v:48063.18-48063.101"
- wire $not$libresoc.v:48063$1432_Y
- attribute \src "libresoc.v:48064.18-48064.106"
- wire $not$libresoc.v:48064$1433_Y
- attribute \src "libresoc.v:48065.18-48065.103"
- wire $not$libresoc.v:48065$1434_Y
- attribute \src "libresoc.v:48067.18-48067.106"
- wire $not$libresoc.v:48067$1436_Y
- attribute \src "libresoc.v:48068.18-48068.103"
- wire $not$libresoc.v:48068$1437_Y
- attribute \src "libresoc.v:48070.18-48070.106"
- wire $not$libresoc.v:48070$1439_Y
- attribute \src "libresoc.v:48071.18-48071.103"
- wire $not$libresoc.v:48071$1440_Y
- attribute \src "libresoc.v:48073.18-48073.106"
- wire $not$libresoc.v:48073$1442_Y
- attribute \src "libresoc.v:48074.18-48074.103"
- wire $not$libresoc.v:48074$1443_Y
- attribute \src "libresoc.v:48077.18-48077.106"
- wire $not$libresoc.v:48077$1446_Y
- attribute \src "libresoc.v:48078.18-48078.103"
- wire $not$libresoc.v:48078$1447_Y
- attribute \src "libresoc.v:48080.18-48080.99"
- wire $not$libresoc.v:48080$1449_Y
- attribute \src "libresoc.v:48081.18-48081.106"
- wire $not$libresoc.v:48081$1450_Y
- attribute \src "libresoc.v:48082.18-48082.103"
- wire $not$libresoc.v:48082$1451_Y
- attribute \src "libresoc.v:48084.18-48084.101"
- wire $not$libresoc.v:48084$1453_Y
- attribute \src "libresoc.v:48085.18-48085.106"
- wire $not$libresoc.v:48085$1454_Y
- attribute \src "libresoc.v:48087.18-48087.103"
- wire $not$libresoc.v:48087$1456_Y
- attribute \src "libresoc.v:48089.18-48089.106"
- wire $not$libresoc.v:48089$1458_Y
- attribute \src "libresoc.v:48090.18-48090.103"
- wire $not$libresoc.v:48090$1459_Y
- attribute \src "libresoc.v:48086.17-48086.109"
- wire $or$libresoc.v:48086$1455_Y
- attribute \src "libresoc.v:48043.19-48043.109"
- wire width 64 $pos$libresoc.v:48043$1411_Y
- attribute \src "libresoc.v:48044.19-48044.108"
- wire width 64 $pos$libresoc.v:48044$1413_Y
- attribute \src "libresoc.v:48059.18-48059.91"
- wire $reduce_or$libresoc.v:48059$1428_Y
- attribute \src "libresoc.v:48038.19-48038.42"
- wire width 64 $shr$libresoc.v:48038$1405_Y
- attribute \src "libresoc.v:48040.19-48040.42"
- wire width 64 $shr$libresoc.v:48040$1407_Y
- attribute \src "libresoc.v:48045.19-48045.110"
- wire width 65 $sub$libresoc.v:48045$1414_Y
- attribute \src "libresoc.v:48075.17-48075.100"
- wire width 3 $sub$libresoc.v:48075$1444_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161"
+ attribute \src "libresoc.v:49784.3-49820.6"
+ wire $4\bigendian_i$next[0:0]$1888
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_core_cr_rd_ok$next[0:0]$1849
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_core_cr_wr_ok$next[0:0]$1850
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_core_oe_ok$next[0:0]$1851
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_core_rc_ok$next[0:0]$1852
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_cr_in1_ok$next[0:0]$1853
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_cr_in2_ok$40$next[0:0]$1854
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_cr_in2_ok$next[0:0]$1855
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_cr_out_ok$next[0:0]$1856
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_ea_ok$next[0:0]$1857
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_fast1_ok$next[0:0]$1858
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_fast2_ok$next[0:0]$1859
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_fasto1_ok$next[0:0]$1860
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_fasto2_ok$next[0:0]$1861
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_reg1_ok$next[0:0]$1862
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_reg2_ok$next[0:0]$1863
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_reg3_ok$next[0:0]$1864
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_rego_ok$next[0:0]$1865
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_spr1_ok$next[0:0]$1866
+ attribute \src "libresoc.v:49613.3-49719.6"
+ wire $4\core_spro_ok$next[0:0]$1867
+ attribute \src "libresoc.v:49938.3-49983.6"
+ wire width 2 $4\fsm_state$next[1:0]$1908
+ attribute \src "libresoc.v:49908.3-49937.6"
+ wire $4\msr_read$next[0:0]$1902
+ attribute \src "libresoc.v:49747.3-49783.6"
+ wire width 32 $4\raw_insn_i$next[31:0]$1882
+ attribute \src "libresoc.v:49938.3-49983.6"
+ wire width 2 $5\fsm_state$next[1:0]$1909
+ attribute \src "libresoc.v:48723.19-48723.110"
+ wire width 65 $add$libresoc.v:48723$1455_Y
+ attribute \src "libresoc.v:48726.18-48726.107"
+ wire width 65 $add$libresoc.v:48726$1458_Y
+ attribute \src "libresoc.v:48725.18-48725.104"
+ wire $and$libresoc.v:48725$1457_Y
+ attribute \src "libresoc.v:48734.18-48734.101"
+ wire $and$libresoc.v:48734$1466_Y
+ attribute \src "libresoc.v:48735.18-48735.109"
+ wire width 4 $and$libresoc.v:48735$1467_Y
+ attribute \src "libresoc.v:48743.18-48743.101"
+ wire $and$libresoc.v:48743$1475_Y
+ attribute \src "libresoc.v:48746.18-48746.101"
+ wire $and$libresoc.v:48746$1478_Y
+ attribute \src "libresoc.v:48749.18-48749.101"
+ wire $and$libresoc.v:48749$1481_Y
+ attribute \src "libresoc.v:48753.18-48753.101"
+ wire $and$libresoc.v:48753$1485_Y
+ attribute \src "libresoc.v:48756.18-48756.101"
+ wire $and$libresoc.v:48756$1488_Y
+ attribute \src "libresoc.v:48760.18-48760.101"
+ wire $and$libresoc.v:48760$1492_Y
+ attribute \src "libresoc.v:48765.18-48765.101"
+ wire $and$libresoc.v:48765$1497_Y
+ attribute \src "libresoc.v:48768.18-48768.101"
+ wire $and$libresoc.v:48768$1500_Y
+ attribute \src "libresoc.v:48720.19-48720.109"
+ wire width 64 $extend$libresoc.v:48720$1450_Y
+ attribute \src "libresoc.v:48721.19-48721.108"
+ wire width 64 $extend$libresoc.v:48721$1452_Y
+ attribute \src "libresoc.v:48714.19-48714.111"
+ wire width 7 $mul$libresoc.v:48714$1444_Y
+ attribute \src "libresoc.v:48716.19-48716.111"
+ wire width 7 $mul$libresoc.v:48716$1446_Y
+ attribute \src "libresoc.v:48718.18-48718.101"
+ wire $ne$libresoc.v:48718$1448_Y
+ attribute \src "libresoc.v:48719.19-48719.118"
+ wire $ne$libresoc.v:48719$1449_Y
+ attribute \src "libresoc.v:48737.17-48737.101"
+ wire $ne$libresoc.v:48737$1469_Y
+ attribute \src "libresoc.v:48713.18-48713.99"
+ wire $not$libresoc.v:48713$1443_Y
+ attribute \src "libresoc.v:48724.18-48724.103"
+ wire $not$libresoc.v:48724$1456_Y
+ attribute \src "libresoc.v:48727.18-48727.98"
+ wire $not$libresoc.v:48727$1459_Y
+ attribute \src "libresoc.v:48728.18-48728.101"
+ wire $not$libresoc.v:48728$1460_Y
+ attribute \src "libresoc.v:48729.18-48729.101"
+ wire $not$libresoc.v:48729$1461_Y
+ attribute \src "libresoc.v:48730.18-48730.101"
+ wire $not$libresoc.v:48730$1462_Y
+ attribute \src "libresoc.v:48731.18-48731.101"
+ wire $not$libresoc.v:48731$1463_Y
+ attribute \src "libresoc.v:48732.18-48732.106"
+ wire $not$libresoc.v:48732$1464_Y
+ attribute \src "libresoc.v:48733.18-48733.103"
+ wire $not$libresoc.v:48733$1465_Y
+ attribute \src "libresoc.v:48738.18-48738.101"
+ wire $not$libresoc.v:48738$1470_Y
+ attribute \src "libresoc.v:48739.18-48739.101"
+ wire $not$libresoc.v:48739$1471_Y
+ attribute \src "libresoc.v:48740.18-48740.101"
+ wire $not$libresoc.v:48740$1472_Y
+ attribute \src "libresoc.v:48741.18-48741.106"
+ wire $not$libresoc.v:48741$1473_Y
+ attribute \src "libresoc.v:48742.18-48742.103"
+ wire $not$libresoc.v:48742$1474_Y
+ attribute \src "libresoc.v:48744.18-48744.106"
+ wire $not$libresoc.v:48744$1476_Y
+ attribute \src "libresoc.v:48745.18-48745.103"
+ wire $not$libresoc.v:48745$1477_Y
+ attribute \src "libresoc.v:48747.18-48747.106"
+ wire $not$libresoc.v:48747$1479_Y
+ attribute \src "libresoc.v:48748.18-48748.103"
+ wire $not$libresoc.v:48748$1480_Y
+ attribute \src "libresoc.v:48750.18-48750.106"
+ wire $not$libresoc.v:48750$1482_Y
+ attribute \src "libresoc.v:48751.18-48751.103"
+ wire $not$libresoc.v:48751$1483_Y
+ attribute \src "libresoc.v:48754.18-48754.106"
+ wire $not$libresoc.v:48754$1486_Y
+ attribute \src "libresoc.v:48755.18-48755.103"
+ wire $not$libresoc.v:48755$1487_Y
+ attribute \src "libresoc.v:48757.18-48757.99"
+ wire $not$libresoc.v:48757$1489_Y
+ attribute \src "libresoc.v:48758.18-48758.106"
+ wire $not$libresoc.v:48758$1490_Y
+ attribute \src "libresoc.v:48759.18-48759.103"
+ wire $not$libresoc.v:48759$1491_Y
+ attribute \src "libresoc.v:48761.18-48761.101"
+ wire $not$libresoc.v:48761$1493_Y
+ attribute \src "libresoc.v:48762.18-48762.106"
+ wire $not$libresoc.v:48762$1494_Y
+ attribute \src "libresoc.v:48764.18-48764.103"
+ wire $not$libresoc.v:48764$1496_Y
+ attribute \src "libresoc.v:48766.18-48766.106"
+ wire $not$libresoc.v:48766$1498_Y
+ attribute \src "libresoc.v:48767.18-48767.103"
+ wire $not$libresoc.v:48767$1499_Y
+ attribute \src "libresoc.v:48763.17-48763.109"
+ wire $or$libresoc.v:48763$1495_Y
+ attribute \src "libresoc.v:48720.19-48720.109"
+ wire width 64 $pos$libresoc.v:48720$1451_Y
+ attribute \src "libresoc.v:48721.19-48721.108"
+ wire width 64 $pos$libresoc.v:48721$1453_Y
+ attribute \src "libresoc.v:48736.18-48736.91"
+ wire $reduce_or$libresoc.v:48736$1468_Y
+ attribute \src "libresoc.v:48715.19-48715.42"
+ wire width 64 $shr$libresoc.v:48715$1445_Y
+ attribute \src "libresoc.v:48717.19-48717.42"
+ wire width 64 $shr$libresoc.v:48717$1447_Y
+ attribute \src "libresoc.v:48722.19-48722.110"
+ wire width 65 $sub$libresoc.v:48722$1454_Y
+ attribute \src "libresoc.v:48752.17-48752.100"
+ wire width 3 $sub$libresoc.v:48752$1484_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:163"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:268"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:270"
wire width 32 \$101
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
wire width 7 \$102
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:268"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:270"
wire width 32 \$105
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
wire width 7 \$106
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
wire \$109
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \$111
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \$113
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375"
wire width 65 \$116
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375"
wire width 65 \$117
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:389"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391"
wire width 65 \$120
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:389"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391"
wire width 65 \$121
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:181"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:183"
wire width 65 \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:181"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:183"
wire width 65 \$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:186"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:188"
wire \$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
wire \$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297"
wire \$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
wire \$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297"
wire \$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:156"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:158"
wire \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$33
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire \$35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
- wire width 4 \$36
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ wire width 4 \$36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
wire \$41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
wire \$43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
wire \$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:159"
wire width 3 \$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$53
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$57
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$59
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:159"
wire width 3 \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$61
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$63
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$65
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$67
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$69
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$71
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$73
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$75
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257"
wire \$77
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$79
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:163"
wire \$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$81
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$83
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
wire \$85
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$87
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$89
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$91
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$93
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$95
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
wire \$97
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257"
wire \$99
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39"
- wire input 11 \TAP_bus__tck
+ wire input 122 \TAP_bus__tck
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39"
- wire input 9 \TAP_bus__tdi
+ wire input 62 \TAP_bus__tdi
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39"
- wire output 8 \TAP_bus__tdo
+ wire output 113 \TAP_bus__tdo
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39"
- wire input 10 \TAP_bus__tms
+ wire input 123 \TAP_bus__tms
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94"
wire \bigendian_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94"
wire \bigendian_i$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:90"
- wire output 5 \busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:92"
+ wire output 140 \busy_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \cia__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \cia__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151"
- wire input 6 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92"
wire width 8 \core_asmcode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92"
wire width 8 \core_asmcode$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:89"
- wire input 4 \core_bigendian_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:91"
+ wire input 1 \core_bigendian_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
wire width 64 \core_core_cia
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
wire \core_xer_out$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99"
wire \corebusy_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:154"
wire \coresync_clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire \cu_ad__go_i
wire \cu_st__rel_o_dly$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
wire \cu_st__rel_o_rise
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325"
wire \d_cr_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325"
wire \d_cr_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
wire \d_reg_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
wire \d_reg_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335"
wire \d_xer_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335"
wire \d_xer_delay$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \data_i
wire \dbg_dmi_we_i$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102"
wire \dbg_terminate_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire input 138 \dbus__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire width 45 input 132 \dbus__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire width 2 input 141 \dbus__bte
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire width 3 input 140 \dbus__cti
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire input 136 \dbus__cyc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire width 64 input 134 \dbus__dat_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire width 64 input 133 \dbus__dat_w
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire input 142 \dbus__err
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire width 8 input 135 \dbus__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire input 137 \dbus__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire input 139 \dbus__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92"
wire width 8 \dec2_asmcode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443"
wire width 3 \dec2_xer_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103"
wire \dec2_xer_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:155"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157"
wire width 2 \delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:155"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157"
wire width 2 \delay$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 5 \dmi__addr
wire width 64 \dmi__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire \dmi__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
wire width 2 \fsm_state
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363"
wire width 2 \fsm_state$115
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363"
wire width 2 \fsm_state$115$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
wire width 2 \fsm_state$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 \full_rd2__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 \full_rd__ren
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 25 \gpio_gpio0__core__i
+ wire output 65 \gpio_gpio0__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 26 \gpio_gpio0__core__o
+ wire input 15 \gpio_gpio0__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 27 \gpio_gpio0__core__oe
+ wire input 16 \gpio_gpio0__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 28 \gpio_gpio0__pad__i
+ wire input 14 \gpio_gpio0__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 29 \gpio_gpio0__pad__o
+ wire output 66 \gpio_gpio0__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 30 \gpio_gpio0__pad__oe
+ wire output 67 \gpio_gpio0__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 85 \gpio_gpio10__core__i
+ wire output 95 \gpio_gpio10__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 86 \gpio_gpio10__core__o
+ wire input 45 \gpio_gpio10__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 87 \gpio_gpio10__core__oe
+ wire input 46 \gpio_gpio10__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 88 \gpio_gpio10__pad__i
+ wire input 44 \gpio_gpio10__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 89 \gpio_gpio10__pad__o
+ wire output 96 \gpio_gpio10__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 90 \gpio_gpio10__pad__oe
+ wire output 97 \gpio_gpio10__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 91 \gpio_gpio11__core__i
+ wire output 98 \gpio_gpio11__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 92 \gpio_gpio11__core__o
+ wire input 48 \gpio_gpio11__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 93 \gpio_gpio11__core__oe
+ wire input 49 \gpio_gpio11__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 94 \gpio_gpio11__pad__i
+ wire input 47 \gpio_gpio11__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 95 \gpio_gpio11__pad__o
+ wire output 99 \gpio_gpio11__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 96 \gpio_gpio11__pad__oe
+ wire output 100 \gpio_gpio11__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 97 \gpio_gpio12__core__i
+ wire output 101 \gpio_gpio12__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 98 \gpio_gpio12__core__o
+ wire input 51 \gpio_gpio12__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 99 \gpio_gpio12__core__oe
+ wire input 52 \gpio_gpio12__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 100 \gpio_gpio12__pad__i
+ wire input 50 \gpio_gpio12__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 101 \gpio_gpio12__pad__o
+ wire output 102 \gpio_gpio12__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 102 \gpio_gpio12__pad__oe
+ wire output 103 \gpio_gpio12__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 103 \gpio_gpio13__core__i
+ wire output 104 \gpio_gpio13__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 104 \gpio_gpio13__core__o
+ wire input 54 \gpio_gpio13__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 105 \gpio_gpio13__core__oe
+ wire input 55 \gpio_gpio13__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 106 \gpio_gpio13__pad__i
+ wire input 53 \gpio_gpio13__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 107 \gpio_gpio13__pad__o
+ wire output 105 \gpio_gpio13__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 108 \gpio_gpio13__pad__oe
+ wire output 106 \gpio_gpio13__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 109 \gpio_gpio14__core__i
+ wire output 107 \gpio_gpio14__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 110 \gpio_gpio14__core__o
+ wire input 57 \gpio_gpio14__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 111 \gpio_gpio14__core__oe
+ wire input 58 \gpio_gpio14__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 112 \gpio_gpio14__pad__i
+ wire input 56 \gpio_gpio14__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 113 \gpio_gpio14__pad__o
+ wire output 108 \gpio_gpio14__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 114 \gpio_gpio14__pad__oe
+ wire output 109 \gpio_gpio14__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 115 \gpio_gpio15__core__i
+ wire output 110 \gpio_gpio15__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 116 \gpio_gpio15__core__o
+ wire input 60 \gpio_gpio15__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 117 \gpio_gpio15__core__oe
+ wire input 61 \gpio_gpio15__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 118 \gpio_gpio15__pad__i
+ wire input 59 \gpio_gpio15__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 119 \gpio_gpio15__pad__o
+ wire output 111 \gpio_gpio15__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 120 \gpio_gpio15__pad__oe
+ wire output 112 \gpio_gpio15__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 31 \gpio_gpio1__core__i
+ wire output 68 \gpio_gpio1__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 32 \gpio_gpio1__core__o
+ wire input 18 \gpio_gpio1__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 33 \gpio_gpio1__core__oe
+ wire input 19 \gpio_gpio1__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 34 \gpio_gpio1__pad__i
+ wire input 17 \gpio_gpio1__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 35 \gpio_gpio1__pad__o
+ wire output 69 \gpio_gpio1__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 36 \gpio_gpio1__pad__oe
+ wire output 70 \gpio_gpio1__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 37 \gpio_gpio2__core__i
+ wire output 71 \gpio_gpio2__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 38 \gpio_gpio2__core__o
+ wire input 21 \gpio_gpio2__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 39 \gpio_gpio2__core__oe
+ wire input 22 \gpio_gpio2__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 40 \gpio_gpio2__pad__i
+ wire input 20 \gpio_gpio2__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 41 \gpio_gpio2__pad__o
+ wire output 72 \gpio_gpio2__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 42 \gpio_gpio2__pad__oe
+ wire output 73 \gpio_gpio2__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 43 \gpio_gpio3__core__i
+ wire output 74 \gpio_gpio3__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 44 \gpio_gpio3__core__o
+ wire input 24 \gpio_gpio3__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 45 \gpio_gpio3__core__oe
+ wire input 25 \gpio_gpio3__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 46 \gpio_gpio3__pad__i
+ wire input 23 \gpio_gpio3__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 47 \gpio_gpio3__pad__o
+ wire output 75 \gpio_gpio3__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 48 \gpio_gpio3__pad__oe
+ wire output 76 \gpio_gpio3__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 49 \gpio_gpio4__core__i
+ wire output 77 \gpio_gpio4__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 50 \gpio_gpio4__core__o
+ wire input 27 \gpio_gpio4__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 51 \gpio_gpio4__core__oe
+ wire input 28 \gpio_gpio4__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 52 \gpio_gpio4__pad__i
+ wire input 26 \gpio_gpio4__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 53 \gpio_gpio4__pad__o
+ wire output 78 \gpio_gpio4__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 54 \gpio_gpio4__pad__oe
+ wire output 79 \gpio_gpio4__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 55 \gpio_gpio5__core__i
+ wire output 80 \gpio_gpio5__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 56 \gpio_gpio5__core__o
+ wire input 30 \gpio_gpio5__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 57 \gpio_gpio5__core__oe
+ wire input 31 \gpio_gpio5__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 58 \gpio_gpio5__pad__i
+ wire input 29 \gpio_gpio5__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 59 \gpio_gpio5__pad__o
+ wire output 81 \gpio_gpio5__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 60 \gpio_gpio5__pad__oe
+ wire output 82 \gpio_gpio5__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 61 \gpio_gpio6__core__i
+ wire output 83 \gpio_gpio6__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 62 \gpio_gpio6__core__o
+ wire input 33 \gpio_gpio6__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 63 \gpio_gpio6__core__oe
+ wire input 34 \gpio_gpio6__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 64 \gpio_gpio6__pad__i
+ wire input 32 \gpio_gpio6__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 65 \gpio_gpio6__pad__o
+ wire output 84 \gpio_gpio6__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 66 \gpio_gpio6__pad__oe
+ wire output 85 \gpio_gpio6__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 67 \gpio_gpio7__core__i
+ wire output 86 \gpio_gpio7__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 68 \gpio_gpio7__core__o
+ wire input 36 \gpio_gpio7__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 69 \gpio_gpio7__core__oe
+ wire input 37 \gpio_gpio7__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 70 \gpio_gpio7__pad__i
+ wire input 35 \gpio_gpio7__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 71 \gpio_gpio7__pad__o
+ wire output 87 \gpio_gpio7__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 72 \gpio_gpio7__pad__oe
+ wire output 88 \gpio_gpio7__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 73 \gpio_gpio8__core__i
+ wire output 89 \gpio_gpio8__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 74 \gpio_gpio8__core__o
+ wire input 39 \gpio_gpio8__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 75 \gpio_gpio8__core__oe
+ wire input 40 \gpio_gpio8__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 76 \gpio_gpio8__pad__i
+ wire input 38 \gpio_gpio8__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 77 \gpio_gpio8__pad__o
+ wire output 90 \gpio_gpio8__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 78 \gpio_gpio8__pad__oe
+ wire output 91 \gpio_gpio8__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 79 \gpio_gpio9__core__i
+ wire output 92 \gpio_gpio9__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 80 \gpio_gpio9__core__o
+ wire input 42 \gpio_gpio9__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 81 \gpio_gpio9__core__oe
+ wire input 43 \gpio_gpio9__core__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 82 \gpio_gpio9__pad__i
+ wire input 41 \gpio_gpio9__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 83 \gpio_gpio9__pad__o
+ wire output 93 \gpio_gpio9__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 84 \gpio_gpio9__pad__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire input 127 \ibus__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire width 45 output 121 \ibus__adr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire width 2 input 130 \ibus__bte
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire width 3 input 129 \ibus__cti
+ wire output 94 \gpio_gpio9__pad__oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire output 125 \ibus__cyc
+ wire input 6 \ibus__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire width 64 input 123 \ibus__dat_r
+ wire width 45 output 11 \ibus__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire width 64 input 122 \ibus__dat_w
+ wire output 5 \ibus__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire input 131 \ibus__err
+ wire width 64 input 10 \ibus__dat_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire width 8 output 124 \ibus__sel
+ wire input 7 \ibus__err
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire output 126 \ibus__stb
+ wire width 8 output 9 \ibus__sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
- wire input 128 \ibus__we
+ wire output 8 \ibus__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire output 149 \icp_wb__ack
+ wire output 124 \icp_wb__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 28 input 143 \icp_wb__adr
+ wire width 28 input 130 \icp_wb__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 2 input 152 \icp_wb__bte
+ wire input 125 \icp_wb__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 3 input 151 \icp_wb__cti
+ wire width 32 output 126 \icp_wb__dat_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire input 147 \icp_wb__cyc
+ wire width 32 input 127 \icp_wb__dat_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 32 output 145 \icp_wb__dat_r
+ wire width 4 input 131 \icp_wb__sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 32 input 144 \icp_wb__dat_w
+ wire input 128 \icp_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire input 153 \icp_wb__err
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire width 4 input 146 \icp_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire input 148 \icp_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
- wire input 150 \icp_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire output 160 \ics_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 28 input 154 \ics_wb__adr
+ wire input 129 \icp_wb__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 2 input 163 \ics_wb__bte
+ wire output 137 \ics_wb__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 3 input 162 \ics_wb__cti
+ wire width 28 input 132 \ics_wb__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 158 \ics_wb__cyc
+ wire input 134 \ics_wb__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 32 output 156 \ics_wb__dat_r
+ wire width 32 output 136 \ics_wb__dat_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 32 input 155 \ics_wb__dat_w
+ wire width 32 input 138 \ics_wb__dat_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 164 \ics_wb__err
+ wire input 135 \ics_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire width 4 input 157 \ics_wb__sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 159 \ics_wb__stb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
- wire input 161 \ics_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
+ wire input 139 \ics_wb__we
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179"
wire width 32 \ilatch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179"
wire width 32 \ilatch$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
wire width 48 \imem_a_pc_i
wire width 64 \imem_f_instr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
wire \imem_f_valid_i
- attribute \src "libresoc.v:46401.7-46401.15"
+ attribute \src "libresoc.v:47126.7-47126.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
- wire width 16 input 165 \int_level_i
+ wire width 16 input 133 \int_level_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153"
+ wire \intclk_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153"
+ wire \intclk_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 \issue__addr
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61"
wire \jtag_dmi0_we_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
- wire input 19 \jtag_wb__ack
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
- wire width 29 output 12 \jtag_wb__adr
+ wire input 120 \jtag_wb__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
- wire output 16 \jtag_wb__cyc
+ wire width 29 output 114 \jtag_wb__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
- wire width 64 input 14 \jtag_wb__dat_r
+ wire output 116 \jtag_wb__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
- wire width 64 output 13 \jtag_wb__dat_w
+ wire width 64 input 121 \jtag_wb__dat_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
- wire input 20 \jtag_wb__err
+ wire width 64 output 119 \jtag_wb__dat_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
- wire output 15 \jtag_wb__sel
+ wire output 115 \jtag_wb__sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
- wire output 17 \jtag_wb__stb
+ wire output 117 \jtag_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89"
- wire output 18 \jtag_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:91"
- wire input 3 \memerr_o
+ wire output 118 \jtag_wb__we
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \msr__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \msr__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205"
wire \msr_read
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205"
wire \msr_read$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:371"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373"
wire width 64 \new_dec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390"
wire width 64 \new_tb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:182"
wire width 64 \nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:184"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:186"
wire width 64 \pc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
wire \pc_changed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
wire \pc_changed$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
- wire width 64 input 166 \pc_i
+ wire width 64 input 4 \pc_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
- wire input 1 \pc_i_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:87"
+ wire input 3 \pc_i_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:89"
wire width 64 output 2 \pc_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187"
wire \pc_ok_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187"
wire \pc_ok_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152"
wire \por_clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93"
wire width 32 \raw_insn_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93"
wire width 32 \raw_insn_i$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151"
- wire input 7 \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \state_nia_wen
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 23 \uart_rx__core__i
+ wire output 64 \uart_rx__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 24 \uart_rx__pad__i
+ wire input 13 \uart_rx__pad__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire input 21 \uart_tx__core__o
+ wire input 12 \uart_tx__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48"
- wire output 22 \uart_tx__pad__o
+ wire output 63 \uart_tx__pad__o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \wen
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
wire width 8 \xics_ics_icp_o_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
wire width 4 \xics_ics_icp_o_src
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:389"
- cell $add $add$libresoc.v:48046$1415
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391"
+ cell $add $add$libresoc.v:48723$1455
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \issue__data_o
connect \B 1'1
- connect \Y $add$libresoc.v:48046$1415_Y
+ connect \Y $add$libresoc.v:48723$1455_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:181"
- cell $add $add$libresoc.v:48049$1418
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:183"
+ cell $add $add$libresoc.v:48726$1458
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \dec2_cur_pc
connect \B 3'100
- connect \Y $add$libresoc.v:48049$1418_Y
+ connect \Y $add$libresoc.v:48726$1458_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $and$libresoc.v:48048$1417
+ cell $and $and$libresoc.v:48725$1457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_st__rel_o
connect \B \$12
- connect \Y $and$libresoc.v:48048$1417_Y
+ connect \Y $and$libresoc.v:48725$1457_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
- cell $and $and$libresoc.v:48057$1426
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
+ cell $and $and$libresoc.v:48734$1466
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$29
connect \B \$31
- connect \Y $and$libresoc.v:48057$1426_Y
+ connect \Y $and$libresoc.v:48734$1466_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
- cell $and $and$libresoc.v:48058$1427
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ cell $and $and$libresoc.v:48735$1467
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \state_nia_wen
connect \B 1'1
- connect \Y $and$libresoc.v:48058$1427_Y
+ connect \Y $and$libresoc.v:48735$1467_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
- cell $and $and$libresoc.v:48066$1435
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
+ cell $and $and$libresoc.v:48743$1475
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$47
connect \B \$49
- connect \Y $and$libresoc.v:48066$1435_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$53
connect \B \$55
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$59
connect \B \$61
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$65
connect \B \$67
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$71
connect \B \$73
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$79
connect \B \$81
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$87
connect \B \$89
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$93
connect \B \$95
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
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parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \full_rd2__data_o
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
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parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \full_rd__data_o
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end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $mul$libresoc.v:48037$1404
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A \dec2_cur_pc [2]
connect \B 6'100000
- connect \Y $mul$libresoc.v:48037$1404_Y
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end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $mul$libresoc.v:48039$1406
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A \dec2_cur_pc [2]
connect \B 6'100000
- connect \Y $mul$libresoc.v:48039$1406_Y
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:163"
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parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \delay
connect \B \$8
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
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parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_insn_type
connect \B 7'0000001
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:156"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:158"
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parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \delay
connect \B 1'0
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msr_read
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end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \cu_st__rel_o_dly
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:186"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:188"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_i_ok
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_changed
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_changed
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_reset_i
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_reset_i
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_reset_i
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
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connect \A \core_reset_i
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_reset_i
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_reset_i
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msr_read
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
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parameter \Y_WIDTH 1
connect \A \core_reset_i
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
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end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
parameter \A_WIDTH 1
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connect \A \core_reset_i
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
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parameter \A_SIGNED 0
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connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:48089$1458_Y
+ connect \Y $not$libresoc.v:48766$1498_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
- cell $not $not$libresoc.v:48090$1459
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
+ cell $not $not$libresoc.v:48767$1499
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_reset_i
- connect \Y $not$libresoc.v:48090$1459_Y
+ connect \Y $not$libresoc.v:48767$1499_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161"
- cell $or $or$libresoc.v:48086$1455
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:163"
+ cell $or $or$libresoc.v:48763$1495
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A 1'0
connect \B \dbg_core_rst_o
- connect \Y $or$libresoc.v:48086$1455_Y
+ connect \Y $or$libresoc.v:48763$1495_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- cell $pos $pos$libresoc.v:48043$1411
+ cell $pos $pos$libresoc.v:48720$1451
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:48043$1410_Y
- connect \Y $pos$libresoc.v:48043$1411_Y
+ connect \A $extend$libresoc.v:48720$1450_Y
+ connect \Y $pos$libresoc.v:48720$1451_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- cell $pos $pos$libresoc.v:48044$1413
+ cell $pos $pos$libresoc.v:48721$1453
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:48044$1412_Y
- connect \Y $pos$libresoc.v:48044$1413_Y
+ connect \A $extend$libresoc.v:48721$1452_Y
+ connect \Y $pos$libresoc.v:48721$1453_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:48059$1428
+ cell $reduce_or $reduce_or$libresoc.v:48736$1468
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \$36
- connect \Y $reduce_or$libresoc.v:48059$1428_Y
+ connect \Y $reduce_or$libresoc.v:48736$1468_Y
end
- attribute \src "libresoc.v:48038.19-48038.42"
- cell $shr $shr$libresoc.v:48038$1405
+ attribute \src "libresoc.v:48715.19-48715.42"
+ cell $shr $shr$libresoc.v:48715$1445
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \imem_f_instr_o
connect \B \$102
- connect \Y $shr$libresoc.v:48038$1405_Y
+ connect \Y $shr$libresoc.v:48715$1445_Y
end
- attribute \src "libresoc.v:48040.19-48040.42"
- cell $shr $shr$libresoc.v:48040$1407
+ attribute \src "libresoc.v:48717.19-48717.42"
+ cell $shr $shr$libresoc.v:48717$1447
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \imem_f_instr_o
connect \B \$106
- connect \Y $shr$libresoc.v:48040$1407_Y
+ connect \Y $shr$libresoc.v:48717$1447_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373"
- cell $sub $sub$libresoc.v:48045$1414
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375"
+ cell $sub $sub$libresoc.v:48722$1454
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \issue__data_o
connect \B 1'1
- connect \Y $sub$libresoc.v:48045$1414_Y
+ connect \Y $sub$libresoc.v:48722$1454_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157"
- cell $sub $sub$libresoc.v:48075$1444
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:159"
+ cell $sub $sub$libresoc.v:48752$1484
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \delay
connect \B 1'1
- connect \Y $sub$libresoc.v:48075$1444_Y
+ connect \Y $sub$libresoc.v:48752$1484_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:48248.7-48273.4"
+ attribute \src "libresoc.v:48925.7-48950.4"
cell \dbg \dbg
- connect \clk \clk
connect \core_dbg_msr \dbg_core_dbg_msr
connect \core_dbg_pc \dbg_core_dbg_pc
connect \core_rst_o \dbg_core_rst_o
connect \dmi_dout \dbg_dmi_dout
connect \dmi_req_i \dbg_dmi_req_i
connect \dmi_we_i \dbg_dmi_we_i
- connect \rst \rst
+ connect \intclk_clk \intclk_clk
+ connect \intclk_rst \intclk_rst
connect \terminate_i \dbg_terminate_i
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:48274.8-48332.4"
+ attribute \src "libresoc.v:48951.8-49009.4"
cell \dec2 \dec2
connect \asmcode \dec2_asmcode
connect \bigendian \dec2_bigendian
connect \xer_out \dec2_xer_out
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:48333.8-48348.4"
+ attribute \src "libresoc.v:49010.8-49025.4"
cell \imem \imem
connect \a_pc_i \imem_a_pc_i
connect \a_valid_i \imem_a_valid_i
- connect \clk \clk
connect \f_busy_o \imem_f_busy_o
connect \f_instr_o \imem_f_instr_o
connect \f_valid_i \imem_f_valid_i
connect \ibus__err \ibus__err
connect \ibus__sel \ibus__sel
connect \ibus__stb \ibus__stb
- connect \rst \rst
+ connect \intclk_clk \intclk_clk
+ connect \intclk_rst \intclk_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:48349.8-48470.4"
+ attribute \src "libresoc.v:49026.8-49147.4"
cell \jtag \jtag
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tdi \TAP_bus__tdi
connect \TAP_bus__tdo \TAP_bus__tdo
connect \TAP_bus__tms \TAP_bus__tms
- connect \clk \clk
connect \dmi0_ack_o \jtag_dmi0_ack_o
connect \dmi0_addr_i \jtag_dmi0_addr_i
connect \dmi0_din \jtag_dmi0_din
connect \gpio_gpio9__pad__i \gpio_gpio9__pad__i
connect \gpio_gpio9__pad__o \gpio_gpio9__pad__o
connect \gpio_gpio9__pad__oe \gpio_gpio9__pad__oe
+ connect \intclk_clk \intclk_clk
+ connect \intclk_rst \intclk_rst
connect \jtag_wb__ack \jtag_wb__ack
connect \jtag_wb__adr \jtag_wb__adr
connect \jtag_wb__cyc \jtag_wb__cyc
connect \jtag_wb__sel \jtag_wb__sel
connect \jtag_wb__stb \jtag_wb__stb
connect \jtag_wb__we \jtag_wb__we
- connect \rst \rst
connect \uart_rx__core__i \uart_rx__core__i
connect \uart_rx__pad__i \uart_rx__pad__i
connect \uart_tx__core__o \uart_tx__core__o
connect \uart_tx__pad__o \uart_tx__pad__o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:48471.12-48485.4"
+ attribute \src "libresoc.v:49148.12-49162.4"
cell \xics_icp \xics_icp
- connect \clk \clk
connect \core_irq_o \xics_icp_core_irq_o
connect \icp_wb__ack \icp_wb__ack
connect \icp_wb__adr \icp_wb__adr
connect \icp_wb__we \icp_wb__we
connect \ics_i_pri \xics_icp_ics_i_pri
connect \ics_i_src \xics_icp_ics_i_src
- connect \rst \rst
+ connect \intclk_clk \intclk_clk
+ connect \intclk_rst \intclk_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:48486.12-48499.4"
+ attribute \src "libresoc.v:49163.12-49176.4"
cell \xics_ics \xics_ics
- connect \clk \clk
connect \icp_o_pri \xics_ics_icp_o_pri
connect \icp_o_src \xics_ics_icp_o_src
connect \ics_wb__ack \ics_wb__ack
connect \ics_wb__stb \ics_wb__stb
connect \ics_wb__we \ics_wb__we
connect \int_level_i \int_level_i
- connect \rst \rst
+ connect \intclk_clk \intclk_clk
+ connect \intclk_rst \intclk_rst
end
- attribute \src "libresoc.v:46401.7-46401.20"
- process $proc$libresoc.v:46401$1904
+ attribute \src "libresoc.v:47126.7-47126.20"
+ process $proc$libresoc.v:47126$1944
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:46531.7-46531.25"
- process $proc$libresoc.v:46531$1905
+ attribute \src "libresoc.v:47256.7-47256.25"
+ process $proc$libresoc.v:47256$1945
assign { } { }
assign $1\bigendian_i[0:0] 1'0
sync always
sync init
update \bigendian_i $1\bigendian_i[0:0]
end
- attribute \src "libresoc.v:46543.13-46543.33"
- process $proc$libresoc.v:46543$1906
+ attribute \src "libresoc.v:47266.13-47266.33"
+ process $proc$libresoc.v:47266$1946
assign { } { }
assign $1\core_asmcode[7:0] 8'00000000
sync always
sync init
update \core_asmcode $1\core_asmcode[7:0]
end
- attribute \src "libresoc.v:46549.14-46549.50"
- process $proc$libresoc.v:46549$1907
+ attribute \src "libresoc.v:47272.14-47272.50"
+ process $proc$libresoc.v:47272$1947
assign { } { }
assign $1\core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_cia $1\core_core_cia[63:0]
end
- attribute \src "libresoc.v:46553.13-46553.36"
- process $proc$libresoc.v:46553$1908
+ attribute \src "libresoc.v:47276.13-47276.36"
+ process $proc$libresoc.v:47276$1948
assign { } { }
assign $1\core_core_cr_rd[7:0] 8'00000000
sync always
sync init
update \core_core_cr_rd $1\core_core_cr_rd[7:0]
end
- attribute \src "libresoc.v:46557.7-46557.32"
- process $proc$libresoc.v:46557$1909
+ attribute \src "libresoc.v:47280.7-47280.32"
+ process $proc$libresoc.v:47280$1949
assign { } { }
assign $1\core_core_cr_rd_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_rd_ok $1\core_core_cr_rd_ok[0:0]
end
- attribute \src "libresoc.v:46561.13-46561.36"
- process $proc$libresoc.v:46561$1910
+ attribute \src "libresoc.v:47284.13-47284.36"
+ process $proc$libresoc.v:47284$1950
assign { } { }
assign $1\core_core_cr_wr[7:0] 8'00000000
sync always
sync init
update \core_core_cr_wr $1\core_core_cr_wr[7:0]
end
- attribute \src "libresoc.v:46565.7-46565.32"
- process $proc$libresoc.v:46565$1911
+ attribute \src "libresoc.v:47288.7-47288.32"
+ process $proc$libresoc.v:47288$1951
assign { } { }
assign $1\core_core_cr_wr_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0]
end
- attribute \src "libresoc.v:46582.14-46582.41"
- process $proc$libresoc.v:46582$1912
+ attribute \src "libresoc.v:47305.14-47305.41"
+ process $proc$libresoc.v:47305$1952
assign { } { }
assign $1\core_core_fn_unit[11:0] 12'000000000000
sync always
sync init
update \core_core_fn_unit $1\core_core_fn_unit[11:0]
end
- attribute \src "libresoc.v:46590.13-46590.41"
- process $proc$libresoc.v:46590$1913
+ attribute \src "libresoc.v:47313.13-47313.41"
+ process $proc$libresoc.v:47313$1953
assign { } { }
assign $1\core_core_input_carry[1:0] 2'00
sync always
sync init
update \core_core_input_carry $1\core_core_input_carry[1:0]
end
- attribute \src "libresoc.v:46594.14-46594.36"
- process $proc$libresoc.v:46594$1914
+ attribute \src "libresoc.v:47317.14-47317.36"
+ process $proc$libresoc.v:47317$1954
assign { } { }
assign $1\core_core_insn[31:0] 0
sync always
sync init
update \core_core_insn $1\core_core_insn[31:0]
end
- attribute \src "libresoc.v:46672.13-46672.40"
- process $proc$libresoc.v:46672$1915
+ attribute \src "libresoc.v:47395.13-47395.40"
+ process $proc$libresoc.v:47395$1955
assign { } { }
assign $1\core_core_insn_type[6:0] 7'0000000
sync always
sync init
update \core_core_insn_type $1\core_core_insn_type[6:0]
end
- attribute \src "libresoc.v:46676.7-46676.32"
- process $proc$libresoc.v:46676$1916
+ attribute \src "libresoc.v:47399.7-47399.32"
+ process $proc$libresoc.v:47399$1956
assign { } { }
assign $1\core_core_is_32bit[0:0] 1'0
sync always
sync init
update \core_core_is_32bit $1\core_core_is_32bit[0:0]
end
- attribute \src "libresoc.v:46680.7-46680.26"
- process $proc$libresoc.v:46680$1917
+ attribute \src "libresoc.v:47403.7-47403.26"
+ process $proc$libresoc.v:47403$1957
assign { } { }
assign $1\core_core_lk[0:0] 1'0
sync always
sync init
update \core_core_lk $1\core_core_lk[0:0]
end
- attribute \src "libresoc.v:46684.14-46684.50"
- process $proc$libresoc.v:46684$1918
+ attribute \src "libresoc.v:47407.14-47407.50"
+ process $proc$libresoc.v:47407$1958
assign { } { }
assign $1\core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_msr $1\core_core_msr[63:0]
end
- attribute \src "libresoc.v:46688.7-46688.26"
- process $proc$libresoc.v:46688$1919
+ attribute \src "libresoc.v:47411.7-47411.26"
+ process $proc$libresoc.v:47411$1959
assign { } { }
assign $1\core_core_oe[0:0] 1'0
sync always
sync init
update \core_core_oe $1\core_core_oe[0:0]
end
- attribute \src "libresoc.v:46692.7-46692.29"
- process $proc$libresoc.v:46692$1920
+ attribute \src "libresoc.v:47415.7-47415.29"
+ process $proc$libresoc.v:47415$1960
assign { } { }
assign $1\core_core_oe_ok[0:0] 1'0
sync always
sync init
update \core_core_oe_ok $1\core_core_oe_ok[0:0]
end
- attribute \src "libresoc.v:46696.7-46696.26"
- process $proc$libresoc.v:46696$1921
+ attribute \src "libresoc.v:47419.7-47419.26"
+ process $proc$libresoc.v:47419$1961
assign { } { }
assign $1\core_core_rc[0:0] 1'0
sync always
sync init
update \core_core_rc $1\core_core_rc[0:0]
end
- attribute \src "libresoc.v:46700.7-46700.29"
- process $proc$libresoc.v:46700$1922
+ attribute \src "libresoc.v:47423.7-47423.29"
+ process $proc$libresoc.v:47423$1962
assign { } { }
assign $1\core_core_rc_ok[0:0] 1'0
sync always
sync init
update \core_core_rc_ok $1\core_core_rc_ok[0:0]
end
- attribute \src "libresoc.v:46704.14-46704.43"
- process $proc$libresoc.v:46704$1923
+ attribute \src "libresoc.v:47427.14-47427.43"
+ process $proc$libresoc.v:47427$1963
assign { } { }
assign $1\core_core_trapaddr[12:0] 13'0000000000000
sync always
sync init
update \core_core_trapaddr $1\core_core_trapaddr[12:0]
end
- attribute \src "libresoc.v:46708.13-46708.39"
- process $proc$libresoc.v:46708$1924
+ attribute \src "libresoc.v:47431.13-47431.39"
+ process $proc$libresoc.v:47431$1964
assign { } { }
assign $1\core_core_traptype[6:0] 7'0000000
sync always
sync init
update \core_core_traptype $1\core_core_traptype[6:0]
end
- attribute \src "libresoc.v:46712.13-46712.31"
- process $proc$libresoc.v:46712$1925
+ attribute \src "libresoc.v:47435.13-47435.31"
+ process $proc$libresoc.v:47435$1965
assign { } { }
assign $1\core_cr_in1[2:0] 3'000
sync always
sync init
update \core_cr_in1 $1\core_cr_in1[2:0]
end
- attribute \src "libresoc.v:46716.7-46716.28"
- process $proc$libresoc.v:46716$1926
+ attribute \src "libresoc.v:47439.7-47439.28"
+ process $proc$libresoc.v:47439$1966
assign { } { }
assign $1\core_cr_in1_ok[0:0] 1'0
sync always
sync init
update \core_cr_in1_ok $1\core_cr_in1_ok[0:0]
end
- attribute \src "libresoc.v:46720.13-46720.31"
- process $proc$libresoc.v:46720$1927
+ attribute \src "libresoc.v:47443.13-47443.31"
+ process $proc$libresoc.v:47443$1967
assign { } { }
assign $1\core_cr_in2[2:0] 3'000
sync always
sync init
update \core_cr_in2 $1\core_cr_in2[2:0]
end
- attribute \src "libresoc.v:46722.13-46722.36"
- process $proc$libresoc.v:46722$1928
+ attribute \src "libresoc.v:47445.13-47445.36"
+ process $proc$libresoc.v:47445$1968
assign { } { }
- assign $0\core_cr_in2$39[2:0]$1929 3'000
+ assign $0\core_cr_in2$39[2:0]$1969 3'000
sync always
sync init
- update \core_cr_in2$39 $0\core_cr_in2$39[2:0]$1929
+ update \core_cr_in2$39 $0\core_cr_in2$39[2:0]$1969
end
- attribute \src "libresoc.v:46728.7-46728.28"
- process $proc$libresoc.v:46728$1930
+ attribute \src "libresoc.v:47451.7-47451.28"
+ process $proc$libresoc.v:47451$1970
assign { } { }
assign $1\core_cr_in2_ok[0:0] 1'0
sync always
sync init
update \core_cr_in2_ok $1\core_cr_in2_ok[0:0]
end
- attribute \src "libresoc.v:46730.7-46730.33"
- process $proc$libresoc.v:46730$1931
+ attribute \src "libresoc.v:47453.7-47453.33"
+ process $proc$libresoc.v:47453$1971
assign { } { }
- assign $0\core_cr_in2_ok$40[0:0]$1932 1'0
+ assign $0\core_cr_in2_ok$40[0:0]$1972 1'0
sync always
sync init
- update \core_cr_in2_ok$40 $0\core_cr_in2_ok$40[0:0]$1932
+ update \core_cr_in2_ok$40 $0\core_cr_in2_ok$40[0:0]$1972
end
- attribute \src "libresoc.v:46736.13-46736.31"
- process $proc$libresoc.v:46736$1933
+ attribute \src "libresoc.v:47459.13-47459.31"
+ process $proc$libresoc.v:47459$1973
assign { } { }
assign $1\core_cr_out[2:0] 3'000
sync always
sync init
update \core_cr_out $1\core_cr_out[2:0]
end
- attribute \src "libresoc.v:46740.7-46740.28"
- process $proc$libresoc.v:46740$1934
+ attribute \src "libresoc.v:47463.7-47463.28"
+ process $proc$libresoc.v:47463$1974
assign { } { }
assign $1\core_cr_out_ok[0:0] 1'0
sync always
sync init
update \core_cr_out_ok $1\core_cr_out_ok[0:0]
end
- attribute \src "libresoc.v:46744.14-46744.45"
- process $proc$libresoc.v:46744$1935
+ attribute \src "libresoc.v:47467.14-47467.45"
+ process $proc$libresoc.v:47467$1975
assign { } { }
assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_dec $1\core_dec[63:0]
end
- attribute \src "libresoc.v:46748.13-46748.28"
- process $proc$libresoc.v:46748$1936
+ attribute \src "libresoc.v:47471.13-47471.28"
+ process $proc$libresoc.v:47471$1976
assign { } { }
assign $1\core_ea[4:0] 5'00000
sync always
sync init
update \core_ea $1\core_ea[4:0]
end
- attribute \src "libresoc.v:46752.7-46752.24"
- process $proc$libresoc.v:46752$1937
+ attribute \src "libresoc.v:47475.7-47475.24"
+ process $proc$libresoc.v:47475$1977
assign { } { }
assign $1\core_ea_ok[0:0] 1'0
sync always
sync init
update \core_ea_ok $1\core_ea_ok[0:0]
end
- attribute \src "libresoc.v:46756.7-46756.23"
- process $proc$libresoc.v:46756$1938
+ attribute \src "libresoc.v:47479.7-47479.23"
+ process $proc$libresoc.v:47479$1978
assign { } { }
assign $1\core_eint[0:0] 1'0
sync always
sync init
update \core_eint $1\core_eint[0:0]
end
- attribute \src "libresoc.v:46760.13-46760.30"
- process $proc$libresoc.v:46760$1939
+ attribute \src "libresoc.v:47483.13-47483.30"
+ process $proc$libresoc.v:47483$1979
assign { } { }
assign $1\core_fast1[2:0] 3'000
sync always
sync init
update \core_fast1 $1\core_fast1[2:0]
end
- attribute \src "libresoc.v:46764.7-46764.27"
- process $proc$libresoc.v:46764$1940
+ attribute \src "libresoc.v:47487.7-47487.27"
+ process $proc$libresoc.v:47487$1980
assign { } { }
assign $1\core_fast1_ok[0:0] 1'0
sync always
sync init
update \core_fast1_ok $1\core_fast1_ok[0:0]
end
- attribute \src "libresoc.v:46768.13-46768.30"
- process $proc$libresoc.v:46768$1941
+ attribute \src "libresoc.v:47491.13-47491.30"
+ process $proc$libresoc.v:47491$1981
assign { } { }
assign $1\core_fast2[2:0] 3'000
sync always
sync init
update \core_fast2 $1\core_fast2[2:0]
end
- attribute \src "libresoc.v:46772.7-46772.27"
- process $proc$libresoc.v:46772$1942
+ attribute \src "libresoc.v:47495.7-47495.27"
+ process $proc$libresoc.v:47495$1982
assign { } { }
assign $1\core_fast2_ok[0:0] 1'0
sync always
sync init
update \core_fast2_ok $1\core_fast2_ok[0:0]
end
- attribute \src "libresoc.v:46776.13-46776.31"
- process $proc$libresoc.v:46776$1943
+ attribute \src "libresoc.v:47499.13-47499.31"
+ process $proc$libresoc.v:47499$1983
assign { } { }
assign $1\core_fasto1[2:0] 3'000
sync always
sync init
update \core_fasto1 $1\core_fasto1[2:0]
end
- attribute \src "libresoc.v:46780.7-46780.28"
- process $proc$libresoc.v:46780$1944
+ attribute \src "libresoc.v:47503.7-47503.28"
+ process $proc$libresoc.v:47503$1984
assign { } { }
assign $1\core_fasto1_ok[0:0] 1'0
sync always
sync init
update \core_fasto1_ok $1\core_fasto1_ok[0:0]
end
- attribute \src "libresoc.v:46784.13-46784.31"
- process $proc$libresoc.v:46784$1945
+ attribute \src "libresoc.v:47507.13-47507.31"
+ process $proc$libresoc.v:47507$1985
assign { } { }
assign $1\core_fasto2[2:0] 3'000
sync always
sync init
update \core_fasto2 $1\core_fasto2[2:0]
end
- attribute \src "libresoc.v:46788.7-46788.28"
- process $proc$libresoc.v:46788$1946
+ attribute \src "libresoc.v:47511.7-47511.28"
+ process $proc$libresoc.v:47511$1986
assign { } { }
assign $1\core_fasto2_ok[0:0] 1'0
sync always
sync init
update \core_fasto2_ok $1\core_fasto2_ok[0:0]
end
- attribute \src "libresoc.v:46792.14-46792.45"
- process $proc$libresoc.v:46792$1947
+ attribute \src "libresoc.v:47515.14-47515.45"
+ process $proc$libresoc.v:47515$1987
assign { } { }
assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_msr $1\core_msr[63:0]
end
- attribute \src "libresoc.v:46796.14-46796.44"
- process $proc$libresoc.v:46796$1948
+ attribute \src "libresoc.v:47519.14-47519.44"
+ process $proc$libresoc.v:47519$1988
assign { } { }
assign $1\core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_pc $1\core_pc[63:0]
end
- attribute \src "libresoc.v:46800.13-46800.30"
- process $proc$libresoc.v:46800$1949
+ attribute \src "libresoc.v:47523.13-47523.30"
+ process $proc$libresoc.v:47523$1989
assign { } { }
assign $1\core_reg1[4:0] 5'00000
sync always
sync init
update \core_reg1 $1\core_reg1[4:0]
end
- attribute \src "libresoc.v:46804.7-46804.26"
- process $proc$libresoc.v:46804$1950
+ attribute \src "libresoc.v:47527.7-47527.26"
+ process $proc$libresoc.v:47527$1990
assign { } { }
assign $1\core_reg1_ok[0:0] 1'0
sync always
sync init
update \core_reg1_ok $1\core_reg1_ok[0:0]
end
- attribute \src "libresoc.v:46808.13-46808.30"
- process $proc$libresoc.v:46808$1951
+ attribute \src "libresoc.v:47531.13-47531.30"
+ process $proc$libresoc.v:47531$1991
assign { } { }
assign $1\core_reg2[4:0] 5'00000
sync always
sync init
update \core_reg2 $1\core_reg2[4:0]
end
- attribute \src "libresoc.v:46812.7-46812.26"
- process $proc$libresoc.v:46812$1952
+ attribute \src "libresoc.v:47535.7-47535.26"
+ process $proc$libresoc.v:47535$1992
assign { } { }
assign $1\core_reg2_ok[0:0] 1'0
sync always
sync init
update \core_reg2_ok $1\core_reg2_ok[0:0]
end
- attribute \src "libresoc.v:46816.13-46816.30"
- process $proc$libresoc.v:46816$1953
+ attribute \src "libresoc.v:47539.13-47539.30"
+ process $proc$libresoc.v:47539$1993
assign { } { }
assign $1\core_reg3[4:0] 5'00000
sync always
sync init
update \core_reg3 $1\core_reg3[4:0]
end
- attribute \src "libresoc.v:46820.7-46820.26"
- process $proc$libresoc.v:46820$1954
+ attribute \src "libresoc.v:47543.7-47543.26"
+ process $proc$libresoc.v:47543$1994
assign { } { }
assign $1\core_reg3_ok[0:0] 1'0
sync always
sync init
update \core_reg3_ok $1\core_reg3_ok[0:0]
end
- attribute \src "libresoc.v:46824.13-46824.30"
- process $proc$libresoc.v:46824$1955
+ attribute \src "libresoc.v:47547.13-47547.30"
+ process $proc$libresoc.v:47547$1995
assign { } { }
assign $1\core_rego[4:0] 5'00000
sync always
sync init
update \core_rego $1\core_rego[4:0]
end
- attribute \src "libresoc.v:46828.7-46828.26"
- process $proc$libresoc.v:46828$1956
+ attribute \src "libresoc.v:47551.7-47551.26"
+ process $proc$libresoc.v:47551$1996
assign { } { }
assign $1\core_rego_ok[0:0] 1'0
sync always
sync init
update \core_rego_ok $1\core_rego_ok[0:0]
end
- attribute \src "libresoc.v:46945.13-46945.32"
- process $proc$libresoc.v:46945$1957
+ attribute \src "libresoc.v:47668.13-47668.32"
+ process $proc$libresoc.v:47668$1997
assign { } { }
assign $1\core_spr1[9:0] 10'0000000000
sync always
sync init
update \core_spr1 $1\core_spr1[9:0]
end
- attribute \src "libresoc.v:46949.7-46949.26"
- process $proc$libresoc.v:46949$1958
+ attribute \src "libresoc.v:47672.7-47672.26"
+ process $proc$libresoc.v:47672$1998
assign { } { }
assign $1\core_spr1_ok[0:0] 1'0
sync always
sync init
update \core_spr1_ok $1\core_spr1_ok[0:0]
end
- attribute \src "libresoc.v:47064.13-47064.32"
- process $proc$libresoc.v:47064$1959
+ attribute \src "libresoc.v:47787.13-47787.32"
+ process $proc$libresoc.v:47787$1999
assign { } { }
assign $1\core_spro[9:0] 10'0000000000
sync always
sync init
update \core_spro $1\core_spro[9:0]
end
- attribute \src "libresoc.v:47068.7-47068.26"
- process $proc$libresoc.v:47068$1960
+ attribute \src "libresoc.v:47791.7-47791.26"
+ process $proc$libresoc.v:47791$2000
assign { } { }
assign $1\core_spro_ok[0:0] 1'0
sync always
sync init
update \core_spro_ok $1\core_spro_ok[0:0]
end
- attribute \src "libresoc.v:47076.13-47076.31"
- process $proc$libresoc.v:47076$1961
+ attribute \src "libresoc.v:47799.13-47799.31"
+ process $proc$libresoc.v:47799$2001
assign { } { }
assign $1\core_xer_in[2:0] 3'000
sync always
sync init
update \core_xer_in $1\core_xer_in[2:0]
end
- attribute \src "libresoc.v:47080.7-47080.26"
- process $proc$libresoc.v:47080$1962
+ attribute \src "libresoc.v:47803.7-47803.26"
+ process $proc$libresoc.v:47803$2002
assign { } { }
assign $1\core_xer_out[0:0] 1'0
sync always
sync init
update \core_xer_out $1\core_xer_out[0:0]
end
- attribute \src "libresoc.v:47096.7-47096.30"
- process $proc$libresoc.v:47096$1963
+ attribute \src "libresoc.v:47819.7-47819.30"
+ process $proc$libresoc.v:47819$2003
assign { } { }
assign $1\cu_st__rel_o_dly[0:0] 1'0
sync always
sync init
update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0]
end
- attribute \src "libresoc.v:47102.7-47102.24"
- process $proc$libresoc.v:47102$1964
+ attribute \src "libresoc.v:47825.7-47825.24"
+ process $proc$libresoc.v:47825$2004
assign { } { }
assign $1\d_cr_delay[0:0] 1'0
sync always
sync init
update \d_cr_delay $1\d_cr_delay[0:0]
end
- attribute \src "libresoc.v:47106.7-47106.25"
- process $proc$libresoc.v:47106$1965
+ attribute \src "libresoc.v:47829.7-47829.25"
+ process $proc$libresoc.v:47829$2005
assign { } { }
assign $1\d_reg_delay[0:0] 1'0
sync always
sync init
update \d_reg_delay $1\d_reg_delay[0:0]
end
- attribute \src "libresoc.v:47110.7-47110.25"
- process $proc$libresoc.v:47110$1966
+ attribute \src "libresoc.v:47833.7-47833.25"
+ process $proc$libresoc.v:47833$2006
assign { } { }
assign $1\d_xer_delay[0:0] 1'0
sync always
sync init
update \d_xer_delay $1\d_xer_delay[0:0]
end
- attribute \src "libresoc.v:47148.13-47148.34"
- process $proc$libresoc.v:47148$1967
+ attribute \src "libresoc.v:47871.13-47871.34"
+ process $proc$libresoc.v:47871$2007
assign { } { }
assign $1\dbg_dmi_addr_i[3:0] 4'0000
sync always
sync init
update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0]
end
- attribute \src "libresoc.v:47152.14-47152.48"
- process $proc$libresoc.v:47152$1968
+ attribute \src "libresoc.v:47875.14-47875.48"
+ process $proc$libresoc.v:47875$2008
assign { } { }
assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dbg_dmi_din $1\dbg_dmi_din[63:0]
end
- attribute \src "libresoc.v:47158.7-47158.27"
- process $proc$libresoc.v:47158$1969
+ attribute \src "libresoc.v:47881.7-47881.27"
+ process $proc$libresoc.v:47881$2009
assign { } { }
assign $1\dbg_dmi_req_i[0:0] 1'0
sync always
sync init
update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0]
end
- attribute \src "libresoc.v:47162.7-47162.26"
- process $proc$libresoc.v:47162$1970
+ attribute \src "libresoc.v:47885.7-47885.26"
+ process $proc$libresoc.v:47885$2010
assign { } { }
assign $1\dbg_dmi_we_i[0:0] 1'0
sync always
sync init
update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0]
end
- attribute \src "libresoc.v:47220.14-47220.49"
- process $proc$libresoc.v:47220$1971
+ attribute \src "libresoc.v:47921.14-47921.49"
+ process $proc$libresoc.v:47921$2011
assign { } { }
assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_dec $1\dec2_cur_dec[63:0]
end
- attribute \src "libresoc.v:47224.7-47224.27"
- process $proc$libresoc.v:47224$1972
+ attribute \src "libresoc.v:47925.7-47925.27"
+ process $proc$libresoc.v:47925$2012
assign { } { }
assign $1\dec2_cur_eint[0:0] 1'0
sync always
sync init
update \dec2_cur_eint $1\dec2_cur_eint[0:0]
end
- attribute \src "libresoc.v:47228.14-47228.49"
- process $proc$libresoc.v:47228$1973
+ attribute \src "libresoc.v:47929.14-47929.49"
+ process $proc$libresoc.v:47929$2013
assign { } { }
assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_msr $1\dec2_cur_msr[63:0]
end
- attribute \src "libresoc.v:47232.14-47232.48"
- process $proc$libresoc.v:47232$1974
+ attribute \src "libresoc.v:47933.14-47933.48"
+ process $proc$libresoc.v:47933$2014
assign { } { }
assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_pc $1\dec2_cur_pc[63:0]
end
- attribute \src "libresoc.v:47625.13-47625.25"
- process $proc$libresoc.v:47625$1975
+ attribute \src "libresoc.v:48326.13-48326.25"
+ process $proc$libresoc.v:48326$2015
assign { } { }
assign $1\delay[1:0] 2'11
sync always
sync init
update \delay $1\delay[1:0]
end
- attribute \src "libresoc.v:47635.13-47635.29"
- process $proc$libresoc.v:47635$1976
+ attribute \src "libresoc.v:48336.13-48336.29"
+ process $proc$libresoc.v:48336$2016
assign { } { }
assign $1\fsm_state[1:0] 2'00
sync always
sync init
update \fsm_state $1\fsm_state[1:0]
end
- attribute \src "libresoc.v:47637.13-47637.35"
- process $proc$libresoc.v:47637$1977
+ attribute \src "libresoc.v:48338.13-48338.35"
+ process $proc$libresoc.v:48338$2017
assign { } { }
- assign $0\fsm_state$115[1:0]$1978 2'00
+ assign $0\fsm_state$115[1:0]$2018 2'00
sync always
sync init
- update \fsm_state$115 $0\fsm_state$115[1:0]$1978
+ update \fsm_state$115 $0\fsm_state$115[1:0]$2018
end
- attribute \src "libresoc.v:47909.14-47909.28"
- process $proc$libresoc.v:47909$1979
+ attribute \src "libresoc.v:48588.14-48588.28"
+ process $proc$libresoc.v:48588$2019
assign { } { }
assign $1\ilatch[31:0] 0
sync always
sync init
update \ilatch $1\ilatch[31:0]
end
- attribute \src "libresoc.v:47941.7-47941.29"
- process $proc$libresoc.v:47941$1980
+ attribute \src "libresoc.v:48624.7-48624.29"
+ process $proc$libresoc.v:48624$2020
assign { } { }
assign $1\jtag_dmi0_ack_o[0:0] 1'0
sync always
sync init
update \jtag_dmi0_ack_o $1\jtag_dmi0_ack_o[0:0]
end
- attribute \src "libresoc.v:47949.14-47949.51"
- process $proc$libresoc.v:47949$1981
+ attribute \src "libresoc.v:48632.14-48632.51"
+ process $proc$libresoc.v:48632$2021
assign { } { }
assign $1\jtag_dmi0_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_dmi0_dout $1\jtag_dmi0_dout[63:0]
end
- attribute \src "libresoc.v:47981.7-47981.22"
- process $proc$libresoc.v:47981$1982
+ attribute \src "libresoc.v:48660.7-48660.22"
+ process $proc$libresoc.v:48660$2022
assign { } { }
assign $1\msr_read[0:0] 1'1
sync always
sync init
update \msr_read $1\msr_read[0:0]
end
- attribute \src "libresoc.v:47993.7-47993.24"
- process $proc$libresoc.v:47993$1983
+ attribute \src "libresoc.v:48672.7-48672.24"
+ process $proc$libresoc.v:48672$2023
assign { } { }
assign $1\pc_changed[0:0] 1'0
sync always
sync init
update \pc_changed $1\pc_changed[0:0]
end
- attribute \src "libresoc.v:48003.7-48003.25"
- process $proc$libresoc.v:48003$1984
+ attribute \src "libresoc.v:48682.7-48682.25"
+ process $proc$libresoc.v:48682$2024
assign { } { }
assign $1\pc_ok_delay[0:0] 1'0
sync always
sync init
update \pc_ok_delay $1\pc_ok_delay[0:0]
end
- attribute \src "libresoc.v:48009.14-48009.32"
- process $proc$libresoc.v:48009$1985
+ attribute \src "libresoc.v:48688.14-48688.32"
+ process $proc$libresoc.v:48688$2025
assign { } { }
assign $1\raw_insn_i[31:0] 0
sync always
sync init
update \raw_insn_i $1\raw_insn_i[31:0]
end
- attribute \src "libresoc.v:48092.3-48093.41"
- process $proc$libresoc.v:48092$1461
+ attribute \src "libresoc.v:48769.3-48770.39"
+ process $proc$libresoc.v:48769$1501
assign { } { }
- assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next
- sync posedge \clk
- update \dec2_cur_dec $0\dec2_cur_dec[63:0]
+ assign $0\d_reg_delay[0:0] \d_reg_delay$next
+ sync posedge \intclk_clk
+ update \d_reg_delay $0\d_reg_delay[0:0]
+ end
+ attribute \src "libresoc.v:48771.3-48772.29"
+ process $proc$libresoc.v:48771$1502
+ assign { } { }
+ assign $0\ilatch[31:0] \ilatch$next
+ sync posedge \intclk_clk
+ update \ilatch $0\ilatch[31:0]
+ end
+ attribute \src "libresoc.v:48773.3-48774.31"
+ process $proc$libresoc.v:48773$1503
+ assign { } { }
+ assign $0\core_pc[63:0] \core_pc$next
+ sync posedge \intclk_clk
+ update \core_pc $0\core_pc[63:0]
+ end
+ attribute \src "libresoc.v:48775.3-48776.33"
+ process $proc$libresoc.v:48775$1504
+ assign { } { }
+ assign $0\core_msr[63:0] \core_msr$next
+ sync posedge \intclk_clk
+ update \core_msr $0\core_msr[63:0]
+ end
+ attribute \src "libresoc.v:48777.3-48778.35"
+ process $proc$libresoc.v:48777$1505
+ assign { } { }
+ assign $0\core_eint[0:0] \core_eint$next
+ sync posedge \intclk_clk
+ update \core_eint $0\core_eint[0:0]
end
- attribute \src "libresoc.v:48094.3-48095.33"
- process $proc$libresoc.v:48094$1462
+ attribute \src "libresoc.v:48779.3-48780.33"
+ process $proc$libresoc.v:48779$1506
assign { } { }
assign $0\core_dec[63:0] \core_dec$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_dec $0\core_dec[63:0]
end
- attribute \src "libresoc.v:48096.3-48097.41"
- process $proc$libresoc.v:48096$1463
+ attribute \src "libresoc.v:48781.3-48782.41"
+ process $proc$libresoc.v:48781$1507
assign { } { }
assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dec2_cur_msr $0\dec2_cur_msr[63:0]
end
- attribute \src "libresoc.v:48098.3-48099.35"
- process $proc$libresoc.v:48098$1464
+ attribute \src "libresoc.v:48783.3-48784.35"
+ process $proc$libresoc.v:48783$1508
assign { } { }
assign $0\fsm_state[1:0] \fsm_state$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \fsm_state $0\fsm_state[1:0]
end
- attribute \src "libresoc.v:48100.3-48101.33"
- process $proc$libresoc.v:48100$1465
+ attribute \src "libresoc.v:48785.3-48786.33"
+ process $proc$libresoc.v:48785$1509
assign { } { }
assign $0\msr_read[0:0] \msr_read$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \msr_read $0\msr_read[0:0]
end
- attribute \src "libresoc.v:48102.3-48103.39"
- process $proc$libresoc.v:48102$1466
+ attribute \src "libresoc.v:48787.3-48788.39"
+ process $proc$libresoc.v:48787$1510
assign { } { }
assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dec2_cur_pc $0\dec2_cur_pc[63:0]
end
- attribute \src "libresoc.v:48104.3-48105.39"
- process $proc$libresoc.v:48104$1467
+ attribute \src "libresoc.v:48789.3-48790.39"
+ process $proc$libresoc.v:48789$1511
assign { } { }
assign $0\bigendian_i[0:0] \bigendian_i$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \bigendian_i $0\bigendian_i[0:0]
end
- attribute \src "libresoc.v:48106.3-48107.37"
- process $proc$libresoc.v:48106$1468
+ attribute \src "libresoc.v:48791.3-48792.37"
+ process $proc$libresoc.v:48791$1512
assign { } { }
assign $0\raw_insn_i[31:0] \raw_insn_i$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \raw_insn_i $0\raw_insn_i[31:0]
end
- attribute \src "libresoc.v:48108.3-48109.41"
- process $proc$libresoc.v:48108$1469
+ attribute \src "libresoc.v:48793.3-48794.41"
+ process $proc$libresoc.v:48793$1513
assign { } { }
assign $0\core_asmcode[7:0] \core_asmcode$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_asmcode $0\core_asmcode[7:0]
end
- attribute \src "libresoc.v:48110.3-48111.35"
- process $proc$libresoc.v:48110$1470
+ attribute \src "libresoc.v:48795.3-48796.35"
+ process $proc$libresoc.v:48795$1514
assign { } { }
assign $0\core_rego[4:0] \core_rego$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_rego $0\core_rego[4:0]
end
- attribute \src "libresoc.v:48112.3-48113.41"
- process $proc$libresoc.v:48112$1471
+ attribute \src "libresoc.v:48797.3-48798.41"
+ process $proc$libresoc.v:48797$1515
assign { } { }
assign $0\core_rego_ok[0:0] \core_rego_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_rego_ok $0\core_rego_ok[0:0]
end
- attribute \src "libresoc.v:48114.3-48115.45"
- process $proc$libresoc.v:48114$1472
- assign { } { }
- assign $0\fsm_state$115[1:0]$1473 \fsm_state$115$next
- sync posedge \clk
- update \fsm_state$115 $0\fsm_state$115[1:0]$1473
- end
- attribute \src "libresoc.v:48116.3-48117.31"
- process $proc$libresoc.v:48116$1474
+ attribute \src "libresoc.v:48799.3-48800.31"
+ process $proc$libresoc.v:48799$1516
assign { } { }
assign $0\core_ea[4:0] \core_ea$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_ea $0\core_ea[4:0]
end
- attribute \src "libresoc.v:48118.3-48119.37"
- process $proc$libresoc.v:48118$1475
+ attribute \src "libresoc.v:48801.3-48802.37"
+ process $proc$libresoc.v:48801$1517
assign { } { }
assign $0\core_ea_ok[0:0] \core_ea_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_ea_ok $0\core_ea_ok[0:0]
end
- attribute \src "libresoc.v:48120.3-48121.35"
- process $proc$libresoc.v:48120$1476
+ attribute \src "libresoc.v:48803.3-48804.35"
+ process $proc$libresoc.v:48803$1518
assign { } { }
assign $0\core_reg1[4:0] \core_reg1$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_reg1 $0\core_reg1[4:0]
end
- attribute \src "libresoc.v:48122.3-48123.41"
- process $proc$libresoc.v:48122$1477
+ attribute \src "libresoc.v:48805.3-48806.41"
+ process $proc$libresoc.v:48805$1519
assign { } { }
assign $0\core_reg1_ok[0:0] \core_reg1_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_reg1_ok $0\core_reg1_ok[0:0]
end
- attribute \src "libresoc.v:48124.3-48125.35"
- process $proc$libresoc.v:48124$1478
+ attribute \src "libresoc.v:48807.3-48808.35"
+ process $proc$libresoc.v:48807$1520
assign { } { }
assign $0\core_reg2[4:0] \core_reg2$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_reg2 $0\core_reg2[4:0]
end
- attribute \src "libresoc.v:48126.3-48127.41"
- process $proc$libresoc.v:48126$1479
+ attribute \src "libresoc.v:48809.3-48810.41"
+ process $proc$libresoc.v:48809$1521
assign { } { }
assign $0\core_reg2_ok[0:0] \core_reg2_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_reg2_ok $0\core_reg2_ok[0:0]
end
- attribute \src "libresoc.v:48128.3-48129.35"
- process $proc$libresoc.v:48128$1480
+ attribute \src "libresoc.v:48811.3-48812.35"
+ process $proc$libresoc.v:48811$1522
assign { } { }
assign $0\core_reg3[4:0] \core_reg3$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_reg3 $0\core_reg3[4:0]
end
- attribute \src "libresoc.v:48130.3-48131.41"
- process $proc$libresoc.v:48130$1481
+ attribute \src "libresoc.v:48813.3-48814.41"
+ process $proc$libresoc.v:48813$1523
assign { } { }
assign $0\core_reg3_ok[0:0] \core_reg3_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_reg3_ok $0\core_reg3_ok[0:0]
end
- attribute \src "libresoc.v:48132.3-48133.35"
- process $proc$libresoc.v:48132$1482
+ attribute \src "libresoc.v:48815.3-48816.35"
+ process $proc$libresoc.v:48815$1524
assign { } { }
assign $0\core_spro[9:0] \core_spro$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_spro $0\core_spro[9:0]
end
- attribute \src "libresoc.v:48134.3-48135.41"
- process $proc$libresoc.v:48134$1483
+ attribute \src "libresoc.v:48817.3-48818.41"
+ process $proc$libresoc.v:48817$1525
assign { } { }
assign $0\core_spro_ok[0:0] \core_spro_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_spro_ok $0\core_spro_ok[0:0]
end
- attribute \src "libresoc.v:48136.3-48137.39"
- process $proc$libresoc.v:48136$1484
- assign { } { }
- assign $0\d_xer_delay[0:0] \d_xer_delay$next
- sync posedge \clk
- update \d_xer_delay $0\d_xer_delay[0:0]
- end
- attribute \src "libresoc.v:48138.3-48139.35"
- process $proc$libresoc.v:48138$1485
+ attribute \src "libresoc.v:48819.3-48820.35"
+ process $proc$libresoc.v:48819$1526
assign { } { }
assign $0\core_spr1[9:0] \core_spr1$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_spr1 $0\core_spr1[9:0]
end
- attribute \src "libresoc.v:48140.3-48141.41"
- process $proc$libresoc.v:48140$1486
+ attribute \src "libresoc.v:48821.3-48822.41"
+ process $proc$libresoc.v:48821$1527
assign { } { }
assign $0\core_spr1_ok[0:0] \core_spr1_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_spr1_ok $0\core_spr1_ok[0:0]
end
- attribute \src "libresoc.v:48142.3-48143.39"
- process $proc$libresoc.v:48142$1487
+ attribute \src "libresoc.v:48823.3-48824.39"
+ process $proc$libresoc.v:48823$1528
assign { } { }
assign $0\core_xer_in[2:0] \core_xer_in$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_xer_in $0\core_xer_in[2:0]
end
- attribute \src "libresoc.v:48144.3-48145.41"
- process $proc$libresoc.v:48144$1488
+ attribute \src "libresoc.v:48825.3-48826.41"
+ process $proc$libresoc.v:48825$1529
assign { } { }
assign $0\core_xer_out[0:0] \core_xer_out$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_xer_out $0\core_xer_out[0:0]
end
- attribute \src "libresoc.v:48146.3-48147.37"
- process $proc$libresoc.v:48146$1489
+ attribute \src "libresoc.v:48827.3-48828.37"
+ process $proc$libresoc.v:48827$1530
assign { } { }
assign $0\core_fast1[2:0] \core_fast1$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_fast1 $0\core_fast1[2:0]
end
- attribute \src "libresoc.v:48148.3-48149.43"
- process $proc$libresoc.v:48148$1490
+ attribute \src "libresoc.v:48829.3-48830.43"
+ process $proc$libresoc.v:48829$1531
assign { } { }
assign $0\core_fast1_ok[0:0] \core_fast1_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_fast1_ok $0\core_fast1_ok[0:0]
end
- attribute \src "libresoc.v:48150.3-48151.37"
- process $proc$libresoc.v:48150$1491
+ attribute \src "libresoc.v:48831.3-48832.37"
+ process $proc$libresoc.v:48831$1532
assign { } { }
assign $0\core_fast2[2:0] \core_fast2$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_fast2 $0\core_fast2[2:0]
end
- attribute \src "libresoc.v:48152.3-48153.43"
- process $proc$libresoc.v:48152$1492
+ attribute \src "libresoc.v:48833.3-48834.43"
+ process $proc$libresoc.v:48833$1533
assign { } { }
assign $0\core_fast2_ok[0:0] \core_fast2_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_fast2_ok $0\core_fast2_ok[0:0]
end
- attribute \src "libresoc.v:48154.3-48155.39"
- process $proc$libresoc.v:48154$1493
+ attribute \src "libresoc.v:48835.3-48836.39"
+ process $proc$libresoc.v:48835$1534
assign { } { }
assign $0\core_fasto1[2:0] \core_fasto1$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_fasto1 $0\core_fasto1[2:0]
end
- attribute \src "libresoc.v:48156.3-48157.45"
- process $proc$libresoc.v:48156$1494
+ attribute \src "libresoc.v:48837.3-48838.45"
+ process $proc$libresoc.v:48837$1535
assign { } { }
assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_fasto1_ok $0\core_fasto1_ok[0:0]
end
- attribute \src "libresoc.v:48158.3-48159.37"
- process $proc$libresoc.v:48158$1495
- assign { } { }
- assign $0\d_cr_delay[0:0] \d_cr_delay$next
- sync posedge \clk
- update \d_cr_delay $0\d_cr_delay[0:0]
- end
- attribute \src "libresoc.v:48160.3-48161.39"
- process $proc$libresoc.v:48160$1496
+ attribute \src "libresoc.v:48839.3-48840.39"
+ process $proc$libresoc.v:48839$1536
assign { } { }
assign $0\core_fasto2[2:0] \core_fasto2$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_fasto2 $0\core_fasto2[2:0]
end
- attribute \src "libresoc.v:48162.3-48163.45"
- process $proc$libresoc.v:48162$1497
+ attribute \src "libresoc.v:48841.3-48842.45"
+ process $proc$libresoc.v:48841$1537
assign { } { }
assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_fasto2_ok $0\core_fasto2_ok[0:0]
end
- attribute \src "libresoc.v:48164.3-48165.39"
- process $proc$libresoc.v:48164$1498
+ attribute \src "libresoc.v:48843.3-48844.39"
+ process $proc$libresoc.v:48843$1538
assign { } { }
assign $0\core_cr_in1[2:0] \core_cr_in1$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_cr_in1 $0\core_cr_in1[2:0]
end
- attribute \src "libresoc.v:48166.3-48167.45"
- process $proc$libresoc.v:48166$1499
+ attribute \src "libresoc.v:48845.3-48846.45"
+ process $proc$libresoc.v:48845$1539
assign { } { }
assign $0\core_cr_in1_ok[0:0] \core_cr_in1_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_cr_in1_ok $0\core_cr_in1_ok[0:0]
end
- attribute \src "libresoc.v:48168.3-48169.39"
- process $proc$libresoc.v:48168$1500
+ attribute \src "libresoc.v:48847.3-48848.39"
+ process $proc$libresoc.v:48847$1540
assign { } { }
assign $0\core_cr_in2[2:0] \core_cr_in2$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_cr_in2 $0\core_cr_in2[2:0]
end
- attribute \src "libresoc.v:48170.3-48171.45"
- process $proc$libresoc.v:48170$1501
+ attribute \src "libresoc.v:48849.3-48850.45"
+ process $proc$libresoc.v:48849$1541
assign { } { }
assign $0\core_cr_in2_ok[0:0] \core_cr_in2_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_cr_in2_ok $0\core_cr_in2_ok[0:0]
end
- attribute \src "libresoc.v:48172.3-48173.47"
- process $proc$libresoc.v:48172$1502
+ attribute \src "libresoc.v:48851.3-48852.47"
+ process $proc$libresoc.v:48851$1542
assign { } { }
- assign $0\core_cr_in2$39[2:0]$1503 \core_cr_in2$39$next
- sync posedge \clk
- update \core_cr_in2$39 $0\core_cr_in2$39[2:0]$1503
+ assign $0\core_cr_in2$39[2:0]$1543 \core_cr_in2$39$next
+ sync posedge \intclk_clk
+ update \core_cr_in2$39 $0\core_cr_in2$39[2:0]$1543
end
- attribute \src "libresoc.v:48174.3-48175.53"
- process $proc$libresoc.v:48174$1504
+ attribute \src "libresoc.v:48853.3-48854.53"
+ process $proc$libresoc.v:48853$1544
assign { } { }
- assign $0\core_cr_in2_ok$40[0:0]$1505 \core_cr_in2_ok$40$next
- sync posedge \clk
- update \core_cr_in2_ok$40 $0\core_cr_in2_ok$40[0:0]$1505
+ assign $0\core_cr_in2_ok$40[0:0]$1545 \core_cr_in2_ok$40$next
+ sync posedge \intclk_clk
+ update \core_cr_in2_ok$40 $0\core_cr_in2_ok$40[0:0]$1545
end
- attribute \src "libresoc.v:48176.3-48177.39"
- process $proc$libresoc.v:48176$1506
+ attribute \src "libresoc.v:48855.3-48856.39"
+ process $proc$libresoc.v:48855$1546
assign { } { }
assign $0\core_cr_out[2:0] \core_cr_out$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_cr_out $0\core_cr_out[2:0]
end
- attribute \src "libresoc.v:48178.3-48179.45"
- process $proc$libresoc.v:48178$1507
+ attribute \src "libresoc.v:48857.3-48858.45"
+ process $proc$libresoc.v:48857$1547
assign { } { }
assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_cr_out_ok $0\core_cr_out_ok[0:0]
end
- attribute \src "libresoc.v:48180.3-48181.39"
- process $proc$libresoc.v:48180$1508
- assign { } { }
- assign $0\d_reg_delay[0:0] \d_reg_delay$next
- sync posedge \clk
- update \d_reg_delay $0\d_reg_delay[0:0]
- end
- attribute \src "libresoc.v:48182.3-48183.43"
- process $proc$libresoc.v:48182$1509
+ attribute \src "libresoc.v:48859.3-48860.43"
+ process $proc$libresoc.v:48859$1548
assign { } { }
assign $0\core_core_msr[63:0] \core_core_msr$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_msr $0\core_core_msr[63:0]
end
- attribute \src "libresoc.v:48184.3-48185.43"
- process $proc$libresoc.v:48184$1510
+ attribute \src "libresoc.v:48861.3-48862.43"
+ process $proc$libresoc.v:48861$1549
assign { } { }
assign $0\core_core_cia[63:0] \core_core_cia$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_cia $0\core_core_cia[63:0]
end
- attribute \src "libresoc.v:48186.3-48187.45"
- process $proc$libresoc.v:48186$1511
+ attribute \src "libresoc.v:48863.3-48864.45"
+ process $proc$libresoc.v:48863$1550
assign { } { }
assign $0\core_core_insn[31:0] \core_core_insn$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_insn $0\core_core_insn[31:0]
end
- attribute \src "libresoc.v:48188.3-48189.55"
- process $proc$libresoc.v:48188$1512
+ attribute \src "libresoc.v:48865.3-48866.55"
+ process $proc$libresoc.v:48865$1551
assign { } { }
assign $0\core_core_insn_type[6:0] \core_core_insn_type$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_insn_type $0\core_core_insn_type[6:0]
end
- attribute \src "libresoc.v:48190.3-48191.51"
- process $proc$libresoc.v:48190$1513
+ attribute \src "libresoc.v:48867.3-48868.51"
+ process $proc$libresoc.v:48867$1552
assign { } { }
assign $0\core_core_fn_unit[11:0] \core_core_fn_unit$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_fn_unit $0\core_core_fn_unit[11:0]
end
- attribute \src "libresoc.v:48192.3-48193.41"
- process $proc$libresoc.v:48192$1514
+ attribute \src "libresoc.v:48869.3-48870.41"
+ process $proc$libresoc.v:48869$1553
+ assign { } { }
+ assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next
+ sync posedge \intclk_clk
+ update \dec2_cur_dec $0\dec2_cur_dec[63:0]
+ end
+ attribute \src "libresoc.v:48871.3-48872.41"
+ process $proc$libresoc.v:48871$1554
assign { } { }
assign $0\core_core_lk[0:0] \core_core_lk$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_lk $0\core_core_lk[0:0]
end
- attribute \src "libresoc.v:48194.3-48195.41"
- process $proc$libresoc.v:48194$1515
+ attribute \src "libresoc.v:48873.3-48874.41"
+ process $proc$libresoc.v:48873$1555
assign { } { }
assign $0\core_core_rc[0:0] \core_core_rc$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_rc $0\core_core_rc[0:0]
end
- attribute \src "libresoc.v:48196.3-48197.47"
- process $proc$libresoc.v:48196$1516
+ attribute \src "libresoc.v:48875.3-48876.47"
+ process $proc$libresoc.v:48875$1556
assign { } { }
assign $0\core_core_rc_ok[0:0] \core_core_rc_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_rc_ok $0\core_core_rc_ok[0:0]
end
- attribute \src "libresoc.v:48198.3-48199.41"
- process $proc$libresoc.v:48198$1517
+ attribute \src "libresoc.v:48877.3-48878.41"
+ process $proc$libresoc.v:48877$1557
assign { } { }
assign $0\core_core_oe[0:0] \core_core_oe$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_oe $0\core_core_oe[0:0]
end
- attribute \src "libresoc.v:48200.3-48201.47"
- process $proc$libresoc.v:48200$1518
+ attribute \src "libresoc.v:48879.3-48880.47"
+ process $proc$libresoc.v:48879$1558
assign { } { }
assign $0\core_core_oe_ok[0:0] \core_core_oe_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_oe_ok $0\core_core_oe_ok[0:0]
end
- attribute \src "libresoc.v:48202.3-48203.29"
- process $proc$libresoc.v:48202$1519
- assign { } { }
- assign $0\ilatch[31:0] \ilatch$next
- sync posedge \clk
- update \ilatch $0\ilatch[31:0]
- end
- attribute \src "libresoc.v:48204.3-48205.59"
- process $proc$libresoc.v:48204$1520
+ attribute \src "libresoc.v:48881.3-48882.59"
+ process $proc$libresoc.v:48881$1559
assign { } { }
assign $0\core_core_input_carry[1:0] \core_core_input_carry$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_input_carry $0\core_core_input_carry[1:0]
end
- attribute \src "libresoc.v:48206.3-48207.53"
- process $proc$libresoc.v:48206$1521
+ attribute \src "libresoc.v:48883.3-48884.53"
+ process $proc$libresoc.v:48883$1560
assign { } { }
assign $0\core_core_traptype[6:0] \core_core_traptype$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_traptype $0\core_core_traptype[6:0]
end
- attribute \src "libresoc.v:48208.3-48209.53"
- process $proc$libresoc.v:48208$1522
+ attribute \src "libresoc.v:48885.3-48886.53"
+ process $proc$libresoc.v:48885$1561
assign { } { }
assign $0\core_core_trapaddr[12:0] \core_core_trapaddr$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_trapaddr $0\core_core_trapaddr[12:0]
end
- attribute \src "libresoc.v:48210.3-48211.47"
- process $proc$libresoc.v:48210$1523
+ attribute \src "libresoc.v:48887.3-48888.47"
+ process $proc$libresoc.v:48887$1562
assign { } { }
assign $0\core_core_cr_rd[7:0] \core_core_cr_rd$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_cr_rd $0\core_core_cr_rd[7:0]
end
- attribute \src "libresoc.v:48212.3-48213.53"
- process $proc$libresoc.v:48212$1524
+ attribute \src "libresoc.v:48889.3-48890.53"
+ process $proc$libresoc.v:48889$1563
assign { } { }
assign $0\core_core_cr_rd_ok[0:0] \core_core_cr_rd_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_cr_rd_ok $0\core_core_cr_rd_ok[0:0]
end
- attribute \src "libresoc.v:48214.3-48215.47"
- process $proc$libresoc.v:48214$1525
+ attribute \src "libresoc.v:48891.3-48892.45"
+ process $proc$libresoc.v:48891$1564
+ assign { } { }
+ assign $0\fsm_state$115[1:0]$1565 \fsm_state$115$next
+ sync posedge \intclk_clk
+ update \fsm_state$115 $0\fsm_state$115[1:0]$1565
+ end
+ attribute \src "libresoc.v:48893.3-48894.47"
+ process $proc$libresoc.v:48893$1566
assign { } { }
assign $0\core_core_cr_wr[7:0] \core_core_cr_wr$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_cr_wr $0\core_core_cr_wr[7:0]
end
- attribute \src "libresoc.v:48216.3-48217.53"
- process $proc$libresoc.v:48216$1526
+ attribute \src "libresoc.v:48895.3-48896.53"
+ process $proc$libresoc.v:48895$1567
assign { } { }
assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0]
end
- attribute \src "libresoc.v:48218.3-48219.53"
- process $proc$libresoc.v:48218$1527
+ attribute \src "libresoc.v:48897.3-48898.53"
+ process $proc$libresoc.v:48897$1568
assign { } { }
assign $0\core_core_is_32bit[0:0] \core_core_is_32bit$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_core_is_32bit $0\core_core_is_32bit[0:0]
end
- attribute \src "libresoc.v:48220.3-48221.37"
- process $proc$libresoc.v:48220$1528
+ attribute \src "libresoc.v:48899.3-48900.37"
+ process $proc$libresoc.v:48899$1569
assign { } { }
assign $0\pc_changed[0:0] \pc_changed$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \pc_changed $0\pc_changed[0:0]
end
- attribute \src "libresoc.v:48222.3-48223.39"
- process $proc$libresoc.v:48222$1529
+ attribute \src "libresoc.v:48901.3-48902.39"
+ process $proc$libresoc.v:48901$1570
assign { } { }
assign $0\pc_ok_delay[0:0] \pc_ok_delay$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \pc_ok_delay $0\pc_ok_delay[0:0]
end
- attribute \src "libresoc.v:48224.3-48225.31"
- process $proc$libresoc.v:48224$1530
- assign { } { }
- assign $0\core_pc[63:0] \core_pc$next
- sync posedge \clk
- update \core_pc $0\core_pc[63:0]
- end
- attribute \src "libresoc.v:48226.3-48227.30"
- process $proc$libresoc.v:48226$1531
+ attribute \src "libresoc.v:48903.3-48904.30"
+ process $proc$libresoc.v:48903$1571
assign { } { }
assign $0\cu_st__rel_o_dly[0:0] 1'0
- sync posedge \clk
+ sync posedge \intclk_clk
update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0]
end
- attribute \src "libresoc.v:48228.3-48229.27"
- process $proc$libresoc.v:48228$1532
+ attribute \src "libresoc.v:48905.3-48906.27"
+ process $proc$libresoc.v:48905$1572
assign { } { }
assign $0\delay[1:0] \delay$next
sync posedge \por_clk
update \delay $0\delay[1:0]
end
- attribute \src "libresoc.v:48230.3-48231.43"
- process $proc$libresoc.v:48230$1533
+ attribute \src "libresoc.v:48907.3-48908.43"
+ process $proc$libresoc.v:48907$1573
assign { } { }
assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dec2_cur_eint $0\dec2_cur_eint[0:0]
end
- attribute \src "libresoc.v:48232.3-48233.45"
- process $proc$libresoc.v:48232$1534
+ attribute \src "libresoc.v:48909.3-48910.45"
+ process $proc$libresoc.v:48909$1574
assign { } { }
assign $0\jtag_dmi0_dout[63:0] \jtag_dmi0_dout$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \jtag_dmi0_dout $0\jtag_dmi0_dout[63:0]
end
- attribute \src "libresoc.v:48234.3-48235.47"
- process $proc$libresoc.v:48234$1535
+ attribute \src "libresoc.v:48911.3-48912.47"
+ process $proc$libresoc.v:48911$1575
assign { } { }
assign $0\jtag_dmi0_ack_o[0:0] \jtag_dmi0_ack_o$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \jtag_dmi0_ack_o $0\jtag_dmi0_ack_o[0:0]
end
- attribute \src "libresoc.v:48236.3-48237.39"
- process $proc$libresoc.v:48236$1536
+ attribute \src "libresoc.v:48913.3-48914.39"
+ process $proc$libresoc.v:48913$1576
+ assign { } { }
+ assign $0\d_xer_delay[0:0] \d_xer_delay$next
+ sync posedge \intclk_clk
+ update \d_xer_delay $0\d_xer_delay[0:0]
+ end
+ attribute \src "libresoc.v:48915.3-48916.39"
+ process $proc$libresoc.v:48915$1577
assign { } { }
assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dbg_dmi_din $0\dbg_dmi_din[63:0]
end
- attribute \src "libresoc.v:48238.3-48239.41"
- process $proc$libresoc.v:48238$1537
+ attribute \src "libresoc.v:48917.3-48918.41"
+ process $proc$libresoc.v:48917$1578
assign { } { }
assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0]
end
- attribute \src "libresoc.v:48240.3-48241.43"
- process $proc$libresoc.v:48240$1538
+ attribute \src "libresoc.v:48919.3-48920.43"
+ process $proc$libresoc.v:48919$1579
assign { } { }
assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0]
end
- attribute \src "libresoc.v:48242.3-48243.45"
- process $proc$libresoc.v:48242$1539
+ attribute \src "libresoc.v:48921.3-48922.45"
+ process $proc$libresoc.v:48921$1580
assign { } { }
assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0]
end
- attribute \src "libresoc.v:48244.3-48245.33"
- process $proc$libresoc.v:48244$1540
- assign { } { }
- assign $0\core_msr[63:0] \core_msr$next
- sync posedge \clk
- update \core_msr $0\core_msr[63:0]
- end
- attribute \src "libresoc.v:48246.3-48247.35"
- process $proc$libresoc.v:48246$1541
+ attribute \src "libresoc.v:48923.3-48924.37"
+ process $proc$libresoc.v:48923$1581
assign { } { }
- assign $0\core_eint[0:0] \core_eint$next
- sync posedge \clk
- update \core_eint $0\core_eint[0:0]
+ assign $0\d_cr_delay[0:0] \d_cr_delay$next
+ sync posedge \intclk_clk
+ update \d_cr_delay $0\d_cr_delay[0:0]
end
- attribute \src "libresoc.v:48500.3-48508.6"
- process $proc$libresoc.v:48500$1542
+ attribute \src "libresoc.v:49177.3-49185.6"
+ process $proc$libresoc.v:49177$1582
assign { } { }
assign { } { }
- assign $0\dbg_dmi_addr_i$next[3:0]$1543 $1\dbg_dmi_addr_i$next[3:0]$1544
- attribute \src "libresoc.v:48501.5-48501.29"
+ assign $0\dbg_dmi_addr_i$next[3:0]$1583 $1\dbg_dmi_addr_i$next[3:0]$1584
+ attribute \src "libresoc.v:49178.5-49178.29"
switch \initial
- attribute \src "libresoc.v:48501.9-48501.17"
+ attribute \src "libresoc.v:49178.9-49178.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_addr_i$next[3:0]$1544 4'0000
+ assign $1\dbg_dmi_addr_i$next[3:0]$1584 4'0000
case
- assign $1\dbg_dmi_addr_i$next[3:0]$1544 \jtag_dmi0_addr_i
+ assign $1\dbg_dmi_addr_i$next[3:0]$1584 \jtag_dmi0_addr_i
end
sync always
- update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$1543
+ update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$1583
end
- attribute \src "libresoc.v:48509.3-48517.6"
- process $proc$libresoc.v:48509$1545
+ attribute \src "libresoc.v:49186.3-49194.6"
+ process $proc$libresoc.v:49186$1585
assign { } { }
assign { } { }
- assign $0\dbg_dmi_req_i$next[0:0]$1546 $1\dbg_dmi_req_i$next[0:0]$1547
- attribute \src "libresoc.v:48510.5-48510.29"
+ assign $0\dbg_dmi_req_i$next[0:0]$1586 $1\dbg_dmi_req_i$next[0:0]$1587
+ attribute \src "libresoc.v:49187.5-49187.29"
switch \initial
- attribute \src "libresoc.v:48510.9-48510.17"
+ attribute \src "libresoc.v:49187.9-49187.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_req_i$next[0:0]$1547 1'0
+ assign $1\dbg_dmi_req_i$next[0:0]$1587 1'0
case
- assign $1\dbg_dmi_req_i$next[0:0]$1547 \jtag_dmi0_req_i
+ assign $1\dbg_dmi_req_i$next[0:0]$1587 \jtag_dmi0_req_i
end
sync always
- update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$1546
+ update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$1586
end
- attribute \src "libresoc.v:48518.3-48528.6"
- process $proc$libresoc.v:48518$1548
+ attribute \src "libresoc.v:49195.3-49205.6"
+ process $proc$libresoc.v:49195$1588
assign { } { }
assign { } { }
assign $0\issue_i[0:0] $1\issue_i[0:0]
- attribute \src "libresoc.v:48519.5-48519.29"
+ attribute \src "libresoc.v:49196.5-49196.29"
switch \initial
- attribute \src "libresoc.v:48519.9-48519.17"
+ attribute \src "libresoc.v:49196.9-49196.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'10
sync always
update \issue_i $0\issue_i[0:0]
end
- attribute \src "libresoc.v:48529.3-48538.6"
- process $proc$libresoc.v:48529$1549
+ attribute \src "libresoc.v:49206.3-49215.6"
+ process $proc$libresoc.v:49206$1589
assign { } { }
assign { } { }
assign $0\dmi__addr[4:0] $1\dmi__addr[4:0]
- attribute \src "libresoc.v:48530.5-48530.29"
+ attribute \src "libresoc.v:49207.5-49207.29"
switch \initial
- attribute \src "libresoc.v:48530.9-48530.17"
+ attribute \src "libresoc.v:49207.9-49207.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307"
switch \dbg_d_gpr_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dmi__addr $0\dmi__addr[4:0]
end
- attribute \src "libresoc.v:48539.3-48548.6"
- process $proc$libresoc.v:48539$1550
+ attribute \src "libresoc.v:49216.3-49225.6"
+ process $proc$libresoc.v:49216$1590
assign { } { }
assign { } { }
assign $0\dmi__ren[0:0] $1\dmi__ren[0:0]
- attribute \src "libresoc.v:48540.5-48540.29"
+ attribute \src "libresoc.v:49217.5-49217.29"
switch \initial
- attribute \src "libresoc.v:48540.9-48540.17"
+ attribute \src "libresoc.v:49217.9-49217.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307"
switch \dbg_d_gpr_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dmi__ren $0\dmi__ren[0:0]
end
- attribute \src "libresoc.v:48549.3-48557.6"
- process $proc$libresoc.v:48549$1551
+ attribute \src "libresoc.v:49226.3-49234.6"
+ process $proc$libresoc.v:49226$1591
assign { } { }
assign { } { }
- assign $0\d_reg_delay$next[0:0]$1552 $1\d_reg_delay$next[0:0]$1553
- attribute \src "libresoc.v:48550.5-48550.29"
+ assign $0\d_reg_delay$next[0:0]$1592 $1\d_reg_delay$next[0:0]$1593
+ attribute \src "libresoc.v:49227.5-49227.29"
switch \initial
- attribute \src "libresoc.v:48550.9-48550.17"
+ attribute \src "libresoc.v:49227.9-49227.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_reg_delay$next[0:0]$1553 1'0
+ assign $1\d_reg_delay$next[0:0]$1593 1'0
case
- assign $1\d_reg_delay$next[0:0]$1553 \dbg_d_gpr_req
+ assign $1\d_reg_delay$next[0:0]$1593 \dbg_d_gpr_req
end
sync always
- update \d_reg_delay$next $0\d_reg_delay$next[0:0]$1552
+ update \d_reg_delay$next $0\d_reg_delay$next[0:0]$1592
end
- attribute \src "libresoc.v:48558.3-48567.6"
- process $proc$libresoc.v:48558$1554
+ attribute \src "libresoc.v:49235.3-49244.6"
+ process $proc$libresoc.v:49235$1594
assign { } { }
assign { } { }
assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:48559.5-48559.29"
+ attribute \src "libresoc.v:49236.5-49236.29"
switch \initial
- attribute \src "libresoc.v:48559.9-48559.17"
+ attribute \src "libresoc.v:49236.9-49236.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317"
switch \d_reg_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0]
end
- attribute \src "libresoc.v:48568.3-48577.6"
- process $proc$libresoc.v:48568$1555
+ attribute \src "libresoc.v:49245.3-49254.6"
+ process $proc$libresoc.v:49245$1595
assign { } { }
assign { } { }
assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:48569.5-48569.29"
+ attribute \src "libresoc.v:49246.5-49246.29"
switch \initial
- attribute \src "libresoc.v:48569.9-48569.17"
+ attribute \src "libresoc.v:49246.9-49246.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317"
switch \d_reg_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0]
end
- attribute \src "libresoc.v:48578.3-48587.6"
- process $proc$libresoc.v:48578$1556
+ attribute \src "libresoc.v:49255.3-49264.6"
+ process $proc$libresoc.v:49255$1596
assign { } { }
assign { } { }
assign $0\full_rd2__ren[7:0] $1\full_rd2__ren[7:0]
- attribute \src "libresoc.v:48579.5-48579.29"
+ attribute \src "libresoc.v:49256.5-49256.29"
switch \initial
- attribute \src "libresoc.v:48579.9-48579.17"
+ attribute \src "libresoc.v:49256.9-49256.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323"
switch \dbg_d_cr_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \full_rd2__ren $0\full_rd2__ren[7:0]
end
- attribute \src "libresoc.v:48588.3-48596.6"
- process $proc$libresoc.v:48588$1557
+ attribute \src "libresoc.v:49265.3-49273.6"
+ process $proc$libresoc.v:49265$1597
assign { } { }
assign { } { }
- assign $0\d_cr_delay$next[0:0]$1558 $1\d_cr_delay$next[0:0]$1559
- attribute \src "libresoc.v:48589.5-48589.29"
+ assign $0\d_cr_delay$next[0:0]$1598 $1\d_cr_delay$next[0:0]$1599
+ attribute \src "libresoc.v:49266.5-49266.29"
switch \initial
- attribute \src "libresoc.v:48589.9-48589.17"
+ attribute \src "libresoc.v:49266.9-49266.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_cr_delay$next[0:0]$1559 1'0
+ assign $1\d_cr_delay$next[0:0]$1599 1'0
case
- assign $1\d_cr_delay$next[0:0]$1559 \dbg_d_cr_req
+ assign $1\d_cr_delay$next[0:0]$1599 \dbg_d_cr_req
end
sync always
- update \d_cr_delay$next $0\d_cr_delay$next[0:0]$1558
+ update \d_cr_delay$next $0\d_cr_delay$next[0:0]$1598
end
- attribute \src "libresoc.v:48597.3-48606.6"
- process $proc$libresoc.v:48597$1560
+ attribute \src "libresoc.v:49274.3-49283.6"
+ process $proc$libresoc.v:49274$1600
assign { } { }
assign { } { }
assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:48598.5-48598.29"
+ attribute \src "libresoc.v:49275.5-49275.29"
switch \initial
- attribute \src "libresoc.v:48598.9-48598.17"
+ attribute \src "libresoc.v:49275.9-49275.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327"
switch \d_cr_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_cr_data $0\dbg_d_cr_data[63:0]
end
- attribute \src "libresoc.v:48607.3-48616.6"
- process $proc$libresoc.v:48607$1561
+ attribute \src "libresoc.v:49284.3-49293.6"
+ process $proc$libresoc.v:49284$1601
assign { } { }
assign { } { }
assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:48608.5-48608.29"
+ attribute \src "libresoc.v:49285.5-49285.29"
switch \initial
- attribute \src "libresoc.v:48608.9-48608.17"
+ attribute \src "libresoc.v:49285.9-49285.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327"
switch \d_cr_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0]
end
- attribute \src "libresoc.v:48617.3-48626.6"
- process $proc$libresoc.v:48617$1562
+ attribute \src "libresoc.v:49294.3-49303.6"
+ process $proc$libresoc.v:49294$1602
assign { } { }
assign { } { }
assign $0\full_rd__ren[2:0] $1\full_rd__ren[2:0]
- attribute \src "libresoc.v:48618.5-48618.29"
+ attribute \src "libresoc.v:49295.5-49295.29"
switch \initial
- attribute \src "libresoc.v:48618.9-48618.17"
+ attribute \src "libresoc.v:49295.9-49295.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:331"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333"
switch \dbg_d_xer_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \full_rd__ren $0\full_rd__ren[2:0]
end
- attribute \src "libresoc.v:48627.3-48635.6"
- process $proc$libresoc.v:48627$1563
+ attribute \src "libresoc.v:49304.3-49312.6"
+ process $proc$libresoc.v:49304$1603
assign { } { }
assign { } { }
- assign $0\d_xer_delay$next[0:0]$1564 $1\d_xer_delay$next[0:0]$1565
- attribute \src "libresoc.v:48628.5-48628.29"
+ assign $0\d_xer_delay$next[0:0]$1604 $1\d_xer_delay$next[0:0]$1605
+ attribute \src "libresoc.v:49305.5-49305.29"
switch \initial
- attribute \src "libresoc.v:48628.9-48628.17"
+ attribute \src "libresoc.v:49305.9-49305.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_xer_delay$next[0:0]$1565 1'0
+ assign $1\d_xer_delay$next[0:0]$1605 1'0
case
- assign $1\d_xer_delay$next[0:0]$1565 \dbg_d_xer_req
+ assign $1\d_xer_delay$next[0:0]$1605 \dbg_d_xer_req
end
sync always
- update \d_xer_delay$next $0\d_xer_delay$next[0:0]$1564
+ update \d_xer_delay$next $0\d_xer_delay$next[0:0]$1604
end
- attribute \src "libresoc.v:48636.3-48645.6"
- process $proc$libresoc.v:48636$1566
+ attribute \src "libresoc.v:49313.3-49322.6"
+ process $proc$libresoc.v:49313$1606
assign { } { }
assign { } { }
assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:48637.5-48637.29"
+ attribute \src "libresoc.v:49314.5-49314.29"
switch \initial
- attribute \src "libresoc.v:48637.9-48637.17"
+ attribute \src "libresoc.v:49314.9-49314.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
switch \d_xer_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_xer_data $0\dbg_d_xer_data[63:0]
end
- attribute \src "libresoc.v:48646.3-48655.6"
- process $proc$libresoc.v:48646$1567
+ attribute \src "libresoc.v:49323.3-49332.6"
+ process $proc$libresoc.v:49323$1607
assign { } { }
assign { } { }
assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:48647.5-48647.29"
+ attribute \src "libresoc.v:49324.5-49324.29"
switch \initial
- attribute \src "libresoc.v:48647.9-48647.17"
+ attribute \src "libresoc.v:49324.9-49324.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337"
switch \d_xer_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0]
end
- attribute \src "libresoc.v:48656.3-48670.6"
- process $proc$libresoc.v:48656$1568
+ attribute \src "libresoc.v:49333.3-49347.6"
+ process $proc$libresoc.v:49333$1608
assign { } { }
assign { } { }
assign $0\issue__addr[2:0] $1\issue__addr[2:0]
- attribute \src "libresoc.v:48657.5-48657.29"
+ attribute \src "libresoc.v:49334.5-49334.29"
switch \initial
- attribute \src "libresoc.v:48657.9-48657.17"
+ attribute \src "libresoc.v:49334.9-49334.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363"
switch \fsm_state$115
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \issue__addr $0\issue__addr[2:0]
end
- attribute \src "libresoc.v:48671.3-48685.6"
- process $proc$libresoc.v:48671$1569
+ attribute \src "libresoc.v:49348.3-49362.6"
+ process $proc$libresoc.v:49348$1609
assign { } { }
assign { } { }
assign $0\issue__ren[0:0] $1\issue__ren[0:0]
- attribute \src "libresoc.v:48672.5-48672.29"
+ attribute \src "libresoc.v:49349.5-49349.29"
switch \initial
- attribute \src "libresoc.v:48672.9-48672.17"
+ attribute \src "libresoc.v:49349.9-49349.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363"
switch \fsm_state$115
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \issue__ren $0\issue__ren[0:0]
end
- attribute \src "libresoc.v:48686.3-48713.6"
- process $proc$libresoc.v:48686$1570
+ attribute \src "libresoc.v:49363.3-49390.6"
+ process $proc$libresoc.v:49363$1610
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$115$next[1:0]$1571 $2\fsm_state$115$next[1:0]$1573
- attribute \src "libresoc.v:48687.5-48687.29"
+ assign $0\fsm_state$115$next[1:0]$1611 $2\fsm_state$115$next[1:0]$1613
+ attribute \src "libresoc.v:49364.5-49364.29"
switch \initial
- attribute \src "libresoc.v:48687.9-48687.17"
+ attribute \src "libresoc.v:49364.9-49364.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363"
switch \fsm_state$115
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\fsm_state$115$next[1:0]$1572 2'01
+ assign $1\fsm_state$115$next[1:0]$1612 2'01
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\fsm_state$115$next[1:0]$1572 2'10
+ assign $1\fsm_state$115$next[1:0]$1612 2'10
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\fsm_state$115$next[1:0]$1572 2'11
+ assign $1\fsm_state$115$next[1:0]$1612 2'11
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\fsm_state$115$next[1:0]$1572 2'00
+ assign $1\fsm_state$115$next[1:0]$1612 2'00
case
- assign $1\fsm_state$115$next[1:0]$1572 \fsm_state$115
+ assign $1\fsm_state$115$next[1:0]$1612 \fsm_state$115
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fsm_state$115$next[1:0]$1573 2'00
+ assign $2\fsm_state$115$next[1:0]$1613 2'00
case
- assign $2\fsm_state$115$next[1:0]$1573 $1\fsm_state$115$next[1:0]$1572
+ assign $2\fsm_state$115$next[1:0]$1613 $1\fsm_state$115$next[1:0]$1612
end
sync always
- update \fsm_state$115$next $0\fsm_state$115$next[1:0]$1571
+ update \fsm_state$115$next $0\fsm_state$115$next[1:0]$1611
end
- attribute \src "libresoc.v:48714.3-48724.6"
- process $proc$libresoc.v:48714$1574
+ attribute \src "libresoc.v:49391.3-49401.6"
+ process $proc$libresoc.v:49391$1614
assign { } { }
assign { } { }
assign $0\new_dec[63:0] $1\new_dec[63:0]
- attribute \src "libresoc.v:48715.5-48715.29"
+ attribute \src "libresoc.v:49392.5-49392.29"
switch \initial
- attribute \src "libresoc.v:48715.9-48715.17"
+ attribute \src "libresoc.v:49392.9-49392.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363"
switch \fsm_state$115
attribute \src "libresoc.v:0.0-0.0"
case 2'01
sync always
update \new_dec $0\new_dec[63:0]
end
- attribute \src "libresoc.v:48725.3-48739.6"
- process $proc$libresoc.v:48725$1575
+ attribute \src "libresoc.v:49402.3-49416.6"
+ process $proc$libresoc.v:49402$1615
assign { } { }
assign { } { }
- assign $0\issue__addr$119[2:0]$1576 $1\issue__addr$119[2:0]$1577
- attribute \src "libresoc.v:48726.5-48726.29"
+ assign $0\issue__addr$119[2:0]$1616 $1\issue__addr$119[2:0]$1617
+ attribute \src "libresoc.v:49403.5-49403.29"
switch \initial
- attribute \src "libresoc.v:48726.9-48726.17"
+ attribute \src "libresoc.v:49403.9-49403.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363"
switch \fsm_state$115
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\issue__addr$119[2:0]$1577 3'110
+ assign $1\issue__addr$119[2:0]$1617 3'110
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\issue__addr$119[2:0]$1577 3'111
+ assign $1\issue__addr$119[2:0]$1617 3'111
case
- assign $1\issue__addr$119[2:0]$1577 3'000
+ assign $1\issue__addr$119[2:0]$1617 3'000
end
sync always
- update \issue__addr$119 $0\issue__addr$119[2:0]$1576
+ update \issue__addr$119 $0\issue__addr$119[2:0]$1616
end
- attribute \src "libresoc.v:48740.3-48754.6"
- process $proc$libresoc.v:48740$1578
+ attribute \src "libresoc.v:49417.3-49431.6"
+ process $proc$libresoc.v:49417$1618
assign { } { }
assign { } { }
assign $0\issue__wen[0:0] $1\issue__wen[0:0]
- attribute \src "libresoc.v:48741.5-48741.29"
+ attribute \src "libresoc.v:49418.5-49418.29"
switch \initial
- attribute \src "libresoc.v:48741.9-48741.17"
+ attribute \src "libresoc.v:49418.9-49418.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363"
switch \fsm_state$115
attribute \src "libresoc.v:0.0-0.0"
case 2'01
sync always
update \issue__wen $0\issue__wen[0:0]
end
- attribute \src "libresoc.v:48755.3-48769.6"
- process $proc$libresoc.v:48755$1579
+ attribute \src "libresoc.v:49432.3-49446.6"
+ process $proc$libresoc.v:49432$1619
assign { } { }
assign { } { }
assign $0\issue__data_i[63:0] $1\issue__data_i[63:0]
- attribute \src "libresoc.v:48756.5-48756.29"
+ attribute \src "libresoc.v:49433.5-49433.29"
switch \initial
- attribute \src "libresoc.v:48756.9-48756.17"
+ attribute \src "libresoc.v:49433.9-49433.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363"
switch \fsm_state$115
attribute \src "libresoc.v:0.0-0.0"
case 2'01
sync always
update \issue__data_i $0\issue__data_i[63:0]
end
- attribute \src "libresoc.v:48770.3-48785.6"
- process $proc$libresoc.v:48770$1580
+ attribute \src "libresoc.v:49447.3-49462.6"
+ process $proc$libresoc.v:49447$1620
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_dec$next[63:0]$1581 $2\dec2_cur_dec$next[63:0]$1583
- attribute \src "libresoc.v:48771.5-48771.29"
+ assign $0\dec2_cur_dec$next[63:0]$1621 $2\dec2_cur_dec$next[63:0]$1623
+ attribute \src "libresoc.v:49448.5-49448.29"
switch \initial
- attribute \src "libresoc.v:48771.9-48771.17"
+ attribute \src "libresoc.v:49448.9-49448.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363"
switch \fsm_state$115
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\dec2_cur_dec$next[63:0]$1582 \new_dec
+ assign $1\dec2_cur_dec$next[63:0]$1622 \new_dec
case
- assign $1\dec2_cur_dec$next[63:0]$1582 \dec2_cur_dec
+ assign $1\dec2_cur_dec$next[63:0]$1622 \dec2_cur_dec
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_dec$next[63:0]$1583 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\dec2_cur_dec$next[63:0]$1623 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\dec2_cur_dec$next[63:0]$1583 $1\dec2_cur_dec$next[63:0]$1582
+ assign $2\dec2_cur_dec$next[63:0]$1623 $1\dec2_cur_dec$next[63:0]$1622
end
sync always
- update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$1581
+ update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$1621
end
- attribute \src "libresoc.v:48786.3-48796.6"
- process $proc$libresoc.v:48786$1584
+ attribute \src "libresoc.v:49463.3-49473.6"
+ process $proc$libresoc.v:49463$1624
assign { } { }
assign { } { }
assign $0\new_tb[63:0] $1\new_tb[63:0]
- attribute \src "libresoc.v:48787.5-48787.29"
+ attribute \src "libresoc.v:49464.5-49464.29"
switch \initial
- attribute \src "libresoc.v:48787.9-48787.17"
+ attribute \src "libresoc.v:49464.9-49464.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363"
switch \fsm_state$115
attribute \src "libresoc.v:0.0-0.0"
case 2'11
sync always
update \new_tb $0\new_tb[63:0]
end
- attribute \src "libresoc.v:48797.3-48805.6"
- process $proc$libresoc.v:48797$1585
+ attribute \src "libresoc.v:49474.3-49482.6"
+ process $proc$libresoc.v:49474$1625
assign { } { }
assign { } { }
- assign $0\dbg_dmi_we_i$next[0:0]$1586 $1\dbg_dmi_we_i$next[0:0]$1587
- attribute \src "libresoc.v:48798.5-48798.29"
+ assign $0\dbg_dmi_we_i$next[0:0]$1626 $1\dbg_dmi_we_i$next[0:0]$1627
+ attribute \src "libresoc.v:49475.5-49475.29"
switch \initial
- attribute \src "libresoc.v:48798.9-48798.17"
+ attribute \src "libresoc.v:49475.9-49475.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_we_i$next[0:0]$1587 1'0
+ assign $1\dbg_dmi_we_i$next[0:0]$1627 1'0
case
- assign $1\dbg_dmi_we_i$next[0:0]$1587 \jtag_dmi0_we_i
+ assign $1\dbg_dmi_we_i$next[0:0]$1627 \jtag_dmi0_we_i
end
sync always
- update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$1586
+ update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$1626
end
- attribute \src "libresoc.v:48806.3-48814.6"
- process $proc$libresoc.v:48806$1588
+ attribute \src "libresoc.v:49483.3-49491.6"
+ process $proc$libresoc.v:49483$1628
assign { } { }
assign { } { }
- assign $0\pc_ok_delay$next[0:0]$1589 $1\pc_ok_delay$next[0:0]$1590
- attribute \src "libresoc.v:48807.5-48807.29"
+ assign $0\pc_ok_delay$next[0:0]$1629 $1\pc_ok_delay$next[0:0]$1630
+ attribute \src "libresoc.v:49484.5-49484.29"
switch \initial
- attribute \src "libresoc.v:48807.9-48807.17"
+ attribute \src "libresoc.v:49484.9-49484.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\pc_ok_delay$next[0:0]$1590 1'0
+ assign $1\pc_ok_delay$next[0:0]$1630 1'0
case
- assign $1\pc_ok_delay$next[0:0]$1590 \$19
+ assign $1\pc_ok_delay$next[0:0]$1630 \$19
end
sync always
- update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$1589
+ update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$1629
end
- attribute \src "libresoc.v:48815.3-48830.6"
- process $proc$libresoc.v:48815$1591
+ attribute \src "libresoc.v:49492.3-49507.6"
+ process $proc$libresoc.v:49492$1631
assign { } { }
assign { } { }
assign { } { }
assign $0\pc[63:0] $2\pc[63:0]
- attribute \src "libresoc.v:48816.5-48816.29"
+ attribute \src "libresoc.v:49493.5-49493.29"
switch \initial
- attribute \src "libresoc.v:48816.9-48816.17"
+ attribute \src "libresoc.v:49493.9-49493.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:189"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196"
switch \pc_ok_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \pc $0\pc[63:0]
end
- attribute \src "libresoc.v:48831.3-48843.6"
- process $proc$libresoc.v:48831$1592
+ attribute \src "libresoc.v:49508.3-49520.6"
+ process $proc$libresoc.v:49508$1632
assign { } { }
assign { } { }
assign $0\cia__ren[3:0] $1\cia__ren[3:0]
- attribute \src "libresoc.v:48832.5-48832.29"
+ attribute \src "libresoc.v:49509.5-49509.29"
switch \initial
- attribute \src "libresoc.v:48832.9-48832.17"
+ attribute \src "libresoc.v:49509.9-49509.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:189"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \cia__ren $0\cia__ren[3:0]
end
- attribute \src "libresoc.v:48844.3-48864.6"
- process $proc$libresoc.v:48844$1593
+ attribute \src "libresoc.v:49521.3-49541.6"
+ process $proc$libresoc.v:49521$1633
assign { } { }
assign { } { }
assign $0\wen[3:0] $1\wen[3:0]
- attribute \src "libresoc.v:48845.5-48845.29"
+ attribute \src "libresoc.v:49522.5-49522.29"
switch \initial
- attribute \src "libresoc.v:48845.9-48845.17"
+ attribute \src "libresoc.v:49522.9-49522.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
assign $1\wen[3:0] $2\wen[3:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
switch \$21
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $2\wen[3:0] $3\wen[3:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297"
switch \$23
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \wen $0\wen[3:0]
end
- attribute \src "libresoc.v:48865.3-48885.6"
- process $proc$libresoc.v:48865$1594
+ attribute \src "libresoc.v:49542.3-49562.6"
+ process $proc$libresoc.v:49542$1634
assign { } { }
assign { } { }
assign $0\data_i[63:0] $1\data_i[63:0]
- attribute \src "libresoc.v:48866.5-48866.29"
+ attribute \src "libresoc.v:49543.5-49543.29"
switch \initial
- attribute \src "libresoc.v:48866.9-48866.17"
+ attribute \src "libresoc.v:49543.9-49543.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
assign $1\data_i[63:0] $2\data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
switch \$25
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $2\data_i[63:0] $3\data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297"
switch \$27
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \data_i $0\data_i[63:0]
end
- attribute \src "libresoc.v:48886.3-48901.6"
- process $proc$libresoc.v:48886$1595
+ attribute \src "libresoc.v:49563.3-49578.6"
+ process $proc$libresoc.v:49563$1635
assign { } { }
assign { } { }
assign $0\msr__ren[3:0] $1\msr__ren[3:0]
- attribute \src "libresoc.v:48887.5-48887.29"
+ attribute \src "libresoc.v:49564.5-49564.29"
switch \initial
- attribute \src "libresoc.v:48887.9-48887.17"
+ attribute \src "libresoc.v:49564.9-49564.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\msr__ren[3:0] $2\msr__ren[3:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
switch \$33
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \msr__ren $0\msr__ren[3:0]
end
- attribute \src "libresoc.v:48902.3-48910.6"
- process $proc$libresoc.v:48902$1596
+ attribute \src "libresoc.v:49579.3-49587.6"
+ process $proc$libresoc.v:49579$1636
assign { } { }
assign { } { }
- assign $0\dbg_dmi_din$next[63:0]$1597 $1\dbg_dmi_din$next[63:0]$1598
- attribute \src "libresoc.v:48903.5-48903.29"
+ assign $0\dbg_dmi_din$next[63:0]$1637 $1\dbg_dmi_din$next[63:0]$1638
+ attribute \src "libresoc.v:49580.5-49580.29"
switch \initial
- attribute \src "libresoc.v:48903.9-48903.17"
+ attribute \src "libresoc.v:49580.9-49580.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_din$next[63:0]$1598 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\dbg_dmi_din$next[63:0]$1638 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $1\dbg_dmi_din$next[63:0]$1598 \jtag_dmi0_din
+ assign $1\dbg_dmi_din$next[63:0]$1638 \jtag_dmi0_din
end
sync always
- update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$1597
+ update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$1637
end
- attribute \src "libresoc.v:48911.3-48935.6"
- process $proc$libresoc.v:48911$1599
+ attribute \src "libresoc.v:49588.3-49612.6"
+ process $proc$libresoc.v:49588$1639
assign { } { }
assign { } { }
assign { } { }
- assign $0\pc_changed$next[0:0]$1600 $3\pc_changed$next[0:0]$1603
- attribute \src "libresoc.v:48912.5-48912.29"
+ assign $0\pc_changed$next[0:0]$1640 $3\pc_changed$next[0:0]$1643
+ attribute \src "libresoc.v:49589.5-49589.29"
switch \initial
- attribute \src "libresoc.v:48912.9-48912.17"
+ attribute \src "libresoc.v:49589.9-49589.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\pc_changed$next[0:0]$1601 1'0
+ assign $1\pc_changed$next[0:0]$1641 1'0
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\pc_changed$next[0:0]$1601 $2\pc_changed$next[0:0]$1602
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+ assign $1\pc_changed$next[0:0]$1641 $2\pc_changed$next[0:0]$1642
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
switch \$35
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\pc_changed$next[0:0]$1602 1'1
+ assign $2\pc_changed$next[0:0]$1642 1'1
case
- assign $2\pc_changed$next[0:0]$1602 \pc_changed
+ assign $2\pc_changed$next[0:0]$1642 \pc_changed
end
case
- assign $1\pc_changed$next[0:0]$1601 \pc_changed
+ assign $1\pc_changed$next[0:0]$1641 \pc_changed
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\pc_changed$next[0:0]$1603 1'0
+ assign $3\pc_changed$next[0:0]$1643 1'0
case
- assign $3\pc_changed$next[0:0]$1603 $1\pc_changed$next[0:0]$1601
+ assign $3\pc_changed$next[0:0]$1643 $1\pc_changed$next[0:0]$1641
end
sync always
- update \pc_changed$next $0\pc_changed$next[0:0]$1600
+ update \pc_changed$next $0\pc_changed$next[0:0]$1640
end
- attribute \src "libresoc.v:48936.3-49042.6"
- process $proc$libresoc.v:48936$1604
+ attribute \src "libresoc.v:49613.3-49719.6"
+ process $proc$libresoc.v:49613$1644
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_asmcode$next[7:0]$1605 $1\core_asmcode$next[7:0]$1656
- assign $0\core_core_cia$next[63:0]$1606 $1\core_core_cia$next[63:0]$1657
- assign $0\core_core_cr_rd$next[7:0]$1607 $1\core_core_cr_rd$next[7:0]$1658
+ assign $0\core_asmcode$next[7:0]$1645 $1\core_asmcode$next[7:0]$1696
+ assign $0\core_core_cia$next[63:0]$1646 $1\core_core_cia$next[63:0]$1697
+ assign $0\core_core_cr_rd$next[7:0]$1647 $1\core_core_cr_rd$next[7:0]$1698
assign { } { }
- assign $0\core_core_cr_wr$next[7:0]$1609 $1\core_core_cr_wr$next[7:0]$1660
+ assign $0\core_core_cr_wr$next[7:0]$1649 $1\core_core_cr_wr$next[7:0]$1700
assign { } { }
- assign $0\core_core_fn_unit$next[11:0]$1611 $1\core_core_fn_unit$next[11:0]$1662
- assign $0\core_core_input_carry$next[1:0]$1612 $1\core_core_input_carry$next[1:0]$1663
- assign $0\core_core_insn$next[31:0]$1613 $1\core_core_insn$next[31:0]$1664
- assign $0\core_core_insn_type$next[6:0]$1614 $1\core_core_insn_type$next[6:0]$1665
- assign $0\core_core_is_32bit$next[0:0]$1615 $1\core_core_is_32bit$next[0:0]$1666
- assign $0\core_core_lk$next[0:0]$1616 $1\core_core_lk$next[0:0]$1667
- assign $0\core_core_msr$next[63:0]$1617 $1\core_core_msr$next[63:0]$1668
- assign $0\core_core_oe$next[0:0]$1618 $1\core_core_oe$next[0:0]$1669
+ assign $0\core_core_fn_unit$next[11:0]$1651 $1\core_core_fn_unit$next[11:0]$1702
+ assign $0\core_core_input_carry$next[1:0]$1652 $1\core_core_input_carry$next[1:0]$1703
+ assign $0\core_core_insn$next[31:0]$1653 $1\core_core_insn$next[31:0]$1704
+ assign $0\core_core_insn_type$next[6:0]$1654 $1\core_core_insn_type$next[6:0]$1705
+ assign $0\core_core_is_32bit$next[0:0]$1655 $1\core_core_is_32bit$next[0:0]$1706
+ assign $0\core_core_lk$next[0:0]$1656 $1\core_core_lk$next[0:0]$1707
+ assign $0\core_core_msr$next[63:0]$1657 $1\core_core_msr$next[63:0]$1708
+ assign $0\core_core_oe$next[0:0]$1658 $1\core_core_oe$next[0:0]$1709
assign { } { }
- assign $0\core_core_rc$next[0:0]$1620 $1\core_core_rc$next[0:0]$1671
+ assign $0\core_core_rc$next[0:0]$1660 $1\core_core_rc$next[0:0]$1711
assign { } { }
- assign $0\core_core_trapaddr$next[12:0]$1622 $1\core_core_trapaddr$next[12:0]$1673
- assign $0\core_core_traptype$next[6:0]$1623 $1\core_core_traptype$next[6:0]$1674
- assign $0\core_cr_in1$next[2:0]$1624 $1\core_cr_in1$next[2:0]$1675
+ assign $0\core_core_trapaddr$next[12:0]$1662 $1\core_core_trapaddr$next[12:0]$1713
+ assign $0\core_core_traptype$next[6:0]$1663 $1\core_core_traptype$next[6:0]$1714
+ assign $0\core_cr_in1$next[2:0]$1664 $1\core_cr_in1$next[2:0]$1715
assign { } { }
- assign $0\core_cr_in2$39$next[2:0]$1626 $1\core_cr_in2$39$next[2:0]$1677
- assign $0\core_cr_in2$next[2:0]$1627 $1\core_cr_in2$next[2:0]$1678
+ assign $0\core_cr_in2$39$next[2:0]$1666 $1\core_cr_in2$39$next[2:0]$1717
+ assign $0\core_cr_in2$next[2:0]$1667 $1\core_cr_in2$next[2:0]$1718
assign { } { }
assign { } { }
- assign $0\core_cr_out$next[2:0]$1630 $1\core_cr_out$next[2:0]$1681
+ assign $0\core_cr_out$next[2:0]$1670 $1\core_cr_out$next[2:0]$1721
assign { } { }
- assign $0\core_ea$next[4:0]$1632 $1\core_ea$next[4:0]$1683
+ assign $0\core_ea$next[4:0]$1672 $1\core_ea$next[4:0]$1723
assign { } { }
- assign $0\core_fast1$next[2:0]$1634 $1\core_fast1$next[2:0]$1685
+ assign $0\core_fast1$next[2:0]$1674 $1\core_fast1$next[2:0]$1725
assign { } { }
- assign $0\core_fast2$next[2:0]$1636 $1\core_fast2$next[2:0]$1687
+ assign $0\core_fast2$next[2:0]$1676 $1\core_fast2$next[2:0]$1727
assign { } { }
- assign $0\core_fasto1$next[2:0]$1638 $1\core_fasto1$next[2:0]$1689
+ assign $0\core_fasto1$next[2:0]$1678 $1\core_fasto1$next[2:0]$1729
assign { } { }
- assign $0\core_fasto2$next[2:0]$1640 $1\core_fasto2$next[2:0]$1691
+ assign $0\core_fasto2$next[2:0]$1680 $1\core_fasto2$next[2:0]$1731
assign { } { }
- assign $0\core_reg1$next[4:0]$1642 $1\core_reg1$next[4:0]$1693
+ assign $0\core_reg1$next[4:0]$1682 $1\core_reg1$next[4:0]$1733
assign { } { }
- assign $0\core_reg2$next[4:0]$1644 $1\core_reg2$next[4:0]$1695
+ assign $0\core_reg2$next[4:0]$1684 $1\core_reg2$next[4:0]$1735
assign { } { }
- assign $0\core_reg3$next[4:0]$1646 $1\core_reg3$next[4:0]$1697
+ assign $0\core_reg3$next[4:0]$1686 $1\core_reg3$next[4:0]$1737
assign { } { }
- assign $0\core_rego$next[4:0]$1648 $1\core_rego$next[4:0]$1699
+ assign $0\core_rego$next[4:0]$1688 $1\core_rego$next[4:0]$1739
assign { } { }
- assign $0\core_spr1$next[9:0]$1650 $1\core_spr1$next[9:0]$1701
+ assign $0\core_spr1$next[9:0]$1690 $1\core_spr1$next[9:0]$1741
assign { } { }
- assign $0\core_spro$next[9:0]$1652 $1\core_spro$next[9:0]$1703
+ assign $0\core_spro$next[9:0]$1692 $1\core_spro$next[9:0]$1743
assign { } { }
- assign $0\core_xer_in$next[2:0]$1654 $1\core_xer_in$next[2:0]$1705
- assign $0\core_xer_out$next[0:0]$1655 $1\core_xer_out$next[0:0]$1706
- assign $0\core_core_cr_rd_ok$next[0:0]$1608 $4\core_core_cr_rd_ok$next[0:0]$1809
- assign $0\core_core_cr_wr_ok$next[0:0]$1610 $4\core_core_cr_wr_ok$next[0:0]$1810
- assign $0\core_core_oe_ok$next[0:0]$1619 $4\core_core_oe_ok$next[0:0]$1811
- assign $0\core_core_rc_ok$next[0:0]$1621 $4\core_core_rc_ok$next[0:0]$1812
- assign $0\core_cr_in1_ok$next[0:0]$1625 $4\core_cr_in1_ok$next[0:0]$1813
- assign $0\core_cr_in2_ok$40$next[0:0]$1628 $4\core_cr_in2_ok$40$next[0:0]$1814
- assign $0\core_cr_in2_ok$next[0:0]$1629 $4\core_cr_in2_ok$next[0:0]$1815
- assign $0\core_cr_out_ok$next[0:0]$1631 $4\core_cr_out_ok$next[0:0]$1816
- assign $0\core_ea_ok$next[0:0]$1633 $4\core_ea_ok$next[0:0]$1817
- assign $0\core_fast1_ok$next[0:0]$1635 $4\core_fast1_ok$next[0:0]$1818
- assign $0\core_fast2_ok$next[0:0]$1637 $4\core_fast2_ok$next[0:0]$1819
- assign $0\core_fasto1_ok$next[0:0]$1639 $4\core_fasto1_ok$next[0:0]$1820
- assign $0\core_fasto2_ok$next[0:0]$1641 $4\core_fasto2_ok$next[0:0]$1821
- assign $0\core_reg1_ok$next[0:0]$1643 $4\core_reg1_ok$next[0:0]$1822
- assign $0\core_reg2_ok$next[0:0]$1645 $4\core_reg2_ok$next[0:0]$1823
- assign $0\core_reg3_ok$next[0:0]$1647 $4\core_reg3_ok$next[0:0]$1824
- assign $0\core_rego_ok$next[0:0]$1649 $4\core_rego_ok$next[0:0]$1825
- assign $0\core_spr1_ok$next[0:0]$1651 $4\core_spr1_ok$next[0:0]$1826
- assign $0\core_spro_ok$next[0:0]$1653 $4\core_spro_ok$next[0:0]$1827
- attribute \src "libresoc.v:48937.5-48937.29"
+ assign $0\core_xer_in$next[2:0]$1694 $1\core_xer_in$next[2:0]$1745
+ assign $0\core_xer_out$next[0:0]$1695 $1\core_xer_out$next[0:0]$1746
+ assign $0\core_core_cr_rd_ok$next[0:0]$1648 $4\core_core_cr_rd_ok$next[0:0]$1849
+ assign $0\core_core_cr_wr_ok$next[0:0]$1650 $4\core_core_cr_wr_ok$next[0:0]$1850
+ assign $0\core_core_oe_ok$next[0:0]$1659 $4\core_core_oe_ok$next[0:0]$1851
+ assign $0\core_core_rc_ok$next[0:0]$1661 $4\core_core_rc_ok$next[0:0]$1852
+ assign $0\core_cr_in1_ok$next[0:0]$1665 $4\core_cr_in1_ok$next[0:0]$1853
+ assign $0\core_cr_in2_ok$40$next[0:0]$1668 $4\core_cr_in2_ok$40$next[0:0]$1854
+ assign $0\core_cr_in2_ok$next[0:0]$1669 $4\core_cr_in2_ok$next[0:0]$1855
+ assign $0\core_cr_out_ok$next[0:0]$1671 $4\core_cr_out_ok$next[0:0]$1856
+ assign $0\core_ea_ok$next[0:0]$1673 $4\core_ea_ok$next[0:0]$1857
+ assign $0\core_fast1_ok$next[0:0]$1675 $4\core_fast1_ok$next[0:0]$1858
+ assign $0\core_fast2_ok$next[0:0]$1677 $4\core_fast2_ok$next[0:0]$1859
+ assign $0\core_fasto1_ok$next[0:0]$1679 $4\core_fasto1_ok$next[0:0]$1860
+ assign $0\core_fasto2_ok$next[0:0]$1681 $4\core_fasto2_ok$next[0:0]$1861
+ assign $0\core_reg1_ok$next[0:0]$1683 $4\core_reg1_ok$next[0:0]$1862
+ assign $0\core_reg2_ok$next[0:0]$1685 $4\core_reg2_ok$next[0:0]$1863
+ assign $0\core_reg3_ok$next[0:0]$1687 $4\core_reg3_ok$next[0:0]$1864
+ assign $0\core_rego_ok$next[0:0]$1689 $4\core_rego_ok$next[0:0]$1865
+ assign $0\core_spr1_ok$next[0:0]$1691 $4\core_spr1_ok$next[0:0]$1866
+ assign $0\core_spro_ok$next[0:0]$1693 $4\core_spro_ok$next[0:0]$1867
+ attribute \src "libresoc.v:49614.5-49614.29"
switch \initial
- attribute \src "libresoc.v:48937.9-48937.17"
+ attribute \src "libresoc.v:49614.9-49614.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign { } { }
assign { } { }
- assign { $1\core_core_is_32bit$next[0:0]$1666 $1\core_core_cr_wr_ok$next[0:0]$1661 $1\core_core_cr_wr$next[7:0]$1660 $1\core_core_cr_rd_ok$next[0:0]$1659 $1\core_core_cr_rd$next[7:0]$1658 $1\core_core_trapaddr$next[12:0]$1673 $1\core_core_traptype$next[6:0]$1674 $1\core_core_input_carry$next[1:0]$1663 $1\core_core_oe_ok$next[0:0]$1670 $1\core_core_oe$next[0:0]$1669 $1\core_core_rc_ok$next[0:0]$1672 $1\core_core_rc$next[0:0]$1671 $1\core_core_lk$next[0:0]$1667 $1\core_core_fn_unit$next[11:0]$1662 $1\core_core_insn_type$next[6:0]$1665 $1\core_core_insn$next[31:0]$1664 $1\core_core_cia$next[63:0]$1657 $1\core_core_msr$next[63:0]$1668 $1\core_cr_out_ok$next[0:0]$1682 $1\core_cr_out$next[2:0]$1681 $1\core_cr_in2_ok$40$next[0:0]$1679 $1\core_cr_in2$39$next[2:0]$1677 $1\core_cr_in2_ok$next[0:0]$1680 $1\core_cr_in2$next[2:0]$1678 $1\core_cr_in1_ok$next[0:0]$1676 $1\core_cr_in1$next[2:0]$1675 $1\core_fasto2_ok$next[0:0]$1692 $1\core_fasto2$next[2:0]$1691 $1\core_fasto1_ok$next[0:0]$1690 $1\core_fasto1$next[2:0]$1689 $1\core_fast2_ok$next[0:0]$1688 $1\core_fast2$next[2:0]$1687 $1\core_fast1_ok$next[0:0]$1686 $1\core_fast1$next[2:0]$1685 $1\core_xer_out$next[0:0]$1706 $1\core_xer_in$next[2:0]$1705 $1\core_spr1_ok$next[0:0]$1702 $1\core_spr1$next[9:0]$1701 $1\core_spro_ok$next[0:0]$1704 $1\core_spro$next[9:0]$1703 $1\core_reg3_ok$next[0:0]$1698 $1\core_reg3$next[4:0]$1697 $1\core_reg2_ok$next[0:0]$1696 $1\core_reg2$next[4:0]$1695 $1\core_reg1_ok$next[0:0]$1694 $1\core_reg1$next[4:0]$1693 $1\core_ea_ok$next[0:0]$1684 $1\core_ea$next[4:0]$1683 $1\core_rego_ok$next[0:0]$1700 $1\core_rego$next[4:0]$1699 $1\core_asmcode$next[7:0]$1656 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\core_core_is_32bit$next[0:0]$1706 $1\core_core_cr_wr_ok$next[0:0]$1701 $1\core_core_cr_wr$next[7:0]$1700 $1\core_core_cr_rd_ok$next[0:0]$1699 $1\core_core_cr_rd$next[7:0]$1698 $1\core_core_trapaddr$next[12:0]$1713 $1\core_core_traptype$next[6:0]$1714 $1\core_core_input_carry$next[1:0]$1703 $1\core_core_oe_ok$next[0:0]$1710 $1\core_core_oe$next[0:0]$1709 $1\core_core_rc_ok$next[0:0]$1712 $1\core_core_rc$next[0:0]$1711 $1\core_core_lk$next[0:0]$1707 $1\core_core_fn_unit$next[11:0]$1702 $1\core_core_insn_type$next[6:0]$1705 $1\core_core_insn$next[31:0]$1704 $1\core_core_cia$next[63:0]$1697 $1\core_core_msr$next[63:0]$1708 $1\core_cr_out_ok$next[0:0]$1722 $1\core_cr_out$next[2:0]$1721 $1\core_cr_in2_ok$40$next[0:0]$1719 $1\core_cr_in2$39$next[2:0]$1717 $1\core_cr_in2_ok$next[0:0]$1720 $1\core_cr_in2$next[2:0]$1718 $1\core_cr_in1_ok$next[0:0]$1716 $1\core_cr_in1$next[2:0]$1715 $1\core_fasto2_ok$next[0:0]$1732 $1\core_fasto2$next[2:0]$1731 $1\core_fasto1_ok$next[0:0]$1730 $1\core_fasto1$next[2:0]$1729 $1\core_fast2_ok$next[0:0]$1728 $1\core_fast2$next[2:0]$1727 $1\core_fast1_ok$next[0:0]$1726 $1\core_fast1$next[2:0]$1725 $1\core_xer_out$next[0:0]$1746 $1\core_xer_in$next[2:0]$1745 $1\core_spr1_ok$next[0:0]$1742 $1\core_spr1$next[9:0]$1741 $1\core_spro_ok$next[0:0]$1744 $1\core_spro$next[9:0]$1743 $1\core_reg3_ok$next[0:0]$1738 $1\core_reg3$next[4:0]$1737 $1\core_reg2_ok$next[0:0]$1736 $1\core_reg2$next[4:0]$1735 $1\core_reg1_ok$next[0:0]$1734 $1\core_reg1$next[4:0]$1733 $1\core_ea_ok$next[0:0]$1724 $1\core_ea$next[4:0]$1723 $1\core_rego_ok$next[0:0]$1740 $1\core_rego$next[4:0]$1739 $1\core_asmcode$next[7:0]$1696 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\core_asmcode$next[7:0]$1656 $2\core_asmcode$next[7:0]$1707
- assign $1\core_core_cia$next[63:0]$1657 $2\core_core_cia$next[63:0]$1708
- assign $1\core_core_cr_rd$next[7:0]$1658 $2\core_core_cr_rd$next[7:0]$1709
- assign $1\core_core_cr_rd_ok$next[0:0]$1659 $2\core_core_cr_rd_ok$next[0:0]$1710
- assign $1\core_core_cr_wr$next[7:0]$1660 $2\core_core_cr_wr$next[7:0]$1711
- assign $1\core_core_cr_wr_ok$next[0:0]$1661 $2\core_core_cr_wr_ok$next[0:0]$1712
- assign $1\core_core_fn_unit$next[11:0]$1662 $2\core_core_fn_unit$next[11:0]$1713
- assign $1\core_core_input_carry$next[1:0]$1663 $2\core_core_input_carry$next[1:0]$1714
- assign $1\core_core_insn$next[31:0]$1664 $2\core_core_insn$next[31:0]$1715
- assign $1\core_core_insn_type$next[6:0]$1665 $2\core_core_insn_type$next[6:0]$1716
- assign $1\core_core_is_32bit$next[0:0]$1666 $2\core_core_is_32bit$next[0:0]$1717
- assign $1\core_core_lk$next[0:0]$1667 $2\core_core_lk$next[0:0]$1718
- assign $1\core_core_msr$next[63:0]$1668 $2\core_core_msr$next[63:0]$1719
- assign $1\core_core_oe$next[0:0]$1669 $2\core_core_oe$next[0:0]$1720
- assign $1\core_core_oe_ok$next[0:0]$1670 $2\core_core_oe_ok$next[0:0]$1721
- assign $1\core_core_rc$next[0:0]$1671 $2\core_core_rc$next[0:0]$1722
- assign $1\core_core_rc_ok$next[0:0]$1672 $2\core_core_rc_ok$next[0:0]$1723
- assign $1\core_core_trapaddr$next[12:0]$1673 $2\core_core_trapaddr$next[12:0]$1724
- assign $1\core_core_traptype$next[6:0]$1674 $2\core_core_traptype$next[6:0]$1725
- assign $1\core_cr_in1$next[2:0]$1675 $2\core_cr_in1$next[2:0]$1726
- assign $1\core_cr_in1_ok$next[0:0]$1676 $2\core_cr_in1_ok$next[0:0]$1727
- assign $1\core_cr_in2$39$next[2:0]$1677 $2\core_cr_in2$39$next[2:0]$1728
- assign $1\core_cr_in2$next[2:0]$1678 $2\core_cr_in2$next[2:0]$1729
- assign $1\core_cr_in2_ok$40$next[0:0]$1679 $2\core_cr_in2_ok$40$next[0:0]$1730
- assign $1\core_cr_in2_ok$next[0:0]$1680 $2\core_cr_in2_ok$next[0:0]$1731
- assign $1\core_cr_out$next[2:0]$1681 $2\core_cr_out$next[2:0]$1732
- assign $1\core_cr_out_ok$next[0:0]$1682 $2\core_cr_out_ok$next[0:0]$1733
- assign $1\core_ea$next[4:0]$1683 $2\core_ea$next[4:0]$1734
- assign $1\core_ea_ok$next[0:0]$1684 $2\core_ea_ok$next[0:0]$1735
- assign $1\core_fast1$next[2:0]$1685 $2\core_fast1$next[2:0]$1736
- assign $1\core_fast1_ok$next[0:0]$1686 $2\core_fast1_ok$next[0:0]$1737
- assign $1\core_fast2$next[2:0]$1687 $2\core_fast2$next[2:0]$1738
- assign $1\core_fast2_ok$next[0:0]$1688 $2\core_fast2_ok$next[0:0]$1739
- assign $1\core_fasto1$next[2:0]$1689 $2\core_fasto1$next[2:0]$1740
- assign $1\core_fasto1_ok$next[0:0]$1690 $2\core_fasto1_ok$next[0:0]$1741
- assign $1\core_fasto2$next[2:0]$1691 $2\core_fasto2$next[2:0]$1742
- assign $1\core_fasto2_ok$next[0:0]$1692 $2\core_fasto2_ok$next[0:0]$1743
- assign $1\core_reg1$next[4:0]$1693 $2\core_reg1$next[4:0]$1744
- assign $1\core_reg1_ok$next[0:0]$1694 $2\core_reg1_ok$next[0:0]$1745
- assign $1\core_reg2$next[4:0]$1695 $2\core_reg2$next[4:0]$1746
- assign $1\core_reg2_ok$next[0:0]$1696 $2\core_reg2_ok$next[0:0]$1747
- assign $1\core_reg3$next[4:0]$1697 $2\core_reg3$next[4:0]$1748
- assign $1\core_reg3_ok$next[0:0]$1698 $2\core_reg3_ok$next[0:0]$1749
- assign $1\core_rego$next[4:0]$1699 $2\core_rego$next[4:0]$1750
- assign $1\core_rego_ok$next[0:0]$1700 $2\core_rego_ok$next[0:0]$1751
- assign $1\core_spr1$next[9:0]$1701 $2\core_spr1$next[9:0]$1752
- assign $1\core_spr1_ok$next[0:0]$1702 $2\core_spr1_ok$next[0:0]$1753
- assign $1\core_spro$next[9:0]$1703 $2\core_spro$next[9:0]$1754
- assign $1\core_spro_ok$next[0:0]$1704 $2\core_spro_ok$next[0:0]$1755
- assign $1\core_xer_in$next[2:0]$1705 $2\core_xer_in$next[2:0]$1756
- assign $1\core_xer_out$next[0:0]$1706 $2\core_xer_out$next[0:0]$1757
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258"
+ assign $1\core_asmcode$next[7:0]$1696 $2\core_asmcode$next[7:0]$1747
+ assign $1\core_core_cia$next[63:0]$1697 $2\core_core_cia$next[63:0]$1748
+ assign $1\core_core_cr_rd$next[7:0]$1698 $2\core_core_cr_rd$next[7:0]$1749
+ assign $1\core_core_cr_rd_ok$next[0:0]$1699 $2\core_core_cr_rd_ok$next[0:0]$1750
+ assign $1\core_core_cr_wr$next[7:0]$1700 $2\core_core_cr_wr$next[7:0]$1751
+ assign $1\core_core_cr_wr_ok$next[0:0]$1701 $2\core_core_cr_wr_ok$next[0:0]$1752
+ assign $1\core_core_fn_unit$next[11:0]$1702 $2\core_core_fn_unit$next[11:0]$1753
+ assign $1\core_core_input_carry$next[1:0]$1703 $2\core_core_input_carry$next[1:0]$1754
+ assign $1\core_core_insn$next[31:0]$1704 $2\core_core_insn$next[31:0]$1755
+ assign $1\core_core_insn_type$next[6:0]$1705 $2\core_core_insn_type$next[6:0]$1756
+ assign $1\core_core_is_32bit$next[0:0]$1706 $2\core_core_is_32bit$next[0:0]$1757
+ assign $1\core_core_lk$next[0:0]$1707 $2\core_core_lk$next[0:0]$1758
+ assign $1\core_core_msr$next[63:0]$1708 $2\core_core_msr$next[63:0]$1759
+ assign $1\core_core_oe$next[0:0]$1709 $2\core_core_oe$next[0:0]$1760
+ assign $1\core_core_oe_ok$next[0:0]$1710 $2\core_core_oe_ok$next[0:0]$1761
+ assign $1\core_core_rc$next[0:0]$1711 $2\core_core_rc$next[0:0]$1762
+ assign $1\core_core_rc_ok$next[0:0]$1712 $2\core_core_rc_ok$next[0:0]$1763
+ assign $1\core_core_trapaddr$next[12:0]$1713 $2\core_core_trapaddr$next[12:0]$1764
+ assign $1\core_core_traptype$next[6:0]$1714 $2\core_core_traptype$next[6:0]$1765
+ assign $1\core_cr_in1$next[2:0]$1715 $2\core_cr_in1$next[2:0]$1766
+ assign $1\core_cr_in1_ok$next[0:0]$1716 $2\core_cr_in1_ok$next[0:0]$1767
+ assign $1\core_cr_in2$39$next[2:0]$1717 $2\core_cr_in2$39$next[2:0]$1768
+ assign $1\core_cr_in2$next[2:0]$1718 $2\core_cr_in2$next[2:0]$1769
+ assign $1\core_cr_in2_ok$40$next[0:0]$1719 $2\core_cr_in2_ok$40$next[0:0]$1770
+ assign $1\core_cr_in2_ok$next[0:0]$1720 $2\core_cr_in2_ok$next[0:0]$1771
+ assign $1\core_cr_out$next[2:0]$1721 $2\core_cr_out$next[2:0]$1772
+ assign $1\core_cr_out_ok$next[0:0]$1722 $2\core_cr_out_ok$next[0:0]$1773
+ assign $1\core_ea$next[4:0]$1723 $2\core_ea$next[4:0]$1774
+ assign $1\core_ea_ok$next[0:0]$1724 $2\core_ea_ok$next[0:0]$1775
+ assign $1\core_fast1$next[2:0]$1725 $2\core_fast1$next[2:0]$1776
+ assign $1\core_fast1_ok$next[0:0]$1726 $2\core_fast1_ok$next[0:0]$1777
+ assign $1\core_fast2$next[2:0]$1727 $2\core_fast2$next[2:0]$1778
+ assign $1\core_fast2_ok$next[0:0]$1728 $2\core_fast2_ok$next[0:0]$1779
+ assign $1\core_fasto1$next[2:0]$1729 $2\core_fasto1$next[2:0]$1780
+ assign $1\core_fasto1_ok$next[0:0]$1730 $2\core_fasto1_ok$next[0:0]$1781
+ assign $1\core_fasto2$next[2:0]$1731 $2\core_fasto2$next[2:0]$1782
+ assign $1\core_fasto2_ok$next[0:0]$1732 $2\core_fasto2_ok$next[0:0]$1783
+ assign $1\core_reg1$next[4:0]$1733 $2\core_reg1$next[4:0]$1784
+ assign $1\core_reg1_ok$next[0:0]$1734 $2\core_reg1_ok$next[0:0]$1785
+ assign $1\core_reg2$next[4:0]$1735 $2\core_reg2$next[4:0]$1786
+ assign $1\core_reg2_ok$next[0:0]$1736 $2\core_reg2_ok$next[0:0]$1787
+ assign $1\core_reg3$next[4:0]$1737 $2\core_reg3$next[4:0]$1788
+ assign $1\core_reg3_ok$next[0:0]$1738 $2\core_reg3_ok$next[0:0]$1789
+ assign $1\core_rego$next[4:0]$1739 $2\core_rego$next[4:0]$1790
+ assign $1\core_rego_ok$next[0:0]$1740 $2\core_rego_ok$next[0:0]$1791
+ assign $1\core_spr1$next[9:0]$1741 $2\core_spr1$next[9:0]$1792
+ assign $1\core_spr1_ok$next[0:0]$1742 $2\core_spr1_ok$next[0:0]$1793
+ assign $1\core_spro$next[9:0]$1743 $2\core_spro$next[9:0]$1794
+ assign $1\core_spro_ok$next[0:0]$1744 $2\core_spro_ok$next[0:0]$1795
+ assign $1\core_xer_in$next[2:0]$1745 $2\core_xer_in$next[2:0]$1796
+ assign $1\core_xer_out$next[0:0]$1746 $2\core_xer_out$next[0:0]$1797
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\core_asmcode$next[7:0]$1707 \core_asmcode
- assign $2\core_core_cia$next[63:0]$1708 \core_core_cia
- assign $2\core_core_cr_rd$next[7:0]$1709 \core_core_cr_rd
- assign $2\core_core_cr_rd_ok$next[0:0]$1710 \core_core_cr_rd_ok
- assign $2\core_core_cr_wr$next[7:0]$1711 \core_core_cr_wr
- assign $2\core_core_cr_wr_ok$next[0:0]$1712 \core_core_cr_wr_ok
- assign $2\core_core_fn_unit$next[11:0]$1713 \core_core_fn_unit
- assign $2\core_core_input_carry$next[1:0]$1714 \core_core_input_carry
- assign $2\core_core_insn$next[31:0]$1715 \core_core_insn
- assign $2\core_core_insn_type$next[6:0]$1716 \core_core_insn_type
- assign $2\core_core_is_32bit$next[0:0]$1717 \core_core_is_32bit
- assign $2\core_core_lk$next[0:0]$1718 \core_core_lk
- assign $2\core_core_msr$next[63:0]$1719 \core_core_msr
- assign $2\core_core_oe$next[0:0]$1720 \core_core_oe
- assign $2\core_core_oe_ok$next[0:0]$1721 \core_core_oe_ok
- assign $2\core_core_rc$next[0:0]$1722 \core_core_rc
- assign $2\core_core_rc_ok$next[0:0]$1723 \core_core_rc_ok
- assign $2\core_core_trapaddr$next[12:0]$1724 \core_core_trapaddr
- assign $2\core_core_traptype$next[6:0]$1725 \core_core_traptype
- assign $2\core_cr_in1$next[2:0]$1726 \core_cr_in1
- assign $2\core_cr_in1_ok$next[0:0]$1727 \core_cr_in1_ok
- assign $2\core_cr_in2$39$next[2:0]$1728 \core_cr_in2$39
- assign $2\core_cr_in2$next[2:0]$1729 \core_cr_in2
- assign $2\core_cr_in2_ok$40$next[0:0]$1730 \core_cr_in2_ok$40
- assign $2\core_cr_in2_ok$next[0:0]$1731 \core_cr_in2_ok
- assign $2\core_cr_out$next[2:0]$1732 \core_cr_out
- assign $2\core_cr_out_ok$next[0:0]$1733 \core_cr_out_ok
- assign $2\core_ea$next[4:0]$1734 \core_ea
- assign $2\core_ea_ok$next[0:0]$1735 \core_ea_ok
- assign $2\core_fast1$next[2:0]$1736 \core_fast1
- assign $2\core_fast1_ok$next[0:0]$1737 \core_fast1_ok
- assign $2\core_fast2$next[2:0]$1738 \core_fast2
- assign $2\core_fast2_ok$next[0:0]$1739 \core_fast2_ok
- assign $2\core_fasto1$next[2:0]$1740 \core_fasto1
- assign $2\core_fasto1_ok$next[0:0]$1741 \core_fasto1_ok
- assign $2\core_fasto2$next[2:0]$1742 \core_fasto2
- assign $2\core_fasto2_ok$next[0:0]$1743 \core_fasto2_ok
- assign $2\core_reg1$next[4:0]$1744 \core_reg1
- assign $2\core_reg1_ok$next[0:0]$1745 \core_reg1_ok
- assign $2\core_reg2$next[4:0]$1746 \core_reg2
- assign $2\core_reg2_ok$next[0:0]$1747 \core_reg2_ok
- assign $2\core_reg3$next[4:0]$1748 \core_reg3
- assign $2\core_reg3_ok$next[0:0]$1749 \core_reg3_ok
- assign $2\core_rego$next[4:0]$1750 \core_rego
- assign $2\core_rego_ok$next[0:0]$1751 \core_rego_ok
- assign $2\core_spr1$next[9:0]$1752 \core_spr1
- assign $2\core_spr1_ok$next[0:0]$1753 \core_spr1_ok
- assign $2\core_spro$next[9:0]$1754 \core_spro
- assign $2\core_spro_ok$next[0:0]$1755 \core_spro_ok
- assign $2\core_xer_in$next[2:0]$1756 \core_xer_in
- assign $2\core_xer_out$next[0:0]$1757 \core_xer_out
+ assign $2\core_asmcode$next[7:0]$1747 \core_asmcode
+ assign $2\core_core_cia$next[63:0]$1748 \core_core_cia
+ assign $2\core_core_cr_rd$next[7:0]$1749 \core_core_cr_rd
+ assign $2\core_core_cr_rd_ok$next[0:0]$1750 \core_core_cr_rd_ok
+ assign $2\core_core_cr_wr$next[7:0]$1751 \core_core_cr_wr
+ assign $2\core_core_cr_wr_ok$next[0:0]$1752 \core_core_cr_wr_ok
+ assign $2\core_core_fn_unit$next[11:0]$1753 \core_core_fn_unit
+ assign $2\core_core_input_carry$next[1:0]$1754 \core_core_input_carry
+ assign $2\core_core_insn$next[31:0]$1755 \core_core_insn
+ assign $2\core_core_insn_type$next[6:0]$1756 \core_core_insn_type
+ assign $2\core_core_is_32bit$next[0:0]$1757 \core_core_is_32bit
+ assign $2\core_core_lk$next[0:0]$1758 \core_core_lk
+ assign $2\core_core_msr$next[63:0]$1759 \core_core_msr
+ assign $2\core_core_oe$next[0:0]$1760 \core_core_oe
+ assign $2\core_core_oe_ok$next[0:0]$1761 \core_core_oe_ok
+ assign $2\core_core_rc$next[0:0]$1762 \core_core_rc
+ assign $2\core_core_rc_ok$next[0:0]$1763 \core_core_rc_ok
+ assign $2\core_core_trapaddr$next[12:0]$1764 \core_core_trapaddr
+ assign $2\core_core_traptype$next[6:0]$1765 \core_core_traptype
+ assign $2\core_cr_in1$next[2:0]$1766 \core_cr_in1
+ assign $2\core_cr_in1_ok$next[0:0]$1767 \core_cr_in1_ok
+ assign $2\core_cr_in2$39$next[2:0]$1768 \core_cr_in2$39
+ assign $2\core_cr_in2$next[2:0]$1769 \core_cr_in2
+ assign $2\core_cr_in2_ok$40$next[0:0]$1770 \core_cr_in2_ok$40
+ assign $2\core_cr_in2_ok$next[0:0]$1771 \core_cr_in2_ok
+ assign $2\core_cr_out$next[2:0]$1772 \core_cr_out
+ assign $2\core_cr_out_ok$next[0:0]$1773 \core_cr_out_ok
+ assign $2\core_ea$next[4:0]$1774 \core_ea
+ assign $2\core_ea_ok$next[0:0]$1775 \core_ea_ok
+ assign $2\core_fast1$next[2:0]$1776 \core_fast1
+ assign $2\core_fast1_ok$next[0:0]$1777 \core_fast1_ok
+ assign $2\core_fast2$next[2:0]$1778 \core_fast2
+ assign $2\core_fast2_ok$next[0:0]$1779 \core_fast2_ok
+ assign $2\core_fasto1$next[2:0]$1780 \core_fasto1
+ assign $2\core_fasto1_ok$next[0:0]$1781 \core_fasto1_ok
+ assign $2\core_fasto2$next[2:0]$1782 \core_fasto2
+ assign $2\core_fasto2_ok$next[0:0]$1783 \core_fasto2_ok
+ assign $2\core_reg1$next[4:0]$1784 \core_reg1
+ assign $2\core_reg1_ok$next[0:0]$1785 \core_reg1_ok
+ assign $2\core_reg2$next[4:0]$1786 \core_reg2
+ assign $2\core_reg2_ok$next[0:0]$1787 \core_reg2_ok
+ assign $2\core_reg3$next[4:0]$1788 \core_reg3
+ assign $2\core_reg3_ok$next[0:0]$1789 \core_reg3_ok
+ assign $2\core_rego$next[4:0]$1790 \core_rego
+ assign $2\core_rego_ok$next[0:0]$1791 \core_rego_ok
+ assign $2\core_spr1$next[9:0]$1792 \core_spr1
+ assign $2\core_spr1_ok$next[0:0]$1793 \core_spr1_ok
+ assign $2\core_spro$next[9:0]$1794 \core_spro
+ assign $2\core_spro_ok$next[0:0]$1795 \core_spro_ok
+ assign $2\core_xer_in$next[2:0]$1796 \core_xer_in
+ assign $2\core_xer_out$next[0:0]$1797 \core_xer_out
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $2\core_core_is_32bit$next[0:0]$1717 $2\core_core_cr_wr_ok$next[0:0]$1712 $2\core_core_cr_wr$next[7:0]$1711 $2\core_core_cr_rd_ok$next[0:0]$1710 $2\core_core_cr_rd$next[7:0]$1709 $2\core_core_trapaddr$next[12:0]$1724 $2\core_core_traptype$next[6:0]$1725 $2\core_core_input_carry$next[1:0]$1714 $2\core_core_oe_ok$next[0:0]$1721 $2\core_core_oe$next[0:0]$1720 $2\core_core_rc_ok$next[0:0]$1723 $2\core_core_rc$next[0:0]$1722 $2\core_core_lk$next[0:0]$1718 $2\core_core_fn_unit$next[11:0]$1713 $2\core_core_insn_type$next[6:0]$1716 $2\core_core_insn$next[31:0]$1715 $2\core_core_cia$next[63:0]$1708 $2\core_core_msr$next[63:0]$1719 $2\core_cr_out_ok$next[0:0]$1733 $2\core_cr_out$next[2:0]$1732 $2\core_cr_in2_ok$40$next[0:0]$1730 $2\core_cr_in2$39$next[2:0]$1728 $2\core_cr_in2_ok$next[0:0]$1731 $2\core_cr_in2$next[2:0]$1729 $2\core_cr_in1_ok$next[0:0]$1727 $2\core_cr_in1$next[2:0]$1726 $2\core_fasto2_ok$next[0:0]$1743 $2\core_fasto2$next[2:0]$1742 $2\core_fasto1_ok$next[0:0]$1741 $2\core_fasto1$next[2:0]$1740 $2\core_fast2_ok$next[0:0]$1739 $2\core_fast2$next[2:0]$1738 $2\core_fast1_ok$next[0:0]$1737 $2\core_fast1$next[2:0]$1736 $2\core_xer_out$next[0:0]$1757 $2\core_xer_in$next[2:0]$1756 $2\core_spr1_ok$next[0:0]$1753 $2\core_spr1$next[9:0]$1752 $2\core_spro_ok$next[0:0]$1755 $2\core_spro$next[9:0]$1754 $2\core_reg3_ok$next[0:0]$1749 $2\core_reg3$next[4:0]$1748 $2\core_reg2_ok$next[0:0]$1747 $2\core_reg2$next[4:0]$1746 $2\core_reg1_ok$next[0:0]$1745 $2\core_reg1$next[4:0]$1744 $2\core_ea_ok$next[0:0]$1735 $2\core_ea$next[4:0]$1734 $2\core_rego_ok$next[0:0]$1751 $2\core_rego$next[4:0]$1750 $2\core_asmcode$next[7:0]$1707 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$2 \dec2_cr_in2$1 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
+ assign { $2\core_core_is_32bit$next[0:0]$1757 $2\core_core_cr_wr_ok$next[0:0]$1752 $2\core_core_cr_wr$next[7:0]$1751 $2\core_core_cr_rd_ok$next[0:0]$1750 $2\core_core_cr_rd$next[7:0]$1749 $2\core_core_trapaddr$next[12:0]$1764 $2\core_core_traptype$next[6:0]$1765 $2\core_core_input_carry$next[1:0]$1754 $2\core_core_oe_ok$next[0:0]$1761 $2\core_core_oe$next[0:0]$1760 $2\core_core_rc_ok$next[0:0]$1763 $2\core_core_rc$next[0:0]$1762 $2\core_core_lk$next[0:0]$1758 $2\core_core_fn_unit$next[11:0]$1753 $2\core_core_insn_type$next[6:0]$1756 $2\core_core_insn$next[31:0]$1755 $2\core_core_cia$next[63:0]$1748 $2\core_core_msr$next[63:0]$1759 $2\core_cr_out_ok$next[0:0]$1773 $2\core_cr_out$next[2:0]$1772 $2\core_cr_in2_ok$40$next[0:0]$1770 $2\core_cr_in2$39$next[2:0]$1768 $2\core_cr_in2_ok$next[0:0]$1771 $2\core_cr_in2$next[2:0]$1769 $2\core_cr_in1_ok$next[0:0]$1767 $2\core_cr_in1$next[2:0]$1766 $2\core_fasto2_ok$next[0:0]$1783 $2\core_fasto2$next[2:0]$1782 $2\core_fasto1_ok$next[0:0]$1781 $2\core_fasto1$next[2:0]$1780 $2\core_fast2_ok$next[0:0]$1779 $2\core_fast2$next[2:0]$1778 $2\core_fast1_ok$next[0:0]$1777 $2\core_fast1$next[2:0]$1776 $2\core_xer_out$next[0:0]$1797 $2\core_xer_in$next[2:0]$1796 $2\core_spr1_ok$next[0:0]$1793 $2\core_spr1$next[9:0]$1792 $2\core_spro_ok$next[0:0]$1795 $2\core_spro$next[9:0]$1794 $2\core_reg3_ok$next[0:0]$1789 $2\core_reg3$next[4:0]$1788 $2\core_reg2_ok$next[0:0]$1787 $2\core_reg2$next[4:0]$1786 $2\core_reg1_ok$next[0:0]$1785 $2\core_reg1$next[4:0]$1784 $2\core_ea_ok$next[0:0]$1775 $2\core_ea$next[4:0]$1774 $2\core_rego_ok$next[0:0]$1791 $2\core_rego$next[4:0]$1790 $2\core_asmcode$next[7:0]$1747 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$2 \dec2_cr_in2$1 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
end
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
assign { } { }
assign { } { }
- assign $1\core_asmcode$next[7:0]$1656 $3\core_asmcode$next[7:0]$1758
- assign $1\core_core_cia$next[63:0]$1657 $3\core_core_cia$next[63:0]$1759
- assign $1\core_core_cr_rd$next[7:0]$1658 $3\core_core_cr_rd$next[7:0]$1760
- assign $1\core_core_cr_rd_ok$next[0:0]$1659 $3\core_core_cr_rd_ok$next[0:0]$1761
- assign $1\core_core_cr_wr$next[7:0]$1660 $3\core_core_cr_wr$next[7:0]$1762
- assign $1\core_core_cr_wr_ok$next[0:0]$1661 $3\core_core_cr_wr_ok$next[0:0]$1763
- assign $1\core_core_fn_unit$next[11:0]$1662 $3\core_core_fn_unit$next[11:0]$1764
- assign $1\core_core_input_carry$next[1:0]$1663 $3\core_core_input_carry$next[1:0]$1765
- assign $1\core_core_insn$next[31:0]$1664 $3\core_core_insn$next[31:0]$1766
- assign $1\core_core_insn_type$next[6:0]$1665 $3\core_core_insn_type$next[6:0]$1767
- assign $1\core_core_is_32bit$next[0:0]$1666 $3\core_core_is_32bit$next[0:0]$1768
- assign $1\core_core_lk$next[0:0]$1667 $3\core_core_lk$next[0:0]$1769
- assign $1\core_core_msr$next[63:0]$1668 $3\core_core_msr$next[63:0]$1770
- assign $1\core_core_oe$next[0:0]$1669 $3\core_core_oe$next[0:0]$1771
- assign $1\core_core_oe_ok$next[0:0]$1670 $3\core_core_oe_ok$next[0:0]$1772
- assign $1\core_core_rc$next[0:0]$1671 $3\core_core_rc$next[0:0]$1773
- assign $1\core_core_rc_ok$next[0:0]$1672 $3\core_core_rc_ok$next[0:0]$1774
- assign $1\core_core_trapaddr$next[12:0]$1673 $3\core_core_trapaddr$next[12:0]$1775
- assign $1\core_core_traptype$next[6:0]$1674 $3\core_core_traptype$next[6:0]$1776
- assign $1\core_cr_in1$next[2:0]$1675 $3\core_cr_in1$next[2:0]$1777
- assign $1\core_cr_in1_ok$next[0:0]$1676 $3\core_cr_in1_ok$next[0:0]$1778
- assign $1\core_cr_in2$39$next[2:0]$1677 $3\core_cr_in2$39$next[2:0]$1779
- assign $1\core_cr_in2$next[2:0]$1678 $3\core_cr_in2$next[2:0]$1780
- assign $1\core_cr_in2_ok$40$next[0:0]$1679 $3\core_cr_in2_ok$40$next[0:0]$1781
- assign $1\core_cr_in2_ok$next[0:0]$1680 $3\core_cr_in2_ok$next[0:0]$1782
- assign $1\core_cr_out$next[2:0]$1681 $3\core_cr_out$next[2:0]$1783
- assign $1\core_cr_out_ok$next[0:0]$1682 $3\core_cr_out_ok$next[0:0]$1784
- assign $1\core_ea$next[4:0]$1683 $3\core_ea$next[4:0]$1785
- assign $1\core_ea_ok$next[0:0]$1684 $3\core_ea_ok$next[0:0]$1786
- assign $1\core_fast1$next[2:0]$1685 $3\core_fast1$next[2:0]$1787
- assign $1\core_fast1_ok$next[0:0]$1686 $3\core_fast1_ok$next[0:0]$1788
- assign $1\core_fast2$next[2:0]$1687 $3\core_fast2$next[2:0]$1789
- assign $1\core_fast2_ok$next[0:0]$1688 $3\core_fast2_ok$next[0:0]$1790
- assign $1\core_fasto1$next[2:0]$1689 $3\core_fasto1$next[2:0]$1791
- assign $1\core_fasto1_ok$next[0:0]$1690 $3\core_fasto1_ok$next[0:0]$1792
- assign $1\core_fasto2$next[2:0]$1691 $3\core_fasto2$next[2:0]$1793
- assign $1\core_fasto2_ok$next[0:0]$1692 $3\core_fasto2_ok$next[0:0]$1794
- assign $1\core_reg1$next[4:0]$1693 $3\core_reg1$next[4:0]$1795
- assign $1\core_reg1_ok$next[0:0]$1694 $3\core_reg1_ok$next[0:0]$1796
- assign $1\core_reg2$next[4:0]$1695 $3\core_reg2$next[4:0]$1797
- assign $1\core_reg2_ok$next[0:0]$1696 $3\core_reg2_ok$next[0:0]$1798
- assign $1\core_reg3$next[4:0]$1697 $3\core_reg3$next[4:0]$1799
- assign $1\core_reg3_ok$next[0:0]$1698 $3\core_reg3_ok$next[0:0]$1800
- assign $1\core_rego$next[4:0]$1699 $3\core_rego$next[4:0]$1801
- assign $1\core_rego_ok$next[0:0]$1700 $3\core_rego_ok$next[0:0]$1802
- assign $1\core_spr1$next[9:0]$1701 $3\core_spr1$next[9:0]$1803
- assign $1\core_spr1_ok$next[0:0]$1702 $3\core_spr1_ok$next[0:0]$1804
- assign $1\core_spro$next[9:0]$1703 $3\core_spro$next[9:0]$1805
- assign $1\core_spro_ok$next[0:0]$1704 $3\core_spro_ok$next[0:0]$1806
- assign $1\core_xer_in$next[2:0]$1705 $3\core_xer_in$next[2:0]$1807
- assign $1\core_xer_out$next[0:0]$1706 $3\core_xer_out$next[0:0]$1808
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ assign $1\core_asmcode$next[7:0]$1696 $3\core_asmcode$next[7:0]$1798
+ assign $1\core_core_cia$next[63:0]$1697 $3\core_core_cia$next[63:0]$1799
+ assign $1\core_core_cr_rd$next[7:0]$1698 $3\core_core_cr_rd$next[7:0]$1800
+ assign $1\core_core_cr_rd_ok$next[0:0]$1699 $3\core_core_cr_rd_ok$next[0:0]$1801
+ assign $1\core_core_cr_wr$next[7:0]$1700 $3\core_core_cr_wr$next[7:0]$1802
+ assign $1\core_core_cr_wr_ok$next[0:0]$1701 $3\core_core_cr_wr_ok$next[0:0]$1803
+ assign $1\core_core_fn_unit$next[11:0]$1702 $3\core_core_fn_unit$next[11:0]$1804
+ assign $1\core_core_input_carry$next[1:0]$1703 $3\core_core_input_carry$next[1:0]$1805
+ assign $1\core_core_insn$next[31:0]$1704 $3\core_core_insn$next[31:0]$1806
+ assign $1\core_core_insn_type$next[6:0]$1705 $3\core_core_insn_type$next[6:0]$1807
+ assign $1\core_core_is_32bit$next[0:0]$1706 $3\core_core_is_32bit$next[0:0]$1808
+ assign $1\core_core_lk$next[0:0]$1707 $3\core_core_lk$next[0:0]$1809
+ assign $1\core_core_msr$next[63:0]$1708 $3\core_core_msr$next[63:0]$1810
+ assign $1\core_core_oe$next[0:0]$1709 $3\core_core_oe$next[0:0]$1811
+ assign $1\core_core_oe_ok$next[0:0]$1710 $3\core_core_oe_ok$next[0:0]$1812
+ assign $1\core_core_rc$next[0:0]$1711 $3\core_core_rc$next[0:0]$1813
+ assign $1\core_core_rc_ok$next[0:0]$1712 $3\core_core_rc_ok$next[0:0]$1814
+ assign $1\core_core_trapaddr$next[12:0]$1713 $3\core_core_trapaddr$next[12:0]$1815
+ assign $1\core_core_traptype$next[6:0]$1714 $3\core_core_traptype$next[6:0]$1816
+ assign $1\core_cr_in1$next[2:0]$1715 $3\core_cr_in1$next[2:0]$1817
+ assign $1\core_cr_in1_ok$next[0:0]$1716 $3\core_cr_in1_ok$next[0:0]$1818
+ assign $1\core_cr_in2$39$next[2:0]$1717 $3\core_cr_in2$39$next[2:0]$1819
+ assign $1\core_cr_in2$next[2:0]$1718 $3\core_cr_in2$next[2:0]$1820
+ assign $1\core_cr_in2_ok$40$next[0:0]$1719 $3\core_cr_in2_ok$40$next[0:0]$1821
+ assign $1\core_cr_in2_ok$next[0:0]$1720 $3\core_cr_in2_ok$next[0:0]$1822
+ assign $1\core_cr_out$next[2:0]$1721 $3\core_cr_out$next[2:0]$1823
+ assign $1\core_cr_out_ok$next[0:0]$1722 $3\core_cr_out_ok$next[0:0]$1824
+ assign $1\core_ea$next[4:0]$1723 $3\core_ea$next[4:0]$1825
+ assign $1\core_ea_ok$next[0:0]$1724 $3\core_ea_ok$next[0:0]$1826
+ assign $1\core_fast1$next[2:0]$1725 $3\core_fast1$next[2:0]$1827
+ assign $1\core_fast1_ok$next[0:0]$1726 $3\core_fast1_ok$next[0:0]$1828
+ assign $1\core_fast2$next[2:0]$1727 $3\core_fast2$next[2:0]$1829
+ assign $1\core_fast2_ok$next[0:0]$1728 $3\core_fast2_ok$next[0:0]$1830
+ assign $1\core_fasto1$next[2:0]$1729 $3\core_fasto1$next[2:0]$1831
+ assign $1\core_fasto1_ok$next[0:0]$1730 $3\core_fasto1_ok$next[0:0]$1832
+ assign $1\core_fasto2$next[2:0]$1731 $3\core_fasto2$next[2:0]$1833
+ assign $1\core_fasto2_ok$next[0:0]$1732 $3\core_fasto2_ok$next[0:0]$1834
+ assign $1\core_reg1$next[4:0]$1733 $3\core_reg1$next[4:0]$1835
+ assign $1\core_reg1_ok$next[0:0]$1734 $3\core_reg1_ok$next[0:0]$1836
+ assign $1\core_reg2$next[4:0]$1735 $3\core_reg2$next[4:0]$1837
+ assign $1\core_reg2_ok$next[0:0]$1736 $3\core_reg2_ok$next[0:0]$1838
+ assign $1\core_reg3$next[4:0]$1737 $3\core_reg3$next[4:0]$1839
+ assign $1\core_reg3_ok$next[0:0]$1738 $3\core_reg3_ok$next[0:0]$1840
+ assign $1\core_rego$next[4:0]$1739 $3\core_rego$next[4:0]$1841
+ assign $1\core_rego_ok$next[0:0]$1740 $3\core_rego_ok$next[0:0]$1842
+ assign $1\core_spr1$next[9:0]$1741 $3\core_spr1$next[9:0]$1843
+ assign $1\core_spr1_ok$next[0:0]$1742 $3\core_spr1_ok$next[0:0]$1844
+ assign $1\core_spro$next[9:0]$1743 $3\core_spro$next[9:0]$1845
+ assign $1\core_spro_ok$next[0:0]$1744 $3\core_spro_ok$next[0:0]$1846
+ assign $1\core_xer_in$next[2:0]$1745 $3\core_xer_in$next[2:0]$1847
+ assign $1\core_xer_out$next[0:0]$1746 $3\core_xer_out$next[0:0]$1848
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
switch \$41
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $3\core_core_is_32bit$next[0:0]$1768 $3\core_core_cr_wr_ok$next[0:0]$1763 $3\core_core_cr_wr$next[7:0]$1762 $3\core_core_cr_rd_ok$next[0:0]$1761 $3\core_core_cr_rd$next[7:0]$1760 $3\core_core_trapaddr$next[12:0]$1775 $3\core_core_traptype$next[6:0]$1776 $3\core_core_input_carry$next[1:0]$1765 $3\core_core_oe_ok$next[0:0]$1772 $3\core_core_oe$next[0:0]$1771 $3\core_core_rc_ok$next[0:0]$1774 $3\core_core_rc$next[0:0]$1773 $3\core_core_lk$next[0:0]$1769 $3\core_core_fn_unit$next[11:0]$1764 $3\core_core_insn_type$next[6:0]$1767 $3\core_core_insn$next[31:0]$1766 $3\core_core_cia$next[63:0]$1759 $3\core_core_msr$next[63:0]$1770 $3\core_cr_out_ok$next[0:0]$1784 $3\core_cr_out$next[2:0]$1783 $3\core_cr_in2_ok$40$next[0:0]$1781 $3\core_cr_in2$39$next[2:0]$1779 $3\core_cr_in2_ok$next[0:0]$1782 $3\core_cr_in2$next[2:0]$1780 $3\core_cr_in1_ok$next[0:0]$1778 $3\core_cr_in1$next[2:0]$1777 $3\core_fasto2_ok$next[0:0]$1794 $3\core_fasto2$next[2:0]$1793 $3\core_fasto1_ok$next[0:0]$1792 $3\core_fasto1$next[2:0]$1791 $3\core_fast2_ok$next[0:0]$1790 $3\core_fast2$next[2:0]$1789 $3\core_fast1_ok$next[0:0]$1788 $3\core_fast1$next[2:0]$1787 $3\core_xer_out$next[0:0]$1808 $3\core_xer_in$next[2:0]$1807 $3\core_spr1_ok$next[0:0]$1804 $3\core_spr1$next[9:0]$1803 $3\core_spro_ok$next[0:0]$1806 $3\core_spro$next[9:0]$1805 $3\core_reg3_ok$next[0:0]$1800 $3\core_reg3$next[4:0]$1799 $3\core_reg2_ok$next[0:0]$1798 $3\core_reg2$next[4:0]$1797 $3\core_reg1_ok$next[0:0]$1796 $3\core_reg1$next[4:0]$1795 $3\core_ea_ok$next[0:0]$1786 $3\core_ea$next[4:0]$1785 $3\core_rego_ok$next[0:0]$1802 $3\core_rego$next[4:0]$1801 $3\core_asmcode$next[7:0]$1758 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $3\core_core_is_32bit$next[0:0]$1808 $3\core_core_cr_wr_ok$next[0:0]$1803 $3\core_core_cr_wr$next[7:0]$1802 $3\core_core_cr_rd_ok$next[0:0]$1801 $3\core_core_cr_rd$next[7:0]$1800 $3\core_core_trapaddr$next[12:0]$1815 $3\core_core_traptype$next[6:0]$1816 $3\core_core_input_carry$next[1:0]$1805 $3\core_core_oe_ok$next[0:0]$1812 $3\core_core_oe$next[0:0]$1811 $3\core_core_rc_ok$next[0:0]$1814 $3\core_core_rc$next[0:0]$1813 $3\core_core_lk$next[0:0]$1809 $3\core_core_fn_unit$next[11:0]$1804 $3\core_core_insn_type$next[6:0]$1807 $3\core_core_insn$next[31:0]$1806 $3\core_core_cia$next[63:0]$1799 $3\core_core_msr$next[63:0]$1810 $3\core_cr_out_ok$next[0:0]$1824 $3\core_cr_out$next[2:0]$1823 $3\core_cr_in2_ok$40$next[0:0]$1821 $3\core_cr_in2$39$next[2:0]$1819 $3\core_cr_in2_ok$next[0:0]$1822 $3\core_cr_in2$next[2:0]$1820 $3\core_cr_in1_ok$next[0:0]$1818 $3\core_cr_in1$next[2:0]$1817 $3\core_fasto2_ok$next[0:0]$1834 $3\core_fasto2$next[2:0]$1833 $3\core_fasto1_ok$next[0:0]$1832 $3\core_fasto1$next[2:0]$1831 $3\core_fast2_ok$next[0:0]$1830 $3\core_fast2$next[2:0]$1829 $3\core_fast1_ok$next[0:0]$1828 $3\core_fast1$next[2:0]$1827 $3\core_xer_out$next[0:0]$1848 $3\core_xer_in$next[2:0]$1847 $3\core_spr1_ok$next[0:0]$1844 $3\core_spr1$next[9:0]$1843 $3\core_spro_ok$next[0:0]$1846 $3\core_spro$next[9:0]$1845 $3\core_reg3_ok$next[0:0]$1840 $3\core_reg3$next[4:0]$1839 $3\core_reg2_ok$next[0:0]$1838 $3\core_reg2$next[4:0]$1837 $3\core_reg1_ok$next[0:0]$1836 $3\core_reg1$next[4:0]$1835 $3\core_ea_ok$next[0:0]$1826 $3\core_ea$next[4:0]$1825 $3\core_rego_ok$next[0:0]$1842 $3\core_rego$next[4:0]$1841 $3\core_asmcode$next[7:0]$1798 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\core_asmcode$next[7:0]$1758 \core_asmcode
- assign $3\core_core_cia$next[63:0]$1759 \core_core_cia
- assign $3\core_core_cr_rd$next[7:0]$1760 \core_core_cr_rd
- assign $3\core_core_cr_rd_ok$next[0:0]$1761 \core_core_cr_rd_ok
- assign $3\core_core_cr_wr$next[7:0]$1762 \core_core_cr_wr
- assign $3\core_core_cr_wr_ok$next[0:0]$1763 \core_core_cr_wr_ok
- assign $3\core_core_fn_unit$next[11:0]$1764 \core_core_fn_unit
- assign $3\core_core_input_carry$next[1:0]$1765 \core_core_input_carry
- assign $3\core_core_insn$next[31:0]$1766 \core_core_insn
- assign $3\core_core_insn_type$next[6:0]$1767 \core_core_insn_type
- assign $3\core_core_is_32bit$next[0:0]$1768 \core_core_is_32bit
- assign $3\core_core_lk$next[0:0]$1769 \core_core_lk
- assign $3\core_core_msr$next[63:0]$1770 \core_core_msr
- assign $3\core_core_oe$next[0:0]$1771 \core_core_oe
- assign $3\core_core_oe_ok$next[0:0]$1772 \core_core_oe_ok
- assign $3\core_core_rc$next[0:0]$1773 \core_core_rc
- assign $3\core_core_rc_ok$next[0:0]$1774 \core_core_rc_ok
- assign $3\core_core_trapaddr$next[12:0]$1775 \core_core_trapaddr
- assign $3\core_core_traptype$next[6:0]$1776 \core_core_traptype
- assign $3\core_cr_in1$next[2:0]$1777 \core_cr_in1
- assign $3\core_cr_in1_ok$next[0:0]$1778 \core_cr_in1_ok
- assign $3\core_cr_in2$39$next[2:0]$1779 \core_cr_in2$39
- assign $3\core_cr_in2$next[2:0]$1780 \core_cr_in2
- assign $3\core_cr_in2_ok$40$next[0:0]$1781 \core_cr_in2_ok$40
- assign $3\core_cr_in2_ok$next[0:0]$1782 \core_cr_in2_ok
- assign $3\core_cr_out$next[2:0]$1783 \core_cr_out
- assign $3\core_cr_out_ok$next[0:0]$1784 \core_cr_out_ok
- assign $3\core_ea$next[4:0]$1785 \core_ea
- assign $3\core_ea_ok$next[0:0]$1786 \core_ea_ok
- assign $3\core_fast1$next[2:0]$1787 \core_fast1
- assign $3\core_fast1_ok$next[0:0]$1788 \core_fast1_ok
- assign $3\core_fast2$next[2:0]$1789 \core_fast2
- assign $3\core_fast2_ok$next[0:0]$1790 \core_fast2_ok
- assign $3\core_fasto1$next[2:0]$1791 \core_fasto1
- assign $3\core_fasto1_ok$next[0:0]$1792 \core_fasto1_ok
- assign $3\core_fasto2$next[2:0]$1793 \core_fasto2
- assign $3\core_fasto2_ok$next[0:0]$1794 \core_fasto2_ok
- assign $3\core_reg1$next[4:0]$1795 \core_reg1
- assign $3\core_reg1_ok$next[0:0]$1796 \core_reg1_ok
- assign $3\core_reg2$next[4:0]$1797 \core_reg2
- assign $3\core_reg2_ok$next[0:0]$1798 \core_reg2_ok
- assign $3\core_reg3$next[4:0]$1799 \core_reg3
- assign $3\core_reg3_ok$next[0:0]$1800 \core_reg3_ok
- assign $3\core_rego$next[4:0]$1801 \core_rego
- assign $3\core_rego_ok$next[0:0]$1802 \core_rego_ok
- assign $3\core_spr1$next[9:0]$1803 \core_spr1
- assign $3\core_spr1_ok$next[0:0]$1804 \core_spr1_ok
- assign $3\core_spro$next[9:0]$1805 \core_spro
- assign $3\core_spro_ok$next[0:0]$1806 \core_spro_ok
- assign $3\core_xer_in$next[2:0]$1807 \core_xer_in
- assign $3\core_xer_out$next[0:0]$1808 \core_xer_out
+ assign $3\core_asmcode$next[7:0]$1798 \core_asmcode
+ assign $3\core_core_cia$next[63:0]$1799 \core_core_cia
+ assign $3\core_core_cr_rd$next[7:0]$1800 \core_core_cr_rd
+ assign $3\core_core_cr_rd_ok$next[0:0]$1801 \core_core_cr_rd_ok
+ assign $3\core_core_cr_wr$next[7:0]$1802 \core_core_cr_wr
+ assign $3\core_core_cr_wr_ok$next[0:0]$1803 \core_core_cr_wr_ok
+ assign $3\core_core_fn_unit$next[11:0]$1804 \core_core_fn_unit
+ assign $3\core_core_input_carry$next[1:0]$1805 \core_core_input_carry
+ assign $3\core_core_insn$next[31:0]$1806 \core_core_insn
+ assign $3\core_core_insn_type$next[6:0]$1807 \core_core_insn_type
+ assign $3\core_core_is_32bit$next[0:0]$1808 \core_core_is_32bit
+ assign $3\core_core_lk$next[0:0]$1809 \core_core_lk
+ assign $3\core_core_msr$next[63:0]$1810 \core_core_msr
+ assign $3\core_core_oe$next[0:0]$1811 \core_core_oe
+ assign $3\core_core_oe_ok$next[0:0]$1812 \core_core_oe_ok
+ assign $3\core_core_rc$next[0:0]$1813 \core_core_rc
+ assign $3\core_core_rc_ok$next[0:0]$1814 \core_core_rc_ok
+ assign $3\core_core_trapaddr$next[12:0]$1815 \core_core_trapaddr
+ assign $3\core_core_traptype$next[6:0]$1816 \core_core_traptype
+ assign $3\core_cr_in1$next[2:0]$1817 \core_cr_in1
+ assign $3\core_cr_in1_ok$next[0:0]$1818 \core_cr_in1_ok
+ assign $3\core_cr_in2$39$next[2:0]$1819 \core_cr_in2$39
+ assign $3\core_cr_in2$next[2:0]$1820 \core_cr_in2
+ assign $3\core_cr_in2_ok$40$next[0:0]$1821 \core_cr_in2_ok$40
+ assign $3\core_cr_in2_ok$next[0:0]$1822 \core_cr_in2_ok
+ assign $3\core_cr_out$next[2:0]$1823 \core_cr_out
+ assign $3\core_cr_out_ok$next[0:0]$1824 \core_cr_out_ok
+ assign $3\core_ea$next[4:0]$1825 \core_ea
+ assign $3\core_ea_ok$next[0:0]$1826 \core_ea_ok
+ assign $3\core_fast1$next[2:0]$1827 \core_fast1
+ assign $3\core_fast1_ok$next[0:0]$1828 \core_fast1_ok
+ assign $3\core_fast2$next[2:0]$1829 \core_fast2
+ assign $3\core_fast2_ok$next[0:0]$1830 \core_fast2_ok
+ assign $3\core_fasto1$next[2:0]$1831 \core_fasto1
+ assign $3\core_fasto1_ok$next[0:0]$1832 \core_fasto1_ok
+ assign $3\core_fasto2$next[2:0]$1833 \core_fasto2
+ assign $3\core_fasto2_ok$next[0:0]$1834 \core_fasto2_ok
+ assign $3\core_reg1$next[4:0]$1835 \core_reg1
+ assign $3\core_reg1_ok$next[0:0]$1836 \core_reg1_ok
+ assign $3\core_reg2$next[4:0]$1837 \core_reg2
+ assign $3\core_reg2_ok$next[0:0]$1838 \core_reg2_ok
+ assign $3\core_reg3$next[4:0]$1839 \core_reg3
+ assign $3\core_reg3_ok$next[0:0]$1840 \core_reg3_ok
+ assign $3\core_rego$next[4:0]$1841 \core_rego
+ assign $3\core_rego_ok$next[0:0]$1842 \core_rego_ok
+ assign $3\core_spr1$next[9:0]$1843 \core_spr1
+ assign $3\core_spr1_ok$next[0:0]$1844 \core_spr1_ok
+ assign $3\core_spro$next[9:0]$1845 \core_spro
+ assign $3\core_spro_ok$next[0:0]$1846 \core_spro_ok
+ assign $3\core_xer_in$next[2:0]$1847 \core_xer_in
+ assign $3\core_xer_out$next[0:0]$1848 \core_xer_out
end
case
- assign $1\core_asmcode$next[7:0]$1656 \core_asmcode
- assign $1\core_core_cia$next[63:0]$1657 \core_core_cia
- assign $1\core_core_cr_rd$next[7:0]$1658 \core_core_cr_rd
- assign $1\core_core_cr_rd_ok$next[0:0]$1659 \core_core_cr_rd_ok
- assign $1\core_core_cr_wr$next[7:0]$1660 \core_core_cr_wr
- assign $1\core_core_cr_wr_ok$next[0:0]$1661 \core_core_cr_wr_ok
- assign $1\core_core_fn_unit$next[11:0]$1662 \core_core_fn_unit
- assign $1\core_core_input_carry$next[1:0]$1663 \core_core_input_carry
- assign $1\core_core_insn$next[31:0]$1664 \core_core_insn
- assign $1\core_core_insn_type$next[6:0]$1665 \core_core_insn_type
- assign $1\core_core_is_32bit$next[0:0]$1666 \core_core_is_32bit
- assign $1\core_core_lk$next[0:0]$1667 \core_core_lk
- assign $1\core_core_msr$next[63:0]$1668 \core_core_msr
- assign $1\core_core_oe$next[0:0]$1669 \core_core_oe
- assign $1\core_core_oe_ok$next[0:0]$1670 \core_core_oe_ok
- assign $1\core_core_rc$next[0:0]$1671 \core_core_rc
- assign $1\core_core_rc_ok$next[0:0]$1672 \core_core_rc_ok
- assign $1\core_core_trapaddr$next[12:0]$1673 \core_core_trapaddr
- assign $1\core_core_traptype$next[6:0]$1674 \core_core_traptype
- assign $1\core_cr_in1$next[2:0]$1675 \core_cr_in1
- assign $1\core_cr_in1_ok$next[0:0]$1676 \core_cr_in1_ok
- assign $1\core_cr_in2$39$next[2:0]$1677 \core_cr_in2$39
- assign $1\core_cr_in2$next[2:0]$1678 \core_cr_in2
- assign $1\core_cr_in2_ok$40$next[0:0]$1679 \core_cr_in2_ok$40
- assign $1\core_cr_in2_ok$next[0:0]$1680 \core_cr_in2_ok
- assign $1\core_cr_out$next[2:0]$1681 \core_cr_out
- assign $1\core_cr_out_ok$next[0:0]$1682 \core_cr_out_ok
- assign $1\core_ea$next[4:0]$1683 \core_ea
- assign $1\core_ea_ok$next[0:0]$1684 \core_ea_ok
- assign $1\core_fast1$next[2:0]$1685 \core_fast1
- assign $1\core_fast1_ok$next[0:0]$1686 \core_fast1_ok
- assign $1\core_fast2$next[2:0]$1687 \core_fast2
- assign $1\core_fast2_ok$next[0:0]$1688 \core_fast2_ok
- assign $1\core_fasto1$next[2:0]$1689 \core_fasto1
- assign $1\core_fasto1_ok$next[0:0]$1690 \core_fasto1_ok
- assign $1\core_fasto2$next[2:0]$1691 \core_fasto2
- assign $1\core_fasto2_ok$next[0:0]$1692 \core_fasto2_ok
- assign $1\core_reg1$next[4:0]$1693 \core_reg1
- assign $1\core_reg1_ok$next[0:0]$1694 \core_reg1_ok
- assign $1\core_reg2$next[4:0]$1695 \core_reg2
- assign $1\core_reg2_ok$next[0:0]$1696 \core_reg2_ok
- assign $1\core_reg3$next[4:0]$1697 \core_reg3
- assign $1\core_reg3_ok$next[0:0]$1698 \core_reg3_ok
- assign $1\core_rego$next[4:0]$1699 \core_rego
- assign $1\core_rego_ok$next[0:0]$1700 \core_rego_ok
- assign $1\core_spr1$next[9:0]$1701 \core_spr1
- assign $1\core_spr1_ok$next[0:0]$1702 \core_spr1_ok
- assign $1\core_spro$next[9:0]$1703 \core_spro
- assign $1\core_spro_ok$next[0:0]$1704 \core_spro_ok
- assign $1\core_xer_in$next[2:0]$1705 \core_xer_in
- assign $1\core_xer_out$next[0:0]$1706 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$1696 \core_asmcode
+ assign $1\core_core_cia$next[63:0]$1697 \core_core_cia
+ assign $1\core_core_cr_rd$next[7:0]$1698 \core_core_cr_rd
+ assign $1\core_core_cr_rd_ok$next[0:0]$1699 \core_core_cr_rd_ok
+ assign $1\core_core_cr_wr$next[7:0]$1700 \core_core_cr_wr
+ assign $1\core_core_cr_wr_ok$next[0:0]$1701 \core_core_cr_wr_ok
+ assign $1\core_core_fn_unit$next[11:0]$1702 \core_core_fn_unit
+ assign $1\core_core_input_carry$next[1:0]$1703 \core_core_input_carry
+ assign $1\core_core_insn$next[31:0]$1704 \core_core_insn
+ assign $1\core_core_insn_type$next[6:0]$1705 \core_core_insn_type
+ assign $1\core_core_is_32bit$next[0:0]$1706 \core_core_is_32bit
+ assign $1\core_core_lk$next[0:0]$1707 \core_core_lk
+ assign $1\core_core_msr$next[63:0]$1708 \core_core_msr
+ assign $1\core_core_oe$next[0:0]$1709 \core_core_oe
+ assign $1\core_core_oe_ok$next[0:0]$1710 \core_core_oe_ok
+ assign $1\core_core_rc$next[0:0]$1711 \core_core_rc
+ assign $1\core_core_rc_ok$next[0:0]$1712 \core_core_rc_ok
+ assign $1\core_core_trapaddr$next[12:0]$1713 \core_core_trapaddr
+ assign $1\core_core_traptype$next[6:0]$1714 \core_core_traptype
+ assign $1\core_cr_in1$next[2:0]$1715 \core_cr_in1
+ assign $1\core_cr_in1_ok$next[0:0]$1716 \core_cr_in1_ok
+ assign $1\core_cr_in2$39$next[2:0]$1717 \core_cr_in2$39
+ assign $1\core_cr_in2$next[2:0]$1718 \core_cr_in2
+ assign $1\core_cr_in2_ok$40$next[0:0]$1719 \core_cr_in2_ok$40
+ assign $1\core_cr_in2_ok$next[0:0]$1720 \core_cr_in2_ok
+ assign $1\core_cr_out$next[2:0]$1721 \core_cr_out
+ assign $1\core_cr_out_ok$next[0:0]$1722 \core_cr_out_ok
+ assign $1\core_ea$next[4:0]$1723 \core_ea
+ assign $1\core_ea_ok$next[0:0]$1724 \core_ea_ok
+ assign $1\core_fast1$next[2:0]$1725 \core_fast1
+ assign $1\core_fast1_ok$next[0:0]$1726 \core_fast1_ok
+ assign $1\core_fast2$next[2:0]$1727 \core_fast2
+ assign $1\core_fast2_ok$next[0:0]$1728 \core_fast2_ok
+ assign $1\core_fasto1$next[2:0]$1729 \core_fasto1
+ assign $1\core_fasto1_ok$next[0:0]$1730 \core_fasto1_ok
+ assign $1\core_fasto2$next[2:0]$1731 \core_fasto2
+ assign $1\core_fasto2_ok$next[0:0]$1732 \core_fasto2_ok
+ assign $1\core_reg1$next[4:0]$1733 \core_reg1
+ assign $1\core_reg1_ok$next[0:0]$1734 \core_reg1_ok
+ assign $1\core_reg2$next[4:0]$1735 \core_reg2
+ assign $1\core_reg2_ok$next[0:0]$1736 \core_reg2_ok
+ assign $1\core_reg3$next[4:0]$1737 \core_reg3
+ assign $1\core_reg3_ok$next[0:0]$1738 \core_reg3_ok
+ assign $1\core_rego$next[4:0]$1739 \core_rego
+ assign $1\core_rego_ok$next[0:0]$1740 \core_rego_ok
+ assign $1\core_spr1$next[9:0]$1741 \core_spr1
+ assign $1\core_spr1_ok$next[0:0]$1742 \core_spr1_ok
+ assign $1\core_spro$next[9:0]$1743 \core_spro
+ assign $1\core_spro_ok$next[0:0]$1744 \core_spro_ok
+ assign $1\core_xer_in$next[2:0]$1745 \core_xer_in
+ assign $1\core_xer_out$next[0:0]$1746 \core_xer_out
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign { } { }
- assign $4\core_rego_ok$next[0:0]$1825 1'0
- assign $4\core_ea_ok$next[0:0]$1817 1'0
- assign $4\core_reg1_ok$next[0:0]$1822 1'0
- assign $4\core_reg2_ok$next[0:0]$1823 1'0
- assign $4\core_reg3_ok$next[0:0]$1824 1'0
- assign $4\core_spro_ok$next[0:0]$1827 1'0
- assign $4\core_spr1_ok$next[0:0]$1826 1'0
- assign $4\core_fast1_ok$next[0:0]$1818 1'0
- assign $4\core_fast2_ok$next[0:0]$1819 1'0
- assign $4\core_fasto1_ok$next[0:0]$1820 1'0
- assign $4\core_fasto2_ok$next[0:0]$1821 1'0
- assign $4\core_cr_in1_ok$next[0:0]$1813 1'0
- assign $4\core_cr_in2_ok$next[0:0]$1815 1'0
- assign $4\core_cr_in2_ok$40$next[0:0]$1814 1'0
- assign $4\core_cr_out_ok$next[0:0]$1816 1'0
- assign $4\core_core_rc_ok$next[0:0]$1812 1'0
- assign $4\core_core_oe_ok$next[0:0]$1811 1'0
- assign $4\core_core_cr_rd_ok$next[0:0]$1809 1'0
- assign $4\core_core_cr_wr_ok$next[0:0]$1810 1'0
+ switch \intclk_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign { } { }
+ assign $4\core_rego_ok$next[0:0]$1865 1'0
+ assign $4\core_ea_ok$next[0:0]$1857 1'0
+ assign $4\core_reg1_ok$next[0:0]$1862 1'0
+ assign $4\core_reg2_ok$next[0:0]$1863 1'0
+ assign $4\core_reg3_ok$next[0:0]$1864 1'0
+ assign $4\core_spro_ok$next[0:0]$1867 1'0
+ assign $4\core_spr1_ok$next[0:0]$1866 1'0
+ assign $4\core_fast1_ok$next[0:0]$1858 1'0
+ assign $4\core_fast2_ok$next[0:0]$1859 1'0
+ assign $4\core_fasto1_ok$next[0:0]$1860 1'0
+ assign $4\core_fasto2_ok$next[0:0]$1861 1'0
+ assign $4\core_cr_in1_ok$next[0:0]$1853 1'0
+ assign $4\core_cr_in2_ok$next[0:0]$1855 1'0
+ assign $4\core_cr_in2_ok$40$next[0:0]$1854 1'0
+ assign $4\core_cr_out_ok$next[0:0]$1856 1'0
+ assign $4\core_core_rc_ok$next[0:0]$1852 1'0
+ assign $4\core_core_oe_ok$next[0:0]$1851 1'0
+ assign $4\core_core_cr_rd_ok$next[0:0]$1849 1'0
+ assign $4\core_core_cr_wr_ok$next[0:0]$1850 1'0
case
- assign $4\core_core_cr_rd_ok$next[0:0]$1809 $1\core_core_cr_rd_ok$next[0:0]$1659
- assign $4\core_core_cr_wr_ok$next[0:0]$1810 $1\core_core_cr_wr_ok$next[0:0]$1661
- assign $4\core_core_oe_ok$next[0:0]$1811 $1\core_core_oe_ok$next[0:0]$1670
- assign $4\core_core_rc_ok$next[0:0]$1812 $1\core_core_rc_ok$next[0:0]$1672
- assign $4\core_cr_in1_ok$next[0:0]$1813 $1\core_cr_in1_ok$next[0:0]$1676
- assign $4\core_cr_in2_ok$40$next[0:0]$1814 $1\core_cr_in2_ok$40$next[0:0]$1679
- assign $4\core_cr_in2_ok$next[0:0]$1815 $1\core_cr_in2_ok$next[0:0]$1680
- assign $4\core_cr_out_ok$next[0:0]$1816 $1\core_cr_out_ok$next[0:0]$1682
- assign $4\core_ea_ok$next[0:0]$1817 $1\core_ea_ok$next[0:0]$1684
- assign $4\core_fast1_ok$next[0:0]$1818 $1\core_fast1_ok$next[0:0]$1686
- assign $4\core_fast2_ok$next[0:0]$1819 $1\core_fast2_ok$next[0:0]$1688
- assign $4\core_fasto1_ok$next[0:0]$1820 $1\core_fasto1_ok$next[0:0]$1690
- assign $4\core_fasto2_ok$next[0:0]$1821 $1\core_fasto2_ok$next[0:0]$1692
- assign $4\core_reg1_ok$next[0:0]$1822 $1\core_reg1_ok$next[0:0]$1694
- assign $4\core_reg2_ok$next[0:0]$1823 $1\core_reg2_ok$next[0:0]$1696
- assign $4\core_reg3_ok$next[0:0]$1824 $1\core_reg3_ok$next[0:0]$1698
- assign $4\core_rego_ok$next[0:0]$1825 $1\core_rego_ok$next[0:0]$1700
- assign $4\core_spr1_ok$next[0:0]$1826 $1\core_spr1_ok$next[0:0]$1702
- assign $4\core_spro_ok$next[0:0]$1827 $1\core_spro_ok$next[0:0]$1704
+ assign $4\core_core_cr_rd_ok$next[0:0]$1849 $1\core_core_cr_rd_ok$next[0:0]$1699
+ assign $4\core_core_cr_wr_ok$next[0:0]$1850 $1\core_core_cr_wr_ok$next[0:0]$1701
+ assign $4\core_core_oe_ok$next[0:0]$1851 $1\core_core_oe_ok$next[0:0]$1710
+ assign $4\core_core_rc_ok$next[0:0]$1852 $1\core_core_rc_ok$next[0:0]$1712
+ assign $4\core_cr_in1_ok$next[0:0]$1853 $1\core_cr_in1_ok$next[0:0]$1716
+ assign $4\core_cr_in2_ok$40$next[0:0]$1854 $1\core_cr_in2_ok$40$next[0:0]$1719
+ assign $4\core_cr_in2_ok$next[0:0]$1855 $1\core_cr_in2_ok$next[0:0]$1720
+ assign $4\core_cr_out_ok$next[0:0]$1856 $1\core_cr_out_ok$next[0:0]$1722
+ assign $4\core_ea_ok$next[0:0]$1857 $1\core_ea_ok$next[0:0]$1724
+ assign $4\core_fast1_ok$next[0:0]$1858 $1\core_fast1_ok$next[0:0]$1726
+ assign $4\core_fast2_ok$next[0:0]$1859 $1\core_fast2_ok$next[0:0]$1728
+ assign $4\core_fasto1_ok$next[0:0]$1860 $1\core_fasto1_ok$next[0:0]$1730
+ assign $4\core_fasto2_ok$next[0:0]$1861 $1\core_fasto2_ok$next[0:0]$1732
+ assign $4\core_reg1_ok$next[0:0]$1862 $1\core_reg1_ok$next[0:0]$1734
+ assign $4\core_reg2_ok$next[0:0]$1863 $1\core_reg2_ok$next[0:0]$1736
+ assign $4\core_reg3_ok$next[0:0]$1864 $1\core_reg3_ok$next[0:0]$1738
+ assign $4\core_rego_ok$next[0:0]$1865 $1\core_rego_ok$next[0:0]$1740
+ assign $4\core_spr1_ok$next[0:0]$1866 $1\core_spr1_ok$next[0:0]$1742
+ assign $4\core_spro_ok$next[0:0]$1867 $1\core_spro_ok$next[0:0]$1744
end
sync always
- update \core_asmcode$next $0\core_asmcode$next[7:0]$1605
- update \core_core_cia$next $0\core_core_cia$next[63:0]$1606
- update \core_core_cr_rd$next $0\core_core_cr_rd$next[7:0]$1607
- update \core_core_cr_rd_ok$next $0\core_core_cr_rd_ok$next[0:0]$1608
- update \core_core_cr_wr$next $0\core_core_cr_wr$next[7:0]$1609
- update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$1610
- update \core_core_fn_unit$next $0\core_core_fn_unit$next[11:0]$1611
- update \core_core_input_carry$next $0\core_core_input_carry$next[1:0]$1612
- update \core_core_insn$next $0\core_core_insn$next[31:0]$1613
- update \core_core_insn_type$next $0\core_core_insn_type$next[6:0]$1614
- update \core_core_is_32bit$next $0\core_core_is_32bit$next[0:0]$1615
- update \core_core_lk$next $0\core_core_lk$next[0:0]$1616
- update \core_core_msr$next $0\core_core_msr$next[63:0]$1617
- update \core_core_oe$next $0\core_core_oe$next[0:0]$1618
- update \core_core_oe_ok$next $0\core_core_oe_ok$next[0:0]$1619
- update \core_core_rc$next $0\core_core_rc$next[0:0]$1620
- update \core_core_rc_ok$next $0\core_core_rc_ok$next[0:0]$1621
- update \core_core_trapaddr$next $0\core_core_trapaddr$next[12:0]$1622
- update \core_core_traptype$next $0\core_core_traptype$next[6:0]$1623
- update \core_cr_in1$next $0\core_cr_in1$next[2:0]$1624
- update \core_cr_in1_ok$next $0\core_cr_in1_ok$next[0:0]$1625
- update \core_cr_in2$39$next $0\core_cr_in2$39$next[2:0]$1626
- update \core_cr_in2$next $0\core_cr_in2$next[2:0]$1627
- update \core_cr_in2_ok$40$next $0\core_cr_in2_ok$40$next[0:0]$1628
- update \core_cr_in2_ok$next $0\core_cr_in2_ok$next[0:0]$1629
- update \core_cr_out$next $0\core_cr_out$next[2:0]$1630
- update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$1631
- update \core_ea$next $0\core_ea$next[4:0]$1632
- update \core_ea_ok$next $0\core_ea_ok$next[0:0]$1633
- update \core_fast1$next $0\core_fast1$next[2:0]$1634
- update \core_fast1_ok$next $0\core_fast1_ok$next[0:0]$1635
- update \core_fast2$next $0\core_fast2$next[2:0]$1636
- update \core_fast2_ok$next $0\core_fast2_ok$next[0:0]$1637
- update \core_fasto1$next $0\core_fasto1$next[2:0]$1638
- update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$1639
- update \core_fasto2$next $0\core_fasto2$next[2:0]$1640
- update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$1641
- update \core_reg1$next $0\core_reg1$next[4:0]$1642
- update \core_reg1_ok$next $0\core_reg1_ok$next[0:0]$1643
- update \core_reg2$next $0\core_reg2$next[4:0]$1644
- update \core_reg2_ok$next $0\core_reg2_ok$next[0:0]$1645
- update \core_reg3$next $0\core_reg3$next[4:0]$1646
- update \core_reg3_ok$next $0\core_reg3_ok$next[0:0]$1647
- update \core_rego$next $0\core_rego$next[4:0]$1648
- update \core_rego_ok$next $0\core_rego_ok$next[0:0]$1649
- update \core_spr1$next $0\core_spr1$next[9:0]$1650
- update \core_spr1_ok$next $0\core_spr1_ok$next[0:0]$1651
- update \core_spro$next $0\core_spro$next[9:0]$1652
- update \core_spro_ok$next $0\core_spro_ok$next[0:0]$1653
- update \core_xer_in$next $0\core_xer_in$next[2:0]$1654
- update \core_xer_out$next $0\core_xer_out$next[0:0]$1655
- end
- attribute \src "libresoc.v:49043.3-49051.6"
- process $proc$libresoc.v:49043$1828
- assign { } { }
- assign { } { }
- assign $0\jtag_dmi0_ack_o$next[0:0]$1829 $1\jtag_dmi0_ack_o$next[0:0]$1830
- attribute \src "libresoc.v:49044.5-49044.29"
- switch \initial
- attribute \src "libresoc.v:49044.9-49044.17"
+ update \core_asmcode$next $0\core_asmcode$next[7:0]$1645
+ update \core_core_cia$next $0\core_core_cia$next[63:0]$1646
+ update \core_core_cr_rd$next $0\core_core_cr_rd$next[7:0]$1647
+ update \core_core_cr_rd_ok$next $0\core_core_cr_rd_ok$next[0:0]$1648
+ update \core_core_cr_wr$next $0\core_core_cr_wr$next[7:0]$1649
+ update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$1650
+ update \core_core_fn_unit$next $0\core_core_fn_unit$next[11:0]$1651
+ update \core_core_input_carry$next $0\core_core_input_carry$next[1:0]$1652
+ update \core_core_insn$next $0\core_core_insn$next[31:0]$1653
+ update \core_core_insn_type$next $0\core_core_insn_type$next[6:0]$1654
+ update \core_core_is_32bit$next $0\core_core_is_32bit$next[0:0]$1655
+ update \core_core_lk$next $0\core_core_lk$next[0:0]$1656
+ update \core_core_msr$next $0\core_core_msr$next[63:0]$1657
+ update \core_core_oe$next $0\core_core_oe$next[0:0]$1658
+ update \core_core_oe_ok$next $0\core_core_oe_ok$next[0:0]$1659
+ update \core_core_rc$next $0\core_core_rc$next[0:0]$1660
+ update \core_core_rc_ok$next $0\core_core_rc_ok$next[0:0]$1661
+ update \core_core_trapaddr$next $0\core_core_trapaddr$next[12:0]$1662
+ update \core_core_traptype$next $0\core_core_traptype$next[6:0]$1663
+ update \core_cr_in1$next $0\core_cr_in1$next[2:0]$1664
+ update \core_cr_in1_ok$next $0\core_cr_in1_ok$next[0:0]$1665
+ update \core_cr_in2$39$next $0\core_cr_in2$39$next[2:0]$1666
+ update \core_cr_in2$next $0\core_cr_in2$next[2:0]$1667
+ update \core_cr_in2_ok$40$next $0\core_cr_in2_ok$40$next[0:0]$1668
+ update \core_cr_in2_ok$next $0\core_cr_in2_ok$next[0:0]$1669
+ update \core_cr_out$next $0\core_cr_out$next[2:0]$1670
+ update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$1671
+ update \core_ea$next $0\core_ea$next[4:0]$1672
+ update \core_ea_ok$next $0\core_ea_ok$next[0:0]$1673
+ update \core_fast1$next $0\core_fast1$next[2:0]$1674
+ update \core_fast1_ok$next $0\core_fast1_ok$next[0:0]$1675
+ update \core_fast2$next $0\core_fast2$next[2:0]$1676
+ update \core_fast2_ok$next $0\core_fast2_ok$next[0:0]$1677
+ update \core_fasto1$next $0\core_fasto1$next[2:0]$1678
+ update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$1679
+ update \core_fasto2$next $0\core_fasto2$next[2:0]$1680
+ update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$1681
+ update \core_reg1$next $0\core_reg1$next[4:0]$1682
+ update \core_reg1_ok$next $0\core_reg1_ok$next[0:0]$1683
+ update \core_reg2$next $0\core_reg2$next[4:0]$1684
+ update \core_reg2_ok$next $0\core_reg2_ok$next[0:0]$1685
+ update \core_reg3$next $0\core_reg3$next[4:0]$1686
+ update \core_reg3_ok$next $0\core_reg3_ok$next[0:0]$1687
+ update \core_rego$next $0\core_rego$next[4:0]$1688
+ update \core_rego_ok$next $0\core_rego_ok$next[0:0]$1689
+ update \core_spr1$next $0\core_spr1$next[9:0]$1690
+ update \core_spr1_ok$next $0\core_spr1_ok$next[0:0]$1691
+ update \core_spro$next $0\core_spro$next[9:0]$1692
+ update \core_spro_ok$next $0\core_spro_ok$next[0:0]$1693
+ update \core_xer_in$next $0\core_xer_in$next[2:0]$1694
+ update \core_xer_out$next $0\core_xer_out$next[0:0]$1695
+ end
+ attribute \src "libresoc.v:49720.3-49728.6"
+ process $proc$libresoc.v:49720$1868
+ assign { } { }
+ assign { } { }
+ assign $0\jtag_dmi0_ack_o$next[0:0]$1869 $1\jtag_dmi0_ack_o$next[0:0]$1870
+ attribute \src "libresoc.v:49721.5-49721.29"
+ switch \initial
+ attribute \src "libresoc.v:49721.9-49721.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_dmi0_ack_o$next[0:0]$1830 1'0
+ assign $1\jtag_dmi0_ack_o$next[0:0]$1870 1'0
case
- assign $1\jtag_dmi0_ack_o$next[0:0]$1830 \dbg_dmi_ack_o
+ assign $1\jtag_dmi0_ack_o$next[0:0]$1870 \dbg_dmi_ack_o
end
sync always
- update \jtag_dmi0_ack_o$next $0\jtag_dmi0_ack_o$next[0:0]$1829
+ update \jtag_dmi0_ack_o$next $0\jtag_dmi0_ack_o$next[0:0]$1869
end
- attribute \src "libresoc.v:49052.3-49060.6"
- process $proc$libresoc.v:49052$1831
+ attribute \src "libresoc.v:49729.3-49737.6"
+ process $proc$libresoc.v:49729$1871
assign { } { }
assign { } { }
- assign $0\jtag_dmi0_dout$next[63:0]$1832 $1\jtag_dmi0_dout$next[63:0]$1833
- attribute \src "libresoc.v:49053.5-49053.29"
+ assign $0\jtag_dmi0_dout$next[63:0]$1872 $1\jtag_dmi0_dout$next[63:0]$1873
+ attribute \src "libresoc.v:49730.5-49730.29"
switch \initial
- attribute \src "libresoc.v:49053.9-49053.17"
+ attribute \src "libresoc.v:49730.9-49730.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_dmi0_dout$next[63:0]$1833 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\jtag_dmi0_dout$next[63:0]$1873 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $1\jtag_dmi0_dout$next[63:0]$1833 \dbg_dmi_dout
+ assign $1\jtag_dmi0_dout$next[63:0]$1873 \dbg_dmi_dout
end
sync always
- update \jtag_dmi0_dout$next $0\jtag_dmi0_dout$next[63:0]$1832
+ update \jtag_dmi0_dout$next $0\jtag_dmi0_dout$next[63:0]$1872
end
- attribute \src "libresoc.v:49061.3-49069.6"
- process $proc$libresoc.v:49061$1834
+ attribute \src "libresoc.v:49738.3-49746.6"
+ process $proc$libresoc.v:49738$1874
assign { } { }
assign { } { }
- assign $0\dec2_cur_eint$next[0:0]$1835 $1\dec2_cur_eint$next[0:0]$1836
- attribute \src "libresoc.v:49062.5-49062.29"
+ assign $0\dec2_cur_eint$next[0:0]$1875 $1\dec2_cur_eint$next[0:0]$1876
+ attribute \src "libresoc.v:49739.5-49739.29"
switch \initial
- attribute \src "libresoc.v:49062.9-49062.17"
+ attribute \src "libresoc.v:49739.9-49739.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dec2_cur_eint$next[0:0]$1836 1'0
+ assign $1\dec2_cur_eint$next[0:0]$1876 1'0
case
- assign $1\dec2_cur_eint$next[0:0]$1836 \xics_icp_core_irq_o
+ assign $1\dec2_cur_eint$next[0:0]$1876 \xics_icp_core_irq_o
end
sync always
- update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$1835
+ update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$1875
end
- attribute \src "libresoc.v:49070.3-49106.6"
- process $proc$libresoc.v:49070$1837
+ attribute \src "libresoc.v:49747.3-49783.6"
+ process $proc$libresoc.v:49747$1877
assign { } { }
assign { } { }
assign { } { }
- assign $0\raw_insn_i$next[31:0]$1838 $4\raw_insn_i$next[31:0]$1842
- attribute \src "libresoc.v:49071.5-49071.29"
+ assign $0\raw_insn_i$next[31:0]$1878 $4\raw_insn_i$next[31:0]$1882
+ attribute \src "libresoc.v:49748.5-49748.29"
switch \initial
- attribute \src "libresoc.v:49071.9-49071.17"
+ attribute \src "libresoc.v:49748.9-49748.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\raw_insn_i$next[31:0]$1839 0
+ assign $1\raw_insn_i$next[31:0]$1879 0
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\raw_insn_i$next[31:0]$1839 $2\raw_insn_i$next[31:0]$1840
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258"
+ assign $1\raw_insn_i$next[31:0]$1879 $2\raw_insn_i$next[31:0]$1880
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\raw_insn_i$next[31:0]$1840 \raw_insn_i
+ assign $2\raw_insn_i$next[31:0]$1880 \raw_insn_i
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\raw_insn_i$next[31:0]$1840 \dec2_raw_opcode_in
+ assign $2\raw_insn_i$next[31:0]$1880 \dec2_raw_opcode_in
end
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\raw_insn_i$next[31:0]$1839 $3\raw_insn_i$next[31:0]$1841
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ assign $1\raw_insn_i$next[31:0]$1879 $3\raw_insn_i$next[31:0]$1881
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
switch \$43
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\raw_insn_i$next[31:0]$1841 0
+ assign $3\raw_insn_i$next[31:0]$1881 0
case
- assign $3\raw_insn_i$next[31:0]$1841 \raw_insn_i
+ assign $3\raw_insn_i$next[31:0]$1881 \raw_insn_i
end
case
- assign $1\raw_insn_i$next[31:0]$1839 \raw_insn_i
+ assign $1\raw_insn_i$next[31:0]$1879 \raw_insn_i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\raw_insn_i$next[31:0]$1842 0
+ assign $4\raw_insn_i$next[31:0]$1882 0
case
- assign $4\raw_insn_i$next[31:0]$1842 $1\raw_insn_i$next[31:0]$1839
+ assign $4\raw_insn_i$next[31:0]$1882 $1\raw_insn_i$next[31:0]$1879
end
sync always
- update \raw_insn_i$next $0\raw_insn_i$next[31:0]$1838
+ update \raw_insn_i$next $0\raw_insn_i$next[31:0]$1878
end
- attribute \src "libresoc.v:49107.3-49143.6"
- process $proc$libresoc.v:49107$1843
+ attribute \src "libresoc.v:49784.3-49820.6"
+ process $proc$libresoc.v:49784$1883
assign { } { }
assign { } { }
assign { } { }
- assign $0\bigendian_i$next[0:0]$1844 $4\bigendian_i$next[0:0]$1848
- attribute \src "libresoc.v:49108.5-49108.29"
+ assign $0\bigendian_i$next[0:0]$1884 $4\bigendian_i$next[0:0]$1888
+ attribute \src "libresoc.v:49785.5-49785.29"
switch \initial
- attribute \src "libresoc.v:49108.9-49108.17"
+ attribute \src "libresoc.v:49785.9-49785.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\bigendian_i$next[0:0]$1845 1'0
+ assign $1\bigendian_i$next[0:0]$1885 1'0
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\bigendian_i$next[0:0]$1845 $2\bigendian_i$next[0:0]$1846
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258"
+ assign $1\bigendian_i$next[0:0]$1885 $2\bigendian_i$next[0:0]$1886
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\bigendian_i$next[0:0]$1846 \bigendian_i
+ assign $2\bigendian_i$next[0:0]$1886 \bigendian_i
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\bigendian_i$next[0:0]$1846 \core_bigendian_i
+ assign $2\bigendian_i$next[0:0]$1886 \core_bigendian_i
end
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\bigendian_i$next[0:0]$1845 $3\bigendian_i$next[0:0]$1847
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ assign $1\bigendian_i$next[0:0]$1885 $3\bigendian_i$next[0:0]$1887
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
switch \$45
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\bigendian_i$next[0:0]$1847 1'0
+ assign $3\bigendian_i$next[0:0]$1887 1'0
case
- assign $3\bigendian_i$next[0:0]$1847 \bigendian_i
+ assign $3\bigendian_i$next[0:0]$1887 \bigendian_i
end
case
- assign $1\bigendian_i$next[0:0]$1845 \bigendian_i
+ assign $1\bigendian_i$next[0:0]$1885 \bigendian_i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\bigendian_i$next[0:0]$1848 1'0
+ assign $4\bigendian_i$next[0:0]$1888 1'0
case
- assign $4\bigendian_i$next[0:0]$1848 $1\bigendian_i$next[0:0]$1845
+ assign $4\bigendian_i$next[0:0]$1888 $1\bigendian_i$next[0:0]$1885
end
sync always
- update \bigendian_i$next $0\bigendian_i$next[0:0]$1844
+ update \bigendian_i$next $0\bigendian_i$next[0:0]$1884
end
- attribute \src "libresoc.v:49144.3-49159.6"
- process $proc$libresoc.v:49144$1849
+ attribute \src "libresoc.v:49821.3-49836.6"
+ process $proc$libresoc.v:49821$1889
assign { } { }
assign { } { }
assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:49145.5-49145.29"
+ attribute \src "libresoc.v:49822.5-49822.29"
switch \initial
- attribute \src "libresoc.v:49145.9-49145.17"
+ attribute \src "libresoc.v:49822.9-49822.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
switch \$51
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \imem_a_pc_i $0\imem_a_pc_i[47:0]
end
- attribute \src "libresoc.v:49160.3-49184.6"
- process $proc$libresoc.v:49160$1850
+ attribute \src "libresoc.v:49837.3-49861.6"
+ process $proc$libresoc.v:49837$1890
assign { } { }
assign { } { }
assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:49161.5-49161.29"
+ attribute \src "libresoc.v:49838.5-49838.29"
switch \initial
- attribute \src "libresoc.v:49161.9-49161.17"
+ attribute \src "libresoc.v:49838.9-49838.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
switch \$57
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 2'01
assign { } { }
assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \imem_a_valid_i $0\imem_a_valid_i[0:0]
end
- attribute \src "libresoc.v:49185.3-49209.6"
- process $proc$libresoc.v:49185$1851
+ attribute \src "libresoc.v:49862.3-49886.6"
+ process $proc$libresoc.v:49862$1891
assign { } { }
assign { } { }
assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:49186.5-49186.29"
+ attribute \src "libresoc.v:49863.5-49863.29"
switch \initial
- attribute \src "libresoc.v:49186.9-49186.17"
+ attribute \src "libresoc.v:49863.9-49863.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
switch \$63
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 2'01
assign { } { }
assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \imem_f_valid_i $0\imem_f_valid_i[0:0]
end
- attribute \src "libresoc.v:49210.3-49230.6"
- process $proc$libresoc.v:49210$1852
+ attribute \src "libresoc.v:49887.3-49907.6"
+ process $proc$libresoc.v:49887$1892
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_pc$next[63:0]$1853 $3\dec2_cur_pc$next[63:0]$1856
- attribute \src "libresoc.v:49211.5-49211.29"
+ assign $0\dec2_cur_pc$next[63:0]$1893 $3\dec2_cur_pc$next[63:0]$1896
+ attribute \src "libresoc.v:49888.5-49888.29"
switch \initial
- attribute \src "libresoc.v:49211.9-49211.17"
+ attribute \src "libresoc.v:49888.9-49888.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\dec2_cur_pc$next[63:0]$1854 $2\dec2_cur_pc$next[63:0]$1855
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ assign $1\dec2_cur_pc$next[63:0]$1894 $2\dec2_cur_pc$next[63:0]$1895
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
switch \$69
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_pc$next[63:0]$1855 \pc
+ assign $2\dec2_cur_pc$next[63:0]$1895 \pc
case
- assign $2\dec2_cur_pc$next[63:0]$1855 \dec2_cur_pc
+ assign $2\dec2_cur_pc$next[63:0]$1895 \dec2_cur_pc
end
case
- assign $1\dec2_cur_pc$next[63:0]$1854 \dec2_cur_pc
+ assign $1\dec2_cur_pc$next[63:0]$1894 \dec2_cur_pc
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dec2_cur_pc$next[63:0]$1856 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dec2_cur_pc$next[63:0]$1896 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dec2_cur_pc$next[63:0]$1856 $1\dec2_cur_pc$next[63:0]$1854
+ assign $3\dec2_cur_pc$next[63:0]$1896 $1\dec2_cur_pc$next[63:0]$1894
end
sync always
- update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$1853
+ update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$1893
end
- attribute \src "libresoc.v:49231.3-49260.6"
- process $proc$libresoc.v:49231$1857
+ attribute \src "libresoc.v:49908.3-49937.6"
+ process $proc$libresoc.v:49908$1897
assign { } { }
assign { } { }
assign { } { }
- assign $0\msr_read$next[0:0]$1858 $4\msr_read$next[0:0]$1862
- attribute \src "libresoc.v:49232.5-49232.29"
+ assign $0\msr_read$next[0:0]$1898 $4\msr_read$next[0:0]$1902
+ attribute \src "libresoc.v:49909.5-49909.29"
switch \initial
- attribute \src "libresoc.v:49232.9-49232.17"
+ attribute \src "libresoc.v:49909.9-49909.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\msr_read$next[0:0]$1859 $2\msr_read$next[0:0]$1860
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ assign $1\msr_read$next[0:0]$1899 $2\msr_read$next[0:0]$1900
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
switch \$75
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\msr_read$next[0:0]$1860 1'0
+ assign $2\msr_read$next[0:0]$1900 1'0
case
- assign $2\msr_read$next[0:0]$1860 \msr_read
+ assign $2\msr_read$next[0:0]$1900 \msr_read
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\msr_read$next[0:0]$1859 $3\msr_read$next[0:0]$1861
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255"
+ assign $1\msr_read$next[0:0]$1899 $3\msr_read$next[0:0]$1901
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257"
switch \$77
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\msr_read$next[0:0]$1861 1'1
+ assign $3\msr_read$next[0:0]$1901 1'1
case
- assign $3\msr_read$next[0:0]$1861 \msr_read
+ assign $3\msr_read$next[0:0]$1901 \msr_read
end
case
- assign $1\msr_read$next[0:0]$1859 \msr_read
+ assign $1\msr_read$next[0:0]$1899 \msr_read
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\msr_read$next[0:0]$1862 1'1
+ assign $4\msr_read$next[0:0]$1902 1'1
case
- assign $4\msr_read$next[0:0]$1862 $1\msr_read$next[0:0]$1859
+ assign $4\msr_read$next[0:0]$1902 $1\msr_read$next[0:0]$1899
end
sync always
- update \msr_read$next $0\msr_read$next[0:0]$1858
+ update \msr_read$next $0\msr_read$next[0:0]$1898
end
- attribute \src "libresoc.v:49261.3-49306.6"
- process $proc$libresoc.v:49261$1863
+ attribute \src "libresoc.v:49938.3-49983.6"
+ process $proc$libresoc.v:49938$1903
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$next[1:0]$1864 $5\fsm_state$next[1:0]$1869
- attribute \src "libresoc.v:49262.5-49262.29"
+ assign $0\fsm_state$next[1:0]$1904 $5\fsm_state$next[1:0]$1909
+ attribute \src "libresoc.v:49939.5-49939.29"
switch \initial
- attribute \src "libresoc.v:49262.9-49262.17"
+ attribute \src "libresoc.v:49939.9-49939.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\fsm_state$next[1:0]$1865 $2\fsm_state$next[1:0]$1866
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ assign $1\fsm_state$next[1:0]$1905 $2\fsm_state$next[1:0]$1906
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
switch \$83
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fsm_state$next[1:0]$1866 2'01
+ assign $2\fsm_state$next[1:0]$1906 2'01
case
- assign $2\fsm_state$next[1:0]$1866 \fsm_state
+ assign $2\fsm_state$next[1:0]$1906 \fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\fsm_state$next[1:0]$1865 $3\fsm_state$next[1:0]$1867
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258"
+ assign $1\fsm_state$next[1:0]$1905 $3\fsm_state$next[1:0]$1907
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $3\fsm_state$next[1:0]$1867 \fsm_state
+ assign $3\fsm_state$next[1:0]$1907 \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $3\fsm_state$next[1:0]$1867 2'10
+ assign $3\fsm_state$next[1:0]$1907 2'10
end
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\fsm_state$next[1:0]$1865 2'11
+ assign $1\fsm_state$next[1:0]$1905 2'11
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\fsm_state$next[1:0]$1865 $4\fsm_state$next[1:0]$1868
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291"
+ assign $1\fsm_state$next[1:0]$1905 $4\fsm_state$next[1:0]$1908
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293"
switch \$85
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\fsm_state$next[1:0]$1868 2'00
+ assign $4\fsm_state$next[1:0]$1908 2'00
case
- assign $4\fsm_state$next[1:0]$1868 \fsm_state
+ assign $4\fsm_state$next[1:0]$1908 \fsm_state
end
case
- assign $1\fsm_state$next[1:0]$1865 \fsm_state
+ assign $1\fsm_state$next[1:0]$1905 \fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fsm_state$next[1:0]$1869 2'00
+ assign $5\fsm_state$next[1:0]$1909 2'00
case
- assign $5\fsm_state$next[1:0]$1869 $1\fsm_state$next[1:0]$1865
+ assign $5\fsm_state$next[1:0]$1909 $1\fsm_state$next[1:0]$1905
end
sync always
- update \fsm_state$next $0\fsm_state$next[1:0]$1864
+ update \fsm_state$next $0\fsm_state$next[1:0]$1904
end
- attribute \src "libresoc.v:49307.3-49316.6"
- process $proc$libresoc.v:49307$1870
+ attribute \src "libresoc.v:49984.3-49993.6"
+ process $proc$libresoc.v:49984$1910
assign { } { }
assign { } { }
- assign $0\delay$next[1:0]$1871 $1\delay$next[1:0]$1872
- attribute \src "libresoc.v:49308.5-49308.29"
+ assign $0\delay$next[1:0]$1911 $1\delay$next[1:0]$1912
+ attribute \src "libresoc.v:49985.5-49985.29"
switch \initial
- attribute \src "libresoc.v:49308.9-49308.17"
+ attribute \src "libresoc.v:49985.9-49985.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:156"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:158"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\delay$next[1:0]$1872 \$5 [1:0]
+ assign $1\delay$next[1:0]$1912 \$5 [1:0]
case
- assign $1\delay$next[1:0]$1872 \delay
+ assign $1\delay$next[1:0]$1912 \delay
end
sync always
- update \delay$next $0\delay$next[1:0]$1871
+ update \delay$next $0\delay$next[1:0]$1911
end
- attribute \src "libresoc.v:49317.3-49335.6"
- process $proc$libresoc.v:49317$1873
+ attribute \src "libresoc.v:49994.3-50012.6"
+ process $proc$libresoc.v:49994$1913
assign { } { }
assign { } { }
assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0]
- attribute \src "libresoc.v:49318.5-49318.29"
+ attribute \src "libresoc.v:49995.5-49995.29"
switch \initial
- attribute \src "libresoc.v:49318.9-49318.17"
+ attribute \src "libresoc.v:49995.9-49995.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
switch \$91
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_stopped_i $0\core_stopped_i[0:0]
end
- attribute \src "libresoc.v:49336.3-49354.6"
- process $proc$libresoc.v:49336$1874
+ attribute \src "libresoc.v:50013.3-50031.6"
+ process $proc$libresoc.v:50013$1914
assign { } { }
assign { } { }
assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:49337.5-49337.29"
+ attribute \src "libresoc.v:50014.5-50014.29"
switch \initial
- attribute \src "libresoc.v:49337.9-49337.17"
+ attribute \src "libresoc.v:50014.9-50014.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235"
switch \$97
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0]
end
- attribute \src "libresoc.v:49355.3-49375.6"
- process $proc$libresoc.v:49355$1875
+ attribute \src "libresoc.v:50032.3-50052.6"
+ process $proc$libresoc.v:50032$1915
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_msr$next[63:0]$1876 $3\dec2_cur_msr$next[63:0]$1879
- attribute \src "libresoc.v:49356.5-49356.29"
+ assign $0\dec2_cur_msr$next[63:0]$1916 $3\dec2_cur_msr$next[63:0]$1919
+ attribute \src "libresoc.v:50033.5-50033.29"
switch \initial
- attribute \src "libresoc.v:49356.9-49356.17"
+ attribute \src "libresoc.v:50033.9-50033.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\dec2_cur_msr$next[63:0]$1877 $2\dec2_cur_msr$next[63:0]$1878
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255"
+ assign $1\dec2_cur_msr$next[63:0]$1917 $2\dec2_cur_msr$next[63:0]$1918
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257"
switch \$99
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_msr$next[63:0]$1878 \msr__data_o
+ assign $2\dec2_cur_msr$next[63:0]$1918 \msr__data_o
case
- assign $2\dec2_cur_msr$next[63:0]$1878 \dec2_cur_msr
+ assign $2\dec2_cur_msr$next[63:0]$1918 \dec2_cur_msr
end
case
- assign $1\dec2_cur_msr$next[63:0]$1877 \dec2_cur_msr
+ assign $1\dec2_cur_msr$next[63:0]$1917 \dec2_cur_msr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dec2_cur_msr$next[63:0]$1879 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dec2_cur_msr$next[63:0]$1919 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dec2_cur_msr$next[63:0]$1879 $1\dec2_cur_msr$next[63:0]$1877
+ assign $3\dec2_cur_msr$next[63:0]$1919 $1\dec2_cur_msr$next[63:0]$1917
end
sync always
- update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$1876
+ update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$1916
end
- attribute \src "libresoc.v:49376.3-49394.6"
- process $proc$libresoc.v:49376$1880
+ attribute \src "libresoc.v:50053.3-50071.6"
+ process $proc$libresoc.v:50053$1920
assign { } { }
assign { } { }
assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:49377.5-49377.29"
+ attribute \src "libresoc.v:50054.5-50054.29"
switch \initial
- attribute \src "libresoc.v:49377.9-49377.17"
+ attribute \src "libresoc.v:50054.9-50054.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0]
end
- attribute \src "libresoc.v:49395.3-49426.6"
- process $proc$libresoc.v:49395$1881
+ attribute \src "libresoc.v:50072.3-50103.6"
+ process $proc$libresoc.v:50072$1921
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_dec$next[63:0]$1882 $3\core_dec$next[63:0]$1894
- assign $0\core_eint$next[0:0]$1883 $3\core_eint$next[0:0]$1895
- assign $0\core_msr$next[63:0]$1884 $3\core_msr$next[63:0]$1896
- assign $0\core_pc$next[63:0]$1885 $3\core_pc$next[63:0]$1897
- attribute \src "libresoc.v:49396.5-49396.29"
+ assign $0\core_dec$next[63:0]$1922 $3\core_dec$next[63:0]$1934
+ assign $0\core_eint$next[0:0]$1923 $3\core_eint$next[0:0]$1935
+ assign $0\core_msr$next[63:0]$1924 $3\core_msr$next[63:0]$1936
+ assign $0\core_pc$next[63:0]$1925 $3\core_pc$next[63:0]$1937
+ attribute \src "libresoc.v:50073.5-50073.29"
switch \initial
- attribute \src "libresoc.v:49396.9-49396.17"
+ attribute \src "libresoc.v:50073.9-50073.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
assign { } { }
assign { } { }
- assign $1\core_dec$next[63:0]$1886 $2\core_dec$next[63:0]$1890
- assign $1\core_eint$next[0:0]$1887 $2\core_eint$next[0:0]$1891
- assign $1\core_msr$next[63:0]$1888 $2\core_msr$next[63:0]$1892
- assign $1\core_pc$next[63:0]$1889 $2\core_pc$next[63:0]$1893
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258"
+ assign $1\core_dec$next[63:0]$1926 $2\core_dec$next[63:0]$1930
+ assign $1\core_eint$next[0:0]$1927 $2\core_eint$next[0:0]$1931
+ assign $1\core_msr$next[63:0]$1928 $2\core_msr$next[63:0]$1932
+ assign $1\core_pc$next[63:0]$1929 $2\core_pc$next[63:0]$1933
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\core_dec$next[63:0]$1890 \core_dec
- assign $2\core_eint$next[0:0]$1891 \core_eint
- assign $2\core_msr$next[63:0]$1892 \core_msr
- assign $2\core_pc$next[63:0]$1893 \core_pc
+ assign $2\core_dec$next[63:0]$1930 \core_dec
+ assign $2\core_eint$next[0:0]$1931 \core_eint
+ assign $2\core_msr$next[63:0]$1932 \core_msr
+ assign $2\core_pc$next[63:0]$1933 \core_pc
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $2\core_dec$next[63:0]$1890 $2\core_eint$next[0:0]$1891 $2\core_msr$next[63:0]$1892 $2\core_pc$next[63:0]$1893 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
+ assign { $2\core_dec$next[63:0]$1930 $2\core_eint$next[0:0]$1931 $2\core_msr$next[63:0]$1932 $2\core_pc$next[63:0]$1933 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
end
case
- assign $1\core_dec$next[63:0]$1886 \core_dec
- assign $1\core_eint$next[0:0]$1887 \core_eint
- assign $1\core_msr$next[63:0]$1888 \core_msr
- assign $1\core_pc$next[63:0]$1889 \core_pc
+ assign $1\core_dec$next[63:0]$1926 \core_dec
+ assign $1\core_eint$next[0:0]$1927 \core_eint
+ assign $1\core_msr$next[63:0]$1928 \core_msr
+ assign $1\core_pc$next[63:0]$1929 \core_pc
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $3\core_pc$next[63:0]$1897 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\core_msr$next[63:0]$1896 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\core_eint$next[0:0]$1895 1'0
- assign $3\core_dec$next[63:0]$1894 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_pc$next[63:0]$1937 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_msr$next[63:0]$1936 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_eint$next[0:0]$1935 1'0
+ assign $3\core_dec$next[63:0]$1934 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\core_dec$next[63:0]$1894 $1\core_dec$next[63:0]$1886
- assign $3\core_eint$next[0:0]$1895 $1\core_eint$next[0:0]$1887
- assign $3\core_msr$next[63:0]$1896 $1\core_msr$next[63:0]$1888
- assign $3\core_pc$next[63:0]$1897 $1\core_pc$next[63:0]$1889
+ assign $3\core_dec$next[63:0]$1934 $1\core_dec$next[63:0]$1926
+ assign $3\core_eint$next[0:0]$1935 $1\core_eint$next[0:0]$1927
+ assign $3\core_msr$next[63:0]$1936 $1\core_msr$next[63:0]$1928
+ assign $3\core_pc$next[63:0]$1937 $1\core_pc$next[63:0]$1929
end
sync always
- update \core_dec$next $0\core_dec$next[63:0]$1882
- update \core_eint$next $0\core_eint$next[0:0]$1883
- update \core_msr$next $0\core_msr$next[63:0]$1884
- update \core_pc$next $0\core_pc$next[63:0]$1885
+ update \core_dec$next $0\core_dec$next[63:0]$1922
+ update \core_eint$next $0\core_eint$next[0:0]$1923
+ update \core_msr$next $0\core_msr$next[63:0]$1924
+ update \core_pc$next $0\core_pc$next[63:0]$1925
end
- attribute \src "libresoc.v:49427.3-49450.6"
- process $proc$libresoc.v:49427$1898
+ attribute \src "libresoc.v:50104.3-50127.6"
+ process $proc$libresoc.v:50104$1938
assign { } { }
assign { } { }
assign { } { }
- assign $0\ilatch$next[31:0]$1899 $3\ilatch$next[31:0]$1902
- attribute \src "libresoc.v:49428.5-49428.29"
+ assign $0\ilatch$next[31:0]$1939 $3\ilatch$next[31:0]$1942
+ attribute \src "libresoc.v:50105.5-50105.29"
switch \initial
- attribute \src "libresoc.v:49428.9-49428.17"
+ attribute \src "libresoc.v:50105.9-50105.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\ilatch$next[31:0]$1900 $2\ilatch$next[31:0]$1901
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258"
+ assign $1\ilatch$next[31:0]$1940 $2\ilatch$next[31:0]$1941
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\ilatch$next[31:0]$1901 \ilatch
+ assign $2\ilatch$next[31:0]$1941 \ilatch
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\ilatch$next[31:0]$1901 \$105
+ assign $2\ilatch$next[31:0]$1941 \$105
end
case
- assign $1\ilatch$next[31:0]$1900 \ilatch
+ assign $1\ilatch$next[31:0]$1940 \ilatch
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ilatch$next[31:0]$1902 0
+ assign $3\ilatch$next[31:0]$1942 0
case
- assign $3\ilatch$next[31:0]$1902 $1\ilatch$next[31:0]$1900
+ assign $3\ilatch$next[31:0]$1942 $1\ilatch$next[31:0]$1940
end
sync always
- update \ilatch$next $0\ilatch$next[31:0]$1899
+ update \ilatch$next $0\ilatch$next[31:0]$1939
end
- attribute \src "libresoc.v:49451.3-49470.6"
- process $proc$libresoc.v:49451$1903
+ attribute \src "libresoc.v:50128.3-50147.6"
+ process $proc$libresoc.v:50128$1943
assign { } { }
assign { } { }
assign $0\ivalid_i[0:0] $1\ivalid_i[0:0]
- attribute \src "libresoc.v:49452.5-49452.29"
+ attribute \src "libresoc.v:50129.5-50129.29"
switch \initial
- attribute \src "libresoc.v:49452.9-49452.17"
+ attribute \src "libresoc.v:50129.9-50129.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 2'11
assign { } { }
assign $1\ivalid_i[0:0] $2\ivalid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
switch \$109
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \ivalid_i $0\ivalid_i[0:0]
end
- connect \$99 $not$libresoc.v:48036$1403_Y
- connect \$102 $mul$libresoc.v:48037$1404_Y
- connect \$101 $shr$libresoc.v:48038$1405_Y [31:0]
- connect \$106 $mul$libresoc.v:48039$1406_Y
- connect \$105 $shr$libresoc.v:48040$1407_Y [31:0]
- connect \$10 $ne$libresoc.v:48041$1408_Y
- connect \$109 $ne$libresoc.v:48042$1409_Y
- connect \$111 $pos$libresoc.v:48043$1411_Y
- connect \$113 $pos$libresoc.v:48044$1413_Y
- connect \$117 $sub$libresoc.v:48045$1414_Y
- connect \$121 $add$libresoc.v:48046$1415_Y
- connect \$12 $not$libresoc.v:48047$1416_Y
- connect \$14 $and$libresoc.v:48048$1417_Y
- connect \$17 $add$libresoc.v:48049$1418_Y
- connect \$19 $not$libresoc.v:48050$1419_Y
- connect \$21 $not$libresoc.v:48051$1420_Y
- connect \$23 $not$libresoc.v:48052$1421_Y
- connect \$25 $not$libresoc.v:48053$1422_Y
- connect \$27 $not$libresoc.v:48054$1423_Y
- connect \$29 $not$libresoc.v:48055$1424_Y
- connect \$31 $not$libresoc.v:48056$1425_Y
- connect \$33 $and$libresoc.v:48057$1426_Y
- connect \$36 $and$libresoc.v:48058$1427_Y
- connect \$35 $reduce_or$libresoc.v:48059$1428_Y
- connect \$3 $ne$libresoc.v:48060$1429_Y
- connect \$41 $not$libresoc.v:48061$1430_Y
- connect \$43 $not$libresoc.v:48062$1431_Y
- connect \$45 $not$libresoc.v:48063$1432_Y
- connect \$47 $not$libresoc.v:48064$1433_Y
- connect \$49 $not$libresoc.v:48065$1434_Y
- connect \$51 $and$libresoc.v:48066$1435_Y
- connect \$53 $not$libresoc.v:48067$1436_Y
- connect \$55 $not$libresoc.v:48068$1437_Y
- connect \$57 $and$libresoc.v:48069$1438_Y
- connect \$59 $not$libresoc.v:48070$1439_Y
- connect \$61 $not$libresoc.v:48071$1440_Y
- connect \$63 $and$libresoc.v:48072$1441_Y
- connect \$65 $not$libresoc.v:48073$1442_Y
- connect \$67 $not$libresoc.v:48074$1443_Y
- connect \$6 $sub$libresoc.v:48075$1444_Y
- connect \$69 $and$libresoc.v:48076$1445_Y
- connect \$71 $not$libresoc.v:48077$1446_Y
- connect \$73 $not$libresoc.v:48078$1447_Y
- connect \$75 $and$libresoc.v:48079$1448_Y
- connect \$77 $not$libresoc.v:48080$1449_Y
- connect \$79 $not$libresoc.v:48081$1450_Y
- connect \$81 $not$libresoc.v:48082$1451_Y
- connect \$83 $and$libresoc.v:48083$1452_Y
- connect \$85 $not$libresoc.v:48084$1453_Y
- connect \$87 $not$libresoc.v:48085$1454_Y
- connect \$8 $or$libresoc.v:48086$1455_Y
- connect \$89 $not$libresoc.v:48087$1456_Y
- connect \$91 $and$libresoc.v:48088$1457_Y
- connect \$93 $not$libresoc.v:48089$1458_Y
- connect \$95 $not$libresoc.v:48090$1459_Y
- connect \$97 $and$libresoc.v:48091$1460_Y
+ connect \$99 $not$libresoc.v:48713$1443_Y
+ connect \$102 $mul$libresoc.v:48714$1444_Y
+ connect \$101 $shr$libresoc.v:48715$1445_Y [31:0]
+ connect \$106 $mul$libresoc.v:48716$1446_Y
+ connect \$105 $shr$libresoc.v:48717$1447_Y [31:0]
+ connect \$10 $ne$libresoc.v:48718$1448_Y
+ connect \$109 $ne$libresoc.v:48719$1449_Y
+ connect \$111 $pos$libresoc.v:48720$1451_Y
+ connect \$113 $pos$libresoc.v:48721$1453_Y
+ connect \$117 $sub$libresoc.v:48722$1454_Y
+ connect \$121 $add$libresoc.v:48723$1455_Y
+ connect \$12 $not$libresoc.v:48724$1456_Y
+ connect \$14 $and$libresoc.v:48725$1457_Y
+ connect \$17 $add$libresoc.v:48726$1458_Y
+ connect \$19 $not$libresoc.v:48727$1459_Y
+ connect \$21 $not$libresoc.v:48728$1460_Y
+ connect \$23 $not$libresoc.v:48729$1461_Y
+ connect \$25 $not$libresoc.v:48730$1462_Y
+ connect \$27 $not$libresoc.v:48731$1463_Y
+ connect \$29 $not$libresoc.v:48732$1464_Y
+ connect \$31 $not$libresoc.v:48733$1465_Y
+ connect \$33 $and$libresoc.v:48734$1466_Y
+ connect \$36 $and$libresoc.v:48735$1467_Y
+ connect \$35 $reduce_or$libresoc.v:48736$1468_Y
+ connect \$3 $ne$libresoc.v:48737$1469_Y
+ connect \$41 $not$libresoc.v:48738$1470_Y
+ connect \$43 $not$libresoc.v:48739$1471_Y
+ connect \$45 $not$libresoc.v:48740$1472_Y
+ connect \$47 $not$libresoc.v:48741$1473_Y
+ connect \$49 $not$libresoc.v:48742$1474_Y
+ connect \$51 $and$libresoc.v:48743$1475_Y
+ connect \$53 $not$libresoc.v:48744$1476_Y
+ connect \$55 $not$libresoc.v:48745$1477_Y
+ connect \$57 $and$libresoc.v:48746$1478_Y
+ connect \$59 $not$libresoc.v:48747$1479_Y
+ connect \$61 $not$libresoc.v:48748$1480_Y
+ connect \$63 $and$libresoc.v:48749$1481_Y
+ connect \$65 $not$libresoc.v:48750$1482_Y
+ connect \$67 $not$libresoc.v:48751$1483_Y
+ connect \$6 $sub$libresoc.v:48752$1484_Y
+ connect \$69 $and$libresoc.v:48753$1485_Y
+ connect \$71 $not$libresoc.v:48754$1486_Y
+ connect \$73 $not$libresoc.v:48755$1487_Y
+ connect \$75 $and$libresoc.v:48756$1488_Y
+ connect \$77 $not$libresoc.v:48757$1489_Y
+ connect \$79 $not$libresoc.v:48758$1490_Y
+ connect \$81 $not$libresoc.v:48759$1491_Y
+ connect \$83 $and$libresoc.v:48760$1492_Y
+ connect \$85 $not$libresoc.v:48761$1493_Y
+ connect \$87 $not$libresoc.v:48762$1494_Y
+ connect \$8 $or$libresoc.v:48763$1495_Y
+ connect \$89 $not$libresoc.v:48764$1496_Y
+ connect \$91 $and$libresoc.v:48765$1497_Y
+ connect \$93 $not$libresoc.v:48766$1498_Y
+ connect \$95 $not$libresoc.v:48767$1499_Y
+ connect \$97 $and$libresoc.v:48768$1500_Y
connect \$5 \$6
connect \$16 \$17
connect \$116 \$117
connect \$120 \$121
+ connect \intclk_clk 1'0
+ connect \intclk_rst 1'0
connect \corebusy_o 1'0
connect \cu_st__rel_o 1'0
connect \cu_ad__rel_o 1'0
connect \dec2_bigendian \core_bigendian_i
connect \busy_o 1'0
connect \core_reset_i \$10
- connect \coresync_clk \clk
- connect \por_clk \clk
+ connect \coresync_clk 1'0
+ connect \por_clk 1'0
connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src }
end
-attribute \src "libresoc.v:49505.1-49819.10"
+attribute \src "libresoc.v:50184.1-50498.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.xics_icp"
+attribute \nmigen.hierarchy "test_issuer.ti.xics_icp"
attribute \generator "nMigen"
module \xics_icp
- attribute \src "libresoc.v:49683.3-49711.6"
+ attribute \src "libresoc.v:50362.3-50390.6"
wire width 32 $0\be_out[31:0]
- attribute \src "libresoc.v:49734.3-49742.6"
- wire $0\core_irq_o$next[0:0]$2021
- attribute \src "libresoc.v:49625.3-49626.37"
+ attribute \src "libresoc.v:50413.3-50421.6"
+ wire $0\core_irq_o$next[0:0]$2061
+ attribute \src "libresoc.v:50304.3-50305.37"
wire $0\core_irq_o[0:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire width 8 $0\cppr$10[7:0]$2025
- attribute \src "libresoc.v:49639.3-49654.6"
- wire width 8 $0\cppr$next[7:0]$2004
- attribute \src "libresoc.v:49629.3-49630.25"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire width 8 $0\cppr$10[7:0]$2065
+ attribute \src "libresoc.v:50318.3-50333.6"
+ wire width 8 $0\cppr$next[7:0]$2044
+ attribute \src "libresoc.v:50308.3-50309.25"
wire width 8 $0\cppr[7:0]
- attribute \src "libresoc.v:49743.3-49752.6"
+ attribute \src "libresoc.v:50422.3-50431.6"
wire width 32 $0\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:49506.7-49506.20"
+ attribute \src "libresoc.v:50185.7-50185.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire $0\irq$12[0:0]$2026
- attribute \src "libresoc.v:49639.3-49654.6"
- wire $0\irq$next[0:0]$2005
- attribute \src "libresoc.v:49633.3-49634.23"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire $0\irq$12[0:0]$2066
+ attribute \src "libresoc.v:50318.3-50333.6"
+ wire $0\irq$next[0:0]$2045
+ attribute \src "libresoc.v:50312.3-50313.23"
wire $0\irq[0:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire width 8 $0\mfrr$11[7:0]$2027
- attribute \src "libresoc.v:49639.3-49654.6"
- wire width 8 $0\mfrr$next[7:0]$2006
- attribute \src "libresoc.v:49631.3-49632.25"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire width 8 $0\mfrr$11[7:0]$2067
+ attribute \src "libresoc.v:50318.3-50333.6"
+ wire width 8 $0\mfrr$next[7:0]$2046
+ attribute \src "libresoc.v:50310.3-50311.25"
wire width 8 $0\mfrr[7:0]
- attribute \src "libresoc.v:49722.3-49733.6"
+ attribute \src "libresoc.v:50401.3-50412.6"
wire width 8 $0\min_pri[7:0]
- attribute \src "libresoc.v:49712.3-49721.6"
+ attribute \src "libresoc.v:50391.3-50400.6"
wire width 8 $0\pending_priority[7:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire $0\wb_ack$14[0:0]$2028
- attribute \src "libresoc.v:49639.3-49654.6"
- wire $0\wb_ack$next[0:0]$2007
- attribute \src "libresoc.v:49637.3-49638.29"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire $0\wb_ack$14[0:0]$2068
+ attribute \src "libresoc.v:50318.3-50333.6"
+ wire $0\wb_ack$next[0:0]$2047
+ attribute \src "libresoc.v:50316.3-50317.29"
wire $0\wb_ack[0:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire width 32 $0\wb_rd_data$13[31:0]$2029
- attribute \src "libresoc.v:49639.3-49654.6"
- wire width 32 $0\wb_rd_data$next[31:0]$2008
- attribute \src "libresoc.v:49635.3-49636.37"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire width 32 $0\wb_rd_data$13[31:0]$2069
+ attribute \src "libresoc.v:50318.3-50333.6"
+ wire width 32 $0\wb_rd_data$next[31:0]$2048
+ attribute \src "libresoc.v:50314.3-50315.37"
wire width 32 $0\wb_rd_data[31:0]
- attribute \src "libresoc.v:49655.3-49682.6"
+ attribute \src "libresoc.v:50334.3-50361.6"
wire $0\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire width 24 $0\xisr$9[23:0]$2030
- attribute \src "libresoc.v:49639.3-49654.6"
- wire width 24 $0\xisr$next[23:0]$2009
- attribute \src "libresoc.v:49627.3-49628.25"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire width 24 $0\xisr$9[23:0]$2070
+ attribute \src "libresoc.v:50318.3-50333.6"
+ wire width 24 $0\xisr$next[23:0]$2049
+ attribute \src "libresoc.v:50306.3-50307.25"
wire width 24 $0\xisr[23:0]
- attribute \src "libresoc.v:49683.3-49711.6"
+ attribute \src "libresoc.v:50362.3-50390.6"
wire width 32 $1\be_out[31:0]
- attribute \src "libresoc.v:49734.3-49742.6"
- wire $1\core_irq_o$next[0:0]$2022
- attribute \src "libresoc.v:49535.7-49535.24"
+ attribute \src "libresoc.v:50413.3-50421.6"
+ wire $1\core_irq_o$next[0:0]$2062
+ attribute \src "libresoc.v:50212.7-50212.24"
wire $1\core_irq_o[0:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire width 8 $1\cppr$10[7:0]$2031
- attribute \src "libresoc.v:49639.3-49654.6"
- wire width 8 $1\cppr$next[7:0]$2010
- attribute \src "libresoc.v:49539.13-49539.25"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire width 8 $1\cppr$10[7:0]$2071
+ attribute \src "libresoc.v:50318.3-50333.6"
+ wire width 8 $1\cppr$next[7:0]$2050
+ attribute \src "libresoc.v:50216.13-50216.25"
wire width 8 $1\cppr[7:0]
- attribute \src "libresoc.v:49743.3-49752.6"
+ attribute \src "libresoc.v:50422.3-50431.6"
wire width 32 $1\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire $1\irq$12[0:0]$2041
- attribute \src "libresoc.v:49639.3-49654.6"
- wire $1\irq$next[0:0]$2011
- attribute \src "libresoc.v:49568.7-49568.17"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire $1\irq$12[0:0]$2081
+ attribute \src "libresoc.v:50318.3-50333.6"
+ wire $1\irq$next[0:0]$2051
+ attribute \src "libresoc.v:50249.7-50249.17"
wire $1\irq[0:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire width 8 $1\mfrr$11[7:0]$2032
- attribute \src "libresoc.v:49639.3-49654.6"
- wire width 8 $1\mfrr$next[7:0]$2012
- attribute \src "libresoc.v:49576.13-49576.25"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire width 8 $1\mfrr$11[7:0]$2072
+ attribute \src "libresoc.v:50318.3-50333.6"
+ wire width 8 $1\mfrr$next[7:0]$2052
+ attribute \src "libresoc.v:50257.13-50257.25"
wire width 8 $1\mfrr[7:0]
- attribute \src "libresoc.v:49722.3-49733.6"
+ attribute \src "libresoc.v:50401.3-50412.6"
wire width 8 $1\min_pri[7:0]
- attribute \src "libresoc.v:49712.3-49721.6"
+ attribute \src "libresoc.v:50391.3-50400.6"
wire width 8 $1\pending_priority[7:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire $1\wb_ack$14[0:0]$2033
- attribute \src "libresoc.v:49639.3-49654.6"
- wire $1\wb_ack$next[0:0]$2013
- attribute \src "libresoc.v:49590.7-49590.20"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire $1\wb_ack$14[0:0]$2073
+ attribute \src "libresoc.v:50318.3-50333.6"
+ wire $1\wb_ack$next[0:0]$2053
+ attribute \src "libresoc.v:50269.7-50269.20"
wire $1\wb_ack[0:0]
- attribute \src "libresoc.v:49639.3-49654.6"
- wire width 32 $1\wb_rd_data$next[31:0]$2014
- attribute \src "libresoc.v:49598.14-49598.32"
+ attribute \src "libresoc.v:50318.3-50333.6"
+ wire width 32 $1\wb_rd_data$next[31:0]$2054
+ attribute \src "libresoc.v:50277.14-50277.32"
wire width 32 $1\wb_rd_data[31:0]
- attribute \src "libresoc.v:49655.3-49682.6"
+ attribute \src "libresoc.v:50334.3-50361.6"
wire $1\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire width 24 $1\xisr$9[23:0]$2038
- attribute \src "libresoc.v:49639.3-49654.6"
- wire width 24 $1\xisr$next[23:0]$2015
- attribute \src "libresoc.v:49608.14-49608.31"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire width 24 $1\xisr$9[23:0]$2078
+ attribute \src "libresoc.v:50318.3-50333.6"
+ wire width 24 $1\xisr$next[23:0]$2055
+ attribute \src "libresoc.v:50287.14-50287.31"
wire width 24 $1\xisr[23:0]
- attribute \src "libresoc.v:49683.3-49711.6"
+ attribute \src "libresoc.v:50362.3-50390.6"
wire width 32 $2\be_out[31:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire width 8 $2\cppr$10[7:0]$2034
- attribute \src "libresoc.v:49753.3-49815.6"
- wire width 8 $2\mfrr$11[7:0]$2035
- attribute \src "libresoc.v:49655.3-49682.6"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire width 8 $2\cppr$10[7:0]$2074
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire width 8 $2\mfrr$11[7:0]$2075
+ attribute \src "libresoc.v:50334.3-50361.6"
wire $2\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire width 24 $2\xisr$9[23:0]$2039
- attribute \src "libresoc.v:49683.3-49711.6"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire width 24 $2\xisr$9[23:0]$2079
+ attribute \src "libresoc.v:50362.3-50390.6"
wire width 32 $3\be_out[31:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire width 8 $3\cppr$10[7:0]$2036
- attribute \src "libresoc.v:49753.3-49815.6"
- wire width 8 $3\mfrr$11[7:0]$2037
- attribute \src "libresoc.v:49655.3-49682.6"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire width 8 $3\cppr$10[7:0]$2076
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire width 8 $3\mfrr$11[7:0]$2077
+ attribute \src "libresoc.v:50334.3-50361.6"
wire $3\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:49753.3-49815.6"
- wire width 8 $4\cppr$10[7:0]$2040
- attribute \src "libresoc.v:49655.3-49682.6"
+ attribute \src "libresoc.v:50432.3-50494.6"
+ wire width 8 $4\cppr$10[7:0]$2080
+ attribute \src "libresoc.v:50334.3-50361.6"
wire $4\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:49615.18-49615.116"
- wire $and$libresoc.v:49615$1986_Y
- attribute \src "libresoc.v:49619.18-49619.116"
- wire $and$libresoc.v:49619$1990_Y
- attribute \src "libresoc.v:49621.18-49621.116"
- wire $and$libresoc.v:49621$1992_Y
- attribute \src "libresoc.v:49624.17-49624.109"
- wire $and$libresoc.v:49624$1995_Y
- attribute \src "libresoc.v:49620.18-49620.110"
- wire $eq$libresoc.v:49620$1991_Y
- attribute \src "libresoc.v:49617.18-49617.114"
- wire $lt$libresoc.v:49617$1988_Y
- attribute \src "libresoc.v:49618.18-49618.109"
- wire $lt$libresoc.v:49618$1989_Y
- attribute \src "libresoc.v:49623.18-49623.114"
- wire $lt$libresoc.v:49623$1994_Y
- attribute \src "libresoc.v:49616.18-49616.109"
- wire $ne$libresoc.v:49616$1987_Y
- attribute \src "libresoc.v:49622.18-49622.109"
- wire $ne$libresoc.v:49622$1993_Y
+ attribute \src "libresoc.v:50294.18-50294.116"
+ wire $and$libresoc.v:50294$2026_Y
+ attribute \src "libresoc.v:50298.18-50298.116"
+ wire $and$libresoc.v:50298$2030_Y
+ attribute \src "libresoc.v:50300.18-50300.116"
+ wire $and$libresoc.v:50300$2032_Y
+ attribute \src "libresoc.v:50303.17-50303.109"
+ wire $and$libresoc.v:50303$2035_Y
+ attribute \src "libresoc.v:50299.18-50299.110"
+ wire $eq$libresoc.v:50299$2031_Y
+ attribute \src "libresoc.v:50296.18-50296.114"
+ wire $lt$libresoc.v:50296$2028_Y
+ attribute \src "libresoc.v:50297.18-50297.109"
+ wire $lt$libresoc.v:50297$2029_Y
+ attribute \src "libresoc.v:50302.18-50302.114"
+ wire $lt$libresoc.v:50302$2034_Y
+ attribute \src "libresoc.v:50295.18-50295.109"
+ wire $ne$libresoc.v:50295$2027_Y
+ attribute \src "libresoc.v:50301.18-50301.109"
+ wire $ne$libresoc.v:50301$2033_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
wire \$15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
wire width 32 \be_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104"
wire width 32 \be_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151"
- wire input 3 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
wire output 2 \core_irq_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
wire width 8 input 1 \ics_i_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
wire width 4 input 13 \ics_i_src
- attribute \src "libresoc.v:49506.7-49506.15"
+ attribute \src "libresoc.v:50185.7-50185.15"
wire \initial
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153"
+ wire input 3 \intclk_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153"
+ wire input 4 \intclk_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64"
wire \irq
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64"
wire width 8 \min_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106"
wire width 8 \pending_priority
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151"
- wire input 4 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66"
wire \wb_ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61"
wire width 24 \xisr$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:49615$1986
+ cell $and $and$libresoc.v:50294$2026
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:49615$1986_Y
+ connect \Y $and$libresoc.v:50294$2026_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:49619$1990
+ cell $and $and$libresoc.v:50298$2030
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:49619$1990_Y
+ connect \Y $and$libresoc.v:50298$2030_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:49621$1992
+ cell $and $and$libresoc.v:50300$2032
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:49621$1992_Y
+ connect \Y $and$libresoc.v:50300$2032_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96"
- cell $and $and$libresoc.v:49624$1995
+ cell $and $and$libresoc.v:50303$2035
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_ack
connect \B \icp_wb__cyc
- connect \Y $and$libresoc.v:49624$1995_Y
+ connect \Y $and$libresoc.v:50303$2035_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162"
- cell $eq $eq$libresoc.v:49620$1991
+ cell $eq $eq$libresoc.v:50299$2031
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__sel
connect \B 4'1111
- connect \Y $eq$libresoc.v:49620$1991_Y
+ connect \Y $eq$libresoc.v:50299$2031_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
- cell $lt $lt$libresoc.v:49617$1988
+ cell $lt $lt$libresoc.v:50296$2028
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mfrr
connect \B \pending_priority
- connect \Y $lt$libresoc.v:49617$1988_Y
+ connect \Y $lt$libresoc.v:50296$2028_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
- cell $lt $lt$libresoc.v:49618$1989
+ cell $lt $lt$libresoc.v:50297$2029
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \min_pri
connect \B \cppr$10
- connect \Y $lt$libresoc.v:49618$1989_Y
+ connect \Y $lt$libresoc.v:50297$2029_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
- cell $lt $lt$libresoc.v:49623$1994
+ cell $lt $lt$libresoc.v:50302$2034
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mfrr
connect \B \pending_priority
- connect \Y $lt$libresoc.v:49623$1994_Y
+ connect \Y $lt$libresoc.v:50302$2034_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
- cell $ne $ne$libresoc.v:49616$1987
+ cell $ne $ne$libresoc.v:50295$2027
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_i_pri
connect \B 8'11111111
- connect \Y $ne$libresoc.v:49616$1987_Y
+ connect \Y $ne$libresoc.v:50295$2027_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
- cell $ne $ne$libresoc.v:49622$1993
+ cell $ne $ne$libresoc.v:50301$2033
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_i_pri
connect \B 8'11111111
- connect \Y $ne$libresoc.v:49622$1993_Y
+ connect \Y $ne$libresoc.v:50301$2033_Y
end
- attribute \src "libresoc.v:49506.7-49506.20"
- process $proc$libresoc.v:49506$2042
+ attribute \src "libresoc.v:50185.7-50185.20"
+ process $proc$libresoc.v:50185$2082
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:49535.7-49535.24"
- process $proc$libresoc.v:49535$2043
+ attribute \src "libresoc.v:50212.7-50212.24"
+ process $proc$libresoc.v:50212$2083
assign { } { }
assign $1\core_irq_o[0:0] 1'0
sync always
sync init
update \core_irq_o $1\core_irq_o[0:0]
end
- attribute \src "libresoc.v:49539.13-49539.25"
- process $proc$libresoc.v:49539$2044
+ attribute \src "libresoc.v:50216.13-50216.25"
+ process $proc$libresoc.v:50216$2084
assign { } { }
assign $1\cppr[7:0] 8'00000000
sync always
sync init
update \cppr $1\cppr[7:0]
end
- attribute \src "libresoc.v:49568.7-49568.17"
- process $proc$libresoc.v:49568$2045
+ attribute \src "libresoc.v:50249.7-50249.17"
+ process $proc$libresoc.v:50249$2085
assign { } { }
assign $1\irq[0:0] 1'0
sync always
sync init
update \irq $1\irq[0:0]
end
- attribute \src "libresoc.v:49576.13-49576.25"
- process $proc$libresoc.v:49576$2046
+ attribute \src "libresoc.v:50257.13-50257.25"
+ process $proc$libresoc.v:50257$2086
assign { } { }
assign $1\mfrr[7:0] 8'11111111
sync always
sync init
update \mfrr $1\mfrr[7:0]
end
- attribute \src "libresoc.v:49590.7-49590.20"
- process $proc$libresoc.v:49590$2047
+ attribute \src "libresoc.v:50269.7-50269.20"
+ process $proc$libresoc.v:50269$2087
assign { } { }
assign $1\wb_ack[0:0] 1'0
sync always
sync init
update \wb_ack $1\wb_ack[0:0]
end
- attribute \src "libresoc.v:49598.14-49598.32"
- process $proc$libresoc.v:49598$2048
+ attribute \src "libresoc.v:50277.14-50277.32"
+ process $proc$libresoc.v:50277$2088
assign { } { }
assign $1\wb_rd_data[31:0] 0
sync always
sync init
update \wb_rd_data $1\wb_rd_data[31:0]
end
- attribute \src "libresoc.v:49608.14-49608.31"
- process $proc$libresoc.v:49608$2049
+ attribute \src "libresoc.v:50287.14-50287.31"
+ process $proc$libresoc.v:50287$2089
assign { } { }
assign $1\xisr[23:0] 24'000000000000000000000000
sync always
sync init
update \xisr $1\xisr[23:0]
end
- attribute \src "libresoc.v:49625.3-49626.37"
- process $proc$libresoc.v:49625$1996
+ attribute \src "libresoc.v:50304.3-50305.37"
+ process $proc$libresoc.v:50304$2036
assign { } { }
assign $0\core_irq_o[0:0] \core_irq_o$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \core_irq_o $0\core_irq_o[0:0]
end
- attribute \src "libresoc.v:49627.3-49628.25"
- process $proc$libresoc.v:49627$1997
+ attribute \src "libresoc.v:50306.3-50307.25"
+ process $proc$libresoc.v:50306$2037
assign { } { }
assign $0\xisr[23:0] \xisr$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xisr $0\xisr[23:0]
end
- attribute \src "libresoc.v:49629.3-49630.25"
- process $proc$libresoc.v:49629$1998
+ attribute \src "libresoc.v:50308.3-50309.25"
+ process $proc$libresoc.v:50308$2038
assign { } { }
assign $0\cppr[7:0] \cppr$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \cppr $0\cppr[7:0]
end
- attribute \src "libresoc.v:49631.3-49632.25"
- process $proc$libresoc.v:49631$1999
+ attribute \src "libresoc.v:50310.3-50311.25"
+ process $proc$libresoc.v:50310$2039
assign { } { }
assign $0\mfrr[7:0] \mfrr$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \mfrr $0\mfrr[7:0]
end
- attribute \src "libresoc.v:49633.3-49634.23"
- process $proc$libresoc.v:49633$2000
+ attribute \src "libresoc.v:50312.3-50313.23"
+ process $proc$libresoc.v:50312$2040
assign { } { }
assign $0\irq[0:0] \irq$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \irq $0\irq[0:0]
end
- attribute \src "libresoc.v:49635.3-49636.37"
- process $proc$libresoc.v:49635$2001
+ attribute \src "libresoc.v:50314.3-50315.37"
+ process $proc$libresoc.v:50314$2041
assign { } { }
assign $0\wb_rd_data[31:0] \wb_rd_data$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \wb_rd_data $0\wb_rd_data[31:0]
end
- attribute \src "libresoc.v:49637.3-49638.29"
- process $proc$libresoc.v:49637$2002
+ attribute \src "libresoc.v:50316.3-50317.29"
+ process $proc$libresoc.v:50316$2042
assign { } { }
assign $0\wb_ack[0:0] \wb_ack$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \wb_ack $0\wb_ack[0:0]
end
- attribute \src "libresoc.v:49639.3-49654.6"
- process $proc$libresoc.v:49639$2003
+ attribute \src "libresoc.v:50318.3-50333.6"
+ process $proc$libresoc.v:50318$2043
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cppr$next[7:0]$2004 $1\cppr$next[7:0]$2010
- assign $0\irq$next[0:0]$2005 $1\irq$next[0:0]$2011
- assign $0\mfrr$next[7:0]$2006 $1\mfrr$next[7:0]$2012
- assign $0\wb_ack$next[0:0]$2007 $1\wb_ack$next[0:0]$2013
- assign $0\wb_rd_data$next[31:0]$2008 $1\wb_rd_data$next[31:0]$2014
- assign $0\xisr$next[23:0]$2009 $1\xisr$next[23:0]$2015
- attribute \src "libresoc.v:49640.5-49640.29"
+ assign $0\cppr$next[7:0]$2044 $1\cppr$next[7:0]$2050
+ assign $0\irq$next[0:0]$2045 $1\irq$next[0:0]$2051
+ assign $0\mfrr$next[7:0]$2046 $1\mfrr$next[7:0]$2052
+ assign $0\wb_ack$next[0:0]$2047 $1\wb_ack$next[0:0]$2053
+ assign $0\wb_rd_data$next[31:0]$2048 $1\wb_rd_data$next[31:0]$2054
+ assign $0\xisr$next[23:0]$2049 $1\xisr$next[23:0]$2055
+ attribute \src "libresoc.v:50319.5-50319.29"
switch \initial
- attribute \src "libresoc.v:49640.9-49640.17"
+ attribute \src "libresoc.v:50319.9-50319.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\xisr$next[23:0]$2015 24'000000000000000000000000
- assign $1\cppr$next[7:0]$2010 8'00000000
- assign $1\mfrr$next[7:0]$2012 8'11111111
- assign $1\irq$next[0:0]$2011 1'0
- assign $1\wb_rd_data$next[31:0]$2014 0
- assign $1\wb_ack$next[0:0]$2013 1'0
+ assign $1\xisr$next[23:0]$2055 24'000000000000000000000000
+ assign $1\cppr$next[7:0]$2050 8'00000000
+ assign $1\mfrr$next[7:0]$2052 8'11111111
+ assign $1\irq$next[0:0]$2051 1'0
+ assign $1\wb_rd_data$next[31:0]$2054 0
+ assign $1\wb_ack$next[0:0]$2053 1'0
case
- assign $1\cppr$next[7:0]$2010 \cppr$2
- assign $1\irq$next[0:0]$2011 \irq$4
- assign $1\mfrr$next[7:0]$2012 \mfrr$3
- assign $1\wb_ack$next[0:0]$2013 \wb_ack$6
- assign $1\wb_rd_data$next[31:0]$2014 \wb_rd_data$5
- assign $1\xisr$next[23:0]$2015 \xisr$1
+ assign $1\cppr$next[7:0]$2050 \cppr$2
+ assign $1\irq$next[0:0]$2051 \irq$4
+ assign $1\mfrr$next[7:0]$2052 \mfrr$3
+ assign $1\wb_ack$next[0:0]$2053 \wb_ack$6
+ assign $1\wb_rd_data$next[31:0]$2054 \wb_rd_data$5
+ assign $1\xisr$next[23:0]$2055 \xisr$1
end
sync always
- update \cppr$next $0\cppr$next[7:0]$2004
- update \irq$next $0\irq$next[0:0]$2005
- update \mfrr$next $0\mfrr$next[7:0]$2006
- update \wb_ack$next $0\wb_ack$next[0:0]$2007
- update \wb_rd_data$next $0\wb_rd_data$next[31:0]$2008
- update \xisr$next $0\xisr$next[23:0]$2009
+ update \cppr$next $0\cppr$next[7:0]$2044
+ update \irq$next $0\irq$next[0:0]$2045
+ update \mfrr$next $0\mfrr$next[7:0]$2046
+ update \wb_ack$next $0\wb_ack$next[0:0]$2047
+ update \wb_rd_data$next $0\wb_rd_data$next[31:0]$2048
+ update \xisr$next $0\xisr$next[23:0]$2049
end
- attribute \src "libresoc.v:49655.3-49682.6"
- process $proc$libresoc.v:49655$2016
+ attribute \src "libresoc.v:50334.3-50361.6"
+ process $proc$libresoc.v:50334$2056
assign { } { }
assign { } { }
assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:49656.5-49656.29"
+ attribute \src "libresoc.v:50335.5-50335.29"
switch \initial
- attribute \src "libresoc.v:49656.9-49656.17"
+ attribute \src "libresoc.v:50335.9-50335.17"
case 1'1
case
end
sync always
update \xirr_accept_rd $0\xirr_accept_rd[0:0]
end
- attribute \src "libresoc.v:49683.3-49711.6"
- process $proc$libresoc.v:49683$2017
+ attribute \src "libresoc.v:50362.3-50390.6"
+ process $proc$libresoc.v:50362$2057
assign { } { }
assign { } { }
assign $0\be_out[31:0] $1\be_out[31:0]
- attribute \src "libresoc.v:49684.5-49684.29"
+ attribute \src "libresoc.v:50363.5-50363.29"
switch \initial
- attribute \src "libresoc.v:49684.9-49684.17"
+ attribute \src "libresoc.v:50363.9-50363.17"
case 1'1
case
end
sync always
update \be_out $0\be_out[31:0]
end
- attribute \src "libresoc.v:49712.3-49721.6"
- process $proc$libresoc.v:49712$2018
+ attribute \src "libresoc.v:50391.3-50400.6"
+ process $proc$libresoc.v:50391$2058
assign { } { }
assign { } { }
assign $0\pending_priority[7:0] $1\pending_priority[7:0]
- attribute \src "libresoc.v:49713.5-49713.29"
+ attribute \src "libresoc.v:50392.5-50392.29"
switch \initial
- attribute \src "libresoc.v:49713.9-49713.17"
+ attribute \src "libresoc.v:50392.9-50392.17"
case 1'1
case
end
sync always
update \pending_priority $0\pending_priority[7:0]
end
- attribute \src "libresoc.v:49722.3-49733.6"
- process $proc$libresoc.v:49722$2019
+ attribute \src "libresoc.v:50401.3-50412.6"
+ process $proc$libresoc.v:50401$2059
assign { } { }
assign $0\min_pri[7:0] $1\min_pri[7:0]
- attribute \src "libresoc.v:49723.5-49723.29"
+ attribute \src "libresoc.v:50402.5-50402.29"
switch \initial
- attribute \src "libresoc.v:49723.9-49723.17"
+ attribute \src "libresoc.v:50402.9-50402.17"
case 1'1
case
end
sync always
update \min_pri $0\min_pri[7:0]
end
- attribute \src "libresoc.v:49734.3-49742.6"
- process $proc$libresoc.v:49734$2020
+ attribute \src "libresoc.v:50413.3-50421.6"
+ process $proc$libresoc.v:50413$2060
assign { } { }
assign { } { }
- assign $0\core_irq_o$next[0:0]$2021 $1\core_irq_o$next[0:0]$2022
- attribute \src "libresoc.v:49735.5-49735.29"
+ assign $0\core_irq_o$next[0:0]$2061 $1\core_irq_o$next[0:0]$2062
+ attribute \src "libresoc.v:50414.5-50414.29"
switch \initial
- attribute \src "libresoc.v:49735.9-49735.17"
+ attribute \src "libresoc.v:50414.9-50414.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\core_irq_o$next[0:0]$2022 1'0
+ assign $1\core_irq_o$next[0:0]$2062 1'0
case
- assign $1\core_irq_o$next[0:0]$2022 \irq
+ assign $1\core_irq_o$next[0:0]$2062 \irq
end
sync always
- update \core_irq_o$next $0\core_irq_o$next[0:0]$2021
+ update \core_irq_o$next $0\core_irq_o$next[0:0]$2061
end
- attribute \src "libresoc.v:49743.3-49752.6"
- process $proc$libresoc.v:49743$2023
+ attribute \src "libresoc.v:50422.3-50431.6"
+ process $proc$libresoc.v:50422$2063
assign { } { }
assign { } { }
assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:49744.5-49744.29"
+ attribute \src "libresoc.v:50423.5-50423.29"
switch \initial
- attribute \src "libresoc.v:49744.9-49744.17"
+ attribute \src "libresoc.v:50423.9-50423.17"
case 1'1
case
end
sync always
update \icp_wb__dat_r $0\icp_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:49753.3-49815.6"
- process $proc$libresoc.v:49753$2024
+ attribute \src "libresoc.v:50432.3-50494.6"
+ process $proc$libresoc.v:50432$2064
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mfrr$11[7:0]$2027 $1\mfrr$11[7:0]$2032
- assign $0\wb_ack$14[0:0]$2028 $1\wb_ack$14[0:0]$2033
+ assign $0\mfrr$11[7:0]$2067 $1\mfrr$11[7:0]$2072
+ assign $0\wb_ack$14[0:0]$2068 $1\wb_ack$14[0:0]$2073
assign { } { }
assign { } { }
assign { } { }
- assign $0\xisr$9[23:0]$2030 $2\xisr$9[23:0]$2039
- assign $0\cppr$10[7:0]$2025 $4\cppr$10[7:0]$2040
- assign $0\wb_rd_data$13[31:0]$2029 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
- assign $0\irq$12[0:0]$2026 $1\irq$12[0:0]$2041
- attribute \src "libresoc.v:49754.5-49754.29"
+ assign $0\xisr$9[23:0]$2070 $2\xisr$9[23:0]$2079
+ assign $0\cppr$10[7:0]$2065 $4\cppr$10[7:0]$2080
+ assign $0\wb_rd_data$13[31:0]$2069 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
+ assign $0\irq$12[0:0]$2066 $1\irq$12[0:0]$2081
+ attribute \src "libresoc.v:50433.5-50433.29"
switch \initial
- attribute \src "libresoc.v:49754.9-49754.17"
+ attribute \src "libresoc.v:50433.9-50433.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wb_ack$14[0:0]$2033 1'1
- assign $1\cppr$10[7:0]$2031 $2\cppr$10[7:0]$2034
- assign $1\mfrr$11[7:0]$2032 $2\mfrr$11[7:0]$2035
+ assign $1\wb_ack$14[0:0]$2073 1'1
+ assign $1\cppr$10[7:0]$2071 $2\cppr$10[7:0]$2074
+ assign $1\mfrr$11[7:0]$2072 $2\mfrr$11[7:0]$2075
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119"
switch \icp_wb__we
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
- assign $2\cppr$10[7:0]$2034 $3\cppr$10[7:0]$2036
- assign $2\mfrr$11[7:0]$2035 $3\mfrr$11[7:0]$2037
+ assign $2\cppr$10[7:0]$2074 $3\cppr$10[7:0]$2076
+ assign $2\mfrr$11[7:0]$2075 $3\mfrr$11[7:0]$2077
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121"
switch \icp_wb__adr [5:0]
attribute \src "libresoc.v:0.0-0.0"
case 6'000000
assign { } { }
- assign $3\mfrr$11[7:0]$2037 \mfrr
- assign $3\cppr$10[7:0]$2036 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$2077 \mfrr
+ assign $3\cppr$10[7:0]$2076 \be_in [31:24]
attribute \src "libresoc.v:0.0-0.0"
case 6'000001
assign { } { }
- assign $3\mfrr$11[7:0]$2037 \mfrr
- assign $3\cppr$10[7:0]$2036 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$2077 \mfrr
+ assign $3\cppr$10[7:0]$2076 \be_in [31:24]
attribute \src "libresoc.v:0.0-0.0"
case 6'000011
- assign $3\cppr$10[7:0]$2036 \cppr
+ assign $3\cppr$10[7:0]$2076 \cppr
assign { } { }
- assign $3\mfrr$11[7:0]$2037 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$2077 \be_in [31:24]
case
- assign $3\cppr$10[7:0]$2036 \cppr
- assign $3\mfrr$11[7:0]$2037 \mfrr
+ assign $3\cppr$10[7:0]$2076 \cppr
+ assign $3\mfrr$11[7:0]$2077 \mfrr
end
case
- assign $2\cppr$10[7:0]$2034 \cppr
- assign $2\mfrr$11[7:0]$2035 \mfrr
+ assign $2\cppr$10[7:0]$2074 \cppr
+ assign $2\mfrr$11[7:0]$2075 \mfrr
end
case
- assign $1\cppr$10[7:0]$2031 \cppr
- assign $1\mfrr$11[7:0]$2032 \mfrr
- assign $1\wb_ack$14[0:0]$2033 1'0
+ assign $1\cppr$10[7:0]$2071 \cppr
+ assign $1\mfrr$11[7:0]$2072 \mfrr
+ assign $1\wb_ack$14[0:0]$2073 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
switch \$17
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xisr$9[23:0]$2038 { 20'00000000000000000001 \ics_i_src }
+ assign $1\xisr$9[23:0]$2078 { 20'00000000000000000001 \ics_i_src }
case
- assign $1\xisr$9[23:0]$2038 24'000000000000000000000000
+ assign $1\xisr$9[23:0]$2078 24'000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
switch \$19
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xisr$9[23:0]$2039 24'000000000000000000000010
+ assign $2\xisr$9[23:0]$2079 24'000000000000000000000010
case
- assign $2\xisr$9[23:0]$2039 $1\xisr$9[23:0]$2038
+ assign $2\xisr$9[23:0]$2079 $1\xisr$9[23:0]$2078
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185"
switch \xirr_accept_rd
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cppr$10[7:0]$2040 \min_pri
+ assign $4\cppr$10[7:0]$2080 \min_pri
case
- assign $4\cppr$10[7:0]$2040 $1\cppr$10[7:0]$2031
+ assign $4\cppr$10[7:0]$2080 $1\cppr$10[7:0]$2071
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
switch { \irq \$21 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\irq$12[0:0]$2041 1'1
+ assign $1\irq$12[0:0]$2081 1'1
case
- assign $1\irq$12[0:0]$2041 1'0
+ assign $1\irq$12[0:0]$2081 1'0
end
sync always
- update \cppr$10 $0\cppr$10[7:0]$2025
- update \irq$12 $0\irq$12[0:0]$2026
- update \mfrr$11 $0\mfrr$11[7:0]$2027
- update \wb_ack$14 $0\wb_ack$14[0:0]$2028
- update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$2029
- update \xisr$9 $0\xisr$9[23:0]$2030
+ update \cppr$10 $0\cppr$10[7:0]$2065
+ update \irq$12 $0\irq$12[0:0]$2066
+ update \mfrr$11 $0\mfrr$11[7:0]$2067
+ update \wb_ack$14 $0\wb_ack$14[0:0]$2068
+ update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$2069
+ update \xisr$9 $0\xisr$9[23:0]$2070
end
- connect \$15 $and$libresoc.v:49615$1986_Y
- connect \$17 $ne$libresoc.v:49616$1987_Y
- connect \$19 $lt$libresoc.v:49617$1988_Y
- connect \$21 $lt$libresoc.v:49618$1989_Y
- connect \$23 $and$libresoc.v:49619$1990_Y
- connect \$25 $eq$libresoc.v:49620$1991_Y
- connect \$27 $and$libresoc.v:49621$1992_Y
- connect \$29 $ne$libresoc.v:49622$1993_Y
- connect \$31 $lt$libresoc.v:49623$1994_Y
- connect \$7 $and$libresoc.v:49624$1995_Y
+ connect \$15 $and$libresoc.v:50294$2026_Y
+ connect \$17 $ne$libresoc.v:50295$2027_Y
+ connect \$19 $lt$libresoc.v:50296$2028_Y
+ connect \$21 $lt$libresoc.v:50297$2029_Y
+ connect \$23 $and$libresoc.v:50298$2030_Y
+ connect \$25 $eq$libresoc.v:50299$2031_Y
+ connect \$27 $and$libresoc.v:50300$2032_Y
+ connect \$29 $ne$libresoc.v:50301$2033_Y
+ connect \$31 $lt$libresoc.v:50302$2034_Y
+ connect \$7 $and$libresoc.v:50303$2035_Y
connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 }
connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] }
connect \icp_wb__ack \$7
end
-attribute \src "libresoc.v:49823.1-50872.10"
+attribute \src "libresoc.v:50502.1-51551.10"
attribute \cells_not_processed 1
-attribute \nmigen.hierarchy "test_issuer.xics_ics"
+attribute \nmigen.hierarchy "test_issuer.ti.xics_ics"
attribute \generator "nMigen"
module \xics_ics
- attribute \src "libresoc.v:50753.3-50802.6"
+ attribute \src "libresoc.v:51432.3-51481.6"
wire width 32 $0\be_out[31:0]
- attribute \src "libresoc.v:50464.3-50473.6"
+ attribute \src "libresoc.v:51143.3-51152.6"
wire width 4 $0\cur_idx0[3:0]
- attribute \src "libresoc.v:50673.3-50682.6"
+ attribute \src "libresoc.v:51352.3-51361.6"
wire width 4 $0\cur_idx10[3:0]
- attribute \src "libresoc.v:50693.3-50702.6"
+ attribute \src "libresoc.v:51372.3-51381.6"
wire width 4 $0\cur_idx11[3:0]
- attribute \src "libresoc.v:50713.3-50722.6"
+ attribute \src "libresoc.v:51392.3-51401.6"
wire width 4 $0\cur_idx12[3:0]
- attribute \src "libresoc.v:50733.3-50742.6"
+ attribute \src "libresoc.v:51412.3-51421.6"
wire width 4 $0\cur_idx13[3:0]
- attribute \src "libresoc.v:50803.3-50812.6"
+ attribute \src "libresoc.v:51482.3-51491.6"
wire width 4 $0\cur_idx14[3:0]
- attribute \src "libresoc.v:50823.3-50832.6"
+ attribute \src "libresoc.v:51502.3-51511.6"
wire width 4 $0\cur_idx15[3:0]
- attribute \src "libresoc.v:50484.3-50493.6"
+ attribute \src "libresoc.v:51163.3-51172.6"
wire width 4 $0\cur_idx1[3:0]
- attribute \src "libresoc.v:50504.3-50513.6"
+ attribute \src "libresoc.v:51183.3-51192.6"
wire width 4 $0\cur_idx2[3:0]
- attribute \src "libresoc.v:50524.3-50533.6"
+ attribute \src "libresoc.v:51203.3-51212.6"
wire width 4 $0\cur_idx3[3:0]
- attribute \src "libresoc.v:50553.3-50562.6"
+ attribute \src "libresoc.v:51232.3-51241.6"
wire width 4 $0\cur_idx4[3:0]
- attribute \src "libresoc.v:50573.3-50582.6"
+ attribute \src "libresoc.v:51252.3-51261.6"
wire width 4 $0\cur_idx5[3:0]
- attribute \src "libresoc.v:50593.3-50602.6"
+ attribute \src "libresoc.v:51272.3-51281.6"
wire width 4 $0\cur_idx6[3:0]
- attribute \src "libresoc.v:50613.3-50622.6"
+ attribute \src "libresoc.v:51292.3-51301.6"
wire width 4 $0\cur_idx7[3:0]
- attribute \src "libresoc.v:50633.3-50642.6"
+ attribute \src "libresoc.v:51312.3-51321.6"
wire width 4 $0\cur_idx8[3:0]
- attribute \src "libresoc.v:50653.3-50662.6"
+ attribute \src "libresoc.v:51332.3-51341.6"
wire width 4 $0\cur_idx9[3:0]
- attribute \src "libresoc.v:50454.3-50463.6"
+ attribute \src "libresoc.v:51133.3-51142.6"
wire width 8 $0\cur_pri0[7:0]
- attribute \src "libresoc.v:50663.3-50672.6"
+ attribute \src "libresoc.v:51342.3-51351.6"
wire width 8 $0\cur_pri10[7:0]
- attribute \src "libresoc.v:50683.3-50692.6"
+ attribute \src "libresoc.v:51362.3-51371.6"
wire width 8 $0\cur_pri11[7:0]
- attribute \src "libresoc.v:50703.3-50712.6"
+ attribute \src "libresoc.v:51382.3-51391.6"
wire width 8 $0\cur_pri12[7:0]
- attribute \src "libresoc.v:50723.3-50732.6"
+ attribute \src "libresoc.v:51402.3-51411.6"
wire width 8 $0\cur_pri13[7:0]
- attribute \src "libresoc.v:50743.3-50752.6"
+ attribute \src "libresoc.v:51422.3-51431.6"
wire width 8 $0\cur_pri14[7:0]
- attribute \src "libresoc.v:50813.3-50822.6"
+ attribute \src "libresoc.v:51492.3-51501.6"
wire width 8 $0\cur_pri15[7:0]
- attribute \src "libresoc.v:50474.3-50483.6"
+ attribute \src "libresoc.v:51153.3-51162.6"
wire width 8 $0\cur_pri1[7:0]
- attribute \src "libresoc.v:50494.3-50503.6"
+ attribute \src "libresoc.v:51173.3-51182.6"
wire width 8 $0\cur_pri2[7:0]
- attribute \src "libresoc.v:50514.3-50523.6"
+ attribute \src "libresoc.v:51193.3-51202.6"
wire width 8 $0\cur_pri3[7:0]
- attribute \src "libresoc.v:50534.3-50543.6"
+ attribute \src "libresoc.v:51213.3-51222.6"
wire width 8 $0\cur_pri4[7:0]
- attribute \src "libresoc.v:50563.3-50572.6"
+ attribute \src "libresoc.v:51242.3-51251.6"
wire width 8 $0\cur_pri5[7:0]
- attribute \src "libresoc.v:50583.3-50592.6"
+ attribute \src "libresoc.v:51262.3-51271.6"
wire width 8 $0\cur_pri6[7:0]
- attribute \src "libresoc.v:50603.3-50612.6"
+ attribute \src "libresoc.v:51282.3-51291.6"
wire width 8 $0\cur_pri7[7:0]
- attribute \src "libresoc.v:50623.3-50632.6"
+ attribute \src "libresoc.v:51302.3-51311.6"
wire width 8 $0\cur_pri8[7:0]
- attribute \src "libresoc.v:50643.3-50652.6"
+ attribute \src "libresoc.v:51322.3-51331.6"
wire width 8 $0\cur_pri9[7:0]
- attribute \src "libresoc.v:50833.3-50842.6"
+ attribute \src "libresoc.v:51512.3-51521.6"
wire $0\ibit[0:0]
- attribute \src "libresoc.v:50328.3-50329.25"
+ attribute \src "libresoc.v:51017.3-51018.25"
wire width 8 $0\icp_o_pri[7:0]
- attribute \src "libresoc.v:50326.3-50327.28"
+ attribute \src "libresoc.v:51015.3-51016.28"
wire width 4 $0\icp_o_src[3:0]
- attribute \src "libresoc.v:50852.3-50860.6"
- wire $0\ics_wb__ack$next[0:0]$2296
- attribute \src "libresoc.v:50362.3-50363.39"
+ attribute \src "libresoc.v:51531.3-51539.6"
+ wire $0\ics_wb__ack$next[0:0]$2336
+ attribute \src "libresoc.v:51009.3-51010.39"
wire $0\ics_wb__ack[0:0]
- attribute \src "libresoc.v:50843.3-50851.6"
- wire width 32 $0\ics_wb__dat_r$next[31:0]$2293
- attribute \src "libresoc.v:50364.3-50365.43"
+ attribute \src "libresoc.v:51522.3-51530.6"
+ wire width 32 $0\ics_wb__dat_r$next[31:0]$2333
+ attribute \src "libresoc.v:51011.3-51012.43"
wire width 32 $0\ics_wb__dat_r[31:0]
- attribute \src "libresoc.v:49824.7-49824.20"
+ attribute \src "libresoc.v:50503.7-50503.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:50544.3-50552.6"
- wire width 16 $0\int_level_l$next[15:0]$2265
- attribute \src "libresoc.v:50366.3-50367.39"
+ attribute \src "libresoc.v:51223.3-51231.6"
+ wire width 16 $0\int_level_l$next[15:0]$2305
+ attribute \src "libresoc.v:51013.3-51014.39"
wire width 16 $0\int_level_l[15:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive0_pri$next[7:0]$2175
- attribute \src "libresoc.v:50330.3-50331.35"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive0_pri$next[7:0]$2215
+ attribute \src "libresoc.v:51019.3-51020.35"
wire width 8 $0\xive0_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive10_pri$next[7:0]$2176
- attribute \src "libresoc.v:50350.3-50351.37"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive10_pri$next[7:0]$2216
+ attribute \src "libresoc.v:51039.3-51040.37"
wire width 8 $0\xive10_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive11_pri$next[7:0]$2177
- attribute \src "libresoc.v:50352.3-50353.37"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive11_pri$next[7:0]$2217
+ attribute \src "libresoc.v:51041.3-51042.37"
wire width 8 $0\xive11_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive12_pri$next[7:0]$2178
- attribute \src "libresoc.v:50354.3-50355.37"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive12_pri$next[7:0]$2218
+ attribute \src "libresoc.v:51043.3-51044.37"
wire width 8 $0\xive12_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive13_pri$next[7:0]$2179
- attribute \src "libresoc.v:50356.3-50357.37"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive13_pri$next[7:0]$2219
+ attribute \src "libresoc.v:51045.3-51046.37"
wire width 8 $0\xive13_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive14_pri$next[7:0]$2180
- attribute \src "libresoc.v:50358.3-50359.37"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive14_pri$next[7:0]$2220
+ attribute \src "libresoc.v:51005.3-51006.37"
wire width 8 $0\xive14_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive15_pri$next[7:0]$2181
- attribute \src "libresoc.v:50360.3-50361.37"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive15_pri$next[7:0]$2221
+ attribute \src "libresoc.v:51007.3-51008.37"
wire width 8 $0\xive15_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive1_pri$next[7:0]$2182
- attribute \src "libresoc.v:50332.3-50333.35"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive1_pri$next[7:0]$2222
+ attribute \src "libresoc.v:51021.3-51022.35"
wire width 8 $0\xive1_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive2_pri$next[7:0]$2183
- attribute \src "libresoc.v:50334.3-50335.35"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive2_pri$next[7:0]$2223
+ attribute \src "libresoc.v:51023.3-51024.35"
wire width 8 $0\xive2_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive3_pri$next[7:0]$2184
- attribute \src "libresoc.v:50336.3-50337.35"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive3_pri$next[7:0]$2224
+ attribute \src "libresoc.v:51025.3-51026.35"
wire width 8 $0\xive3_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive4_pri$next[7:0]$2185
- attribute \src "libresoc.v:50338.3-50339.35"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive4_pri$next[7:0]$2225
+ attribute \src "libresoc.v:51027.3-51028.35"
wire width 8 $0\xive4_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive5_pri$next[7:0]$2186
- attribute \src "libresoc.v:50340.3-50341.35"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive5_pri$next[7:0]$2226
+ attribute \src "libresoc.v:51029.3-51030.35"
wire width 8 $0\xive5_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive6_pri$next[7:0]$2187
- attribute \src "libresoc.v:50342.3-50343.35"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive6_pri$next[7:0]$2227
+ attribute \src "libresoc.v:51031.3-51032.35"
wire width 8 $0\xive6_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive7_pri$next[7:0]$2188
- attribute \src "libresoc.v:50344.3-50345.35"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive7_pri$next[7:0]$2228
+ attribute \src "libresoc.v:51033.3-51034.35"
wire width 8 $0\xive7_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive8_pri$next[7:0]$2189
- attribute \src "libresoc.v:50346.3-50347.35"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive8_pri$next[7:0]$2229
+ attribute \src "libresoc.v:51035.3-51036.35"
wire width 8 $0\xive8_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $0\xive9_pri$next[7:0]$2190
- attribute \src "libresoc.v:50348.3-50349.35"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $0\xive9_pri$next[7:0]$2230
+ attribute \src "libresoc.v:51037.3-51038.35"
wire width 8 $0\xive9_pri[7:0]
- attribute \src "libresoc.v:50753.3-50802.6"
+ attribute \src "libresoc.v:51432.3-51481.6"
wire width 32 $1\be_out[31:0]
- attribute \src "libresoc.v:50464.3-50473.6"
+ attribute \src "libresoc.v:51143.3-51152.6"
wire width 4 $1\cur_idx0[3:0]
- attribute \src "libresoc.v:50673.3-50682.6"
+ attribute \src "libresoc.v:51352.3-51361.6"
wire width 4 $1\cur_idx10[3:0]
- attribute \src "libresoc.v:50693.3-50702.6"
+ attribute \src "libresoc.v:51372.3-51381.6"
wire width 4 $1\cur_idx11[3:0]
- attribute \src "libresoc.v:50713.3-50722.6"
+ attribute \src "libresoc.v:51392.3-51401.6"
wire width 4 $1\cur_idx12[3:0]
- attribute \src "libresoc.v:50733.3-50742.6"
+ attribute \src "libresoc.v:51412.3-51421.6"
wire width 4 $1\cur_idx13[3:0]
- attribute \src "libresoc.v:50803.3-50812.6"
+ attribute \src "libresoc.v:51482.3-51491.6"
wire width 4 $1\cur_idx14[3:0]
- attribute \src "libresoc.v:50823.3-50832.6"
+ attribute \src "libresoc.v:51502.3-51511.6"
wire width 4 $1\cur_idx15[3:0]
- attribute \src "libresoc.v:50484.3-50493.6"
+ attribute \src "libresoc.v:51163.3-51172.6"
wire width 4 $1\cur_idx1[3:0]
- attribute \src "libresoc.v:50504.3-50513.6"
+ attribute \src "libresoc.v:51183.3-51192.6"
wire width 4 $1\cur_idx2[3:0]
- attribute \src "libresoc.v:50524.3-50533.6"
+ attribute \src "libresoc.v:51203.3-51212.6"
wire width 4 $1\cur_idx3[3:0]
- attribute \src "libresoc.v:50553.3-50562.6"
+ attribute \src "libresoc.v:51232.3-51241.6"
wire width 4 $1\cur_idx4[3:0]
- attribute \src "libresoc.v:50573.3-50582.6"
+ attribute \src "libresoc.v:51252.3-51261.6"
wire width 4 $1\cur_idx5[3:0]
- attribute \src "libresoc.v:50593.3-50602.6"
+ attribute \src "libresoc.v:51272.3-51281.6"
wire width 4 $1\cur_idx6[3:0]
- attribute \src "libresoc.v:50613.3-50622.6"
+ attribute \src "libresoc.v:51292.3-51301.6"
wire width 4 $1\cur_idx7[3:0]
- attribute \src "libresoc.v:50633.3-50642.6"
+ attribute \src "libresoc.v:51312.3-51321.6"
wire width 4 $1\cur_idx8[3:0]
- attribute \src "libresoc.v:50653.3-50662.6"
+ attribute \src "libresoc.v:51332.3-51341.6"
wire width 4 $1\cur_idx9[3:0]
- attribute \src "libresoc.v:50454.3-50463.6"
+ attribute \src "libresoc.v:51133.3-51142.6"
wire width 8 $1\cur_pri0[7:0]
- attribute \src "libresoc.v:50663.3-50672.6"
+ attribute \src "libresoc.v:51342.3-51351.6"
wire width 8 $1\cur_pri10[7:0]
- attribute \src "libresoc.v:50683.3-50692.6"
+ attribute \src "libresoc.v:51362.3-51371.6"
wire width 8 $1\cur_pri11[7:0]
- attribute \src "libresoc.v:50703.3-50712.6"
+ attribute \src "libresoc.v:51382.3-51391.6"
wire width 8 $1\cur_pri12[7:0]
- attribute \src "libresoc.v:50723.3-50732.6"
+ attribute \src "libresoc.v:51402.3-51411.6"
wire width 8 $1\cur_pri13[7:0]
- attribute \src "libresoc.v:50743.3-50752.6"
+ attribute \src "libresoc.v:51422.3-51431.6"
wire width 8 $1\cur_pri14[7:0]
- attribute \src "libresoc.v:50813.3-50822.6"
+ attribute \src "libresoc.v:51492.3-51501.6"
wire width 8 $1\cur_pri15[7:0]
- attribute \src "libresoc.v:50474.3-50483.6"
+ attribute \src "libresoc.v:51153.3-51162.6"
wire width 8 $1\cur_pri1[7:0]
- attribute \src "libresoc.v:50494.3-50503.6"
+ attribute \src "libresoc.v:51173.3-51182.6"
wire width 8 $1\cur_pri2[7:0]
- attribute \src "libresoc.v:50514.3-50523.6"
+ attribute \src "libresoc.v:51193.3-51202.6"
wire width 8 $1\cur_pri3[7:0]
- attribute \src "libresoc.v:50534.3-50543.6"
+ attribute \src "libresoc.v:51213.3-51222.6"
wire width 8 $1\cur_pri4[7:0]
- attribute \src "libresoc.v:50563.3-50572.6"
+ attribute \src "libresoc.v:51242.3-51251.6"
wire width 8 $1\cur_pri5[7:0]
- attribute \src "libresoc.v:50583.3-50592.6"
+ attribute \src "libresoc.v:51262.3-51271.6"
wire width 8 $1\cur_pri6[7:0]
- attribute \src "libresoc.v:50603.3-50612.6"
+ attribute \src "libresoc.v:51282.3-51291.6"
wire width 8 $1\cur_pri7[7:0]
- attribute \src "libresoc.v:50623.3-50632.6"
+ attribute \src "libresoc.v:51302.3-51311.6"
wire width 8 $1\cur_pri8[7:0]
- attribute \src "libresoc.v:50643.3-50652.6"
+ attribute \src "libresoc.v:51322.3-51331.6"
wire width 8 $1\cur_pri9[7:0]
- attribute \src "libresoc.v:50833.3-50842.6"
+ attribute \src "libresoc.v:51512.3-51521.6"
wire $1\ibit[0:0]
- attribute \src "libresoc.v:50105.13-50105.30"
+ attribute \src "libresoc.v:50782.13-50782.30"
wire width 8 $1\icp_o_pri[7:0]
- attribute \src "libresoc.v:50110.13-50110.29"
+ attribute \src "libresoc.v:50787.13-50787.29"
wire width 4 $1\icp_o_src[3:0]
- attribute \src "libresoc.v:50852.3-50860.6"
- wire $1\ics_wb__ack$next[0:0]$2297
- attribute \src "libresoc.v:50119.7-50119.25"
+ attribute \src "libresoc.v:51531.3-51539.6"
+ wire $1\ics_wb__ack$next[0:0]$2337
+ attribute \src "libresoc.v:50796.7-50796.25"
wire $1\ics_wb__ack[0:0]
- attribute \src "libresoc.v:50843.3-50851.6"
- wire width 32 $1\ics_wb__dat_r$next[31:0]$2294
- attribute \src "libresoc.v:50128.14-50128.35"
+ attribute \src "libresoc.v:51522.3-51530.6"
+ wire width 32 $1\ics_wb__dat_r$next[31:0]$2334
+ attribute \src "libresoc.v:50805.14-50805.35"
wire width 32 $1\ics_wb__dat_r[31:0]
- attribute \src "libresoc.v:50544.3-50552.6"
- wire width 16 $1\int_level_l$next[15:0]$2266
- attribute \src "libresoc.v:50140.14-50140.36"
+ attribute \src "libresoc.v:51223.3-51231.6"
+ wire width 16 $1\int_level_l$next[15:0]$2306
+ attribute \src "libresoc.v:50817.14-50817.36"
wire width 16 $1\int_level_l[15:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive0_pri$next[7:0]$2191
- attribute \src "libresoc.v:50160.13-50160.30"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive0_pri$next[7:0]$2231
+ attribute \src "libresoc.v:50839.13-50839.30"
wire width 8 $1\xive0_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive10_pri$next[7:0]$2192
- attribute \src "libresoc.v:50164.13-50164.31"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive10_pri$next[7:0]$2232
+ attribute \src "libresoc.v:50843.13-50843.31"
wire width 8 $1\xive10_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive11_pri$next[7:0]$2193
- attribute \src "libresoc.v:50168.13-50168.31"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive11_pri$next[7:0]$2233
+ attribute \src "libresoc.v:50847.13-50847.31"
wire width 8 $1\xive11_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive12_pri$next[7:0]$2194
- attribute \src "libresoc.v:50172.13-50172.31"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive12_pri$next[7:0]$2234
+ attribute \src "libresoc.v:50851.13-50851.31"
wire width 8 $1\xive12_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive13_pri$next[7:0]$2195
- attribute \src "libresoc.v:50176.13-50176.31"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive13_pri$next[7:0]$2235
+ attribute \src "libresoc.v:50855.13-50855.31"
wire width 8 $1\xive13_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive14_pri$next[7:0]$2196
- attribute \src "libresoc.v:50180.13-50180.31"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive14_pri$next[7:0]$2236
+ attribute \src "libresoc.v:50859.13-50859.31"
wire width 8 $1\xive14_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive15_pri$next[7:0]$2197
- attribute \src "libresoc.v:50184.13-50184.31"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive15_pri$next[7:0]$2237
+ attribute \src "libresoc.v:50863.13-50863.31"
wire width 8 $1\xive15_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive1_pri$next[7:0]$2198
- attribute \src "libresoc.v:50188.13-50188.30"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive1_pri$next[7:0]$2238
+ attribute \src "libresoc.v:50867.13-50867.30"
wire width 8 $1\xive1_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive2_pri$next[7:0]$2199
- attribute \src "libresoc.v:50192.13-50192.30"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive2_pri$next[7:0]$2239
+ attribute \src "libresoc.v:50871.13-50871.30"
wire width 8 $1\xive2_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive3_pri$next[7:0]$2200
- attribute \src "libresoc.v:50196.13-50196.30"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive3_pri$next[7:0]$2240
+ attribute \src "libresoc.v:50875.13-50875.30"
wire width 8 $1\xive3_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive4_pri$next[7:0]$2201
- attribute \src "libresoc.v:50200.13-50200.30"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive4_pri$next[7:0]$2241
+ attribute \src "libresoc.v:50879.13-50879.30"
wire width 8 $1\xive4_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive5_pri$next[7:0]$2202
- attribute \src "libresoc.v:50204.13-50204.30"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive5_pri$next[7:0]$2242
+ attribute \src "libresoc.v:50883.13-50883.30"
wire width 8 $1\xive5_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive6_pri$next[7:0]$2203
- attribute \src "libresoc.v:50208.13-50208.30"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive6_pri$next[7:0]$2243
+ attribute \src "libresoc.v:50887.13-50887.30"
wire width 8 $1\xive6_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive7_pri$next[7:0]$2204
- attribute \src "libresoc.v:50212.13-50212.30"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive7_pri$next[7:0]$2244
+ attribute \src "libresoc.v:50891.13-50891.30"
wire width 8 $1\xive7_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive8_pri$next[7:0]$2205
- attribute \src "libresoc.v:50216.13-50216.30"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive8_pri$next[7:0]$2245
+ attribute \src "libresoc.v:50895.13-50895.30"
wire width 8 $1\xive8_pri[7:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $1\xive9_pri$next[7:0]$2206
- attribute \src "libresoc.v:50220.13-50220.30"
+ attribute \src "libresoc.v:51047.3-51132.6"
+ wire width 8 $1\xive9_pri$next[7:0]$2246
+ attribute \src "libresoc.v:50899.13-50899.30"
wire width 8 $1\xive9_pri[7:0]
- attribute \src "libresoc.v:50753.3-50802.6"
+ attribute \src "libresoc.v:51432.3-51481.6"
wire width 32 $2\be_out[31:0]
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive0_pri$next[7:0]$2207
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive10_pri$next[7:0]$2208
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive11_pri$next[7:0]$2209
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive12_pri$next[7:0]$2210
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive13_pri$next[7:0]$2211
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive14_pri$next[7:0]$2212
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive15_pri$next[7:0]$2213
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive1_pri$next[7:0]$2214
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive2_pri$next[7:0]$2215
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive3_pri$next[7:0]$2216
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive4_pri$next[7:0]$2217
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive5_pri$next[7:0]$2218
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive6_pri$next[7:0]$2219
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive7_pri$next[7:0]$2220
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive8_pri$next[7:0]$2221
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $2\xive9_pri$next[7:0]$2222
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive0_pri$next[7:0]$2223
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive10_pri$next[7:0]$2224
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive11_pri$next[7:0]$2225
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive12_pri$next[7:0]$2226
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive13_pri$next[7:0]$2227
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive14_pri$next[7:0]$2228
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive15_pri$next[7:0]$2229
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive1_pri$next[7:0]$2230
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive2_pri$next[7:0]$2231
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive3_pri$next[7:0]$2232
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive4_pri$next[7:0]$2233
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive5_pri$next[7:0]$2234
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive6_pri$next[7:0]$2235
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive7_pri$next[7:0]$2236
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive8_pri$next[7:0]$2237
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $3\xive9_pri$next[7:0]$2238
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive0_pri$next[7:0]$2239
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive10_pri$next[7:0]$2240
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive11_pri$next[7:0]$2241
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive12_pri$next[7:0]$2242
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive13_pri$next[7:0]$2243
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive14_pri$next[7:0]$2244
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive15_pri$next[7:0]$2245
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive1_pri$next[7:0]$2246
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive2_pri$next[7:0]$2247
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive3_pri$next[7:0]$2248
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive4_pri$next[7:0]$2249
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive5_pri$next[7:0]$2250
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive6_pri$next[7:0]$2251
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive7_pri$next[7:0]$2252
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive8_pri$next[7:0]$2253
- attribute \src "libresoc.v:50368.3-50453.6"
- wire width 8 $4\xive9_pri$next[7:0]$2254
- attribute \src "libresoc.v:50225.19-50225.113"
- wire $and$libresoc.v:50225$2052_Y
- attribute \src "libresoc.v:50227.19-50227.114"
- wire $and$libresoc.v:50227$2054_Y
- attribute \src "libresoc.v:50229.19-50229.114"
- wire $and$libresoc.v:50229$2056_Y
- attribute \src "libresoc.v:50231.19-50231.114"
- wire $and$libresoc.v:50231$2058_Y
- attribute \src "libresoc.v:50233.19-50233.114"
- wire $and$libresoc.v:50233$2060_Y
- attribute \src "libresoc.v:50235.19-50235.114"
- wire $and$libresoc.v:50235$2062_Y
- attribute \src "libresoc.v:50237.19-50237.114"
- wire $and$libresoc.v:50237$2064_Y
- attribute \src "libresoc.v:50240.19-50240.114"
- wire $and$libresoc.v:50240$2067_Y
- attribute \src "libresoc.v:50242.19-50242.114"
- wire $and$libresoc.v:50242$2069_Y
- attribute \src "libresoc.v:50244.19-50244.114"
- wire $and$libresoc.v:50244$2071_Y
- attribute \src "libresoc.v:50247.19-50247.114"
- wire $and$libresoc.v:50247$2074_Y
- attribute \src "libresoc.v:50249.19-50249.114"
- wire $and$libresoc.v:50249$2076_Y
- attribute \src "libresoc.v:50251.19-50251.114"
- wire $and$libresoc.v:50251$2078_Y
- attribute \src "libresoc.v:50253.19-50253.114"
- wire $and$libresoc.v:50253$2080_Y
- attribute \src "libresoc.v:50255.19-50255.115"
- wire $and$libresoc.v:50255$2082_Y
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+ wire $eq$libresoc.v:50981$2169_Y
+ attribute \src "libresoc.v:50984.18-50984.110"
+ wire $eq$libresoc.v:50984$2172_Y
+ attribute \src "libresoc.v:50986.18-50986.110"
+ wire $eq$libresoc.v:50986$2174_Y
+ attribute \src "libresoc.v:50988.18-50988.110"
+ wire $eq$libresoc.v:50988$2176_Y
+ attribute \src "libresoc.v:50999.17-50999.108"
+ wire $eq$libresoc.v:50999$2187_Y
+ attribute \src "libresoc.v:50903.18-50903.111"
+ wire $lt$libresoc.v:50903$2091_Y
+ attribute \src "libresoc.v:50905.19-50905.112"
+ wire $lt$libresoc.v:50905$2093_Y
+ attribute \src "libresoc.v:50907.19-50907.112"
+ wire $lt$libresoc.v:50907$2095_Y
+ attribute \src "libresoc.v:50909.19-50909.112"
+ wire $lt$libresoc.v:50909$2097_Y
+ attribute \src "libresoc.v:50911.19-50911.112"
+ wire $lt$libresoc.v:50911$2099_Y
+ attribute \src "libresoc.v:50913.19-50913.112"
+ wire $lt$libresoc.v:50913$2101_Y
+ attribute \src "libresoc.v:50915.19-50915.112"
+ wire $lt$libresoc.v:50915$2103_Y
+ attribute \src "libresoc.v:50917.19-50917.112"
+ wire $lt$libresoc.v:50917$2105_Y
+ attribute \src "libresoc.v:50920.19-50920.112"
+ wire $lt$libresoc.v:50920$2108_Y
+ attribute \src "libresoc.v:50922.19-50922.112"
+ wire $lt$libresoc.v:50922$2110_Y
+ attribute \src "libresoc.v:50925.19-50925.112"
+ wire $lt$libresoc.v:50925$2113_Y
+ attribute \src "libresoc.v:50927.19-50927.112"
+ wire $lt$libresoc.v:50927$2115_Y
+ attribute \src "libresoc.v:50929.19-50929.112"
+ wire $lt$libresoc.v:50929$2117_Y
+ attribute \src "libresoc.v:50931.19-50931.112"
+ wire $lt$libresoc.v:50931$2119_Y
+ attribute \src "libresoc.v:50933.19-50933.113"
+ wire $lt$libresoc.v:50933$2121_Y
+ attribute \src "libresoc.v:50935.19-50935.113"
+ wire $lt$libresoc.v:50935$2123_Y
+ attribute \src "libresoc.v:50937.19-50937.114"
+ wire $lt$libresoc.v:50937$2125_Y
+ attribute \src "libresoc.v:50939.19-50939.114"
+ wire $lt$libresoc.v:50939$2127_Y
+ attribute \src "libresoc.v:50942.19-50942.114"
+ wire $lt$libresoc.v:50942$2130_Y
+ attribute \src "libresoc.v:50944.19-50944.114"
+ wire $lt$libresoc.v:50944$2132_Y
+ attribute \src "libresoc.v:50947.19-50947.114"
+ wire $lt$libresoc.v:50947$2135_Y
+ attribute \src "libresoc.v:50949.19-50949.114"
+ wire $lt$libresoc.v:50949$2137_Y
+ attribute \src "libresoc.v:50951.19-50951.114"
+ wire $lt$libresoc.v:50951$2139_Y
+ attribute \src "libresoc.v:50953.19-50953.114"
+ wire $lt$libresoc.v:50953$2141_Y
+ attribute \src "libresoc.v:50955.19-50955.114"
+ wire $lt$libresoc.v:50955$2143_Y
+ attribute \src "libresoc.v:50958.19-50958.114"
+ wire $lt$libresoc.v:50958$2146_Y
+ attribute \src "libresoc.v:50992.18-50992.110"
+ wire $lt$libresoc.v:50992$2180_Y
+ attribute \src "libresoc.v:50994.18-50994.110"
+ wire $lt$libresoc.v:50994$2182_Y
+ attribute \src "libresoc.v:50996.18-50996.111"
+ wire $lt$libresoc.v:50996$2184_Y
+ attribute \src "libresoc.v:50998.18-50998.111"
+ wire $lt$libresoc.v:50998$2186_Y
+ attribute \src "libresoc.v:51001.18-51001.111"
+ wire $lt$libresoc.v:51001$2189_Y
+ attribute \src "libresoc.v:51003.18-51003.111"
+ wire $lt$libresoc.v:51003$2191_Y
+ attribute \src "libresoc.v:50990.18-50990.40"
+ wire width 16 $shr$libresoc.v:50990$2178_Y
+ attribute \src "libresoc.v:50902.17-50902.114"
+ wire width 8 $ternary$libresoc.v:50902$2090_Y
+ attribute \src "libresoc.v:50924.18-50924.116"
+ wire width 8 $ternary$libresoc.v:50924$2112_Y
+ attribute \src "libresoc.v:50946.18-50946.116"
+ wire width 8 $ternary$libresoc.v:50946$2134_Y
+ attribute \src "libresoc.v:50961.19-50961.118"
+ wire width 8 $ternary$libresoc.v:50961$2149_Y
+ attribute \src "libresoc.v:50963.18-50963.116"
+ wire width 8 $ternary$libresoc.v:50963$2151_Y
+ attribute \src "libresoc.v:50965.18-50965.116"
+ wire width 8 $ternary$libresoc.v:50965$2153_Y
+ attribute \src "libresoc.v:50967.18-50967.116"
+ wire width 8 $ternary$libresoc.v:50967$2155_Y
+ attribute \src "libresoc.v:50969.18-50969.116"
+ wire width 8 $ternary$libresoc.v:50969$2157_Y
+ attribute \src "libresoc.v:50971.18-50971.116"
+ wire width 8 $ternary$libresoc.v:50971$2159_Y
+ attribute \src "libresoc.v:50974.18-50974.116"
+ wire width 8 $ternary$libresoc.v:50974$2162_Y
+ attribute \src "libresoc.v:50976.18-50976.116"
+ wire width 8 $ternary$libresoc.v:50976$2164_Y
+ attribute \src "libresoc.v:50978.18-50978.117"
+ wire width 8 $ternary$libresoc.v:50978$2166_Y
+ attribute \src "libresoc.v:50980.18-50980.117"
+ wire width 8 $ternary$libresoc.v:50980$2168_Y
+ attribute \src "libresoc.v:50982.18-50982.117"
+ wire width 8 $ternary$libresoc.v:50982$2170_Y
+ attribute \src "libresoc.v:50985.18-50985.117"
+ wire width 8 $ternary$libresoc.v:50985$2173_Y
+ attribute \src "libresoc.v:50987.18-50987.117"
+ wire width 8 $ternary$libresoc.v:50987$2175_Y
+ attribute \src "libresoc.v:50989.18-50989.117"
+ wire width 8 $ternary$libresoc.v:50989$2177_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
wire width 32 \be_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308"
wire width 32 \be_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151"
- wire input 2 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
wire width 4 \cur_idx0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
wire input 7 \ics_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
wire input 11 \ics_wb__we
- attribute \src "libresoc.v:49824.7-49824.15"
+ attribute \src "libresoc.v:50503.7-50503.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
wire width 16 input 5 \int_level_i
wire width 16 \int_level_l
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263"
wire width 16 \int_level_l$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153"
+ wire input 2 \intclk_clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153"
+ wire input 3 \intclk_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:358"
wire width 4 \max_idx
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:359"
wire \reg_is_debug
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286"
wire \reg_is_xive
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151"
- wire input 3 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260"
wire \wb_valid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
wire width 8 \xive9_pri$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50225$2052
+ cell $and $and$libresoc.v:50904$2092
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [3]
connect \B \$99
- connect \Y $and$libresoc.v:50225$2052_Y
+ connect \Y $and$libresoc.v:50904$2092_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50227$2054
+ cell $and $and$libresoc.v:50906$2094
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [3]
connect \B \$103
- connect \Y $and$libresoc.v:50227$2054_Y
+ connect \Y $and$libresoc.v:50906$2094_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50229$2056
+ cell $and $and$libresoc.v:50908$2096
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [4]
connect \B \$107
- connect \Y $and$libresoc.v:50229$2056_Y
+ connect \Y $and$libresoc.v:50908$2096_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50231$2058
+ cell $and $and$libresoc.v:50910$2098
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [4]
connect \B \$111
- connect \Y $and$libresoc.v:50231$2058_Y
+ connect \Y $and$libresoc.v:50910$2098_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50233$2060
+ cell $and $and$libresoc.v:50912$2100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [5]
connect \B \$115
- connect \Y $and$libresoc.v:50233$2060_Y
+ connect \Y $and$libresoc.v:50912$2100_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50235$2062
+ cell $and $and$libresoc.v:50914$2102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [5]
connect \B \$119
- connect \Y $and$libresoc.v:50235$2062_Y
+ connect \Y $and$libresoc.v:50914$2102_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50237$2064
+ cell $and $and$libresoc.v:50916$2104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [6]
connect \B \$123
- connect \Y $and$libresoc.v:50237$2064_Y
+ connect \Y $and$libresoc.v:50916$2104_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50240$2067
+ cell $and $and$libresoc.v:50919$2107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [6]
connect \B \$127
- connect \Y $and$libresoc.v:50240$2067_Y
+ connect \Y $and$libresoc.v:50919$2107_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50242$2069
+ cell $and $and$libresoc.v:50921$2109
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [7]
connect \B \$131
- connect \Y $and$libresoc.v:50242$2069_Y
+ connect \Y $and$libresoc.v:50921$2109_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50244$2071
+ cell $and $and$libresoc.v:50923$2111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [7]
connect \B \$135
- connect \Y $and$libresoc.v:50244$2071_Y
+ connect \Y $and$libresoc.v:50923$2111_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50247$2074
+ cell $and $and$libresoc.v:50926$2114
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [8]
connect \B \$139
- connect \Y $and$libresoc.v:50247$2074_Y
+ connect \Y $and$libresoc.v:50926$2114_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50249$2076
+ cell $and $and$libresoc.v:50928$2116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [8]
connect \B \$143
- connect \Y $and$libresoc.v:50249$2076_Y
+ connect \Y $and$libresoc.v:50928$2116_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50251$2078
+ cell $and $and$libresoc.v:50930$2118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [9]
connect \B \$147
- connect \Y $and$libresoc.v:50251$2078_Y
+ connect \Y $and$libresoc.v:50930$2118_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50253$2080
+ cell $and $and$libresoc.v:50932$2120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [9]
connect \B \$151
- connect \Y $and$libresoc.v:50253$2080_Y
+ connect \Y $and$libresoc.v:50932$2120_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50255$2082
+ cell $and $and$libresoc.v:50934$2122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [10]
connect \B \$155
- connect \Y $and$libresoc.v:50255$2082_Y
+ connect \Y $and$libresoc.v:50934$2122_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50257$2084
+ cell $and $and$libresoc.v:50936$2124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [10]
connect \B \$159
- connect \Y $and$libresoc.v:50257$2084_Y
+ connect \Y $and$libresoc.v:50936$2124_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50259$2086
+ cell $and $and$libresoc.v:50938$2126
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [11]
connect \B \$163
- connect \Y $and$libresoc.v:50259$2086_Y
+ connect \Y $and$libresoc.v:50938$2126_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50262$2089
+ cell $and $and$libresoc.v:50941$2129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [11]
connect \B \$167
- connect \Y $and$libresoc.v:50262$2089_Y
+ connect \Y $and$libresoc.v:50941$2129_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50264$2091
+ cell $and $and$libresoc.v:50943$2131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [12]
connect \B \$171
- connect \Y $and$libresoc.v:50264$2091_Y
+ connect \Y $and$libresoc.v:50943$2131_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50266$2093
+ cell $and $and$libresoc.v:50945$2133
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [12]
connect \B \$175
- connect \Y $and$libresoc.v:50266$2093_Y
+ connect \Y $and$libresoc.v:50945$2133_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50269$2096
+ cell $and $and$libresoc.v:50948$2136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [13]
connect \B \$179
- connect \Y $and$libresoc.v:50269$2096_Y
+ connect \Y $and$libresoc.v:50948$2136_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50271$2098
+ cell $and $and$libresoc.v:50950$2138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [13]
connect \B \$183
- connect \Y $and$libresoc.v:50271$2098_Y
+ connect \Y $and$libresoc.v:50950$2138_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50273$2100
+ cell $and $and$libresoc.v:50952$2140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [14]
connect \B \$187
- connect \Y $and$libresoc.v:50273$2100_Y
+ connect \Y $and$libresoc.v:50952$2140_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50275$2102
+ cell $and $and$libresoc.v:50954$2142
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [14]
connect \B \$191
- connect \Y $and$libresoc.v:50275$2102_Y
+ connect \Y $and$libresoc.v:50954$2142_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50277$2104
+ cell $and $and$libresoc.v:50956$2144
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [15]
connect \B \$195
- connect \Y $and$libresoc.v:50277$2104_Y
+ connect \Y $and$libresoc.v:50956$2144_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50280$2107
+ cell $and $and$libresoc.v:50959$2147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [15]
connect \B \$199
- connect \Y $and$libresoc.v:50280$2107_Y
+ connect \Y $and$libresoc.v:50959$2147_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304"
- cell $and $and$libresoc.v:50304$2131
+ cell $and $and$libresoc.v:50983$2171
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__cyc
connect \B \ics_wb__stb
- connect \Y $and$libresoc.v:50304$2131_Y
+ connect \Y $and$libresoc.v:50983$2171_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341"
- cell $and $and$libresoc.v:50312$2139
+ cell $and $and$libresoc.v:50991$2179
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_valid
connect \B \ics_wb__we
- connect \Y $and$libresoc.v:50312$2139_Y
+ connect \Y $and$libresoc.v:50991$2179_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50314$2141
+ cell $and $and$libresoc.v:50993$2181
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [0]
connect \B \$75
- connect \Y $and$libresoc.v:50314$2141_Y
+ connect \Y $and$libresoc.v:50993$2181_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50316$2143
+ cell $and $and$libresoc.v:50995$2183
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [0]
connect \B \$79
- connect \Y $and$libresoc.v:50316$2143_Y
+ connect \Y $and$libresoc.v:50995$2183_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50318$2145
+ cell $and $and$libresoc.v:50997$2185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [1]
connect \B \$83
- connect \Y $and$libresoc.v:50318$2145_Y
+ connect \Y $and$libresoc.v:50997$2185_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50321$2148
+ cell $and $and$libresoc.v:51000$2188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [1]
connect \B \$87
- connect \Y $and$libresoc.v:50321$2148_Y
+ connect \Y $and$libresoc.v:51000$2188_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50323$2150
+ cell $and $and$libresoc.v:51002$2190
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [2]
connect \B \$91
- connect \Y $and$libresoc.v:50323$2150_Y
+ connect \Y $and$libresoc.v:51002$2190_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:50325$2152
+ cell $and $and$libresoc.v:51004$2192
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [2]
connect \B \$95
- connect \Y $and$libresoc.v:50325$2152_Y
+ connect \Y $and$libresoc.v:51004$2192_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50239$2066
+ cell $eq $eq$libresoc.v:50918$2106
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50239$2066_Y
+ connect \Y $eq$libresoc.v:50918$2106_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50261$2088
+ cell $eq $eq$libresoc.v:50940$2128
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50261$2088_Y
+ connect \Y $eq$libresoc.v:50940$2128_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
- cell $eq $eq$libresoc.v:50278$2105
+ cell $eq $eq$libresoc.v:50957$2145
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__adr [9:0]
connect \B 1'0
- connect \Y $eq$libresoc.v:50278$2105_Y
+ connect \Y $eq$libresoc.v:50957$2145_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50281$2108
+ cell $eq $eq$libresoc.v:50960$2148
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_pri15
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50281$2108_Y
+ connect \Y $eq$libresoc.v:50960$2148_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50283$2110
+ cell $eq $eq$libresoc.v:50962$2150
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50283$2110_Y
+ connect \Y $eq$libresoc.v:50962$2150_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50285$2112
+ cell $eq $eq$libresoc.v:50964$2152
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50285$2112_Y
+ connect \Y $eq$libresoc.v:50964$2152_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50287$2114
+ cell $eq $eq$libresoc.v:50966$2154
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50287$2114_Y
+ connect \Y $eq$libresoc.v:50966$2154_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50289$2116
+ cell $eq $eq$libresoc.v:50968$2156
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50289$2116_Y
+ connect \Y $eq$libresoc.v:50968$2156_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50291$2118
+ cell $eq $eq$libresoc.v:50970$2158
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50291$2118_Y
+ connect \Y $eq$libresoc.v:50970$2158_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294"
- cell $eq $eq$libresoc.v:50293$2120
+ cell $eq $eq$libresoc.v:50972$2160
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__adr [9:0]
connect \B 3'100
- connect \Y $eq$libresoc.v:50293$2120_Y
+ connect \Y $eq$libresoc.v:50972$2160_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50294$2121
+ cell $eq $eq$libresoc.v:50973$2161
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50294$2121_Y
+ connect \Y $eq$libresoc.v:50973$2161_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50296$2123
+ cell $eq $eq$libresoc.v:50975$2163
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50296$2123_Y
+ connect \Y $eq$libresoc.v:50975$2163_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50298$2125
+ cell $eq $eq$libresoc.v:50977$2165
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50298$2125_Y
+ connect \Y $eq$libresoc.v:50977$2165_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50300$2127
+ cell $eq $eq$libresoc.v:50979$2167
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50300$2127_Y
+ connect \Y $eq$libresoc.v:50979$2167_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50302$2129
+ cell $eq $eq$libresoc.v:50981$2169
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50302$2129_Y
+ connect \Y $eq$libresoc.v:50981$2169_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50305$2132
+ cell $eq $eq$libresoc.v:50984$2172
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50305$2132_Y
+ connect \Y $eq$libresoc.v:50984$2172_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50307$2134
+ cell $eq $eq$libresoc.v:50986$2174
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50307$2134_Y
+ connect \Y $eq$libresoc.v:50986$2174_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50309$2136
+ cell $eq $eq$libresoc.v:50988$2176
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50309$2136_Y
+ connect \Y $eq$libresoc.v:50988$2176_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:50320$2147
+ cell $eq $eq$libresoc.v:50999$2187
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:50320$2147_Y
+ connect \Y $eq$libresoc.v:50999$2187_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50224$2051
+ cell $lt $lt$libresoc.v:50903$2091
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B \cur_pri2
- connect \Y $lt$libresoc.v:50224$2051_Y
+ connect \Y $lt$libresoc.v:50903$2091_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50226$2053
+ cell $lt $lt$libresoc.v:50905$2093
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B \cur_pri2
- connect \Y $lt$libresoc.v:50226$2053_Y
+ connect \Y $lt$libresoc.v:50905$2093_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50228$2055
+ cell $lt $lt$libresoc.v:50907$2095
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B \cur_pri3
- connect \Y $lt$libresoc.v:50228$2055_Y
+ connect \Y $lt$libresoc.v:50907$2095_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50230$2057
+ cell $lt $lt$libresoc.v:50909$2097
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B \cur_pri3
- connect \Y $lt$libresoc.v:50230$2057_Y
+ connect \Y $lt$libresoc.v:50909$2097_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50232$2059
+ cell $lt $lt$libresoc.v:50911$2099
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B \cur_pri4
- connect \Y $lt$libresoc.v:50232$2059_Y
+ connect \Y $lt$libresoc.v:50911$2099_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50234$2061
+ cell $lt $lt$libresoc.v:50913$2101
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B \cur_pri4
- connect \Y $lt$libresoc.v:50234$2061_Y
+ connect \Y $lt$libresoc.v:50913$2101_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50236$2063
+ cell $lt $lt$libresoc.v:50915$2103
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B \cur_pri5
- connect \Y $lt$libresoc.v:50236$2063_Y
+ connect \Y $lt$libresoc.v:50915$2103_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50238$2065
+ cell $lt $lt$libresoc.v:50917$2105
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B \cur_pri5
- connect \Y $lt$libresoc.v:50238$2065_Y
+ connect \Y $lt$libresoc.v:50917$2105_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50241$2068
+ cell $lt $lt$libresoc.v:50920$2108
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B \cur_pri6
- connect \Y $lt$libresoc.v:50241$2068_Y
+ connect \Y $lt$libresoc.v:50920$2108_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50243$2070
+ cell $lt $lt$libresoc.v:50922$2110
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B \cur_pri6
- connect \Y $lt$libresoc.v:50243$2070_Y
+ connect \Y $lt$libresoc.v:50922$2110_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50246$2073
+ cell $lt $lt$libresoc.v:50925$2113
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B \cur_pri7
- connect \Y $lt$libresoc.v:50246$2073_Y
+ connect \Y $lt$libresoc.v:50925$2113_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50248$2075
+ cell $lt $lt$libresoc.v:50927$2115
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B \cur_pri7
- connect \Y $lt$libresoc.v:50248$2075_Y
+ connect \Y $lt$libresoc.v:50927$2115_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50250$2077
+ cell $lt $lt$libresoc.v:50929$2117
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B \cur_pri8
- connect \Y $lt$libresoc.v:50250$2077_Y
+ connect \Y $lt$libresoc.v:50929$2117_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50252$2079
+ cell $lt $lt$libresoc.v:50931$2119
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B \cur_pri8
- connect \Y $lt$libresoc.v:50252$2079_Y
+ connect \Y $lt$libresoc.v:50931$2119_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50254$2081
+ cell $lt $lt$libresoc.v:50933$2121
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B \cur_pri9
- connect \Y $lt$libresoc.v:50254$2081_Y
+ connect \Y $lt$libresoc.v:50933$2121_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50256$2083
+ cell $lt $lt$libresoc.v:50935$2123
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B \cur_pri9
- connect \Y $lt$libresoc.v:50256$2083_Y
+ connect \Y $lt$libresoc.v:50935$2123_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50258$2085
+ cell $lt $lt$libresoc.v:50937$2125
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B \cur_pri10
- connect \Y $lt$libresoc.v:50258$2085_Y
+ connect \Y $lt$libresoc.v:50937$2125_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50260$2087
+ cell $lt $lt$libresoc.v:50939$2127
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B \cur_pri10
- connect \Y $lt$libresoc.v:50260$2087_Y
+ connect \Y $lt$libresoc.v:50939$2127_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50263$2090
+ cell $lt $lt$libresoc.v:50942$2130
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B \cur_pri11
- connect \Y $lt$libresoc.v:50263$2090_Y
+ connect \Y $lt$libresoc.v:50942$2130_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50265$2092
+ cell $lt $lt$libresoc.v:50944$2132
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B \cur_pri11
- connect \Y $lt$libresoc.v:50265$2092_Y
+ connect \Y $lt$libresoc.v:50944$2132_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50268$2095
+ cell $lt $lt$libresoc.v:50947$2135
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B \cur_pri12
- connect \Y $lt$libresoc.v:50268$2095_Y
+ connect \Y $lt$libresoc.v:50947$2135_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50270$2097
+ cell $lt $lt$libresoc.v:50949$2137
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B \cur_pri12
- connect \Y $lt$libresoc.v:50270$2097_Y
+ connect \Y $lt$libresoc.v:50949$2137_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50272$2099
+ cell $lt $lt$libresoc.v:50951$2139
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B \cur_pri13
- connect \Y $lt$libresoc.v:50272$2099_Y
+ connect \Y $lt$libresoc.v:50951$2139_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50274$2101
+ cell $lt $lt$libresoc.v:50953$2141
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B \cur_pri13
- connect \Y $lt$libresoc.v:50274$2101_Y
+ connect \Y $lt$libresoc.v:50953$2141_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50276$2103
+ cell $lt $lt$libresoc.v:50955$2143
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B \cur_pri14
- connect \Y $lt$libresoc.v:50276$2103_Y
+ connect \Y $lt$libresoc.v:50955$2143_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50279$2106
+ cell $lt $lt$libresoc.v:50958$2146
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B \cur_pri14
- connect \Y $lt$libresoc.v:50279$2106_Y
+ connect \Y $lt$libresoc.v:50958$2146_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50313$2140
+ cell $lt $lt$libresoc.v:50992$2180
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B \max_pri
- connect \Y $lt$libresoc.v:50313$2140_Y
+ connect \Y $lt$libresoc.v:50992$2180_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50315$2142
+ cell $lt $lt$libresoc.v:50994$2182
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B \max_pri
- connect \Y $lt$libresoc.v:50315$2142_Y
+ connect \Y $lt$libresoc.v:50994$2182_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50317$2144
+ cell $lt $lt$libresoc.v:50996$2184
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B \cur_pri0
- connect \Y $lt$libresoc.v:50317$2144_Y
+ connect \Y $lt$libresoc.v:50996$2184_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50319$2146
+ cell $lt $lt$libresoc.v:50998$2186
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B \cur_pri0
- connect \Y $lt$libresoc.v:50319$2146_Y
+ connect \Y $lt$libresoc.v:50998$2186_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50322$2149
+ cell $lt $lt$libresoc.v:51001$2189
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B \cur_pri1
- connect \Y $lt$libresoc.v:50322$2149_Y
+ connect \Y $lt$libresoc.v:51001$2189_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:50324$2151
+ cell $lt $lt$libresoc.v:51003$2191
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B \cur_pri1
- connect \Y $lt$libresoc.v:50324$2151_Y
+ connect \Y $lt$libresoc.v:51003$2191_Y
end
- attribute \src "libresoc.v:50311.18-50311.40"
- cell $shr $shr$libresoc.v:50311$2138
+ attribute \src "libresoc.v:50990.18-50990.40"
+ cell $shr $shr$libresoc.v:50990$2178
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \int_level_l
connect \B \reg_idx
- connect \Y $shr$libresoc.v:50311$2138_Y
+ connect \Y $shr$libresoc.v:50990$2178_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50223$2050
+ cell $mux $ternary$libresoc.v:50902$2090
parameter \WIDTH 8
connect \A \xive0_pri
connect \B 8'11111111
connect \S \$8
- connect \Y $ternary$libresoc.v:50223$2050_Y
+ connect \Y $ternary$libresoc.v:50902$2090_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50245$2072
+ cell $mux $ternary$libresoc.v:50924$2112
parameter \WIDTH 8
connect \A \xive1_pri
connect \B 8'11111111
connect \S \$12
- connect \Y $ternary$libresoc.v:50245$2072_Y
+ connect \Y $ternary$libresoc.v:50924$2112_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50267$2094
+ cell $mux $ternary$libresoc.v:50946$2134
parameter \WIDTH 8
connect \A \xive2_pri
connect \B 8'11111111
connect \S \$16
- connect \Y $ternary$libresoc.v:50267$2094_Y
+ connect \Y $ternary$libresoc.v:50946$2134_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50282$2109
+ cell $mux $ternary$libresoc.v:50961$2149
parameter \WIDTH 8
connect \A \cur_pri15
connect \B 8'11111111
connect \S \$204
- connect \Y $ternary$libresoc.v:50282$2109_Y
+ connect \Y $ternary$libresoc.v:50961$2149_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50284$2111
+ cell $mux $ternary$libresoc.v:50963$2151
parameter \WIDTH 8
connect \A \xive3_pri
connect \B 8'11111111
connect \S \$20
- connect \Y $ternary$libresoc.v:50284$2111_Y
+ connect \Y $ternary$libresoc.v:50963$2151_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50286$2113
+ cell $mux $ternary$libresoc.v:50965$2153
parameter \WIDTH 8
connect \A \xive4_pri
connect \B 8'11111111
connect \S \$24
- connect \Y $ternary$libresoc.v:50286$2113_Y
+ connect \Y $ternary$libresoc.v:50965$2153_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50288$2115
+ cell $mux $ternary$libresoc.v:50967$2155
parameter \WIDTH 8
connect \A \xive5_pri
connect \B 8'11111111
connect \S \$28
- connect \Y $ternary$libresoc.v:50288$2115_Y
+ connect \Y $ternary$libresoc.v:50967$2155_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50290$2117
+ cell $mux $ternary$libresoc.v:50969$2157
parameter \WIDTH 8
connect \A \xive6_pri
connect \B 8'11111111
connect \S \$32
- connect \Y $ternary$libresoc.v:50290$2117_Y
+ connect \Y $ternary$libresoc.v:50969$2157_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50292$2119
+ cell $mux $ternary$libresoc.v:50971$2159
parameter \WIDTH 8
connect \A \xive7_pri
connect \B 8'11111111
connect \S \$36
- connect \Y $ternary$libresoc.v:50292$2119_Y
+ connect \Y $ternary$libresoc.v:50971$2159_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50295$2122
+ cell $mux $ternary$libresoc.v:50974$2162
parameter \WIDTH 8
connect \A \xive8_pri
connect \B 8'11111111
connect \S \$40
- connect \Y $ternary$libresoc.v:50295$2122_Y
+ connect \Y $ternary$libresoc.v:50974$2162_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50297$2124
+ cell $mux $ternary$libresoc.v:50976$2164
parameter \WIDTH 8
connect \A \xive9_pri
connect \B 8'11111111
connect \S \$44
- connect \Y $ternary$libresoc.v:50297$2124_Y
+ connect \Y $ternary$libresoc.v:50976$2164_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50299$2126
+ cell $mux $ternary$libresoc.v:50978$2166
parameter \WIDTH 8
connect \A \xive10_pri
connect \B 8'11111111
connect \S \$48
- connect \Y $ternary$libresoc.v:50299$2126_Y
+ connect \Y $ternary$libresoc.v:50978$2166_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50301$2128
+ cell $mux $ternary$libresoc.v:50980$2168
parameter \WIDTH 8
connect \A \xive11_pri
connect \B 8'11111111
connect \S \$52
- connect \Y $ternary$libresoc.v:50301$2128_Y
+ connect \Y $ternary$libresoc.v:50980$2168_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50303$2130
+ cell $mux $ternary$libresoc.v:50982$2170
parameter \WIDTH 8
connect \A \xive12_pri
connect \B 8'11111111
connect \S \$56
- connect \Y $ternary$libresoc.v:50303$2130_Y
+ connect \Y $ternary$libresoc.v:50982$2170_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50306$2133
+ cell $mux $ternary$libresoc.v:50985$2173
parameter \WIDTH 8
connect \A \xive13_pri
connect \B 8'11111111
connect \S \$60
- connect \Y $ternary$libresoc.v:50306$2133_Y
+ connect \Y $ternary$libresoc.v:50985$2173_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50308$2135
+ cell $mux $ternary$libresoc.v:50987$2175
parameter \WIDTH 8
connect \A \xive14_pri
connect \B 8'11111111
connect \S \$64
- connect \Y $ternary$libresoc.v:50308$2135_Y
+ connect \Y $ternary$libresoc.v:50987$2175_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:50310$2137
+ cell $mux $ternary$libresoc.v:50989$2177
parameter \WIDTH 8
connect \A \xive15_pri
connect \B 8'11111111
connect \S \$68
- connect \Y $ternary$libresoc.v:50310$2137_Y
+ connect \Y $ternary$libresoc.v:50989$2177_Y
end
- attribute \src "libresoc.v:49824.7-49824.20"
- process $proc$libresoc.v:49824$2298
+ attribute \src "libresoc.v:50503.7-50503.20"
+ process $proc$libresoc.v:50503$2338
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:50105.13-50105.30"
- process $proc$libresoc.v:50105$2299
+ attribute \src "libresoc.v:50782.13-50782.30"
+ process $proc$libresoc.v:50782$2339
assign { } { }
assign $1\icp_o_pri[7:0] 8'00000000
sync always
sync init
update \icp_o_pri $1\icp_o_pri[7:0]
end
- attribute \src "libresoc.v:50110.13-50110.29"
- process $proc$libresoc.v:50110$2300
+ attribute \src "libresoc.v:50787.13-50787.29"
+ process $proc$libresoc.v:50787$2340
assign { } { }
assign $1\icp_o_src[3:0] 4'0000
sync always
sync init
update \icp_o_src $1\icp_o_src[3:0]
end
- attribute \src "libresoc.v:50119.7-50119.25"
- process $proc$libresoc.v:50119$2301
+ attribute \src "libresoc.v:50796.7-50796.25"
+ process $proc$libresoc.v:50796$2341
assign { } { }
assign $1\ics_wb__ack[0:0] 1'0
sync always
sync init
update \ics_wb__ack $1\ics_wb__ack[0:0]
end
- attribute \src "libresoc.v:50128.14-50128.35"
- process $proc$libresoc.v:50128$2302
+ attribute \src "libresoc.v:50805.14-50805.35"
+ process $proc$libresoc.v:50805$2342
assign { } { }
assign $1\ics_wb__dat_r[31:0] 0
sync always
sync init
update \ics_wb__dat_r $1\ics_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:50140.14-50140.36"
- process $proc$libresoc.v:50140$2303
+ attribute \src "libresoc.v:50817.14-50817.36"
+ process $proc$libresoc.v:50817$2343
assign { } { }
assign $1\int_level_l[15:0] 16'0000000000000000
sync always
sync init
update \int_level_l $1\int_level_l[15:0]
end
- attribute \src "libresoc.v:50160.13-50160.30"
- process $proc$libresoc.v:50160$2304
+ attribute \src "libresoc.v:50839.13-50839.30"
+ process $proc$libresoc.v:50839$2344
assign { } { }
assign $1\xive0_pri[7:0] 8'11111111
sync always
sync init
update \xive0_pri $1\xive0_pri[7:0]
end
- attribute \src "libresoc.v:50164.13-50164.31"
- process $proc$libresoc.v:50164$2305
+ attribute \src "libresoc.v:50843.13-50843.31"
+ process $proc$libresoc.v:50843$2345
assign { } { }
assign $1\xive10_pri[7:0] 8'11111111
sync always
sync init
update \xive10_pri $1\xive10_pri[7:0]
end
- attribute \src "libresoc.v:50168.13-50168.31"
- process $proc$libresoc.v:50168$2306
+ attribute \src "libresoc.v:50847.13-50847.31"
+ process $proc$libresoc.v:50847$2346
assign { } { }
assign $1\xive11_pri[7:0] 8'11111111
sync always
sync init
update \xive11_pri $1\xive11_pri[7:0]
end
- attribute \src "libresoc.v:50172.13-50172.31"
- process $proc$libresoc.v:50172$2307
+ attribute \src "libresoc.v:50851.13-50851.31"
+ process $proc$libresoc.v:50851$2347
assign { } { }
assign $1\xive12_pri[7:0] 8'11111111
sync always
sync init
update \xive12_pri $1\xive12_pri[7:0]
end
- attribute \src "libresoc.v:50176.13-50176.31"
- process $proc$libresoc.v:50176$2308
+ attribute \src "libresoc.v:50855.13-50855.31"
+ process $proc$libresoc.v:50855$2348
assign { } { }
assign $1\xive13_pri[7:0] 8'11111111
sync always
sync init
update \xive13_pri $1\xive13_pri[7:0]
end
- attribute \src "libresoc.v:50180.13-50180.31"
- process $proc$libresoc.v:50180$2309
+ attribute \src "libresoc.v:50859.13-50859.31"
+ process $proc$libresoc.v:50859$2349
assign { } { }
assign $1\xive14_pri[7:0] 8'11111111
sync always
sync init
update \xive14_pri $1\xive14_pri[7:0]
end
- attribute \src "libresoc.v:50184.13-50184.31"
- process $proc$libresoc.v:50184$2310
+ attribute \src "libresoc.v:50863.13-50863.31"
+ process $proc$libresoc.v:50863$2350
assign { } { }
assign $1\xive15_pri[7:0] 8'11111111
sync always
sync init
update \xive15_pri $1\xive15_pri[7:0]
end
- attribute \src "libresoc.v:50188.13-50188.30"
- process $proc$libresoc.v:50188$2311
+ attribute \src "libresoc.v:50867.13-50867.30"
+ process $proc$libresoc.v:50867$2351
assign { } { }
assign $1\xive1_pri[7:0] 8'11111111
sync always
sync init
update \xive1_pri $1\xive1_pri[7:0]
end
- attribute \src "libresoc.v:50192.13-50192.30"
- process $proc$libresoc.v:50192$2312
+ attribute \src "libresoc.v:50871.13-50871.30"
+ process $proc$libresoc.v:50871$2352
assign { } { }
assign $1\xive2_pri[7:0] 8'11111111
sync always
sync init
update \xive2_pri $1\xive2_pri[7:0]
end
- attribute \src "libresoc.v:50196.13-50196.30"
- process $proc$libresoc.v:50196$2313
+ attribute \src "libresoc.v:50875.13-50875.30"
+ process $proc$libresoc.v:50875$2353
assign { } { }
assign $1\xive3_pri[7:0] 8'11111111
sync always
sync init
update \xive3_pri $1\xive3_pri[7:0]
end
- attribute \src "libresoc.v:50200.13-50200.30"
- process $proc$libresoc.v:50200$2314
+ attribute \src "libresoc.v:50879.13-50879.30"
+ process $proc$libresoc.v:50879$2354
assign { } { }
assign $1\xive4_pri[7:0] 8'11111111
sync always
sync init
update \xive4_pri $1\xive4_pri[7:0]
end
- attribute \src "libresoc.v:50204.13-50204.30"
- process $proc$libresoc.v:50204$2315
+ attribute \src "libresoc.v:50883.13-50883.30"
+ process $proc$libresoc.v:50883$2355
assign { } { }
assign $1\xive5_pri[7:0] 8'11111111
sync always
sync init
update \xive5_pri $1\xive5_pri[7:0]
end
- attribute \src "libresoc.v:50208.13-50208.30"
- process $proc$libresoc.v:50208$2316
+ attribute \src "libresoc.v:50887.13-50887.30"
+ process $proc$libresoc.v:50887$2356
assign { } { }
assign $1\xive6_pri[7:0] 8'11111111
sync always
sync init
update \xive6_pri $1\xive6_pri[7:0]
end
- attribute \src "libresoc.v:50212.13-50212.30"
- process $proc$libresoc.v:50212$2317
+ attribute \src "libresoc.v:50891.13-50891.30"
+ process $proc$libresoc.v:50891$2357
assign { } { }
assign $1\xive7_pri[7:0] 8'11111111
sync always
sync init
update \xive7_pri $1\xive7_pri[7:0]
end
- attribute \src "libresoc.v:50216.13-50216.30"
- process $proc$libresoc.v:50216$2318
+ attribute \src "libresoc.v:50895.13-50895.30"
+ process $proc$libresoc.v:50895$2358
assign { } { }
assign $1\xive8_pri[7:0] 8'11111111
sync always
sync init
update \xive8_pri $1\xive8_pri[7:0]
end
- attribute \src "libresoc.v:50220.13-50220.30"
- process $proc$libresoc.v:50220$2319
+ attribute \src "libresoc.v:50899.13-50899.30"
+ process $proc$libresoc.v:50899$2359
assign { } { }
assign $1\xive9_pri[7:0] 8'11111111
sync always
sync init
update \xive9_pri $1\xive9_pri[7:0]
end
- attribute \src "libresoc.v:50326.3-50327.28"
- process $proc$libresoc.v:50326$2153
+ attribute \src "libresoc.v:51005.3-51006.37"
+ process $proc$libresoc.v:51005$2193
+ assign { } { }
+ assign $0\xive14_pri[7:0] \xive14_pri$next
+ sync posedge \intclk_clk
+ update \xive14_pri $0\xive14_pri[7:0]
+ end
+ attribute \src "libresoc.v:51007.3-51008.37"
+ process $proc$libresoc.v:51007$2194
+ assign { } { }
+ assign $0\xive15_pri[7:0] \xive15_pri$next
+ sync posedge \intclk_clk
+ update \xive15_pri $0\xive15_pri[7:0]
+ end
+ attribute \src "libresoc.v:51009.3-51010.39"
+ process $proc$libresoc.v:51009$2195
+ assign { } { }
+ assign $0\ics_wb__ack[0:0] \ics_wb__ack$next
+ sync posedge \intclk_clk
+ update \ics_wb__ack $0\ics_wb__ack[0:0]
+ end
+ attribute \src "libresoc.v:51011.3-51012.43"
+ process $proc$libresoc.v:51011$2196
+ assign { } { }
+ assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next
+ sync posedge \intclk_clk
+ update \ics_wb__dat_r $0\ics_wb__dat_r[31:0]
+ end
+ attribute \src "libresoc.v:51013.3-51014.39"
+ process $proc$libresoc.v:51013$2197
+ assign { } { }
+ assign $0\int_level_l[15:0] \int_level_l$next
+ sync posedge \intclk_clk
+ update \int_level_l $0\int_level_l[15:0]
+ end
+ attribute \src "libresoc.v:51015.3-51016.28"
+ process $proc$libresoc.v:51015$2198
assign { } { }
assign $0\icp_o_src[3:0] \cur_idx15
- sync posedge \clk
+ sync posedge \intclk_clk
update \icp_o_src $0\icp_o_src[3:0]
end
- attribute \src "libresoc.v:50328.3-50329.25"
- process $proc$libresoc.v:50328$2154
+ attribute \src "libresoc.v:51017.3-51018.25"
+ process $proc$libresoc.v:51017$2199
assign { } { }
assign $0\icp_o_pri[7:0] \$203
- sync posedge \clk
+ sync posedge \intclk_clk
update \icp_o_pri $0\icp_o_pri[7:0]
end
- attribute \src "libresoc.v:50330.3-50331.35"
- process $proc$libresoc.v:50330$2155
+ attribute \src "libresoc.v:51019.3-51020.35"
+ process $proc$libresoc.v:51019$2200
assign { } { }
assign $0\xive0_pri[7:0] \xive0_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive0_pri $0\xive0_pri[7:0]
end
- attribute \src "libresoc.v:50332.3-50333.35"
- process $proc$libresoc.v:50332$2156
+ attribute \src "libresoc.v:51021.3-51022.35"
+ process $proc$libresoc.v:51021$2201
assign { } { }
assign $0\xive1_pri[7:0] \xive1_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive1_pri $0\xive1_pri[7:0]
end
- attribute \src "libresoc.v:50334.3-50335.35"
- process $proc$libresoc.v:50334$2157
+ attribute \src "libresoc.v:51023.3-51024.35"
+ process $proc$libresoc.v:51023$2202
assign { } { }
assign $0\xive2_pri[7:0] \xive2_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive2_pri $0\xive2_pri[7:0]
end
- attribute \src "libresoc.v:50336.3-50337.35"
- process $proc$libresoc.v:50336$2158
+ attribute \src "libresoc.v:51025.3-51026.35"
+ process $proc$libresoc.v:51025$2203
assign { } { }
assign $0\xive3_pri[7:0] \xive3_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive3_pri $0\xive3_pri[7:0]
end
- attribute \src "libresoc.v:50338.3-50339.35"
- process $proc$libresoc.v:50338$2159
+ attribute \src "libresoc.v:51027.3-51028.35"
+ process $proc$libresoc.v:51027$2204
assign { } { }
assign $0\xive4_pri[7:0] \xive4_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive4_pri $0\xive4_pri[7:0]
end
- attribute \src "libresoc.v:50340.3-50341.35"
- process $proc$libresoc.v:50340$2160
+ attribute \src "libresoc.v:51029.3-51030.35"
+ process $proc$libresoc.v:51029$2205
assign { } { }
assign $0\xive5_pri[7:0] \xive5_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive5_pri $0\xive5_pri[7:0]
end
- attribute \src "libresoc.v:50342.3-50343.35"
- process $proc$libresoc.v:50342$2161
+ attribute \src "libresoc.v:51031.3-51032.35"
+ process $proc$libresoc.v:51031$2206
assign { } { }
assign $0\xive6_pri[7:0] \xive6_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive6_pri $0\xive6_pri[7:0]
end
- attribute \src "libresoc.v:50344.3-50345.35"
- process $proc$libresoc.v:50344$2162
+ attribute \src "libresoc.v:51033.3-51034.35"
+ process $proc$libresoc.v:51033$2207
assign { } { }
assign $0\xive7_pri[7:0] \xive7_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive7_pri $0\xive7_pri[7:0]
end
- attribute \src "libresoc.v:50346.3-50347.35"
- process $proc$libresoc.v:50346$2163
+ attribute \src "libresoc.v:51035.3-51036.35"
+ process $proc$libresoc.v:51035$2208
assign { } { }
assign $0\xive8_pri[7:0] \xive8_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive8_pri $0\xive8_pri[7:0]
end
- attribute \src "libresoc.v:50348.3-50349.35"
- process $proc$libresoc.v:50348$2164
+ attribute \src "libresoc.v:51037.3-51038.35"
+ process $proc$libresoc.v:51037$2209
assign { } { }
assign $0\xive9_pri[7:0] \xive9_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive9_pri $0\xive9_pri[7:0]
end
- attribute \src "libresoc.v:50350.3-50351.37"
- process $proc$libresoc.v:50350$2165
+ attribute \src "libresoc.v:51039.3-51040.37"
+ process $proc$libresoc.v:51039$2210
assign { } { }
assign $0\xive10_pri[7:0] \xive10_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive10_pri $0\xive10_pri[7:0]
end
- attribute \src "libresoc.v:50352.3-50353.37"
- process $proc$libresoc.v:50352$2166
+ attribute \src "libresoc.v:51041.3-51042.37"
+ process $proc$libresoc.v:51041$2211
assign { } { }
assign $0\xive11_pri[7:0] \xive11_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive11_pri $0\xive11_pri[7:0]
end
- attribute \src "libresoc.v:50354.3-50355.37"
- process $proc$libresoc.v:50354$2167
+ attribute \src "libresoc.v:51043.3-51044.37"
+ process $proc$libresoc.v:51043$2212
assign { } { }
assign $0\xive12_pri[7:0] \xive12_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive12_pri $0\xive12_pri[7:0]
end
- attribute \src "libresoc.v:50356.3-50357.37"
- process $proc$libresoc.v:50356$2168
+ attribute \src "libresoc.v:51045.3-51046.37"
+ process $proc$libresoc.v:51045$2213
assign { } { }
assign $0\xive13_pri[7:0] \xive13_pri$next
- sync posedge \clk
+ sync posedge \intclk_clk
update \xive13_pri $0\xive13_pri[7:0]
end
- attribute \src "libresoc.v:50358.3-50359.37"
- process $proc$libresoc.v:50358$2169
- assign { } { }
- assign $0\xive14_pri[7:0] \xive14_pri$next
- sync posedge \clk
- update \xive14_pri $0\xive14_pri[7:0]
- end
- attribute \src "libresoc.v:50360.3-50361.37"
- process $proc$libresoc.v:50360$2170
- assign { } { }
- assign $0\xive15_pri[7:0] \xive15_pri$next
- sync posedge \clk
- update \xive15_pri $0\xive15_pri[7:0]
- end
- attribute \src "libresoc.v:50362.3-50363.39"
- process $proc$libresoc.v:50362$2171
- assign { } { }
- assign $0\ics_wb__ack[0:0] \ics_wb__ack$next
- sync posedge \clk
- update \ics_wb__ack $0\ics_wb__ack[0:0]
- end
- attribute \src "libresoc.v:50364.3-50365.43"
- process $proc$libresoc.v:50364$2172
- assign { } { }
- assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next
- sync posedge \clk
- update \ics_wb__dat_r $0\ics_wb__dat_r[31:0]
- end
- attribute \src "libresoc.v:50366.3-50367.39"
- process $proc$libresoc.v:50366$2173
- assign { } { }
- assign $0\int_level_l[15:0] \int_level_l$next
- sync posedge \clk
- update \int_level_l $0\int_level_l[15:0]
- end
- attribute \src "libresoc.v:50368.3-50453.6"
- process $proc$libresoc.v:50368$2174
+ attribute \src "libresoc.v:51047.3-51132.6"
+ process $proc$libresoc.v:51047$2214
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xive0_pri$next[7:0]$2175 $4\xive0_pri$next[7:0]$2239
- assign $0\xive10_pri$next[7:0]$2176 $4\xive10_pri$next[7:0]$2240
- assign $0\xive11_pri$next[7:0]$2177 $4\xive11_pri$next[7:0]$2241
- assign $0\xive12_pri$next[7:0]$2178 $4\xive12_pri$next[7:0]$2242
- assign $0\xive13_pri$next[7:0]$2179 $4\xive13_pri$next[7:0]$2243
- assign $0\xive14_pri$next[7:0]$2180 $4\xive14_pri$next[7:0]$2244
- assign $0\xive15_pri$next[7:0]$2181 $4\xive15_pri$next[7:0]$2245
- assign $0\xive1_pri$next[7:0]$2182 $4\xive1_pri$next[7:0]$2246
- assign $0\xive2_pri$next[7:0]$2183 $4\xive2_pri$next[7:0]$2247
- assign $0\xive3_pri$next[7:0]$2184 $4\xive3_pri$next[7:0]$2248
- assign $0\xive4_pri$next[7:0]$2185 $4\xive4_pri$next[7:0]$2249
- assign $0\xive5_pri$next[7:0]$2186 $4\xive5_pri$next[7:0]$2250
- assign $0\xive6_pri$next[7:0]$2187 $4\xive6_pri$next[7:0]$2251
- assign $0\xive7_pri$next[7:0]$2188 $4\xive7_pri$next[7:0]$2252
- assign $0\xive8_pri$next[7:0]$2189 $4\xive8_pri$next[7:0]$2253
- assign $0\xive9_pri$next[7:0]$2190 $4\xive9_pri$next[7:0]$2254
- attribute \src "libresoc.v:50369.5-50369.29"
+ assign $0\xive0_pri$next[7:0]$2215 $4\xive0_pri$next[7:0]$2279
+ assign $0\xive10_pri$next[7:0]$2216 $4\xive10_pri$next[7:0]$2280
+ assign $0\xive11_pri$next[7:0]$2217 $4\xive11_pri$next[7:0]$2281
+ assign $0\xive12_pri$next[7:0]$2218 $4\xive12_pri$next[7:0]$2282
+ assign $0\xive13_pri$next[7:0]$2219 $4\xive13_pri$next[7:0]$2283
+ assign $0\xive14_pri$next[7:0]$2220 $4\xive14_pri$next[7:0]$2284
+ assign $0\xive15_pri$next[7:0]$2221 $4\xive15_pri$next[7:0]$2285
+ assign $0\xive1_pri$next[7:0]$2222 $4\xive1_pri$next[7:0]$2286
+ assign $0\xive2_pri$next[7:0]$2223 $4\xive2_pri$next[7:0]$2287
+ assign $0\xive3_pri$next[7:0]$2224 $4\xive3_pri$next[7:0]$2288
+ assign $0\xive4_pri$next[7:0]$2225 $4\xive4_pri$next[7:0]$2289
+ assign $0\xive5_pri$next[7:0]$2226 $4\xive5_pri$next[7:0]$2290
+ assign $0\xive6_pri$next[7:0]$2227 $4\xive6_pri$next[7:0]$2291
+ assign $0\xive7_pri$next[7:0]$2228 $4\xive7_pri$next[7:0]$2292
+ assign $0\xive8_pri$next[7:0]$2229 $4\xive8_pri$next[7:0]$2293
+ assign $0\xive9_pri$next[7:0]$2230 $4\xive9_pri$next[7:0]$2294
+ attribute \src "libresoc.v:51048.5-51048.29"
switch \initial
- attribute \src "libresoc.v:50369.9-50369.17"
+ attribute \src "libresoc.v:51048.9-51048.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\xive0_pri$next[7:0]$2191 $2\xive0_pri$next[7:0]$2207
- assign $1\xive10_pri$next[7:0]$2192 $2\xive10_pri$next[7:0]$2208
- assign $1\xive11_pri$next[7:0]$2193 $2\xive11_pri$next[7:0]$2209
- assign $1\xive12_pri$next[7:0]$2194 $2\xive12_pri$next[7:0]$2210
- assign $1\xive13_pri$next[7:0]$2195 $2\xive13_pri$next[7:0]$2211
- assign $1\xive14_pri$next[7:0]$2196 $2\xive14_pri$next[7:0]$2212
- assign $1\xive15_pri$next[7:0]$2197 $2\xive15_pri$next[7:0]$2213
- assign $1\xive1_pri$next[7:0]$2198 $2\xive1_pri$next[7:0]$2214
- assign $1\xive2_pri$next[7:0]$2199 $2\xive2_pri$next[7:0]$2215
- assign $1\xive3_pri$next[7:0]$2200 $2\xive3_pri$next[7:0]$2216
- assign $1\xive4_pri$next[7:0]$2201 $2\xive4_pri$next[7:0]$2217
- assign $1\xive5_pri$next[7:0]$2202 $2\xive5_pri$next[7:0]$2218
- assign $1\xive6_pri$next[7:0]$2203 $2\xive6_pri$next[7:0]$2219
- assign $1\xive7_pri$next[7:0]$2204 $2\xive7_pri$next[7:0]$2220
- assign $1\xive8_pri$next[7:0]$2205 $2\xive8_pri$next[7:0]$2221
- assign $1\xive9_pri$next[7:0]$2206 $2\xive9_pri$next[7:0]$2222
+ assign $1\xive0_pri$next[7:0]$2231 $2\xive0_pri$next[7:0]$2247
+ assign $1\xive10_pri$next[7:0]$2232 $2\xive10_pri$next[7:0]$2248
+ assign $1\xive11_pri$next[7:0]$2233 $2\xive11_pri$next[7:0]$2249
+ assign $1\xive12_pri$next[7:0]$2234 $2\xive12_pri$next[7:0]$2250
+ assign $1\xive13_pri$next[7:0]$2235 $2\xive13_pri$next[7:0]$2251
+ assign $1\xive14_pri$next[7:0]$2236 $2\xive14_pri$next[7:0]$2252
+ assign $1\xive15_pri$next[7:0]$2237 $2\xive15_pri$next[7:0]$2253
+ assign $1\xive1_pri$next[7:0]$2238 $2\xive1_pri$next[7:0]$2254
+ assign $1\xive2_pri$next[7:0]$2239 $2\xive2_pri$next[7:0]$2255
+ assign $1\xive3_pri$next[7:0]$2240 $2\xive3_pri$next[7:0]$2256
+ assign $1\xive4_pri$next[7:0]$2241 $2\xive4_pri$next[7:0]$2257
+ assign $1\xive5_pri$next[7:0]$2242 $2\xive5_pri$next[7:0]$2258
+ assign $1\xive6_pri$next[7:0]$2243 $2\xive6_pri$next[7:0]$2259
+ assign $1\xive7_pri$next[7:0]$2244 $2\xive7_pri$next[7:0]$2260
+ assign $1\xive8_pri$next[7:0]$2245 $2\xive8_pri$next[7:0]$2261
+ assign $1\xive9_pri$next[7:0]$2246 $2\xive9_pri$next[7:0]$2262
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342"
switch \reg_is_xive
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign $2\xive0_pri$next[7:0]$2207 $3\xive0_pri$next[7:0]$2223
- assign $2\xive10_pri$next[7:0]$2208 $3\xive10_pri$next[7:0]$2224
- assign $2\xive11_pri$next[7:0]$2209 $3\xive11_pri$next[7:0]$2225
- assign $2\xive12_pri$next[7:0]$2210 $3\xive12_pri$next[7:0]$2226
- assign $2\xive13_pri$next[7:0]$2211 $3\xive13_pri$next[7:0]$2227
- assign $2\xive14_pri$next[7:0]$2212 $3\xive14_pri$next[7:0]$2228
- assign $2\xive15_pri$next[7:0]$2213 $3\xive15_pri$next[7:0]$2229
- assign $2\xive1_pri$next[7:0]$2214 $3\xive1_pri$next[7:0]$2230
- assign $2\xive2_pri$next[7:0]$2215 $3\xive2_pri$next[7:0]$2231
- assign $2\xive3_pri$next[7:0]$2216 $3\xive3_pri$next[7:0]$2232
- assign $2\xive4_pri$next[7:0]$2217 $3\xive4_pri$next[7:0]$2233
- assign $2\xive5_pri$next[7:0]$2218 $3\xive5_pri$next[7:0]$2234
- assign $2\xive6_pri$next[7:0]$2219 $3\xive6_pri$next[7:0]$2235
- assign $2\xive7_pri$next[7:0]$2220 $3\xive7_pri$next[7:0]$2236
- assign $2\xive8_pri$next[7:0]$2221 $3\xive8_pri$next[7:0]$2237
- assign $2\xive9_pri$next[7:0]$2222 $3\xive9_pri$next[7:0]$2238
+ assign $2\xive0_pri$next[7:0]$2247 $3\xive0_pri$next[7:0]$2263
+ assign $2\xive10_pri$next[7:0]$2248 $3\xive10_pri$next[7:0]$2264
+ assign $2\xive11_pri$next[7:0]$2249 $3\xive11_pri$next[7:0]$2265
+ assign $2\xive12_pri$next[7:0]$2250 $3\xive12_pri$next[7:0]$2266
+ assign $2\xive13_pri$next[7:0]$2251 $3\xive13_pri$next[7:0]$2267
+ assign $2\xive14_pri$next[7:0]$2252 $3\xive14_pri$next[7:0]$2268
+ assign $2\xive15_pri$next[7:0]$2253 $3\xive15_pri$next[7:0]$2269
+ assign $2\xive1_pri$next[7:0]$2254 $3\xive1_pri$next[7:0]$2270
+ assign $2\xive2_pri$next[7:0]$2255 $3\xive2_pri$next[7:0]$2271
+ assign $2\xive3_pri$next[7:0]$2256 $3\xive3_pri$next[7:0]$2272
+ assign $2\xive4_pri$next[7:0]$2257 $3\xive4_pri$next[7:0]$2273
+ assign $2\xive5_pri$next[7:0]$2258 $3\xive5_pri$next[7:0]$2274
+ assign $2\xive6_pri$next[7:0]$2259 $3\xive6_pri$next[7:0]$2275
+ assign $2\xive7_pri$next[7:0]$2260 $3\xive7_pri$next[7:0]$2276
+ assign $2\xive8_pri$next[7:0]$2261 $3\xive8_pri$next[7:0]$2277
+ assign $2\xive9_pri$next[7:0]$2262 $3\xive9_pri$next[7:0]$2278
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345"
switch \reg_idx
attribute \src "libresoc.v:0.0-0.0"
case 4'0000
assign { } { }
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive0_pri$next[7:0]$2223 \be_in [7:0]
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive0_pri$next[7:0]$2263 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0001
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
assign { } { }
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive1_pri$next[7:0]$2230 \be_in [7:0]
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive1_pri$next[7:0]$2270 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
assign { } { }
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive2_pri$next[7:0]$2231 \be_in [7:0]
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive2_pri$next[7:0]$2271 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0011
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
assign { } { }
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive3_pri$next[7:0]$2232 \be_in [7:0]
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive3_pri$next[7:0]$2272 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0100
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
assign { } { }
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive4_pri$next[7:0]$2233 \be_in [7:0]
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive4_pri$next[7:0]$2273 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0101
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
assign { } { }
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive5_pri$next[7:0]$2234 \be_in [7:0]
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive5_pri$next[7:0]$2274 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0110
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
assign { } { }
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive6_pri$next[7:0]$2235 \be_in [7:0]
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive6_pri$next[7:0]$2275 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0111
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
assign { } { }
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive7_pri$next[7:0]$2236 \be_in [7:0]
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive7_pri$next[7:0]$2276 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1000
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
assign { } { }
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive8_pri$next[7:0]$2237 \be_in [7:0]
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive8_pri$next[7:0]$2277 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1001
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
assign { } { }
- assign $3\xive9_pri$next[7:0]$2238 \be_in [7:0]
+ assign $3\xive9_pri$next[7:0]$2278 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1010
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
assign { } { }
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive10_pri$next[7:0]$2224 \be_in [7:0]
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive10_pri$next[7:0]$2264 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1011
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
assign { } { }
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive11_pri$next[7:0]$2225 \be_in [7:0]
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive11_pri$next[7:0]$2265 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1100
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
assign { } { }
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive12_pri$next[7:0]$2226 \be_in [7:0]
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive12_pri$next[7:0]$2266 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1101
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
assign { } { }
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive13_pri$next[7:0]$2227 \be_in [7:0]
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive13_pri$next[7:0]$2267 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1110
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
assign { } { }
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive14_pri$next[7:0]$2228 \be_in [7:0]
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive14_pri$next[7:0]$2268 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'----
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
assign { } { }
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
- assign $3\xive15_pri$next[7:0]$2229 \be_in [7:0]
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
+ assign $3\xive15_pri$next[7:0]$2269 \be_in [7:0]
case
- assign $3\xive0_pri$next[7:0]$2223 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2224 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2225 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2226 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2227 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2228 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2229 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2230 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2231 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2232 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2233 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2234 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2235 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2236 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2237 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2238 \xive9_pri
+ assign $3\xive0_pri$next[7:0]$2263 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2264 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2265 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2266 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2267 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2268 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2269 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2270 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2271 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2272 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2273 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2274 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2275 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2276 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2277 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2278 \xive9_pri
end
case
- assign $2\xive0_pri$next[7:0]$2207 \xive0_pri
- assign $2\xive10_pri$next[7:0]$2208 \xive10_pri
- assign $2\xive11_pri$next[7:0]$2209 \xive11_pri
- assign $2\xive12_pri$next[7:0]$2210 \xive12_pri
- assign $2\xive13_pri$next[7:0]$2211 \xive13_pri
- assign $2\xive14_pri$next[7:0]$2212 \xive14_pri
- assign $2\xive15_pri$next[7:0]$2213 \xive15_pri
- assign $2\xive1_pri$next[7:0]$2214 \xive1_pri
- assign $2\xive2_pri$next[7:0]$2215 \xive2_pri
- assign $2\xive3_pri$next[7:0]$2216 \xive3_pri
- assign $2\xive4_pri$next[7:0]$2217 \xive4_pri
- assign $2\xive5_pri$next[7:0]$2218 \xive5_pri
- assign $2\xive6_pri$next[7:0]$2219 \xive6_pri
- assign $2\xive7_pri$next[7:0]$2220 \xive7_pri
- assign $2\xive8_pri$next[7:0]$2221 \xive8_pri
- assign $2\xive9_pri$next[7:0]$2222 \xive9_pri
+ assign $2\xive0_pri$next[7:0]$2247 \xive0_pri
+ assign $2\xive10_pri$next[7:0]$2248 \xive10_pri
+ assign $2\xive11_pri$next[7:0]$2249 \xive11_pri
+ assign $2\xive12_pri$next[7:0]$2250 \xive12_pri
+ assign $2\xive13_pri$next[7:0]$2251 \xive13_pri
+ assign $2\xive14_pri$next[7:0]$2252 \xive14_pri
+ assign $2\xive15_pri$next[7:0]$2253 \xive15_pri
+ assign $2\xive1_pri$next[7:0]$2254 \xive1_pri
+ assign $2\xive2_pri$next[7:0]$2255 \xive2_pri
+ assign $2\xive3_pri$next[7:0]$2256 \xive3_pri
+ assign $2\xive4_pri$next[7:0]$2257 \xive4_pri
+ assign $2\xive5_pri$next[7:0]$2258 \xive5_pri
+ assign $2\xive6_pri$next[7:0]$2259 \xive6_pri
+ assign $2\xive7_pri$next[7:0]$2260 \xive7_pri
+ assign $2\xive8_pri$next[7:0]$2261 \xive8_pri
+ assign $2\xive9_pri$next[7:0]$2262 \xive9_pri
end
case
- assign $1\xive0_pri$next[7:0]$2191 \xive0_pri
- assign $1\xive10_pri$next[7:0]$2192 \xive10_pri
- assign $1\xive11_pri$next[7:0]$2193 \xive11_pri
- assign $1\xive12_pri$next[7:0]$2194 \xive12_pri
- assign $1\xive13_pri$next[7:0]$2195 \xive13_pri
- assign $1\xive14_pri$next[7:0]$2196 \xive14_pri
- assign $1\xive15_pri$next[7:0]$2197 \xive15_pri
- assign $1\xive1_pri$next[7:0]$2198 \xive1_pri
- assign $1\xive2_pri$next[7:0]$2199 \xive2_pri
- assign $1\xive3_pri$next[7:0]$2200 \xive3_pri
- assign $1\xive4_pri$next[7:0]$2201 \xive4_pri
- assign $1\xive5_pri$next[7:0]$2202 \xive5_pri
- assign $1\xive6_pri$next[7:0]$2203 \xive6_pri
- assign $1\xive7_pri$next[7:0]$2204 \xive7_pri
- assign $1\xive8_pri$next[7:0]$2205 \xive8_pri
- assign $1\xive9_pri$next[7:0]$2206 \xive9_pri
+ assign $1\xive0_pri$next[7:0]$2231 \xive0_pri
+ assign $1\xive10_pri$next[7:0]$2232 \xive10_pri
+ assign $1\xive11_pri$next[7:0]$2233 \xive11_pri
+ assign $1\xive12_pri$next[7:0]$2234 \xive12_pri
+ assign $1\xive13_pri$next[7:0]$2235 \xive13_pri
+ assign $1\xive14_pri$next[7:0]$2236 \xive14_pri
+ assign $1\xive15_pri$next[7:0]$2237 \xive15_pri
+ assign $1\xive1_pri$next[7:0]$2238 \xive1_pri
+ assign $1\xive2_pri$next[7:0]$2239 \xive2_pri
+ assign $1\xive3_pri$next[7:0]$2240 \xive3_pri
+ assign $1\xive4_pri$next[7:0]$2241 \xive4_pri
+ assign $1\xive5_pri$next[7:0]$2242 \xive5_pri
+ assign $1\xive6_pri$next[7:0]$2243 \xive6_pri
+ assign $1\xive7_pri$next[7:0]$2244 \xive7_pri
+ assign $1\xive8_pri$next[7:0]$2245 \xive8_pri
+ assign $1\xive9_pri$next[7:0]$2246 \xive9_pri
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $4\xive0_pri$next[7:0]$2239 8'11111111
- assign $4\xive1_pri$next[7:0]$2246 8'11111111
- assign $4\xive2_pri$next[7:0]$2247 8'11111111
- assign $4\xive3_pri$next[7:0]$2248 8'11111111
- assign $4\xive4_pri$next[7:0]$2249 8'11111111
- assign $4\xive5_pri$next[7:0]$2250 8'11111111
- assign $4\xive6_pri$next[7:0]$2251 8'11111111
- assign $4\xive7_pri$next[7:0]$2252 8'11111111
- assign $4\xive8_pri$next[7:0]$2253 8'11111111
- assign $4\xive9_pri$next[7:0]$2254 8'11111111
- assign $4\xive10_pri$next[7:0]$2240 8'11111111
- assign $4\xive11_pri$next[7:0]$2241 8'11111111
- assign $4\xive12_pri$next[7:0]$2242 8'11111111
- assign $4\xive13_pri$next[7:0]$2243 8'11111111
- assign $4\xive14_pri$next[7:0]$2244 8'11111111
- assign $4\xive15_pri$next[7:0]$2245 8'11111111
+ assign $4\xive0_pri$next[7:0]$2279 8'11111111
+ assign $4\xive1_pri$next[7:0]$2286 8'11111111
+ assign $4\xive2_pri$next[7:0]$2287 8'11111111
+ assign $4\xive3_pri$next[7:0]$2288 8'11111111
+ assign $4\xive4_pri$next[7:0]$2289 8'11111111
+ assign $4\xive5_pri$next[7:0]$2290 8'11111111
+ assign $4\xive6_pri$next[7:0]$2291 8'11111111
+ assign $4\xive7_pri$next[7:0]$2292 8'11111111
+ assign $4\xive8_pri$next[7:0]$2293 8'11111111
+ assign $4\xive9_pri$next[7:0]$2294 8'11111111
+ assign $4\xive10_pri$next[7:0]$2280 8'11111111
+ assign $4\xive11_pri$next[7:0]$2281 8'11111111
+ assign $4\xive12_pri$next[7:0]$2282 8'11111111
+ assign $4\xive13_pri$next[7:0]$2283 8'11111111
+ assign $4\xive14_pri$next[7:0]$2284 8'11111111
+ assign $4\xive15_pri$next[7:0]$2285 8'11111111
case
- assign $4\xive0_pri$next[7:0]$2239 $1\xive0_pri$next[7:0]$2191
- assign $4\xive10_pri$next[7:0]$2240 $1\xive10_pri$next[7:0]$2192
- assign $4\xive11_pri$next[7:0]$2241 $1\xive11_pri$next[7:0]$2193
- assign $4\xive12_pri$next[7:0]$2242 $1\xive12_pri$next[7:0]$2194
- assign $4\xive13_pri$next[7:0]$2243 $1\xive13_pri$next[7:0]$2195
- assign $4\xive14_pri$next[7:0]$2244 $1\xive14_pri$next[7:0]$2196
- assign $4\xive15_pri$next[7:0]$2245 $1\xive15_pri$next[7:0]$2197
- assign $4\xive1_pri$next[7:0]$2246 $1\xive1_pri$next[7:0]$2198
- assign $4\xive2_pri$next[7:0]$2247 $1\xive2_pri$next[7:0]$2199
- assign $4\xive3_pri$next[7:0]$2248 $1\xive3_pri$next[7:0]$2200
- assign $4\xive4_pri$next[7:0]$2249 $1\xive4_pri$next[7:0]$2201
- assign $4\xive5_pri$next[7:0]$2250 $1\xive5_pri$next[7:0]$2202
- assign $4\xive6_pri$next[7:0]$2251 $1\xive6_pri$next[7:0]$2203
- assign $4\xive7_pri$next[7:0]$2252 $1\xive7_pri$next[7:0]$2204
- assign $4\xive8_pri$next[7:0]$2253 $1\xive8_pri$next[7:0]$2205
- assign $4\xive9_pri$next[7:0]$2254 $1\xive9_pri$next[7:0]$2206
+ assign $4\xive0_pri$next[7:0]$2279 $1\xive0_pri$next[7:0]$2231
+ assign $4\xive10_pri$next[7:0]$2280 $1\xive10_pri$next[7:0]$2232
+ assign $4\xive11_pri$next[7:0]$2281 $1\xive11_pri$next[7:0]$2233
+ assign $4\xive12_pri$next[7:0]$2282 $1\xive12_pri$next[7:0]$2234
+ assign $4\xive13_pri$next[7:0]$2283 $1\xive13_pri$next[7:0]$2235
+ assign $4\xive14_pri$next[7:0]$2284 $1\xive14_pri$next[7:0]$2236
+ assign $4\xive15_pri$next[7:0]$2285 $1\xive15_pri$next[7:0]$2237
+ assign $4\xive1_pri$next[7:0]$2286 $1\xive1_pri$next[7:0]$2238
+ assign $4\xive2_pri$next[7:0]$2287 $1\xive2_pri$next[7:0]$2239
+ assign $4\xive3_pri$next[7:0]$2288 $1\xive3_pri$next[7:0]$2240
+ assign $4\xive4_pri$next[7:0]$2289 $1\xive4_pri$next[7:0]$2241
+ assign $4\xive5_pri$next[7:0]$2290 $1\xive5_pri$next[7:0]$2242
+ assign $4\xive6_pri$next[7:0]$2291 $1\xive6_pri$next[7:0]$2243
+ assign $4\xive7_pri$next[7:0]$2292 $1\xive7_pri$next[7:0]$2244
+ assign $4\xive8_pri$next[7:0]$2293 $1\xive8_pri$next[7:0]$2245
+ assign $4\xive9_pri$next[7:0]$2294 $1\xive9_pri$next[7:0]$2246
end
sync always
- update \xive0_pri$next $0\xive0_pri$next[7:0]$2175
- update \xive10_pri$next $0\xive10_pri$next[7:0]$2176
- update \xive11_pri$next $0\xive11_pri$next[7:0]$2177
- update \xive12_pri$next $0\xive12_pri$next[7:0]$2178
- update \xive13_pri$next $0\xive13_pri$next[7:0]$2179
- update \xive14_pri$next $0\xive14_pri$next[7:0]$2180
- update \xive15_pri$next $0\xive15_pri$next[7:0]$2181
- update \xive1_pri$next $0\xive1_pri$next[7:0]$2182
- update \xive2_pri$next $0\xive2_pri$next[7:0]$2183
- update \xive3_pri$next $0\xive3_pri$next[7:0]$2184
- update \xive4_pri$next $0\xive4_pri$next[7:0]$2185
- update \xive5_pri$next $0\xive5_pri$next[7:0]$2186
- update \xive6_pri$next $0\xive6_pri$next[7:0]$2187
- update \xive7_pri$next $0\xive7_pri$next[7:0]$2188
- update \xive8_pri$next $0\xive8_pri$next[7:0]$2189
- update \xive9_pri$next $0\xive9_pri$next[7:0]$2190
+ update \xive0_pri$next $0\xive0_pri$next[7:0]$2215
+ update \xive10_pri$next $0\xive10_pri$next[7:0]$2216
+ update \xive11_pri$next $0\xive11_pri$next[7:0]$2217
+ update \xive12_pri$next $0\xive12_pri$next[7:0]$2218
+ update \xive13_pri$next $0\xive13_pri$next[7:0]$2219
+ update \xive14_pri$next $0\xive14_pri$next[7:0]$2220
+ update \xive15_pri$next $0\xive15_pri$next[7:0]$2221
+ update \xive1_pri$next $0\xive1_pri$next[7:0]$2222
+ update \xive2_pri$next $0\xive2_pri$next[7:0]$2223
+ update \xive3_pri$next $0\xive3_pri$next[7:0]$2224
+ update \xive4_pri$next $0\xive4_pri$next[7:0]$2225
+ update \xive5_pri$next $0\xive5_pri$next[7:0]$2226
+ update \xive6_pri$next $0\xive6_pri$next[7:0]$2227
+ update \xive7_pri$next $0\xive7_pri$next[7:0]$2228
+ update \xive8_pri$next $0\xive8_pri$next[7:0]$2229
+ update \xive9_pri$next $0\xive9_pri$next[7:0]$2230
end
- attribute \src "libresoc.v:50454.3-50463.6"
- process $proc$libresoc.v:50454$2255
+ attribute \src "libresoc.v:51133.3-51142.6"
+ process $proc$libresoc.v:51133$2295
assign { } { }
assign { } { }
assign $0\cur_pri0[7:0] $1\cur_pri0[7:0]
- attribute \src "libresoc.v:50455.5-50455.29"
+ attribute \src "libresoc.v:51134.5-51134.29"
switch \initial
- attribute \src "libresoc.v:50455.9-50455.17"
+ attribute \src "libresoc.v:51134.9-51134.17"
case 1'1
case
end
sync always
update \cur_pri0 $0\cur_pri0[7:0]
end
- attribute \src "libresoc.v:50464.3-50473.6"
- process $proc$libresoc.v:50464$2256
+ attribute \src "libresoc.v:51143.3-51152.6"
+ process $proc$libresoc.v:51143$2296
assign { } { }
assign { } { }
assign $0\cur_idx0[3:0] $1\cur_idx0[3:0]
- attribute \src "libresoc.v:50465.5-50465.29"
+ attribute \src "libresoc.v:51144.5-51144.29"
switch \initial
- attribute \src "libresoc.v:50465.9-50465.17"
+ attribute \src "libresoc.v:51144.9-51144.17"
case 1'1
case
end
sync always
update \cur_idx0 $0\cur_idx0[3:0]
end
- attribute \src "libresoc.v:50474.3-50483.6"
- process $proc$libresoc.v:50474$2257
+ attribute \src "libresoc.v:51153.3-51162.6"
+ process $proc$libresoc.v:51153$2297
assign { } { }
assign { } { }
assign $0\cur_pri1[7:0] $1\cur_pri1[7:0]
- attribute \src "libresoc.v:50475.5-50475.29"
+ attribute \src "libresoc.v:51154.5-51154.29"
switch \initial
- attribute \src "libresoc.v:50475.9-50475.17"
+ attribute \src "libresoc.v:51154.9-51154.17"
case 1'1
case
end
sync always
update \cur_pri1 $0\cur_pri1[7:0]
end
- attribute \src "libresoc.v:50484.3-50493.6"
- process $proc$libresoc.v:50484$2258
+ attribute \src "libresoc.v:51163.3-51172.6"
+ process $proc$libresoc.v:51163$2298
assign { } { }
assign { } { }
assign $0\cur_idx1[3:0] $1\cur_idx1[3:0]
- attribute \src "libresoc.v:50485.5-50485.29"
+ attribute \src "libresoc.v:51164.5-51164.29"
switch \initial
- attribute \src "libresoc.v:50485.9-50485.17"
+ attribute \src "libresoc.v:51164.9-51164.17"
case 1'1
case
end
sync always
update \cur_idx1 $0\cur_idx1[3:0]
end
- attribute \src "libresoc.v:50494.3-50503.6"
- process $proc$libresoc.v:50494$2259
+ attribute \src "libresoc.v:51173.3-51182.6"
+ process $proc$libresoc.v:51173$2299
assign { } { }
assign { } { }
assign $0\cur_pri2[7:0] $1\cur_pri2[7:0]
- attribute \src "libresoc.v:50495.5-50495.29"
+ attribute \src "libresoc.v:51174.5-51174.29"
switch \initial
- attribute \src "libresoc.v:50495.9-50495.17"
+ attribute \src "libresoc.v:51174.9-51174.17"
case 1'1
case
end
sync always
update \cur_pri2 $0\cur_pri2[7:0]
end
- attribute \src "libresoc.v:50504.3-50513.6"
- process $proc$libresoc.v:50504$2260
+ attribute \src "libresoc.v:51183.3-51192.6"
+ process $proc$libresoc.v:51183$2300
assign { } { }
assign { } { }
assign $0\cur_idx2[3:0] $1\cur_idx2[3:0]
- attribute \src "libresoc.v:50505.5-50505.29"
+ attribute \src "libresoc.v:51184.5-51184.29"
switch \initial
- attribute \src "libresoc.v:50505.9-50505.17"
+ attribute \src "libresoc.v:51184.9-51184.17"
case 1'1
case
end
sync always
update \cur_idx2 $0\cur_idx2[3:0]
end
- attribute \src "libresoc.v:50514.3-50523.6"
- process $proc$libresoc.v:50514$2261
+ attribute \src "libresoc.v:51193.3-51202.6"
+ process $proc$libresoc.v:51193$2301
assign { } { }
assign { } { }
assign $0\cur_pri3[7:0] $1\cur_pri3[7:0]
- attribute \src "libresoc.v:50515.5-50515.29"
+ attribute \src "libresoc.v:51194.5-51194.29"
switch \initial
- attribute \src "libresoc.v:50515.9-50515.17"
+ attribute \src "libresoc.v:51194.9-51194.17"
case 1'1
case
end
sync always
update \cur_pri3 $0\cur_pri3[7:0]
end
- attribute \src "libresoc.v:50524.3-50533.6"
- process $proc$libresoc.v:50524$2262
+ attribute \src "libresoc.v:51203.3-51212.6"
+ process $proc$libresoc.v:51203$2302
assign { } { }
assign { } { }
assign $0\cur_idx3[3:0] $1\cur_idx3[3:0]
- attribute \src "libresoc.v:50525.5-50525.29"
+ attribute \src "libresoc.v:51204.5-51204.29"
switch \initial
- attribute \src "libresoc.v:50525.9-50525.17"
+ attribute \src "libresoc.v:51204.9-51204.17"
case 1'1
case
end
sync always
update \cur_idx3 $0\cur_idx3[3:0]
end
- attribute \src "libresoc.v:50534.3-50543.6"
- process $proc$libresoc.v:50534$2263
+ attribute \src "libresoc.v:51213.3-51222.6"
+ process $proc$libresoc.v:51213$2303
assign { } { }
assign { } { }
assign $0\cur_pri4[7:0] $1\cur_pri4[7:0]
- attribute \src "libresoc.v:50535.5-50535.29"
+ attribute \src "libresoc.v:51214.5-51214.29"
switch \initial
- attribute \src "libresoc.v:50535.9-50535.17"
+ attribute \src "libresoc.v:51214.9-51214.17"
case 1'1
case
end
sync always
update \cur_pri4 $0\cur_pri4[7:0]
end
- attribute \src "libresoc.v:50544.3-50552.6"
- process $proc$libresoc.v:50544$2264
+ attribute \src "libresoc.v:51223.3-51231.6"
+ process $proc$libresoc.v:51223$2304
assign { } { }
assign { } { }
- assign $0\int_level_l$next[15:0]$2265 $1\int_level_l$next[15:0]$2266
- attribute \src "libresoc.v:50545.5-50545.29"
+ assign $0\int_level_l$next[15:0]$2305 $1\int_level_l$next[15:0]$2306
+ attribute \src "libresoc.v:51224.5-51224.29"
switch \initial
- attribute \src "libresoc.v:50545.9-50545.17"
+ attribute \src "libresoc.v:51224.9-51224.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\int_level_l$next[15:0]$2266 16'0000000000000000
+ assign $1\int_level_l$next[15:0]$2306 16'0000000000000000
case
- assign $1\int_level_l$next[15:0]$2266 \int_level_i
+ assign $1\int_level_l$next[15:0]$2306 \int_level_i
end
sync always
- update \int_level_l$next $0\int_level_l$next[15:0]$2265
+ update \int_level_l$next $0\int_level_l$next[15:0]$2305
end
- attribute \src "libresoc.v:50553.3-50562.6"
- process $proc$libresoc.v:50553$2267
+ attribute \src "libresoc.v:51232.3-51241.6"
+ process $proc$libresoc.v:51232$2307
assign { } { }
assign { } { }
assign $0\cur_idx4[3:0] $1\cur_idx4[3:0]
- attribute \src "libresoc.v:50554.5-50554.29"
+ attribute \src "libresoc.v:51233.5-51233.29"
switch \initial
- attribute \src "libresoc.v:50554.9-50554.17"
+ attribute \src "libresoc.v:51233.9-51233.17"
case 1'1
case
end
sync always
update \cur_idx4 $0\cur_idx4[3:0]
end
- attribute \src "libresoc.v:50563.3-50572.6"
- process $proc$libresoc.v:50563$2268
+ attribute \src "libresoc.v:51242.3-51251.6"
+ process $proc$libresoc.v:51242$2308
assign { } { }
assign { } { }
assign $0\cur_pri5[7:0] $1\cur_pri5[7:0]
- attribute \src "libresoc.v:50564.5-50564.29"
+ attribute \src "libresoc.v:51243.5-51243.29"
switch \initial
- attribute \src "libresoc.v:50564.9-50564.17"
+ attribute \src "libresoc.v:51243.9-51243.17"
case 1'1
case
end
sync always
update \cur_pri5 $0\cur_pri5[7:0]
end
- attribute \src "libresoc.v:50573.3-50582.6"
- process $proc$libresoc.v:50573$2269
+ attribute \src "libresoc.v:51252.3-51261.6"
+ process $proc$libresoc.v:51252$2309
assign { } { }
assign { } { }
assign $0\cur_idx5[3:0] $1\cur_idx5[3:0]
- attribute \src "libresoc.v:50574.5-50574.29"
+ attribute \src "libresoc.v:51253.5-51253.29"
switch \initial
- attribute \src "libresoc.v:50574.9-50574.17"
+ attribute \src "libresoc.v:51253.9-51253.17"
case 1'1
case
end
sync always
update \cur_idx5 $0\cur_idx5[3:0]
end
- attribute \src "libresoc.v:50583.3-50592.6"
- process $proc$libresoc.v:50583$2270
+ attribute \src "libresoc.v:51262.3-51271.6"
+ process $proc$libresoc.v:51262$2310
assign { } { }
assign { } { }
assign $0\cur_pri6[7:0] $1\cur_pri6[7:0]
- attribute \src "libresoc.v:50584.5-50584.29"
+ attribute \src "libresoc.v:51263.5-51263.29"
switch \initial
- attribute \src "libresoc.v:50584.9-50584.17"
+ attribute \src "libresoc.v:51263.9-51263.17"
case 1'1
case
end
sync always
update \cur_pri6 $0\cur_pri6[7:0]
end
- attribute \src "libresoc.v:50593.3-50602.6"
- process $proc$libresoc.v:50593$2271
+ attribute \src "libresoc.v:51272.3-51281.6"
+ process $proc$libresoc.v:51272$2311
assign { } { }
assign { } { }
assign $0\cur_idx6[3:0] $1\cur_idx6[3:0]
- attribute \src "libresoc.v:50594.5-50594.29"
+ attribute \src "libresoc.v:51273.5-51273.29"
switch \initial
- attribute \src "libresoc.v:50594.9-50594.17"
+ attribute \src "libresoc.v:51273.9-51273.17"
case 1'1
case
end
sync always
update \cur_idx6 $0\cur_idx6[3:0]
end
- attribute \src "libresoc.v:50603.3-50612.6"
- process $proc$libresoc.v:50603$2272
+ attribute \src "libresoc.v:51282.3-51291.6"
+ process $proc$libresoc.v:51282$2312
assign { } { }
assign { } { }
assign $0\cur_pri7[7:0] $1\cur_pri7[7:0]
- attribute \src "libresoc.v:50604.5-50604.29"
+ attribute \src "libresoc.v:51283.5-51283.29"
switch \initial
- attribute \src "libresoc.v:50604.9-50604.17"
+ attribute \src "libresoc.v:51283.9-51283.17"
case 1'1
case
end
sync always
update \cur_pri7 $0\cur_pri7[7:0]
end
- attribute \src "libresoc.v:50613.3-50622.6"
- process $proc$libresoc.v:50613$2273
+ attribute \src "libresoc.v:51292.3-51301.6"
+ process $proc$libresoc.v:51292$2313
assign { } { }
assign { } { }
assign $0\cur_idx7[3:0] $1\cur_idx7[3:0]
- attribute \src "libresoc.v:50614.5-50614.29"
+ attribute \src "libresoc.v:51293.5-51293.29"
switch \initial
- attribute \src "libresoc.v:50614.9-50614.17"
+ attribute \src "libresoc.v:51293.9-51293.17"
case 1'1
case
end
sync always
update \cur_idx7 $0\cur_idx7[3:0]
end
- attribute \src "libresoc.v:50623.3-50632.6"
- process $proc$libresoc.v:50623$2274
+ attribute \src "libresoc.v:51302.3-51311.6"
+ process $proc$libresoc.v:51302$2314
assign { } { }
assign { } { }
assign $0\cur_pri8[7:0] $1\cur_pri8[7:0]
- attribute \src "libresoc.v:50624.5-50624.29"
+ attribute \src "libresoc.v:51303.5-51303.29"
switch \initial
- attribute \src "libresoc.v:50624.9-50624.17"
+ attribute \src "libresoc.v:51303.9-51303.17"
case 1'1
case
end
sync always
update \cur_pri8 $0\cur_pri8[7:0]
end
- attribute \src "libresoc.v:50633.3-50642.6"
- process $proc$libresoc.v:50633$2275
+ attribute \src "libresoc.v:51312.3-51321.6"
+ process $proc$libresoc.v:51312$2315
assign { } { }
assign { } { }
assign $0\cur_idx8[3:0] $1\cur_idx8[3:0]
- attribute \src "libresoc.v:50634.5-50634.29"
+ attribute \src "libresoc.v:51313.5-51313.29"
switch \initial
- attribute \src "libresoc.v:50634.9-50634.17"
+ attribute \src "libresoc.v:51313.9-51313.17"
case 1'1
case
end
sync always
update \cur_idx8 $0\cur_idx8[3:0]
end
- attribute \src "libresoc.v:50643.3-50652.6"
- process $proc$libresoc.v:50643$2276
+ attribute \src "libresoc.v:51322.3-51331.6"
+ process $proc$libresoc.v:51322$2316
assign { } { }
assign { } { }
assign $0\cur_pri9[7:0] $1\cur_pri9[7:0]
- attribute \src "libresoc.v:50644.5-50644.29"
+ attribute \src "libresoc.v:51323.5-51323.29"
switch \initial
- attribute \src "libresoc.v:50644.9-50644.17"
+ attribute \src "libresoc.v:51323.9-51323.17"
case 1'1
case
end
sync always
update \cur_pri9 $0\cur_pri9[7:0]
end
- attribute \src "libresoc.v:50653.3-50662.6"
- process $proc$libresoc.v:50653$2277
+ attribute \src "libresoc.v:51332.3-51341.6"
+ process $proc$libresoc.v:51332$2317
assign { } { }
assign { } { }
assign $0\cur_idx9[3:0] $1\cur_idx9[3:0]
- attribute \src "libresoc.v:50654.5-50654.29"
+ attribute \src "libresoc.v:51333.5-51333.29"
switch \initial
- attribute \src "libresoc.v:50654.9-50654.17"
+ attribute \src "libresoc.v:51333.9-51333.17"
case 1'1
case
end
sync always
update \cur_idx9 $0\cur_idx9[3:0]
end
- attribute \src "libresoc.v:50663.3-50672.6"
- process $proc$libresoc.v:50663$2278
+ attribute \src "libresoc.v:51342.3-51351.6"
+ process $proc$libresoc.v:51342$2318
assign { } { }
assign { } { }
assign $0\cur_pri10[7:0] $1\cur_pri10[7:0]
- attribute \src "libresoc.v:50664.5-50664.29"
+ attribute \src "libresoc.v:51343.5-51343.29"
switch \initial
- attribute \src "libresoc.v:50664.9-50664.17"
+ attribute \src "libresoc.v:51343.9-51343.17"
case 1'1
case
end
sync always
update \cur_pri10 $0\cur_pri10[7:0]
end
- attribute \src "libresoc.v:50673.3-50682.6"
- process $proc$libresoc.v:50673$2279
+ attribute \src "libresoc.v:51352.3-51361.6"
+ process $proc$libresoc.v:51352$2319
assign { } { }
assign { } { }
assign $0\cur_idx10[3:0] $1\cur_idx10[3:0]
- attribute \src "libresoc.v:50674.5-50674.29"
+ attribute \src "libresoc.v:51353.5-51353.29"
switch \initial
- attribute \src "libresoc.v:50674.9-50674.17"
+ attribute \src "libresoc.v:51353.9-51353.17"
case 1'1
case
end
sync always
update \cur_idx10 $0\cur_idx10[3:0]
end
- attribute \src "libresoc.v:50683.3-50692.6"
- process $proc$libresoc.v:50683$2280
+ attribute \src "libresoc.v:51362.3-51371.6"
+ process $proc$libresoc.v:51362$2320
assign { } { }
assign { } { }
assign $0\cur_pri11[7:0] $1\cur_pri11[7:0]
- attribute \src "libresoc.v:50684.5-50684.29"
+ attribute \src "libresoc.v:51363.5-51363.29"
switch \initial
- attribute \src "libresoc.v:50684.9-50684.17"
+ attribute \src "libresoc.v:51363.9-51363.17"
case 1'1
case
end
sync always
update \cur_pri11 $0\cur_pri11[7:0]
end
- attribute \src "libresoc.v:50693.3-50702.6"
- process $proc$libresoc.v:50693$2281
+ attribute \src "libresoc.v:51372.3-51381.6"
+ process $proc$libresoc.v:51372$2321
assign { } { }
assign { } { }
assign $0\cur_idx11[3:0] $1\cur_idx11[3:0]
- attribute \src "libresoc.v:50694.5-50694.29"
+ attribute \src "libresoc.v:51373.5-51373.29"
switch \initial
- attribute \src "libresoc.v:50694.9-50694.17"
+ attribute \src "libresoc.v:51373.9-51373.17"
case 1'1
case
end
sync always
update \cur_idx11 $0\cur_idx11[3:0]
end
- attribute \src "libresoc.v:50703.3-50712.6"
- process $proc$libresoc.v:50703$2282
+ attribute \src "libresoc.v:51382.3-51391.6"
+ process $proc$libresoc.v:51382$2322
assign { } { }
assign { } { }
assign $0\cur_pri12[7:0] $1\cur_pri12[7:0]
- attribute \src "libresoc.v:50704.5-50704.29"
+ attribute \src "libresoc.v:51383.5-51383.29"
switch \initial
- attribute \src "libresoc.v:50704.9-50704.17"
+ attribute \src "libresoc.v:51383.9-51383.17"
case 1'1
case
end
sync always
update \cur_pri12 $0\cur_pri12[7:0]
end
- attribute \src "libresoc.v:50713.3-50722.6"
- process $proc$libresoc.v:50713$2283
+ attribute \src "libresoc.v:51392.3-51401.6"
+ process $proc$libresoc.v:51392$2323
assign { } { }
assign { } { }
assign $0\cur_idx12[3:0] $1\cur_idx12[3:0]
- attribute \src "libresoc.v:50714.5-50714.29"
+ attribute \src "libresoc.v:51393.5-51393.29"
switch \initial
- attribute \src "libresoc.v:50714.9-50714.17"
+ attribute \src "libresoc.v:51393.9-51393.17"
case 1'1
case
end
sync always
update \cur_idx12 $0\cur_idx12[3:0]
end
- attribute \src "libresoc.v:50723.3-50732.6"
- process $proc$libresoc.v:50723$2284
+ attribute \src "libresoc.v:51402.3-51411.6"
+ process $proc$libresoc.v:51402$2324
assign { } { }
assign { } { }
assign $0\cur_pri13[7:0] $1\cur_pri13[7:0]
- attribute \src "libresoc.v:50724.5-50724.29"
+ attribute \src "libresoc.v:51403.5-51403.29"
switch \initial
- attribute \src "libresoc.v:50724.9-50724.17"
+ attribute \src "libresoc.v:51403.9-51403.17"
case 1'1
case
end
sync always
update \cur_pri13 $0\cur_pri13[7:0]
end
- attribute \src "libresoc.v:50733.3-50742.6"
- process $proc$libresoc.v:50733$2285
+ attribute \src "libresoc.v:51412.3-51421.6"
+ process $proc$libresoc.v:51412$2325
assign { } { }
assign { } { }
assign $0\cur_idx13[3:0] $1\cur_idx13[3:0]
- attribute \src "libresoc.v:50734.5-50734.29"
+ attribute \src "libresoc.v:51413.5-51413.29"
switch \initial
- attribute \src "libresoc.v:50734.9-50734.17"
+ attribute \src "libresoc.v:51413.9-51413.17"
case 1'1
case
end
sync always
update \cur_idx13 $0\cur_idx13[3:0]
end
- attribute \src "libresoc.v:50743.3-50752.6"
- process $proc$libresoc.v:50743$2286
+ attribute \src "libresoc.v:51422.3-51431.6"
+ process $proc$libresoc.v:51422$2326
assign { } { }
assign { } { }
assign $0\cur_pri14[7:0] $1\cur_pri14[7:0]
- attribute \src "libresoc.v:50744.5-50744.29"
+ attribute \src "libresoc.v:51423.5-51423.29"
switch \initial
- attribute \src "libresoc.v:50744.9-50744.17"
+ attribute \src "libresoc.v:51423.9-51423.17"
case 1'1
case
end
sync always
update \cur_pri14 $0\cur_pri14[7:0]
end
- attribute \src "libresoc.v:50753.3-50802.6"
- process $proc$libresoc.v:50753$2287
+ attribute \src "libresoc.v:51432.3-51481.6"
+ process $proc$libresoc.v:51432$2327
assign { } { }
assign { } { }
assign $0\be_out[31:0] $1\be_out[31:0]
- attribute \src "libresoc.v:50754.5-50754.29"
+ attribute \src "libresoc.v:51433.5-51433.29"
switch \initial
- attribute \src "libresoc.v:50754.9-50754.17"
+ attribute \src "libresoc.v:51433.9-51433.17"
case 1'1
case
end
sync always
update \be_out $0\be_out[31:0]
end
- attribute \src "libresoc.v:50803.3-50812.6"
- process $proc$libresoc.v:50803$2288
+ attribute \src "libresoc.v:51482.3-51491.6"
+ process $proc$libresoc.v:51482$2328
assign { } { }
assign { } { }
assign $0\cur_idx14[3:0] $1\cur_idx14[3:0]
- attribute \src "libresoc.v:50804.5-50804.29"
+ attribute \src "libresoc.v:51483.5-51483.29"
switch \initial
- attribute \src "libresoc.v:50804.9-50804.17"
+ attribute \src "libresoc.v:51483.9-51483.17"
case 1'1
case
end
sync always
update \cur_idx14 $0\cur_idx14[3:0]
end
- attribute \src "libresoc.v:50813.3-50822.6"
- process $proc$libresoc.v:50813$2289
+ attribute \src "libresoc.v:51492.3-51501.6"
+ process $proc$libresoc.v:51492$2329
assign { } { }
assign { } { }
assign $0\cur_pri15[7:0] $1\cur_pri15[7:0]
- attribute \src "libresoc.v:50814.5-50814.29"
+ attribute \src "libresoc.v:51493.5-51493.29"
switch \initial
- attribute \src "libresoc.v:50814.9-50814.17"
+ attribute \src "libresoc.v:51493.9-51493.17"
case 1'1
case
end
sync always
update \cur_pri15 $0\cur_pri15[7:0]
end
- attribute \src "libresoc.v:50823.3-50832.6"
- process $proc$libresoc.v:50823$2290
+ attribute \src "libresoc.v:51502.3-51511.6"
+ process $proc$libresoc.v:51502$2330
assign { } { }
assign { } { }
assign $0\cur_idx15[3:0] $1\cur_idx15[3:0]
- attribute \src "libresoc.v:50824.5-50824.29"
+ attribute \src "libresoc.v:51503.5-51503.29"
switch \initial
- attribute \src "libresoc.v:50824.9-50824.17"
+ attribute \src "libresoc.v:51503.9-51503.17"
case 1'1
case
end
sync always
update \cur_idx15 $0\cur_idx15[3:0]
end
- attribute \src "libresoc.v:50833.3-50842.6"
- process $proc$libresoc.v:50833$2291
+ attribute \src "libresoc.v:51512.3-51521.6"
+ process $proc$libresoc.v:51512$2331
assign { } { }
assign { } { }
assign $0\ibit[0:0] $1\ibit[0:0]
- attribute \src "libresoc.v:50834.5-50834.29"
+ attribute \src "libresoc.v:51513.5-51513.29"
switch \initial
- attribute \src "libresoc.v:50834.9-50834.17"
+ attribute \src "libresoc.v:51513.9-51513.17"
case 1'1
case
end
sync always
update \ibit $0\ibit[0:0]
end
- attribute \src "libresoc.v:50843.3-50851.6"
- process $proc$libresoc.v:50843$2292
+ attribute \src "libresoc.v:51522.3-51530.6"
+ process $proc$libresoc.v:51522$2332
assign { } { }
assign { } { }
- assign $0\ics_wb__dat_r$next[31:0]$2293 $1\ics_wb__dat_r$next[31:0]$2294
- attribute \src "libresoc.v:50844.5-50844.29"
+ assign $0\ics_wb__dat_r$next[31:0]$2333 $1\ics_wb__dat_r$next[31:0]$2334
+ attribute \src "libresoc.v:51523.5-51523.29"
switch \initial
- attribute \src "libresoc.v:50844.9-50844.17"
+ attribute \src "libresoc.v:51523.9-51523.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
+ switch \intclk_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ics_wb__dat_r$next[31:0]$2294 0
+ assign $1\ics_wb__dat_r$next[31:0]$2334 0
case
- assign $1\ics_wb__dat_r$next[31:0]$2294 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
+ assign $1\ics_wb__dat_r$next[31:0]$2334 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
end
sync always
- update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$2293
+ update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$2333
end
- attribute \src "libresoc.v:50852.3-50860.6"
- process $proc$libresoc.v:50852$2295
+ attribute \src "libresoc.v:51531.3-51539.6"
+ process $proc$libresoc.v:51531$2335
assign { } { }
assign { } { }
- assign $0\ics_wb__ack$next[0:0]$2296 $1\ics_wb__ack$next[0:0]$2297
- attribute \src "libresoc.v:50853.5-50853.29"
+ assign $0\ics_wb__ack$next[0:0]$2336 $1\ics_wb__ack$next[0:0]$2337
+ attribute \src "libresoc.v:51532.5-51532.29"
switch \initial
- attribute \src "libresoc.v:50853.9-50853.17"
+ attribute \src "libresoc.v:51532.9-51532.17"
case 1'1
case
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
- switch \rst
- attribute \src "libresoc.v:0.0-0.0"
- case 1'1
- assign { } { }
- assign $1\ics_wb__ack$next[0:0]$2297 1'0
- case
- assign $1\ics_wb__ack$next[0:0]$2297 \wb_valid
- end
- sync always
- update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$2296
- end
- connect \$7 $ternary$libresoc.v:50223$2050_Y
- connect \$99 $lt$libresoc.v:50224$2051_Y
- connect \$101 $and$libresoc.v:50225$2052_Y
- connect \$103 $lt$libresoc.v:50226$2053_Y
- connect \$105 $and$libresoc.v:50227$2054_Y
- connect \$107 $lt$libresoc.v:50228$2055_Y
- connect \$109 $and$libresoc.v:50229$2056_Y
- connect \$111 $lt$libresoc.v:50230$2057_Y
- connect \$113 $and$libresoc.v:50231$2058_Y
- connect \$115 $lt$libresoc.v:50232$2059_Y
- connect \$117 $and$libresoc.v:50233$2060_Y
- connect \$119 $lt$libresoc.v:50234$2061_Y
- connect \$121 $and$libresoc.v:50235$2062_Y
- connect \$123 $lt$libresoc.v:50236$2063_Y
- connect \$125 $and$libresoc.v:50237$2064_Y
- connect \$127 $lt$libresoc.v:50238$2065_Y
- connect \$12 $eq$libresoc.v:50239$2066_Y
- connect \$129 $and$libresoc.v:50240$2067_Y
- connect \$131 $lt$libresoc.v:50241$2068_Y
- connect \$133 $and$libresoc.v:50242$2069_Y
- connect \$135 $lt$libresoc.v:50243$2070_Y
- connect \$137 $and$libresoc.v:50244$2071_Y
- connect \$11 $ternary$libresoc.v:50245$2072_Y
- connect \$139 $lt$libresoc.v:50246$2073_Y
- connect \$141 $and$libresoc.v:50247$2074_Y
- connect \$143 $lt$libresoc.v:50248$2075_Y
- connect \$145 $and$libresoc.v:50249$2076_Y
- connect \$147 $lt$libresoc.v:50250$2077_Y
- connect \$149 $and$libresoc.v:50251$2078_Y
- connect \$151 $lt$libresoc.v:50252$2079_Y
- connect \$153 $and$libresoc.v:50253$2080_Y
- connect \$155 $lt$libresoc.v:50254$2081_Y
- connect \$157 $and$libresoc.v:50255$2082_Y
- connect \$159 $lt$libresoc.v:50256$2083_Y
- connect \$161 $and$libresoc.v:50257$2084_Y
- connect \$163 $lt$libresoc.v:50258$2085_Y
- connect \$165 $and$libresoc.v:50259$2086_Y
- connect \$167 $lt$libresoc.v:50260$2087_Y
- connect \$16 $eq$libresoc.v:50261$2088_Y
- connect \$169 $and$libresoc.v:50262$2089_Y
- connect \$171 $lt$libresoc.v:50263$2090_Y
- connect \$173 $and$libresoc.v:50264$2091_Y
- connect \$175 $lt$libresoc.v:50265$2092_Y
- connect \$177 $and$libresoc.v:50266$2093_Y
- connect \$15 $ternary$libresoc.v:50267$2094_Y
- connect \$179 $lt$libresoc.v:50268$2095_Y
- connect \$181 $and$libresoc.v:50269$2096_Y
- connect \$183 $lt$libresoc.v:50270$2097_Y
- connect \$185 $and$libresoc.v:50271$2098_Y
- connect \$187 $lt$libresoc.v:50272$2099_Y
- connect \$189 $and$libresoc.v:50273$2100_Y
- connect \$191 $lt$libresoc.v:50274$2101_Y
- connect \$193 $and$libresoc.v:50275$2102_Y
- connect \$195 $lt$libresoc.v:50276$2103_Y
- connect \$197 $and$libresoc.v:50277$2104_Y
- connect \$1 $eq$libresoc.v:50278$2105_Y
- connect \$199 $lt$libresoc.v:50279$2106_Y
- connect \$201 $and$libresoc.v:50280$2107_Y
- connect \$204 $eq$libresoc.v:50281$2108_Y
- connect \$203 $ternary$libresoc.v:50282$2109_Y
- connect \$20 $eq$libresoc.v:50283$2110_Y
- connect \$19 $ternary$libresoc.v:50284$2111_Y
- connect \$24 $eq$libresoc.v:50285$2112_Y
- connect \$23 $ternary$libresoc.v:50286$2113_Y
- connect \$28 $eq$libresoc.v:50287$2114_Y
- connect \$27 $ternary$libresoc.v:50288$2115_Y
- connect \$32 $eq$libresoc.v:50289$2116_Y
- connect \$31 $ternary$libresoc.v:50290$2117_Y
- connect \$36 $eq$libresoc.v:50291$2118_Y
- connect \$35 $ternary$libresoc.v:50292$2119_Y
- connect \$3 $eq$libresoc.v:50293$2120_Y
- connect \$40 $eq$libresoc.v:50294$2121_Y
- connect \$39 $ternary$libresoc.v:50295$2122_Y
- connect \$44 $eq$libresoc.v:50296$2123_Y
- connect \$43 $ternary$libresoc.v:50297$2124_Y
- connect \$48 $eq$libresoc.v:50298$2125_Y
- connect \$47 $ternary$libresoc.v:50299$2126_Y
- connect \$52 $eq$libresoc.v:50300$2127_Y
- connect \$51 $ternary$libresoc.v:50301$2128_Y
- connect \$56 $eq$libresoc.v:50302$2129_Y
- connect \$55 $ternary$libresoc.v:50303$2130_Y
- connect \$5 $and$libresoc.v:50304$2131_Y
- connect \$60 $eq$libresoc.v:50305$2132_Y
- connect \$59 $ternary$libresoc.v:50306$2133_Y
- connect \$64 $eq$libresoc.v:50307$2134_Y
- connect \$63 $ternary$libresoc.v:50308$2135_Y
- connect \$68 $eq$libresoc.v:50309$2136_Y
- connect \$67 $ternary$libresoc.v:50310$2137_Y
- connect \$71 $shr$libresoc.v:50311$2138_Y [0]
- connect \$73 $and$libresoc.v:50312$2139_Y
- connect \$75 $lt$libresoc.v:50313$2140_Y
- connect \$77 $and$libresoc.v:50314$2141_Y
- connect \$79 $lt$libresoc.v:50315$2142_Y
- connect \$81 $and$libresoc.v:50316$2143_Y
- connect \$83 $lt$libresoc.v:50317$2144_Y
- connect \$85 $and$libresoc.v:50318$2145_Y
- connect \$87 $lt$libresoc.v:50319$2146_Y
- connect \$8 $eq$libresoc.v:50320$2147_Y
- connect \$89 $and$libresoc.v:50321$2148_Y
- connect \$91 $lt$libresoc.v:50322$2149_Y
- connect \$93 $and$libresoc.v:50323$2150_Y
- connect \$95 $lt$libresoc.v:50324$2151_Y
- connect \$97 $and$libresoc.v:50325$2152_Y
+ switch \intclk_rst
+ attribute \src "libresoc.v:0.0-0.0"
+ case 1'1
+ assign { } { }
+ assign $1\ics_wb__ack$next[0:0]$2337 1'0
+ case
+ assign $1\ics_wb__ack$next[0:0]$2337 \wb_valid
+ end
+ sync always
+ update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$2336
+ end
+ connect \$7 $ternary$libresoc.v:50902$2090_Y
+ connect \$99 $lt$libresoc.v:50903$2091_Y
+ connect \$101 $and$libresoc.v:50904$2092_Y
+ connect \$103 $lt$libresoc.v:50905$2093_Y
+ connect \$105 $and$libresoc.v:50906$2094_Y
+ connect \$107 $lt$libresoc.v:50907$2095_Y
+ connect \$109 $and$libresoc.v:50908$2096_Y
+ connect \$111 $lt$libresoc.v:50909$2097_Y
+ connect \$113 $and$libresoc.v:50910$2098_Y
+ connect \$115 $lt$libresoc.v:50911$2099_Y
+ connect \$117 $and$libresoc.v:50912$2100_Y
+ connect \$119 $lt$libresoc.v:50913$2101_Y
+ connect \$121 $and$libresoc.v:50914$2102_Y
+ connect \$123 $lt$libresoc.v:50915$2103_Y
+ connect \$125 $and$libresoc.v:50916$2104_Y
+ connect \$127 $lt$libresoc.v:50917$2105_Y
+ connect \$12 $eq$libresoc.v:50918$2106_Y
+ connect \$129 $and$libresoc.v:50919$2107_Y
+ connect \$131 $lt$libresoc.v:50920$2108_Y
+ connect \$133 $and$libresoc.v:50921$2109_Y
+ connect \$135 $lt$libresoc.v:50922$2110_Y
+ connect \$137 $and$libresoc.v:50923$2111_Y
+ connect \$11 $ternary$libresoc.v:50924$2112_Y
+ connect \$139 $lt$libresoc.v:50925$2113_Y
+ connect \$141 $and$libresoc.v:50926$2114_Y
+ connect \$143 $lt$libresoc.v:50927$2115_Y
+ connect \$145 $and$libresoc.v:50928$2116_Y
+ connect \$147 $lt$libresoc.v:50929$2117_Y
+ connect \$149 $and$libresoc.v:50930$2118_Y
+ connect \$151 $lt$libresoc.v:50931$2119_Y
+ connect \$153 $and$libresoc.v:50932$2120_Y
+ connect \$155 $lt$libresoc.v:50933$2121_Y
+ connect \$157 $and$libresoc.v:50934$2122_Y
+ connect \$159 $lt$libresoc.v:50935$2123_Y
+ connect \$161 $and$libresoc.v:50936$2124_Y
+ connect \$163 $lt$libresoc.v:50937$2125_Y
+ connect \$165 $and$libresoc.v:50938$2126_Y
+ connect \$167 $lt$libresoc.v:50939$2127_Y
+ connect \$16 $eq$libresoc.v:50940$2128_Y
+ connect \$169 $and$libresoc.v:50941$2129_Y
+ connect \$171 $lt$libresoc.v:50942$2130_Y
+ connect \$173 $and$libresoc.v:50943$2131_Y
+ connect \$175 $lt$libresoc.v:50944$2132_Y
+ connect \$177 $and$libresoc.v:50945$2133_Y
+ connect \$15 $ternary$libresoc.v:50946$2134_Y
+ connect \$179 $lt$libresoc.v:50947$2135_Y
+ connect \$181 $and$libresoc.v:50948$2136_Y
+ connect \$183 $lt$libresoc.v:50949$2137_Y
+ connect \$185 $and$libresoc.v:50950$2138_Y
+ connect \$187 $lt$libresoc.v:50951$2139_Y
+ connect \$189 $and$libresoc.v:50952$2140_Y
+ connect \$191 $lt$libresoc.v:50953$2141_Y
+ connect \$193 $and$libresoc.v:50954$2142_Y
+ connect \$195 $lt$libresoc.v:50955$2143_Y
+ connect \$197 $and$libresoc.v:50956$2144_Y
+ connect \$1 $eq$libresoc.v:50957$2145_Y
+ connect \$199 $lt$libresoc.v:50958$2146_Y
+ connect \$201 $and$libresoc.v:50959$2147_Y
+ connect \$204 $eq$libresoc.v:50960$2148_Y
+ connect \$203 $ternary$libresoc.v:50961$2149_Y
+ connect \$20 $eq$libresoc.v:50962$2150_Y
+ connect \$19 $ternary$libresoc.v:50963$2151_Y
+ connect \$24 $eq$libresoc.v:50964$2152_Y
+ connect \$23 $ternary$libresoc.v:50965$2153_Y
+ connect \$28 $eq$libresoc.v:50966$2154_Y
+ connect \$27 $ternary$libresoc.v:50967$2155_Y
+ connect \$32 $eq$libresoc.v:50968$2156_Y
+ connect \$31 $ternary$libresoc.v:50969$2157_Y
+ connect \$36 $eq$libresoc.v:50970$2158_Y
+ connect \$35 $ternary$libresoc.v:50971$2159_Y
+ connect \$3 $eq$libresoc.v:50972$2160_Y
+ connect \$40 $eq$libresoc.v:50973$2161_Y
+ connect \$39 $ternary$libresoc.v:50974$2162_Y
+ connect \$44 $eq$libresoc.v:50975$2163_Y
+ connect \$43 $ternary$libresoc.v:50976$2164_Y
+ connect \$48 $eq$libresoc.v:50977$2165_Y
+ connect \$47 $ternary$libresoc.v:50978$2166_Y
+ connect \$52 $eq$libresoc.v:50979$2167_Y
+ connect \$51 $ternary$libresoc.v:50980$2168_Y
+ connect \$56 $eq$libresoc.v:50981$2169_Y
+ connect \$55 $ternary$libresoc.v:50982$2170_Y
+ connect \$5 $and$libresoc.v:50983$2171_Y
+ connect \$60 $eq$libresoc.v:50984$2172_Y
+ connect \$59 $ternary$libresoc.v:50985$2173_Y
+ connect \$64 $eq$libresoc.v:50986$2174_Y
+ connect \$63 $ternary$libresoc.v:50987$2175_Y
+ connect \$68 $eq$libresoc.v:50988$2176_Y
+ connect \$67 $ternary$libresoc.v:50989$2177_Y
+ connect \$71 $shr$libresoc.v:50990$2178_Y [0]
+ connect \$73 $and$libresoc.v:50991$2179_Y
+ connect \$75 $lt$libresoc.v:50992$2180_Y
+ connect \$77 $and$libresoc.v:50993$2181_Y
+ connect \$79 $lt$libresoc.v:50994$2182_Y
+ connect \$81 $and$libresoc.v:50995$2183_Y
+ connect \$83 $lt$libresoc.v:50996$2184_Y
+ connect \$85 $and$libresoc.v:50997$2185_Y
+ connect \$87 $lt$libresoc.v:50998$2186_Y
+ connect \$8 $eq$libresoc.v:50999$2187_Y
+ connect \$89 $and$libresoc.v:51000$2188_Y
+ connect \$91 $lt$libresoc.v:51001$2189_Y
+ connect \$93 $and$libresoc.v:51002$2190_Y
+ connect \$95 $lt$libresoc.v:51003$2191_Y
+ connect \$97 $and$libresoc.v:51004$2192_Y
connect \icp_r_pri \$203
connect \icp_r_src \cur_idx15
connect \max_idx 4'0000
projects / soclayout.git / commitdiff