remove XER.ca from logical Input Data - not needed

diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py
index 2f399b49e39b37b4bdf6e517e0850e8abe15ef85..b0ea4b327408e584ab5fd49ca0b490375e72972e 100644 (file)
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -28,13 +28,14 @@ class CommonInputStage(PipeModBase):
         ##### carry-in #####
 
         # either copy incoming carry or set to 1/0 as defined by op
-        with m.Switch(self.i.ctx.op.input_carry):
-            with m.Case(CryIn.ZERO):
-                comb += self.o.xer_ca.eq(0b00)
-            with m.Case(CryIn.ONE):
-                comb += self.o.xer_ca.eq(0b11) # XER CA/CA32
-            with m.Case(CryIn.CA):
-                comb += self.o.xer_ca.eq(self.i.xer_ca)
+        if hasattr(self.i, "xer_ca"): # hack (for now - for LogicalInputData)
+            with m.Switch(self.i.ctx.op.input_carry):
+                with m.Case(CryIn.ZERO):
+                    comb += self.o.xer_ca.eq(0b00)
+                with m.Case(CryIn.ONE):
+                    comb += self.o.xer_ca.eq(0b11) # XER CA/CA32
+                with m.Case(CryIn.CA):
+                    comb += self.o.xer_ca.eq(self.i.xer_ca)
 
         ##### sticky overflow and context (both pass-through) #####
 

diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py
index dedf33f6bf16ca84991a38341208f63fd364cc45..c80b6fb390df307b5cd39427fad4de42be49aa87 100644 (file)
--- a/src/soc/fu/logical/formal/proof_input_stage.py
+++ b/src/soc/fu/logical/formal/proof_input_stage.py
@@ -32,7 +32,7 @@ class Driver(Elaboratable):
             recwidth += width
             comb += p.eq(AnyConst(width))
 
-        pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth)
+        pspec = ALUPipeSpec(id_wid=2)
         m.submodules.dut = dut = ALUInputStage(pspec)
 
         a = Signal(64)
@@ -42,10 +42,8 @@ class Driver(Elaboratable):
                  a.eq(AnyConst(64)),
                  b.eq(AnyConst(64))]
                       
-
         comb += dut.i.ctx.op.eq(rec)
 
-
         # Assert that op gets copied from the input to output
         for p in rec.ports():
             name = p.name
@@ -64,11 +62,9 @@ class Driver(Elaboratable):
         with m.Else():
             comb += Assert(dut.o.b == b)
 
-
-
-
         return m
 
+
 class GTCombinerTestCase(FHDLTestCase):
     def test_formal(self):
         module = Driver()

diff --git a/src/soc/fu/logical/formal/proof_main_stage.py b/src/soc/fu/logical/formal/proof_main_stage.py
index d37bec3d5173eea91df03fa5ecf94e71742317e0..708d732d5a8a4369b3e353f1d92ae081d3f3fb40 100644 (file)
--- a/src/soc/fu/logical/formal/proof_main_stage.py
+++ b/src/soc/fu/logical/formal/proof_main_stage.py
@@ -49,14 +49,14 @@ class Driver(Elaboratable):
         # convenience variables
         a = dut.i.a
         b = dut.i.b
-        carry_in = dut.i.xer_ca[0]
-        carry_in32 = dut.i.xer_ca[1]
+        #carry_in = dut.i.xer_ca[0]
+        #carry_in32 = dut.i.xer_ca[1]
         o = dut.o.o.data
 
         # setup random inputs
         comb += [a.eq(AnyConst(64)),
                  b.eq(AnyConst(64)),
-                 carry_in.eq(AnyConst(0b11)),
+                 #carry_in.eq(AnyConst(0b11)),
                  ]
 
         comb += dut.i.ctx.op.eq(rec)

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 7113773337798eb62bc082ddb0acde56deba91da..35d637ae197789e3811fec8b9299b0b4b991cd8b 100644 (file)
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -9,23 +9,21 @@ from soc.fu.logical.logical_input_record import CompLogicalOpSubset
 class LogicalInputData(IntegerData):
     regspec = [('INT', 'a', '0:63'),
                ('INT', 'rb', '0:63'),
-               ('XER', 'xer_ca', '34,45')]
+               ]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.a = Signal(64, reset_less=True) # RA
         self.b = Signal(64, reset_less=True) # RB/immediate
-        self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
 
     def __iter__(self):
         yield from super().__iter__()
         yield self.a
         yield self.b
-        yield self.xer_ca
 
     def eq(self, i):
         lst = super().eq(i)
         return lst + [self.a.eq(i.a), self.b.eq(i.b),
-                      self.xer_ca.eq(i.xer_ca) ]
+                       ]
 
 
 class LogicalOutputData(IntegerData):

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index ac0729e0b6d5f50746cdc085c349bd9eec33fa0f..04778c6381e827dbe95d0a8b19dafacecb550e4b 100644 (file)
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -56,13 +56,6 @@ def set_alu_inputs(alu, dec2, sim):
     yield alu.p.data_i.b.eq(data2)
 
 
-def set_extra_alu_inputs(alu, dec2, sim):
-    carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
-    carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
-    yield alu.p.data_i.xer_ca[0].eq(carry)
-    yield alu.p.data_i.xer_ca[1].eq(carry32)
-
-
 # This test bench is a bit different than is usual. Initially when I
 # was writing it, I had all of the tests call a function to create a
 # device under test and simulator, initialize the dut, run the
@@ -223,7 +216,6 @@ class TestRunner(FHDLTestCase):
                     fn_unit = yield pdecode2.e.fn_unit
                     self.assertEqual(fn_unit, Function.LOGICAL.value, code)
                     yield from set_alu_inputs(alu, pdecode2, simulator)
-                    yield from set_extra_alu_inputs(alu, pdecode2, simulator)
                     yield
                     opname = code.split(' ')[0]
                     yield from simulator.call(opname)