adding in ALU test back in, debugging SPR setup

diff --git a/src/soc/regfile/util.py b/src/soc/regfile/util.py
index dff63be8da15d7f6ebe77f2285e7f1415a0c0e1b..536c16fbfb53a6b2a4bb7269c5ae001dc2745dbf 100644 (file)
--- a/src/soc/regfile/util.py
+++ b/src/soc/regfile/util.py
@@ -1,5 +1,5 @@
 from soc.regfile.regfiles import FastRegs
-from soc.decoder.power_enums import SPR
+from soc.decoder.power_enums import SPR, spr_dict
 
 def fast_reg_to_spr(spr_num):
     if spr_num == FastRegs.CTR:

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index d3599be807b63a99fb5b1054d11dd23d60046865..aa1845e7846546a047b1a4dadf6b6479523e19ec 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -14,7 +14,7 @@ from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_decoder2 import PowerDecode2
 from soc.decoder.selectable_int import SelectableInt
 from soc.decoder.isa.all import ISA
-from soc.decoder.power_enums import Function, XER_bits
+from soc.decoder.power_enums import SPR, Function, XER_bits
 from soc.config.test.test_loadstore import TestMemPspec
 
 from soc.simple.core import NonProductionCore

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 1159a85da2feb8937e820ce1226823109dd273a3..b91c1ddeeac3fa2de870569101180fa61227a221 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -25,7 +25,7 @@ from soc.fu.compunits.test.test_compunit import (setup_test_memory,
                                                  check_sim_memory)
 
 # test with ALU data and Logical data
-#from soc.fu.alu.test.test_pipe_caller import ALUTestCase
+from soc.fu.alu.test.test_pipe_caller import ALUTestCase
 #from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
 #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
 #from soc.fu.cr.test.test_pipe_caller import CRTestCase
@@ -186,7 +186,7 @@ if __name__ == "__main__":
     #suite.addTest(TestRunner(CRTestCase.test_data))
     #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
     #suite.addTest(TestRunner(LogicalTestCase.test_data))
-    #suite.addTest(TestRunner(ALUTestCase.test_data))
+    suite.addTest(TestRunner(ALUTestCase.test_data))
     #suite.addTest(TestRunner(BranchTestCase.test_data))
     suite.addTest(TestRunner(SPRTestCase.test_data))