whoops, messing up on m_width *sigh*

diff --git a/src/add/fmul.py b/src/add/fmul.py
index d5c3a830d8d9e7e4a11f988cede742e8f5f1c545..bb508e1a4733b61427c688d3d9488dee9c5f490c 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -24,7 +24,7 @@ class FPMUL(FPBase):
         b = FPNum(self.width, False)
         z = FPNum(self.width, False)
 
-        mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
+        mw = (z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
         product = Signal(mw)
 
         of = Overflow()
@@ -103,7 +103,7 @@ class FPMUL(FPBase):
 
             #multiply_1
             with m.State("multiply_1"):
-                mw = z.m.m_width
+                mw = z.m_width
                 m.next = "normalise_1"
                 m.d.sync += [
                 z.m.eq(product[mw+3:]),