get fp mul pipe working using new FPNumBaseRecord

diff --git a/src/ieee754/fpmul/mul0.py b/src/ieee754/fpmul/mul0.py
index b488c95c9d5b14e4024e5ee253173ca11d935e4c..6c264fbcc7895733536c6e68d2814b742891339d 100644 (file)
--- a/src/ieee754/fpmul/mul0.py
+++ b/src/ieee754/fpmul/mul0.py
@@ -5,7 +5,7 @@
 from nmigen import Module, Signal, Cat, Elaboratable
 from nmigen.cli import main, verilog
 
-from ieee754.fpcommon.fpbase import FPNumBase
+from ieee754.fpcommon.fpbase import FPNumBaseRecord
 from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.denorm import FPSCData
 
@@ -13,7 +13,7 @@ from ieee754.fpcommon.denorm import FPSCData
 class FPMulStage0Data:
 
     def __init__(self, width, id_wid):
-        self.z = FPNumBase(width, False)
+        self.z = FPNumBaseRecord(width, False)
         self.out_do_z = Signal(reset_less=True)
         self.oz = Signal(width, reset_less=True)
         mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
@@ -50,9 +50,9 @@ class FPMulStage0Mod(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.mul0_in_a = self.i.a
-        m.submodules.mul0_in_b = self.i.b
-        m.submodules.mul0_out_z = self.o.z
+        #m.submodules.mul0_in_a = self.i.a
+        #m.submodules.mul0_in_b = self.i.b
+        #m.submodules.mul0_out_z = self.o.z
 
         # store intermediate tests (and zero-extended mantissas)
         am0 = Signal(len(self.i.a.m)+1, reset_less=True)

diff --git a/src/ieee754/fpmul/mul1.py b/src/ieee754/fpmul/mul1.py
index 9e82626763a91c5e02ba7f290fbe9d6c359b0165..d932871bbeaee3c4cac98c6750cc40824676bb58 100644 (file)
--- a/src/ieee754/fpmul/mul1.py
+++ b/src/ieee754/fpmul/mul1.py
@@ -31,7 +31,7 @@ class FPMulStage1Mod(FPState, Elaboratable):
         """ links module to inputs and outputs
         """
         m.submodules.mul1 = self
-        m.submodules.mul1_out_overflow = self.o.of
+        #m.submodules.mul1_out_overflow = self.o.of
 
         m.d.comb += self.i.eq(i)
 
@@ -60,7 +60,7 @@ class FPMulStage1(FPState):
     def __init__(self, width, id_wid):
         FPState.__init__(self, "multiply_1")
         self.mod = FPMulStage1Mod(width)
-        self.out_z = FPNumBase(width, False)
+        self.out_z = FPNumBaseRecord(width, False)
         self.out_of = Overflow()
         self.norm_stb = Signal()
 

diff --git a/src/ieee754/fpmul/specialcases.py b/src/ieee754/fpmul/specialcases.py
index 83f82558b9e6c8015bd4f83c1b15811d5b0819fe..b7a59b37950a5425497db1a2b5e4d8457265b7ab 100644 (file)
--- a/src/ieee754/fpmul/specialcases.py
+++ b/src/ieee754/fpmul/specialcases.py
@@ -4,7 +4,7 @@ from nmigen import Module, Signal, Cat, Const, Elaboratable
 from nmigen.cli import main, verilog
 from math import log
 
-from ieee754.fpcommon.fpbase import FPNumDecode
+from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 from nmutil.singlepipe import SimpleHandshake, StageChain
 
 from ieee754.fpcommon.fpbase import FPState, FPID
@@ -42,13 +42,13 @@ class FPMulSpecialCasesMod(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        m.submodules.sc_out_z = self.o.z
+        #m.submodules.sc_out_z = self.o.z
 
         # decode: XXX really should move to separate stage
-        a1 = FPNumDecode(None, self.width, False)
-        b1 = FPNumDecode(None, self.width, False)
-        m.submodules.sc_decode_a = a1
-        m.submodules.sc_decode_b = b1
+        a1 = FPNumBaseRecord(self.width, False)
+        b1 = FPNumBaseRecord(self.width, False)
+        m.submodules.sc_decode_a = a1 = FPNumDecode(None, a1)
+        m.submodules.sc_decode_b = b1 = FPNumDecode(None, b1)
         m.d.comb += [a1.v.eq(self.i.a),
                      b1.v.eq(self.i.b),
                      self.o.a.eq(a1),

diff --git a/src/nmutil/concurrentunit.py b/src/nmutil/concurrentunit.py
index 5f02d7cd9ade7e11364c75aab2079bedd1fac57c..3d426ff9a7fe67f8969a9454ddf9cda365c61d97 100644 (file)
--- a/src/nmutil/concurrentunit.py
+++ b/src/nmutil/concurrentunit.py
@@ -9,7 +9,7 @@
 """
 
 from math import log
-from nmigen import Module
+from nmigen import Module, Elaboratable
 from nmigen.cli import main, verilog
 
 from nmutil.singlepipe import PassThroughStage
@@ -35,7 +35,7 @@ class FPADDMuxOutPipe(CombMuxOutPipe):
         CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
 
-class ReservationStations:
+class ReservationStations(Elaboratable):
     """ Reservation-Station pipeline
 
         Input: num_rows - number of input and output Reservation Stations