`endif
endinterface
interface Ifc_slow_peripherals;
- interface AXI4_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
+ interface AXI4_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
interface SP_dedicated_ios slow_ios;
`ifdef CLINT
method Bit#(1) msip_int;
/*=======================================================*/
- AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE)
+ AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `DATA,`USERSPACE)
slow_fabric <- mkAXI4_Lite_Fabric(fn_slow_address_mapping);
Ifc_AXI4Lite_AXI4_Bridge
bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
/* ==== define the number of slow peripheral irqs ==== */
function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
- fn_slow_address_mapping (Bit#(`ADDR) addr);
+ fn_slow_address_mapping (Bit#(`PADDR) addr);
`ifdef CLINT
if(addr>=`ClintBase && addr<=`ClintEnd)
return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
`endif
`ifdef DDR
(*prefix="M_AXI"*) interface
- AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
+ AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
`endif
`ifdef HYPER
(*always_ready,always_enabled*)
// Fabric
AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
- `ADDR, `DATA,`USERSPACE)
+ `PADDR, `DATA,`USERSPACE)
fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
// Connect traffic generators to fabric
def mkfast_peripheral(self):
return "AXI4_Slave_to_FlexBus_Master_Xactor_IFC " + \
- "#(`ADDR, `DATA, `USERSPACE)\n" + \
+ "#(`PADDR, `DATA, `USERSPACE)\n" + \
" fb{0} <- mkAXI4_Slave_to_FlexBus_Master_Xactor;"
def _mk_connection(self, name=None, count=0):
with open(idef, 'w') as bsv_file:
txt = '''\
`define ADDR {0}
-`define PADDR {0}
+`define PADDR 32
`define DATA {1}
`define Reg_width {1}
`define USERSPACE 0