tlb_req_index is TLB_BITS long not TLB_SIZE

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index f66e2210e91a3e1cf00feb70a4cbcf2a748580b7..3a80e430ba4a17481959ba521d3989a885c01179 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -824,7 +824,7 @@ class ICache(FetchUnitInterface, Elaboratable):
         req_is_miss      = Signal()
         req_laddr        = Signal(64)
 
-        tlb_req_index    = Signal(TLB_SIZE)
+        tlb_req_index    = Signal(TLB_BITS)
         real_addr        = Signal(REAL_ADDR_BITS)
         ra_valid         = Signal()
         priv_fault       = Signal()