whitespace cleanup

diff --git a/src/add/test_prioritymux_pipe.py b/src/add/test_prioritymux_pipe.py
index 6b41f1b4d30535864db7e82b2e21e32634549f99..d216736664b2775e24669b56d224588c456d7c12 100644 (file)
--- a/src/add/test_prioritymux_pipe.py
+++ b/src/add/test_prioritymux_pipe.py
@@ -7,7 +7,6 @@ from nmigen.cli import verilog, rtlil
 from multipipe import CombMultiInPipeline, InputPriorityArbiter
 
 
-
 class PriorityUnbufferedPipeline(CombMultiInPipeline):
     def __init__(self, stage, p_len=4):
         p_mux = InputPriorityArbiter(self, p_len)
@@ -17,6 +16,7 @@ class PriorityUnbufferedPipeline(CombMultiInPipeline):
         return self.p_mux.ports()
         #return UnbufferedPipeline.ports(self) + self.p_mux.ports()
 
+
 class PassData:
     def __init__(self):
         self.mid = Signal(2, reset_less=True)