upate dsisr and dar using sync

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index af92d68d7b0befa5fdb701d4eab13c81fdf9dfdf..05d1f899c02849a3caad293ac4ba419d882a88fc 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -359,10 +359,11 @@ class FSMMMUStage(ControlBase):
                     # subset SPR: first check a few bits
                     with m.If(~spr[9] & ~spr[5]):
                         comb += self.debug0.eq(3)
+                        #if matched update local cached value
                         with m.If(spr[0]):
-                            comb += dsisr.eq(a_i[:32])
+                            sync += dsisr.eq(a_i[:32])
                         with m.Else():
-                            comb += dar.eq(a_i)
+                            sync += dar.eq(a_i)
                         comb += done.eq(1)
                     # pass it over to the MMU instead
                     with m.Else():