fix spr state test

diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py
index b3452ca8d6dbda9edc09075f5b5ca86cad7376bb..a824e8ae9b6b3606bcf423d2e11fbfc9f8e0a043 100644 (file)
--- a/src/soc/fu/spr/test/test_pipe_caller.py
+++ b/src/soc/fu/spr/test/test_pipe_caller.py
@@ -200,8 +200,8 @@ class TestRunner(unittest.TestCase):
 
                     # ask the decoder to decode this binary data (endian'd)
                     yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
-                    yield pdecode2.msr.eq(msr)  # set MSR in pdecode2
-                    yield pdecode2.cia.eq(pc)  # set PC in pdecode2
+                    yield pdecode2.state.msr.eq(msr)  # set MSR in pdecode2
+                    yield pdecode2.state.pc.eq(pc)  # set PC in pdecode2
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()