decode fast spr for OP_BCREG CTR, TAR and LR

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index e50d1ca5d35d45e1297a7d24e8ebe06d38b5b95e..76188bf731e6d3b0f3f8c057168313a710b80a89 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -62,8 +62,10 @@ class DecodeA(Elaboratable):
         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
         with m.If((op.internal_op == InternalOp.OP_BC) |
                   (op.internal_op == InternalOp.OP_BCREG)):
+            xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
+            xo5 = self.dec.FormXL.XO[5] # 3.0B p38 
             with m.If(~self.dec.BO[2] |        # 3.0B p38 BO2=0, use CTR reg
-                       self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
+                       (xo9 & ~xo5)):
                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
                 comb += self.fast_out.ok.eq(1)
 
@@ -157,13 +159,18 @@ class DecodeB(Elaboratable):
 
         # decode SPR2 based on instruction type
         op = self.dec.op
-        # BCREG implicitly uses LR or TAR for 2nd reg (TODO: TAR)
+        # BCREG implicitly uses LR or TAR for 2nd reg
         # CTR however is already in fast_spr1 *not* 2.
         with m.If((op.internal_op == InternalOp.OP_BC) |
                  (op.internal_op == InternalOp.OP_BCREG)):
-            with m.If(~self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
+            xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
+            xo5 = self.dec.FormXL.XO[5] # 3.0B p38 
+            with m.If(~xo9):
                 comb += self.fast_out.data.eq(FastRegs.LR)
                 comb += self.fast_out.ok.eq(1)
+            with m.Elif(xo5):
+                comb += self.fast_out.data.eq(FastRegs.TAR)
+                comb += self.fast_out.ok.eq(1)
 
         return m
 

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index aa544c6616e9b71d7044b6dacbee6795a76a4324..c14ed97479701a160421506eebbd816a4e0aa7aa 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -16,7 +16,7 @@ from soc.fu.branch.pipeline import BranchBasePipe
 from soc.fu.branch.pipe_data import BranchPipeSpec
 import random
 
-from soc.compunits.test.test_branch_compunit import fast_reg_to_spr # HACK!
+from soc.regfile.util import fast_reg_to_spr # HACK!
 
 class TestCase:
     def __init__(self, program, regs, sprs, cr, name):

diff --git a/src/soc/fu/compunits/test/test_branch_compunit.py b/src/soc/fu/compunits/test/test_branch_compunit.py
index 312d3348b69787870a068a90bac9750d3a52ec31..0c84d94b0a2a63058a835116480e799a00572ea8 100644 (file)
--- a/src/soc/fu/compunits/test/test_branch_compunit.py
+++ b/src/soc/fu/compunits/test/test_branch_compunit.py
@@ -8,20 +8,12 @@ from soc.fu.branch.test.test_pipe_caller import test_data
 from soc.fu.compunits.compunits import BranchFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
 
-from soc.regfile.regfiles import FastRegs
+from soc.regfile.util import fast_reg_to_spr # HACK!
 
 """
     def assert_outputs(self, branch, dec2, sim, prev_nia, code):
 """
 
-def fast_reg_to_spr(spr_num):
-    if spr_num == FastRegs.CTR:
-        return SPR.CTR.value
-    elif spr_num == FastRegs.LR:
-        return SPR.LR.value
-    elif spr_num == FastRegs.TAR:
-        return SPR.TAR.value
-
 
 class BranchTestRunner(TestRunner):
     def __init__(self, test_data):

diff --git a/src/soc/regfile/util.py b/src/soc/regfile/util.py
new file mode 100644 (file)
index 0000000..f27d711
--- /dev/null
+++ b/src/soc/regfile/util.py
@@ -0,0 +1,10 @@
+from soc.regfile.regfiles import FastRegs
+from soc.decoder.power_enums import SPR
+
+def fast_reg_to_spr(spr_num):
+    if spr_num == FastRegs.CTR:
+        return SPR.CTR.value
+    elif spr_num == FastRegs.LR:
+        return SPR.LR.value
+    elif spr_num == FastRegs.TAR:
+        return SPR.TAR.value