add links for trap main stage
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 24 May 2020 19:01:56 +0000 (20:01 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 24 May 2020 19:01:56 +0000 (20:01 +0100)
src/soc/fu/trap/main_stage.py

index 4efbff00f9eb13dc8f601fcbf79d492107d675a3..2d42c15370644f6645089e79907f36189b629068 100644 (file)
@@ -1,6 +1,8 @@
 """Trap Pipeline
 
 * https://bugs.libre-soc.org/show_bug.cgi?id=325
+* https://bugs.libre-soc.org/show_bug.cgi?id=344
+* https://libre-soc.org/openpower/isa/fixedtrap/
 """
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, signed)