move sdir to CompFSMOpSubset in alu_fsm example

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index 606b4790566d4c188b0f4d0bb60f452e1e9a5a94..f85703c832156e7f2c91f11d3bb90e9e51f27ba1 100644 (file)
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -28,7 +28,7 @@ from soc.decoder.power_enums import (MicrOp, Function)
 
 class CompFSMOpSubset(CompOpSubsetBase):
     def __init__(self, name=None):
-        layout = (('dir', 1),
+        layout = (('sdir', 1),
                   )
 
         super().__init__(layout, name=name)
@@ -58,7 +58,6 @@ class Shifter(Elaboratable):
         def __init__(self, width):
             self.data = Signal(width, name="p_data_i")
             self.shift = Signal(width, name="p_shift_i")
-            self.sdir = Signal(name="p_sdir_i")
             self.ctx = Dummy() # comply with CompALU API
 
         def _get_data(self):
@@ -157,7 +156,7 @@ class Shifter(Elaboratable):
                     next_count.eq(self.p.data_i.shift),
                 ]
                 # capture the direction bit as well
-                m.d.sync += direction.eq(self.p.data_i.sdir)
+                m.d.sync += direction.eq(self.op.sdir)
                 with m.If(self.p.valid_i):
                     # Leave IDLE when data arrives
                     with m.If(next_count == 0):
@@ -185,9 +184,9 @@ class Shifter(Elaboratable):
         return m
 
     def __iter__(self):
+        yield self.op.sdir
         yield self.p.data_i.data
         yield self.p.data_i.shift
-        yield self.p.data_i.sdir
         yield self.p.valid_i
         yield self.p.ready_o
         yield self.n.ready_i
@@ -216,7 +215,7 @@ def test_shifter():
         # present input data and assert valid_i
         yield dut.p.data_i.data.eq(data)
         yield dut.p.data_i.shift.eq(shift)
-        yield dut.p.data_i.sdir.eq(direction)
+        yield dut.op.sdir.eq(direction)
         yield dut.p.valid_i.eq(1)
         yield
         # wait for p.ready_o to be asserted
@@ -226,7 +225,7 @@ def test_shifter():
         yield dut.p.valid_i.eq(0)
         yield dut.p.data_i.data.eq(0)
         yield dut.p.data_i.shift.eq(0)
-        yield dut.p.data_i.sdir.eq(0)
+        yield dut.op.sdir.eq(0)
 
     def receive(expected):
         # signal readiness to receive data