arch,cpu: Move a Decode DPRINTF into the arch Decoder classes.

This DPRINTF accesses the ExtMachInst typed machInst member of the
StaticInst class, and so is ISA dependent. Move the DPRINTF to where the
instructions are actually decoded where that type doesn't have to be
disambiguated.

Also, this change makes this DPRINTF more accurate, since microops are
not really "decoded" when they are extracted from a macroop. The process
of unpacking them to feed into the rest of the CPU should be fairly
trivial, so really they're just being retrieved. With the DPRINTF in
this new position, it will only trigger when an instruction is actually
decoded from memory.

Change-Id: I14145165b93bb004057a729fa7909cd2d3d34d29
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40099
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 4f8e71a02169ce646973e664a8d5ea5f89866974..1f143287faffe708bceb89d5752c1fceca419e3a 100644 (file)
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -49,6 +49,7 @@
 #include "arch/generic/decoder.hh"
 #include "base/types.hh"
 #include "cpu/static_inst.hh"
+#include "debug/Decode.hh"
 #include "enums/DecoderFlavor.hh"
 
 namespace ArmISA
@@ -172,7 +173,10 @@ class Decoder : public InstDecoder
     StaticInstPtr
     decode(ExtMachInst mach_inst, Addr addr)
     {
-        return defaultCache.decode(this, mach_inst, addr);
+        StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
+        DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
+                si->getName(), mach_inst);
+        return si;
     }
 
     /**

diff --git a/src/arch/mips/decoder.hh b/src/arch/mips/decoder.hh
index 9c6ae18f12110bf01d5d293eb6b1a8e3eb148f7b..6e00bc373188055c2bb46b3c97fa19229f3b3b09 100644 (file)
--- a/src/arch/mips/decoder.hh
+++ b/src/arch/mips/decoder.hh
@@ -35,6 +35,7 @@
 #include "base/logging.hh"
 #include "base/types.hh"
 #include "cpu/static_inst.hh"
+#include "debug/Decode.hh"
 
 namespace MipsISA
 {
@@ -98,7 +99,10 @@ class Decoder : public InstDecoder
     StaticInstPtr
     decode(ExtMachInst mach_inst, Addr addr)
     {
-        return defaultCache.decode(this, mach_inst, addr);
+        StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
+        DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
+                si->getName(), mach_inst);
+        return si;
     }
 
     StaticInstPtr

diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh
index d89c9b1d3926f8bc01c55a2a9b8a94fa4e3e5f31..4e02ef7bca0d496a0e3037cdcc8a2de1f728052c 100644 (file)
--- a/src/arch/power/decoder.hh
+++ b/src/arch/power/decoder.hh
@@ -33,6 +33,7 @@
 #include "arch/generic/decoder.hh"
 #include "arch/power/types.hh"
 #include "cpu/static_inst.hh"
+#include "debug/Decode.hh"
 
 namespace PowerISA
 {
@@ -105,7 +106,10 @@ class Decoder : public InstDecoder
     StaticInstPtr
     decode(ExtMachInst mach_inst, Addr addr)
     {
-        return defaultCache.decode(this, mach_inst, addr);
+        StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
+        DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
+                si->getName(), mach_inst);
+        return si;
     }
 
     StaticInstPtr

diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc
index a117991752dc74da5b386f18a64983f7b1c7db3c..26b6adba42ea79cfac206f4ea2b89af487cfe6f1 100644 (file)
--- a/src/arch/riscv/decoder.cc
+++ b/src/arch/riscv/decoder.cc
@@ -81,13 +81,14 @@ Decoder::decode(ExtMachInst mach_inst, Addr addr)
 {
     DPRINTF(Decode, "Decoding instruction 0x%08x at address %#x\n",
             mach_inst, addr);
-    if (instMap.find(mach_inst) != instMap.end())
-        return instMap[mach_inst];
-    else {
-        StaticInstPtr si = decodeInst(mach_inst);
-        instMap[mach_inst] = si;
-        return si;
-    }
+
+    StaticInstPtr &si = instMap[mach_inst];
+    if (!si)
+        si = decodeInst(mach_inst);
+
+    DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
+            si->getName(), mach_inst);
+    return si;
 }
 
 StaticInstPtr

diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh
index 8e6845131cec1410da1af62c46eb6cb777f68070..ece3b9c77d493ac2691db6d27681e1100801e798 100644 (file)
--- a/src/arch/sparc/decoder.hh
+++ b/src/arch/sparc/decoder.hh
@@ -34,6 +34,7 @@
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/types.hh"
 #include "cpu/static_inst.hh"
+#include "debug/Decode.hh"
 
 namespace SparcISA
 {
@@ -112,7 +113,10 @@ class Decoder : public InstDecoder
     StaticInstPtr
     decode(ExtMachInst mach_inst, Addr addr)
     {
-        return defaultCache.decode(this, mach_inst, addr);
+        StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
+        DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
+                si->getName(), mach_inst);
+        return si;
     }
 
     StaticInstPtr

diff --git a/src/arch/x86/decoder.cc b/src/arch/x86/decoder.cc
index 415c7b4c84decd935c0f45501428b57e6d3fbef9..95b80a8b11193caea45ec25de58c1c1a1add1570 100644 (file)
--- a/src/arch/x86/decoder.cc
+++ b/src/arch/x86/decoder.cc
@@ -32,6 +32,7 @@
 #include "base/logging.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
+#include "debug/Decode.hh"
 #include "debug/Decoder.hh"
 
 namespace X86ISA
@@ -674,12 +675,18 @@ Decoder::InstCacheMap Decoder::instCacheMap;
 StaticInstPtr
 Decoder::decode(ExtMachInst mach_inst, Addr addr)
 {
+    StaticInstPtr si;
+
     auto iter = instMap->find(mach_inst);
-    if (iter != instMap->end())
-        return iter->second;
+    if (iter != instMap->end()) {
+        si = iter->second;
+    } else {
+        si = decodeInst(mach_inst);
+        (*instMap)[mach_inst] = si;
+    }
 
-    StaticInstPtr si = decodeInst(mach_inst);
-    (*instMap)[mach_inst] = si;
+    DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
+            si->getName(), mach_inst);
     return si;
 }
 

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 62df848812e2c65db96418ac0ead11019e158396..0941388f73500c90892e790e5b0f33cf848ca782 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -368,9 +368,6 @@ BaseSimpleCPU::preExecute()
 #if TRACING_ON
         traceData = tracer->getInstRecord(curTick(), thread->getTC(),
                 curStaticInst, thread->pcState(), curMacroStaticInst);
-
-        DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
-                curStaticInst->getName(), curStaticInst->machInst);
 #endif // TRACING_ON
     }