debugging decoding of SPRs (fast)

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index d093ad1b5c74b85a3f09b3d88033673c43897d82..12cb66478cca422e5261abc2650801706ef62a45 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -188,6 +188,8 @@ class SPR(dict):
         self.sd = dec2
         dict.__init__(self)
         for key, v in initial_sprs.items():
+            if isinstance(key, str):
+                key = spr_byname[key].SPR
             if isinstance(key, SelectableInt):
                 key = key.value
             key = special_sprs.get(key, key)
@@ -200,21 +202,26 @@ class SPR(dict):
             self[key] = v
 
     def __getitem__(self, key):
+        print ("get spr", key)
+        print ("dict", self.items())
         # if key in special_sprs get the special spr, otherwise return key
         if isinstance(key, SelectableInt):
             key = key.value
         key = special_sprs.get(key, key)
         if key in self:
-            return dict.__getitem__(self, key)
+            res = dict.__getitem__(self, key)
         else:
             info = spr_dict[key]
             dict.__setitem__(self, key, SelectableInt(0, info.length))
-            return dict.__getitem__(self, key)
+            res = dict.__getitem__(self, key)
+        print ("spr returning", key, res)
+        return res
 
     def __setitem__(self, key, value):
         if isinstance(key, SelectableInt):
             key = key.value
         key = special_sprs.get(key, key)
+        print ("setting spr", key, value)
         dict.__setitem__(self, key, value)
 
     def __call__(self, ridx):

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index dd7b7a5d940c021764da338d27b6a90a181b01ac..aa9fcaecae14b6bf38099e153dd9bf0aa0276fdb 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -107,23 +107,27 @@ class DecodeA(Elaboratable):
             comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
             with m.Switch(spr):
                 # fast SPRs
-                with m.Case(SPR.CTR):
-                    self.fast_out.data.eq(FastRegs.CTR)
-                    self.fast_out.ok.eq(1)
-                with m.Case(SPR.LR):
-                    self.fast_out.data.eq(FastRegs.LR)
-                    self.fast_out.ok.eq(1)
-                with m.Case(SPR.TAR):
-                    self.fast_out.data.eq(FastRegs.TAR)
-                    self.fast_out.ok.eq(1)
-                with m.Case(SPR.SRR0):
-                    self.fast_out.data.eq(FastRegs.SRR0)
-                    self.fast_out.ok.eq(1)
-                with m.Case(SPR.SRR1):
-                    self.fast_out.data.eq(FastRegs.SRR1)
-                    self.fast_out.ok.eq(1)
+                with m.Case(SPR.CTR.value):
+                    comb += self.fast_out.data.eq(FastRegs.CTR)
+                    comb += self.fast_out.ok.eq(1)
+                with m.Case(SPR.LR.value):
+                    comb += self.fast_out.data.eq(FastRegs.LR)
+                    comb += self.fast_out.ok.eq(1)
+                with m.Case(SPR.TAR.value):
+                    comb += self.fast_out.data.eq(FastRegs.TAR)
+                    comb += self.fast_out.ok.eq(1)
+                with m.Case(SPR.SRR0.value):
+                    comb += self.fast_out.data.eq(FastRegs.SRR0)
+                    comb += self.fast_out.ok.eq(1)
+                with m.Case(SPR.SRR1.value):
+                    comb += self.fast_out.data.eq(FastRegs.SRR1)
+                    comb += self.fast_out.ok.eq(1)
+                with m.Case(SPR.XER.value):
+                    pass # do nothing
+                # XXX TODO: map to internal SPR numbers
+                # XXX TODO: dec and tb not to go through mapping.
                 with m.Default():
-                    comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
+                    comb += self.spr_out.data.eq(spr)
                     comb += self.spr_out.ok.eq(1)
 
 
@@ -272,23 +276,27 @@ class DecodeOut(Elaboratable):
                 with m.If(op.internal_op == InternalOp.OP_MTSPR):
                     with m.Switch(spr):
                         # fast SPRs
-                        with m.Case(SPR.CTR):
-                            self.fast_out.data.eq(FastRegs.CTR)
-                            self.fast_out.ok.eq(1)
-                        with m.Case(SPR.LR):
-                            self.fast_out.data.eq(FastRegs.LR)
-                            self.fast_out.ok.eq(1)
-                        with m.Case(SPR.TAR):
-                            self.fast_out.data.eq(FastRegs.TAR)
-                            self.fast_out.ok.eq(1)
-                        with m.Case(SPR.SRR0):
-                            self.fast_out.data.eq(FastRegs.SRR0)
-                            self.fast_out.ok.eq(1)
-                        with m.Case(SPR.SRR1):
-                            self.fast_out.data.eq(FastRegs.SRR1)
-                            self.fast_out.ok.eq(1)
+                        with m.Case(SPR.CTR.value):
+                            comb += self.fast_out.data.eq(FastRegs.CTR)
+                            comb += self.fast_out.ok.eq(1)
+                        with m.Case(SPR.LR.value):
+                            comb += self.fast_out.data.eq(FastRegs.LR)
+                            comb += self.fast_out.ok.eq(1)
+                        with m.Case(SPR.TAR.value):
+                            comb += self.fast_out.data.eq(FastRegs.TAR)
+                            comb += self.fast_out.ok.eq(1)
+                        with m.Case(SPR.SRR0.value):
+                            comb += self.fast_out.data.eq(FastRegs.SRR0)
+                            comb += self.fast_out.ok.eq(1)
+                        with m.Case(SPR.SRR1.value):
+                            comb += self.fast_out.data.eq(FastRegs.SRR1)
+                            comb += self.fast_out.ok.eq(1)
+                        with m.Case(SPR.XER.value):
+                            pass # do nothing
+                        # XXX TODO: map to internal SPR numbers
+                        # XXX TODO: dec and tb not to go through mapping.
                         with m.Default():
-                            comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
+                            comb += self.spr_out.data.eq(spr)
                             comb += self.spr_out.ok.eq(1)
 
         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
@@ -579,7 +587,7 @@ class PowerDecode2(Elaboratable):
         comb += e.read_fast1.eq(dec_a.fast_out)
         comb += e.read_fast2.eq(dec_b.fast_out)
         comb += e.write_fast1.eq(dec_o.fast_out)
-        comb += e.write_fast2.eq(dec_o2.fast_out)
+        comb += e.write_fast1.eq(dec_o2.fast_out)
 
         comb += e.read_cr1.eq(dec_cr_in.cr_bitfield)
         comb += e.read_cr2.eq(dec_cr_in.cr_bitfield_b)

diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py
index f16d24dff54c867cace9ecdaac53b56e3005dc49..e2234e67edaca195601de8dcc7ea4b7b07064842 100644 (file)
--- a/src/soc/fu/spr/main_stage.py
+++ b/src/soc/fu/spr/main_stage.py
@@ -39,8 +39,8 @@ class SPRMainStage(PipeModBase):
 
         # take copy of D-Form TO field
         x_fields = self.fields.FormXFX
-        spr = Signal(x_fields.SPR[0:-1].shape())
-        comb += spr.eq(decode_spr_num(x_fields.SPR[0:-1]))
+        spr = Signal(len(x_fields.SPR))
+        comb += spr.eq(decode_spr_num(x_fields.SPR))
 
         # TODO: some #defines for the bits n stuff.
         with m.Switch(op.insn_type):

diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py
index 7eca695d7e9bccc54d59fe22f595216352010502..77d0519a3a5bac9ded00dafedf817caa2f34c54f 100644 (file)
--- a/src/soc/fu/spr/test/test_pipe_caller.py
+++ b/src/soc/fu/spr/test/test_pipe_caller.py
@@ -83,9 +83,10 @@ class SPRTestCase(FHDLTestCase):
 
     def test_1_mfspr(self):
         lst = ["mfspr 1, 26", # SRR0
-               "mfspr 2, 27",] # SRR1
+               "mfspr 2, 27",  # SRR1
+               "mfspr 2, 8",] # LR
         initial_regs = [0] * 32
-        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
+        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234}
         self.run_tst_program(Program(lst), initial_regs, initial_sprs)
 
     def test_ilang(self):
@@ -122,7 +123,8 @@ class TestRunner(FHDLTestCase):
         sim.add_clock(1e-6)
         def process():
             for test in self.test_data:
-                print(test.name)
+                print("test", test.name)
+                print ("sprs", test.sprs)
                 program = test.program
                 self.subTest(test.name)
                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
@@ -137,6 +139,7 @@ class TestRunner(FHDLTestCase):
 
                     print("pc %08x instr: %08x" % (pc, ins & 0xffffffff))
                     print(code)
+
                     if 'XER' in sim.spr:
                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
@@ -147,6 +150,15 @@ class TestRunner(FHDLTestCase):
                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
+
+                    fast_in = yield pdecode2.e.read_fast1.data
+                    spr_in = yield pdecode2.e.read_spr1.data
+                    print ("dec2 spr/fast in", fast_in, spr_in)
+
+                    fast_out = yield pdecode2.e.write_fast1.data
+                    spr_out = yield pdecode2.e.write_spr.data
+                    print ("dec2 spr/fast in", fast_out, spr_out)
+
                     fn_unit = yield pdecode2.e.fn_unit
                     self.assertEqual(fn_unit, Function.SPR.value)
                     yield from set_alu_inputs(alu, pdecode2, sim)

diff --git a/src/soc/regfile/util.py b/src/soc/regfile/util.py
index f27d711e417e0fd990cd42decbd5988497c979f3..1587e550d0a445406bee600cb2215af16044b5b9 100644 (file)
--- a/src/soc/regfile/util.py
+++ b/src/soc/regfile/util.py
@@ -8,3 +8,7 @@ def fast_reg_to_spr(spr_num):
         return SPR.LR.value
     elif spr_num == FastRegs.TAR:
         return SPR.TAR.value
+    elif spr_num == FastRegs.SRR0:
+        return SPR.SRR0.value
+    elif spr_num == FastRegs.SRR1:
+        return SPR.SRR1.value