more post-processing of vst files

diff --git a/ls180/post_pnr/cocotb/Makefile b/ls180/post_pnr/cocotb/Makefile
index 9cd849af9df3b0fe00f4a922cbbbc114a36c0126..cb4cc70b30138743f9f6dc074932158cfbf94daf 100644 (file)
--- a/ls180/post_pnr/cocotb/Makefile
+++ b/ls180/post_pnr/cocotb/Makefile
@@ -12,13 +12,13 @@ VSTDIR=$(TOPDIR)/vst_src
 CHIPDIR=$(TOPDIR)/chip_corona
 NSXLIBDIR=$(TOPDIR)/nsxlib
 NIOLIBDIR=$(TOPDIR)/niolib
+#  $(CHIPDIR)/chip_r.vhd 
+#  $(CHIPDIR)/corona_cts_r.vhd 
 VHDL_SOURCES = \
-  $(CHIPDIR)/chip_r.vhd \
-  $(CHIPDIR)/corona_cts_r.vhd \
   $(wildcard $(VSTDIR)/*.vst) \
   $(wildcard $(NSXLIBDIR)/*.vhd) \
   $(wildcard $(NIOLIBDIR)/*.vhd)
-TOPLEVEL=chip_r
+TOPLEVEL=chip
 TOPLEVEL_LANG=vhdl
 MODULE=test
 SIM=ghdl

diff --git a/ls180/post_pnr/vst_correct.py b/ls180/post_pnr/vst_correct.py
index d78d08d6ef73e19e1c86fb855487587c6cc601e7..0f454660241d8c40f376e191f7244af3b64c687c 100755 (executable)
--- a/ls180/post_pnr/vst_correct.py
+++ b/ls180/post_pnr/vst_correct.py
@@ -37,6 +37,9 @@ for fname in os.listdir("vst_src"):
         txt = txt.replace("sys_rst : gpio",
                           "p_sys_rst: gpio")
 
+        # corona instance needs renaming too
+        txt = txt.replace("corona : corona", "instance_corona : corona")
+
         # temporary hack to rename niolib to avoid name-clashes
         for cell in ['gpio', 'vss', 'vdd', 'iovss', 'iovdd']:
             txt = txt.replace(": %s" % cell, ": cmpt_%s" % cell)
@@ -60,6 +63,12 @@ for fname in os.listdir("vst_src"):
             res.append(line)
         # re-join lines
         txt = '\n'.join(res)
+        # easier to just post-process-correct the iovdd std_logic
+        for port in ['vss', 'vdd', 'iovss', 'iovdd']:
+            txt = txt.replace("%-9s: inout std_logic" % port,
+                              "%-9s: in bit" % port)
+
+        
     # write the file
     with open(fname, "w") as f:
         f.write(txt)