horrible clock-sync hack

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index e4df4b5ea86870086ab2479a76482f3180a90c43..e7de1965accbb0ebd52bf40a4bbf8b723decc346 100644 (file)
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -245,6 +245,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection(
                     n_ = "{0}{1}".format(n, count)
                 else:
                     n_ = n
+                n_ = '{0}_{1}'.format(n_, pname)
                 ret.append(template.format("Bit#(1)", n_, ck, spc))
             if typ == 'in' or typ == 'inout':
                 #fname = self.pinname_in(pname)