whitespace

diff --git a/libreriscv b/libreriscv
index d83e5ccbacd56e762bedc660cdd930264e12b81b..12e9237b896ad233cb18946b34dab17d976f415c 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit d83e5ccbacd56e762bedc660cdd930264e12b81b
+Subproject commit 12e9237b896ad233cb18946b34dab17d976f415c

diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py
index 970ac7cfb5c476b6020fdeccadc7b9f4d4b3ff00..b029f04bf86b3c2a18607c84cab6f847fd65c639 100644 (file)
--- a/src/soc/fu/div/pipe_data.py
+++ b/src/soc/fu/div/pipe_data.py
@@ -54,7 +54,8 @@ class DivPipeKindConfig:
 class DivPipeKind(enum.Enum):
     # use ieee754.div_rem_sqrt_rsqrt.core.DivPipeCore*
     DivPipeCore = enum.auto()
-    # use nmigen's built-in div and rem operators -- only suitable for simulation
+    # use nmigen's built-in div and rem operators -- only suitable for
+    # simulation
     SimOnly = enum.auto()
     # use a FSM-based div core
     FSMCore = enum.auto()
@@ -142,14 +143,17 @@ class CoreBaseData(DivInputData):
 
 class CoreInputData(CoreBaseData):
     def __init__(self, pspec):
-        super().__init__(pspec, pspec.div_pipe_kind.config.core_input_data_class)
+        super().__init__(pspec,
+                         pspec.div_pipe_kind.config.core_input_data_class)
 
 
 class CoreInterstageData(CoreBaseData):
     def __init__(self, pspec):
-        super().__init__(pspec, pspec.div_pipe_kind.config.core_interstage_data_class)
+        super().__init__(pspec,
+                         pspec.div_pipe_kind.config.core_interstage_data_class)
 
 
 class CoreOutputData(CoreBaseData):
     def __init__(self, pspec):
-        super().__init__(pspec, pspec.div_pipe_kind.config.core_output_data_class)
+        super().__init__(pspec,
+                         pspec.div_pipe_kind.config.core_output_data_class)