call property data_r not data

diff --git a/src/add/iocontrol.py b/src/add/iocontrol.py
index 3afd98475c43e2152ef6f566d604d118dcb3f8b1..a6a94bc4031bb02dacb8079c54fc18dee873a474 100644 (file)
--- a/src/add/iocontrol.py
+++ b/src/add/iocontrol.py
@@ -541,7 +541,7 @@ class ControlBase(Elaboratable):
         return eqs
 
     @property
-    def data(self):
+    def data_r(self):
         return self.stage.process(self.p.data_i)
 
     def _postprocess(self, i): # XXX DISABLED

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 220dbefcf28a0fd3666b3ca3c73c093c1c2800d8..5f7dc66ba23679ddb5b783ac395d99782bfbc7b2 100644 (file)
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -209,7 +209,7 @@ class BufferedHandshake(ControlBase):
         ]
 
         # store result of processing in combinatorial temporary
-        self.m.d.comb += nmoperator.eq(result, self.data)
+        self.m.d.comb += nmoperator.eq(result, self.data_r)
 
         # if not in stall condition, update the temporary register
         with self.m.If(self.p.ready_o): # not stalled
@@ -292,7 +292,7 @@ class SimpleHandshake(ControlBase):
         ]
 
         # store result of processing in combinatorial temporary
-        m.d.comb += nmoperator.eq(result, self.data)
+        m.d.comb += nmoperator.eq(result, self.data_r)
 
         # previous valid and ready
         with m.If(p_valid_i_p_ready_o):
@@ -403,7 +403,7 @@ class UnbufferedPipeline(ControlBase):
         m.d.sync += data_valid.eq(p_valid_i | buf_full)
 
         with m.If(pv):
-            m.d.sync += nmoperator.eq(r_data, self.data)
+            m.d.sync += nmoperator.eq(r_data, self.data_r)
         data_o = self._postprocess(r_data) # XXX TBD, does nothing right now
         m.d.comb += nmoperator.eq(self.n.data_o, data_o)
 
@@ -484,7 +484,7 @@ class UnbufferedPipeline2(ControlBase):
         m.d.comb += self.p._ready_o.eq(~buf_full)
         m.d.sync += buf_full.eq(~self.n.ready_i_test & self.n.valid_o)
 
-        data_o = Mux(buf_full, buf, self.data)
+        data_o = Mux(buf_full, buf, self.data_r)
         data_o = self._postprocess(data_o) # XXX TBD, does nothing right now
         m.d.comb += nmoperator.eq(self.n.data_o, data_o)
         m.d.sync += nmoperator.eq(buf, self.n.data_o)
@@ -554,7 +554,7 @@ class PassThroughHandshake(ControlBase):
         m.d.comb += self.p.ready_o.eq(~self.n.valid_o |  self.n.ready_i_test)
         m.d.sync += self.n.valid_o.eq(p_valid_i       | ~self.p.ready_o)
 
-        odata = Mux(pvr, self.data, r_data)
+        odata = Mux(pvr, self.data_r, r_data)
         m.d.sync += nmoperator.eq(r_data, odata)
         r_data = self._postprocess(r_data) # XXX TBD, does nothing right now
         m.d.comb += nmoperator.eq(self.n.data_o, r_data)
@@ -622,7 +622,7 @@ class FIFOControl(ControlBase):
 
         # store result of processing in combinatorial temporary
         result = _spec(self.stage.ospec, "r_temp")
-        m.d.comb += nmoperator.eq(result, self.data)
+        m.d.comb += nmoperator.eq(result, self.data_r)
 
         # connect previous rdy/valid/data - do cat on data_i
         # NOTE: cannot do the PrevControl-looking trick because

diff --git a/src/add/test_fsm_experiment.py b/src/add/test_fsm_experiment.py
index b40bb63f0445a3e2ad080be4d8b8f9319f8330f7..d9c76e6080cbb9a2a50c31f6f9746ebeed0549aa 100644 (file)
--- a/src/add/test_fsm_experiment.py
+++ b/src/add/test_fsm_experiment.py
@@ -105,7 +105,7 @@ class FPDIVPipe(ControlBase):
 
         m.d.comb += self.n.valid_o.eq(self.fpdiv.out_z.valid_o)
         m.d.comb += self.fpdiv.out_z.ready_i.eq(self.n.ready_i_test)
-        m.d.comb += self.n.data_o.eq(self.data)
+        m.d.comb += self.n.data_o.eq(self.data_r)
 
         return m