rename ref to ref_v in PLL due to ref being a verilog keyword

diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py
index 2363274cf4f6dcde2dc336297ae16da4f733619e..1fcc4f3b74e1e8caff9337b6f4c62207f34de6e2 100644 (file)
--- a/src/soc/clock/dummypll.py
+++ b/src/soc/clock/dummypll.py
@@ -22,7 +22,7 @@ class DummyPLL(Elaboratable):
             clk_pll_o = Signal(reset_less=True)  # output clock
             pll_test_o = Signal(reset_less=True)  # test out
             pll_vco_o = Signal(reset_less=True) # analog
-            pll = Instance("pll", i_ref=clk_24_i,
+            pll = Instance("pll", i_ref_v=clk_24_i,
                                   i_a0=clk_sel_i[0],
                                   i_a1=clk_sel_i[1],
                                   o_out_v=clk_pll_o,