separate out divide by zero cases

diff --git a/src/soc/simulator/test_div_sim.py b/src/soc/simulator/test_div_sim.py
index 37d0dc7ca4982a414cb5005df6a667d856db02bb..610f7f86086faf88678d33d3a89029619ccc6879 100644 (file)
--- a/src/soc/simulator/test_div_sim.py
+++ b/src/soc/simulator/test_div_sim.py
@@ -48,8 +48,30 @@ class DivTestCases(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1, 2, 3])
 
-    @unittest.skip("qemu_wrong_result")
-    def test_3_divwo_byzero(self):
+    def test_4_moduw(self):
+        lst = ["addi 1, 0, 0x5678",
+               "addi 2, 0, 0x1234",
+               "moduw  3, 1, 2",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
+    def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
+                                    initial_mem=None):
+        initial_regs = [0] * 32
+        tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
+                                            initial_mem, 0)
+        self.test_data.append(tc)
+
+
+class DivZeroTestCases(FHDLTestCase):
+    test_data = []
+
+    def __init__(self, name="divbyzero"):
+        super().__init__(name)
+        self.test_name = name
+
+    def test_0_divw(self):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x0",
                "divw  3, 1, 2",
@@ -57,9 +79,25 @@ class DivTestCases(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1, 2, 3])
 
+    def test_1_divwe(self):
+        lst = ["addi 1, 0, 0x5678",
+               "addi 2, 0, 0x0",
+               "divwe  3, 1, 2",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
+    def test_2_divweu(self):
+        lst = ["addi 1, 0, 0x5678",
+               "addi 2, 0, 0x0",
+               "divweu  3, 1, 2",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
     def test_4_moduw(self):
         lst = ["addi 1, 0, 0x5678",
-               "addi 2, 0, 0x1234",
+               "addi 2, 0, 0x0",
                "moduw  3, 1, 2",
                ]
         with Program(lst) as program:
@@ -73,9 +111,12 @@ class DivTestCases(FHDLTestCase):
         self.test_data.append(tc)
 
 
-class DecoderTestCase(DecoderBase, DivTestCases):
+
+class DivDecoderTestCase(DecoderBase, DivTestCases):
     pass
 
+class DivZeroDecoderTestCase(DecoderBase, DivZeroTestCases):
+    pass
 
 if __name__ == "__main__":
     unittest.main()