add some print statements and comments explaining what the heck is going on

diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py
index 5349ee9ab23564d03f5d946e01f11b98b1192259..a972ce518370a90c59e1bedaa3226aec2930213c 100644 (file)
--- a/src/spec/testing_stage1.py
+++ b/src/spec/testing_stage1.py
@@ -243,8 +243,20 @@ class ASICPlatform(TemplatedPlatform):
 
         print ("    get_input", pin, "port", port, port.layout)
         if pin.name not in ['clk_0', 'rst_0']: # sigh
-            pad = self.padlookup[pin.name]
-            print ("       pad", pad)
+            (res, pin, port, attrs) = self.padlookup[pin.name]
+            io = self.jtag.ios[pin.name]
+            print ("       pad", res, pin, port, attrs)
+            print ("       pin", pin.layout)
+            print ("      jtag", io.core.layout, io.pad.layout)
+            # Layout basically contains the list of objects (and sizes)
+            # so a Layout of [('i', 1)] means, "this object has a Signal
+            # named i and it is of length 1".  threfore:
+            # * pin has a pin.i of length 1
+            # * io.core has an io.core.i of length 1
+            # * io.pad has an io.pad.i of length 1
+            # Your Mission, Should You Choose To Accept It, is to
+            # work out which bleeding way round what the hell is
+            # connected to what.
         m = Module()
         m.d.comb += pin.i.eq(self._invert_if(invert, port))
         return m