comment where ALUIntermediateData to go

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index 07fb0180de7d73f627386a3d847dd56ded43aadd..7d79b1a187a303fce461149bd5610ac6ab58659e 100644 (file)
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -18,7 +18,7 @@ class ALUMainStage(PipeModBase):
         return ALUInputData(self.pspec)
 
     def ospec(self):
-        return ALUOutputData(self.pspec)
+        return ALUOutputData(self.pspec) # TODO: ALUIntermediateData
 
     def elaborate(self, platform):
         m = Module()

diff --git a/src/soc/alu/output_stage.py b/src/soc/alu/output_stage.py
index 1a8a82b620149ce83aceabe8a0cf6262e7ab58b0..188ea4ab0f021db9585e172ced2bc144b4368d3e 100644 (file)
--- a/src/soc/alu/output_stage.py
+++ b/src/soc/alu/output_stage.py
@@ -13,7 +13,7 @@ class ALUOutputStage(PipeModBase):
         super().__init__(pspec, "output")
 
     def ispec(self):
-        return ALUOutputData(self.pspec)
+        return ALUOutputData(self.pspec) # TODO: ALUIntermediateData
 
     def ospec(self):
         return ALUOutputData(self.pspec)