self.namespace[name] = SelectableInt(val, bits=signal.width)
def call(self, name):
- function, read_regs, uninit_regs, write_regs, op_fields, form \
+ # TODO, asmregs is from the spec, e.g. add RT,RA,RB
+ # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
+ fn, read_regs, uninit_regs, write_regs, op_fields, asmregs, form \
= self.instrs[name]
yield from self.prep_namespace(form, op_fields)
print('reading reg %d' % regnum)
inputs.append(self.gpr(regnum))
print(inputs)
- results = function(self, *inputs)
+ results = fn(self, *inputs)
print(results)
if write_regs:
"""
+iinfo_template = """(%s, %s,
+ %s, %s,
+ %s, '%s',
+ %s)"""
+
class PyISAWriter(ISA):
def __init__(self):
ISA.__init__(self)
f.write("\n")
# accumulate the instruction info
ops = repr(rused['op_fields'])
- iinfo = """(%s, %s,
- %s, %s,
- %s, '%s')""" % (op_fname, rused['read_regs'],
+ iinfo = iinfo_template % (op_fname, rused['read_regs'],
rused['uninit_regs'], rused['write_regs'],
- ops, d.form)
+ ops, d.form, d.regs)
iinf += " %s_instrs['%s'] = %s\n" % (pagename, page, iinfo)
# write out initialisation of info, for ISACaller to use
f.write(" %s_instrs = {}\n" % pagename)