use signals instead of arrays

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index d1c2dbb5a2b949b0ef457bebba2a78d1482bcd7d..d40a34dd03bb8431784bb00fca230498c94f1134 100644 (file)
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -259,14 +259,11 @@ class Scoreboard(Elaboratable):
         m.d.comb += intfus.int_src1_i.eq(self.int_src1_i)
         m.d.comb += intfus.int_src2_i.eq(self.int_src2_i)
 
-        fn_issue_o = Signal(n_int_fus, reset_less=True)
-        for i in range(n_int_fus):
-            m.d.comb += fn_issue_o[i].eq(issueunit.i.fn_issue_o[i])
+        fn_issue_o = issueunit.i.fn_issue_o
 
         m.d.comb += intfus.fn_issue_i.eq(fn_issue_o)
         # XXX sync, so as to stop a simulation infinite loop
-        for i in range(n_int_fus):
-            m.d.sync += issueunit.i.busy_i[i].eq(intfus.fn_busy_o[i])
+        m.d.sync += issueunit.i.busy_i.eq(intfus.fn_busy_o)
 
         #---------
         # connect fu-fu matrix
@@ -307,14 +304,11 @@ class Scoreboard(Elaboratable):
 
         # Connect Picker
         #---------
-        m.d.comb += intpick1.req_rel_i[0].eq(cu.req_rel_o[0])
-        m.d.comb += intpick1.req_rel_i[1].eq(cu.req_rel_o[1])
+        m.d.comb += intpick1.req_rel_i[0:2].eq(cu.req_rel_o[0:2])
         int_readable_o = intfudeps.readable_o
         int_writable_o = intfudeps.writable_o
-        m.d.sync += intpick1.readable_i[0].eq(int_readable_o[0]) # add rd
-        m.d.sync += intpick1.writable_i[0].eq(int_writable_o[0]) # add wr
-        m.d.sync += intpick1.readable_i[1].eq(int_readable_o[1]) # sub rd
-        m.d.sync += intpick1.writable_i[1].eq(int_writable_o[1]) # sub wr
+        m.d.sync += intpick1.readable_i[0:2].eq(int_readable_o[0:2])
+        m.d.sync += intpick1.writable_i[0:2].eq(int_writable_o[0:2])
 
         #---------
         # Connect Register File(s)
@@ -330,10 +324,9 @@ class Scoreboard(Elaboratable):
         m.d.comb += cu.src2_data_i.eq(int_src2.data_o)
 
         # connect ALU Computation Units
-        for i in range(n_int_alus):
-            m.d.sync += cu.go_rd_i[i].eq(go_rd_o[i])
-            m.d.sync += cu.go_wr_i[i].eq(go_wr_o[i])
-            m.d.sync += cu.issue_i[i].eq(fn_issue_o[i])
+        m.d.sync += cu.go_rd_i[0:2].eq(go_rd_o[0:2])
+        m.d.sync += cu.go_wr_i[0:2].eq(go_wr_o[0:2])
+        m.d.sync += cu.issue_i[0:2].eq(fn_issue_o[0:2])
 
         # Connect ALU request release to FUs
         m.d.comb += intfus.req_rel_i.eq(cu.req_rel_o) # pipe out ready

diff --git a/src/scoreboard/issue_unit.py b/src/scoreboard/issue_unit.py
index 2ebb695ed6a92e2227e2db7fccd1bd9cacc48766..ade35d7683262e3f00d5533d297d4bd6c20e61eb 100644 (file)
--- a/src/scoreboard/issue_unit.py
+++ b/src/scoreboard/issue_unit.py
@@ -75,12 +75,10 @@ class IssueUnit(Elaboratable):
         self.g_wr_pend_i = Signal(wid, reset_less=True) # write pending vector
 
         self.insn_i = Signal(n_insns, reset_less=True, name="insn_i")
-        self.busy_i = Array(Signal(reset_less=True, name="busy_i") \
-                               for i in range(n_insns))
+        self.busy_i = Signal(n_insns, reset_less=True, name="busy_i")
 
         # outputs
-        self.fn_issue_o = Array(Signal(reset_less=True, name="fn_issue_o") \
-                               for i in range(n_insns))
+        self.fn_issue_o = Signal(n_insns, reset_less=True, name="fn_issue_o")
         self.g_issue_o = Signal(reset_less=True)
 
     def elaborate(self, platform):