add jtagremote to litex sim, add new "variant" to core.py for jtag

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 77352d8b4c855152cd3c381907d54cf2fecd3063..a082f72bb983bb7379b0ad21f278ef1d0e4edf76 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -5,23 +5,26 @@ from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
 from litex.soc.interconnect import wishbone as wb
 from litex.soc.cores.cpu import CPU
 
-CPU_VARIANTS = ["standard", "standard32", "ls180"]
+CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180"]
 
 
-def make_wb_bus(prefix, obj):
+def make_wb_bus(prefix, obj, simple=False):
     res = {}
-    for o in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
-        res['o_%s_%s' % (prefix, o)] = getattr(obj, o)
+    outpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
+    if not simple:
+        outpins += ['cti', 'bte']
+    for o in outpins:
+        res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
     for i in ['ack', 'err', 'dat_r']:
-        res['i_%s_%s' % (prefix, i)] = getattr(obj, i)
+        res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
     return res
 
 def make_wb_slave(prefix, obj):
     res = {}
     for i in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
-        res['i_%s_%s' % (prefix, i)] = getattr(obj, i)
+        res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
     for o in ['ack', 'err', 'dat_r']:
-        res['o_%s_%s' % (prefix, o)] = getattr(obj, o)
+        res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
     return res
 
 
@@ -72,15 +75,17 @@ class LibreSoC(CPU):
         self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
         self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
 
+        jtag_en = ('jtag' in variant) or variant == 'ls180'
+
         if variant != "ls180":
             self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
-        else:
+        if jtag_en:
             self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
 
         self.periph_buses = [ibus, dbus]
         self.memory_buses = []
 
-        if variant == "ls180":
+        if jtag_en:
             self.periph_buses.append(jtag_wb)
             self.jtag_tck = Signal(1)
             self.jtag_tms = Signal(1)
@@ -114,7 +119,15 @@ class LibreSoC(CPU):
 
         )
 
-        if variant != "ls180":
+        if jtag_en:
+            self.cpu_params.update(dict(
+                # JTAG Debug bus
+                o_TAP_bus__tdo = self.jtag_tdo,
+                i_TAP_bus__tdi = self.jtag_tdi,
+                i_TAP_bus__tms = self.jtag_tms,
+                i_TAP_bus__tck = self.jtag_tck,
+            ))
+        else:
             self.cpu_params.update(dict(
                 # DMI Debug bus
                 i_dmi_addr_i          = self.dmi_addr,
@@ -124,24 +137,16 @@ class LibreSoC(CPU):
                 i_dmi_we_i            = self.dmi_wr,
                 o_dmi_ack_o           = self.dmi_ack,
             ))
-        else:
-            self.cpu_params.update(dict(
-                # JTAG Debug bus
-                o_TAP_bus__tdo = self.jtag_tdo,
-                i_TAP_bus__tdi = self.jtag_tdi,
-                i_TAP_bus__tms = self.jtag_tms,
-                i_TAP_bus__tck = self.jtag_tck,
-            ))
 
         # add wishbone buses to cpu params
-        self.cpu_params.update(make_wb_bus("ibus_", ibus))
-        self.cpu_params.update(make_wb_bus("dbus_", dbus))
-        self.cpu_params.update(make_wb_slave("ics_wb_", ics))
-        self.cpu_params.update(make_wb_slave("icp_wb_", icp))
+        self.cpu_params.update(make_wb_bus("ibus", ibus))
+        self.cpu_params.update(make_wb_bus("dbus", dbus))
+        self.cpu_params.update(make_wb_slave("ics_wb", ics))
+        self.cpu_params.update(make_wb_slave("icp_wb", icp))
         if variant != "ls180":
-            self.cpu_params.update(make_wb_slave("gpio_wb_", gpio))
-        else:
-            self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb))
+            self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
+        if jtag_en:
+            self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
 
         # add verilog sources
         self.add_sources(platform)

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index b18ccb95b13458773db787ae5b2236f29f27638e..87521ebd0519f110de29ca2a48320261459ba048 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -49,22 +49,22 @@ class LibreSoCSim(SoCSDRAM):
         if cpu_data_width == 32:
             variant = "standard32"
         else:
-            variant = "standard"
+            variant = "standardjtag"
 
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "tests/1.bin"
         #ram_fname = "/tmp/test.bin"
-        #ram_fname = None
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "micropython/firmware.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "tests/xics/xics.bin"
-        ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-                    "tests/decrementer/decrementer.bin"
+        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+        #            "tests/decrementer/decrementer.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
+        ram_fname = None
 
         # reserve XICS ICP and XICS memory addresses.
         self.mem_map['icp'] = 0xc0004000
@@ -446,6 +446,7 @@ def main():
 
     sim_config = SimConfig(default_clk="sys_clk")
     sim_config.add_module("serial2console", "serial")
+    sim_config.add_module("jtagremote", "jtag", args={'port': 44853})
 
     for i in range(2):
         soc = LibreSoCSim(cpu=args.cpu, debug=args.debug)

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 820e5fd32ddfb3603efcd53b0639d1eb22080ff7..394913c2226b21922509f51ee372975b70305b65 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -28,7 +28,7 @@ if __name__ == '__main__':
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
                          xics=True,
-                         gpio=False, # for test purposes
+                         gpio=True, # for test purposes
                          debug="jtag", # set to jtag or dmi
                          units=units)