format code

diff --git a/src/soc/fu/div/test/runner.py b/src/soc/fu/div/test/runner.py
index 04f837b6590175a61d86216afe1bbffc13771e49..ee4d842d0c0dd2a83952294ac0a5d2a25d10eaaf 100644 (file)
--- a/src/soc/fu/div/test/runner.py
+++ b/src/soc/fu/div/test/runner.py
@@ -16,6 +16,7 @@ from soc.fu.div.pipe_data import DivPipeSpec, DivPipeKind
 
 import power_instruction_analyzer as pia
 
+
 def log_rand(n, min_val=1):
     logrange = random.randint(1, n)
     return random.randint(min_val, (1 << logrange)-1)
@@ -100,7 +101,7 @@ def set_alu_inputs(alu, dec2, sim):
 
 class DivRunner(unittest.TestCase):
     def __init__(self, test_data, div_pipe_kind=None):
-        print ("DivRunner", test_data, div_pipe_kind)
+        print("DivRunner", test_data, div_pipe_kind)
         super().__init__("run_all")
         self.test_data = test_data
         self.div_pipe_kind = div_pipe_kind
@@ -301,4 +302,3 @@ class DivRunner(unittest.TestCase):
             print("so, ov", so_ok, ov_ok)
             self.assertEqual(ov_ok, False, code)
             self.assertEqual(so_ok, False, code)
-

diff --git a/src/soc/fu/div/test/test_all_pipe_caller.py b/src/soc/fu/div/test/test_all_pipe_caller.py
index 319f1ef8241aa27def7d55dd08ddb3ec3ee80159..bf62cd5f76230031d05641b0b5fd4d8ab312c787 100644 (file)
--- a/src/soc/fu/div/test/test_all_pipe_caller.py
+++ b/src/soc/fu/div/test/test_all_pipe_caller.py
@@ -53,7 +53,5 @@ if __name__ == "__main__":
     suite.addTest(DivRunner(DivTestLong().test_data, DivPipeKind.FSMDivCore))
     suite.addTest(DivRunner(DivTestLong().test_data, DivPipeKind.SimOnly))
 
-
     runner = unittest.TextTestRunner()
     runner.run(suite)
-

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 6b02d0d92127d25eb4dc05ffeaacd5f5d68957e9..88e721551303c54ea06ef13122652592f1376679 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -85,7 +85,7 @@ class DivTestCases(TestAccumulatorBase):
         with Program(lst, bigendian) as prog:
             self.add_case(prog, initial_regs)
 
-    def case_8_fsm_regression(self): # FSM result is "36" not 6
+    def case_8_fsm_regression(self):  # FSM result is "36" not 6
         lst = ["divwu. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 18
@@ -93,7 +93,7 @@ class DivTestCases(TestAccumulatorBase):
         with Program(lst, bigendian) as prog:
             self.add_case(prog, initial_regs)
 
-    def case_9_regression(self): # CR0 fails: expected 0b10, actual 0b11
+    def case_9_regression(self):  # CR0 fails: expected 0b10, actual 0b11
         lst = ["divw. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 1
@@ -173,4 +173,3 @@ if __name__ == "__main__":
 
     runner = unittest.TextTestRunner()
     runner.run(suite)
-