add link to XICS bugreport

diff --git a/src/soc/interrupts/xics.py b/src/soc/interrupts/xics.py
index ede33a1b03913307f33ce8080652d315c0403ce9..d1bc0296a58ac8ee92c57b6a40d850d77f76c851 100644 (file)
--- a/src/soc/interrupts/xics.py
+++ b/src/soc/interrupts/xics.py
@@ -16,6 +16,9 @@
 # highest priority interrupt currently presented (which is allowed
 # via XICS)
 #
+# Bugreports:
+#
+# * https://bugs.libre-soc.org/show_bug.cgi?id=407
 """
 from nmigen import Elaboratable, Module, Signal, Cat, Const, Record, Array, Mux
 from nmutil.iocontrol import RecordObject