fix regfile port names for "fast" port access (regreduce=False)

diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py
index cccb21330a872721aa1ffa7a4eaa2a3b318d5aeb..2e8643da33072c26363a248b85c0819338fa60ff 100644 (file)
--- a/src/soc/experiment/pi2ls.py
+++ b/src/soc/experiment/pi2ls.py
@@ -47,6 +47,7 @@ class Pi2LSUI(PortInterfaceBase):
         self.valid_l = SRLatch(False, name="valid")
 
     def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz):
+        print("pi2lsui TODO, implement is_dcbz")
         m.d.comb += self.valid_l.s.eq(1)
         m.d.comb += self.lsui.x_mask_i.eq(mask)
         m.d.comb += self.lsui.x_addr_i.eq(addr)

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index dd7e3a76a4c23f1f187d270e7e8d98e681d29d20..93d94226c3c7637769416ae619c1380fc17a1b80 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -149,6 +149,9 @@ class FastRegs(RegFileMem, FastRegsEnum): #RegFileArray):
                         }
         if not self.regreduce_en:
             r_port_spec['fast2'] = "src2"
+            r_port_spec['fast3'] = "src3"
+            w_port_spec['fast2'] = "dest2"
+            w_port_spec['fast3'] = "dest3"
 
         return w_port_spec, r_port_spec
 

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 78e839768afe614df842a8b926b5ec63b074ccc8..d01490648a0ff8d603168551627a300f24a3026b 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -100,8 +100,8 @@ class NonProductionCore(ControlBase):
         mmu = self.fus.get_fu('mmu0')
         print ("core pspec", pspec.ldst_ifacetype)
         print ("core mmu", mmu)
-        print ("core lsmem.lsi", l0.cmpi.lsmem.lsi)
         if mmu is not None:
+            print ("core lsmem.lsi", l0.cmpi.lsmem.lsi)
             mmu.alu.set_ldst_interface(l0.cmpi.lsmem.lsi)
 
         # register files (yes plural)