sync on reset in compalu

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 864dc048ec832edeef143cf0187671c683aaafad..dbd47c8c33d6376d0e9932bdaa6037d278f400cd 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -237,8 +237,8 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.d.sync += rok_l.r.eq(self.alu.n.valid_o & self.busy_o)  # ALU done
 
         # wr-done, back-to-start latch
-        m.d.comb += rst_l.s.eq(all_rd)     # set when read-phase is fully done
-        m.d.comb += rst_l.r.eq(rst_r)        # *off* on issue
+        m.d.sync += rst_l.s.eq(all_rd)     # set when read-phase is fully done
+        m.d.sync += rst_l.r.eq(rst_r)        # *off* on issue
 
         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
         m.d.sync += opc_l.s.eq(self.issue_i)       # set on issue