move writing rtlil into do_sim

diff --git a/src/nmutil/lut.py b/src/nmutil/lut.py
index 8e8a18a7c4c5c99b815dcbc0bdcc05e1947cbde3..4eb790d4e11c843aec4e4678735b15fd9f777e05 100644 (file)
--- a/src/nmutil/lut.py
+++ b/src/nmutil/lut.py
@@ -144,9 +144,5 @@ class TreeBitwiseLut(Elaboratable):
         return [self.input, self.chunk_sizes, self.output]
 
 
-# useful to see what is going on: use yosys "read_ilang test_lut.il; show top"
-if __name__ == '__main__':
-    dut = BitwiseLut(3, 8)
-    vl = rtlil.convert(dut, ports=dut.ports())
-    with open("test_lut.il", "w") as f:
-        f.write(vl)
+# useful to see what is going on:
+# yosys <<<"read_ilang sim_test_out/__main__.TestBitwiseLut.test_tree/0.il; proc;;; show top"

diff --git a/src/nmutil/sim_util.py b/src/nmutil/sim_util.py
index 9484eb4ab7bf619226689576ffac56a6be389c2d..018564c18b44930f0d1004429da3600a9d6450ea 100644 (file)
--- a/src/nmutil/sim_util.py
+++ b/src/nmutil/sim_util.py
@@ -6,8 +6,11 @@
 
 from contextlib import contextmanager
 from hashlib import sha256
+
+from nmigen.hdl.ir import Fragment
 from nmutil.get_test_path import get_test_path
 from nmigen.sim import Simulator
+from nmigen.back.rtlil import convert
 
 
 def hash_256(v):
@@ -18,12 +21,18 @@ def hash_256(v):
 
 
 @contextmanager
-def do_sim(test_case, dut, traces=()):
+def do_sim(test_case, dut, traces=(), ports=None):
+    # only elaborate once, cuz users' stupid code breaks if elaborating twice
+    dut = Fragment.get(dut, platform=None)
     sim = Simulator(dut)
     path = get_test_path(test_case, "sim_test_out")
     path.parent.mkdir(parents=True, exist_ok=True)
     vcd_path = path.with_suffix(".vcd")
     gtkw_path = path.with_suffix(".gtkw")
+    il_path = path.with_suffix(".il")
+    if ports is None:
+        ports = traces
+    il_path.write_text(convert(dut, ports=ports), encoding="utf-8")
     with sim.write_vcd(vcd_path.open("wt", encoding="utf-8"),
                        gtkw_path.open("wt", encoding="utf-8"),
                        traces=traces):