projects / ieee754fpu.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 748826f)
add comment
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 7 Jul 2019 13:02:17 +0000 (14:02 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 7 Jul 2019 13:02:17 +0000 (14:02 +0100)
src/ieee754/div_rem_sqrt_rsqrt/core.py patch | blob | history

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index 5f4eefc35e12a4609eec395e2bd7a4a587b17f3f..c17a2be64031ad73126fb08f5be7a34c5ebb0a43 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -360,6 +360,7 @@ class DivPipeCoreCalculateStage(Elaboratable):
             next_flag = pass_flags[i + 1] if i + 1 < radix else 0
             flag = Signal(reset_less=True)
             test = Signal(reset_less=True)
+            # XXX TODO: check the width on this
             m.d.comb += test.eq((pass_flags[i] & ~next_flag))
             m.d.comb += flag.eq(Mux(test,
                                     trial_compare_rhs_values[i],