add SVSTATE to CoreState

diff --git a/src/soc/config/state.py b/src/soc/config/state.py
index 3fc919671fe984800d6da46c60170d19dfa8d266..ebc5bb861053713e430d077a44a5f6efb5b45cce 100644 (file)
--- a/src/soc/config/state.py
+++ b/src/soc/config/state.py
@@ -1,5 +1,6 @@
 from nmutil.iocontrol import RecordObject
 from nmigen import Signal
+from soc.sv.svstate import SVSTATERec
 
 
 class CoreState(RecordObject):
@@ -9,3 +10,4 @@ class CoreState(RecordObject):
         self.msr = Signal(64)     # Machine Status Register (MSR)
         self.eint = Signal()      # External Interrupt
         self.dec = Signal(64)     # DEC SPR (again, for interrupt generation)
+        self.svstate = SVSTATERec(name) # Simple-V SVSTATE

diff --git a/src/soc/sv/svstate.py b/src/soc/sv/svstate.py
index 7bca63e3cb85c3c5f6051e4f5a6b9981966c8699..c97efa4833da1b856a0b33b0c4c7beed41210b99 100644 (file)
--- a/src/soc/sv/svstate.py
+++ b/src/soc/sv/svstate.py
@@ -15,17 +15,17 @@ https://libre-soc.org/openpower/sv/sprs/
 | 30:31 | svstep   | for svstep = 0..SUBVL-1  |
 """
 
-from nmigen import Record
+from nmutil.iocontrol import RecordObject
+from nmigen import Signal
 
-class SVSTATERec(Record):
+
+class SVSTATERec(RecordObject):
     def __init__(self, name=None):
-        Record.__init__(self, layout=[("maxvl"     : 7),
-                                      ("vl"        : 7),
-                                      ("srcstep"   : 7),
-                                      ("dststep"   : 7),
-                                      ("subvl"     : 2),
-                                      ("svstep"    : 2)], name=name)
-    def ports(self):
-        return [self.maxvl, self.vl, self.srcstep, self.dststep, self.subvl,
-                self.svstep]
+        super().__init__(name=name)
+        self.maxvl = Signal(7)
+        self.vl = Signal(7)
+        self.srcstep = Signal(7)
+        self.dststep = Signal(7)
+        self.subvl = Signal(2)
+        self.svstep = Signal(2)