Modify pi2ls so it passes the portinterface unit tests

diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py
index 3fe43b73d4896e5b6f27585743c7dee32abb9d4d..548ac5e5a8333744ce003e4b6b9af63a5f1b04ee 100644 (file)
--- a/src/soc/experiment/pi2ls.py
+++ b/src/soc/experiment/pi2ls.py
@@ -51,6 +51,8 @@ class Pi2LSUI(Elaboratable):
         pi, lsui, addrbits = self.pi, self.lsui, self.addrbits
         m.submodules.lenexp = lenexp = LenExpand(self.addrbits, 8)
 
+        ld_in_progress = Signal(reset=0)
+
         m.d.comb += lsui.x_ld_i.eq(pi.is_ld_i)
         m.d.comb += lsui.x_st_i.eq(pi.is_st_i)
         m.d.comb += pi.busy_o.eq(lsui.x_busy_o)
@@ -68,10 +70,20 @@ class Pi2LSUI(Elaboratable):
 
         with m.If(pi.is_ld_i):
             m.d.comb += pi.ld.data.eq(lsui.m_ld_data_o)
-            m.d.comb += pi.ld.ok.eq(1) # TODO whether this should be one cycle
+            # remember we're in the process of loading
+            m.d.sync += ld_in_progress.eq(1)
+
+        # If a load happened on the previous cycle and the memory is
+        # not busy, that means it returned the data from the load. In
+        # that case ld.ok should be set andwe can clear the
+        # ld_in_progress flag
+        with m.If(ld_in_progress & ~lsui.x_busy_o):
+            m.d.comb += pi.ld.ok.eq(1)
+            m.d.sync += ld_in_progress.eq(0)
+        with m.Else():
+            m.d.comb += pi.ld.ok.eq(0)
 
         with m.If(pi.is_st_i & pi.st.ok):
             m.d.comb += lsui.x_st_data_i.eq(pi.st.data)
 
         return m
-

diff --git a/src/soc/experiment/test/test_pi2ls.py b/src/soc/experiment/test/test_pi2ls.py
index eda2f51514cbbc21610e847e36293d7cbcb4bccc..a1ea76334841911d1815642f214d61ec92aecd28 100644 (file)
--- a/src/soc/experiment/test/test_pi2ls.py
+++ b/src/soc/experiment/test/test_pi2ls.py
@@ -84,7 +84,7 @@ def l0_cache_ld(dut, addr, datalen, expected):
     yield port1.pi.addr.ok.eq(1)  # set ok
     yield Settle()
     yield from wait_addr(port1)             # wait until addr ok
-
+    yield
     yield from wait_ldok(port1)             # wait until ld ok
     data = yield port1.pi.ld.data