add missing args to ISA

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 07ef8150530cc9369de74693004ad75907df4225..7708f22eda07e7fb0bd427f9e12093a857a3e1f6 100644 (file)
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -199,7 +199,8 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                simulator = ISA(pdecode2, test.regs, test.sprs, 0)
+                simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
+                                test.mem, test.msr)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))