add arbitrary random experimentation values for TLB and PTW unit tests

diff --git a/TLB/src/ariane/test_ptw.py b/TLB/src/ariane/test_ptw.py
new file mode 100644 (file)
index 0000000..7132eb4
--- /dev/null
+++ b/TLB/src/ariane/test_ptw.py
@@ -0,0 +1,27 @@
+from nmigen.compat.sim import run_simulation
+
+from ptw import PTW
+
+
+def testbench(dut):
+    yield dut.req_port_i.data_gnt.eq(1)
+    yield dut.req_port_i.data_rvalid.eq(1)
+    yield dut.req_port_i.data_rdata.eq(0x0001)
+
+    yield dut.enable_translation_i.eq(1)
+    yield dut.asid_i.eq(1)
+
+    yield dut.itlb_access_i.eq(1)
+    yield dut.itlb_hit_i.eq(0)
+    yield dut.itlb_vaddr_i.eq(0x0001)
+
+    yield
+    yield
+    yield
+    yield
+
+    
+
+if __name__ == "__main__":
+    dut = PTW()
+    run_simulation(dut, testbench(dut), vcd_name="test_ptw.vcd")

diff --git a/TLB/src/ariane/test_tlb.py b/TLB/src/ariane/test_tlb.py
new file mode 100644 (file)
index 0000000..78cf154
--- /dev/null
+++ b/TLB/src/ariane/test_tlb.py
@@ -0,0 +1,36 @@
+from nmigen.compat.sim import run_simulation
+
+from tlb import TLB
+
+
+def testbench(dut):
+    yield dut.lu_access_i.eq(1)
+    yield dut.lu_asid_i.eq(1)
+    yield dut.lu_vaddr_i.eq(0x80000)
+    yield dut.update_i.valid.eq(1)
+    yield dut.update_i.is_1G.eq(0)
+    yield dut.update_i.is_2M.eq(0)
+    yield dut.update_i.vpn.eq(0x80000)
+    yield dut.update_i.asid.eq(1)
+    yield dut.update_i.content.ppn.eq(0)
+    yield dut.update_i.content.rsw.eq(0)
+    yield dut.update_i.content.r.eq(1)
+
+    yield
+
+    yield dut.lu_vaddr_i.eq(0x80000)
+    yield dut.update_i.vpn.eq(0x80000)
+    yield
+
+    yield dut.lu_vaddr_i.eq(0x280000)
+    yield dut.update_i.vpn.eq(0x280000)
+    yield
+
+    yield dut.lu_vaddr_i.eq(0x040000)
+    yield dut.update_i.vpn.eq(0x040000)
+    yield
+    
+
+if __name__ == "__main__":
+    dut = TLB()
+    run_simulation(dut, testbench(dut), vcd_name="test_tlb.vcd")

diff --git a/TLB/src/ariane/tlb.py b/TLB/src/ariane/tlb.py
index 740cf42c2ed6eb06e225b565f46832241d9993bb..3a51c6650351cf130a6a8ecf985187e30c140a4b 100644 (file)
--- a/TLB/src/ariane/tlb.py
+++ b/TLB/src/ariane/tlb.py
@@ -22,7 +22,7 @@ from nmigen.lib.coding import Encoder
 
 from ptw import TLBUpdate, PTE, ASID_WIDTH
 
-TLB_ENTRIES = 8
+TLB_ENTRIES = 4
 
 
 class TLBEntry: