CHIPSET(0x0156, IVYBRIDGE_M_GT1, ivb_gt1)
CHIPSET(0x0166, IVYBRIDGE_M_GT2, ivb_gt2)
CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1)
+CHIPSET(0x0402, HASWELL_GT1, hsw_gt1)
+CHIPSET(0x0412, HASWELL_GT2, hsw_gt2)
+CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1)
+CHIPSET(0x0416, HASWELL_M_GT2, hsw_gt2)
+CHIPSET(0x0A16, HASWELL_M_ULT_GT2, hsw_gt2)
#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */
+#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
+#define PCI_CHIP_HASWELL_GT2 0x0412
+#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
+#define PCI_CHIP_HASWELL_M_GT2 0x0416
+#define PCI_CHIP_HASWELL_M_ULT_GT2 0x0A16 /* Mobile ULT */
+
#define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
devid == PCI_CHIP_I915_GM || \
devid == PCI_CHIP_I945_GM || \
#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
IS_HASWELL(devid))
-#define IS_HSW_GT1(devid) 0
-#define IS_HSW_GT2(devid) 0
+#define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
+ devid == PCI_CHIP_HASWELL_M_GT1)
+#define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \
+ devid == PCI_CHIP_HASWELL_M_GT2 || \
+ devid == PCI_CHIP_HASWELL_M_ULT_GT2)
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
IS_HSW_GT2(devid))
case PCI_CHIP_IVYBRIDGE_S_GT1:
chipset = "Intel(R) Ivybridge Server";
break;
+ case PCI_CHIP_HASWELL_GT1:
+ case PCI_CHIP_HASWELL_GT2:
+ chipset = "Intel(R) Haswell Desktop";
+ break;
+ case PCI_CHIP_HASWELL_M_GT1:
+ case PCI_CHIP_HASWELL_M_GT2:
+ case PCI_CHIP_HASWELL_M_ULT_GT2:
+ chipset = "Intel(R) Haswell Mobile";
+ break;
default:
chipset = "Unknown Intel Chipset";
break;