intel: Add some PCI IDs for Haswell.
authorKenneth Graunke <kenneth@whitecape.org>
Mon, 19 Mar 2012 20:42:16 +0000 (13:42 -0700)
committerKenneth Graunke <kenneth@whitecape.org>
Fri, 30 Mar 2012 21:39:31 +0000 (14:39 -0700)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
include/pci_ids/i965_pci_ids.h
src/mesa/drivers/dri/intel/intel_chipset.h
src/mesa/drivers/dri/intel/intel_context.c

index d37a2eed4b09a15c417516e2fe3c47f965544aa0..a29150955b42510a3f6b600ee036b49447b83c34 100644 (file)
@@ -25,3 +25,8 @@ CHIPSET(0x0162, IVYBRIDGE_GT2, ivb_gt2)
 CHIPSET(0x0156, IVYBRIDGE_M_GT1, ivb_gt1)
 CHIPSET(0x0166, IVYBRIDGE_M_GT2, ivb_gt2)
 CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1)
+CHIPSET(0x0402, HASWELL_GT1, hsw_gt1)
+CHIPSET(0x0412, HASWELL_GT2, hsw_gt2)
+CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1)
+CHIPSET(0x0416, HASWELL_M_GT2, hsw_gt2)
+CHIPSET(0x0A16, HASWELL_M_ULT_GT2, hsw_gt2)
index eefb430f0b3b3970f11853cf5ba2f48668959c3d..424c70ce2f1a35d4424decb41e1183d2735a2c2f 100644 (file)
 #define PCI_CHIP_IVYBRIDGE_M_GT2        0x0166
 #define PCI_CHIP_IVYBRIDGE_S_GT1        0x015a  /* Server */
 
+#define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
+#define PCI_CHIP_HASWELL_GT2            0x0412
+#define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
+#define PCI_CHIP_HASWELL_M_GT2          0x0416
+#define PCI_CHIP_HASWELL_M_ULT_GT2      0x0A16 /* Mobile ULT */
+
 #define IS_MOBILE(devid)       (devid == PCI_CHIP_I855_GM || \
                                 devid == PCI_CHIP_I915_GM || \
                                 devid == PCI_CHIP_I945_GM || \
 #define IS_GEN7(devid)         (IS_IVYBRIDGE(devid) || \
                                 IS_HASWELL(devid))
 
-#define IS_HSW_GT1(devid)      0
-#define IS_HSW_GT2(devid)      0
+#define IS_HSW_GT1(devid)      (devid == PCI_CHIP_HASWELL_GT1 || \
+                                devid == PCI_CHIP_HASWELL_M_GT1)
+#define IS_HSW_GT2(devid)      (devid == PCI_CHIP_HASWELL_GT2 || \
+                                devid == PCI_CHIP_HASWELL_M_GT2 || \
+                                devid == PCI_CHIP_HASWELL_M_ULT_GT2)
 
 #define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
                                 IS_HSW_GT2(devid))
index 1aa2e9a40ece64853871cba77a5099458adcb4ff..ff2b7feec8dfa6a395caf5cb34866ce036ba1c38 100644 (file)
@@ -185,6 +185,15 @@ intelGetString(struct gl_context * ctx, GLenum name)
       case PCI_CHIP_IVYBRIDGE_S_GT1:
         chipset = "Intel(R) Ivybridge Server";
         break;
+      case PCI_CHIP_HASWELL_GT1:
+      case PCI_CHIP_HASWELL_GT2:
+        chipset = "Intel(R) Haswell Desktop";
+        break;
+      case PCI_CHIP_HASWELL_M_GT1:
+      case PCI_CHIP_HASWELL_M_GT2:
+      case PCI_CHIP_HASWELL_M_ULT_GT2:
+        chipset = "Intel(R) Haswell Mobile";
+        break;
       default:
          chipset = "Unknown Intel Chipset";
          break;