add msr to MMU Op Subset record

diff --git a/src/soc/fu/mmu/mmu_input_record.py b/src/soc/fu/mmu/mmu_input_record.py
index 079c2e9f4991703d9d4801511e87ff1817409a42..54256ca5b67942a5e60d6d4ffb3eaeea36b073f0 100644 (file)
--- a/src/soc/fu/mmu/mmu_input_record.py
+++ b/src/soc/fu/mmu/mmu_input_record.py
@@ -14,6 +14,7 @@ class CompMMUOpSubset(CompOpSubsetBase):
                   ('fn_unit', Function),
                   ('insn', 32),
                   ('nia', 64), # for instruction fault (MMU PTE lookup)
+                  ('msr', 64), # ditto, to set priv_mode etc.
                   ('zero_a', 1),
                   )
         super().__init__(layout, name=name)